1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #define SUPPORT_SYSRQ
16 #endif
17 
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/tty.h>
27 #include <linux/ratelimit.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/serial_8250.h>
31 #include <linux/nmi.h>
32 #include <linux/mutex.h>
33 #include <linux/slab.h>
34 #include <linux/uaccess.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/ktime.h>
37 
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 
41 #include "8250.h"
42 
43 /*
44  * These are definitions for the Exar XR17V35X and XR17(C|D)15X
45  */
46 #define UART_EXAR_INT0		0x80
47 #define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
48 #define UART_EXAR_DVID		0x8d	/* Device identification */
49 
50 /* Nuvoton NPCM timeout register */
51 #define UART_NPCM_TOR          7
52 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
53 
54 /*
55  * Debugging.
56  */
57 #if 0
58 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
59 #else
60 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
61 #endif
62 
63 #define BOTH_EMPTY	(UART_LSR_TEMT | UART_LSR_THRE)
64 
65 /*
66  * Here we define the default xmit fifo size used for each type of UART.
67  */
68 static const struct serial8250_config uart_config[] = {
69 	[PORT_UNKNOWN] = {
70 		.name		= "unknown",
71 		.fifo_size	= 1,
72 		.tx_loadsz	= 1,
73 	},
74 	[PORT_8250] = {
75 		.name		= "8250",
76 		.fifo_size	= 1,
77 		.tx_loadsz	= 1,
78 	},
79 	[PORT_16450] = {
80 		.name		= "16450",
81 		.fifo_size	= 1,
82 		.tx_loadsz	= 1,
83 	},
84 	[PORT_16550] = {
85 		.name		= "16550",
86 		.fifo_size	= 1,
87 		.tx_loadsz	= 1,
88 	},
89 	[PORT_16550A] = {
90 		.name		= "16550A",
91 		.fifo_size	= 16,
92 		.tx_loadsz	= 16,
93 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
94 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
95 		.rxtrig_bytes	= {1, 4, 8, 14},
96 		.flags		= UART_CAP_FIFO,
97 	},
98 	[PORT_CIRRUS] = {
99 		.name		= "Cirrus",
100 		.fifo_size	= 1,
101 		.tx_loadsz	= 1,
102 	},
103 	[PORT_16650] = {
104 		.name		= "ST16650",
105 		.fifo_size	= 1,
106 		.tx_loadsz	= 1,
107 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
108 	},
109 	[PORT_16650V2] = {
110 		.name		= "ST16650V2",
111 		.fifo_size	= 32,
112 		.tx_loadsz	= 16,
113 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
114 				  UART_FCR_T_TRIG_00,
115 		.rxtrig_bytes	= {8, 16, 24, 28},
116 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
117 	},
118 	[PORT_16750] = {
119 		.name		= "TI16750",
120 		.fifo_size	= 64,
121 		.tx_loadsz	= 64,
122 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
123 				  UART_FCR7_64BYTE,
124 		.rxtrig_bytes	= {1, 16, 32, 56},
125 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
126 	},
127 	[PORT_STARTECH] = {
128 		.name		= "Startech",
129 		.fifo_size	= 1,
130 		.tx_loadsz	= 1,
131 	},
132 	[PORT_16C950] = {
133 		.name		= "16C950/954",
134 		.fifo_size	= 128,
135 		.tx_loadsz	= 128,
136 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
137 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
138 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
139 	},
140 	[PORT_16654] = {
141 		.name		= "ST16654",
142 		.fifo_size	= 64,
143 		.tx_loadsz	= 32,
144 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
145 				  UART_FCR_T_TRIG_10,
146 		.rxtrig_bytes	= {8, 16, 56, 60},
147 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
148 	},
149 	[PORT_16850] = {
150 		.name		= "XR16850",
151 		.fifo_size	= 128,
152 		.tx_loadsz	= 128,
153 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
154 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
155 	},
156 	[PORT_RSA] = {
157 		.name		= "RSA",
158 		.fifo_size	= 2048,
159 		.tx_loadsz	= 2048,
160 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
161 		.flags		= UART_CAP_FIFO,
162 	},
163 	[PORT_NS16550A] = {
164 		.name		= "NS16550A",
165 		.fifo_size	= 16,
166 		.tx_loadsz	= 16,
167 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
168 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
169 	},
170 	[PORT_XSCALE] = {
171 		.name		= "XScale",
172 		.fifo_size	= 32,
173 		.tx_loadsz	= 32,
174 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
175 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
176 	},
177 	[PORT_OCTEON] = {
178 		.name		= "OCTEON",
179 		.fifo_size	= 64,
180 		.tx_loadsz	= 64,
181 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
182 		.flags		= UART_CAP_FIFO,
183 	},
184 	[PORT_AR7] = {
185 		.name		= "AR7",
186 		.fifo_size	= 16,
187 		.tx_loadsz	= 16,
188 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
189 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
190 	},
191 	[PORT_U6_16550A] = {
192 		.name		= "U6_16550A",
193 		.fifo_size	= 64,
194 		.tx_loadsz	= 64,
195 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
196 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
197 	},
198 	[PORT_TEGRA] = {
199 		.name		= "Tegra",
200 		.fifo_size	= 32,
201 		.tx_loadsz	= 8,
202 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
203 				  UART_FCR_T_TRIG_01,
204 		.rxtrig_bytes	= {1, 4, 8, 14},
205 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
206 	},
207 	[PORT_XR17D15X] = {
208 		.name		= "XR17D15X",
209 		.fifo_size	= 64,
210 		.tx_loadsz	= 64,
211 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
212 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
213 				  UART_CAP_SLEEP,
214 	},
215 	[PORT_XR17V35X] = {
216 		.name		= "XR17V35X",
217 		.fifo_size	= 256,
218 		.tx_loadsz	= 256,
219 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
220 				  UART_FCR_T_TRIG_11,
221 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
222 				  UART_CAP_SLEEP,
223 	},
224 	[PORT_LPC3220] = {
225 		.name		= "LPC3220",
226 		.fifo_size	= 64,
227 		.tx_loadsz	= 32,
228 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
229 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
230 		.flags		= UART_CAP_FIFO,
231 	},
232 	[PORT_BRCM_TRUMANAGE] = {
233 		.name		= "TruManage",
234 		.fifo_size	= 1,
235 		.tx_loadsz	= 1024,
236 		.flags		= UART_CAP_HFIFO,
237 	},
238 	[PORT_8250_CIR] = {
239 		.name		= "CIR port"
240 	},
241 	[PORT_ALTR_16550_F32] = {
242 		.name		= "Altera 16550 FIFO32",
243 		.fifo_size	= 32,
244 		.tx_loadsz	= 32,
245 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 		.rxtrig_bytes	= {1, 8, 16, 30},
247 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
248 	},
249 	[PORT_ALTR_16550_F64] = {
250 		.name		= "Altera 16550 FIFO64",
251 		.fifo_size	= 64,
252 		.tx_loadsz	= 64,
253 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 		.rxtrig_bytes	= {1, 16, 32, 62},
255 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
256 	},
257 	[PORT_ALTR_16550_F128] = {
258 		.name		= "Altera 16550 FIFO128",
259 		.fifo_size	= 128,
260 		.tx_loadsz	= 128,
261 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
262 		.rxtrig_bytes	= {1, 32, 64, 126},
263 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
264 	},
265 	/*
266 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
267 	 * workaround of errata A-008006 which states that tx_loadsz should
268 	 * be configured less than Maximum supported fifo bytes.
269 	 */
270 	[PORT_16550A_FSL64] = {
271 		.name		= "16550A_FSL64",
272 		.fifo_size	= 64,
273 		.tx_loadsz	= 63,
274 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
275 				  UART_FCR7_64BYTE,
276 		.flags		= UART_CAP_FIFO,
277 	},
278 	[PORT_RT2880] = {
279 		.name		= "Palmchip BK-3103",
280 		.fifo_size	= 16,
281 		.tx_loadsz	= 16,
282 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 		.rxtrig_bytes	= {1, 4, 8, 14},
284 		.flags		= UART_CAP_FIFO,
285 	},
286 	[PORT_DA830] = {
287 		.name		= "TI DA8xx/66AK2x",
288 		.fifo_size	= 16,
289 		.tx_loadsz	= 16,
290 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
291 				  UART_FCR_R_TRIG_10,
292 		.rxtrig_bytes	= {1, 4, 8, 14},
293 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
294 	},
295 	[PORT_MTK_BTIF] = {
296 		.name		= "MediaTek BTIF",
297 		.fifo_size	= 16,
298 		.tx_loadsz	= 16,
299 		.fcr		= UART_FCR_ENABLE_FIFO |
300 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
301 		.flags		= UART_CAP_FIFO,
302 	},
303 	[PORT_NPCM] = {
304 		.name		= "Nuvoton 16550",
305 		.fifo_size	= 16,
306 		.tx_loadsz	= 16,
307 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
308 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
309 		.rxtrig_bytes	= {1, 4, 8, 14},
310 		.flags		= UART_CAP_FIFO,
311 	},
312 };
313 
314 /* Uart divisor latch read */
315 static int default_serial_dl_read(struct uart_8250_port *up)
316 {
317 	return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
318 }
319 
320 /* Uart divisor latch write */
321 static void default_serial_dl_write(struct uart_8250_port *up, int value)
322 {
323 	serial_out(up, UART_DLL, value & 0xff);
324 	serial_out(up, UART_DLM, value >> 8 & 0xff);
325 }
326 
327 #ifdef CONFIG_SERIAL_8250_RT288X
328 
329 /* Au1x00/RT288x UART hardware has a weird register layout */
330 static const s8 au_io_in_map[8] = {
331 	 0,	/* UART_RX  */
332 	 2,	/* UART_IER */
333 	 3,	/* UART_IIR */
334 	 5,	/* UART_LCR */
335 	 6,	/* UART_MCR */
336 	 7,	/* UART_LSR */
337 	 8,	/* UART_MSR */
338 	-1,	/* UART_SCR (unmapped) */
339 };
340 
341 static const s8 au_io_out_map[8] = {
342 	 1,	/* UART_TX  */
343 	 2,	/* UART_IER */
344 	 4,	/* UART_FCR */
345 	 5,	/* UART_LCR */
346 	 6,	/* UART_MCR */
347 	-1,	/* UART_LSR (unmapped) */
348 	-1,	/* UART_MSR (unmapped) */
349 	-1,	/* UART_SCR (unmapped) */
350 };
351 
352 unsigned int au_serial_in(struct uart_port *p, int offset)
353 {
354 	if (offset >= ARRAY_SIZE(au_io_in_map))
355 		return UINT_MAX;
356 	offset = au_io_in_map[offset];
357 	if (offset < 0)
358 		return UINT_MAX;
359 	return __raw_readl(p->membase + (offset << p->regshift));
360 }
361 
362 void au_serial_out(struct uart_port *p, int offset, int value)
363 {
364 	if (offset >= ARRAY_SIZE(au_io_out_map))
365 		return;
366 	offset = au_io_out_map[offset];
367 	if (offset < 0)
368 		return;
369 	__raw_writel(value, p->membase + (offset << p->regshift));
370 }
371 
372 /* Au1x00 haven't got a standard divisor latch */
373 static int au_serial_dl_read(struct uart_8250_port *up)
374 {
375 	return __raw_readl(up->port.membase + 0x28);
376 }
377 
378 static void au_serial_dl_write(struct uart_8250_port *up, int value)
379 {
380 	__raw_writel(value, up->port.membase + 0x28);
381 }
382 
383 #endif
384 
385 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
386 {
387 	offset = offset << p->regshift;
388 	outb(p->hub6 - 1 + offset, p->iobase);
389 	return inb(p->iobase + 1);
390 }
391 
392 static void hub6_serial_out(struct uart_port *p, int offset, int value)
393 {
394 	offset = offset << p->regshift;
395 	outb(p->hub6 - 1 + offset, p->iobase);
396 	outb(value, p->iobase + 1);
397 }
398 
399 static unsigned int mem_serial_in(struct uart_port *p, int offset)
400 {
401 	offset = offset << p->regshift;
402 	return readb(p->membase + offset);
403 }
404 
405 static void mem_serial_out(struct uart_port *p, int offset, int value)
406 {
407 	offset = offset << p->regshift;
408 	writeb(value, p->membase + offset);
409 }
410 
411 static void mem16_serial_out(struct uart_port *p, int offset, int value)
412 {
413 	offset = offset << p->regshift;
414 	writew(value, p->membase + offset);
415 }
416 
417 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
418 {
419 	offset = offset << p->regshift;
420 	return readw(p->membase + offset);
421 }
422 
423 static void mem32_serial_out(struct uart_port *p, int offset, int value)
424 {
425 	offset = offset << p->regshift;
426 	writel(value, p->membase + offset);
427 }
428 
429 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
430 {
431 	offset = offset << p->regshift;
432 	return readl(p->membase + offset);
433 }
434 
435 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
436 {
437 	offset = offset << p->regshift;
438 	iowrite32be(value, p->membase + offset);
439 }
440 
441 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
442 {
443 	offset = offset << p->regshift;
444 	return ioread32be(p->membase + offset);
445 }
446 
447 static unsigned int io_serial_in(struct uart_port *p, int offset)
448 {
449 	offset = offset << p->regshift;
450 	return inb(p->iobase + offset);
451 }
452 
453 static void io_serial_out(struct uart_port *p, int offset, int value)
454 {
455 	offset = offset << p->regshift;
456 	outb(value, p->iobase + offset);
457 }
458 
459 static int serial8250_default_handle_irq(struct uart_port *port);
460 
461 static void set_io_from_upio(struct uart_port *p)
462 {
463 	struct uart_8250_port *up = up_to_u8250p(p);
464 
465 	up->dl_read = default_serial_dl_read;
466 	up->dl_write = default_serial_dl_write;
467 
468 	switch (p->iotype) {
469 	case UPIO_HUB6:
470 		p->serial_in = hub6_serial_in;
471 		p->serial_out = hub6_serial_out;
472 		break;
473 
474 	case UPIO_MEM:
475 		p->serial_in = mem_serial_in;
476 		p->serial_out = mem_serial_out;
477 		break;
478 
479 	case UPIO_MEM16:
480 		p->serial_in = mem16_serial_in;
481 		p->serial_out = mem16_serial_out;
482 		break;
483 
484 	case UPIO_MEM32:
485 		p->serial_in = mem32_serial_in;
486 		p->serial_out = mem32_serial_out;
487 		break;
488 
489 	case UPIO_MEM32BE:
490 		p->serial_in = mem32be_serial_in;
491 		p->serial_out = mem32be_serial_out;
492 		break;
493 
494 #ifdef CONFIG_SERIAL_8250_RT288X
495 	case UPIO_AU:
496 		p->serial_in = au_serial_in;
497 		p->serial_out = au_serial_out;
498 		up->dl_read = au_serial_dl_read;
499 		up->dl_write = au_serial_dl_write;
500 		break;
501 #endif
502 
503 	default:
504 		p->serial_in = io_serial_in;
505 		p->serial_out = io_serial_out;
506 		break;
507 	}
508 	/* Remember loaded iotype */
509 	up->cur_iotype = p->iotype;
510 	p->handle_irq = serial8250_default_handle_irq;
511 }
512 
513 static void
514 serial_port_out_sync(struct uart_port *p, int offset, int value)
515 {
516 	switch (p->iotype) {
517 	case UPIO_MEM:
518 	case UPIO_MEM16:
519 	case UPIO_MEM32:
520 	case UPIO_MEM32BE:
521 	case UPIO_AU:
522 		p->serial_out(p, offset, value);
523 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
524 		break;
525 	default:
526 		p->serial_out(p, offset, value);
527 	}
528 }
529 
530 /*
531  * For the 16C950
532  */
533 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
534 {
535 	serial_out(up, UART_SCR, offset);
536 	serial_out(up, UART_ICR, value);
537 }
538 
539 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
540 {
541 	unsigned int value;
542 
543 	serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
544 	serial_out(up, UART_SCR, offset);
545 	value = serial_in(up, UART_ICR);
546 	serial_icr_write(up, UART_ACR, up->acr);
547 
548 	return value;
549 }
550 
551 /*
552  * FIFO support.
553  */
554 static void serial8250_clear_fifos(struct uart_8250_port *p)
555 {
556 	if (p->capabilities & UART_CAP_FIFO) {
557 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
558 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
559 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
560 		serial_out(p, UART_FCR, 0);
561 	}
562 }
563 
564 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
565 {
566 	unsigned char mcr = serial8250_in_MCR(p);
567 
568 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
569 		mcr |= UART_MCR_RTS;
570 	else
571 		mcr &= ~UART_MCR_RTS;
572 	serial8250_out_MCR(p, mcr);
573 }
574 
575 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
576 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
577 
578 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
579 {
580 	serial8250_clear_fifos(p);
581 	serial_out(p, UART_FCR, p->fcr);
582 }
583 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
584 
585 void serial8250_rpm_get(struct uart_8250_port *p)
586 {
587 	if (!(p->capabilities & UART_CAP_RPM))
588 		return;
589 	pm_runtime_get_sync(p->port.dev);
590 }
591 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
592 
593 void serial8250_rpm_put(struct uart_8250_port *p)
594 {
595 	if (!(p->capabilities & UART_CAP_RPM))
596 		return;
597 	pm_runtime_mark_last_busy(p->port.dev);
598 	pm_runtime_put_autosuspend(p->port.dev);
599 }
600 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
601 
602 /**
603  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
604  *	@p:	uart_8250_port port instance
605  *
606  *	The function is used to start rs485 software emulating on the
607  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
608  *	transmission. The function is idempotent, so it is safe to call it
609  *	multiple times.
610  *
611  *	The caller MUST enable interrupt on empty shift register before
612  *	calling serial8250_em485_init(). This interrupt is not a part of
613  *	8250 standard, but implementation defined.
614  *
615  *	The function is supposed to be called from .rs485_config callback
616  *	or from any other callback protected with p->port.lock spinlock.
617  *
618  *	See also serial8250_em485_destroy()
619  *
620  *	Return 0 - success, -errno - otherwise
621  */
622 int serial8250_em485_init(struct uart_8250_port *p)
623 {
624 	if (p->em485)
625 		return 0;
626 
627 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
628 	if (!p->em485)
629 		return -ENOMEM;
630 
631 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
632 		     HRTIMER_MODE_REL);
633 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
634 		     HRTIMER_MODE_REL);
635 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
636 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
637 	p->em485->port = p;
638 	p->em485->active_timer = NULL;
639 	serial8250_em485_rts_after_send(p);
640 
641 	return 0;
642 }
643 EXPORT_SYMBOL_GPL(serial8250_em485_init);
644 
645 /**
646  *	serial8250_em485_destroy() - put uart_8250_port into normal state
647  *	@p:	uart_8250_port port instance
648  *
649  *	The function is used to stop rs485 software emulating on the
650  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
651  *	call it multiple times.
652  *
653  *	The function is supposed to be called from .rs485_config callback
654  *	or from any other callback protected with p->port.lock spinlock.
655  *
656  *	See also serial8250_em485_init()
657  */
658 void serial8250_em485_destroy(struct uart_8250_port *p)
659 {
660 	if (!p->em485)
661 		return;
662 
663 	hrtimer_cancel(&p->em485->start_tx_timer);
664 	hrtimer_cancel(&p->em485->stop_tx_timer);
665 
666 	kfree(p->em485);
667 	p->em485 = NULL;
668 }
669 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
670 
671 /*
672  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
673  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
674  * empty and the HW can idle again.
675  */
676 void serial8250_rpm_get_tx(struct uart_8250_port *p)
677 {
678 	unsigned char rpm_active;
679 
680 	if (!(p->capabilities & UART_CAP_RPM))
681 		return;
682 
683 	rpm_active = xchg(&p->rpm_tx_active, 1);
684 	if (rpm_active)
685 		return;
686 	pm_runtime_get_sync(p->port.dev);
687 }
688 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
689 
690 void serial8250_rpm_put_tx(struct uart_8250_port *p)
691 {
692 	unsigned char rpm_active;
693 
694 	if (!(p->capabilities & UART_CAP_RPM))
695 		return;
696 
697 	rpm_active = xchg(&p->rpm_tx_active, 0);
698 	if (!rpm_active)
699 		return;
700 	pm_runtime_mark_last_busy(p->port.dev);
701 	pm_runtime_put_autosuspend(p->port.dev);
702 }
703 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
704 
705 /*
706  * IER sleep support.  UARTs which have EFRs need the "extended
707  * capability" bit enabled.  Note that on XR16C850s, we need to
708  * reset LCR to write to IER.
709  */
710 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
711 {
712 	unsigned char lcr = 0, efr = 0;
713 	/*
714 	 * Exar UARTs have a SLEEP register that enables or disables
715 	 * each UART to enter sleep mode separately.  On the XR17V35x the
716 	 * register is accessible to each UART at the UART_EXAR_SLEEP
717 	 * offset but the UART channel may only write to the corresponding
718 	 * bit.
719 	 */
720 	serial8250_rpm_get(p);
721 	if ((p->port.type == PORT_XR17V35X) ||
722 	   (p->port.type == PORT_XR17D15X)) {
723 		serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
724 		goto out;
725 	}
726 
727 	if (p->capabilities & UART_CAP_SLEEP) {
728 		if (p->capabilities & UART_CAP_EFR) {
729 			lcr = serial_in(p, UART_LCR);
730 			efr = serial_in(p, UART_EFR);
731 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
732 			serial_out(p, UART_EFR, UART_EFR_ECB);
733 			serial_out(p, UART_LCR, 0);
734 		}
735 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
736 		if (p->capabilities & UART_CAP_EFR) {
737 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
738 			serial_out(p, UART_EFR, efr);
739 			serial_out(p, UART_LCR, lcr);
740 		}
741 	}
742 out:
743 	serial8250_rpm_put(p);
744 }
745 
746 #ifdef CONFIG_SERIAL_8250_RSA
747 /*
748  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
749  * We set the port uart clock rate if we succeed.
750  */
751 static int __enable_rsa(struct uart_8250_port *up)
752 {
753 	unsigned char mode;
754 	int result;
755 
756 	mode = serial_in(up, UART_RSA_MSR);
757 	result = mode & UART_RSA_MSR_FIFO;
758 
759 	if (!result) {
760 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
761 		mode = serial_in(up, UART_RSA_MSR);
762 		result = mode & UART_RSA_MSR_FIFO;
763 	}
764 
765 	if (result)
766 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
767 
768 	return result;
769 }
770 
771 static void enable_rsa(struct uart_8250_port *up)
772 {
773 	if (up->port.type == PORT_RSA) {
774 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
775 			spin_lock_irq(&up->port.lock);
776 			__enable_rsa(up);
777 			spin_unlock_irq(&up->port.lock);
778 		}
779 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
780 			serial_out(up, UART_RSA_FRR, 0);
781 	}
782 }
783 
784 /*
785  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
786  * It is unknown why interrupts were disabled in here.  However,
787  * the caller is expected to preserve this behaviour by grabbing
788  * the spinlock before calling this function.
789  */
790 static void disable_rsa(struct uart_8250_port *up)
791 {
792 	unsigned char mode;
793 	int result;
794 
795 	if (up->port.type == PORT_RSA &&
796 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
797 		spin_lock_irq(&up->port.lock);
798 
799 		mode = serial_in(up, UART_RSA_MSR);
800 		result = !(mode & UART_RSA_MSR_FIFO);
801 
802 		if (!result) {
803 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
804 			mode = serial_in(up, UART_RSA_MSR);
805 			result = !(mode & UART_RSA_MSR_FIFO);
806 		}
807 
808 		if (result)
809 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
810 		spin_unlock_irq(&up->port.lock);
811 	}
812 }
813 #endif /* CONFIG_SERIAL_8250_RSA */
814 
815 /*
816  * This is a quickie test to see how big the FIFO is.
817  * It doesn't work at all the time, more's the pity.
818  */
819 static int size_fifo(struct uart_8250_port *up)
820 {
821 	unsigned char old_fcr, old_mcr, old_lcr;
822 	unsigned short old_dl;
823 	int count;
824 
825 	old_lcr = serial_in(up, UART_LCR);
826 	serial_out(up, UART_LCR, 0);
827 	old_fcr = serial_in(up, UART_FCR);
828 	old_mcr = serial8250_in_MCR(up);
829 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
830 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
831 	serial8250_out_MCR(up, UART_MCR_LOOP);
832 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
833 	old_dl = serial_dl_read(up);
834 	serial_dl_write(up, 0x0001);
835 	serial_out(up, UART_LCR, 0x03);
836 	for (count = 0; count < 256; count++)
837 		serial_out(up, UART_TX, count);
838 	mdelay(20);/* FIXME - schedule_timeout */
839 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
840 	     (count < 256); count++)
841 		serial_in(up, UART_RX);
842 	serial_out(up, UART_FCR, old_fcr);
843 	serial8250_out_MCR(up, old_mcr);
844 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
845 	serial_dl_write(up, old_dl);
846 	serial_out(up, UART_LCR, old_lcr);
847 
848 	return count;
849 }
850 
851 /*
852  * Read UART ID using the divisor method - set DLL and DLM to zero
853  * and the revision will be in DLL and device type in DLM.  We
854  * preserve the device state across this.
855  */
856 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
857 {
858 	unsigned char old_lcr;
859 	unsigned int id, old_dl;
860 
861 	old_lcr = serial_in(p, UART_LCR);
862 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
863 	old_dl = serial_dl_read(p);
864 	serial_dl_write(p, 0);
865 	id = serial_dl_read(p);
866 	serial_dl_write(p, old_dl);
867 
868 	serial_out(p, UART_LCR, old_lcr);
869 
870 	return id;
871 }
872 
873 /*
874  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
875  * When this function is called we know it is at least a StarTech
876  * 16650 V2, but it might be one of several StarTech UARTs, or one of
877  * its clones.  (We treat the broken original StarTech 16650 V1 as a
878  * 16550, and why not?  Startech doesn't seem to even acknowledge its
879  * existence.)
880  *
881  * What evil have men's minds wrought...
882  */
883 static void autoconfig_has_efr(struct uart_8250_port *up)
884 {
885 	unsigned int id1, id2, id3, rev;
886 
887 	/*
888 	 * Everything with an EFR has SLEEP
889 	 */
890 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
891 
892 	/*
893 	 * First we check to see if it's an Oxford Semiconductor UART.
894 	 *
895 	 * If we have to do this here because some non-National
896 	 * Semiconductor clone chips lock up if you try writing to the
897 	 * LSR register (which serial_icr_read does)
898 	 */
899 
900 	/*
901 	 * Check for Oxford Semiconductor 16C950.
902 	 *
903 	 * EFR [4] must be set else this test fails.
904 	 *
905 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
906 	 * claims that it's needed for 952 dual UART's (which are not
907 	 * recommended for new designs).
908 	 */
909 	up->acr = 0;
910 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
911 	serial_out(up, UART_EFR, UART_EFR_ECB);
912 	serial_out(up, UART_LCR, 0x00);
913 	id1 = serial_icr_read(up, UART_ID1);
914 	id2 = serial_icr_read(up, UART_ID2);
915 	id3 = serial_icr_read(up, UART_ID3);
916 	rev = serial_icr_read(up, UART_REV);
917 
918 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
919 
920 	if (id1 == 0x16 && id2 == 0xC9 &&
921 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
922 		up->port.type = PORT_16C950;
923 
924 		/*
925 		 * Enable work around for the Oxford Semiconductor 952 rev B
926 		 * chip which causes it to seriously miscalculate baud rates
927 		 * when DLL is 0.
928 		 */
929 		if (id3 == 0x52 && rev == 0x01)
930 			up->bugs |= UART_BUG_QUOT;
931 		return;
932 	}
933 
934 	/*
935 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
936 	 * reading back DLL and DLM.  The chip type depends on the DLM
937 	 * value read back:
938 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
939 	 *  0x12 - XR16C2850.
940 	 *  0x14 - XR16C854.
941 	 */
942 	id1 = autoconfig_read_divisor_id(up);
943 	DEBUG_AUTOCONF("850id=%04x ", id1);
944 
945 	id2 = id1 >> 8;
946 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
947 		up->port.type = PORT_16850;
948 		return;
949 	}
950 
951 	/*
952 	 * It wasn't an XR16C850.
953 	 *
954 	 * We distinguish between the '654 and the '650 by counting
955 	 * how many bytes are in the FIFO.  I'm using this for now,
956 	 * since that's the technique that was sent to me in the
957 	 * serial driver update, but I'm not convinced this works.
958 	 * I've had problems doing this in the past.  -TYT
959 	 */
960 	if (size_fifo(up) == 64)
961 		up->port.type = PORT_16654;
962 	else
963 		up->port.type = PORT_16650V2;
964 }
965 
966 /*
967  * We detected a chip without a FIFO.  Only two fall into
968  * this category - the original 8250 and the 16450.  The
969  * 16450 has a scratch register (accessible with LCR=0)
970  */
971 static void autoconfig_8250(struct uart_8250_port *up)
972 {
973 	unsigned char scratch, status1, status2;
974 
975 	up->port.type = PORT_8250;
976 
977 	scratch = serial_in(up, UART_SCR);
978 	serial_out(up, UART_SCR, 0xa5);
979 	status1 = serial_in(up, UART_SCR);
980 	serial_out(up, UART_SCR, 0x5a);
981 	status2 = serial_in(up, UART_SCR);
982 	serial_out(up, UART_SCR, scratch);
983 
984 	if (status1 == 0xa5 && status2 == 0x5a)
985 		up->port.type = PORT_16450;
986 }
987 
988 static int broken_efr(struct uart_8250_port *up)
989 {
990 	/*
991 	 * Exar ST16C2550 "A2" devices incorrectly detect as
992 	 * having an EFR, and report an ID of 0x0201.  See
993 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
994 	 */
995 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
996 		return 1;
997 
998 	return 0;
999 }
1000 
1001 /*
1002  * We know that the chip has FIFOs.  Does it have an EFR?  The
1003  * EFR is located in the same register position as the IIR and
1004  * we know the top two bits of the IIR are currently set.  The
1005  * EFR should contain zero.  Try to read the EFR.
1006  */
1007 static void autoconfig_16550a(struct uart_8250_port *up)
1008 {
1009 	unsigned char status1, status2;
1010 	unsigned int iersave;
1011 
1012 	up->port.type = PORT_16550A;
1013 	up->capabilities |= UART_CAP_FIFO;
1014 
1015 	/*
1016 	 * XR17V35x UARTs have an extra divisor register, DLD
1017 	 * that gets enabled with when DLAB is set which will
1018 	 * cause the device to incorrectly match and assign
1019 	 * port type to PORT_16650.  The EFR for this UART is
1020 	 * found at offset 0x09. Instead check the Deice ID (DVID)
1021 	 * register for a 2, 4 or 8 port UART.
1022 	 */
1023 	if (up->port.flags & UPF_EXAR_EFR) {
1024 		status1 = serial_in(up, UART_EXAR_DVID);
1025 		if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1026 			DEBUG_AUTOCONF("Exar XR17V35x ");
1027 			up->port.type = PORT_XR17V35X;
1028 			up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1029 						UART_CAP_SLEEP;
1030 
1031 			return;
1032 		}
1033 
1034 	}
1035 
1036 	/*
1037 	 * Check for presence of the EFR when DLAB is set.
1038 	 * Only ST16C650V1 UARTs pass this test.
1039 	 */
1040 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1041 	if (serial_in(up, UART_EFR) == 0) {
1042 		serial_out(up, UART_EFR, 0xA8);
1043 		if (serial_in(up, UART_EFR) != 0) {
1044 			DEBUG_AUTOCONF("EFRv1 ");
1045 			up->port.type = PORT_16650;
1046 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1047 		} else {
1048 			serial_out(up, UART_LCR, 0);
1049 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1050 				   UART_FCR7_64BYTE);
1051 			status1 = serial_in(up, UART_IIR) >> 5;
1052 			serial_out(up, UART_FCR, 0);
1053 			serial_out(up, UART_LCR, 0);
1054 
1055 			if (status1 == 7)
1056 				up->port.type = PORT_16550A_FSL64;
1057 			else
1058 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1059 		}
1060 		serial_out(up, UART_EFR, 0);
1061 		return;
1062 	}
1063 
1064 	/*
1065 	 * Maybe it requires 0xbf to be written to the LCR.
1066 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1067 	 */
1068 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1069 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1070 		DEBUG_AUTOCONF("EFRv2 ");
1071 		autoconfig_has_efr(up);
1072 		return;
1073 	}
1074 
1075 	/*
1076 	 * Check for a National Semiconductor SuperIO chip.
1077 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1078 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1079 	 * switch back to bank 2, read it from EXCR1 again and check
1080 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1081 	 */
1082 	serial_out(up, UART_LCR, 0);
1083 	status1 = serial8250_in_MCR(up);
1084 	serial_out(up, UART_LCR, 0xE0);
1085 	status2 = serial_in(up, 0x02); /* EXCR1 */
1086 
1087 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1088 		serial_out(up, UART_LCR, 0);
1089 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1090 		serial_out(up, UART_LCR, 0xE0);
1091 		status2 = serial_in(up, 0x02); /* EXCR1 */
1092 		serial_out(up, UART_LCR, 0);
1093 		serial8250_out_MCR(up, status1);
1094 
1095 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1096 			unsigned short quot;
1097 
1098 			serial_out(up, UART_LCR, 0xE0);
1099 
1100 			quot = serial_dl_read(up);
1101 			quot <<= 3;
1102 
1103 			if (ns16550a_goto_highspeed(up))
1104 				serial_dl_write(up, quot);
1105 
1106 			serial_out(up, UART_LCR, 0);
1107 
1108 			up->port.uartclk = 921600*16;
1109 			up->port.type = PORT_NS16550A;
1110 			up->capabilities |= UART_NATSEMI;
1111 			return;
1112 		}
1113 	}
1114 
1115 	/*
1116 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1117 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1118 	 * Try setting it with and without DLAB set.  Cheap clones
1119 	 * set bit 5 without DLAB set.
1120 	 */
1121 	serial_out(up, UART_LCR, 0);
1122 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1123 	status1 = serial_in(up, UART_IIR) >> 5;
1124 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1125 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1126 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1127 	status2 = serial_in(up, UART_IIR) >> 5;
1128 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1129 	serial_out(up, UART_LCR, 0);
1130 
1131 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1132 
1133 	if (status1 == 6 && status2 == 7) {
1134 		up->port.type = PORT_16750;
1135 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1136 		return;
1137 	}
1138 
1139 	/*
1140 	 * Try writing and reading the UART_IER_UUE bit (b6).
1141 	 * If it works, this is probably one of the Xscale platform's
1142 	 * internal UARTs.
1143 	 * We're going to explicitly set the UUE bit to 0 before
1144 	 * trying to write and read a 1 just to make sure it's not
1145 	 * already a 1 and maybe locked there before we even start start.
1146 	 */
1147 	iersave = serial_in(up, UART_IER);
1148 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1149 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1150 		/*
1151 		 * OK it's in a known zero state, try writing and reading
1152 		 * without disturbing the current state of the other bits.
1153 		 */
1154 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1155 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1156 			/*
1157 			 * It's an Xscale.
1158 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1159 			 */
1160 			DEBUG_AUTOCONF("Xscale ");
1161 			up->port.type = PORT_XSCALE;
1162 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1163 			return;
1164 		}
1165 	} else {
1166 		/*
1167 		 * If we got here we couldn't force the IER_UUE bit to 0.
1168 		 * Log it and continue.
1169 		 */
1170 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1171 	}
1172 	serial_out(up, UART_IER, iersave);
1173 
1174 	/*
1175 	 * Exar uarts have EFR in a weird location
1176 	 */
1177 	if (up->port.flags & UPF_EXAR_EFR) {
1178 		DEBUG_AUTOCONF("Exar XR17D15x ");
1179 		up->port.type = PORT_XR17D15X;
1180 		up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1181 				    UART_CAP_SLEEP;
1182 
1183 		return;
1184 	}
1185 
1186 	/*
1187 	 * We distinguish between 16550A and U6 16550A by counting
1188 	 * how many bytes are in the FIFO.
1189 	 */
1190 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1191 		up->port.type = PORT_U6_16550A;
1192 		up->capabilities |= UART_CAP_AFE;
1193 	}
1194 }
1195 
1196 /*
1197  * This routine is called by rs_init() to initialize a specific serial
1198  * port.  It determines what type of UART chip this serial port is
1199  * using: 8250, 16450, 16550, 16550A.  The important question is
1200  * whether or not this UART is a 16550A or not, since this will
1201  * determine whether or not we can use its FIFO features or not.
1202  */
1203 static void autoconfig(struct uart_8250_port *up)
1204 {
1205 	unsigned char status1, scratch, scratch2, scratch3;
1206 	unsigned char save_lcr, save_mcr;
1207 	struct uart_port *port = &up->port;
1208 	unsigned long flags;
1209 	unsigned int old_capabilities;
1210 
1211 	if (!port->iobase && !port->mapbase && !port->membase)
1212 		return;
1213 
1214 	DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1215 		       serial_index(port), port->iobase, port->membase);
1216 
1217 	/*
1218 	 * We really do need global IRQs disabled here - we're going to
1219 	 * be frobbing the chips IRQ enable register to see if it exists.
1220 	 */
1221 	spin_lock_irqsave(&port->lock, flags);
1222 
1223 	up->capabilities = 0;
1224 	up->bugs = 0;
1225 
1226 	if (!(port->flags & UPF_BUGGY_UART)) {
1227 		/*
1228 		 * Do a simple existence test first; if we fail this,
1229 		 * there's no point trying anything else.
1230 		 *
1231 		 * 0x80 is used as a nonsense port to prevent against
1232 		 * false positives due to ISA bus float.  The
1233 		 * assumption is that 0x80 is a non-existent port;
1234 		 * which should be safe since include/asm/io.h also
1235 		 * makes this assumption.
1236 		 *
1237 		 * Note: this is safe as long as MCR bit 4 is clear
1238 		 * and the device is in "PC" mode.
1239 		 */
1240 		scratch = serial_in(up, UART_IER);
1241 		serial_out(up, UART_IER, 0);
1242 #ifdef __i386__
1243 		outb(0xff, 0x080);
1244 #endif
1245 		/*
1246 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1247 		 * 16C754B) allow only to modify them if an EFR bit is set.
1248 		 */
1249 		scratch2 = serial_in(up, UART_IER) & 0x0f;
1250 		serial_out(up, UART_IER, 0x0F);
1251 #ifdef __i386__
1252 		outb(0, 0x080);
1253 #endif
1254 		scratch3 = serial_in(up, UART_IER) & 0x0f;
1255 		serial_out(up, UART_IER, scratch);
1256 		if (scratch2 != 0 || scratch3 != 0x0F) {
1257 			/*
1258 			 * We failed; there's nothing here
1259 			 */
1260 			spin_unlock_irqrestore(&port->lock, flags);
1261 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1262 				       scratch2, scratch3);
1263 			goto out;
1264 		}
1265 	}
1266 
1267 	save_mcr = serial8250_in_MCR(up);
1268 	save_lcr = serial_in(up, UART_LCR);
1269 
1270 	/*
1271 	 * Check to see if a UART is really there.  Certain broken
1272 	 * internal modems based on the Rockwell chipset fail this
1273 	 * test, because they apparently don't implement the loopback
1274 	 * test mode.  So this test is skipped on the COM 1 through
1275 	 * COM 4 ports.  This *should* be safe, since no board
1276 	 * manufacturer would be stupid enough to design a board
1277 	 * that conflicts with COM 1-4 --- we hope!
1278 	 */
1279 	if (!(port->flags & UPF_SKIP_TEST)) {
1280 		serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1281 		status1 = serial_in(up, UART_MSR) & 0xF0;
1282 		serial8250_out_MCR(up, save_mcr);
1283 		if (status1 != 0x90) {
1284 			spin_unlock_irqrestore(&port->lock, flags);
1285 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1286 				       status1);
1287 			goto out;
1288 		}
1289 	}
1290 
1291 	/*
1292 	 * We're pretty sure there's a port here.  Lets find out what
1293 	 * type of port it is.  The IIR top two bits allows us to find
1294 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1295 	 * determines what we test for next.
1296 	 *
1297 	 * We also initialise the EFR (if any) to zero for later.  The
1298 	 * EFR occupies the same register location as the FCR and IIR.
1299 	 */
1300 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1301 	serial_out(up, UART_EFR, 0);
1302 	serial_out(up, UART_LCR, 0);
1303 
1304 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1305 	scratch = serial_in(up, UART_IIR) >> 6;
1306 
1307 	switch (scratch) {
1308 	case 0:
1309 		autoconfig_8250(up);
1310 		break;
1311 	case 1:
1312 		port->type = PORT_UNKNOWN;
1313 		break;
1314 	case 2:
1315 		port->type = PORT_16550;
1316 		break;
1317 	case 3:
1318 		autoconfig_16550a(up);
1319 		break;
1320 	}
1321 
1322 #ifdef CONFIG_SERIAL_8250_RSA
1323 	/*
1324 	 * Only probe for RSA ports if we got the region.
1325 	 */
1326 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1327 	    __enable_rsa(up))
1328 		port->type = PORT_RSA;
1329 #endif
1330 
1331 	serial_out(up, UART_LCR, save_lcr);
1332 
1333 	port->fifosize = uart_config[up->port.type].fifo_size;
1334 	old_capabilities = up->capabilities;
1335 	up->capabilities = uart_config[port->type].flags;
1336 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1337 
1338 	if (port->type == PORT_UNKNOWN)
1339 		goto out_lock;
1340 
1341 	/*
1342 	 * Reset the UART.
1343 	 */
1344 #ifdef CONFIG_SERIAL_8250_RSA
1345 	if (port->type == PORT_RSA)
1346 		serial_out(up, UART_RSA_FRR, 0);
1347 #endif
1348 	serial8250_out_MCR(up, save_mcr);
1349 	serial8250_clear_fifos(up);
1350 	serial_in(up, UART_RX);
1351 	if (up->capabilities & UART_CAP_UUE)
1352 		serial_out(up, UART_IER, UART_IER_UUE);
1353 	else
1354 		serial_out(up, UART_IER, 0);
1355 
1356 out_lock:
1357 	spin_unlock_irqrestore(&port->lock, flags);
1358 
1359 	/*
1360 	 * Check if the device is a Fintek F81216A
1361 	 */
1362 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1363 		fintek_8250_probe(up);
1364 
1365 	if (up->capabilities != old_capabilities) {
1366 		pr_warn("ttyS%d: detected caps %08x should be %08x\n",
1367 		       serial_index(port), old_capabilities,
1368 		       up->capabilities);
1369 	}
1370 out:
1371 	DEBUG_AUTOCONF("iir=%d ", scratch);
1372 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1373 }
1374 
1375 static void autoconfig_irq(struct uart_8250_port *up)
1376 {
1377 	struct uart_port *port = &up->port;
1378 	unsigned char save_mcr, save_ier;
1379 	unsigned char save_ICP = 0;
1380 	unsigned int ICP = 0;
1381 	unsigned long irqs;
1382 	int irq;
1383 
1384 	if (port->flags & UPF_FOURPORT) {
1385 		ICP = (port->iobase & 0xfe0) | 0x1f;
1386 		save_ICP = inb_p(ICP);
1387 		outb_p(0x80, ICP);
1388 		inb_p(ICP);
1389 	}
1390 
1391 	if (uart_console(port))
1392 		console_lock();
1393 
1394 	/* forget possible initially masked and pending IRQ */
1395 	probe_irq_off(probe_irq_on());
1396 	save_mcr = serial8250_in_MCR(up);
1397 	save_ier = serial_in(up, UART_IER);
1398 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1399 
1400 	irqs = probe_irq_on();
1401 	serial8250_out_MCR(up, 0);
1402 	udelay(10);
1403 	if (port->flags & UPF_FOURPORT) {
1404 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1405 	} else {
1406 		serial8250_out_MCR(up,
1407 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1408 	}
1409 	serial_out(up, UART_IER, 0x0f);	/* enable all intrs */
1410 	serial_in(up, UART_LSR);
1411 	serial_in(up, UART_RX);
1412 	serial_in(up, UART_IIR);
1413 	serial_in(up, UART_MSR);
1414 	serial_out(up, UART_TX, 0xFF);
1415 	udelay(20);
1416 	irq = probe_irq_off(irqs);
1417 
1418 	serial8250_out_MCR(up, save_mcr);
1419 	serial_out(up, UART_IER, save_ier);
1420 
1421 	if (port->flags & UPF_FOURPORT)
1422 		outb_p(save_ICP, ICP);
1423 
1424 	if (uart_console(port))
1425 		console_unlock();
1426 
1427 	port->irq = (irq > 0) ? irq : 0;
1428 }
1429 
1430 static void serial8250_stop_rx(struct uart_port *port)
1431 {
1432 	struct uart_8250_port *up = up_to_u8250p(port);
1433 
1434 	serial8250_rpm_get(up);
1435 
1436 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1437 	up->port.read_status_mask &= ~UART_LSR_DR;
1438 	serial_port_out(port, UART_IER, up->ier);
1439 
1440 	serial8250_rpm_put(up);
1441 }
1442 
1443 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1444 {
1445 	serial8250_em485_rts_after_send(p);
1446 
1447 	/*
1448 	 * Empty the RX FIFO, we are not interested in anything
1449 	 * received during the half-duplex transmission.
1450 	 * Enable previously disabled RX interrupts.
1451 	 */
1452 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1453 		serial8250_clear_and_reinit_fifos(p);
1454 
1455 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1456 		serial_port_out(&p->port, UART_IER, p->ier);
1457 	}
1458 }
1459 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1460 {
1461 	struct uart_8250_em485 *em485;
1462 	struct uart_8250_port *p;
1463 	unsigned long flags;
1464 
1465 	em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1466 	p = em485->port;
1467 
1468 	serial8250_rpm_get(p);
1469 	spin_lock_irqsave(&p->port.lock, flags);
1470 	if (em485->active_timer == &em485->stop_tx_timer) {
1471 		__do_stop_tx_rs485(p);
1472 		em485->active_timer = NULL;
1473 	}
1474 	spin_unlock_irqrestore(&p->port.lock, flags);
1475 	serial8250_rpm_put(p);
1476 	return HRTIMER_NORESTART;
1477 }
1478 
1479 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1480 {
1481 	long sec = msec / 1000;
1482 	long nsec = (msec % 1000) * 1000000;
1483 	ktime_t t = ktime_set(sec, nsec);
1484 
1485 	hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1486 }
1487 
1488 static void __stop_tx_rs485(struct uart_8250_port *p)
1489 {
1490 	struct uart_8250_em485 *em485 = p->em485;
1491 
1492 	/*
1493 	 * __do_stop_tx_rs485 is going to set RTS according to config
1494 	 * AND flush RX FIFO if required.
1495 	 */
1496 	if (p->port.rs485.delay_rts_after_send > 0) {
1497 		em485->active_timer = &em485->stop_tx_timer;
1498 		start_hrtimer_ms(&em485->stop_tx_timer,
1499 				   p->port.rs485.delay_rts_after_send);
1500 	} else {
1501 		__do_stop_tx_rs485(p);
1502 	}
1503 }
1504 
1505 static inline void __do_stop_tx(struct uart_8250_port *p)
1506 {
1507 	if (p->ier & UART_IER_THRI) {
1508 		p->ier &= ~UART_IER_THRI;
1509 		serial_out(p, UART_IER, p->ier);
1510 		serial8250_rpm_put_tx(p);
1511 	}
1512 }
1513 
1514 static inline void __stop_tx(struct uart_8250_port *p)
1515 {
1516 	struct uart_8250_em485 *em485 = p->em485;
1517 
1518 	if (em485) {
1519 		unsigned char lsr = serial_in(p, UART_LSR);
1520 		/*
1521 		 * To provide required timeing and allow FIFO transfer,
1522 		 * __stop_tx_rs485() must be called only when both FIFO and
1523 		 * shift register are empty. It is for device driver to enable
1524 		 * interrupt on TEMT.
1525 		 */
1526 		if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1527 			return;
1528 
1529 		em485->active_timer = NULL;
1530 
1531 		__stop_tx_rs485(p);
1532 	}
1533 	__do_stop_tx(p);
1534 }
1535 
1536 static void serial8250_stop_tx(struct uart_port *port)
1537 {
1538 	struct uart_8250_port *up = up_to_u8250p(port);
1539 
1540 	serial8250_rpm_get(up);
1541 	__stop_tx(up);
1542 
1543 	/*
1544 	 * We really want to stop the transmitter from sending.
1545 	 */
1546 	if (port->type == PORT_16C950) {
1547 		up->acr |= UART_ACR_TXDIS;
1548 		serial_icr_write(up, UART_ACR, up->acr);
1549 	}
1550 	serial8250_rpm_put(up);
1551 }
1552 
1553 static inline void __start_tx(struct uart_port *port)
1554 {
1555 	struct uart_8250_port *up = up_to_u8250p(port);
1556 
1557 	if (up->dma && !up->dma->tx_dma(up))
1558 		return;
1559 
1560 	if (!(up->ier & UART_IER_THRI)) {
1561 		up->ier |= UART_IER_THRI;
1562 		serial_port_out(port, UART_IER, up->ier);
1563 
1564 		if (up->bugs & UART_BUG_TXEN) {
1565 			unsigned char lsr;
1566 
1567 			lsr = serial_in(up, UART_LSR);
1568 			up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1569 			if (lsr & UART_LSR_THRE)
1570 				serial8250_tx_chars(up);
1571 		}
1572 	}
1573 
1574 	/*
1575 	 * Re-enable the transmitter if we disabled it.
1576 	 */
1577 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1578 		up->acr &= ~UART_ACR_TXDIS;
1579 		serial_icr_write(up, UART_ACR, up->acr);
1580 	}
1581 }
1582 
1583 static inline void start_tx_rs485(struct uart_port *port)
1584 {
1585 	struct uart_8250_port *up = up_to_u8250p(port);
1586 	struct uart_8250_em485 *em485 = up->em485;
1587 	unsigned char mcr;
1588 
1589 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1590 		serial8250_stop_rx(&up->port);
1591 
1592 	em485->active_timer = NULL;
1593 
1594 	mcr = serial8250_in_MCR(up);
1595 	if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1596 	    !!(mcr & UART_MCR_RTS)) {
1597 		if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1598 			mcr |= UART_MCR_RTS;
1599 		else
1600 			mcr &= ~UART_MCR_RTS;
1601 		serial8250_out_MCR(up, mcr);
1602 
1603 		if (up->port.rs485.delay_rts_before_send > 0) {
1604 			em485->active_timer = &em485->start_tx_timer;
1605 			start_hrtimer_ms(&em485->start_tx_timer,
1606 					 up->port.rs485.delay_rts_before_send);
1607 			return;
1608 		}
1609 	}
1610 
1611 	__start_tx(port);
1612 }
1613 
1614 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1615 {
1616 	struct uart_8250_em485 *em485;
1617 	struct uart_8250_port *p;
1618 	unsigned long flags;
1619 
1620 	em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1621 	p = em485->port;
1622 
1623 	spin_lock_irqsave(&p->port.lock, flags);
1624 	if (em485->active_timer == &em485->start_tx_timer) {
1625 		__start_tx(&p->port);
1626 		em485->active_timer = NULL;
1627 	}
1628 	spin_unlock_irqrestore(&p->port.lock, flags);
1629 	return HRTIMER_NORESTART;
1630 }
1631 
1632 static void serial8250_start_tx(struct uart_port *port)
1633 {
1634 	struct uart_8250_port *up = up_to_u8250p(port);
1635 	struct uart_8250_em485 *em485 = up->em485;
1636 
1637 	serial8250_rpm_get_tx(up);
1638 
1639 	if (em485 &&
1640 	    em485->active_timer == &em485->start_tx_timer)
1641 		return;
1642 
1643 	if (em485)
1644 		start_tx_rs485(port);
1645 	else
1646 		__start_tx(port);
1647 }
1648 
1649 static void serial8250_throttle(struct uart_port *port)
1650 {
1651 	port->throttle(port);
1652 }
1653 
1654 static void serial8250_unthrottle(struct uart_port *port)
1655 {
1656 	port->unthrottle(port);
1657 }
1658 
1659 static void serial8250_disable_ms(struct uart_port *port)
1660 {
1661 	struct uart_8250_port *up = up_to_u8250p(port);
1662 
1663 	/* no MSR capabilities */
1664 	if (up->bugs & UART_BUG_NOMSR)
1665 		return;
1666 
1667 	up->ier &= ~UART_IER_MSI;
1668 	serial_port_out(port, UART_IER, up->ier);
1669 }
1670 
1671 static void serial8250_enable_ms(struct uart_port *port)
1672 {
1673 	struct uart_8250_port *up = up_to_u8250p(port);
1674 
1675 	/* no MSR capabilities */
1676 	if (up->bugs & UART_BUG_NOMSR)
1677 		return;
1678 
1679 	up->ier |= UART_IER_MSI;
1680 
1681 	serial8250_rpm_get(up);
1682 	serial_port_out(port, UART_IER, up->ier);
1683 	serial8250_rpm_put(up);
1684 }
1685 
1686 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1687 {
1688 	struct uart_port *port = &up->port;
1689 	unsigned char ch;
1690 	char flag = TTY_NORMAL;
1691 
1692 	if (likely(lsr & UART_LSR_DR))
1693 		ch = serial_in(up, UART_RX);
1694 	else
1695 		/*
1696 		 * Intel 82571 has a Serial Over Lan device that will
1697 		 * set UART_LSR_BI without setting UART_LSR_DR when
1698 		 * it receives a break. To avoid reading from the
1699 		 * receive buffer without UART_LSR_DR bit set, we
1700 		 * just force the read character to be 0
1701 		 */
1702 		ch = 0;
1703 
1704 	port->icount.rx++;
1705 
1706 	lsr |= up->lsr_saved_flags;
1707 	up->lsr_saved_flags = 0;
1708 
1709 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1710 		if (lsr & UART_LSR_BI) {
1711 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1712 			port->icount.brk++;
1713 			/*
1714 			 * We do the SysRQ and SAK checking
1715 			 * here because otherwise the break
1716 			 * may get masked by ignore_status_mask
1717 			 * or read_status_mask.
1718 			 */
1719 			if (uart_handle_break(port))
1720 				return;
1721 		} else if (lsr & UART_LSR_PE)
1722 			port->icount.parity++;
1723 		else if (lsr & UART_LSR_FE)
1724 			port->icount.frame++;
1725 		if (lsr & UART_LSR_OE)
1726 			port->icount.overrun++;
1727 
1728 		/*
1729 		 * Mask off conditions which should be ignored.
1730 		 */
1731 		lsr &= port->read_status_mask;
1732 
1733 		if (lsr & UART_LSR_BI) {
1734 			pr_debug("%s: handling break\n", __func__);
1735 			flag = TTY_BREAK;
1736 		} else if (lsr & UART_LSR_PE)
1737 			flag = TTY_PARITY;
1738 		else if (lsr & UART_LSR_FE)
1739 			flag = TTY_FRAME;
1740 	}
1741 	if (uart_handle_sysrq_char(port, ch))
1742 		return;
1743 
1744 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1745 }
1746 EXPORT_SYMBOL_GPL(serial8250_read_char);
1747 
1748 /*
1749  * serial8250_rx_chars: processes according to the passed in LSR
1750  * value, and returns the remaining LSR bits not handled
1751  * by this Rx routine.
1752  */
1753 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1754 {
1755 	struct uart_port *port = &up->port;
1756 	int max_count = 256;
1757 
1758 	do {
1759 		serial8250_read_char(up, lsr);
1760 		if (--max_count == 0)
1761 			break;
1762 		lsr = serial_in(up, UART_LSR);
1763 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1764 
1765 	tty_flip_buffer_push(&port->state->port);
1766 	return lsr;
1767 }
1768 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1769 
1770 void serial8250_tx_chars(struct uart_8250_port *up)
1771 {
1772 	struct uart_port *port = &up->port;
1773 	struct circ_buf *xmit = &port->state->xmit;
1774 	int count;
1775 
1776 	if (port->x_char) {
1777 		serial_out(up, UART_TX, port->x_char);
1778 		port->icount.tx++;
1779 		port->x_char = 0;
1780 		return;
1781 	}
1782 	if (uart_tx_stopped(port)) {
1783 		serial8250_stop_tx(port);
1784 		return;
1785 	}
1786 	if (uart_circ_empty(xmit)) {
1787 		__stop_tx(up);
1788 		return;
1789 	}
1790 
1791 	count = up->tx_loadsz;
1792 	do {
1793 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1794 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1795 		port->icount.tx++;
1796 		if (uart_circ_empty(xmit))
1797 			break;
1798 		if ((up->capabilities & UART_CAP_HFIFO) &&
1799 		    (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1800 			break;
1801 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1802 		if ((up->capabilities & UART_CAP_MINI) &&
1803 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1804 			break;
1805 	} while (--count > 0);
1806 
1807 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1808 		uart_write_wakeup(port);
1809 
1810 	/*
1811 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1812 	 * HW can go idle. So we get here once again with empty FIFO and disable
1813 	 * the interrupt and RPM in __stop_tx()
1814 	 */
1815 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1816 		__stop_tx(up);
1817 }
1818 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1819 
1820 /* Caller holds uart port lock */
1821 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1822 {
1823 	struct uart_port *port = &up->port;
1824 	unsigned int status = serial_in(up, UART_MSR);
1825 
1826 	status |= up->msr_saved_flags;
1827 	up->msr_saved_flags = 0;
1828 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1829 	    port->state != NULL) {
1830 		if (status & UART_MSR_TERI)
1831 			port->icount.rng++;
1832 		if (status & UART_MSR_DDSR)
1833 			port->icount.dsr++;
1834 		if (status & UART_MSR_DDCD)
1835 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1836 		if (status & UART_MSR_DCTS)
1837 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1838 
1839 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1840 	}
1841 
1842 	return status;
1843 }
1844 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1845 
1846 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1847 {
1848 	switch (iir & 0x3f) {
1849 	case UART_IIR_RX_TIMEOUT:
1850 		serial8250_rx_dma_flush(up);
1851 		/* fall-through */
1852 	case UART_IIR_RLSI:
1853 		return true;
1854 	}
1855 	return up->dma->rx_dma(up);
1856 }
1857 
1858 /*
1859  * This handles the interrupt from one port.
1860  */
1861 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1862 {
1863 	unsigned char status;
1864 	unsigned long flags;
1865 	struct uart_8250_port *up = up_to_u8250p(port);
1866 
1867 	if (iir & UART_IIR_NO_INT)
1868 		return 0;
1869 
1870 	spin_lock_irqsave(&port->lock, flags);
1871 
1872 	status = serial_port_in(port, UART_LSR);
1873 
1874 	if (status & (UART_LSR_DR | UART_LSR_BI) &&
1875 	    iir & UART_IIR_RDI) {
1876 		if (!up->dma || handle_rx_dma(up, iir))
1877 			status = serial8250_rx_chars(up, status);
1878 	}
1879 	serial8250_modem_status(up);
1880 	if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1881 		serial8250_tx_chars(up);
1882 
1883 	spin_unlock_irqrestore(&port->lock, flags);
1884 	return 1;
1885 }
1886 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1887 
1888 static int serial8250_default_handle_irq(struct uart_port *port)
1889 {
1890 	struct uart_8250_port *up = up_to_u8250p(port);
1891 	unsigned int iir;
1892 	int ret;
1893 
1894 	serial8250_rpm_get(up);
1895 
1896 	iir = serial_port_in(port, UART_IIR);
1897 	ret = serial8250_handle_irq(port, iir);
1898 
1899 	serial8250_rpm_put(up);
1900 	return ret;
1901 }
1902 
1903 /*
1904  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1905  * have a programmable TX threshold that triggers the THRE interrupt in
1906  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1907  * has space available. Load it up with tx_loadsz bytes.
1908  */
1909 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1910 {
1911 	unsigned long flags;
1912 	unsigned int iir = serial_port_in(port, UART_IIR);
1913 
1914 	/* TX Threshold IRQ triggered so load up FIFO */
1915 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1916 		struct uart_8250_port *up = up_to_u8250p(port);
1917 
1918 		spin_lock_irqsave(&port->lock, flags);
1919 		serial8250_tx_chars(up);
1920 		spin_unlock_irqrestore(&port->lock, flags);
1921 	}
1922 
1923 	iir = serial_port_in(port, UART_IIR);
1924 	return serial8250_handle_irq(port, iir);
1925 }
1926 
1927 static unsigned int serial8250_tx_empty(struct uart_port *port)
1928 {
1929 	struct uart_8250_port *up = up_to_u8250p(port);
1930 	unsigned long flags;
1931 	unsigned int lsr;
1932 
1933 	serial8250_rpm_get(up);
1934 
1935 	spin_lock_irqsave(&port->lock, flags);
1936 	lsr = serial_port_in(port, UART_LSR);
1937 	up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1938 	spin_unlock_irqrestore(&port->lock, flags);
1939 
1940 	serial8250_rpm_put(up);
1941 
1942 	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1943 }
1944 
1945 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1946 {
1947 	struct uart_8250_port *up = up_to_u8250p(port);
1948 	unsigned int status;
1949 	unsigned int ret;
1950 
1951 	serial8250_rpm_get(up);
1952 	status = serial8250_modem_status(up);
1953 	serial8250_rpm_put(up);
1954 
1955 	ret = 0;
1956 	if (status & UART_MSR_DCD)
1957 		ret |= TIOCM_CAR;
1958 	if (status & UART_MSR_RI)
1959 		ret |= TIOCM_RNG;
1960 	if (status & UART_MSR_DSR)
1961 		ret |= TIOCM_DSR;
1962 	if (status & UART_MSR_CTS)
1963 		ret |= TIOCM_CTS;
1964 	return ret;
1965 }
1966 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1967 
1968 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1969 {
1970 	if (port->get_mctrl)
1971 		return port->get_mctrl(port);
1972 	return serial8250_do_get_mctrl(port);
1973 }
1974 
1975 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1976 {
1977 	struct uart_8250_port *up = up_to_u8250p(port);
1978 	unsigned char mcr = 0;
1979 
1980 	if (mctrl & TIOCM_RTS)
1981 		mcr |= UART_MCR_RTS;
1982 	if (mctrl & TIOCM_DTR)
1983 		mcr |= UART_MCR_DTR;
1984 	if (mctrl & TIOCM_OUT1)
1985 		mcr |= UART_MCR_OUT1;
1986 	if (mctrl & TIOCM_OUT2)
1987 		mcr |= UART_MCR_OUT2;
1988 	if (mctrl & TIOCM_LOOP)
1989 		mcr |= UART_MCR_LOOP;
1990 
1991 	mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1992 
1993 	serial8250_out_MCR(up, mcr);
1994 }
1995 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1996 
1997 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1998 {
1999 	if (port->set_mctrl)
2000 		port->set_mctrl(port, mctrl);
2001 	else
2002 		serial8250_do_set_mctrl(port, mctrl);
2003 }
2004 
2005 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2006 {
2007 	struct uart_8250_port *up = up_to_u8250p(port);
2008 	unsigned long flags;
2009 
2010 	serial8250_rpm_get(up);
2011 	spin_lock_irqsave(&port->lock, flags);
2012 	if (break_state == -1)
2013 		up->lcr |= UART_LCR_SBC;
2014 	else
2015 		up->lcr &= ~UART_LCR_SBC;
2016 	serial_port_out(port, UART_LCR, up->lcr);
2017 	spin_unlock_irqrestore(&port->lock, flags);
2018 	serial8250_rpm_put(up);
2019 }
2020 
2021 /*
2022  *	Wait for transmitter & holding register to empty
2023  */
2024 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2025 {
2026 	unsigned int status, tmout = 10000;
2027 
2028 	/* Wait up to 10ms for the character(s) to be sent. */
2029 	for (;;) {
2030 		status = serial_in(up, UART_LSR);
2031 
2032 		up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2033 
2034 		if ((status & bits) == bits)
2035 			break;
2036 		if (--tmout == 0)
2037 			break;
2038 		udelay(1);
2039 		touch_nmi_watchdog();
2040 	}
2041 
2042 	/* Wait up to 1s for flow control if necessary */
2043 	if (up->port.flags & UPF_CONS_FLOW) {
2044 		for (tmout = 1000000; tmout; tmout--) {
2045 			unsigned int msr = serial_in(up, UART_MSR);
2046 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2047 			if (msr & UART_MSR_CTS)
2048 				break;
2049 			udelay(1);
2050 			touch_nmi_watchdog();
2051 		}
2052 	}
2053 }
2054 
2055 #ifdef CONFIG_CONSOLE_POLL
2056 /*
2057  * Console polling routines for writing and reading from the uart while
2058  * in an interrupt or debug context.
2059  */
2060 
2061 static int serial8250_get_poll_char(struct uart_port *port)
2062 {
2063 	struct uart_8250_port *up = up_to_u8250p(port);
2064 	unsigned char lsr;
2065 	int status;
2066 
2067 	serial8250_rpm_get(up);
2068 
2069 	lsr = serial_port_in(port, UART_LSR);
2070 
2071 	if (!(lsr & UART_LSR_DR)) {
2072 		status = NO_POLL_CHAR;
2073 		goto out;
2074 	}
2075 
2076 	status = serial_port_in(port, UART_RX);
2077 out:
2078 	serial8250_rpm_put(up);
2079 	return status;
2080 }
2081 
2082 
2083 static void serial8250_put_poll_char(struct uart_port *port,
2084 			 unsigned char c)
2085 {
2086 	unsigned int ier;
2087 	struct uart_8250_port *up = up_to_u8250p(port);
2088 
2089 	serial8250_rpm_get(up);
2090 	/*
2091 	 *	First save the IER then disable the interrupts
2092 	 */
2093 	ier = serial_port_in(port, UART_IER);
2094 	if (up->capabilities & UART_CAP_UUE)
2095 		serial_port_out(port, UART_IER, UART_IER_UUE);
2096 	else
2097 		serial_port_out(port, UART_IER, 0);
2098 
2099 	wait_for_xmitr(up, BOTH_EMPTY);
2100 	/*
2101 	 *	Send the character out.
2102 	 */
2103 	serial_port_out(port, UART_TX, c);
2104 
2105 	/*
2106 	 *	Finally, wait for transmitter to become empty
2107 	 *	and restore the IER
2108 	 */
2109 	wait_for_xmitr(up, BOTH_EMPTY);
2110 	serial_port_out(port, UART_IER, ier);
2111 	serial8250_rpm_put(up);
2112 }
2113 
2114 #endif /* CONFIG_CONSOLE_POLL */
2115 
2116 int serial8250_do_startup(struct uart_port *port)
2117 {
2118 	struct uart_8250_port *up = up_to_u8250p(port);
2119 	unsigned long flags;
2120 	unsigned char lsr, iir;
2121 	int retval;
2122 
2123 	if (!port->fifosize)
2124 		port->fifosize = uart_config[port->type].fifo_size;
2125 	if (!up->tx_loadsz)
2126 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2127 	if (!up->capabilities)
2128 		up->capabilities = uart_config[port->type].flags;
2129 	up->mcr = 0;
2130 
2131 	if (port->iotype != up->cur_iotype)
2132 		set_io_from_upio(port);
2133 
2134 	serial8250_rpm_get(up);
2135 	if (port->type == PORT_16C950) {
2136 		/* Wake up and initialize UART */
2137 		up->acr = 0;
2138 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2139 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2140 		serial_port_out(port, UART_IER, 0);
2141 		serial_port_out(port, UART_LCR, 0);
2142 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2143 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2144 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2145 		serial_port_out(port, UART_LCR, 0);
2146 	}
2147 
2148 	if (port->type == PORT_DA830) {
2149 		/* Reset the port */
2150 		serial_port_out(port, UART_IER, 0);
2151 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2152 		mdelay(10);
2153 
2154 		/* Enable Tx, Rx and free run mode */
2155 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2156 				UART_DA830_PWREMU_MGMT_UTRST |
2157 				UART_DA830_PWREMU_MGMT_URRST |
2158 				UART_DA830_PWREMU_MGMT_FREE);
2159 	}
2160 
2161 	if (port->type == PORT_NPCM) {
2162 		/*
2163 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2164 		 * register). Enable it, and set TIOC (timeout interrupt
2165 		 * comparator) to be 0x20 for correct operation.
2166 		 */
2167 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2168 	}
2169 
2170 #ifdef CONFIG_SERIAL_8250_RSA
2171 	/*
2172 	 * If this is an RSA port, see if we can kick it up to the
2173 	 * higher speed clock.
2174 	 */
2175 	enable_rsa(up);
2176 #endif
2177 
2178 	if (port->type == PORT_XR17V35X) {
2179 		/*
2180 		 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2181 		 * MCR [7:5] and MSR [7:0]
2182 		 */
2183 		serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2184 
2185 		/*
2186 		 * Make sure all interrups are masked until initialization is
2187 		 * complete and the FIFOs are cleared
2188 		 */
2189 		serial_port_out(port, UART_IER, 0);
2190 	}
2191 
2192 	/*
2193 	 * Clear the FIFO buffers and disable them.
2194 	 * (they will be reenabled in set_termios())
2195 	 */
2196 	serial8250_clear_fifos(up);
2197 
2198 	/*
2199 	 * Clear the interrupt registers.
2200 	 */
2201 	serial_port_in(port, UART_LSR);
2202 	serial_port_in(port, UART_RX);
2203 	serial_port_in(port, UART_IIR);
2204 	serial_port_in(port, UART_MSR);
2205 	if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2206 		serial_port_in(port, UART_EXAR_INT0);
2207 
2208 	/*
2209 	 * At this point, there's no way the LSR could still be 0xff;
2210 	 * if it is, then bail out, because there's likely no UART
2211 	 * here.
2212 	 */
2213 	if (!(port->flags & UPF_BUGGY_UART) &&
2214 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2215 		printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2216 				   serial_index(port));
2217 		retval = -ENODEV;
2218 		goto out;
2219 	}
2220 
2221 	/*
2222 	 * For a XR16C850, we need to set the trigger levels
2223 	 */
2224 	if (port->type == PORT_16850) {
2225 		unsigned char fctr;
2226 
2227 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2228 
2229 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2230 		serial_port_out(port, UART_FCTR,
2231 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2232 		serial_port_out(port, UART_TRG, UART_TRG_96);
2233 		serial_port_out(port, UART_FCTR,
2234 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2235 		serial_port_out(port, UART_TRG, UART_TRG_96);
2236 
2237 		serial_port_out(port, UART_LCR, 0);
2238 	}
2239 
2240 	/*
2241 	 * For the Altera 16550 variants, set TX threshold trigger level.
2242 	 */
2243 	if (((port->type == PORT_ALTR_16550_F32) ||
2244 	     (port->type == PORT_ALTR_16550_F64) ||
2245 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2246 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2247 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2248 			pr_err("ttyS%d TX FIFO Threshold errors, skipping\n",
2249 			       serial_index(port));
2250 		} else {
2251 			serial_port_out(port, UART_ALTR_AFR,
2252 					UART_ALTR_EN_TXFIFO_LW);
2253 			serial_port_out(port, UART_ALTR_TX_LOW,
2254 					port->fifosize - up->tx_loadsz);
2255 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2256 		}
2257 	}
2258 
2259 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2260 		unsigned char iir1;
2261 		/*
2262 		 * Test for UARTs that do not reassert THRE when the
2263 		 * transmitter is idle and the interrupt has already
2264 		 * been cleared.  Real 16550s should always reassert
2265 		 * this interrupt whenever the transmitter is idle and
2266 		 * the interrupt is enabled.  Delays are necessary to
2267 		 * allow register changes to become visible.
2268 		 */
2269 		spin_lock_irqsave(&port->lock, flags);
2270 		if (up->port.irqflags & IRQF_SHARED)
2271 			disable_irq_nosync(port->irq);
2272 
2273 		wait_for_xmitr(up, UART_LSR_THRE);
2274 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2275 		udelay(1); /* allow THRE to set */
2276 		iir1 = serial_port_in(port, UART_IIR);
2277 		serial_port_out(port, UART_IER, 0);
2278 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2279 		udelay(1); /* allow a working UART time to re-assert THRE */
2280 		iir = serial_port_in(port, UART_IIR);
2281 		serial_port_out(port, UART_IER, 0);
2282 
2283 		if (port->irqflags & IRQF_SHARED)
2284 			enable_irq(port->irq);
2285 		spin_unlock_irqrestore(&port->lock, flags);
2286 
2287 		/*
2288 		 * If the interrupt is not reasserted, or we otherwise
2289 		 * don't trust the iir, setup a timer to kick the UART
2290 		 * on a regular basis.
2291 		 */
2292 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2293 		    up->port.flags & UPF_BUG_THRE) {
2294 			up->bugs |= UART_BUG_THRE;
2295 		}
2296 	}
2297 
2298 	retval = up->ops->setup_irq(up);
2299 	if (retval)
2300 		goto out;
2301 
2302 	/*
2303 	 * Now, initialize the UART
2304 	 */
2305 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2306 
2307 	spin_lock_irqsave(&port->lock, flags);
2308 	if (up->port.flags & UPF_FOURPORT) {
2309 		if (!up->port.irq)
2310 			up->port.mctrl |= TIOCM_OUT1;
2311 	} else
2312 		/*
2313 		 * Most PC uarts need OUT2 raised to enable interrupts.
2314 		 */
2315 		if (port->irq)
2316 			up->port.mctrl |= TIOCM_OUT2;
2317 
2318 	serial8250_set_mctrl(port, port->mctrl);
2319 
2320 	/*
2321 	 * Serial over Lan (SoL) hack:
2322 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2323 	 * used for Serial Over Lan.  Those chips take a longer time than a
2324 	 * normal serial device to signalize that a transmission data was
2325 	 * queued. Due to that, the above test generally fails. One solution
2326 	 * would be to delay the reading of iir. However, this is not
2327 	 * reliable, since the timeout is variable. So, let's just don't
2328 	 * test if we receive TX irq.  This way, we'll never enable
2329 	 * UART_BUG_TXEN.
2330 	 */
2331 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2332 		goto dont_test_tx_en;
2333 
2334 	/*
2335 	 * Do a quick test to see if we receive an interrupt when we enable
2336 	 * the TX irq.
2337 	 */
2338 	serial_port_out(port, UART_IER, UART_IER_THRI);
2339 	lsr = serial_port_in(port, UART_LSR);
2340 	iir = serial_port_in(port, UART_IIR);
2341 	serial_port_out(port, UART_IER, 0);
2342 
2343 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2344 		if (!(up->bugs & UART_BUG_TXEN)) {
2345 			up->bugs |= UART_BUG_TXEN;
2346 			pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2347 				 serial_index(port));
2348 		}
2349 	} else {
2350 		up->bugs &= ~UART_BUG_TXEN;
2351 	}
2352 
2353 dont_test_tx_en:
2354 	spin_unlock_irqrestore(&port->lock, flags);
2355 
2356 	/*
2357 	 * Clear the interrupt registers again for luck, and clear the
2358 	 * saved flags to avoid getting false values from polling
2359 	 * routines or the previous session.
2360 	 */
2361 	serial_port_in(port, UART_LSR);
2362 	serial_port_in(port, UART_RX);
2363 	serial_port_in(port, UART_IIR);
2364 	serial_port_in(port, UART_MSR);
2365 	if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2366 		serial_port_in(port, UART_EXAR_INT0);
2367 	up->lsr_saved_flags = 0;
2368 	up->msr_saved_flags = 0;
2369 
2370 	/*
2371 	 * Request DMA channels for both RX and TX.
2372 	 */
2373 	if (up->dma) {
2374 		retval = serial8250_request_dma(up);
2375 		if (retval) {
2376 			pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2377 					    serial_index(port));
2378 			up->dma = NULL;
2379 		}
2380 	}
2381 
2382 	/*
2383 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2384 	 * enable until after the FIFOs are enabled; otherwise, an already-
2385 	 * active sender can swamp the interrupt handler with "too much work".
2386 	 */
2387 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2388 
2389 	if (port->flags & UPF_FOURPORT) {
2390 		unsigned int icp;
2391 		/*
2392 		 * Enable interrupts on the AST Fourport board
2393 		 */
2394 		icp = (port->iobase & 0xfe0) | 0x01f;
2395 		outb_p(0x80, icp);
2396 		inb_p(icp);
2397 	}
2398 	retval = 0;
2399 out:
2400 	serial8250_rpm_put(up);
2401 	return retval;
2402 }
2403 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2404 
2405 static int serial8250_startup(struct uart_port *port)
2406 {
2407 	if (port->startup)
2408 		return port->startup(port);
2409 	return serial8250_do_startup(port);
2410 }
2411 
2412 void serial8250_do_shutdown(struct uart_port *port)
2413 {
2414 	struct uart_8250_port *up = up_to_u8250p(port);
2415 	unsigned long flags;
2416 
2417 	serial8250_rpm_get(up);
2418 	/*
2419 	 * Disable interrupts from this port
2420 	 */
2421 	spin_lock_irqsave(&port->lock, flags);
2422 	up->ier = 0;
2423 	serial_port_out(port, UART_IER, 0);
2424 	spin_unlock_irqrestore(&port->lock, flags);
2425 
2426 	synchronize_irq(port->irq);
2427 
2428 	if (up->dma)
2429 		serial8250_release_dma(up);
2430 
2431 	spin_lock_irqsave(&port->lock, flags);
2432 	if (port->flags & UPF_FOURPORT) {
2433 		/* reset interrupts on the AST Fourport board */
2434 		inb((port->iobase & 0xfe0) | 0x1f);
2435 		port->mctrl |= TIOCM_OUT1;
2436 	} else
2437 		port->mctrl &= ~TIOCM_OUT2;
2438 
2439 	serial8250_set_mctrl(port, port->mctrl);
2440 	spin_unlock_irqrestore(&port->lock, flags);
2441 
2442 	/*
2443 	 * Disable break condition and FIFOs
2444 	 */
2445 	serial_port_out(port, UART_LCR,
2446 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2447 	serial8250_clear_fifos(up);
2448 
2449 #ifdef CONFIG_SERIAL_8250_RSA
2450 	/*
2451 	 * Reset the RSA board back to 115kbps compat mode.
2452 	 */
2453 	disable_rsa(up);
2454 #endif
2455 
2456 	/*
2457 	 * Read data port to reset things, and then unlink from
2458 	 * the IRQ chain.
2459 	 */
2460 	serial_port_in(port, UART_RX);
2461 	serial8250_rpm_put(up);
2462 
2463 	up->ops->release_irq(up);
2464 }
2465 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2466 
2467 static void serial8250_shutdown(struct uart_port *port)
2468 {
2469 	if (port->shutdown)
2470 		port->shutdown(port);
2471 	else
2472 		serial8250_do_shutdown(port);
2473 }
2474 
2475 /*
2476  * XR17V35x UARTs have an extra fractional divisor register (DLD)
2477  * Calculate divisor with extra 4-bit fractional portion
2478  */
2479 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2480 					 unsigned int baud,
2481 					 unsigned int *frac)
2482 {
2483 	struct uart_port *port = &up->port;
2484 	unsigned int quot_16;
2485 
2486 	quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2487 	*frac = quot_16 & 0x0f;
2488 
2489 	return quot_16 >> 4;
2490 }
2491 
2492 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2493 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2494 		unsigned int baud)
2495 {
2496 	struct uart_port *port = &up->port;
2497 
2498 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2499 }
2500 
2501 static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2502 					   unsigned int baud,
2503 					   unsigned int *frac)
2504 {
2505 	struct uart_port *port = &up->port;
2506 	unsigned int quot;
2507 
2508 	/*
2509 	 * Handle magic divisors for baud rates above baud_base on
2510 	 * SMSC SuperIO chips.
2511 	 *
2512 	 */
2513 	if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2514 	    baud == (port->uartclk/4))
2515 		quot = 0x8001;
2516 	else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2517 		 baud == (port->uartclk/8))
2518 		quot = 0x8002;
2519 	else if (up->port.type == PORT_XR17V35X)
2520 		quot = xr17v35x_get_divisor(up, baud, frac);
2521 	else if (up->port.type == PORT_NPCM)
2522 		quot = npcm_get_divisor(up, baud);
2523 	else
2524 		quot = uart_get_divisor(port, baud);
2525 
2526 	/*
2527 	 * Oxford Semi 952 rev B workaround
2528 	 */
2529 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2530 		quot++;
2531 
2532 	return quot;
2533 }
2534 
2535 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2536 					    tcflag_t c_cflag)
2537 {
2538 	unsigned char cval;
2539 
2540 	switch (c_cflag & CSIZE) {
2541 	case CS5:
2542 		cval = UART_LCR_WLEN5;
2543 		break;
2544 	case CS6:
2545 		cval = UART_LCR_WLEN6;
2546 		break;
2547 	case CS7:
2548 		cval = UART_LCR_WLEN7;
2549 		break;
2550 	default:
2551 	case CS8:
2552 		cval = UART_LCR_WLEN8;
2553 		break;
2554 	}
2555 
2556 	if (c_cflag & CSTOPB)
2557 		cval |= UART_LCR_STOP;
2558 	if (c_cflag & PARENB) {
2559 		cval |= UART_LCR_PARITY;
2560 		if (up->bugs & UART_BUG_PARITY)
2561 			up->fifo_bug = true;
2562 	}
2563 	if (!(c_cflag & PARODD))
2564 		cval |= UART_LCR_EPAR;
2565 #ifdef CMSPAR
2566 	if (c_cflag & CMSPAR)
2567 		cval |= UART_LCR_SPAR;
2568 #endif
2569 
2570 	return cval;
2571 }
2572 
2573 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2574 			    unsigned int quot, unsigned int quot_frac)
2575 {
2576 	struct uart_8250_port *up = up_to_u8250p(port);
2577 
2578 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2579 	if (is_omap1510_8250(up)) {
2580 		if (baud == 115200) {
2581 			quot = 1;
2582 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2583 		} else
2584 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2585 	}
2586 
2587 	/*
2588 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2589 	 * otherwise just set DLAB
2590 	 */
2591 	if (up->capabilities & UART_NATSEMI)
2592 		serial_port_out(port, UART_LCR, 0xe0);
2593 	else
2594 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2595 
2596 	serial_dl_write(up, quot);
2597 
2598 	/* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2599 	if (up->port.type == PORT_XR17V35X) {
2600 		/* Preserve bits not related to baudrate; DLD[7:4]. */
2601 		quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2602 		serial_port_out(port, 0x2, quot_frac);
2603 	}
2604 }
2605 
2606 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2607 					     struct ktermios *termios,
2608 					     struct ktermios *old)
2609 {
2610 	/*
2611 	 * Ask the core to calculate the divisor for us.
2612 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2613 	 * slower than nominal still match standard baud rates without
2614 	 * causing transmission errors.
2615 	 */
2616 	return uart_get_baud_rate(port, termios, old,
2617 				  port->uartclk / 16 / UART_DIV_MAX,
2618 				  port->uartclk);
2619 }
2620 
2621 void
2622 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2623 			  struct ktermios *old)
2624 {
2625 	struct uart_8250_port *up = up_to_u8250p(port);
2626 	unsigned char cval;
2627 	unsigned long flags;
2628 	unsigned int baud, quot, frac = 0;
2629 
2630 	if (up->capabilities & UART_CAP_MINI) {
2631 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2632 		if ((termios->c_cflag & CSIZE) == CS5 ||
2633 		    (termios->c_cflag & CSIZE) == CS6)
2634 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2635 	}
2636 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2637 
2638 	baud = serial8250_get_baud_rate(port, termios, old);
2639 	quot = serial8250_get_divisor(up, baud, &frac);
2640 
2641 	/*
2642 	 * Ok, we're now changing the port state.  Do it with
2643 	 * interrupts disabled.
2644 	 */
2645 	serial8250_rpm_get(up);
2646 	spin_lock_irqsave(&port->lock, flags);
2647 
2648 	up->lcr = cval;					/* Save computed LCR */
2649 
2650 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2651 		/* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2652 		if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2653 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2654 			up->fcr |= UART_FCR_TRIGGER_1;
2655 		}
2656 	}
2657 
2658 	/*
2659 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2660 	 * deasserted when the receive FIFO contains more characters than
2661 	 * the trigger, or the MCR RTS bit is cleared.
2662 	 */
2663 	if (up->capabilities & UART_CAP_AFE) {
2664 		up->mcr &= ~UART_MCR_AFE;
2665 		if (termios->c_cflag & CRTSCTS)
2666 			up->mcr |= UART_MCR_AFE;
2667 	}
2668 
2669 	/*
2670 	 * Update the per-port timeout.
2671 	 */
2672 	uart_update_timeout(port, termios->c_cflag, baud);
2673 
2674 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2675 	if (termios->c_iflag & INPCK)
2676 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2677 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2678 		port->read_status_mask |= UART_LSR_BI;
2679 
2680 	/*
2681 	 * Characteres to ignore
2682 	 */
2683 	port->ignore_status_mask = 0;
2684 	if (termios->c_iflag & IGNPAR)
2685 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2686 	if (termios->c_iflag & IGNBRK) {
2687 		port->ignore_status_mask |= UART_LSR_BI;
2688 		/*
2689 		 * If we're ignoring parity and break indicators,
2690 		 * ignore overruns too (for real raw support).
2691 		 */
2692 		if (termios->c_iflag & IGNPAR)
2693 			port->ignore_status_mask |= UART_LSR_OE;
2694 	}
2695 
2696 	/*
2697 	 * ignore all characters if CREAD is not set
2698 	 */
2699 	if ((termios->c_cflag & CREAD) == 0)
2700 		port->ignore_status_mask |= UART_LSR_DR;
2701 
2702 	/*
2703 	 * CTS flow control flag and modem status interrupts
2704 	 */
2705 	up->ier &= ~UART_IER_MSI;
2706 	if (!(up->bugs & UART_BUG_NOMSR) &&
2707 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2708 		up->ier |= UART_IER_MSI;
2709 	if (up->capabilities & UART_CAP_UUE)
2710 		up->ier |= UART_IER_UUE;
2711 	if (up->capabilities & UART_CAP_RTOIE)
2712 		up->ier |= UART_IER_RTOIE;
2713 
2714 	serial_port_out(port, UART_IER, up->ier);
2715 
2716 	if (up->capabilities & UART_CAP_EFR) {
2717 		unsigned char efr = 0;
2718 		/*
2719 		 * TI16C752/Startech hardware flow control.  FIXME:
2720 		 * - TI16C752 requires control thresholds to be set.
2721 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2722 		 */
2723 		if (termios->c_cflag & CRTSCTS)
2724 			efr |= UART_EFR_CTS;
2725 
2726 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2727 		if (port->flags & UPF_EXAR_EFR)
2728 			serial_port_out(port, UART_XR_EFR, efr);
2729 		else
2730 			serial_port_out(port, UART_EFR, efr);
2731 	}
2732 
2733 	serial8250_set_divisor(port, baud, quot, frac);
2734 
2735 	/*
2736 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2737 	 * is written without DLAB set, this mode will be disabled.
2738 	 */
2739 	if (port->type == PORT_16750)
2740 		serial_port_out(port, UART_FCR, up->fcr);
2741 
2742 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2743 	if (port->type != PORT_16750) {
2744 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2745 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2746 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2747 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2748 	}
2749 	serial8250_set_mctrl(port, port->mctrl);
2750 	spin_unlock_irqrestore(&port->lock, flags);
2751 	serial8250_rpm_put(up);
2752 
2753 	/* Don't rewrite B0 */
2754 	if (tty_termios_baud_rate(termios))
2755 		tty_termios_encode_baud_rate(termios, baud, baud);
2756 }
2757 EXPORT_SYMBOL(serial8250_do_set_termios);
2758 
2759 static void
2760 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2761 		       struct ktermios *old)
2762 {
2763 	if (port->set_termios)
2764 		port->set_termios(port, termios, old);
2765 	else
2766 		serial8250_do_set_termios(port, termios, old);
2767 }
2768 
2769 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2770 {
2771 	if (termios->c_line == N_PPS) {
2772 		port->flags |= UPF_HARDPPS_CD;
2773 		spin_lock_irq(&port->lock);
2774 		serial8250_enable_ms(port);
2775 		spin_unlock_irq(&port->lock);
2776 	} else {
2777 		port->flags &= ~UPF_HARDPPS_CD;
2778 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2779 			spin_lock_irq(&port->lock);
2780 			serial8250_disable_ms(port);
2781 			spin_unlock_irq(&port->lock);
2782 		}
2783 	}
2784 }
2785 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2786 
2787 static void
2788 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2789 {
2790 	if (port->set_ldisc)
2791 		port->set_ldisc(port, termios);
2792 	else
2793 		serial8250_do_set_ldisc(port, termios);
2794 }
2795 
2796 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2797 		      unsigned int oldstate)
2798 {
2799 	struct uart_8250_port *p = up_to_u8250p(port);
2800 
2801 	serial8250_set_sleep(p, state != 0);
2802 }
2803 EXPORT_SYMBOL(serial8250_do_pm);
2804 
2805 static void
2806 serial8250_pm(struct uart_port *port, unsigned int state,
2807 	      unsigned int oldstate)
2808 {
2809 	if (port->pm)
2810 		port->pm(port, state, oldstate);
2811 	else
2812 		serial8250_do_pm(port, state, oldstate);
2813 }
2814 
2815 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2816 {
2817 	if (pt->port.mapsize)
2818 		return pt->port.mapsize;
2819 	if (pt->port.iotype == UPIO_AU) {
2820 		if (pt->port.type == PORT_RT2880)
2821 			return 0x100;
2822 		return 0x1000;
2823 	}
2824 	if (is_omap1_8250(pt))
2825 		return 0x16 << pt->port.regshift;
2826 
2827 	return 8 << pt->port.regshift;
2828 }
2829 
2830 /*
2831  * Resource handling.
2832  */
2833 static int serial8250_request_std_resource(struct uart_8250_port *up)
2834 {
2835 	unsigned int size = serial8250_port_size(up);
2836 	struct uart_port *port = &up->port;
2837 	int ret = 0;
2838 
2839 	switch (port->iotype) {
2840 	case UPIO_AU:
2841 	case UPIO_TSI:
2842 	case UPIO_MEM32:
2843 	case UPIO_MEM32BE:
2844 	case UPIO_MEM16:
2845 	case UPIO_MEM:
2846 		if (!port->mapbase)
2847 			break;
2848 
2849 		if (!request_mem_region(port->mapbase, size, "serial")) {
2850 			ret = -EBUSY;
2851 			break;
2852 		}
2853 
2854 		if (port->flags & UPF_IOREMAP) {
2855 			port->membase = ioremap_nocache(port->mapbase, size);
2856 			if (!port->membase) {
2857 				release_mem_region(port->mapbase, size);
2858 				ret = -ENOMEM;
2859 			}
2860 		}
2861 		break;
2862 
2863 	case UPIO_HUB6:
2864 	case UPIO_PORT:
2865 		if (!request_region(port->iobase, size, "serial"))
2866 			ret = -EBUSY;
2867 		break;
2868 	}
2869 	return ret;
2870 }
2871 
2872 static void serial8250_release_std_resource(struct uart_8250_port *up)
2873 {
2874 	unsigned int size = serial8250_port_size(up);
2875 	struct uart_port *port = &up->port;
2876 
2877 	switch (port->iotype) {
2878 	case UPIO_AU:
2879 	case UPIO_TSI:
2880 	case UPIO_MEM32:
2881 	case UPIO_MEM32BE:
2882 	case UPIO_MEM16:
2883 	case UPIO_MEM:
2884 		if (!port->mapbase)
2885 			break;
2886 
2887 		if (port->flags & UPF_IOREMAP) {
2888 			iounmap(port->membase);
2889 			port->membase = NULL;
2890 		}
2891 
2892 		release_mem_region(port->mapbase, size);
2893 		break;
2894 
2895 	case UPIO_HUB6:
2896 	case UPIO_PORT:
2897 		release_region(port->iobase, size);
2898 		break;
2899 	}
2900 }
2901 
2902 static void serial8250_release_port(struct uart_port *port)
2903 {
2904 	struct uart_8250_port *up = up_to_u8250p(port);
2905 
2906 	serial8250_release_std_resource(up);
2907 }
2908 
2909 static int serial8250_request_port(struct uart_port *port)
2910 {
2911 	struct uart_8250_port *up = up_to_u8250p(port);
2912 
2913 	return serial8250_request_std_resource(up);
2914 }
2915 
2916 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2917 {
2918 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
2919 	unsigned char bytes;
2920 
2921 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2922 
2923 	return bytes ? bytes : -EOPNOTSUPP;
2924 }
2925 
2926 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2927 {
2928 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
2929 	int i;
2930 
2931 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2932 		return -EOPNOTSUPP;
2933 
2934 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2935 		if (bytes < conf_type->rxtrig_bytes[i])
2936 			/* Use the nearest lower value */
2937 			return (--i) << UART_FCR_R_TRIG_SHIFT;
2938 	}
2939 
2940 	return UART_FCR_R_TRIG_11;
2941 }
2942 
2943 static int do_get_rxtrig(struct tty_port *port)
2944 {
2945 	struct uart_state *state = container_of(port, struct uart_state, port);
2946 	struct uart_port *uport = state->uart_port;
2947 	struct uart_8250_port *up = up_to_u8250p(uport);
2948 
2949 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2950 		return -EINVAL;
2951 
2952 	return fcr_get_rxtrig_bytes(up);
2953 }
2954 
2955 static int do_serial8250_get_rxtrig(struct tty_port *port)
2956 {
2957 	int rxtrig_bytes;
2958 
2959 	mutex_lock(&port->mutex);
2960 	rxtrig_bytes = do_get_rxtrig(port);
2961 	mutex_unlock(&port->mutex);
2962 
2963 	return rxtrig_bytes;
2964 }
2965 
2966 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2967 	struct device_attribute *attr, char *buf)
2968 {
2969 	struct tty_port *port = dev_get_drvdata(dev);
2970 	int rxtrig_bytes;
2971 
2972 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
2973 	if (rxtrig_bytes < 0)
2974 		return rxtrig_bytes;
2975 
2976 	return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2977 }
2978 
2979 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2980 {
2981 	struct uart_state *state = container_of(port, struct uart_state, port);
2982 	struct uart_port *uport = state->uart_port;
2983 	struct uart_8250_port *up = up_to_u8250p(uport);
2984 	int rxtrig;
2985 
2986 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2987 	    up->fifo_bug)
2988 		return -EINVAL;
2989 
2990 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2991 	if (rxtrig < 0)
2992 		return rxtrig;
2993 
2994 	serial8250_clear_fifos(up);
2995 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
2996 	up->fcr |= (unsigned char)rxtrig;
2997 	serial_out(up, UART_FCR, up->fcr);
2998 	return 0;
2999 }
3000 
3001 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3002 {
3003 	int ret;
3004 
3005 	mutex_lock(&port->mutex);
3006 	ret = do_set_rxtrig(port, bytes);
3007 	mutex_unlock(&port->mutex);
3008 
3009 	return ret;
3010 }
3011 
3012 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3013 	struct device_attribute *attr, const char *buf, size_t count)
3014 {
3015 	struct tty_port *port = dev_get_drvdata(dev);
3016 	unsigned char bytes;
3017 	int ret;
3018 
3019 	if (!count)
3020 		return -EINVAL;
3021 
3022 	ret = kstrtou8(buf, 10, &bytes);
3023 	if (ret < 0)
3024 		return ret;
3025 
3026 	ret = do_serial8250_set_rxtrig(port, bytes);
3027 	if (ret < 0)
3028 		return ret;
3029 
3030 	return count;
3031 }
3032 
3033 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3034 		   serial8250_get_attr_rx_trig_bytes,
3035 		   serial8250_set_attr_rx_trig_bytes);
3036 
3037 static struct attribute *serial8250_dev_attrs[] = {
3038 	&dev_attr_rx_trig_bytes.attr,
3039 	NULL,
3040 	};
3041 
3042 static struct attribute_group serial8250_dev_attr_group = {
3043 	.attrs = serial8250_dev_attrs,
3044 	};
3045 
3046 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3047 {
3048 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3049 
3050 	if (conf_type->rxtrig_bytes[0])
3051 		up->port.attr_group = &serial8250_dev_attr_group;
3052 }
3053 
3054 static void serial8250_config_port(struct uart_port *port, int flags)
3055 {
3056 	struct uart_8250_port *up = up_to_u8250p(port);
3057 	int ret;
3058 
3059 	/*
3060 	 * Find the region that we can probe for.  This in turn
3061 	 * tells us whether we can probe for the type of port.
3062 	 */
3063 	ret = serial8250_request_std_resource(up);
3064 	if (ret < 0)
3065 		return;
3066 
3067 	if (port->iotype != up->cur_iotype)
3068 		set_io_from_upio(port);
3069 
3070 	if (flags & UART_CONFIG_TYPE)
3071 		autoconfig(up);
3072 
3073 	/* if access method is AU, it is a 16550 with a quirk */
3074 	if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3075 		up->bugs |= UART_BUG_NOMSR;
3076 
3077 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3078 	if (port->type == PORT_TEGRA)
3079 		up->bugs |= UART_BUG_NOMSR;
3080 
3081 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3082 		autoconfig_irq(up);
3083 
3084 	if (port->type == PORT_UNKNOWN)
3085 		serial8250_release_std_resource(up);
3086 
3087 	register_dev_spec_attr_grp(up);
3088 	up->fcr = uart_config[up->port.type].fcr;
3089 }
3090 
3091 static int
3092 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3093 {
3094 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3095 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3096 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3097 	    ser->type == PORT_STARTECH)
3098 		return -EINVAL;
3099 	return 0;
3100 }
3101 
3102 static const char *serial8250_type(struct uart_port *port)
3103 {
3104 	int type = port->type;
3105 
3106 	if (type >= ARRAY_SIZE(uart_config))
3107 		type = 0;
3108 	return uart_config[type].name;
3109 }
3110 
3111 static const struct uart_ops serial8250_pops = {
3112 	.tx_empty	= serial8250_tx_empty,
3113 	.set_mctrl	= serial8250_set_mctrl,
3114 	.get_mctrl	= serial8250_get_mctrl,
3115 	.stop_tx	= serial8250_stop_tx,
3116 	.start_tx	= serial8250_start_tx,
3117 	.throttle	= serial8250_throttle,
3118 	.unthrottle	= serial8250_unthrottle,
3119 	.stop_rx	= serial8250_stop_rx,
3120 	.enable_ms	= serial8250_enable_ms,
3121 	.break_ctl	= serial8250_break_ctl,
3122 	.startup	= serial8250_startup,
3123 	.shutdown	= serial8250_shutdown,
3124 	.set_termios	= serial8250_set_termios,
3125 	.set_ldisc	= serial8250_set_ldisc,
3126 	.pm		= serial8250_pm,
3127 	.type		= serial8250_type,
3128 	.release_port	= serial8250_release_port,
3129 	.request_port	= serial8250_request_port,
3130 	.config_port	= serial8250_config_port,
3131 	.verify_port	= serial8250_verify_port,
3132 #ifdef CONFIG_CONSOLE_POLL
3133 	.poll_get_char = serial8250_get_poll_char,
3134 	.poll_put_char = serial8250_put_poll_char,
3135 #endif
3136 };
3137 
3138 void serial8250_init_port(struct uart_8250_port *up)
3139 {
3140 	struct uart_port *port = &up->port;
3141 
3142 	spin_lock_init(&port->lock);
3143 	port->ops = &serial8250_pops;
3144 
3145 	up->cur_iotype = 0xFF;
3146 }
3147 EXPORT_SYMBOL_GPL(serial8250_init_port);
3148 
3149 void serial8250_set_defaults(struct uart_8250_port *up)
3150 {
3151 	struct uart_port *port = &up->port;
3152 
3153 	if (up->port.flags & UPF_FIXED_TYPE) {
3154 		unsigned int type = up->port.type;
3155 
3156 		if (!up->port.fifosize)
3157 			up->port.fifosize = uart_config[type].fifo_size;
3158 		if (!up->tx_loadsz)
3159 			up->tx_loadsz = uart_config[type].tx_loadsz;
3160 		if (!up->capabilities)
3161 			up->capabilities = uart_config[type].flags;
3162 	}
3163 
3164 	set_io_from_upio(port);
3165 
3166 	/* default dma handlers */
3167 	if (up->dma) {
3168 		if (!up->dma->tx_dma)
3169 			up->dma->tx_dma = serial8250_tx_dma;
3170 		if (!up->dma->rx_dma)
3171 			up->dma->rx_dma = serial8250_rx_dma;
3172 	}
3173 }
3174 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3175 
3176 #ifdef CONFIG_SERIAL_8250_CONSOLE
3177 
3178 static void serial8250_console_putchar(struct uart_port *port, int ch)
3179 {
3180 	struct uart_8250_port *up = up_to_u8250p(port);
3181 
3182 	wait_for_xmitr(up, UART_LSR_THRE);
3183 	serial_port_out(port, UART_TX, ch);
3184 }
3185 
3186 /*
3187  *	Restore serial console when h/w power-off detected
3188  */
3189 static void serial8250_console_restore(struct uart_8250_port *up)
3190 {
3191 	struct uart_port *port = &up->port;
3192 	struct ktermios termios;
3193 	unsigned int baud, quot, frac = 0;
3194 
3195 	termios.c_cflag = port->cons->cflag;
3196 	if (port->state->port.tty && termios.c_cflag == 0)
3197 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3198 
3199 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3200 	quot = serial8250_get_divisor(up, baud, &frac);
3201 
3202 	serial8250_set_divisor(port, baud, quot, frac);
3203 	serial_port_out(port, UART_LCR, up->lcr);
3204 	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3205 }
3206 
3207 /*
3208  *	Print a string to the serial port trying not to disturb
3209  *	any possible real use of the port...
3210  *
3211  *	The console_lock must be held when we get here.
3212  */
3213 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3214 			      unsigned int count)
3215 {
3216 	struct uart_port *port = &up->port;
3217 	unsigned long flags;
3218 	unsigned int ier;
3219 	int locked = 1;
3220 
3221 	touch_nmi_watchdog();
3222 
3223 	serial8250_rpm_get(up);
3224 
3225 	if (port->sysrq)
3226 		locked = 0;
3227 	else if (oops_in_progress)
3228 		locked = spin_trylock_irqsave(&port->lock, flags);
3229 	else
3230 		spin_lock_irqsave(&port->lock, flags);
3231 
3232 	/*
3233 	 *	First save the IER then disable the interrupts
3234 	 */
3235 	ier = serial_port_in(port, UART_IER);
3236 
3237 	if (up->capabilities & UART_CAP_UUE)
3238 		serial_port_out(port, UART_IER, UART_IER_UUE);
3239 	else
3240 		serial_port_out(port, UART_IER, 0);
3241 
3242 	/* check scratch reg to see if port powered off during system sleep */
3243 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3244 		serial8250_console_restore(up);
3245 		up->canary = 0;
3246 	}
3247 
3248 	uart_console_write(port, s, count, serial8250_console_putchar);
3249 
3250 	/*
3251 	 *	Finally, wait for transmitter to become empty
3252 	 *	and restore the IER
3253 	 */
3254 	wait_for_xmitr(up, BOTH_EMPTY);
3255 	serial_port_out(port, UART_IER, ier);
3256 
3257 	/*
3258 	 *	The receive handling will happen properly because the
3259 	 *	receive ready bit will still be set; it is not cleared
3260 	 *	on read.  However, modem control will not, we must
3261 	 *	call it if we have saved something in the saved flags
3262 	 *	while processing with interrupts off.
3263 	 */
3264 	if (up->msr_saved_flags)
3265 		serial8250_modem_status(up);
3266 
3267 	if (locked)
3268 		spin_unlock_irqrestore(&port->lock, flags);
3269 	serial8250_rpm_put(up);
3270 }
3271 
3272 static unsigned int probe_baud(struct uart_port *port)
3273 {
3274 	unsigned char lcr, dll, dlm;
3275 	unsigned int quot;
3276 
3277 	lcr = serial_port_in(port, UART_LCR);
3278 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3279 	dll = serial_port_in(port, UART_DLL);
3280 	dlm = serial_port_in(port, UART_DLM);
3281 	serial_port_out(port, UART_LCR, lcr);
3282 
3283 	quot = (dlm << 8) | dll;
3284 	return (port->uartclk / 16) / quot;
3285 }
3286 
3287 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3288 {
3289 	int baud = 9600;
3290 	int bits = 8;
3291 	int parity = 'n';
3292 	int flow = 'n';
3293 
3294 	if (!port->iobase && !port->membase)
3295 		return -ENODEV;
3296 
3297 	if (options)
3298 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3299 	else if (probe)
3300 		baud = probe_baud(port);
3301 
3302 	return uart_set_options(port, port->cons, baud, parity, bits, flow);
3303 }
3304 
3305 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3306 
3307 MODULE_LICENSE("GPL");
3308