1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
34 
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 
38 #include "8250.h"
39 
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR          7
42 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
43 
44 /*
45  * Debugging.
46  */
47 #if 0
48 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
49 #else
50 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
51 #endif
52 
53 #define BOTH_EMPTY	(UART_LSR_TEMT | UART_LSR_THRE)
54 
55 /*
56  * Here we define the default xmit fifo size used for each type of UART.
57  */
58 static const struct serial8250_config uart_config[] = {
59 	[PORT_UNKNOWN] = {
60 		.name		= "unknown",
61 		.fifo_size	= 1,
62 		.tx_loadsz	= 1,
63 	},
64 	[PORT_8250] = {
65 		.name		= "8250",
66 		.fifo_size	= 1,
67 		.tx_loadsz	= 1,
68 	},
69 	[PORT_16450] = {
70 		.name		= "16450",
71 		.fifo_size	= 1,
72 		.tx_loadsz	= 1,
73 	},
74 	[PORT_16550] = {
75 		.name		= "16550",
76 		.fifo_size	= 1,
77 		.tx_loadsz	= 1,
78 	},
79 	[PORT_16550A] = {
80 		.name		= "16550A",
81 		.fifo_size	= 16,
82 		.tx_loadsz	= 16,
83 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 		.rxtrig_bytes	= {1, 4, 8, 14},
85 		.flags		= UART_CAP_FIFO,
86 	},
87 	[PORT_CIRRUS] = {
88 		.name		= "Cirrus",
89 		.fifo_size	= 1,
90 		.tx_loadsz	= 1,
91 	},
92 	[PORT_16650] = {
93 		.name		= "ST16650",
94 		.fifo_size	= 1,
95 		.tx_loadsz	= 1,
96 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
97 	},
98 	[PORT_16650V2] = {
99 		.name		= "ST16650V2",
100 		.fifo_size	= 32,
101 		.tx_loadsz	= 16,
102 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 				  UART_FCR_T_TRIG_00,
104 		.rxtrig_bytes	= {8, 16, 24, 28},
105 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
106 	},
107 	[PORT_16750] = {
108 		.name		= "TI16750",
109 		.fifo_size	= 64,
110 		.tx_loadsz	= 64,
111 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 				  UART_FCR7_64BYTE,
113 		.rxtrig_bytes	= {1, 16, 32, 56},
114 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
115 	},
116 	[PORT_STARTECH] = {
117 		.name		= "Startech",
118 		.fifo_size	= 1,
119 		.tx_loadsz	= 1,
120 	},
121 	[PORT_16C950] = {
122 		.name		= "16C950/954",
123 		.fifo_size	= 128,
124 		.tx_loadsz	= 128,
125 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 		.rxtrig_bytes	= {16, 32, 112, 120},
127 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
129 	},
130 	[PORT_16654] = {
131 		.name		= "ST16654",
132 		.fifo_size	= 64,
133 		.tx_loadsz	= 32,
134 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
135 				  UART_FCR_T_TRIG_10,
136 		.rxtrig_bytes	= {8, 16, 56, 60},
137 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
138 	},
139 	[PORT_16850] = {
140 		.name		= "XR16850",
141 		.fifo_size	= 128,
142 		.tx_loadsz	= 128,
143 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 	},
146 	[PORT_RSA] = {
147 		.name		= "RSA",
148 		.fifo_size	= 2048,
149 		.tx_loadsz	= 2048,
150 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 		.flags		= UART_CAP_FIFO,
152 	},
153 	[PORT_NS16550A] = {
154 		.name		= "NS16550A",
155 		.fifo_size	= 16,
156 		.tx_loadsz	= 16,
157 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
159 	},
160 	[PORT_XSCALE] = {
161 		.name		= "XScale",
162 		.fifo_size	= 32,
163 		.tx_loadsz	= 32,
164 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
166 	},
167 	[PORT_OCTEON] = {
168 		.name		= "OCTEON",
169 		.fifo_size	= 64,
170 		.tx_loadsz	= 64,
171 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 		.flags		= UART_CAP_FIFO,
173 	},
174 	[PORT_AR7] = {
175 		.name		= "AR7",
176 		.fifo_size	= 16,
177 		.tx_loadsz	= 16,
178 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
180 	},
181 	[PORT_U6_16550A] = {
182 		.name		= "U6_16550A",
183 		.fifo_size	= 64,
184 		.tx_loadsz	= 64,
185 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
187 	},
188 	[PORT_TEGRA] = {
189 		.name		= "Tegra",
190 		.fifo_size	= 32,
191 		.tx_loadsz	= 8,
192 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 				  UART_FCR_T_TRIG_01,
194 		.rxtrig_bytes	= {1, 4, 8, 14},
195 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
196 	},
197 	[PORT_XR17D15X] = {
198 		.name		= "XR17D15X",
199 		.fifo_size	= 64,
200 		.tx_loadsz	= 64,
201 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
203 				  UART_CAP_SLEEP,
204 	},
205 	[PORT_XR17V35X] = {
206 		.name		= "XR17V35X",
207 		.fifo_size	= 256,
208 		.tx_loadsz	= 256,
209 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
210 				  UART_FCR_T_TRIG_11,
211 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 				  UART_CAP_SLEEP,
213 	},
214 	[PORT_LPC3220] = {
215 		.name		= "LPC3220",
216 		.fifo_size	= 64,
217 		.tx_loadsz	= 32,
218 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 		.flags		= UART_CAP_FIFO,
221 	},
222 	[PORT_BRCM_TRUMANAGE] = {
223 		.name		= "TruManage",
224 		.fifo_size	= 1,
225 		.tx_loadsz	= 1024,
226 		.flags		= UART_CAP_HFIFO,
227 	},
228 	[PORT_8250_CIR] = {
229 		.name		= "CIR port"
230 	},
231 	[PORT_ALTR_16550_F32] = {
232 		.name		= "Altera 16550 FIFO32",
233 		.fifo_size	= 32,
234 		.tx_loadsz	= 32,
235 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 		.rxtrig_bytes	= {1, 8, 16, 30},
237 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
238 	},
239 	[PORT_ALTR_16550_F64] = {
240 		.name		= "Altera 16550 FIFO64",
241 		.fifo_size	= 64,
242 		.tx_loadsz	= 64,
243 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 		.rxtrig_bytes	= {1, 16, 32, 62},
245 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
246 	},
247 	[PORT_ALTR_16550_F128] = {
248 		.name		= "Altera 16550 FIFO128",
249 		.fifo_size	= 128,
250 		.tx_loadsz	= 128,
251 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 		.rxtrig_bytes	= {1, 32, 64, 126},
253 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
254 	},
255 	/*
256 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 	 * workaround of errata A-008006 which states that tx_loadsz should
258 	 * be configured less than Maximum supported fifo bytes.
259 	 */
260 	[PORT_16550A_FSL64] = {
261 		.name		= "16550A_FSL64",
262 		.fifo_size	= 64,
263 		.tx_loadsz	= 63,
264 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 				  UART_FCR7_64BYTE,
266 		.flags		= UART_CAP_FIFO,
267 	},
268 	[PORT_RT2880] = {
269 		.name		= "Palmchip BK-3103",
270 		.fifo_size	= 16,
271 		.tx_loadsz	= 16,
272 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 		.rxtrig_bytes	= {1, 4, 8, 14},
274 		.flags		= UART_CAP_FIFO,
275 	},
276 	[PORT_DA830] = {
277 		.name		= "TI DA8xx/66AK2x",
278 		.fifo_size	= 16,
279 		.tx_loadsz	= 16,
280 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
281 				  UART_FCR_R_TRIG_10,
282 		.rxtrig_bytes	= {1, 4, 8, 14},
283 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
284 	},
285 	[PORT_MTK_BTIF] = {
286 		.name		= "MediaTek BTIF",
287 		.fifo_size	= 16,
288 		.tx_loadsz	= 16,
289 		.fcr		= UART_FCR_ENABLE_FIFO |
290 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 		.flags		= UART_CAP_FIFO,
292 	},
293 	[PORT_NPCM] = {
294 		.name		= "Nuvoton 16550",
295 		.fifo_size	= 16,
296 		.tx_loadsz	= 16,
297 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 		.rxtrig_bytes	= {1, 4, 8, 14},
300 		.flags		= UART_CAP_FIFO,
301 	},
302 	[PORT_SUNIX] = {
303 		.name		= "Sunix",
304 		.fifo_size	= 128,
305 		.tx_loadsz	= 128,
306 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 		.rxtrig_bytes	= {1, 32, 64, 112},
308 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
309 	},
310 };
311 
312 /* Uart divisor latch read */
313 static int default_serial_dl_read(struct uart_8250_port *up)
314 {
315 	/* Assign these in pieces to truncate any bits above 7.  */
316 	unsigned char dll = serial_in(up, UART_DLL);
317 	unsigned char dlm = serial_in(up, UART_DLM);
318 
319 	return dll | dlm << 8;
320 }
321 
322 /* Uart divisor latch write */
323 static void default_serial_dl_write(struct uart_8250_port *up, int value)
324 {
325 	serial_out(up, UART_DLL, value & 0xff);
326 	serial_out(up, UART_DLM, value >> 8 & 0xff);
327 }
328 
329 #ifdef CONFIG_SERIAL_8250_RT288X
330 
331 /* Au1x00/RT288x UART hardware has a weird register layout */
332 static const s8 au_io_in_map[8] = {
333 	 0,	/* UART_RX  */
334 	 2,	/* UART_IER */
335 	 3,	/* UART_IIR */
336 	 5,	/* UART_LCR */
337 	 6,	/* UART_MCR */
338 	 7,	/* UART_LSR */
339 	 8,	/* UART_MSR */
340 	-1,	/* UART_SCR (unmapped) */
341 };
342 
343 static const s8 au_io_out_map[8] = {
344 	 1,	/* UART_TX  */
345 	 2,	/* UART_IER */
346 	 4,	/* UART_FCR */
347 	 5,	/* UART_LCR */
348 	 6,	/* UART_MCR */
349 	-1,	/* UART_LSR (unmapped) */
350 	-1,	/* UART_MSR (unmapped) */
351 	-1,	/* UART_SCR (unmapped) */
352 };
353 
354 unsigned int au_serial_in(struct uart_port *p, int offset)
355 {
356 	if (offset >= ARRAY_SIZE(au_io_in_map))
357 		return UINT_MAX;
358 	offset = au_io_in_map[offset];
359 	if (offset < 0)
360 		return UINT_MAX;
361 	return __raw_readl(p->membase + (offset << p->regshift));
362 }
363 
364 void au_serial_out(struct uart_port *p, int offset, int value)
365 {
366 	if (offset >= ARRAY_SIZE(au_io_out_map))
367 		return;
368 	offset = au_io_out_map[offset];
369 	if (offset < 0)
370 		return;
371 	__raw_writel(value, p->membase + (offset << p->regshift));
372 }
373 
374 /* Au1x00 haven't got a standard divisor latch */
375 static int au_serial_dl_read(struct uart_8250_port *up)
376 {
377 	return __raw_readl(up->port.membase + 0x28);
378 }
379 
380 static void au_serial_dl_write(struct uart_8250_port *up, int value)
381 {
382 	__raw_writel(value, up->port.membase + 0x28);
383 }
384 
385 #endif
386 
387 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388 {
389 	offset = offset << p->regshift;
390 	outb(p->hub6 - 1 + offset, p->iobase);
391 	return inb(p->iobase + 1);
392 }
393 
394 static void hub6_serial_out(struct uart_port *p, int offset, int value)
395 {
396 	offset = offset << p->regshift;
397 	outb(p->hub6 - 1 + offset, p->iobase);
398 	outb(value, p->iobase + 1);
399 }
400 
401 static unsigned int mem_serial_in(struct uart_port *p, int offset)
402 {
403 	offset = offset << p->regshift;
404 	return readb(p->membase + offset);
405 }
406 
407 static void mem_serial_out(struct uart_port *p, int offset, int value)
408 {
409 	offset = offset << p->regshift;
410 	writeb(value, p->membase + offset);
411 }
412 
413 static void mem16_serial_out(struct uart_port *p, int offset, int value)
414 {
415 	offset = offset << p->regshift;
416 	writew(value, p->membase + offset);
417 }
418 
419 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
420 {
421 	offset = offset << p->regshift;
422 	return readw(p->membase + offset);
423 }
424 
425 static void mem32_serial_out(struct uart_port *p, int offset, int value)
426 {
427 	offset = offset << p->regshift;
428 	writel(value, p->membase + offset);
429 }
430 
431 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
432 {
433 	offset = offset << p->regshift;
434 	return readl(p->membase + offset);
435 }
436 
437 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
438 {
439 	offset = offset << p->regshift;
440 	iowrite32be(value, p->membase + offset);
441 }
442 
443 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
444 {
445 	offset = offset << p->regshift;
446 	return ioread32be(p->membase + offset);
447 }
448 
449 static unsigned int io_serial_in(struct uart_port *p, int offset)
450 {
451 	offset = offset << p->regshift;
452 	return inb(p->iobase + offset);
453 }
454 
455 static void io_serial_out(struct uart_port *p, int offset, int value)
456 {
457 	offset = offset << p->regshift;
458 	outb(value, p->iobase + offset);
459 }
460 
461 static int serial8250_default_handle_irq(struct uart_port *port);
462 
463 static void set_io_from_upio(struct uart_port *p)
464 {
465 	struct uart_8250_port *up = up_to_u8250p(p);
466 
467 	up->dl_read = default_serial_dl_read;
468 	up->dl_write = default_serial_dl_write;
469 
470 	switch (p->iotype) {
471 	case UPIO_HUB6:
472 		p->serial_in = hub6_serial_in;
473 		p->serial_out = hub6_serial_out;
474 		break;
475 
476 	case UPIO_MEM:
477 		p->serial_in = mem_serial_in;
478 		p->serial_out = mem_serial_out;
479 		break;
480 
481 	case UPIO_MEM16:
482 		p->serial_in = mem16_serial_in;
483 		p->serial_out = mem16_serial_out;
484 		break;
485 
486 	case UPIO_MEM32:
487 		p->serial_in = mem32_serial_in;
488 		p->serial_out = mem32_serial_out;
489 		break;
490 
491 	case UPIO_MEM32BE:
492 		p->serial_in = mem32be_serial_in;
493 		p->serial_out = mem32be_serial_out;
494 		break;
495 
496 #ifdef CONFIG_SERIAL_8250_RT288X
497 	case UPIO_AU:
498 		p->serial_in = au_serial_in;
499 		p->serial_out = au_serial_out;
500 		up->dl_read = au_serial_dl_read;
501 		up->dl_write = au_serial_dl_write;
502 		break;
503 #endif
504 
505 	default:
506 		p->serial_in = io_serial_in;
507 		p->serial_out = io_serial_out;
508 		break;
509 	}
510 	/* Remember loaded iotype */
511 	up->cur_iotype = p->iotype;
512 	p->handle_irq = serial8250_default_handle_irq;
513 }
514 
515 static void
516 serial_port_out_sync(struct uart_port *p, int offset, int value)
517 {
518 	switch (p->iotype) {
519 	case UPIO_MEM:
520 	case UPIO_MEM16:
521 	case UPIO_MEM32:
522 	case UPIO_MEM32BE:
523 	case UPIO_AU:
524 		p->serial_out(p, offset, value);
525 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
526 		break;
527 	default:
528 		p->serial_out(p, offset, value);
529 	}
530 }
531 
532 /*
533  * For the 16C950
534  */
535 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
536 {
537 	serial_out(up, UART_SCR, offset);
538 	serial_out(up, UART_ICR, value);
539 }
540 
541 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
542 {
543 	unsigned int value;
544 
545 	serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
546 	serial_out(up, UART_SCR, offset);
547 	value = serial_in(up, UART_ICR);
548 	serial_icr_write(up, UART_ACR, up->acr);
549 
550 	return value;
551 }
552 
553 /*
554  * FIFO support.
555  */
556 static void serial8250_clear_fifos(struct uart_8250_port *p)
557 {
558 	if (p->capabilities & UART_CAP_FIFO) {
559 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
560 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
561 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
562 		serial_out(p, UART_FCR, 0);
563 	}
564 }
565 
566 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
567 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
568 
569 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
570 {
571 	serial8250_clear_fifos(p);
572 	serial_out(p, UART_FCR, p->fcr);
573 }
574 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
575 
576 void serial8250_rpm_get(struct uart_8250_port *p)
577 {
578 	if (!(p->capabilities & UART_CAP_RPM))
579 		return;
580 	pm_runtime_get_sync(p->port.dev);
581 }
582 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
583 
584 void serial8250_rpm_put(struct uart_8250_port *p)
585 {
586 	if (!(p->capabilities & UART_CAP_RPM))
587 		return;
588 	pm_runtime_mark_last_busy(p->port.dev);
589 	pm_runtime_put_autosuspend(p->port.dev);
590 }
591 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
592 
593 /**
594  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
595  *	@p:	uart_8250_port port instance
596  *
597  *	The function is used to start rs485 software emulating on the
598  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
599  *	transmission. The function is idempotent, so it is safe to call it
600  *	multiple times.
601  *
602  *	The caller MUST enable interrupt on empty shift register before
603  *	calling serial8250_em485_init(). This interrupt is not a part of
604  *	8250 standard, but implementation defined.
605  *
606  *	The function is supposed to be called from .rs485_config callback
607  *	or from any other callback protected with p->port.lock spinlock.
608  *
609  *	See also serial8250_em485_destroy()
610  *
611  *	Return 0 - success, -errno - otherwise
612  */
613 static int serial8250_em485_init(struct uart_8250_port *p)
614 {
615 	if (p->em485)
616 		return 0;
617 
618 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
619 	if (!p->em485)
620 		return -ENOMEM;
621 
622 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
623 		     HRTIMER_MODE_REL);
624 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
625 		     HRTIMER_MODE_REL);
626 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
627 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
628 	p->em485->port = p;
629 	p->em485->active_timer = NULL;
630 	p->em485->tx_stopped = true;
631 
632 	p->rs485_stop_tx(p);
633 
634 	return 0;
635 }
636 
637 /**
638  *	serial8250_em485_destroy() - put uart_8250_port into normal state
639  *	@p:	uart_8250_port port instance
640  *
641  *	The function is used to stop rs485 software emulating on the
642  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
643  *	call it multiple times.
644  *
645  *	The function is supposed to be called from .rs485_config callback
646  *	or from any other callback protected with p->port.lock spinlock.
647  *
648  *	See also serial8250_em485_init()
649  */
650 void serial8250_em485_destroy(struct uart_8250_port *p)
651 {
652 	if (!p->em485)
653 		return;
654 
655 	hrtimer_cancel(&p->em485->start_tx_timer);
656 	hrtimer_cancel(&p->em485->stop_tx_timer);
657 
658 	kfree(p->em485);
659 	p->em485 = NULL;
660 }
661 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
662 
663 /**
664  * serial8250_em485_config() - generic ->rs485_config() callback
665  * @port: uart port
666  * @rs485: rs485 settings
667  *
668  * Generic callback usable by 8250 uart drivers to activate rs485 settings
669  * if the uart is incapable of driving RTS as a Transmit Enable signal in
670  * hardware, relying on software emulation instead.
671  */
672 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
673 {
674 	struct uart_8250_port *up = up_to_u8250p(port);
675 
676 	/* pick sane settings if the user hasn't */
677 	if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
678 	    !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
679 		rs485->flags |= SER_RS485_RTS_ON_SEND;
680 		rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
681 	}
682 
683 	/* clamp the delays to [0, 100ms] */
684 	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
685 	rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
686 
687 	memset(rs485->padding, 0, sizeof(rs485->padding));
688 	port->rs485 = *rs485;
689 
690 	gpiod_set_value(port->rs485_term_gpio,
691 			rs485->flags & SER_RS485_TERMINATE_BUS);
692 
693 	/*
694 	 * Both serial8250_em485_init() and serial8250_em485_destroy()
695 	 * are idempotent.
696 	 */
697 	if (rs485->flags & SER_RS485_ENABLED) {
698 		int ret = serial8250_em485_init(up);
699 
700 		if (ret) {
701 			rs485->flags &= ~SER_RS485_ENABLED;
702 			port->rs485.flags &= ~SER_RS485_ENABLED;
703 		}
704 		return ret;
705 	}
706 
707 	serial8250_em485_destroy(up);
708 	return 0;
709 }
710 EXPORT_SYMBOL_GPL(serial8250_em485_config);
711 
712 /*
713  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
714  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
715  * empty and the HW can idle again.
716  */
717 void serial8250_rpm_get_tx(struct uart_8250_port *p)
718 {
719 	unsigned char rpm_active;
720 
721 	if (!(p->capabilities & UART_CAP_RPM))
722 		return;
723 
724 	rpm_active = xchg(&p->rpm_tx_active, 1);
725 	if (rpm_active)
726 		return;
727 	pm_runtime_get_sync(p->port.dev);
728 }
729 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
730 
731 void serial8250_rpm_put_tx(struct uart_8250_port *p)
732 {
733 	unsigned char rpm_active;
734 
735 	if (!(p->capabilities & UART_CAP_RPM))
736 		return;
737 
738 	rpm_active = xchg(&p->rpm_tx_active, 0);
739 	if (!rpm_active)
740 		return;
741 	pm_runtime_mark_last_busy(p->port.dev);
742 	pm_runtime_put_autosuspend(p->port.dev);
743 }
744 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
745 
746 /*
747  * IER sleep support.  UARTs which have EFRs need the "extended
748  * capability" bit enabled.  Note that on XR16C850s, we need to
749  * reset LCR to write to IER.
750  */
751 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
752 {
753 	unsigned char lcr = 0, efr = 0;
754 
755 	serial8250_rpm_get(p);
756 
757 	if (p->capabilities & UART_CAP_SLEEP) {
758 		if (p->capabilities & UART_CAP_EFR) {
759 			lcr = serial_in(p, UART_LCR);
760 			efr = serial_in(p, UART_EFR);
761 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
762 			serial_out(p, UART_EFR, UART_EFR_ECB);
763 			serial_out(p, UART_LCR, 0);
764 		}
765 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
766 		if (p->capabilities & UART_CAP_EFR) {
767 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
768 			serial_out(p, UART_EFR, efr);
769 			serial_out(p, UART_LCR, lcr);
770 		}
771 	}
772 
773 	serial8250_rpm_put(p);
774 }
775 
776 #ifdef CONFIG_SERIAL_8250_RSA
777 /*
778  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
779  * We set the port uart clock rate if we succeed.
780  */
781 static int __enable_rsa(struct uart_8250_port *up)
782 {
783 	unsigned char mode;
784 	int result;
785 
786 	mode = serial_in(up, UART_RSA_MSR);
787 	result = mode & UART_RSA_MSR_FIFO;
788 
789 	if (!result) {
790 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
791 		mode = serial_in(up, UART_RSA_MSR);
792 		result = mode & UART_RSA_MSR_FIFO;
793 	}
794 
795 	if (result)
796 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
797 
798 	return result;
799 }
800 
801 static void enable_rsa(struct uart_8250_port *up)
802 {
803 	if (up->port.type == PORT_RSA) {
804 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
805 			spin_lock_irq(&up->port.lock);
806 			__enable_rsa(up);
807 			spin_unlock_irq(&up->port.lock);
808 		}
809 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
810 			serial_out(up, UART_RSA_FRR, 0);
811 	}
812 }
813 
814 /*
815  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
816  * It is unknown why interrupts were disabled in here.  However,
817  * the caller is expected to preserve this behaviour by grabbing
818  * the spinlock before calling this function.
819  */
820 static void disable_rsa(struct uart_8250_port *up)
821 {
822 	unsigned char mode;
823 	int result;
824 
825 	if (up->port.type == PORT_RSA &&
826 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
827 		spin_lock_irq(&up->port.lock);
828 
829 		mode = serial_in(up, UART_RSA_MSR);
830 		result = !(mode & UART_RSA_MSR_FIFO);
831 
832 		if (!result) {
833 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
834 			mode = serial_in(up, UART_RSA_MSR);
835 			result = !(mode & UART_RSA_MSR_FIFO);
836 		}
837 
838 		if (result)
839 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
840 		spin_unlock_irq(&up->port.lock);
841 	}
842 }
843 #endif /* CONFIG_SERIAL_8250_RSA */
844 
845 /*
846  * This is a quickie test to see how big the FIFO is.
847  * It doesn't work at all the time, more's the pity.
848  */
849 static int size_fifo(struct uart_8250_port *up)
850 {
851 	unsigned char old_fcr, old_mcr, old_lcr;
852 	unsigned short old_dl;
853 	int count;
854 
855 	old_lcr = serial_in(up, UART_LCR);
856 	serial_out(up, UART_LCR, 0);
857 	old_fcr = serial_in(up, UART_FCR);
858 	old_mcr = serial8250_in_MCR(up);
859 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
860 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
861 	serial8250_out_MCR(up, UART_MCR_LOOP);
862 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
863 	old_dl = serial_dl_read(up);
864 	serial_dl_write(up, 0x0001);
865 	serial_out(up, UART_LCR, 0x03);
866 	for (count = 0; count < 256; count++)
867 		serial_out(up, UART_TX, count);
868 	mdelay(20);/* FIXME - schedule_timeout */
869 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
870 	     (count < 256); count++)
871 		serial_in(up, UART_RX);
872 	serial_out(up, UART_FCR, old_fcr);
873 	serial8250_out_MCR(up, old_mcr);
874 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
875 	serial_dl_write(up, old_dl);
876 	serial_out(up, UART_LCR, old_lcr);
877 
878 	return count;
879 }
880 
881 /*
882  * Read UART ID using the divisor method - set DLL and DLM to zero
883  * and the revision will be in DLL and device type in DLM.  We
884  * preserve the device state across this.
885  */
886 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
887 {
888 	unsigned char old_lcr;
889 	unsigned int id, old_dl;
890 
891 	old_lcr = serial_in(p, UART_LCR);
892 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
893 	old_dl = serial_dl_read(p);
894 	serial_dl_write(p, 0);
895 	id = serial_dl_read(p);
896 	serial_dl_write(p, old_dl);
897 
898 	serial_out(p, UART_LCR, old_lcr);
899 
900 	return id;
901 }
902 
903 /*
904  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
905  * When this function is called we know it is at least a StarTech
906  * 16650 V2, but it might be one of several StarTech UARTs, or one of
907  * its clones.  (We treat the broken original StarTech 16650 V1 as a
908  * 16550, and why not?  Startech doesn't seem to even acknowledge its
909  * existence.)
910  *
911  * What evil have men's minds wrought...
912  */
913 static void autoconfig_has_efr(struct uart_8250_port *up)
914 {
915 	unsigned int id1, id2, id3, rev;
916 
917 	/*
918 	 * Everything with an EFR has SLEEP
919 	 */
920 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
921 
922 	/*
923 	 * First we check to see if it's an Oxford Semiconductor UART.
924 	 *
925 	 * If we have to do this here because some non-National
926 	 * Semiconductor clone chips lock up if you try writing to the
927 	 * LSR register (which serial_icr_read does)
928 	 */
929 
930 	/*
931 	 * Check for Oxford Semiconductor 16C950.
932 	 *
933 	 * EFR [4] must be set else this test fails.
934 	 *
935 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
936 	 * claims that it's needed for 952 dual UART's (which are not
937 	 * recommended for new designs).
938 	 */
939 	up->acr = 0;
940 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
941 	serial_out(up, UART_EFR, UART_EFR_ECB);
942 	serial_out(up, UART_LCR, 0x00);
943 	id1 = serial_icr_read(up, UART_ID1);
944 	id2 = serial_icr_read(up, UART_ID2);
945 	id3 = serial_icr_read(up, UART_ID3);
946 	rev = serial_icr_read(up, UART_REV);
947 
948 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
949 
950 	if (id1 == 0x16 && id2 == 0xC9 &&
951 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
952 		up->port.type = PORT_16C950;
953 
954 		/*
955 		 * Enable work around for the Oxford Semiconductor 952 rev B
956 		 * chip which causes it to seriously miscalculate baud rates
957 		 * when DLL is 0.
958 		 */
959 		if (id3 == 0x52 && rev == 0x01)
960 			up->bugs |= UART_BUG_QUOT;
961 		return;
962 	}
963 
964 	/*
965 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
966 	 * reading back DLL and DLM.  The chip type depends on the DLM
967 	 * value read back:
968 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
969 	 *  0x12 - XR16C2850.
970 	 *  0x14 - XR16C854.
971 	 */
972 	id1 = autoconfig_read_divisor_id(up);
973 	DEBUG_AUTOCONF("850id=%04x ", id1);
974 
975 	id2 = id1 >> 8;
976 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
977 		up->port.type = PORT_16850;
978 		return;
979 	}
980 
981 	/*
982 	 * It wasn't an XR16C850.
983 	 *
984 	 * We distinguish between the '654 and the '650 by counting
985 	 * how many bytes are in the FIFO.  I'm using this for now,
986 	 * since that's the technique that was sent to me in the
987 	 * serial driver update, but I'm not convinced this works.
988 	 * I've had problems doing this in the past.  -TYT
989 	 */
990 	if (size_fifo(up) == 64)
991 		up->port.type = PORT_16654;
992 	else
993 		up->port.type = PORT_16650V2;
994 }
995 
996 /*
997  * We detected a chip without a FIFO.  Only two fall into
998  * this category - the original 8250 and the 16450.  The
999  * 16450 has a scratch register (accessible with LCR=0)
1000  */
1001 static void autoconfig_8250(struct uart_8250_port *up)
1002 {
1003 	unsigned char scratch, status1, status2;
1004 
1005 	up->port.type = PORT_8250;
1006 
1007 	scratch = serial_in(up, UART_SCR);
1008 	serial_out(up, UART_SCR, 0xa5);
1009 	status1 = serial_in(up, UART_SCR);
1010 	serial_out(up, UART_SCR, 0x5a);
1011 	status2 = serial_in(up, UART_SCR);
1012 	serial_out(up, UART_SCR, scratch);
1013 
1014 	if (status1 == 0xa5 && status2 == 0x5a)
1015 		up->port.type = PORT_16450;
1016 }
1017 
1018 static int broken_efr(struct uart_8250_port *up)
1019 {
1020 	/*
1021 	 * Exar ST16C2550 "A2" devices incorrectly detect as
1022 	 * having an EFR, and report an ID of 0x0201.  See
1023 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1024 	 */
1025 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1026 		return 1;
1027 
1028 	return 0;
1029 }
1030 
1031 /*
1032  * We know that the chip has FIFOs.  Does it have an EFR?  The
1033  * EFR is located in the same register position as the IIR and
1034  * we know the top two bits of the IIR are currently set.  The
1035  * EFR should contain zero.  Try to read the EFR.
1036  */
1037 static void autoconfig_16550a(struct uart_8250_port *up)
1038 {
1039 	unsigned char status1, status2;
1040 	unsigned int iersave;
1041 
1042 	up->port.type = PORT_16550A;
1043 	up->capabilities |= UART_CAP_FIFO;
1044 
1045 	if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1046 		return;
1047 
1048 	/*
1049 	 * Check for presence of the EFR when DLAB is set.
1050 	 * Only ST16C650V1 UARTs pass this test.
1051 	 */
1052 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1053 	if (serial_in(up, UART_EFR) == 0) {
1054 		serial_out(up, UART_EFR, 0xA8);
1055 		if (serial_in(up, UART_EFR) != 0) {
1056 			DEBUG_AUTOCONF("EFRv1 ");
1057 			up->port.type = PORT_16650;
1058 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1059 		} else {
1060 			serial_out(up, UART_LCR, 0);
1061 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1062 				   UART_FCR7_64BYTE);
1063 			status1 = serial_in(up, UART_IIR) >> 5;
1064 			serial_out(up, UART_FCR, 0);
1065 			serial_out(up, UART_LCR, 0);
1066 
1067 			if (status1 == 7)
1068 				up->port.type = PORT_16550A_FSL64;
1069 			else
1070 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1071 		}
1072 		serial_out(up, UART_EFR, 0);
1073 		return;
1074 	}
1075 
1076 	/*
1077 	 * Maybe it requires 0xbf to be written to the LCR.
1078 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1079 	 */
1080 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1081 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1082 		DEBUG_AUTOCONF("EFRv2 ");
1083 		autoconfig_has_efr(up);
1084 		return;
1085 	}
1086 
1087 	/*
1088 	 * Check for a National Semiconductor SuperIO chip.
1089 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1090 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1091 	 * switch back to bank 2, read it from EXCR1 again and check
1092 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1093 	 */
1094 	serial_out(up, UART_LCR, 0);
1095 	status1 = serial8250_in_MCR(up);
1096 	serial_out(up, UART_LCR, 0xE0);
1097 	status2 = serial_in(up, 0x02); /* EXCR1 */
1098 
1099 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1100 		serial_out(up, UART_LCR, 0);
1101 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1102 		serial_out(up, UART_LCR, 0xE0);
1103 		status2 = serial_in(up, 0x02); /* EXCR1 */
1104 		serial_out(up, UART_LCR, 0);
1105 		serial8250_out_MCR(up, status1);
1106 
1107 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1108 			unsigned short quot;
1109 
1110 			serial_out(up, UART_LCR, 0xE0);
1111 
1112 			quot = serial_dl_read(up);
1113 			quot <<= 3;
1114 
1115 			if (ns16550a_goto_highspeed(up))
1116 				serial_dl_write(up, quot);
1117 
1118 			serial_out(up, UART_LCR, 0);
1119 
1120 			up->port.uartclk = 921600*16;
1121 			up->port.type = PORT_NS16550A;
1122 			up->capabilities |= UART_NATSEMI;
1123 			return;
1124 		}
1125 	}
1126 
1127 	/*
1128 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1129 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1130 	 * Try setting it with and without DLAB set.  Cheap clones
1131 	 * set bit 5 without DLAB set.
1132 	 */
1133 	serial_out(up, UART_LCR, 0);
1134 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1135 	status1 = serial_in(up, UART_IIR) >> 5;
1136 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1137 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1138 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1139 	status2 = serial_in(up, UART_IIR) >> 5;
1140 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1141 	serial_out(up, UART_LCR, 0);
1142 
1143 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1144 
1145 	if (status1 == 6 && status2 == 7) {
1146 		up->port.type = PORT_16750;
1147 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1148 		return;
1149 	}
1150 
1151 	/*
1152 	 * Try writing and reading the UART_IER_UUE bit (b6).
1153 	 * If it works, this is probably one of the Xscale platform's
1154 	 * internal UARTs.
1155 	 * We're going to explicitly set the UUE bit to 0 before
1156 	 * trying to write and read a 1 just to make sure it's not
1157 	 * already a 1 and maybe locked there before we even start start.
1158 	 */
1159 	iersave = serial_in(up, UART_IER);
1160 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1161 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1162 		/*
1163 		 * OK it's in a known zero state, try writing and reading
1164 		 * without disturbing the current state of the other bits.
1165 		 */
1166 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1167 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1168 			/*
1169 			 * It's an Xscale.
1170 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1171 			 */
1172 			DEBUG_AUTOCONF("Xscale ");
1173 			up->port.type = PORT_XSCALE;
1174 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1175 			return;
1176 		}
1177 	} else {
1178 		/*
1179 		 * If we got here we couldn't force the IER_UUE bit to 0.
1180 		 * Log it and continue.
1181 		 */
1182 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1183 	}
1184 	serial_out(up, UART_IER, iersave);
1185 
1186 	/*
1187 	 * We distinguish between 16550A and U6 16550A by counting
1188 	 * how many bytes are in the FIFO.
1189 	 */
1190 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1191 		up->port.type = PORT_U6_16550A;
1192 		up->capabilities |= UART_CAP_AFE;
1193 	}
1194 }
1195 
1196 /*
1197  * This routine is called by rs_init() to initialize a specific serial
1198  * port.  It determines what type of UART chip this serial port is
1199  * using: 8250, 16450, 16550, 16550A.  The important question is
1200  * whether or not this UART is a 16550A or not, since this will
1201  * determine whether or not we can use its FIFO features or not.
1202  */
1203 static void autoconfig(struct uart_8250_port *up)
1204 {
1205 	unsigned char status1, scratch, scratch2, scratch3;
1206 	unsigned char save_lcr, save_mcr;
1207 	struct uart_port *port = &up->port;
1208 	unsigned long flags;
1209 	unsigned int old_capabilities;
1210 
1211 	if (!port->iobase && !port->mapbase && !port->membase)
1212 		return;
1213 
1214 	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1215 		       port->name, port->iobase, port->membase);
1216 
1217 	/*
1218 	 * We really do need global IRQs disabled here - we're going to
1219 	 * be frobbing the chips IRQ enable register to see if it exists.
1220 	 */
1221 	spin_lock_irqsave(&port->lock, flags);
1222 
1223 	up->capabilities = 0;
1224 	up->bugs = 0;
1225 
1226 	if (!(port->flags & UPF_BUGGY_UART)) {
1227 		/*
1228 		 * Do a simple existence test first; if we fail this,
1229 		 * there's no point trying anything else.
1230 		 *
1231 		 * 0x80 is used as a nonsense port to prevent against
1232 		 * false positives due to ISA bus float.  The
1233 		 * assumption is that 0x80 is a non-existent port;
1234 		 * which should be safe since include/asm/io.h also
1235 		 * makes this assumption.
1236 		 *
1237 		 * Note: this is safe as long as MCR bit 4 is clear
1238 		 * and the device is in "PC" mode.
1239 		 */
1240 		scratch = serial_in(up, UART_IER);
1241 		serial_out(up, UART_IER, 0);
1242 #ifdef __i386__
1243 		outb(0xff, 0x080);
1244 #endif
1245 		/*
1246 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1247 		 * 16C754B) allow only to modify them if an EFR bit is set.
1248 		 */
1249 		scratch2 = serial_in(up, UART_IER) & 0x0f;
1250 		serial_out(up, UART_IER, 0x0F);
1251 #ifdef __i386__
1252 		outb(0, 0x080);
1253 #endif
1254 		scratch3 = serial_in(up, UART_IER) & 0x0f;
1255 		serial_out(up, UART_IER, scratch);
1256 		if (scratch2 != 0 || scratch3 != 0x0F) {
1257 			/*
1258 			 * We failed; there's nothing here
1259 			 */
1260 			spin_unlock_irqrestore(&port->lock, flags);
1261 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1262 				       scratch2, scratch3);
1263 			goto out;
1264 		}
1265 	}
1266 
1267 	save_mcr = serial8250_in_MCR(up);
1268 	save_lcr = serial_in(up, UART_LCR);
1269 
1270 	/*
1271 	 * Check to see if a UART is really there.  Certain broken
1272 	 * internal modems based on the Rockwell chipset fail this
1273 	 * test, because they apparently don't implement the loopback
1274 	 * test mode.  So this test is skipped on the COM 1 through
1275 	 * COM 4 ports.  This *should* be safe, since no board
1276 	 * manufacturer would be stupid enough to design a board
1277 	 * that conflicts with COM 1-4 --- we hope!
1278 	 */
1279 	if (!(port->flags & UPF_SKIP_TEST)) {
1280 		serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1281 		status1 = serial_in(up, UART_MSR) & 0xF0;
1282 		serial8250_out_MCR(up, save_mcr);
1283 		if (status1 != 0x90) {
1284 			spin_unlock_irqrestore(&port->lock, flags);
1285 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1286 				       status1);
1287 			goto out;
1288 		}
1289 	}
1290 
1291 	/*
1292 	 * We're pretty sure there's a port here.  Lets find out what
1293 	 * type of port it is.  The IIR top two bits allows us to find
1294 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1295 	 * determines what we test for next.
1296 	 *
1297 	 * We also initialise the EFR (if any) to zero for later.  The
1298 	 * EFR occupies the same register location as the FCR and IIR.
1299 	 */
1300 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1301 	serial_out(up, UART_EFR, 0);
1302 	serial_out(up, UART_LCR, 0);
1303 
1304 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1305 
1306 	/* Assign this as it is to truncate any bits above 7.  */
1307 	scratch = serial_in(up, UART_IIR);
1308 
1309 	switch (scratch >> 6) {
1310 	case 0:
1311 		autoconfig_8250(up);
1312 		break;
1313 	case 1:
1314 		port->type = PORT_UNKNOWN;
1315 		break;
1316 	case 2:
1317 		port->type = PORT_16550;
1318 		break;
1319 	case 3:
1320 		autoconfig_16550a(up);
1321 		break;
1322 	}
1323 
1324 #ifdef CONFIG_SERIAL_8250_RSA
1325 	/*
1326 	 * Only probe for RSA ports if we got the region.
1327 	 */
1328 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1329 	    __enable_rsa(up))
1330 		port->type = PORT_RSA;
1331 #endif
1332 
1333 	serial_out(up, UART_LCR, save_lcr);
1334 
1335 	port->fifosize = uart_config[up->port.type].fifo_size;
1336 	old_capabilities = up->capabilities;
1337 	up->capabilities = uart_config[port->type].flags;
1338 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1339 
1340 	if (port->type == PORT_UNKNOWN)
1341 		goto out_unlock;
1342 
1343 	/*
1344 	 * Reset the UART.
1345 	 */
1346 #ifdef CONFIG_SERIAL_8250_RSA
1347 	if (port->type == PORT_RSA)
1348 		serial_out(up, UART_RSA_FRR, 0);
1349 #endif
1350 	serial8250_out_MCR(up, save_mcr);
1351 	serial8250_clear_fifos(up);
1352 	serial_in(up, UART_RX);
1353 	if (up->capabilities & UART_CAP_UUE)
1354 		serial_out(up, UART_IER, UART_IER_UUE);
1355 	else
1356 		serial_out(up, UART_IER, 0);
1357 
1358 out_unlock:
1359 	spin_unlock_irqrestore(&port->lock, flags);
1360 
1361 	/*
1362 	 * Check if the device is a Fintek F81216A
1363 	 */
1364 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1365 		fintek_8250_probe(up);
1366 
1367 	if (up->capabilities != old_capabilities) {
1368 		dev_warn(port->dev, "detected caps %08x should be %08x\n",
1369 			 old_capabilities, up->capabilities);
1370 	}
1371 out:
1372 	DEBUG_AUTOCONF("iir=%d ", scratch);
1373 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1374 }
1375 
1376 static void autoconfig_irq(struct uart_8250_port *up)
1377 {
1378 	struct uart_port *port = &up->port;
1379 	unsigned char save_mcr, save_ier;
1380 	unsigned char save_ICP = 0;
1381 	unsigned int ICP = 0;
1382 	unsigned long irqs;
1383 	int irq;
1384 
1385 	if (port->flags & UPF_FOURPORT) {
1386 		ICP = (port->iobase & 0xfe0) | 0x1f;
1387 		save_ICP = inb_p(ICP);
1388 		outb_p(0x80, ICP);
1389 		inb_p(ICP);
1390 	}
1391 
1392 	if (uart_console(port))
1393 		console_lock();
1394 
1395 	/* forget possible initially masked and pending IRQ */
1396 	probe_irq_off(probe_irq_on());
1397 	save_mcr = serial8250_in_MCR(up);
1398 	save_ier = serial_in(up, UART_IER);
1399 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1400 
1401 	irqs = probe_irq_on();
1402 	serial8250_out_MCR(up, 0);
1403 	udelay(10);
1404 	if (port->flags & UPF_FOURPORT) {
1405 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1406 	} else {
1407 		serial8250_out_MCR(up,
1408 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1409 	}
1410 	serial_out(up, UART_IER, 0x0f);	/* enable all intrs */
1411 	serial_in(up, UART_LSR);
1412 	serial_in(up, UART_RX);
1413 	serial_in(up, UART_IIR);
1414 	serial_in(up, UART_MSR);
1415 	serial_out(up, UART_TX, 0xFF);
1416 	udelay(20);
1417 	irq = probe_irq_off(irqs);
1418 
1419 	serial8250_out_MCR(up, save_mcr);
1420 	serial_out(up, UART_IER, save_ier);
1421 
1422 	if (port->flags & UPF_FOURPORT)
1423 		outb_p(save_ICP, ICP);
1424 
1425 	if (uart_console(port))
1426 		console_unlock();
1427 
1428 	port->irq = (irq > 0) ? irq : 0;
1429 }
1430 
1431 static void serial8250_stop_rx(struct uart_port *port)
1432 {
1433 	struct uart_8250_port *up = up_to_u8250p(port);
1434 
1435 	serial8250_rpm_get(up);
1436 
1437 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1438 	up->port.read_status_mask &= ~UART_LSR_DR;
1439 	serial_port_out(port, UART_IER, up->ier);
1440 
1441 	serial8250_rpm_put(up);
1442 }
1443 
1444 /**
1445  * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1446  * @p: uart 8250 port
1447  *
1448  * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1449  */
1450 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1451 {
1452 	unsigned char mcr = serial8250_in_MCR(p);
1453 
1454 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1455 		mcr |= UART_MCR_RTS;
1456 	else
1457 		mcr &= ~UART_MCR_RTS;
1458 	serial8250_out_MCR(p, mcr);
1459 
1460 	/*
1461 	 * Empty the RX FIFO, we are not interested in anything
1462 	 * received during the half-duplex transmission.
1463 	 * Enable previously disabled RX interrupts.
1464 	 */
1465 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1466 		serial8250_clear_and_reinit_fifos(p);
1467 
1468 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1469 		serial_port_out(&p->port, UART_IER, p->ier);
1470 	}
1471 }
1472 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1473 
1474 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1475 {
1476 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1477 			stop_tx_timer);
1478 	struct uart_8250_port *p = em485->port;
1479 	unsigned long flags;
1480 
1481 	serial8250_rpm_get(p);
1482 	spin_lock_irqsave(&p->port.lock, flags);
1483 	if (em485->active_timer == &em485->stop_tx_timer) {
1484 		p->rs485_stop_tx(p);
1485 		em485->active_timer = NULL;
1486 		em485->tx_stopped = true;
1487 	}
1488 	spin_unlock_irqrestore(&p->port.lock, flags);
1489 	serial8250_rpm_put(p);
1490 
1491 	return HRTIMER_NORESTART;
1492 }
1493 
1494 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1495 {
1496 	hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1497 }
1498 
1499 static void __stop_tx_rs485(struct uart_8250_port *p)
1500 {
1501 	struct uart_8250_em485 *em485 = p->em485;
1502 
1503 	/*
1504 	 * rs485_stop_tx() is going to set RTS according to config
1505 	 * AND flush RX FIFO if required.
1506 	 */
1507 	if (p->port.rs485.delay_rts_after_send > 0) {
1508 		em485->active_timer = &em485->stop_tx_timer;
1509 		start_hrtimer_ms(&em485->stop_tx_timer,
1510 				   p->port.rs485.delay_rts_after_send);
1511 	} else {
1512 		p->rs485_stop_tx(p);
1513 		em485->active_timer = NULL;
1514 		em485->tx_stopped = true;
1515 	}
1516 }
1517 
1518 static inline void __do_stop_tx(struct uart_8250_port *p)
1519 {
1520 	if (serial8250_clear_THRI(p))
1521 		serial8250_rpm_put_tx(p);
1522 }
1523 
1524 static inline void __stop_tx(struct uart_8250_port *p)
1525 {
1526 	struct uart_8250_em485 *em485 = p->em485;
1527 
1528 	if (em485) {
1529 		unsigned char lsr = serial_in(p, UART_LSR);
1530 		/*
1531 		 * To provide required timeing and allow FIFO transfer,
1532 		 * __stop_tx_rs485() must be called only when both FIFO and
1533 		 * shift register are empty. It is for device driver to enable
1534 		 * interrupt on TEMT.
1535 		 */
1536 		if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1537 			return;
1538 
1539 		__stop_tx_rs485(p);
1540 	}
1541 	__do_stop_tx(p);
1542 }
1543 
1544 static void serial8250_stop_tx(struct uart_port *port)
1545 {
1546 	struct uart_8250_port *up = up_to_u8250p(port);
1547 
1548 	serial8250_rpm_get(up);
1549 	__stop_tx(up);
1550 
1551 	/*
1552 	 * We really want to stop the transmitter from sending.
1553 	 */
1554 	if (port->type == PORT_16C950) {
1555 		up->acr |= UART_ACR_TXDIS;
1556 		serial_icr_write(up, UART_ACR, up->acr);
1557 	}
1558 	serial8250_rpm_put(up);
1559 }
1560 
1561 static inline void __start_tx(struct uart_port *port)
1562 {
1563 	struct uart_8250_port *up = up_to_u8250p(port);
1564 
1565 	if (up->dma && !up->dma->tx_dma(up))
1566 		return;
1567 
1568 	if (serial8250_set_THRI(up)) {
1569 		if (up->bugs & UART_BUG_TXEN) {
1570 			unsigned char lsr;
1571 
1572 			lsr = serial_in(up, UART_LSR);
1573 			up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1574 			if (lsr & UART_LSR_THRE)
1575 				serial8250_tx_chars(up);
1576 		}
1577 	}
1578 
1579 	/*
1580 	 * Re-enable the transmitter if we disabled it.
1581 	 */
1582 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1583 		up->acr &= ~UART_ACR_TXDIS;
1584 		serial_icr_write(up, UART_ACR, up->acr);
1585 	}
1586 }
1587 
1588 /**
1589  * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1590  * @up: uart 8250 port
1591  *
1592  * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1593  * Assumes that setting the RTS bit in the MCR register means RTS is high.
1594  * (Some chips use inverse semantics.)  Further assumes that reception is
1595  * stoppable by disabling the UART_IER_RDI interrupt.  (Some chips set the
1596  * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1597  */
1598 void serial8250_em485_start_tx(struct uart_8250_port *up)
1599 {
1600 	unsigned char mcr = serial8250_in_MCR(up);
1601 
1602 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1603 		serial8250_stop_rx(&up->port);
1604 
1605 	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1606 		mcr |= UART_MCR_RTS;
1607 	else
1608 		mcr &= ~UART_MCR_RTS;
1609 	serial8250_out_MCR(up, mcr);
1610 }
1611 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1612 
1613 static inline void start_tx_rs485(struct uart_port *port)
1614 {
1615 	struct uart_8250_port *up = up_to_u8250p(port);
1616 	struct uart_8250_em485 *em485 = up->em485;
1617 
1618 	em485->active_timer = NULL;
1619 
1620 	if (em485->tx_stopped) {
1621 		em485->tx_stopped = false;
1622 
1623 		up->rs485_start_tx(up);
1624 
1625 		if (up->port.rs485.delay_rts_before_send > 0) {
1626 			em485->active_timer = &em485->start_tx_timer;
1627 			start_hrtimer_ms(&em485->start_tx_timer,
1628 					 up->port.rs485.delay_rts_before_send);
1629 			return;
1630 		}
1631 	}
1632 
1633 	__start_tx(port);
1634 }
1635 
1636 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1637 {
1638 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1639 			start_tx_timer);
1640 	struct uart_8250_port *p = em485->port;
1641 	unsigned long flags;
1642 
1643 	spin_lock_irqsave(&p->port.lock, flags);
1644 	if (em485->active_timer == &em485->start_tx_timer) {
1645 		__start_tx(&p->port);
1646 		em485->active_timer = NULL;
1647 	}
1648 	spin_unlock_irqrestore(&p->port.lock, flags);
1649 
1650 	return HRTIMER_NORESTART;
1651 }
1652 
1653 static void serial8250_start_tx(struct uart_port *port)
1654 {
1655 	struct uart_8250_port *up = up_to_u8250p(port);
1656 	struct uart_8250_em485 *em485 = up->em485;
1657 
1658 	serial8250_rpm_get_tx(up);
1659 
1660 	if (em485 &&
1661 	    em485->active_timer == &em485->start_tx_timer)
1662 		return;
1663 
1664 	if (em485)
1665 		start_tx_rs485(port);
1666 	else
1667 		__start_tx(port);
1668 }
1669 
1670 static void serial8250_throttle(struct uart_port *port)
1671 {
1672 	port->throttle(port);
1673 }
1674 
1675 static void serial8250_unthrottle(struct uart_port *port)
1676 {
1677 	port->unthrottle(port);
1678 }
1679 
1680 static void serial8250_disable_ms(struct uart_port *port)
1681 {
1682 	struct uart_8250_port *up = up_to_u8250p(port);
1683 
1684 	/* no MSR capabilities */
1685 	if (up->bugs & UART_BUG_NOMSR)
1686 		return;
1687 
1688 	mctrl_gpio_disable_ms(up->gpios);
1689 
1690 	up->ier &= ~UART_IER_MSI;
1691 	serial_port_out(port, UART_IER, up->ier);
1692 }
1693 
1694 static void serial8250_enable_ms(struct uart_port *port)
1695 {
1696 	struct uart_8250_port *up = up_to_u8250p(port);
1697 
1698 	/* no MSR capabilities */
1699 	if (up->bugs & UART_BUG_NOMSR)
1700 		return;
1701 
1702 	mctrl_gpio_enable_ms(up->gpios);
1703 
1704 	up->ier |= UART_IER_MSI;
1705 
1706 	serial8250_rpm_get(up);
1707 	serial_port_out(port, UART_IER, up->ier);
1708 	serial8250_rpm_put(up);
1709 }
1710 
1711 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1712 {
1713 	struct uart_port *port = &up->port;
1714 	unsigned char ch;
1715 	char flag = TTY_NORMAL;
1716 
1717 	if (likely(lsr & UART_LSR_DR))
1718 		ch = serial_in(up, UART_RX);
1719 	else
1720 		/*
1721 		 * Intel 82571 has a Serial Over Lan device that will
1722 		 * set UART_LSR_BI without setting UART_LSR_DR when
1723 		 * it receives a break. To avoid reading from the
1724 		 * receive buffer without UART_LSR_DR bit set, we
1725 		 * just force the read character to be 0
1726 		 */
1727 		ch = 0;
1728 
1729 	port->icount.rx++;
1730 
1731 	lsr |= up->lsr_saved_flags;
1732 	up->lsr_saved_flags = 0;
1733 
1734 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1735 		if (lsr & UART_LSR_BI) {
1736 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1737 			port->icount.brk++;
1738 			/*
1739 			 * We do the SysRQ and SAK checking
1740 			 * here because otherwise the break
1741 			 * may get masked by ignore_status_mask
1742 			 * or read_status_mask.
1743 			 */
1744 			if (uart_handle_break(port))
1745 				return;
1746 		} else if (lsr & UART_LSR_PE)
1747 			port->icount.parity++;
1748 		else if (lsr & UART_LSR_FE)
1749 			port->icount.frame++;
1750 		if (lsr & UART_LSR_OE)
1751 			port->icount.overrun++;
1752 
1753 		/*
1754 		 * Mask off conditions which should be ignored.
1755 		 */
1756 		lsr &= port->read_status_mask;
1757 
1758 		if (lsr & UART_LSR_BI) {
1759 			dev_dbg(port->dev, "handling break\n");
1760 			flag = TTY_BREAK;
1761 		} else if (lsr & UART_LSR_PE)
1762 			flag = TTY_PARITY;
1763 		else if (lsr & UART_LSR_FE)
1764 			flag = TTY_FRAME;
1765 	}
1766 	if (uart_prepare_sysrq_char(port, ch))
1767 		return;
1768 
1769 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1770 }
1771 EXPORT_SYMBOL_GPL(serial8250_read_char);
1772 
1773 /*
1774  * serial8250_rx_chars: processes according to the passed in LSR
1775  * value, and returns the remaining LSR bits not handled
1776  * by this Rx routine.
1777  */
1778 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1779 {
1780 	struct uart_port *port = &up->port;
1781 	int max_count = 256;
1782 
1783 	do {
1784 		serial8250_read_char(up, lsr);
1785 		if (--max_count == 0)
1786 			break;
1787 		lsr = serial_in(up, UART_LSR);
1788 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1789 
1790 	tty_flip_buffer_push(&port->state->port);
1791 	return lsr;
1792 }
1793 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1794 
1795 void serial8250_tx_chars(struct uart_8250_port *up)
1796 {
1797 	struct uart_port *port = &up->port;
1798 	struct circ_buf *xmit = &port->state->xmit;
1799 	int count;
1800 
1801 	if (port->x_char) {
1802 		serial_out(up, UART_TX, port->x_char);
1803 		port->icount.tx++;
1804 		port->x_char = 0;
1805 		return;
1806 	}
1807 	if (uart_tx_stopped(port)) {
1808 		serial8250_stop_tx(port);
1809 		return;
1810 	}
1811 	if (uart_circ_empty(xmit)) {
1812 		__stop_tx(up);
1813 		return;
1814 	}
1815 
1816 	count = up->tx_loadsz;
1817 	do {
1818 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1819 		if (up->bugs & UART_BUG_TXRACE) {
1820 			/*
1821 			 * The Aspeed BMC virtual UARTs have a bug where data
1822 			 * may get stuck in the BMC's Tx FIFO from bursts of
1823 			 * writes on the APB interface.
1824 			 *
1825 			 * Delay back-to-back writes by a read cycle to avoid
1826 			 * stalling the VUART. Read a register that won't have
1827 			 * side-effects and discard the result.
1828 			 */
1829 			serial_in(up, UART_SCR);
1830 		}
1831 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1832 		port->icount.tx++;
1833 		if (uart_circ_empty(xmit))
1834 			break;
1835 		if ((up->capabilities & UART_CAP_HFIFO) &&
1836 		    (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1837 			break;
1838 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1839 		if ((up->capabilities & UART_CAP_MINI) &&
1840 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1841 			break;
1842 	} while (--count > 0);
1843 
1844 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1845 		uart_write_wakeup(port);
1846 
1847 	/*
1848 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1849 	 * HW can go idle. So we get here once again with empty FIFO and disable
1850 	 * the interrupt and RPM in __stop_tx()
1851 	 */
1852 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1853 		__stop_tx(up);
1854 }
1855 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1856 
1857 /* Caller holds uart port lock */
1858 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1859 {
1860 	struct uart_port *port = &up->port;
1861 	unsigned int status = serial_in(up, UART_MSR);
1862 
1863 	status |= up->msr_saved_flags;
1864 	up->msr_saved_flags = 0;
1865 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1866 	    port->state != NULL) {
1867 		if (status & UART_MSR_TERI)
1868 			port->icount.rng++;
1869 		if (status & UART_MSR_DDSR)
1870 			port->icount.dsr++;
1871 		if (status & UART_MSR_DDCD)
1872 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1873 		if (status & UART_MSR_DCTS)
1874 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1875 
1876 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1877 	}
1878 
1879 	return status;
1880 }
1881 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1882 
1883 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1884 {
1885 	switch (iir & 0x3f) {
1886 	case UART_IIR_RX_TIMEOUT:
1887 		serial8250_rx_dma_flush(up);
1888 		fallthrough;
1889 	case UART_IIR_RLSI:
1890 		return true;
1891 	}
1892 	return up->dma->rx_dma(up);
1893 }
1894 
1895 /*
1896  * This handles the interrupt from one port.
1897  */
1898 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1899 {
1900 	unsigned char status;
1901 	struct uart_8250_port *up = up_to_u8250p(port);
1902 	bool skip_rx = false;
1903 	unsigned long flags;
1904 
1905 	if (iir & UART_IIR_NO_INT)
1906 		return 0;
1907 
1908 	spin_lock_irqsave(&port->lock, flags);
1909 
1910 	status = serial_port_in(port, UART_LSR);
1911 
1912 	/*
1913 	 * If port is stopped and there are no error conditions in the
1914 	 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1915 	 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1916 	 * control when FIFO occupancy reaches preset threshold, thus
1917 	 * halting RX. This only works when auto HW flow control is
1918 	 * available.
1919 	 */
1920 	if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1921 	    (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1922 	    !(port->read_status_mask & UART_LSR_DR))
1923 		skip_rx = true;
1924 
1925 	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1926 		if (!up->dma || handle_rx_dma(up, iir))
1927 			status = serial8250_rx_chars(up, status);
1928 	}
1929 	serial8250_modem_status(up);
1930 	if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1931 		(up->ier & UART_IER_THRI))
1932 		serial8250_tx_chars(up);
1933 
1934 	uart_unlock_and_check_sysrq_irqrestore(port, flags);
1935 
1936 	return 1;
1937 }
1938 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1939 
1940 static int serial8250_default_handle_irq(struct uart_port *port)
1941 {
1942 	struct uart_8250_port *up = up_to_u8250p(port);
1943 	unsigned int iir;
1944 	int ret;
1945 
1946 	serial8250_rpm_get(up);
1947 
1948 	iir = serial_port_in(port, UART_IIR);
1949 	ret = serial8250_handle_irq(port, iir);
1950 
1951 	serial8250_rpm_put(up);
1952 	return ret;
1953 }
1954 
1955 /*
1956  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1957  * have a programmable TX threshold that triggers the THRE interrupt in
1958  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1959  * has space available. Load it up with tx_loadsz bytes.
1960  */
1961 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1962 {
1963 	unsigned long flags;
1964 	unsigned int iir = serial_port_in(port, UART_IIR);
1965 
1966 	/* TX Threshold IRQ triggered so load up FIFO */
1967 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1968 		struct uart_8250_port *up = up_to_u8250p(port);
1969 
1970 		spin_lock_irqsave(&port->lock, flags);
1971 		serial8250_tx_chars(up);
1972 		spin_unlock_irqrestore(&port->lock, flags);
1973 	}
1974 
1975 	iir = serial_port_in(port, UART_IIR);
1976 	return serial8250_handle_irq(port, iir);
1977 }
1978 
1979 static unsigned int serial8250_tx_empty(struct uart_port *port)
1980 {
1981 	struct uart_8250_port *up = up_to_u8250p(port);
1982 	unsigned long flags;
1983 	unsigned int lsr;
1984 
1985 	serial8250_rpm_get(up);
1986 
1987 	spin_lock_irqsave(&port->lock, flags);
1988 	lsr = serial_port_in(port, UART_LSR);
1989 	up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1990 	spin_unlock_irqrestore(&port->lock, flags);
1991 
1992 	serial8250_rpm_put(up);
1993 
1994 	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1995 }
1996 
1997 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1998 {
1999 	struct uart_8250_port *up = up_to_u8250p(port);
2000 	unsigned int status;
2001 	unsigned int val;
2002 
2003 	serial8250_rpm_get(up);
2004 	status = serial8250_modem_status(up);
2005 	serial8250_rpm_put(up);
2006 
2007 	val = serial8250_MSR_to_TIOCM(status);
2008 	if (up->gpios)
2009 		return mctrl_gpio_get(up->gpios, &val);
2010 
2011 	return val;
2012 }
2013 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2014 
2015 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2016 {
2017 	if (port->get_mctrl)
2018 		return port->get_mctrl(port);
2019 	return serial8250_do_get_mctrl(port);
2020 }
2021 
2022 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2023 {
2024 	struct uart_8250_port *up = up_to_u8250p(port);
2025 	unsigned char mcr;
2026 
2027 	mcr = serial8250_TIOCM_to_MCR(mctrl);
2028 
2029 	mcr |= up->mcr;
2030 
2031 	serial8250_out_MCR(up, mcr);
2032 }
2033 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2034 
2035 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2036 {
2037 	if (port->set_mctrl)
2038 		port->set_mctrl(port, mctrl);
2039 	else
2040 		serial8250_do_set_mctrl(port, mctrl);
2041 }
2042 
2043 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2044 {
2045 	struct uart_8250_port *up = up_to_u8250p(port);
2046 	unsigned long flags;
2047 
2048 	serial8250_rpm_get(up);
2049 	spin_lock_irqsave(&port->lock, flags);
2050 	if (break_state == -1)
2051 		up->lcr |= UART_LCR_SBC;
2052 	else
2053 		up->lcr &= ~UART_LCR_SBC;
2054 	serial_port_out(port, UART_LCR, up->lcr);
2055 	spin_unlock_irqrestore(&port->lock, flags);
2056 	serial8250_rpm_put(up);
2057 }
2058 
2059 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2060 {
2061 	unsigned int status, tmout = 10000;
2062 
2063 	/* Wait up to 10ms for the character(s) to be sent. */
2064 	for (;;) {
2065 		status = serial_in(up, UART_LSR);
2066 
2067 		up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2068 
2069 		if ((status & bits) == bits)
2070 			break;
2071 		if (--tmout == 0)
2072 			break;
2073 		udelay(1);
2074 		touch_nmi_watchdog();
2075 	}
2076 }
2077 
2078 /*
2079  *	Wait for transmitter & holding register to empty
2080  */
2081 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2082 {
2083 	unsigned int tmout;
2084 
2085 	wait_for_lsr(up, bits);
2086 
2087 	/* Wait up to 1s for flow control if necessary */
2088 	if (up->port.flags & UPF_CONS_FLOW) {
2089 		for (tmout = 1000000; tmout; tmout--) {
2090 			unsigned int msr = serial_in(up, UART_MSR);
2091 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2092 			if (msr & UART_MSR_CTS)
2093 				break;
2094 			udelay(1);
2095 			touch_nmi_watchdog();
2096 		}
2097 	}
2098 }
2099 
2100 #ifdef CONFIG_CONSOLE_POLL
2101 /*
2102  * Console polling routines for writing and reading from the uart while
2103  * in an interrupt or debug context.
2104  */
2105 
2106 static int serial8250_get_poll_char(struct uart_port *port)
2107 {
2108 	struct uart_8250_port *up = up_to_u8250p(port);
2109 	unsigned char lsr;
2110 	int status;
2111 
2112 	serial8250_rpm_get(up);
2113 
2114 	lsr = serial_port_in(port, UART_LSR);
2115 
2116 	if (!(lsr & UART_LSR_DR)) {
2117 		status = NO_POLL_CHAR;
2118 		goto out;
2119 	}
2120 
2121 	status = serial_port_in(port, UART_RX);
2122 out:
2123 	serial8250_rpm_put(up);
2124 	return status;
2125 }
2126 
2127 
2128 static void serial8250_put_poll_char(struct uart_port *port,
2129 			 unsigned char c)
2130 {
2131 	unsigned int ier;
2132 	struct uart_8250_port *up = up_to_u8250p(port);
2133 
2134 	serial8250_rpm_get(up);
2135 	/*
2136 	 *	First save the IER then disable the interrupts
2137 	 */
2138 	ier = serial_port_in(port, UART_IER);
2139 	if (up->capabilities & UART_CAP_UUE)
2140 		serial_port_out(port, UART_IER, UART_IER_UUE);
2141 	else
2142 		serial_port_out(port, UART_IER, 0);
2143 
2144 	wait_for_xmitr(up, BOTH_EMPTY);
2145 	/*
2146 	 *	Send the character out.
2147 	 */
2148 	serial_port_out(port, UART_TX, c);
2149 
2150 	/*
2151 	 *	Finally, wait for transmitter to become empty
2152 	 *	and restore the IER
2153 	 */
2154 	wait_for_xmitr(up, BOTH_EMPTY);
2155 	serial_port_out(port, UART_IER, ier);
2156 	serial8250_rpm_put(up);
2157 }
2158 
2159 #endif /* CONFIG_CONSOLE_POLL */
2160 
2161 int serial8250_do_startup(struct uart_port *port)
2162 {
2163 	struct uart_8250_port *up = up_to_u8250p(port);
2164 	unsigned long flags;
2165 	unsigned char lsr, iir;
2166 	int retval;
2167 
2168 	if (!port->fifosize)
2169 		port->fifosize = uart_config[port->type].fifo_size;
2170 	if (!up->tx_loadsz)
2171 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2172 	if (!up->capabilities)
2173 		up->capabilities = uart_config[port->type].flags;
2174 	up->mcr = 0;
2175 
2176 	if (port->iotype != up->cur_iotype)
2177 		set_io_from_upio(port);
2178 
2179 	serial8250_rpm_get(up);
2180 	if (port->type == PORT_16C950) {
2181 		/* Wake up and initialize UART */
2182 		up->acr = 0;
2183 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2184 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2185 		serial_port_out(port, UART_IER, 0);
2186 		serial_port_out(port, UART_LCR, 0);
2187 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2188 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2189 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2190 		serial_port_out(port, UART_LCR, 0);
2191 	}
2192 
2193 	if (port->type == PORT_DA830) {
2194 		/* Reset the port */
2195 		serial_port_out(port, UART_IER, 0);
2196 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2197 		mdelay(10);
2198 
2199 		/* Enable Tx, Rx and free run mode */
2200 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2201 				UART_DA830_PWREMU_MGMT_UTRST |
2202 				UART_DA830_PWREMU_MGMT_URRST |
2203 				UART_DA830_PWREMU_MGMT_FREE);
2204 	}
2205 
2206 	if (port->type == PORT_NPCM) {
2207 		/*
2208 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2209 		 * register). Enable it, and set TIOC (timeout interrupt
2210 		 * comparator) to be 0x20 for correct operation.
2211 		 */
2212 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2213 	}
2214 
2215 #ifdef CONFIG_SERIAL_8250_RSA
2216 	/*
2217 	 * If this is an RSA port, see if we can kick it up to the
2218 	 * higher speed clock.
2219 	 */
2220 	enable_rsa(up);
2221 #endif
2222 
2223 	/*
2224 	 * Clear the FIFO buffers and disable them.
2225 	 * (they will be reenabled in set_termios())
2226 	 */
2227 	serial8250_clear_fifos(up);
2228 
2229 	/*
2230 	 * Clear the interrupt registers.
2231 	 */
2232 	serial_port_in(port, UART_LSR);
2233 	serial_port_in(port, UART_RX);
2234 	serial_port_in(port, UART_IIR);
2235 	serial_port_in(port, UART_MSR);
2236 
2237 	/*
2238 	 * At this point, there's no way the LSR could still be 0xff;
2239 	 * if it is, then bail out, because there's likely no UART
2240 	 * here.
2241 	 */
2242 	if (!(port->flags & UPF_BUGGY_UART) &&
2243 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2244 		dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2245 		retval = -ENODEV;
2246 		goto out;
2247 	}
2248 
2249 	/*
2250 	 * For a XR16C850, we need to set the trigger levels
2251 	 */
2252 	if (port->type == PORT_16850) {
2253 		unsigned char fctr;
2254 
2255 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2256 
2257 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2258 		serial_port_out(port, UART_FCTR,
2259 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2260 		serial_port_out(port, UART_TRG, UART_TRG_96);
2261 		serial_port_out(port, UART_FCTR,
2262 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2263 		serial_port_out(port, UART_TRG, UART_TRG_96);
2264 
2265 		serial_port_out(port, UART_LCR, 0);
2266 	}
2267 
2268 	/*
2269 	 * For the Altera 16550 variants, set TX threshold trigger level.
2270 	 */
2271 	if (((port->type == PORT_ALTR_16550_F32) ||
2272 	     (port->type == PORT_ALTR_16550_F64) ||
2273 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2274 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2275 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2276 			dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2277 		} else {
2278 			serial_port_out(port, UART_ALTR_AFR,
2279 					UART_ALTR_EN_TXFIFO_LW);
2280 			serial_port_out(port, UART_ALTR_TX_LOW,
2281 					port->fifosize - up->tx_loadsz);
2282 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2283 		}
2284 	}
2285 
2286 	/* Check if we need to have shared IRQs */
2287 	if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2288 		up->port.irqflags |= IRQF_SHARED;
2289 
2290 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2291 		unsigned char iir1;
2292 
2293 		if (port->irqflags & IRQF_SHARED)
2294 			disable_irq_nosync(port->irq);
2295 
2296 		/*
2297 		 * Test for UARTs that do not reassert THRE when the
2298 		 * transmitter is idle and the interrupt has already
2299 		 * been cleared.  Real 16550s should always reassert
2300 		 * this interrupt whenever the transmitter is idle and
2301 		 * the interrupt is enabled.  Delays are necessary to
2302 		 * allow register changes to become visible.
2303 		 */
2304 		spin_lock_irqsave(&port->lock, flags);
2305 
2306 		wait_for_xmitr(up, UART_LSR_THRE);
2307 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2308 		udelay(1); /* allow THRE to set */
2309 		iir1 = serial_port_in(port, UART_IIR);
2310 		serial_port_out(port, UART_IER, 0);
2311 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2312 		udelay(1); /* allow a working UART time to re-assert THRE */
2313 		iir = serial_port_in(port, UART_IIR);
2314 		serial_port_out(port, UART_IER, 0);
2315 
2316 		spin_unlock_irqrestore(&port->lock, flags);
2317 
2318 		if (port->irqflags & IRQF_SHARED)
2319 			enable_irq(port->irq);
2320 
2321 		/*
2322 		 * If the interrupt is not reasserted, or we otherwise
2323 		 * don't trust the iir, setup a timer to kick the UART
2324 		 * on a regular basis.
2325 		 */
2326 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2327 		    up->port.flags & UPF_BUG_THRE) {
2328 			up->bugs |= UART_BUG_THRE;
2329 		}
2330 	}
2331 
2332 	retval = up->ops->setup_irq(up);
2333 	if (retval)
2334 		goto out;
2335 
2336 	/*
2337 	 * Now, initialize the UART
2338 	 */
2339 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2340 
2341 	spin_lock_irqsave(&port->lock, flags);
2342 	if (up->port.flags & UPF_FOURPORT) {
2343 		if (!up->port.irq)
2344 			up->port.mctrl |= TIOCM_OUT1;
2345 	} else
2346 		/*
2347 		 * Most PC uarts need OUT2 raised to enable interrupts.
2348 		 */
2349 		if (port->irq)
2350 			up->port.mctrl |= TIOCM_OUT2;
2351 
2352 	serial8250_set_mctrl(port, port->mctrl);
2353 
2354 	/*
2355 	 * Serial over Lan (SoL) hack:
2356 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2357 	 * used for Serial Over Lan.  Those chips take a longer time than a
2358 	 * normal serial device to signalize that a transmission data was
2359 	 * queued. Due to that, the above test generally fails. One solution
2360 	 * would be to delay the reading of iir. However, this is not
2361 	 * reliable, since the timeout is variable. So, let's just don't
2362 	 * test if we receive TX irq.  This way, we'll never enable
2363 	 * UART_BUG_TXEN.
2364 	 */
2365 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2366 		goto dont_test_tx_en;
2367 
2368 	/*
2369 	 * Do a quick test to see if we receive an interrupt when we enable
2370 	 * the TX irq.
2371 	 */
2372 	serial_port_out(port, UART_IER, UART_IER_THRI);
2373 	lsr = serial_port_in(port, UART_LSR);
2374 	iir = serial_port_in(port, UART_IIR);
2375 	serial_port_out(port, UART_IER, 0);
2376 
2377 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2378 		if (!(up->bugs & UART_BUG_TXEN)) {
2379 			up->bugs |= UART_BUG_TXEN;
2380 			dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2381 		}
2382 	} else {
2383 		up->bugs &= ~UART_BUG_TXEN;
2384 	}
2385 
2386 dont_test_tx_en:
2387 	spin_unlock_irqrestore(&port->lock, flags);
2388 
2389 	/*
2390 	 * Clear the interrupt registers again for luck, and clear the
2391 	 * saved flags to avoid getting false values from polling
2392 	 * routines or the previous session.
2393 	 */
2394 	serial_port_in(port, UART_LSR);
2395 	serial_port_in(port, UART_RX);
2396 	serial_port_in(port, UART_IIR);
2397 	serial_port_in(port, UART_MSR);
2398 	up->lsr_saved_flags = 0;
2399 	up->msr_saved_flags = 0;
2400 
2401 	/*
2402 	 * Request DMA channels for both RX and TX.
2403 	 */
2404 	if (up->dma) {
2405 		const char *msg = NULL;
2406 
2407 		if (uart_console(port))
2408 			msg = "forbid DMA for kernel console";
2409 		else if (serial8250_request_dma(up))
2410 			msg = "failed to request DMA";
2411 		if (msg) {
2412 			dev_warn_ratelimited(port->dev, "%s\n", msg);
2413 			up->dma = NULL;
2414 		}
2415 	}
2416 
2417 	/*
2418 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2419 	 * enable until after the FIFOs are enabled; otherwise, an already-
2420 	 * active sender can swamp the interrupt handler with "too much work".
2421 	 */
2422 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2423 
2424 	if (port->flags & UPF_FOURPORT) {
2425 		unsigned int icp;
2426 		/*
2427 		 * Enable interrupts on the AST Fourport board
2428 		 */
2429 		icp = (port->iobase & 0xfe0) | 0x01f;
2430 		outb_p(0x80, icp);
2431 		inb_p(icp);
2432 	}
2433 	retval = 0;
2434 out:
2435 	serial8250_rpm_put(up);
2436 	return retval;
2437 }
2438 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2439 
2440 static int serial8250_startup(struct uart_port *port)
2441 {
2442 	if (port->startup)
2443 		return port->startup(port);
2444 	return serial8250_do_startup(port);
2445 }
2446 
2447 void serial8250_do_shutdown(struct uart_port *port)
2448 {
2449 	struct uart_8250_port *up = up_to_u8250p(port);
2450 	unsigned long flags;
2451 
2452 	serial8250_rpm_get(up);
2453 	/*
2454 	 * Disable interrupts from this port
2455 	 */
2456 	spin_lock_irqsave(&port->lock, flags);
2457 	up->ier = 0;
2458 	serial_port_out(port, UART_IER, 0);
2459 	spin_unlock_irqrestore(&port->lock, flags);
2460 
2461 	synchronize_irq(port->irq);
2462 
2463 	if (up->dma)
2464 		serial8250_release_dma(up);
2465 
2466 	spin_lock_irqsave(&port->lock, flags);
2467 	if (port->flags & UPF_FOURPORT) {
2468 		/* reset interrupts on the AST Fourport board */
2469 		inb((port->iobase & 0xfe0) | 0x1f);
2470 		port->mctrl |= TIOCM_OUT1;
2471 	} else
2472 		port->mctrl &= ~TIOCM_OUT2;
2473 
2474 	serial8250_set_mctrl(port, port->mctrl);
2475 	spin_unlock_irqrestore(&port->lock, flags);
2476 
2477 	/*
2478 	 * Disable break condition and FIFOs
2479 	 */
2480 	serial_port_out(port, UART_LCR,
2481 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2482 	serial8250_clear_fifos(up);
2483 
2484 #ifdef CONFIG_SERIAL_8250_RSA
2485 	/*
2486 	 * Reset the RSA board back to 115kbps compat mode.
2487 	 */
2488 	disable_rsa(up);
2489 #endif
2490 
2491 	/*
2492 	 * Read data port to reset things, and then unlink from
2493 	 * the IRQ chain.
2494 	 */
2495 	serial_port_in(port, UART_RX);
2496 	serial8250_rpm_put(up);
2497 
2498 	up->ops->release_irq(up);
2499 }
2500 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2501 
2502 static void serial8250_shutdown(struct uart_port *port)
2503 {
2504 	if (port->shutdown)
2505 		port->shutdown(port);
2506 	else
2507 		serial8250_do_shutdown(port);
2508 }
2509 
2510 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2511 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2512 		unsigned int baud)
2513 {
2514 	struct uart_port *port = &up->port;
2515 
2516 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2517 }
2518 
2519 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2520 					      unsigned int baud,
2521 					      unsigned int *frac)
2522 {
2523 	upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2524 	struct uart_8250_port *up = up_to_u8250p(port);
2525 	unsigned int quot;
2526 
2527 	/*
2528 	 * Handle magic divisors for baud rates above baud_base on SMSC
2529 	 * Super I/O chips.  We clamp custom rates from clk/6 and clk/12
2530 	 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively.  These
2531 	 * magic divisors actually reprogram the baud rate generator's
2532 	 * reference clock derived from chips's 14.318MHz clock input.
2533 	 *
2534 	 * Documentation claims that with these magic divisors the base
2535 	 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2536 	 * for the extra baud rates of 460800bps and 230400bps rather
2537 	 * than the usual base frequency of 1.8462MHz.  However empirical
2538 	 * evidence contradicts that.
2539 	 *
2540 	 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2541 	 * effectively used as a clock prescaler selection bit for the
2542 	 * base frequency of 7.3728MHz, always used.  If set to 0, then
2543 	 * the base frequency is divided by 4 for use by the Baud Rate
2544 	 * Generator, for the usual arrangement where the value of 1 of
2545 	 * the divisor produces the baud rate of 115200bps.  Conversely,
2546 	 * if set to 1 and high-speed operation has been enabled with the
2547 	 * Serial Port Mode Register in the Device Configuration Space,
2548 	 * then the base frequency is supplied directly to the Baud Rate
2549 	 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2550 	 * 0x8004, etc. the respective baud rates produced are 460800bps,
2551 	 * 230400bps, 153600bps, 115200bps, etc.
2552 	 *
2553 	 * In all cases only low 15 bits of the divisor are used to divide
2554 	 * the baud base and therefore 32767 is the maximum divisor value
2555 	 * possible, even though documentation says that the programmable
2556 	 * Baud Rate Generator is capable of dividing the internal PLL
2557 	 * clock by any divisor from 1 to 65535.
2558 	 */
2559 	if (magic_multiplier && baud >= port->uartclk / 6)
2560 		quot = 0x8001;
2561 	else if (magic_multiplier && baud >= port->uartclk / 12)
2562 		quot = 0x8002;
2563 	else if (up->port.type == PORT_NPCM)
2564 		quot = npcm_get_divisor(up, baud);
2565 	else
2566 		quot = uart_get_divisor(port, baud);
2567 
2568 	/*
2569 	 * Oxford Semi 952 rev B workaround
2570 	 */
2571 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2572 		quot++;
2573 
2574 	return quot;
2575 }
2576 
2577 static unsigned int serial8250_get_divisor(struct uart_port *port,
2578 					   unsigned int baud,
2579 					   unsigned int *frac)
2580 {
2581 	if (port->get_divisor)
2582 		return port->get_divisor(port, baud, frac);
2583 
2584 	return serial8250_do_get_divisor(port, baud, frac);
2585 }
2586 
2587 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2588 					    tcflag_t c_cflag)
2589 {
2590 	unsigned char cval;
2591 
2592 	switch (c_cflag & CSIZE) {
2593 	case CS5:
2594 		cval = UART_LCR_WLEN5;
2595 		break;
2596 	case CS6:
2597 		cval = UART_LCR_WLEN6;
2598 		break;
2599 	case CS7:
2600 		cval = UART_LCR_WLEN7;
2601 		break;
2602 	default:
2603 	case CS8:
2604 		cval = UART_LCR_WLEN8;
2605 		break;
2606 	}
2607 
2608 	if (c_cflag & CSTOPB)
2609 		cval |= UART_LCR_STOP;
2610 	if (c_cflag & PARENB) {
2611 		cval |= UART_LCR_PARITY;
2612 		if (up->bugs & UART_BUG_PARITY)
2613 			up->fifo_bug = true;
2614 	}
2615 	if (!(c_cflag & PARODD))
2616 		cval |= UART_LCR_EPAR;
2617 #ifdef CMSPAR
2618 	if (c_cflag & CMSPAR)
2619 		cval |= UART_LCR_SPAR;
2620 #endif
2621 
2622 	return cval;
2623 }
2624 
2625 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2626 			       unsigned int quot, unsigned int quot_frac)
2627 {
2628 	struct uart_8250_port *up = up_to_u8250p(port);
2629 
2630 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2631 	if (is_omap1510_8250(up)) {
2632 		if (baud == 115200) {
2633 			quot = 1;
2634 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2635 		} else
2636 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2637 	}
2638 
2639 	/*
2640 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2641 	 * otherwise just set DLAB
2642 	 */
2643 	if (up->capabilities & UART_NATSEMI)
2644 		serial_port_out(port, UART_LCR, 0xe0);
2645 	else
2646 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2647 
2648 	serial_dl_write(up, quot);
2649 }
2650 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2651 
2652 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2653 				   unsigned int quot, unsigned int quot_frac)
2654 {
2655 	if (port->set_divisor)
2656 		port->set_divisor(port, baud, quot, quot_frac);
2657 	else
2658 		serial8250_do_set_divisor(port, baud, quot, quot_frac);
2659 }
2660 
2661 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2662 					     struct ktermios *termios,
2663 					     struct ktermios *old)
2664 {
2665 	unsigned int tolerance = port->uartclk / 100;
2666 	unsigned int min;
2667 	unsigned int max;
2668 
2669 	/*
2670 	 * Handle magic divisors for baud rates above baud_base on SMSC
2671 	 * Super I/O chips.  Enable custom rates of clk/4 and clk/8, but
2672 	 * disable divisor values beyond 32767, which are unavailable.
2673 	 */
2674 	if (port->flags & UPF_MAGIC_MULTIPLIER) {
2675 		min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2676 		max = (port->uartclk + tolerance) / 4;
2677 	} else {
2678 		min = port->uartclk / 16 / UART_DIV_MAX;
2679 		max = (port->uartclk + tolerance) / 16;
2680 	}
2681 
2682 	/*
2683 	 * Ask the core to calculate the divisor for us.
2684 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2685 	 * slower than nominal still match standard baud rates without
2686 	 * causing transmission errors.
2687 	 */
2688 	return uart_get_baud_rate(port, termios, old, min, max);
2689 }
2690 
2691 /*
2692  * Note in order to avoid the tty port mutex deadlock don't use the next method
2693  * within the uart port callbacks. Primarily it's supposed to be utilized to
2694  * handle a sudden reference clock rate change.
2695  */
2696 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2697 {
2698 	struct uart_8250_port *up = up_to_u8250p(port);
2699 	struct tty_port *tport = &port->state->port;
2700 	unsigned int baud, quot, frac = 0;
2701 	struct ktermios *termios;
2702 	struct tty_struct *tty;
2703 	unsigned long flags;
2704 
2705 	tty = tty_port_tty_get(tport);
2706 	if (!tty) {
2707 		mutex_lock(&tport->mutex);
2708 		port->uartclk = uartclk;
2709 		mutex_unlock(&tport->mutex);
2710 		return;
2711 	}
2712 
2713 	down_write(&tty->termios_rwsem);
2714 	mutex_lock(&tport->mutex);
2715 
2716 	if (port->uartclk == uartclk)
2717 		goto out_unlock;
2718 
2719 	port->uartclk = uartclk;
2720 
2721 	if (!tty_port_initialized(tport))
2722 		goto out_unlock;
2723 
2724 	termios = &tty->termios;
2725 
2726 	baud = serial8250_get_baud_rate(port, termios, NULL);
2727 	quot = serial8250_get_divisor(port, baud, &frac);
2728 
2729 	serial8250_rpm_get(up);
2730 	spin_lock_irqsave(&port->lock, flags);
2731 
2732 	uart_update_timeout(port, termios->c_cflag, baud);
2733 
2734 	serial8250_set_divisor(port, baud, quot, frac);
2735 	serial_port_out(port, UART_LCR, up->lcr);
2736 
2737 	spin_unlock_irqrestore(&port->lock, flags);
2738 	serial8250_rpm_put(up);
2739 
2740 out_unlock:
2741 	mutex_unlock(&tport->mutex);
2742 	up_write(&tty->termios_rwsem);
2743 	tty_kref_put(tty);
2744 }
2745 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2746 
2747 void
2748 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2749 			  struct ktermios *old)
2750 {
2751 	struct uart_8250_port *up = up_to_u8250p(port);
2752 	unsigned char cval;
2753 	unsigned long flags;
2754 	unsigned int baud, quot, frac = 0;
2755 
2756 	if (up->capabilities & UART_CAP_MINI) {
2757 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2758 		if ((termios->c_cflag & CSIZE) == CS5 ||
2759 		    (termios->c_cflag & CSIZE) == CS6)
2760 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2761 	}
2762 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2763 
2764 	baud = serial8250_get_baud_rate(port, termios, old);
2765 	quot = serial8250_get_divisor(port, baud, &frac);
2766 
2767 	/*
2768 	 * Ok, we're now changing the port state.  Do it with
2769 	 * interrupts disabled.
2770 	 */
2771 	serial8250_rpm_get(up);
2772 	spin_lock_irqsave(&port->lock, flags);
2773 
2774 	up->lcr = cval;					/* Save computed LCR */
2775 
2776 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2777 		/* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2778 		if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2779 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2780 			up->fcr |= UART_FCR_TRIGGER_1;
2781 		}
2782 	}
2783 
2784 	/*
2785 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2786 	 * deasserted when the receive FIFO contains more characters than
2787 	 * the trigger, or the MCR RTS bit is cleared.
2788 	 */
2789 	if (up->capabilities & UART_CAP_AFE) {
2790 		up->mcr &= ~UART_MCR_AFE;
2791 		if (termios->c_cflag & CRTSCTS)
2792 			up->mcr |= UART_MCR_AFE;
2793 	}
2794 
2795 	/*
2796 	 * Update the per-port timeout.
2797 	 */
2798 	uart_update_timeout(port, termios->c_cflag, baud);
2799 
2800 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2801 	if (termios->c_iflag & INPCK)
2802 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2803 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2804 		port->read_status_mask |= UART_LSR_BI;
2805 
2806 	/*
2807 	 * Characteres to ignore
2808 	 */
2809 	port->ignore_status_mask = 0;
2810 	if (termios->c_iflag & IGNPAR)
2811 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2812 	if (termios->c_iflag & IGNBRK) {
2813 		port->ignore_status_mask |= UART_LSR_BI;
2814 		/*
2815 		 * If we're ignoring parity and break indicators,
2816 		 * ignore overruns too (for real raw support).
2817 		 */
2818 		if (termios->c_iflag & IGNPAR)
2819 			port->ignore_status_mask |= UART_LSR_OE;
2820 	}
2821 
2822 	/*
2823 	 * ignore all characters if CREAD is not set
2824 	 */
2825 	if ((termios->c_cflag & CREAD) == 0)
2826 		port->ignore_status_mask |= UART_LSR_DR;
2827 
2828 	/*
2829 	 * CTS flow control flag and modem status interrupts
2830 	 */
2831 	up->ier &= ~UART_IER_MSI;
2832 	if (!(up->bugs & UART_BUG_NOMSR) &&
2833 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2834 		up->ier |= UART_IER_MSI;
2835 	if (up->capabilities & UART_CAP_UUE)
2836 		up->ier |= UART_IER_UUE;
2837 	if (up->capabilities & UART_CAP_RTOIE)
2838 		up->ier |= UART_IER_RTOIE;
2839 
2840 	serial_port_out(port, UART_IER, up->ier);
2841 
2842 	if (up->capabilities & UART_CAP_EFR) {
2843 		unsigned char efr = 0;
2844 		/*
2845 		 * TI16C752/Startech hardware flow control.  FIXME:
2846 		 * - TI16C752 requires control thresholds to be set.
2847 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2848 		 */
2849 		if (termios->c_cflag & CRTSCTS)
2850 			efr |= UART_EFR_CTS;
2851 
2852 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2853 		if (port->flags & UPF_EXAR_EFR)
2854 			serial_port_out(port, UART_XR_EFR, efr);
2855 		else
2856 			serial_port_out(port, UART_EFR, efr);
2857 	}
2858 
2859 	serial8250_set_divisor(port, baud, quot, frac);
2860 
2861 	/*
2862 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2863 	 * is written without DLAB set, this mode will be disabled.
2864 	 */
2865 	if (port->type == PORT_16750)
2866 		serial_port_out(port, UART_FCR, up->fcr);
2867 
2868 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2869 	if (port->type != PORT_16750) {
2870 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2871 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2872 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2873 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2874 	}
2875 	serial8250_set_mctrl(port, port->mctrl);
2876 	spin_unlock_irqrestore(&port->lock, flags);
2877 	serial8250_rpm_put(up);
2878 
2879 	/* Don't rewrite B0 */
2880 	if (tty_termios_baud_rate(termios))
2881 		tty_termios_encode_baud_rate(termios, baud, baud);
2882 }
2883 EXPORT_SYMBOL(serial8250_do_set_termios);
2884 
2885 static void
2886 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2887 		       struct ktermios *old)
2888 {
2889 	if (port->set_termios)
2890 		port->set_termios(port, termios, old);
2891 	else
2892 		serial8250_do_set_termios(port, termios, old);
2893 }
2894 
2895 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2896 {
2897 	if (termios->c_line == N_PPS) {
2898 		port->flags |= UPF_HARDPPS_CD;
2899 		spin_lock_irq(&port->lock);
2900 		serial8250_enable_ms(port);
2901 		spin_unlock_irq(&port->lock);
2902 	} else {
2903 		port->flags &= ~UPF_HARDPPS_CD;
2904 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2905 			spin_lock_irq(&port->lock);
2906 			serial8250_disable_ms(port);
2907 			spin_unlock_irq(&port->lock);
2908 		}
2909 	}
2910 }
2911 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2912 
2913 static void
2914 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2915 {
2916 	if (port->set_ldisc)
2917 		port->set_ldisc(port, termios);
2918 	else
2919 		serial8250_do_set_ldisc(port, termios);
2920 }
2921 
2922 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2923 		      unsigned int oldstate)
2924 {
2925 	struct uart_8250_port *p = up_to_u8250p(port);
2926 
2927 	serial8250_set_sleep(p, state != 0);
2928 }
2929 EXPORT_SYMBOL(serial8250_do_pm);
2930 
2931 static void
2932 serial8250_pm(struct uart_port *port, unsigned int state,
2933 	      unsigned int oldstate)
2934 {
2935 	if (port->pm)
2936 		port->pm(port, state, oldstate);
2937 	else
2938 		serial8250_do_pm(port, state, oldstate);
2939 }
2940 
2941 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2942 {
2943 	if (pt->port.mapsize)
2944 		return pt->port.mapsize;
2945 	if (pt->port.iotype == UPIO_AU) {
2946 		if (pt->port.type == PORT_RT2880)
2947 			return 0x100;
2948 		return 0x1000;
2949 	}
2950 	if (is_omap1_8250(pt))
2951 		return 0x16 << pt->port.regshift;
2952 
2953 	return 8 << pt->port.regshift;
2954 }
2955 
2956 /*
2957  * Resource handling.
2958  */
2959 static int serial8250_request_std_resource(struct uart_8250_port *up)
2960 {
2961 	unsigned int size = serial8250_port_size(up);
2962 	struct uart_port *port = &up->port;
2963 	int ret = 0;
2964 
2965 	switch (port->iotype) {
2966 	case UPIO_AU:
2967 	case UPIO_TSI:
2968 	case UPIO_MEM32:
2969 	case UPIO_MEM32BE:
2970 	case UPIO_MEM16:
2971 	case UPIO_MEM:
2972 		if (!port->mapbase)
2973 			break;
2974 
2975 		if (!request_mem_region(port->mapbase, size, "serial")) {
2976 			ret = -EBUSY;
2977 			break;
2978 		}
2979 
2980 		if (port->flags & UPF_IOREMAP) {
2981 			port->membase = ioremap(port->mapbase, size);
2982 			if (!port->membase) {
2983 				release_mem_region(port->mapbase, size);
2984 				ret = -ENOMEM;
2985 			}
2986 		}
2987 		break;
2988 
2989 	case UPIO_HUB6:
2990 	case UPIO_PORT:
2991 		if (!request_region(port->iobase, size, "serial"))
2992 			ret = -EBUSY;
2993 		break;
2994 	}
2995 	return ret;
2996 }
2997 
2998 static void serial8250_release_std_resource(struct uart_8250_port *up)
2999 {
3000 	unsigned int size = serial8250_port_size(up);
3001 	struct uart_port *port = &up->port;
3002 
3003 	switch (port->iotype) {
3004 	case UPIO_AU:
3005 	case UPIO_TSI:
3006 	case UPIO_MEM32:
3007 	case UPIO_MEM32BE:
3008 	case UPIO_MEM16:
3009 	case UPIO_MEM:
3010 		if (!port->mapbase)
3011 			break;
3012 
3013 		if (port->flags & UPF_IOREMAP) {
3014 			iounmap(port->membase);
3015 			port->membase = NULL;
3016 		}
3017 
3018 		release_mem_region(port->mapbase, size);
3019 		break;
3020 
3021 	case UPIO_HUB6:
3022 	case UPIO_PORT:
3023 		release_region(port->iobase, size);
3024 		break;
3025 	}
3026 }
3027 
3028 static void serial8250_release_port(struct uart_port *port)
3029 {
3030 	struct uart_8250_port *up = up_to_u8250p(port);
3031 
3032 	serial8250_release_std_resource(up);
3033 }
3034 
3035 static int serial8250_request_port(struct uart_port *port)
3036 {
3037 	struct uart_8250_port *up = up_to_u8250p(port);
3038 
3039 	return serial8250_request_std_resource(up);
3040 }
3041 
3042 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3043 {
3044 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3045 	unsigned char bytes;
3046 
3047 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3048 
3049 	return bytes ? bytes : -EOPNOTSUPP;
3050 }
3051 
3052 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3053 {
3054 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3055 	int i;
3056 
3057 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3058 		return -EOPNOTSUPP;
3059 
3060 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3061 		if (bytes < conf_type->rxtrig_bytes[i])
3062 			/* Use the nearest lower value */
3063 			return (--i) << UART_FCR_R_TRIG_SHIFT;
3064 	}
3065 
3066 	return UART_FCR_R_TRIG_11;
3067 }
3068 
3069 static int do_get_rxtrig(struct tty_port *port)
3070 {
3071 	struct uart_state *state = container_of(port, struct uart_state, port);
3072 	struct uart_port *uport = state->uart_port;
3073 	struct uart_8250_port *up = up_to_u8250p(uport);
3074 
3075 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3076 		return -EINVAL;
3077 
3078 	return fcr_get_rxtrig_bytes(up);
3079 }
3080 
3081 static int do_serial8250_get_rxtrig(struct tty_port *port)
3082 {
3083 	int rxtrig_bytes;
3084 
3085 	mutex_lock(&port->mutex);
3086 	rxtrig_bytes = do_get_rxtrig(port);
3087 	mutex_unlock(&port->mutex);
3088 
3089 	return rxtrig_bytes;
3090 }
3091 
3092 static ssize_t rx_trig_bytes_show(struct device *dev,
3093 	struct device_attribute *attr, char *buf)
3094 {
3095 	struct tty_port *port = dev_get_drvdata(dev);
3096 	int rxtrig_bytes;
3097 
3098 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
3099 	if (rxtrig_bytes < 0)
3100 		return rxtrig_bytes;
3101 
3102 	return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3103 }
3104 
3105 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3106 {
3107 	struct uart_state *state = container_of(port, struct uart_state, port);
3108 	struct uart_port *uport = state->uart_port;
3109 	struct uart_8250_port *up = up_to_u8250p(uport);
3110 	int rxtrig;
3111 
3112 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3113 	    up->fifo_bug)
3114 		return -EINVAL;
3115 
3116 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3117 	if (rxtrig < 0)
3118 		return rxtrig;
3119 
3120 	serial8250_clear_fifos(up);
3121 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3122 	up->fcr |= (unsigned char)rxtrig;
3123 	serial_out(up, UART_FCR, up->fcr);
3124 	return 0;
3125 }
3126 
3127 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3128 {
3129 	int ret;
3130 
3131 	mutex_lock(&port->mutex);
3132 	ret = do_set_rxtrig(port, bytes);
3133 	mutex_unlock(&port->mutex);
3134 
3135 	return ret;
3136 }
3137 
3138 static ssize_t rx_trig_bytes_store(struct device *dev,
3139 	struct device_attribute *attr, const char *buf, size_t count)
3140 {
3141 	struct tty_port *port = dev_get_drvdata(dev);
3142 	unsigned char bytes;
3143 	int ret;
3144 
3145 	if (!count)
3146 		return -EINVAL;
3147 
3148 	ret = kstrtou8(buf, 10, &bytes);
3149 	if (ret < 0)
3150 		return ret;
3151 
3152 	ret = do_serial8250_set_rxtrig(port, bytes);
3153 	if (ret < 0)
3154 		return ret;
3155 
3156 	return count;
3157 }
3158 
3159 static DEVICE_ATTR_RW(rx_trig_bytes);
3160 
3161 static struct attribute *serial8250_dev_attrs[] = {
3162 	&dev_attr_rx_trig_bytes.attr,
3163 	NULL
3164 };
3165 
3166 static struct attribute_group serial8250_dev_attr_group = {
3167 	.attrs = serial8250_dev_attrs,
3168 };
3169 
3170 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3171 {
3172 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3173 
3174 	if (conf_type->rxtrig_bytes[0])
3175 		up->port.attr_group = &serial8250_dev_attr_group;
3176 }
3177 
3178 static void serial8250_config_port(struct uart_port *port, int flags)
3179 {
3180 	struct uart_8250_port *up = up_to_u8250p(port);
3181 	int ret;
3182 
3183 	/*
3184 	 * Find the region that we can probe for.  This in turn
3185 	 * tells us whether we can probe for the type of port.
3186 	 */
3187 	ret = serial8250_request_std_resource(up);
3188 	if (ret < 0)
3189 		return;
3190 
3191 	if (port->iotype != up->cur_iotype)
3192 		set_io_from_upio(port);
3193 
3194 	if (flags & UART_CONFIG_TYPE)
3195 		autoconfig(up);
3196 
3197 	if (port->rs485.flags & SER_RS485_ENABLED)
3198 		port->rs485_config(port, &port->rs485);
3199 
3200 	/* if access method is AU, it is a 16550 with a quirk */
3201 	if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3202 		up->bugs |= UART_BUG_NOMSR;
3203 
3204 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3205 	if (port->type == PORT_TEGRA)
3206 		up->bugs |= UART_BUG_NOMSR;
3207 
3208 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3209 		autoconfig_irq(up);
3210 
3211 	if (port->type == PORT_UNKNOWN)
3212 		serial8250_release_std_resource(up);
3213 
3214 	register_dev_spec_attr_grp(up);
3215 	up->fcr = uart_config[up->port.type].fcr;
3216 }
3217 
3218 static int
3219 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3220 {
3221 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3222 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3223 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3224 	    ser->type == PORT_STARTECH)
3225 		return -EINVAL;
3226 	return 0;
3227 }
3228 
3229 static const char *serial8250_type(struct uart_port *port)
3230 {
3231 	int type = port->type;
3232 
3233 	if (type >= ARRAY_SIZE(uart_config))
3234 		type = 0;
3235 	return uart_config[type].name;
3236 }
3237 
3238 static const struct uart_ops serial8250_pops = {
3239 	.tx_empty	= serial8250_tx_empty,
3240 	.set_mctrl	= serial8250_set_mctrl,
3241 	.get_mctrl	= serial8250_get_mctrl,
3242 	.stop_tx	= serial8250_stop_tx,
3243 	.start_tx	= serial8250_start_tx,
3244 	.throttle	= serial8250_throttle,
3245 	.unthrottle	= serial8250_unthrottle,
3246 	.stop_rx	= serial8250_stop_rx,
3247 	.enable_ms	= serial8250_enable_ms,
3248 	.break_ctl	= serial8250_break_ctl,
3249 	.startup	= serial8250_startup,
3250 	.shutdown	= serial8250_shutdown,
3251 	.set_termios	= serial8250_set_termios,
3252 	.set_ldisc	= serial8250_set_ldisc,
3253 	.pm		= serial8250_pm,
3254 	.type		= serial8250_type,
3255 	.release_port	= serial8250_release_port,
3256 	.request_port	= serial8250_request_port,
3257 	.config_port	= serial8250_config_port,
3258 	.verify_port	= serial8250_verify_port,
3259 #ifdef CONFIG_CONSOLE_POLL
3260 	.poll_get_char = serial8250_get_poll_char,
3261 	.poll_put_char = serial8250_put_poll_char,
3262 #endif
3263 };
3264 
3265 void serial8250_init_port(struct uart_8250_port *up)
3266 {
3267 	struct uart_port *port = &up->port;
3268 
3269 	spin_lock_init(&port->lock);
3270 	port->ops = &serial8250_pops;
3271 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3272 
3273 	up->cur_iotype = 0xFF;
3274 }
3275 EXPORT_SYMBOL_GPL(serial8250_init_port);
3276 
3277 void serial8250_set_defaults(struct uart_8250_port *up)
3278 {
3279 	struct uart_port *port = &up->port;
3280 
3281 	if (up->port.flags & UPF_FIXED_TYPE) {
3282 		unsigned int type = up->port.type;
3283 
3284 		if (!up->port.fifosize)
3285 			up->port.fifosize = uart_config[type].fifo_size;
3286 		if (!up->tx_loadsz)
3287 			up->tx_loadsz = uart_config[type].tx_loadsz;
3288 		if (!up->capabilities)
3289 			up->capabilities = uart_config[type].flags;
3290 	}
3291 
3292 	set_io_from_upio(port);
3293 
3294 	/* default dma handlers */
3295 	if (up->dma) {
3296 		if (!up->dma->tx_dma)
3297 			up->dma->tx_dma = serial8250_tx_dma;
3298 		if (!up->dma->rx_dma)
3299 			up->dma->rx_dma = serial8250_rx_dma;
3300 	}
3301 }
3302 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3303 
3304 #ifdef CONFIG_SERIAL_8250_CONSOLE
3305 
3306 static void serial8250_console_putchar(struct uart_port *port, int ch)
3307 {
3308 	struct uart_8250_port *up = up_to_u8250p(port);
3309 
3310 	wait_for_xmitr(up, UART_LSR_THRE);
3311 	serial_port_out(port, UART_TX, ch);
3312 }
3313 
3314 /*
3315  *	Restore serial console when h/w power-off detected
3316  */
3317 static void serial8250_console_restore(struct uart_8250_port *up)
3318 {
3319 	struct uart_port *port = &up->port;
3320 	struct ktermios termios;
3321 	unsigned int baud, quot, frac = 0;
3322 
3323 	termios.c_cflag = port->cons->cflag;
3324 	if (port->state->port.tty && termios.c_cflag == 0)
3325 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3326 
3327 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3328 	quot = serial8250_get_divisor(port, baud, &frac);
3329 
3330 	serial8250_set_divisor(port, baud, quot, frac);
3331 	serial_port_out(port, UART_LCR, up->lcr);
3332 	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3333 }
3334 
3335 /*
3336  * Print a string to the serial port using the device FIFO
3337  *
3338  * It sends fifosize bytes and then waits for the fifo
3339  * to get empty.
3340  */
3341 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3342 					  const char *s, unsigned int count)
3343 {
3344 	int i;
3345 	const char *end = s + count;
3346 	unsigned int fifosize = up->port.fifosize;
3347 	bool cr_sent = false;
3348 
3349 	while (s != end) {
3350 		wait_for_lsr(up, UART_LSR_THRE);
3351 
3352 		for (i = 0; i < fifosize && s != end; ++i) {
3353 			if (*s == '\n' && !cr_sent) {
3354 				serial_out(up, UART_TX, '\r');
3355 				cr_sent = true;
3356 			} else {
3357 				serial_out(up, UART_TX, *s++);
3358 				cr_sent = false;
3359 			}
3360 		}
3361 	}
3362 }
3363 
3364 /*
3365  *	Print a string to the serial port trying not to disturb
3366  *	any possible real use of the port...
3367  *
3368  *	The console_lock must be held when we get here.
3369  *
3370  *	Doing runtime PM is really a bad idea for the kernel console.
3371  *	Thus, we assume the function is called when device is powered up.
3372  */
3373 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3374 			      unsigned int count)
3375 {
3376 	struct uart_8250_em485 *em485 = up->em485;
3377 	struct uart_port *port = &up->port;
3378 	unsigned long flags;
3379 	unsigned int ier, use_fifo;
3380 	int locked = 1;
3381 
3382 	touch_nmi_watchdog();
3383 
3384 	if (oops_in_progress)
3385 		locked = spin_trylock_irqsave(&port->lock, flags);
3386 	else
3387 		spin_lock_irqsave(&port->lock, flags);
3388 
3389 	/*
3390 	 *	First save the IER then disable the interrupts
3391 	 */
3392 	ier = serial_port_in(port, UART_IER);
3393 
3394 	if (up->capabilities & UART_CAP_UUE)
3395 		serial_port_out(port, UART_IER, UART_IER_UUE);
3396 	else
3397 		serial_port_out(port, UART_IER, 0);
3398 
3399 	/* check scratch reg to see if port powered off during system sleep */
3400 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3401 		serial8250_console_restore(up);
3402 		up->canary = 0;
3403 	}
3404 
3405 	if (em485) {
3406 		if (em485->tx_stopped)
3407 			up->rs485_start_tx(up);
3408 		mdelay(port->rs485.delay_rts_before_send);
3409 	}
3410 
3411 	use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3412 		port->fifosize > 1 &&
3413 		(serial_port_in(port, UART_FCR) & UART_FCR_ENABLE_FIFO) &&
3414 		/*
3415 		 * After we put a data in the fifo, the controller will send
3416 		 * it regardless of the CTS state. Therefore, only use fifo
3417 		 * if we don't use control flow.
3418 		 */
3419 		!(up->port.flags & UPF_CONS_FLOW);
3420 
3421 	if (likely(use_fifo))
3422 		serial8250_console_fifo_write(up, s, count);
3423 	else
3424 		uart_console_write(port, s, count, serial8250_console_putchar);
3425 
3426 	/*
3427 	 *	Finally, wait for transmitter to become empty
3428 	 *	and restore the IER
3429 	 */
3430 	wait_for_xmitr(up, BOTH_EMPTY);
3431 
3432 	if (em485) {
3433 		mdelay(port->rs485.delay_rts_after_send);
3434 		if (em485->tx_stopped)
3435 			up->rs485_stop_tx(up);
3436 	}
3437 
3438 	serial_port_out(port, UART_IER, ier);
3439 
3440 	/*
3441 	 *	The receive handling will happen properly because the
3442 	 *	receive ready bit will still be set; it is not cleared
3443 	 *	on read.  However, modem control will not, we must
3444 	 *	call it if we have saved something in the saved flags
3445 	 *	while processing with interrupts off.
3446 	 */
3447 	if (up->msr_saved_flags)
3448 		serial8250_modem_status(up);
3449 
3450 	if (locked)
3451 		spin_unlock_irqrestore(&port->lock, flags);
3452 }
3453 
3454 static unsigned int probe_baud(struct uart_port *port)
3455 {
3456 	unsigned char lcr, dll, dlm;
3457 	unsigned int quot;
3458 
3459 	lcr = serial_port_in(port, UART_LCR);
3460 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3461 	dll = serial_port_in(port, UART_DLL);
3462 	dlm = serial_port_in(port, UART_DLM);
3463 	serial_port_out(port, UART_LCR, lcr);
3464 
3465 	quot = (dlm << 8) | dll;
3466 	return (port->uartclk / 16) / quot;
3467 }
3468 
3469 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3470 {
3471 	int baud = 9600;
3472 	int bits = 8;
3473 	int parity = 'n';
3474 	int flow = 'n';
3475 	int ret;
3476 
3477 	if (!port->iobase && !port->membase)
3478 		return -ENODEV;
3479 
3480 	if (options)
3481 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3482 	else if (probe)
3483 		baud = probe_baud(port);
3484 
3485 	ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3486 	if (ret)
3487 		return ret;
3488 
3489 	if (port->dev)
3490 		pm_runtime_get_sync(port->dev);
3491 
3492 	return 0;
3493 }
3494 
3495 int serial8250_console_exit(struct uart_port *port)
3496 {
3497 	if (port->dev)
3498 		pm_runtime_put_sync(port->dev);
3499 
3500 	return 0;
3501 }
3502 
3503 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3504 
3505 MODULE_LICENSE("GPL");
3506