1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #define SUPPORT_SYSRQ
16 #endif
17 
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/ioport.h>
21 #include <linux/init.h>
22 #include <linux/console.h>
23 #include <linux/sysrq.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/tty.h>
27 #include <linux/ratelimit.h>
28 #include <linux/tty_flip.h>
29 #include <linux/serial.h>
30 #include <linux/serial_8250.h>
31 #include <linux/nmi.h>
32 #include <linux/mutex.h>
33 #include <linux/slab.h>
34 #include <linux/uaccess.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/ktime.h>
37 
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 
41 #include "8250.h"
42 
43 /*
44  * These are definitions for the Exar XR17V35X and XR17(C|D)15X
45  */
46 #define UART_EXAR_INT0		0x80
47 #define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
48 #define UART_EXAR_DVID		0x8d	/* Device identification */
49 
50 /* Nuvoton NPCM timeout register */
51 #define UART_NPCM_TOR          7
52 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
53 
54 /*
55  * Debugging.
56  */
57 #if 0
58 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
59 #else
60 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
61 #endif
62 
63 #define BOTH_EMPTY	(UART_LSR_TEMT | UART_LSR_THRE)
64 
65 /*
66  * Here we define the default xmit fifo size used for each type of UART.
67  */
68 static const struct serial8250_config uart_config[] = {
69 	[PORT_UNKNOWN] = {
70 		.name		= "unknown",
71 		.fifo_size	= 1,
72 		.tx_loadsz	= 1,
73 	},
74 	[PORT_8250] = {
75 		.name		= "8250",
76 		.fifo_size	= 1,
77 		.tx_loadsz	= 1,
78 	},
79 	[PORT_16450] = {
80 		.name		= "16450",
81 		.fifo_size	= 1,
82 		.tx_loadsz	= 1,
83 	},
84 	[PORT_16550] = {
85 		.name		= "16550",
86 		.fifo_size	= 1,
87 		.tx_loadsz	= 1,
88 	},
89 	[PORT_16550A] = {
90 		.name		= "16550A",
91 		.fifo_size	= 16,
92 		.tx_loadsz	= 16,
93 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
94 		.rxtrig_bytes	= {1, 4, 8, 14},
95 		.flags		= UART_CAP_FIFO,
96 	},
97 	[PORT_CIRRUS] = {
98 		.name		= "Cirrus",
99 		.fifo_size	= 1,
100 		.tx_loadsz	= 1,
101 	},
102 	[PORT_16650] = {
103 		.name		= "ST16650",
104 		.fifo_size	= 1,
105 		.tx_loadsz	= 1,
106 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
107 	},
108 	[PORT_16650V2] = {
109 		.name		= "ST16650V2",
110 		.fifo_size	= 32,
111 		.tx_loadsz	= 16,
112 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
113 				  UART_FCR_T_TRIG_00,
114 		.rxtrig_bytes	= {8, 16, 24, 28},
115 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
116 	},
117 	[PORT_16750] = {
118 		.name		= "TI16750",
119 		.fifo_size	= 64,
120 		.tx_loadsz	= 64,
121 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
122 				  UART_FCR7_64BYTE,
123 		.rxtrig_bytes	= {1, 16, 32, 56},
124 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
125 	},
126 	[PORT_STARTECH] = {
127 		.name		= "Startech",
128 		.fifo_size	= 1,
129 		.tx_loadsz	= 1,
130 	},
131 	[PORT_16C950] = {
132 		.name		= "16C950/954",
133 		.fifo_size	= 128,
134 		.tx_loadsz	= 128,
135 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
136 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
137 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
138 	},
139 	[PORT_16654] = {
140 		.name		= "ST16654",
141 		.fifo_size	= 64,
142 		.tx_loadsz	= 32,
143 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
144 				  UART_FCR_T_TRIG_10,
145 		.rxtrig_bytes	= {8, 16, 56, 60},
146 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 	},
148 	[PORT_16850] = {
149 		.name		= "XR16850",
150 		.fifo_size	= 128,
151 		.tx_loadsz	= 128,
152 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
153 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
154 	},
155 	[PORT_RSA] = {
156 		.name		= "RSA",
157 		.fifo_size	= 2048,
158 		.tx_loadsz	= 2048,
159 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
160 		.flags		= UART_CAP_FIFO,
161 	},
162 	[PORT_NS16550A] = {
163 		.name		= "NS16550A",
164 		.fifo_size	= 16,
165 		.tx_loadsz	= 16,
166 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
168 	},
169 	[PORT_XSCALE] = {
170 		.name		= "XScale",
171 		.fifo_size	= 32,
172 		.tx_loadsz	= 32,
173 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
175 	},
176 	[PORT_OCTEON] = {
177 		.name		= "OCTEON",
178 		.fifo_size	= 64,
179 		.tx_loadsz	= 64,
180 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
181 		.flags		= UART_CAP_FIFO,
182 	},
183 	[PORT_AR7] = {
184 		.name		= "AR7",
185 		.fifo_size	= 16,
186 		.tx_loadsz	= 16,
187 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
188 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
189 	},
190 	[PORT_U6_16550A] = {
191 		.name		= "U6_16550A",
192 		.fifo_size	= 64,
193 		.tx_loadsz	= 64,
194 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
195 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
196 	},
197 	[PORT_TEGRA] = {
198 		.name		= "Tegra",
199 		.fifo_size	= 32,
200 		.tx_loadsz	= 8,
201 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
202 				  UART_FCR_T_TRIG_01,
203 		.rxtrig_bytes	= {1, 4, 8, 14},
204 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
205 	},
206 	[PORT_XR17D15X] = {
207 		.name		= "XR17D15X",
208 		.fifo_size	= 64,
209 		.tx_loadsz	= 64,
210 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 				  UART_CAP_SLEEP,
213 	},
214 	[PORT_XR17V35X] = {
215 		.name		= "XR17V35X",
216 		.fifo_size	= 256,
217 		.tx_loadsz	= 256,
218 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
219 				  UART_FCR_T_TRIG_11,
220 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
221 				  UART_CAP_SLEEP,
222 	},
223 	[PORT_LPC3220] = {
224 		.name		= "LPC3220",
225 		.fifo_size	= 64,
226 		.tx_loadsz	= 32,
227 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
228 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
229 		.flags		= UART_CAP_FIFO,
230 	},
231 	[PORT_BRCM_TRUMANAGE] = {
232 		.name		= "TruManage",
233 		.fifo_size	= 1,
234 		.tx_loadsz	= 1024,
235 		.flags		= UART_CAP_HFIFO,
236 	},
237 	[PORT_8250_CIR] = {
238 		.name		= "CIR port"
239 	},
240 	[PORT_ALTR_16550_F32] = {
241 		.name		= "Altera 16550 FIFO32",
242 		.fifo_size	= 32,
243 		.tx_loadsz	= 32,
244 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 		.rxtrig_bytes	= {1, 8, 16, 30},
246 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
247 	},
248 	[PORT_ALTR_16550_F64] = {
249 		.name		= "Altera 16550 FIFO64",
250 		.fifo_size	= 64,
251 		.tx_loadsz	= 64,
252 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 		.rxtrig_bytes	= {1, 16, 32, 62},
254 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
255 	},
256 	[PORT_ALTR_16550_F128] = {
257 		.name		= "Altera 16550 FIFO128",
258 		.fifo_size	= 128,
259 		.tx_loadsz	= 128,
260 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 		.rxtrig_bytes	= {1, 32, 64, 126},
262 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
263 	},
264 	/*
265 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
266 	 * workaround of errata A-008006 which states that tx_loadsz should
267 	 * be configured less than Maximum supported fifo bytes.
268 	 */
269 	[PORT_16550A_FSL64] = {
270 		.name		= "16550A_FSL64",
271 		.fifo_size	= 64,
272 		.tx_loadsz	= 63,
273 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
274 				  UART_FCR7_64BYTE,
275 		.flags		= UART_CAP_FIFO,
276 	},
277 	[PORT_RT2880] = {
278 		.name		= "Palmchip BK-3103",
279 		.fifo_size	= 16,
280 		.tx_loadsz	= 16,
281 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
282 		.rxtrig_bytes	= {1, 4, 8, 14},
283 		.flags		= UART_CAP_FIFO,
284 	},
285 	[PORT_DA830] = {
286 		.name		= "TI DA8xx/66AK2x",
287 		.fifo_size	= 16,
288 		.tx_loadsz	= 16,
289 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
290 				  UART_FCR_R_TRIG_10,
291 		.rxtrig_bytes	= {1, 4, 8, 14},
292 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
293 	},
294 	[PORT_MTK_BTIF] = {
295 		.name		= "MediaTek BTIF",
296 		.fifo_size	= 16,
297 		.tx_loadsz	= 16,
298 		.fcr		= UART_FCR_ENABLE_FIFO |
299 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
300 		.flags		= UART_CAP_FIFO,
301 	},
302 	[PORT_NPCM] = {
303 		.name		= "Nuvoton 16550",
304 		.fifo_size	= 16,
305 		.tx_loadsz	= 16,
306 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
307 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
308 		.rxtrig_bytes	= {1, 4, 8, 14},
309 		.flags		= UART_CAP_FIFO,
310 	},
311 };
312 
313 /* Uart divisor latch read */
314 static int default_serial_dl_read(struct uart_8250_port *up)
315 {
316 	return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
317 }
318 
319 /* Uart divisor latch write */
320 static void default_serial_dl_write(struct uart_8250_port *up, int value)
321 {
322 	serial_out(up, UART_DLL, value & 0xff);
323 	serial_out(up, UART_DLM, value >> 8 & 0xff);
324 }
325 
326 #ifdef CONFIG_SERIAL_8250_RT288X
327 
328 /* Au1x00/RT288x UART hardware has a weird register layout */
329 static const s8 au_io_in_map[8] = {
330 	 0,	/* UART_RX  */
331 	 2,	/* UART_IER */
332 	 3,	/* UART_IIR */
333 	 5,	/* UART_LCR */
334 	 6,	/* UART_MCR */
335 	 7,	/* UART_LSR */
336 	 8,	/* UART_MSR */
337 	-1,	/* UART_SCR (unmapped) */
338 };
339 
340 static const s8 au_io_out_map[8] = {
341 	 1,	/* UART_TX  */
342 	 2,	/* UART_IER */
343 	 4,	/* UART_FCR */
344 	 5,	/* UART_LCR */
345 	 6,	/* UART_MCR */
346 	-1,	/* UART_LSR (unmapped) */
347 	-1,	/* UART_MSR (unmapped) */
348 	-1,	/* UART_SCR (unmapped) */
349 };
350 
351 unsigned int au_serial_in(struct uart_port *p, int offset)
352 {
353 	if (offset >= ARRAY_SIZE(au_io_in_map))
354 		return UINT_MAX;
355 	offset = au_io_in_map[offset];
356 	if (offset < 0)
357 		return UINT_MAX;
358 	return __raw_readl(p->membase + (offset << p->regshift));
359 }
360 
361 void au_serial_out(struct uart_port *p, int offset, int value)
362 {
363 	if (offset >= ARRAY_SIZE(au_io_out_map))
364 		return;
365 	offset = au_io_out_map[offset];
366 	if (offset < 0)
367 		return;
368 	__raw_writel(value, p->membase + (offset << p->regshift));
369 }
370 
371 /* Au1x00 haven't got a standard divisor latch */
372 static int au_serial_dl_read(struct uart_8250_port *up)
373 {
374 	return __raw_readl(up->port.membase + 0x28);
375 }
376 
377 static void au_serial_dl_write(struct uart_8250_port *up, int value)
378 {
379 	__raw_writel(value, up->port.membase + 0x28);
380 }
381 
382 #endif
383 
384 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
385 {
386 	offset = offset << p->regshift;
387 	outb(p->hub6 - 1 + offset, p->iobase);
388 	return inb(p->iobase + 1);
389 }
390 
391 static void hub6_serial_out(struct uart_port *p, int offset, int value)
392 {
393 	offset = offset << p->regshift;
394 	outb(p->hub6 - 1 + offset, p->iobase);
395 	outb(value, p->iobase + 1);
396 }
397 
398 static unsigned int mem_serial_in(struct uart_port *p, int offset)
399 {
400 	offset = offset << p->regshift;
401 	return readb(p->membase + offset);
402 }
403 
404 static void mem_serial_out(struct uart_port *p, int offset, int value)
405 {
406 	offset = offset << p->regshift;
407 	writeb(value, p->membase + offset);
408 }
409 
410 static void mem16_serial_out(struct uart_port *p, int offset, int value)
411 {
412 	offset = offset << p->regshift;
413 	writew(value, p->membase + offset);
414 }
415 
416 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
417 {
418 	offset = offset << p->regshift;
419 	return readw(p->membase + offset);
420 }
421 
422 static void mem32_serial_out(struct uart_port *p, int offset, int value)
423 {
424 	offset = offset << p->regshift;
425 	writel(value, p->membase + offset);
426 }
427 
428 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429 {
430 	offset = offset << p->regshift;
431 	return readl(p->membase + offset);
432 }
433 
434 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
435 {
436 	offset = offset << p->regshift;
437 	iowrite32be(value, p->membase + offset);
438 }
439 
440 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
441 {
442 	offset = offset << p->regshift;
443 	return ioread32be(p->membase + offset);
444 }
445 
446 static unsigned int io_serial_in(struct uart_port *p, int offset)
447 {
448 	offset = offset << p->regshift;
449 	return inb(p->iobase + offset);
450 }
451 
452 static void io_serial_out(struct uart_port *p, int offset, int value)
453 {
454 	offset = offset << p->regshift;
455 	outb(value, p->iobase + offset);
456 }
457 
458 static int serial8250_default_handle_irq(struct uart_port *port);
459 
460 static void set_io_from_upio(struct uart_port *p)
461 {
462 	struct uart_8250_port *up = up_to_u8250p(p);
463 
464 	up->dl_read = default_serial_dl_read;
465 	up->dl_write = default_serial_dl_write;
466 
467 	switch (p->iotype) {
468 	case UPIO_HUB6:
469 		p->serial_in = hub6_serial_in;
470 		p->serial_out = hub6_serial_out;
471 		break;
472 
473 	case UPIO_MEM:
474 		p->serial_in = mem_serial_in;
475 		p->serial_out = mem_serial_out;
476 		break;
477 
478 	case UPIO_MEM16:
479 		p->serial_in = mem16_serial_in;
480 		p->serial_out = mem16_serial_out;
481 		break;
482 
483 	case UPIO_MEM32:
484 		p->serial_in = mem32_serial_in;
485 		p->serial_out = mem32_serial_out;
486 		break;
487 
488 	case UPIO_MEM32BE:
489 		p->serial_in = mem32be_serial_in;
490 		p->serial_out = mem32be_serial_out;
491 		break;
492 
493 #ifdef CONFIG_SERIAL_8250_RT288X
494 	case UPIO_AU:
495 		p->serial_in = au_serial_in;
496 		p->serial_out = au_serial_out;
497 		up->dl_read = au_serial_dl_read;
498 		up->dl_write = au_serial_dl_write;
499 		break;
500 #endif
501 
502 	default:
503 		p->serial_in = io_serial_in;
504 		p->serial_out = io_serial_out;
505 		break;
506 	}
507 	/* Remember loaded iotype */
508 	up->cur_iotype = p->iotype;
509 	p->handle_irq = serial8250_default_handle_irq;
510 }
511 
512 static void
513 serial_port_out_sync(struct uart_port *p, int offset, int value)
514 {
515 	switch (p->iotype) {
516 	case UPIO_MEM:
517 	case UPIO_MEM16:
518 	case UPIO_MEM32:
519 	case UPIO_MEM32BE:
520 	case UPIO_AU:
521 		p->serial_out(p, offset, value);
522 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
523 		break;
524 	default:
525 		p->serial_out(p, offset, value);
526 	}
527 }
528 
529 /*
530  * For the 16C950
531  */
532 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
533 {
534 	serial_out(up, UART_SCR, offset);
535 	serial_out(up, UART_ICR, value);
536 }
537 
538 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
539 {
540 	unsigned int value;
541 
542 	serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
543 	serial_out(up, UART_SCR, offset);
544 	value = serial_in(up, UART_ICR);
545 	serial_icr_write(up, UART_ACR, up->acr);
546 
547 	return value;
548 }
549 
550 /*
551  * FIFO support.
552  */
553 static void serial8250_clear_fifos(struct uart_8250_port *p)
554 {
555 	if (p->capabilities & UART_CAP_FIFO) {
556 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
557 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
558 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
559 		serial_out(p, UART_FCR, 0);
560 	}
561 }
562 
563 static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
564 {
565 	unsigned char mcr = serial8250_in_MCR(p);
566 
567 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
568 		mcr |= UART_MCR_RTS;
569 	else
570 		mcr &= ~UART_MCR_RTS;
571 	serial8250_out_MCR(p, mcr);
572 }
573 
574 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
575 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
576 
577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
578 {
579 	serial8250_clear_fifos(p);
580 	serial_out(p, UART_FCR, p->fcr);
581 }
582 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
583 
584 void serial8250_rpm_get(struct uart_8250_port *p)
585 {
586 	if (!(p->capabilities & UART_CAP_RPM))
587 		return;
588 	pm_runtime_get_sync(p->port.dev);
589 }
590 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
591 
592 void serial8250_rpm_put(struct uart_8250_port *p)
593 {
594 	if (!(p->capabilities & UART_CAP_RPM))
595 		return;
596 	pm_runtime_mark_last_busy(p->port.dev);
597 	pm_runtime_put_autosuspend(p->port.dev);
598 }
599 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
600 
601 /**
602  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
603  *	@p:	uart_8250_port port instance
604  *
605  *	The function is used to start rs485 software emulating on the
606  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
607  *	transmission. The function is idempotent, so it is safe to call it
608  *	multiple times.
609  *
610  *	The caller MUST enable interrupt on empty shift register before
611  *	calling serial8250_em485_init(). This interrupt is not a part of
612  *	8250 standard, but implementation defined.
613  *
614  *	The function is supposed to be called from .rs485_config callback
615  *	or from any other callback protected with p->port.lock spinlock.
616  *
617  *	See also serial8250_em485_destroy()
618  *
619  *	Return 0 - success, -errno - otherwise
620  */
621 int serial8250_em485_init(struct uart_8250_port *p)
622 {
623 	if (p->em485)
624 		return 0;
625 
626 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
627 	if (!p->em485)
628 		return -ENOMEM;
629 
630 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
631 		     HRTIMER_MODE_REL);
632 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
633 		     HRTIMER_MODE_REL);
634 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
635 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
636 	p->em485->port = p;
637 	p->em485->active_timer = NULL;
638 	serial8250_em485_rts_after_send(p);
639 
640 	return 0;
641 }
642 EXPORT_SYMBOL_GPL(serial8250_em485_init);
643 
644 /**
645  *	serial8250_em485_destroy() - put uart_8250_port into normal state
646  *	@p:	uart_8250_port port instance
647  *
648  *	The function is used to stop rs485 software emulating on the
649  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
650  *	call it multiple times.
651  *
652  *	The function is supposed to be called from .rs485_config callback
653  *	or from any other callback protected with p->port.lock spinlock.
654  *
655  *	See also serial8250_em485_init()
656  */
657 void serial8250_em485_destroy(struct uart_8250_port *p)
658 {
659 	if (!p->em485)
660 		return;
661 
662 	hrtimer_cancel(&p->em485->start_tx_timer);
663 	hrtimer_cancel(&p->em485->stop_tx_timer);
664 
665 	kfree(p->em485);
666 	p->em485 = NULL;
667 }
668 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
669 
670 /*
671  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
672  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
673  * empty and the HW can idle again.
674  */
675 void serial8250_rpm_get_tx(struct uart_8250_port *p)
676 {
677 	unsigned char rpm_active;
678 
679 	if (!(p->capabilities & UART_CAP_RPM))
680 		return;
681 
682 	rpm_active = xchg(&p->rpm_tx_active, 1);
683 	if (rpm_active)
684 		return;
685 	pm_runtime_get_sync(p->port.dev);
686 }
687 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
688 
689 void serial8250_rpm_put_tx(struct uart_8250_port *p)
690 {
691 	unsigned char rpm_active;
692 
693 	if (!(p->capabilities & UART_CAP_RPM))
694 		return;
695 
696 	rpm_active = xchg(&p->rpm_tx_active, 0);
697 	if (!rpm_active)
698 		return;
699 	pm_runtime_mark_last_busy(p->port.dev);
700 	pm_runtime_put_autosuspend(p->port.dev);
701 }
702 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
703 
704 /*
705  * IER sleep support.  UARTs which have EFRs need the "extended
706  * capability" bit enabled.  Note that on XR16C850s, we need to
707  * reset LCR to write to IER.
708  */
709 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
710 {
711 	unsigned char lcr = 0, efr = 0;
712 	/*
713 	 * Exar UARTs have a SLEEP register that enables or disables
714 	 * each UART to enter sleep mode separately.  On the XR17V35x the
715 	 * register is accessible to each UART at the UART_EXAR_SLEEP
716 	 * offset but the UART channel may only write to the corresponding
717 	 * bit.
718 	 */
719 	serial8250_rpm_get(p);
720 	if ((p->port.type == PORT_XR17V35X) ||
721 	   (p->port.type == PORT_XR17D15X)) {
722 		serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
723 		goto out;
724 	}
725 
726 	if (p->capabilities & UART_CAP_SLEEP) {
727 		if (p->capabilities & UART_CAP_EFR) {
728 			lcr = serial_in(p, UART_LCR);
729 			efr = serial_in(p, UART_EFR);
730 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
731 			serial_out(p, UART_EFR, UART_EFR_ECB);
732 			serial_out(p, UART_LCR, 0);
733 		}
734 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
735 		if (p->capabilities & UART_CAP_EFR) {
736 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
737 			serial_out(p, UART_EFR, efr);
738 			serial_out(p, UART_LCR, lcr);
739 		}
740 	}
741 out:
742 	serial8250_rpm_put(p);
743 }
744 
745 #ifdef CONFIG_SERIAL_8250_RSA
746 /*
747  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
748  * We set the port uart clock rate if we succeed.
749  */
750 static int __enable_rsa(struct uart_8250_port *up)
751 {
752 	unsigned char mode;
753 	int result;
754 
755 	mode = serial_in(up, UART_RSA_MSR);
756 	result = mode & UART_RSA_MSR_FIFO;
757 
758 	if (!result) {
759 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
760 		mode = serial_in(up, UART_RSA_MSR);
761 		result = mode & UART_RSA_MSR_FIFO;
762 	}
763 
764 	if (result)
765 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
766 
767 	return result;
768 }
769 
770 static void enable_rsa(struct uart_8250_port *up)
771 {
772 	if (up->port.type == PORT_RSA) {
773 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
774 			spin_lock_irq(&up->port.lock);
775 			__enable_rsa(up);
776 			spin_unlock_irq(&up->port.lock);
777 		}
778 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
779 			serial_out(up, UART_RSA_FRR, 0);
780 	}
781 }
782 
783 /*
784  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
785  * It is unknown why interrupts were disabled in here.  However,
786  * the caller is expected to preserve this behaviour by grabbing
787  * the spinlock before calling this function.
788  */
789 static void disable_rsa(struct uart_8250_port *up)
790 {
791 	unsigned char mode;
792 	int result;
793 
794 	if (up->port.type == PORT_RSA &&
795 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
796 		spin_lock_irq(&up->port.lock);
797 
798 		mode = serial_in(up, UART_RSA_MSR);
799 		result = !(mode & UART_RSA_MSR_FIFO);
800 
801 		if (!result) {
802 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
803 			mode = serial_in(up, UART_RSA_MSR);
804 			result = !(mode & UART_RSA_MSR_FIFO);
805 		}
806 
807 		if (result)
808 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
809 		spin_unlock_irq(&up->port.lock);
810 	}
811 }
812 #endif /* CONFIG_SERIAL_8250_RSA */
813 
814 /*
815  * This is a quickie test to see how big the FIFO is.
816  * It doesn't work at all the time, more's the pity.
817  */
818 static int size_fifo(struct uart_8250_port *up)
819 {
820 	unsigned char old_fcr, old_mcr, old_lcr;
821 	unsigned short old_dl;
822 	int count;
823 
824 	old_lcr = serial_in(up, UART_LCR);
825 	serial_out(up, UART_LCR, 0);
826 	old_fcr = serial_in(up, UART_FCR);
827 	old_mcr = serial8250_in_MCR(up);
828 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
829 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
830 	serial8250_out_MCR(up, UART_MCR_LOOP);
831 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
832 	old_dl = serial_dl_read(up);
833 	serial_dl_write(up, 0x0001);
834 	serial_out(up, UART_LCR, 0x03);
835 	for (count = 0; count < 256; count++)
836 		serial_out(up, UART_TX, count);
837 	mdelay(20);/* FIXME - schedule_timeout */
838 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
839 	     (count < 256); count++)
840 		serial_in(up, UART_RX);
841 	serial_out(up, UART_FCR, old_fcr);
842 	serial8250_out_MCR(up, old_mcr);
843 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
844 	serial_dl_write(up, old_dl);
845 	serial_out(up, UART_LCR, old_lcr);
846 
847 	return count;
848 }
849 
850 /*
851  * Read UART ID using the divisor method - set DLL and DLM to zero
852  * and the revision will be in DLL and device type in DLM.  We
853  * preserve the device state across this.
854  */
855 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
856 {
857 	unsigned char old_lcr;
858 	unsigned int id, old_dl;
859 
860 	old_lcr = serial_in(p, UART_LCR);
861 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
862 	old_dl = serial_dl_read(p);
863 	serial_dl_write(p, 0);
864 	id = serial_dl_read(p);
865 	serial_dl_write(p, old_dl);
866 
867 	serial_out(p, UART_LCR, old_lcr);
868 
869 	return id;
870 }
871 
872 /*
873  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
874  * When this function is called we know it is at least a StarTech
875  * 16650 V2, but it might be one of several StarTech UARTs, or one of
876  * its clones.  (We treat the broken original StarTech 16650 V1 as a
877  * 16550, and why not?  Startech doesn't seem to even acknowledge its
878  * existence.)
879  *
880  * What evil have men's minds wrought...
881  */
882 static void autoconfig_has_efr(struct uart_8250_port *up)
883 {
884 	unsigned int id1, id2, id3, rev;
885 
886 	/*
887 	 * Everything with an EFR has SLEEP
888 	 */
889 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
890 
891 	/*
892 	 * First we check to see if it's an Oxford Semiconductor UART.
893 	 *
894 	 * If we have to do this here because some non-National
895 	 * Semiconductor clone chips lock up if you try writing to the
896 	 * LSR register (which serial_icr_read does)
897 	 */
898 
899 	/*
900 	 * Check for Oxford Semiconductor 16C950.
901 	 *
902 	 * EFR [4] must be set else this test fails.
903 	 *
904 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
905 	 * claims that it's needed for 952 dual UART's (which are not
906 	 * recommended for new designs).
907 	 */
908 	up->acr = 0;
909 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
910 	serial_out(up, UART_EFR, UART_EFR_ECB);
911 	serial_out(up, UART_LCR, 0x00);
912 	id1 = serial_icr_read(up, UART_ID1);
913 	id2 = serial_icr_read(up, UART_ID2);
914 	id3 = serial_icr_read(up, UART_ID3);
915 	rev = serial_icr_read(up, UART_REV);
916 
917 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
918 
919 	if (id1 == 0x16 && id2 == 0xC9 &&
920 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
921 		up->port.type = PORT_16C950;
922 
923 		/*
924 		 * Enable work around for the Oxford Semiconductor 952 rev B
925 		 * chip which causes it to seriously miscalculate baud rates
926 		 * when DLL is 0.
927 		 */
928 		if (id3 == 0x52 && rev == 0x01)
929 			up->bugs |= UART_BUG_QUOT;
930 		return;
931 	}
932 
933 	/*
934 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
935 	 * reading back DLL and DLM.  The chip type depends on the DLM
936 	 * value read back:
937 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
938 	 *  0x12 - XR16C2850.
939 	 *  0x14 - XR16C854.
940 	 */
941 	id1 = autoconfig_read_divisor_id(up);
942 	DEBUG_AUTOCONF("850id=%04x ", id1);
943 
944 	id2 = id1 >> 8;
945 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
946 		up->port.type = PORT_16850;
947 		return;
948 	}
949 
950 	/*
951 	 * It wasn't an XR16C850.
952 	 *
953 	 * We distinguish between the '654 and the '650 by counting
954 	 * how many bytes are in the FIFO.  I'm using this for now,
955 	 * since that's the technique that was sent to me in the
956 	 * serial driver update, but I'm not convinced this works.
957 	 * I've had problems doing this in the past.  -TYT
958 	 */
959 	if (size_fifo(up) == 64)
960 		up->port.type = PORT_16654;
961 	else
962 		up->port.type = PORT_16650V2;
963 }
964 
965 /*
966  * We detected a chip without a FIFO.  Only two fall into
967  * this category - the original 8250 and the 16450.  The
968  * 16450 has a scratch register (accessible with LCR=0)
969  */
970 static void autoconfig_8250(struct uart_8250_port *up)
971 {
972 	unsigned char scratch, status1, status2;
973 
974 	up->port.type = PORT_8250;
975 
976 	scratch = serial_in(up, UART_SCR);
977 	serial_out(up, UART_SCR, 0xa5);
978 	status1 = serial_in(up, UART_SCR);
979 	serial_out(up, UART_SCR, 0x5a);
980 	status2 = serial_in(up, UART_SCR);
981 	serial_out(up, UART_SCR, scratch);
982 
983 	if (status1 == 0xa5 && status2 == 0x5a)
984 		up->port.type = PORT_16450;
985 }
986 
987 static int broken_efr(struct uart_8250_port *up)
988 {
989 	/*
990 	 * Exar ST16C2550 "A2" devices incorrectly detect as
991 	 * having an EFR, and report an ID of 0x0201.  See
992 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
993 	 */
994 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
995 		return 1;
996 
997 	return 0;
998 }
999 
1000 /*
1001  * We know that the chip has FIFOs.  Does it have an EFR?  The
1002  * EFR is located in the same register position as the IIR and
1003  * we know the top two bits of the IIR are currently set.  The
1004  * EFR should contain zero.  Try to read the EFR.
1005  */
1006 static void autoconfig_16550a(struct uart_8250_port *up)
1007 {
1008 	unsigned char status1, status2;
1009 	unsigned int iersave;
1010 
1011 	up->port.type = PORT_16550A;
1012 	up->capabilities |= UART_CAP_FIFO;
1013 
1014 	/*
1015 	 * XR17V35x UARTs have an extra divisor register, DLD
1016 	 * that gets enabled with when DLAB is set which will
1017 	 * cause the device to incorrectly match and assign
1018 	 * port type to PORT_16650.  The EFR for this UART is
1019 	 * found at offset 0x09. Instead check the Deice ID (DVID)
1020 	 * register for a 2, 4 or 8 port UART.
1021 	 */
1022 	if (up->port.flags & UPF_EXAR_EFR) {
1023 		status1 = serial_in(up, UART_EXAR_DVID);
1024 		if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
1025 			DEBUG_AUTOCONF("Exar XR17V35x ");
1026 			up->port.type = PORT_XR17V35X;
1027 			up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1028 						UART_CAP_SLEEP;
1029 
1030 			return;
1031 		}
1032 
1033 	}
1034 
1035 	/*
1036 	 * Check for presence of the EFR when DLAB is set.
1037 	 * Only ST16C650V1 UARTs pass this test.
1038 	 */
1039 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1040 	if (serial_in(up, UART_EFR) == 0) {
1041 		serial_out(up, UART_EFR, 0xA8);
1042 		if (serial_in(up, UART_EFR) != 0) {
1043 			DEBUG_AUTOCONF("EFRv1 ");
1044 			up->port.type = PORT_16650;
1045 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1046 		} else {
1047 			serial_out(up, UART_LCR, 0);
1048 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1049 				   UART_FCR7_64BYTE);
1050 			status1 = serial_in(up, UART_IIR) >> 5;
1051 			serial_out(up, UART_FCR, 0);
1052 			serial_out(up, UART_LCR, 0);
1053 
1054 			if (status1 == 7)
1055 				up->port.type = PORT_16550A_FSL64;
1056 			else
1057 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1058 		}
1059 		serial_out(up, UART_EFR, 0);
1060 		return;
1061 	}
1062 
1063 	/*
1064 	 * Maybe it requires 0xbf to be written to the LCR.
1065 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1066 	 */
1067 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1068 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1069 		DEBUG_AUTOCONF("EFRv2 ");
1070 		autoconfig_has_efr(up);
1071 		return;
1072 	}
1073 
1074 	/*
1075 	 * Check for a National Semiconductor SuperIO chip.
1076 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1077 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1078 	 * switch back to bank 2, read it from EXCR1 again and check
1079 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1080 	 */
1081 	serial_out(up, UART_LCR, 0);
1082 	status1 = serial8250_in_MCR(up);
1083 	serial_out(up, UART_LCR, 0xE0);
1084 	status2 = serial_in(up, 0x02); /* EXCR1 */
1085 
1086 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1087 		serial_out(up, UART_LCR, 0);
1088 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1089 		serial_out(up, UART_LCR, 0xE0);
1090 		status2 = serial_in(up, 0x02); /* EXCR1 */
1091 		serial_out(up, UART_LCR, 0);
1092 		serial8250_out_MCR(up, status1);
1093 
1094 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1095 			unsigned short quot;
1096 
1097 			serial_out(up, UART_LCR, 0xE0);
1098 
1099 			quot = serial_dl_read(up);
1100 			quot <<= 3;
1101 
1102 			if (ns16550a_goto_highspeed(up))
1103 				serial_dl_write(up, quot);
1104 
1105 			serial_out(up, UART_LCR, 0);
1106 
1107 			up->port.uartclk = 921600*16;
1108 			up->port.type = PORT_NS16550A;
1109 			up->capabilities |= UART_NATSEMI;
1110 			return;
1111 		}
1112 	}
1113 
1114 	/*
1115 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1116 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1117 	 * Try setting it with and without DLAB set.  Cheap clones
1118 	 * set bit 5 without DLAB set.
1119 	 */
1120 	serial_out(up, UART_LCR, 0);
1121 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1122 	status1 = serial_in(up, UART_IIR) >> 5;
1123 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1124 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1125 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1126 	status2 = serial_in(up, UART_IIR) >> 5;
1127 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1128 	serial_out(up, UART_LCR, 0);
1129 
1130 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1131 
1132 	if (status1 == 6 && status2 == 7) {
1133 		up->port.type = PORT_16750;
1134 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1135 		return;
1136 	}
1137 
1138 	/*
1139 	 * Try writing and reading the UART_IER_UUE bit (b6).
1140 	 * If it works, this is probably one of the Xscale platform's
1141 	 * internal UARTs.
1142 	 * We're going to explicitly set the UUE bit to 0 before
1143 	 * trying to write and read a 1 just to make sure it's not
1144 	 * already a 1 and maybe locked there before we even start start.
1145 	 */
1146 	iersave = serial_in(up, UART_IER);
1147 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1148 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1149 		/*
1150 		 * OK it's in a known zero state, try writing and reading
1151 		 * without disturbing the current state of the other bits.
1152 		 */
1153 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1154 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1155 			/*
1156 			 * It's an Xscale.
1157 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1158 			 */
1159 			DEBUG_AUTOCONF("Xscale ");
1160 			up->port.type = PORT_XSCALE;
1161 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1162 			return;
1163 		}
1164 	} else {
1165 		/*
1166 		 * If we got here we couldn't force the IER_UUE bit to 0.
1167 		 * Log it and continue.
1168 		 */
1169 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1170 	}
1171 	serial_out(up, UART_IER, iersave);
1172 
1173 	/*
1174 	 * Exar uarts have EFR in a weird location
1175 	 */
1176 	if (up->port.flags & UPF_EXAR_EFR) {
1177 		DEBUG_AUTOCONF("Exar XR17D15x ");
1178 		up->port.type = PORT_XR17D15X;
1179 		up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1180 				    UART_CAP_SLEEP;
1181 
1182 		return;
1183 	}
1184 
1185 	/*
1186 	 * We distinguish between 16550A and U6 16550A by counting
1187 	 * how many bytes are in the FIFO.
1188 	 */
1189 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1190 		up->port.type = PORT_U6_16550A;
1191 		up->capabilities |= UART_CAP_AFE;
1192 	}
1193 }
1194 
1195 /*
1196  * This routine is called by rs_init() to initialize a specific serial
1197  * port.  It determines what type of UART chip this serial port is
1198  * using: 8250, 16450, 16550, 16550A.  The important question is
1199  * whether or not this UART is a 16550A or not, since this will
1200  * determine whether or not we can use its FIFO features or not.
1201  */
1202 static void autoconfig(struct uart_8250_port *up)
1203 {
1204 	unsigned char status1, scratch, scratch2, scratch3;
1205 	unsigned char save_lcr, save_mcr;
1206 	struct uart_port *port = &up->port;
1207 	unsigned long flags;
1208 	unsigned int old_capabilities;
1209 
1210 	if (!port->iobase && !port->mapbase && !port->membase)
1211 		return;
1212 
1213 	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1214 		       port->name, port->iobase, port->membase);
1215 
1216 	/*
1217 	 * We really do need global IRQs disabled here - we're going to
1218 	 * be frobbing the chips IRQ enable register to see if it exists.
1219 	 */
1220 	spin_lock_irqsave(&port->lock, flags);
1221 
1222 	up->capabilities = 0;
1223 	up->bugs = 0;
1224 
1225 	if (!(port->flags & UPF_BUGGY_UART)) {
1226 		/*
1227 		 * Do a simple existence test first; if we fail this,
1228 		 * there's no point trying anything else.
1229 		 *
1230 		 * 0x80 is used as a nonsense port to prevent against
1231 		 * false positives due to ISA bus float.  The
1232 		 * assumption is that 0x80 is a non-existent port;
1233 		 * which should be safe since include/asm/io.h also
1234 		 * makes this assumption.
1235 		 *
1236 		 * Note: this is safe as long as MCR bit 4 is clear
1237 		 * and the device is in "PC" mode.
1238 		 */
1239 		scratch = serial_in(up, UART_IER);
1240 		serial_out(up, UART_IER, 0);
1241 #ifdef __i386__
1242 		outb(0xff, 0x080);
1243 #endif
1244 		/*
1245 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1246 		 * 16C754B) allow only to modify them if an EFR bit is set.
1247 		 */
1248 		scratch2 = serial_in(up, UART_IER) & 0x0f;
1249 		serial_out(up, UART_IER, 0x0F);
1250 #ifdef __i386__
1251 		outb(0, 0x080);
1252 #endif
1253 		scratch3 = serial_in(up, UART_IER) & 0x0f;
1254 		serial_out(up, UART_IER, scratch);
1255 		if (scratch2 != 0 || scratch3 != 0x0F) {
1256 			/*
1257 			 * We failed; there's nothing here
1258 			 */
1259 			spin_unlock_irqrestore(&port->lock, flags);
1260 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1261 				       scratch2, scratch3);
1262 			goto out;
1263 		}
1264 	}
1265 
1266 	save_mcr = serial8250_in_MCR(up);
1267 	save_lcr = serial_in(up, UART_LCR);
1268 
1269 	/*
1270 	 * Check to see if a UART is really there.  Certain broken
1271 	 * internal modems based on the Rockwell chipset fail this
1272 	 * test, because they apparently don't implement the loopback
1273 	 * test mode.  So this test is skipped on the COM 1 through
1274 	 * COM 4 ports.  This *should* be safe, since no board
1275 	 * manufacturer would be stupid enough to design a board
1276 	 * that conflicts with COM 1-4 --- we hope!
1277 	 */
1278 	if (!(port->flags & UPF_SKIP_TEST)) {
1279 		serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1280 		status1 = serial_in(up, UART_MSR) & 0xF0;
1281 		serial8250_out_MCR(up, save_mcr);
1282 		if (status1 != 0x90) {
1283 			spin_unlock_irqrestore(&port->lock, flags);
1284 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1285 				       status1);
1286 			goto out;
1287 		}
1288 	}
1289 
1290 	/*
1291 	 * We're pretty sure there's a port here.  Lets find out what
1292 	 * type of port it is.  The IIR top two bits allows us to find
1293 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1294 	 * determines what we test for next.
1295 	 *
1296 	 * We also initialise the EFR (if any) to zero for later.  The
1297 	 * EFR occupies the same register location as the FCR and IIR.
1298 	 */
1299 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1300 	serial_out(up, UART_EFR, 0);
1301 	serial_out(up, UART_LCR, 0);
1302 
1303 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1304 	scratch = serial_in(up, UART_IIR) >> 6;
1305 
1306 	switch (scratch) {
1307 	case 0:
1308 		autoconfig_8250(up);
1309 		break;
1310 	case 1:
1311 		port->type = PORT_UNKNOWN;
1312 		break;
1313 	case 2:
1314 		port->type = PORT_16550;
1315 		break;
1316 	case 3:
1317 		autoconfig_16550a(up);
1318 		break;
1319 	}
1320 
1321 #ifdef CONFIG_SERIAL_8250_RSA
1322 	/*
1323 	 * Only probe for RSA ports if we got the region.
1324 	 */
1325 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1326 	    __enable_rsa(up))
1327 		port->type = PORT_RSA;
1328 #endif
1329 
1330 	serial_out(up, UART_LCR, save_lcr);
1331 
1332 	port->fifosize = uart_config[up->port.type].fifo_size;
1333 	old_capabilities = up->capabilities;
1334 	up->capabilities = uart_config[port->type].flags;
1335 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1336 
1337 	if (port->type == PORT_UNKNOWN)
1338 		goto out_lock;
1339 
1340 	/*
1341 	 * Reset the UART.
1342 	 */
1343 #ifdef CONFIG_SERIAL_8250_RSA
1344 	if (port->type == PORT_RSA)
1345 		serial_out(up, UART_RSA_FRR, 0);
1346 #endif
1347 	serial8250_out_MCR(up, save_mcr);
1348 	serial8250_clear_fifos(up);
1349 	serial_in(up, UART_RX);
1350 	if (up->capabilities & UART_CAP_UUE)
1351 		serial_out(up, UART_IER, UART_IER_UUE);
1352 	else
1353 		serial_out(up, UART_IER, 0);
1354 
1355 out_lock:
1356 	spin_unlock_irqrestore(&port->lock, flags);
1357 
1358 	/*
1359 	 * Check if the device is a Fintek F81216A
1360 	 */
1361 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1362 		fintek_8250_probe(up);
1363 
1364 	if (up->capabilities != old_capabilities) {
1365 		pr_warn("%s: detected caps %08x should be %08x\n",
1366 			port->name, old_capabilities, up->capabilities);
1367 	}
1368 out:
1369 	DEBUG_AUTOCONF("iir=%d ", scratch);
1370 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1371 }
1372 
1373 static void autoconfig_irq(struct uart_8250_port *up)
1374 {
1375 	struct uart_port *port = &up->port;
1376 	unsigned char save_mcr, save_ier;
1377 	unsigned char save_ICP = 0;
1378 	unsigned int ICP = 0;
1379 	unsigned long irqs;
1380 	int irq;
1381 
1382 	if (port->flags & UPF_FOURPORT) {
1383 		ICP = (port->iobase & 0xfe0) | 0x1f;
1384 		save_ICP = inb_p(ICP);
1385 		outb_p(0x80, ICP);
1386 		inb_p(ICP);
1387 	}
1388 
1389 	if (uart_console(port))
1390 		console_lock();
1391 
1392 	/* forget possible initially masked and pending IRQ */
1393 	probe_irq_off(probe_irq_on());
1394 	save_mcr = serial8250_in_MCR(up);
1395 	save_ier = serial_in(up, UART_IER);
1396 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1397 
1398 	irqs = probe_irq_on();
1399 	serial8250_out_MCR(up, 0);
1400 	udelay(10);
1401 	if (port->flags & UPF_FOURPORT) {
1402 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1403 	} else {
1404 		serial8250_out_MCR(up,
1405 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1406 	}
1407 	serial_out(up, UART_IER, 0x0f);	/* enable all intrs */
1408 	serial_in(up, UART_LSR);
1409 	serial_in(up, UART_RX);
1410 	serial_in(up, UART_IIR);
1411 	serial_in(up, UART_MSR);
1412 	serial_out(up, UART_TX, 0xFF);
1413 	udelay(20);
1414 	irq = probe_irq_off(irqs);
1415 
1416 	serial8250_out_MCR(up, save_mcr);
1417 	serial_out(up, UART_IER, save_ier);
1418 
1419 	if (port->flags & UPF_FOURPORT)
1420 		outb_p(save_ICP, ICP);
1421 
1422 	if (uart_console(port))
1423 		console_unlock();
1424 
1425 	port->irq = (irq > 0) ? irq : 0;
1426 }
1427 
1428 static void serial8250_stop_rx(struct uart_port *port)
1429 {
1430 	struct uart_8250_port *up = up_to_u8250p(port);
1431 
1432 	serial8250_rpm_get(up);
1433 
1434 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1435 	up->port.read_status_mask &= ~UART_LSR_DR;
1436 	serial_port_out(port, UART_IER, up->ier);
1437 
1438 	serial8250_rpm_put(up);
1439 }
1440 
1441 static void __do_stop_tx_rs485(struct uart_8250_port *p)
1442 {
1443 	serial8250_em485_rts_after_send(p);
1444 
1445 	/*
1446 	 * Empty the RX FIFO, we are not interested in anything
1447 	 * received during the half-duplex transmission.
1448 	 * Enable previously disabled RX interrupts.
1449 	 */
1450 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1451 		serial8250_clear_and_reinit_fifos(p);
1452 
1453 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1454 		serial_port_out(&p->port, UART_IER, p->ier);
1455 	}
1456 }
1457 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1458 {
1459 	struct uart_8250_em485 *em485;
1460 	struct uart_8250_port *p;
1461 	unsigned long flags;
1462 
1463 	em485 = container_of(t, struct uart_8250_em485, stop_tx_timer);
1464 	p = em485->port;
1465 
1466 	serial8250_rpm_get(p);
1467 	spin_lock_irqsave(&p->port.lock, flags);
1468 	if (em485->active_timer == &em485->stop_tx_timer) {
1469 		__do_stop_tx_rs485(p);
1470 		em485->active_timer = NULL;
1471 	}
1472 	spin_unlock_irqrestore(&p->port.lock, flags);
1473 	serial8250_rpm_put(p);
1474 	return HRTIMER_NORESTART;
1475 }
1476 
1477 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1478 {
1479 	long sec = msec / 1000;
1480 	long nsec = (msec % 1000) * 1000000;
1481 	ktime_t t = ktime_set(sec, nsec);
1482 
1483 	hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1484 }
1485 
1486 static void __stop_tx_rs485(struct uart_8250_port *p)
1487 {
1488 	struct uart_8250_em485 *em485 = p->em485;
1489 
1490 	/*
1491 	 * __do_stop_tx_rs485 is going to set RTS according to config
1492 	 * AND flush RX FIFO if required.
1493 	 */
1494 	if (p->port.rs485.delay_rts_after_send > 0) {
1495 		em485->active_timer = &em485->stop_tx_timer;
1496 		start_hrtimer_ms(&em485->stop_tx_timer,
1497 				   p->port.rs485.delay_rts_after_send);
1498 	} else {
1499 		__do_stop_tx_rs485(p);
1500 	}
1501 }
1502 
1503 static inline void __do_stop_tx(struct uart_8250_port *p)
1504 {
1505 	if (p->ier & UART_IER_THRI) {
1506 		p->ier &= ~UART_IER_THRI;
1507 		serial_out(p, UART_IER, p->ier);
1508 		serial8250_rpm_put_tx(p);
1509 	}
1510 }
1511 
1512 static inline void __stop_tx(struct uart_8250_port *p)
1513 {
1514 	struct uart_8250_em485 *em485 = p->em485;
1515 
1516 	if (em485) {
1517 		unsigned char lsr = serial_in(p, UART_LSR);
1518 		/*
1519 		 * To provide required timeing and allow FIFO transfer,
1520 		 * __stop_tx_rs485() must be called only when both FIFO and
1521 		 * shift register are empty. It is for device driver to enable
1522 		 * interrupt on TEMT.
1523 		 */
1524 		if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1525 			return;
1526 
1527 		em485->active_timer = NULL;
1528 
1529 		__stop_tx_rs485(p);
1530 	}
1531 	__do_stop_tx(p);
1532 }
1533 
1534 static void serial8250_stop_tx(struct uart_port *port)
1535 {
1536 	struct uart_8250_port *up = up_to_u8250p(port);
1537 
1538 	serial8250_rpm_get(up);
1539 	__stop_tx(up);
1540 
1541 	/*
1542 	 * We really want to stop the transmitter from sending.
1543 	 */
1544 	if (port->type == PORT_16C950) {
1545 		up->acr |= UART_ACR_TXDIS;
1546 		serial_icr_write(up, UART_ACR, up->acr);
1547 	}
1548 	serial8250_rpm_put(up);
1549 }
1550 
1551 static inline void __start_tx(struct uart_port *port)
1552 {
1553 	struct uart_8250_port *up = up_to_u8250p(port);
1554 
1555 	if (up->dma && !up->dma->tx_dma(up))
1556 		return;
1557 
1558 	if (!(up->ier & UART_IER_THRI)) {
1559 		up->ier |= UART_IER_THRI;
1560 		serial_port_out(port, UART_IER, up->ier);
1561 
1562 		if (up->bugs & UART_BUG_TXEN) {
1563 			unsigned char lsr;
1564 
1565 			lsr = serial_in(up, UART_LSR);
1566 			up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1567 			if (lsr & UART_LSR_THRE)
1568 				serial8250_tx_chars(up);
1569 		}
1570 	}
1571 
1572 	/*
1573 	 * Re-enable the transmitter if we disabled it.
1574 	 */
1575 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1576 		up->acr &= ~UART_ACR_TXDIS;
1577 		serial_icr_write(up, UART_ACR, up->acr);
1578 	}
1579 }
1580 
1581 static inline void start_tx_rs485(struct uart_port *port)
1582 {
1583 	struct uart_8250_port *up = up_to_u8250p(port);
1584 	struct uart_8250_em485 *em485 = up->em485;
1585 	unsigned char mcr;
1586 
1587 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1588 		serial8250_stop_rx(&up->port);
1589 
1590 	em485->active_timer = NULL;
1591 
1592 	mcr = serial8250_in_MCR(up);
1593 	if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1594 	    !!(mcr & UART_MCR_RTS)) {
1595 		if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1596 			mcr |= UART_MCR_RTS;
1597 		else
1598 			mcr &= ~UART_MCR_RTS;
1599 		serial8250_out_MCR(up, mcr);
1600 
1601 		if (up->port.rs485.delay_rts_before_send > 0) {
1602 			em485->active_timer = &em485->start_tx_timer;
1603 			start_hrtimer_ms(&em485->start_tx_timer,
1604 					 up->port.rs485.delay_rts_before_send);
1605 			return;
1606 		}
1607 	}
1608 
1609 	__start_tx(port);
1610 }
1611 
1612 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1613 {
1614 	struct uart_8250_em485 *em485;
1615 	struct uart_8250_port *p;
1616 	unsigned long flags;
1617 
1618 	em485 = container_of(t, struct uart_8250_em485, start_tx_timer);
1619 	p = em485->port;
1620 
1621 	spin_lock_irqsave(&p->port.lock, flags);
1622 	if (em485->active_timer == &em485->start_tx_timer) {
1623 		__start_tx(&p->port);
1624 		em485->active_timer = NULL;
1625 	}
1626 	spin_unlock_irqrestore(&p->port.lock, flags);
1627 	return HRTIMER_NORESTART;
1628 }
1629 
1630 static void serial8250_start_tx(struct uart_port *port)
1631 {
1632 	struct uart_8250_port *up = up_to_u8250p(port);
1633 	struct uart_8250_em485 *em485 = up->em485;
1634 
1635 	serial8250_rpm_get_tx(up);
1636 
1637 	if (em485 &&
1638 	    em485->active_timer == &em485->start_tx_timer)
1639 		return;
1640 
1641 	if (em485)
1642 		start_tx_rs485(port);
1643 	else
1644 		__start_tx(port);
1645 }
1646 
1647 static void serial8250_throttle(struct uart_port *port)
1648 {
1649 	port->throttle(port);
1650 }
1651 
1652 static void serial8250_unthrottle(struct uart_port *port)
1653 {
1654 	port->unthrottle(port);
1655 }
1656 
1657 static void serial8250_disable_ms(struct uart_port *port)
1658 {
1659 	struct uart_8250_port *up = up_to_u8250p(port);
1660 
1661 	/* no MSR capabilities */
1662 	if (up->bugs & UART_BUG_NOMSR)
1663 		return;
1664 
1665 	up->ier &= ~UART_IER_MSI;
1666 	serial_port_out(port, UART_IER, up->ier);
1667 }
1668 
1669 static void serial8250_enable_ms(struct uart_port *port)
1670 {
1671 	struct uart_8250_port *up = up_to_u8250p(port);
1672 
1673 	/* no MSR capabilities */
1674 	if (up->bugs & UART_BUG_NOMSR)
1675 		return;
1676 
1677 	up->ier |= UART_IER_MSI;
1678 
1679 	serial8250_rpm_get(up);
1680 	serial_port_out(port, UART_IER, up->ier);
1681 	serial8250_rpm_put(up);
1682 }
1683 
1684 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1685 {
1686 	struct uart_port *port = &up->port;
1687 	unsigned char ch;
1688 	char flag = TTY_NORMAL;
1689 
1690 	if (likely(lsr & UART_LSR_DR))
1691 		ch = serial_in(up, UART_RX);
1692 	else
1693 		/*
1694 		 * Intel 82571 has a Serial Over Lan device that will
1695 		 * set UART_LSR_BI without setting UART_LSR_DR when
1696 		 * it receives a break. To avoid reading from the
1697 		 * receive buffer without UART_LSR_DR bit set, we
1698 		 * just force the read character to be 0
1699 		 */
1700 		ch = 0;
1701 
1702 	port->icount.rx++;
1703 
1704 	lsr |= up->lsr_saved_flags;
1705 	up->lsr_saved_flags = 0;
1706 
1707 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1708 		if (lsr & UART_LSR_BI) {
1709 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1710 			port->icount.brk++;
1711 			/*
1712 			 * We do the SysRQ and SAK checking
1713 			 * here because otherwise the break
1714 			 * may get masked by ignore_status_mask
1715 			 * or read_status_mask.
1716 			 */
1717 			if (uart_handle_break(port))
1718 				return;
1719 		} else if (lsr & UART_LSR_PE)
1720 			port->icount.parity++;
1721 		else if (lsr & UART_LSR_FE)
1722 			port->icount.frame++;
1723 		if (lsr & UART_LSR_OE)
1724 			port->icount.overrun++;
1725 
1726 		/*
1727 		 * Mask off conditions which should be ignored.
1728 		 */
1729 		lsr &= port->read_status_mask;
1730 
1731 		if (lsr & UART_LSR_BI) {
1732 			pr_debug("%s: handling break\n", __func__);
1733 			flag = TTY_BREAK;
1734 		} else if (lsr & UART_LSR_PE)
1735 			flag = TTY_PARITY;
1736 		else if (lsr & UART_LSR_FE)
1737 			flag = TTY_FRAME;
1738 	}
1739 	if (uart_prepare_sysrq_char(port, ch))
1740 		return;
1741 
1742 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1743 }
1744 EXPORT_SYMBOL_GPL(serial8250_read_char);
1745 
1746 /*
1747  * serial8250_rx_chars: processes according to the passed in LSR
1748  * value, and returns the remaining LSR bits not handled
1749  * by this Rx routine.
1750  */
1751 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1752 {
1753 	struct uart_port *port = &up->port;
1754 	int max_count = 256;
1755 
1756 	do {
1757 		serial8250_read_char(up, lsr);
1758 		if (--max_count == 0)
1759 			break;
1760 		lsr = serial_in(up, UART_LSR);
1761 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1762 
1763 	tty_flip_buffer_push(&port->state->port);
1764 	return lsr;
1765 }
1766 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1767 
1768 void serial8250_tx_chars(struct uart_8250_port *up)
1769 {
1770 	struct uart_port *port = &up->port;
1771 	struct circ_buf *xmit = &port->state->xmit;
1772 	int count;
1773 
1774 	if (port->x_char) {
1775 		serial_out(up, UART_TX, port->x_char);
1776 		port->icount.tx++;
1777 		port->x_char = 0;
1778 		return;
1779 	}
1780 	if (uart_tx_stopped(port)) {
1781 		serial8250_stop_tx(port);
1782 		return;
1783 	}
1784 	if (uart_circ_empty(xmit)) {
1785 		__stop_tx(up);
1786 		return;
1787 	}
1788 
1789 	count = up->tx_loadsz;
1790 	do {
1791 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1792 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1793 		port->icount.tx++;
1794 		if (uart_circ_empty(xmit))
1795 			break;
1796 		if ((up->capabilities & UART_CAP_HFIFO) &&
1797 		    (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1798 			break;
1799 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1800 		if ((up->capabilities & UART_CAP_MINI) &&
1801 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1802 			break;
1803 	} while (--count > 0);
1804 
1805 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1806 		uart_write_wakeup(port);
1807 
1808 	/*
1809 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1810 	 * HW can go idle. So we get here once again with empty FIFO and disable
1811 	 * the interrupt and RPM in __stop_tx()
1812 	 */
1813 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1814 		__stop_tx(up);
1815 }
1816 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1817 
1818 /* Caller holds uart port lock */
1819 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1820 {
1821 	struct uart_port *port = &up->port;
1822 	unsigned int status = serial_in(up, UART_MSR);
1823 
1824 	status |= up->msr_saved_flags;
1825 	up->msr_saved_flags = 0;
1826 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1827 	    port->state != NULL) {
1828 		if (status & UART_MSR_TERI)
1829 			port->icount.rng++;
1830 		if (status & UART_MSR_DDSR)
1831 			port->icount.dsr++;
1832 		if (status & UART_MSR_DDCD)
1833 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1834 		if (status & UART_MSR_DCTS)
1835 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1836 
1837 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1838 	}
1839 
1840 	return status;
1841 }
1842 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1843 
1844 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1845 {
1846 	switch (iir & 0x3f) {
1847 	case UART_IIR_RX_TIMEOUT:
1848 		serial8250_rx_dma_flush(up);
1849 		/* fall-through */
1850 	case UART_IIR_RLSI:
1851 		return true;
1852 	}
1853 	return up->dma->rx_dma(up);
1854 }
1855 
1856 /*
1857  * This handles the interrupt from one port.
1858  */
1859 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1860 {
1861 	unsigned char status;
1862 	unsigned long flags;
1863 	struct uart_8250_port *up = up_to_u8250p(port);
1864 
1865 	if (iir & UART_IIR_NO_INT)
1866 		return 0;
1867 
1868 	spin_lock_irqsave(&port->lock, flags);
1869 
1870 	status = serial_port_in(port, UART_LSR);
1871 
1872 	if (status & (UART_LSR_DR | UART_LSR_BI) &&
1873 	    iir & UART_IIR_RDI) {
1874 		if (!up->dma || handle_rx_dma(up, iir))
1875 			status = serial8250_rx_chars(up, status);
1876 	}
1877 	serial8250_modem_status(up);
1878 	if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
1879 		serial8250_tx_chars(up);
1880 
1881 	uart_unlock_and_check_sysrq(port, flags);
1882 	return 1;
1883 }
1884 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1885 
1886 static int serial8250_default_handle_irq(struct uart_port *port)
1887 {
1888 	struct uart_8250_port *up = up_to_u8250p(port);
1889 	unsigned int iir;
1890 	int ret;
1891 
1892 	serial8250_rpm_get(up);
1893 
1894 	iir = serial_port_in(port, UART_IIR);
1895 	ret = serial8250_handle_irq(port, iir);
1896 
1897 	serial8250_rpm_put(up);
1898 	return ret;
1899 }
1900 
1901 /*
1902  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1903  * have a programmable TX threshold that triggers the THRE interrupt in
1904  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1905  * has space available. Load it up with tx_loadsz bytes.
1906  */
1907 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1908 {
1909 	unsigned long flags;
1910 	unsigned int iir = serial_port_in(port, UART_IIR);
1911 
1912 	/* TX Threshold IRQ triggered so load up FIFO */
1913 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1914 		struct uart_8250_port *up = up_to_u8250p(port);
1915 
1916 		spin_lock_irqsave(&port->lock, flags);
1917 		serial8250_tx_chars(up);
1918 		spin_unlock_irqrestore(&port->lock, flags);
1919 	}
1920 
1921 	iir = serial_port_in(port, UART_IIR);
1922 	return serial8250_handle_irq(port, iir);
1923 }
1924 
1925 static unsigned int serial8250_tx_empty(struct uart_port *port)
1926 {
1927 	struct uart_8250_port *up = up_to_u8250p(port);
1928 	unsigned long flags;
1929 	unsigned int lsr;
1930 
1931 	serial8250_rpm_get(up);
1932 
1933 	spin_lock_irqsave(&port->lock, flags);
1934 	lsr = serial_port_in(port, UART_LSR);
1935 	up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1936 	spin_unlock_irqrestore(&port->lock, flags);
1937 
1938 	serial8250_rpm_put(up);
1939 
1940 	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1941 }
1942 
1943 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1944 {
1945 	struct uart_8250_port *up = up_to_u8250p(port);
1946 	unsigned int status;
1947 	unsigned int ret;
1948 
1949 	serial8250_rpm_get(up);
1950 	status = serial8250_modem_status(up);
1951 	serial8250_rpm_put(up);
1952 
1953 	ret = 0;
1954 	if (status & UART_MSR_DCD)
1955 		ret |= TIOCM_CAR;
1956 	if (status & UART_MSR_RI)
1957 		ret |= TIOCM_RNG;
1958 	if (status & UART_MSR_DSR)
1959 		ret |= TIOCM_DSR;
1960 	if (status & UART_MSR_CTS)
1961 		ret |= TIOCM_CTS;
1962 	return ret;
1963 }
1964 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1965 
1966 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1967 {
1968 	if (port->get_mctrl)
1969 		return port->get_mctrl(port);
1970 	return serial8250_do_get_mctrl(port);
1971 }
1972 
1973 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1974 {
1975 	struct uart_8250_port *up = up_to_u8250p(port);
1976 	unsigned char mcr = 0;
1977 
1978 	if (mctrl & TIOCM_RTS)
1979 		mcr |= UART_MCR_RTS;
1980 	if (mctrl & TIOCM_DTR)
1981 		mcr |= UART_MCR_DTR;
1982 	if (mctrl & TIOCM_OUT1)
1983 		mcr |= UART_MCR_OUT1;
1984 	if (mctrl & TIOCM_OUT2)
1985 		mcr |= UART_MCR_OUT2;
1986 	if (mctrl & TIOCM_LOOP)
1987 		mcr |= UART_MCR_LOOP;
1988 
1989 	mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1990 
1991 	serial8250_out_MCR(up, mcr);
1992 }
1993 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1994 
1995 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1996 {
1997 	if (port->set_mctrl)
1998 		port->set_mctrl(port, mctrl);
1999 	else
2000 		serial8250_do_set_mctrl(port, mctrl);
2001 }
2002 
2003 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2004 {
2005 	struct uart_8250_port *up = up_to_u8250p(port);
2006 	unsigned long flags;
2007 
2008 	serial8250_rpm_get(up);
2009 	spin_lock_irqsave(&port->lock, flags);
2010 	if (break_state == -1)
2011 		up->lcr |= UART_LCR_SBC;
2012 	else
2013 		up->lcr &= ~UART_LCR_SBC;
2014 	serial_port_out(port, UART_LCR, up->lcr);
2015 	spin_unlock_irqrestore(&port->lock, flags);
2016 	serial8250_rpm_put(up);
2017 }
2018 
2019 /*
2020  *	Wait for transmitter & holding register to empty
2021  */
2022 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2023 {
2024 	unsigned int status, tmout = 10000;
2025 
2026 	/* Wait up to 10ms for the character(s) to be sent. */
2027 	for (;;) {
2028 		status = serial_in(up, UART_LSR);
2029 
2030 		up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2031 
2032 		if ((status & bits) == bits)
2033 			break;
2034 		if (--tmout == 0)
2035 			break;
2036 		udelay(1);
2037 		touch_nmi_watchdog();
2038 	}
2039 
2040 	/* Wait up to 1s for flow control if necessary */
2041 	if (up->port.flags & UPF_CONS_FLOW) {
2042 		for (tmout = 1000000; tmout; tmout--) {
2043 			unsigned int msr = serial_in(up, UART_MSR);
2044 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2045 			if (msr & UART_MSR_CTS)
2046 				break;
2047 			udelay(1);
2048 			touch_nmi_watchdog();
2049 		}
2050 	}
2051 }
2052 
2053 #ifdef CONFIG_CONSOLE_POLL
2054 /*
2055  * Console polling routines for writing and reading from the uart while
2056  * in an interrupt or debug context.
2057  */
2058 
2059 static int serial8250_get_poll_char(struct uart_port *port)
2060 {
2061 	struct uart_8250_port *up = up_to_u8250p(port);
2062 	unsigned char lsr;
2063 	int status;
2064 
2065 	serial8250_rpm_get(up);
2066 
2067 	lsr = serial_port_in(port, UART_LSR);
2068 
2069 	if (!(lsr & UART_LSR_DR)) {
2070 		status = NO_POLL_CHAR;
2071 		goto out;
2072 	}
2073 
2074 	status = serial_port_in(port, UART_RX);
2075 out:
2076 	serial8250_rpm_put(up);
2077 	return status;
2078 }
2079 
2080 
2081 static void serial8250_put_poll_char(struct uart_port *port,
2082 			 unsigned char c)
2083 {
2084 	unsigned int ier;
2085 	struct uart_8250_port *up = up_to_u8250p(port);
2086 
2087 	serial8250_rpm_get(up);
2088 	/*
2089 	 *	First save the IER then disable the interrupts
2090 	 */
2091 	ier = serial_port_in(port, UART_IER);
2092 	if (up->capabilities & UART_CAP_UUE)
2093 		serial_port_out(port, UART_IER, UART_IER_UUE);
2094 	else
2095 		serial_port_out(port, UART_IER, 0);
2096 
2097 	wait_for_xmitr(up, BOTH_EMPTY);
2098 	/*
2099 	 *	Send the character out.
2100 	 */
2101 	serial_port_out(port, UART_TX, c);
2102 
2103 	/*
2104 	 *	Finally, wait for transmitter to become empty
2105 	 *	and restore the IER
2106 	 */
2107 	wait_for_xmitr(up, BOTH_EMPTY);
2108 	serial_port_out(port, UART_IER, ier);
2109 	serial8250_rpm_put(up);
2110 }
2111 
2112 #endif /* CONFIG_CONSOLE_POLL */
2113 
2114 int serial8250_do_startup(struct uart_port *port)
2115 {
2116 	struct uart_8250_port *up = up_to_u8250p(port);
2117 	unsigned long flags;
2118 	unsigned char lsr, iir;
2119 	int retval;
2120 
2121 	if (!port->fifosize)
2122 		port->fifosize = uart_config[port->type].fifo_size;
2123 	if (!up->tx_loadsz)
2124 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2125 	if (!up->capabilities)
2126 		up->capabilities = uart_config[port->type].flags;
2127 	up->mcr = 0;
2128 
2129 	if (port->iotype != up->cur_iotype)
2130 		set_io_from_upio(port);
2131 
2132 	serial8250_rpm_get(up);
2133 	if (port->type == PORT_16C950) {
2134 		/* Wake up and initialize UART */
2135 		up->acr = 0;
2136 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2137 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2138 		serial_port_out(port, UART_IER, 0);
2139 		serial_port_out(port, UART_LCR, 0);
2140 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2141 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2142 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2143 		serial_port_out(port, UART_LCR, 0);
2144 	}
2145 
2146 	if (port->type == PORT_DA830) {
2147 		/* Reset the port */
2148 		serial_port_out(port, UART_IER, 0);
2149 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2150 		mdelay(10);
2151 
2152 		/* Enable Tx, Rx and free run mode */
2153 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2154 				UART_DA830_PWREMU_MGMT_UTRST |
2155 				UART_DA830_PWREMU_MGMT_URRST |
2156 				UART_DA830_PWREMU_MGMT_FREE);
2157 	}
2158 
2159 	if (port->type == PORT_NPCM) {
2160 		/*
2161 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2162 		 * register). Enable it, and set TIOC (timeout interrupt
2163 		 * comparator) to be 0x20 for correct operation.
2164 		 */
2165 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2166 	}
2167 
2168 #ifdef CONFIG_SERIAL_8250_RSA
2169 	/*
2170 	 * If this is an RSA port, see if we can kick it up to the
2171 	 * higher speed clock.
2172 	 */
2173 	enable_rsa(up);
2174 #endif
2175 
2176 	if (port->type == PORT_XR17V35X) {
2177 		/*
2178 		 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2179 		 * MCR [7:5] and MSR [7:0]
2180 		 */
2181 		serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2182 
2183 		/*
2184 		 * Make sure all interrups are masked until initialization is
2185 		 * complete and the FIFOs are cleared
2186 		 */
2187 		serial_port_out(port, UART_IER, 0);
2188 	}
2189 
2190 	/*
2191 	 * Clear the FIFO buffers and disable them.
2192 	 * (they will be reenabled in set_termios())
2193 	 */
2194 	serial8250_clear_fifos(up);
2195 
2196 	/*
2197 	 * Clear the interrupt registers.
2198 	 */
2199 	serial_port_in(port, UART_LSR);
2200 	serial_port_in(port, UART_RX);
2201 	serial_port_in(port, UART_IIR);
2202 	serial_port_in(port, UART_MSR);
2203 	if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2204 		serial_port_in(port, UART_EXAR_INT0);
2205 
2206 	/*
2207 	 * At this point, there's no way the LSR could still be 0xff;
2208 	 * if it is, then bail out, because there's likely no UART
2209 	 * here.
2210 	 */
2211 	if (!(port->flags & UPF_BUGGY_UART) &&
2212 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2213 		pr_info_ratelimited("%s: LSR safety check engaged!\n", port->name);
2214 		retval = -ENODEV;
2215 		goto out;
2216 	}
2217 
2218 	/*
2219 	 * For a XR16C850, we need to set the trigger levels
2220 	 */
2221 	if (port->type == PORT_16850) {
2222 		unsigned char fctr;
2223 
2224 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2225 
2226 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2227 		serial_port_out(port, UART_FCTR,
2228 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2229 		serial_port_out(port, UART_TRG, UART_TRG_96);
2230 		serial_port_out(port, UART_FCTR,
2231 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2232 		serial_port_out(port, UART_TRG, UART_TRG_96);
2233 
2234 		serial_port_out(port, UART_LCR, 0);
2235 	}
2236 
2237 	/*
2238 	 * For the Altera 16550 variants, set TX threshold trigger level.
2239 	 */
2240 	if (((port->type == PORT_ALTR_16550_F32) ||
2241 	     (port->type == PORT_ALTR_16550_F64) ||
2242 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2243 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2244 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2245 			pr_err("%s TX FIFO Threshold errors, skipping\n",
2246 			       port->name);
2247 		} else {
2248 			serial_port_out(port, UART_ALTR_AFR,
2249 					UART_ALTR_EN_TXFIFO_LW);
2250 			serial_port_out(port, UART_ALTR_TX_LOW,
2251 					port->fifosize - up->tx_loadsz);
2252 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2253 		}
2254 	}
2255 
2256 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2257 		unsigned char iir1;
2258 		/*
2259 		 * Test for UARTs that do not reassert THRE when the
2260 		 * transmitter is idle and the interrupt has already
2261 		 * been cleared.  Real 16550s should always reassert
2262 		 * this interrupt whenever the transmitter is idle and
2263 		 * the interrupt is enabled.  Delays are necessary to
2264 		 * allow register changes to become visible.
2265 		 */
2266 		spin_lock_irqsave(&port->lock, flags);
2267 		if (up->port.irqflags & IRQF_SHARED)
2268 			disable_irq_nosync(port->irq);
2269 
2270 		wait_for_xmitr(up, UART_LSR_THRE);
2271 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2272 		udelay(1); /* allow THRE to set */
2273 		iir1 = serial_port_in(port, UART_IIR);
2274 		serial_port_out(port, UART_IER, 0);
2275 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2276 		udelay(1); /* allow a working UART time to re-assert THRE */
2277 		iir = serial_port_in(port, UART_IIR);
2278 		serial_port_out(port, UART_IER, 0);
2279 
2280 		if (port->irqflags & IRQF_SHARED)
2281 			enable_irq(port->irq);
2282 		spin_unlock_irqrestore(&port->lock, flags);
2283 
2284 		/*
2285 		 * If the interrupt is not reasserted, or we otherwise
2286 		 * don't trust the iir, setup a timer to kick the UART
2287 		 * on a regular basis.
2288 		 */
2289 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2290 		    up->port.flags & UPF_BUG_THRE) {
2291 			up->bugs |= UART_BUG_THRE;
2292 		}
2293 	}
2294 
2295 	retval = up->ops->setup_irq(up);
2296 	if (retval)
2297 		goto out;
2298 
2299 	/*
2300 	 * Now, initialize the UART
2301 	 */
2302 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2303 
2304 	spin_lock_irqsave(&port->lock, flags);
2305 	if (up->port.flags & UPF_FOURPORT) {
2306 		if (!up->port.irq)
2307 			up->port.mctrl |= TIOCM_OUT1;
2308 	} else
2309 		/*
2310 		 * Most PC uarts need OUT2 raised to enable interrupts.
2311 		 */
2312 		if (port->irq)
2313 			up->port.mctrl |= TIOCM_OUT2;
2314 
2315 	serial8250_set_mctrl(port, port->mctrl);
2316 
2317 	/*
2318 	 * Serial over Lan (SoL) hack:
2319 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2320 	 * used for Serial Over Lan.  Those chips take a longer time than a
2321 	 * normal serial device to signalize that a transmission data was
2322 	 * queued. Due to that, the above test generally fails. One solution
2323 	 * would be to delay the reading of iir. However, this is not
2324 	 * reliable, since the timeout is variable. So, let's just don't
2325 	 * test if we receive TX irq.  This way, we'll never enable
2326 	 * UART_BUG_TXEN.
2327 	 */
2328 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2329 		goto dont_test_tx_en;
2330 
2331 	/*
2332 	 * Do a quick test to see if we receive an interrupt when we enable
2333 	 * the TX irq.
2334 	 */
2335 	serial_port_out(port, UART_IER, UART_IER_THRI);
2336 	lsr = serial_port_in(port, UART_LSR);
2337 	iir = serial_port_in(port, UART_IIR);
2338 	serial_port_out(port, UART_IER, 0);
2339 
2340 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2341 		if (!(up->bugs & UART_BUG_TXEN)) {
2342 			up->bugs |= UART_BUG_TXEN;
2343 			pr_debug("%s - enabling bad tx status workarounds\n",
2344 				 port->name);
2345 		}
2346 	} else {
2347 		up->bugs &= ~UART_BUG_TXEN;
2348 	}
2349 
2350 dont_test_tx_en:
2351 	spin_unlock_irqrestore(&port->lock, flags);
2352 
2353 	/*
2354 	 * Clear the interrupt registers again for luck, and clear the
2355 	 * saved flags to avoid getting false values from polling
2356 	 * routines or the previous session.
2357 	 */
2358 	serial_port_in(port, UART_LSR);
2359 	serial_port_in(port, UART_RX);
2360 	serial_port_in(port, UART_IIR);
2361 	serial_port_in(port, UART_MSR);
2362 	if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X))
2363 		serial_port_in(port, UART_EXAR_INT0);
2364 	up->lsr_saved_flags = 0;
2365 	up->msr_saved_flags = 0;
2366 
2367 	/*
2368 	 * Request DMA channels for both RX and TX.
2369 	 */
2370 	if (up->dma) {
2371 		retval = serial8250_request_dma(up);
2372 		if (retval) {
2373 			pr_warn_ratelimited("%s - failed to request DMA\n",
2374 					    port->name);
2375 			up->dma = NULL;
2376 		}
2377 	}
2378 
2379 	/*
2380 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2381 	 * enable until after the FIFOs are enabled; otherwise, an already-
2382 	 * active sender can swamp the interrupt handler with "too much work".
2383 	 */
2384 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2385 
2386 	if (port->flags & UPF_FOURPORT) {
2387 		unsigned int icp;
2388 		/*
2389 		 * Enable interrupts on the AST Fourport board
2390 		 */
2391 		icp = (port->iobase & 0xfe0) | 0x01f;
2392 		outb_p(0x80, icp);
2393 		inb_p(icp);
2394 	}
2395 	retval = 0;
2396 out:
2397 	serial8250_rpm_put(up);
2398 	return retval;
2399 }
2400 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2401 
2402 static int serial8250_startup(struct uart_port *port)
2403 {
2404 	if (port->startup)
2405 		return port->startup(port);
2406 	return serial8250_do_startup(port);
2407 }
2408 
2409 void serial8250_do_shutdown(struct uart_port *port)
2410 {
2411 	struct uart_8250_port *up = up_to_u8250p(port);
2412 	unsigned long flags;
2413 
2414 	serial8250_rpm_get(up);
2415 	/*
2416 	 * Disable interrupts from this port
2417 	 */
2418 	spin_lock_irqsave(&port->lock, flags);
2419 	up->ier = 0;
2420 	serial_port_out(port, UART_IER, 0);
2421 	spin_unlock_irqrestore(&port->lock, flags);
2422 
2423 	synchronize_irq(port->irq);
2424 
2425 	if (up->dma)
2426 		serial8250_release_dma(up);
2427 
2428 	spin_lock_irqsave(&port->lock, flags);
2429 	if (port->flags & UPF_FOURPORT) {
2430 		/* reset interrupts on the AST Fourport board */
2431 		inb((port->iobase & 0xfe0) | 0x1f);
2432 		port->mctrl |= TIOCM_OUT1;
2433 	} else
2434 		port->mctrl &= ~TIOCM_OUT2;
2435 
2436 	serial8250_set_mctrl(port, port->mctrl);
2437 	spin_unlock_irqrestore(&port->lock, flags);
2438 
2439 	/*
2440 	 * Disable break condition and FIFOs
2441 	 */
2442 	serial_port_out(port, UART_LCR,
2443 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2444 	serial8250_clear_fifos(up);
2445 
2446 #ifdef CONFIG_SERIAL_8250_RSA
2447 	/*
2448 	 * Reset the RSA board back to 115kbps compat mode.
2449 	 */
2450 	disable_rsa(up);
2451 #endif
2452 
2453 	/*
2454 	 * Read data port to reset things, and then unlink from
2455 	 * the IRQ chain.
2456 	 */
2457 	serial_port_in(port, UART_RX);
2458 	serial8250_rpm_put(up);
2459 
2460 	up->ops->release_irq(up);
2461 }
2462 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2463 
2464 static void serial8250_shutdown(struct uart_port *port)
2465 {
2466 	if (port->shutdown)
2467 		port->shutdown(port);
2468 	else
2469 		serial8250_do_shutdown(port);
2470 }
2471 
2472 /*
2473  * XR17V35x UARTs have an extra fractional divisor register (DLD)
2474  * Calculate divisor with extra 4-bit fractional portion
2475  */
2476 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2477 					 unsigned int baud,
2478 					 unsigned int *frac)
2479 {
2480 	struct uart_port *port = &up->port;
2481 	unsigned int quot_16;
2482 
2483 	quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2484 	*frac = quot_16 & 0x0f;
2485 
2486 	return quot_16 >> 4;
2487 }
2488 
2489 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2490 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2491 		unsigned int baud)
2492 {
2493 	struct uart_port *port = &up->port;
2494 
2495 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2496 }
2497 
2498 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2499 					      unsigned int baud,
2500 					      unsigned int *frac)
2501 {
2502 	struct uart_8250_port *up = up_to_u8250p(port);
2503 	unsigned int quot;
2504 
2505 	/*
2506 	 * Handle magic divisors for baud rates above baud_base on
2507 	 * SMSC SuperIO chips.
2508 	 *
2509 	 */
2510 	if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2511 	    baud == (port->uartclk/4))
2512 		quot = 0x8001;
2513 	else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2514 		 baud == (port->uartclk/8))
2515 		quot = 0x8002;
2516 	else if (up->port.type == PORT_XR17V35X)
2517 		quot = xr17v35x_get_divisor(up, baud, frac);
2518 	else if (up->port.type == PORT_NPCM)
2519 		quot = npcm_get_divisor(up, baud);
2520 	else
2521 		quot = uart_get_divisor(port, baud);
2522 
2523 	/*
2524 	 * Oxford Semi 952 rev B workaround
2525 	 */
2526 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2527 		quot++;
2528 
2529 	return quot;
2530 }
2531 
2532 static unsigned int serial8250_get_divisor(struct uart_port *port,
2533 					   unsigned int baud,
2534 					   unsigned int *frac)
2535 {
2536 	if (port->get_divisor)
2537 		return port->get_divisor(port, baud, frac);
2538 
2539 	return serial8250_do_get_divisor(port, baud, frac);
2540 }
2541 
2542 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2543 					    tcflag_t c_cflag)
2544 {
2545 	unsigned char cval;
2546 
2547 	switch (c_cflag & CSIZE) {
2548 	case CS5:
2549 		cval = UART_LCR_WLEN5;
2550 		break;
2551 	case CS6:
2552 		cval = UART_LCR_WLEN6;
2553 		break;
2554 	case CS7:
2555 		cval = UART_LCR_WLEN7;
2556 		break;
2557 	default:
2558 	case CS8:
2559 		cval = UART_LCR_WLEN8;
2560 		break;
2561 	}
2562 
2563 	if (c_cflag & CSTOPB)
2564 		cval |= UART_LCR_STOP;
2565 	if (c_cflag & PARENB) {
2566 		cval |= UART_LCR_PARITY;
2567 		if (up->bugs & UART_BUG_PARITY)
2568 			up->fifo_bug = true;
2569 	}
2570 	if (!(c_cflag & PARODD))
2571 		cval |= UART_LCR_EPAR;
2572 #ifdef CMSPAR
2573 	if (c_cflag & CMSPAR)
2574 		cval |= UART_LCR_SPAR;
2575 #endif
2576 
2577 	return cval;
2578 }
2579 
2580 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2581 			       unsigned int quot, unsigned int quot_frac)
2582 {
2583 	struct uart_8250_port *up = up_to_u8250p(port);
2584 
2585 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2586 	if (is_omap1510_8250(up)) {
2587 		if (baud == 115200) {
2588 			quot = 1;
2589 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2590 		} else
2591 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2592 	}
2593 
2594 	/*
2595 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2596 	 * otherwise just set DLAB
2597 	 */
2598 	if (up->capabilities & UART_NATSEMI)
2599 		serial_port_out(port, UART_LCR, 0xe0);
2600 	else
2601 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2602 
2603 	serial_dl_write(up, quot);
2604 
2605 	/* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2606 	if (up->port.type == PORT_XR17V35X) {
2607 		/* Preserve bits not related to baudrate; DLD[7:4]. */
2608 		quot_frac |= serial_port_in(port, 0x2) & 0xf0;
2609 		serial_port_out(port, 0x2, quot_frac);
2610 	}
2611 }
2612 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2613 
2614 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2615 				   unsigned int quot, unsigned int quot_frac)
2616 {
2617 	if (port->set_divisor)
2618 		port->set_divisor(port, baud, quot, quot_frac);
2619 	else
2620 		serial8250_do_set_divisor(port, baud, quot, quot_frac);
2621 }
2622 
2623 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2624 					     struct ktermios *termios,
2625 					     struct ktermios *old)
2626 {
2627 	/*
2628 	 * Ask the core to calculate the divisor for us.
2629 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2630 	 * slower than nominal still match standard baud rates without
2631 	 * causing transmission errors.
2632 	 */
2633 	return uart_get_baud_rate(port, termios, old,
2634 				  port->uartclk / 16 / UART_DIV_MAX,
2635 				  port->uartclk);
2636 }
2637 
2638 void
2639 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2640 			  struct ktermios *old)
2641 {
2642 	struct uart_8250_port *up = up_to_u8250p(port);
2643 	unsigned char cval;
2644 	unsigned long flags;
2645 	unsigned int baud, quot, frac = 0;
2646 
2647 	if (up->capabilities & UART_CAP_MINI) {
2648 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2649 		if ((termios->c_cflag & CSIZE) == CS5 ||
2650 		    (termios->c_cflag & CSIZE) == CS6)
2651 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2652 	}
2653 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2654 
2655 	baud = serial8250_get_baud_rate(port, termios, old);
2656 	quot = serial8250_get_divisor(port, baud, &frac);
2657 
2658 	/*
2659 	 * Ok, we're now changing the port state.  Do it with
2660 	 * interrupts disabled.
2661 	 */
2662 	serial8250_rpm_get(up);
2663 	spin_lock_irqsave(&port->lock, flags);
2664 
2665 	up->lcr = cval;					/* Save computed LCR */
2666 
2667 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2668 		/* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2669 		if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2670 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2671 			up->fcr |= UART_FCR_TRIGGER_1;
2672 		}
2673 	}
2674 
2675 	/*
2676 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2677 	 * deasserted when the receive FIFO contains more characters than
2678 	 * the trigger, or the MCR RTS bit is cleared.
2679 	 */
2680 	if (up->capabilities & UART_CAP_AFE) {
2681 		up->mcr &= ~UART_MCR_AFE;
2682 		if (termios->c_cflag & CRTSCTS)
2683 			up->mcr |= UART_MCR_AFE;
2684 	}
2685 
2686 	/*
2687 	 * Update the per-port timeout.
2688 	 */
2689 	uart_update_timeout(port, termios->c_cflag, baud);
2690 
2691 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2692 	if (termios->c_iflag & INPCK)
2693 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2694 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2695 		port->read_status_mask |= UART_LSR_BI;
2696 
2697 	/*
2698 	 * Characteres to ignore
2699 	 */
2700 	port->ignore_status_mask = 0;
2701 	if (termios->c_iflag & IGNPAR)
2702 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2703 	if (termios->c_iflag & IGNBRK) {
2704 		port->ignore_status_mask |= UART_LSR_BI;
2705 		/*
2706 		 * If we're ignoring parity and break indicators,
2707 		 * ignore overruns too (for real raw support).
2708 		 */
2709 		if (termios->c_iflag & IGNPAR)
2710 			port->ignore_status_mask |= UART_LSR_OE;
2711 	}
2712 
2713 	/*
2714 	 * ignore all characters if CREAD is not set
2715 	 */
2716 	if ((termios->c_cflag & CREAD) == 0)
2717 		port->ignore_status_mask |= UART_LSR_DR;
2718 
2719 	/*
2720 	 * CTS flow control flag and modem status interrupts
2721 	 */
2722 	up->ier &= ~UART_IER_MSI;
2723 	if (!(up->bugs & UART_BUG_NOMSR) &&
2724 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2725 		up->ier |= UART_IER_MSI;
2726 	if (up->capabilities & UART_CAP_UUE)
2727 		up->ier |= UART_IER_UUE;
2728 	if (up->capabilities & UART_CAP_RTOIE)
2729 		up->ier |= UART_IER_RTOIE;
2730 
2731 	serial_port_out(port, UART_IER, up->ier);
2732 
2733 	if (up->capabilities & UART_CAP_EFR) {
2734 		unsigned char efr = 0;
2735 		/*
2736 		 * TI16C752/Startech hardware flow control.  FIXME:
2737 		 * - TI16C752 requires control thresholds to be set.
2738 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2739 		 */
2740 		if (termios->c_cflag & CRTSCTS)
2741 			efr |= UART_EFR_CTS;
2742 
2743 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2744 		if (port->flags & UPF_EXAR_EFR)
2745 			serial_port_out(port, UART_XR_EFR, efr);
2746 		else
2747 			serial_port_out(port, UART_EFR, efr);
2748 	}
2749 
2750 	serial8250_set_divisor(port, baud, quot, frac);
2751 
2752 	/*
2753 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2754 	 * is written without DLAB set, this mode will be disabled.
2755 	 */
2756 	if (port->type == PORT_16750)
2757 		serial_port_out(port, UART_FCR, up->fcr);
2758 
2759 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2760 	if (port->type != PORT_16750) {
2761 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2762 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2763 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2764 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2765 	}
2766 	serial8250_set_mctrl(port, port->mctrl);
2767 	spin_unlock_irqrestore(&port->lock, flags);
2768 	serial8250_rpm_put(up);
2769 
2770 	/* Don't rewrite B0 */
2771 	if (tty_termios_baud_rate(termios))
2772 		tty_termios_encode_baud_rate(termios, baud, baud);
2773 }
2774 EXPORT_SYMBOL(serial8250_do_set_termios);
2775 
2776 static void
2777 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2778 		       struct ktermios *old)
2779 {
2780 	if (port->set_termios)
2781 		port->set_termios(port, termios, old);
2782 	else
2783 		serial8250_do_set_termios(port, termios, old);
2784 }
2785 
2786 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2787 {
2788 	if (termios->c_line == N_PPS) {
2789 		port->flags |= UPF_HARDPPS_CD;
2790 		spin_lock_irq(&port->lock);
2791 		serial8250_enable_ms(port);
2792 		spin_unlock_irq(&port->lock);
2793 	} else {
2794 		port->flags &= ~UPF_HARDPPS_CD;
2795 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2796 			spin_lock_irq(&port->lock);
2797 			serial8250_disable_ms(port);
2798 			spin_unlock_irq(&port->lock);
2799 		}
2800 	}
2801 }
2802 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2803 
2804 static void
2805 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2806 {
2807 	if (port->set_ldisc)
2808 		port->set_ldisc(port, termios);
2809 	else
2810 		serial8250_do_set_ldisc(port, termios);
2811 }
2812 
2813 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2814 		      unsigned int oldstate)
2815 {
2816 	struct uart_8250_port *p = up_to_u8250p(port);
2817 
2818 	serial8250_set_sleep(p, state != 0);
2819 }
2820 EXPORT_SYMBOL(serial8250_do_pm);
2821 
2822 static void
2823 serial8250_pm(struct uart_port *port, unsigned int state,
2824 	      unsigned int oldstate)
2825 {
2826 	if (port->pm)
2827 		port->pm(port, state, oldstate);
2828 	else
2829 		serial8250_do_pm(port, state, oldstate);
2830 }
2831 
2832 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2833 {
2834 	if (pt->port.mapsize)
2835 		return pt->port.mapsize;
2836 	if (pt->port.iotype == UPIO_AU) {
2837 		if (pt->port.type == PORT_RT2880)
2838 			return 0x100;
2839 		return 0x1000;
2840 	}
2841 	if (is_omap1_8250(pt))
2842 		return 0x16 << pt->port.regshift;
2843 
2844 	return 8 << pt->port.regshift;
2845 }
2846 
2847 /*
2848  * Resource handling.
2849  */
2850 static int serial8250_request_std_resource(struct uart_8250_port *up)
2851 {
2852 	unsigned int size = serial8250_port_size(up);
2853 	struct uart_port *port = &up->port;
2854 	int ret = 0;
2855 
2856 	switch (port->iotype) {
2857 	case UPIO_AU:
2858 	case UPIO_TSI:
2859 	case UPIO_MEM32:
2860 	case UPIO_MEM32BE:
2861 	case UPIO_MEM16:
2862 	case UPIO_MEM:
2863 		if (!port->mapbase)
2864 			break;
2865 
2866 		if (!request_mem_region(port->mapbase, size, "serial")) {
2867 			ret = -EBUSY;
2868 			break;
2869 		}
2870 
2871 		if (port->flags & UPF_IOREMAP) {
2872 			port->membase = ioremap_nocache(port->mapbase, size);
2873 			if (!port->membase) {
2874 				release_mem_region(port->mapbase, size);
2875 				ret = -ENOMEM;
2876 			}
2877 		}
2878 		break;
2879 
2880 	case UPIO_HUB6:
2881 	case UPIO_PORT:
2882 		if (!request_region(port->iobase, size, "serial"))
2883 			ret = -EBUSY;
2884 		break;
2885 	}
2886 	return ret;
2887 }
2888 
2889 static void serial8250_release_std_resource(struct uart_8250_port *up)
2890 {
2891 	unsigned int size = serial8250_port_size(up);
2892 	struct uart_port *port = &up->port;
2893 
2894 	switch (port->iotype) {
2895 	case UPIO_AU:
2896 	case UPIO_TSI:
2897 	case UPIO_MEM32:
2898 	case UPIO_MEM32BE:
2899 	case UPIO_MEM16:
2900 	case UPIO_MEM:
2901 		if (!port->mapbase)
2902 			break;
2903 
2904 		if (port->flags & UPF_IOREMAP) {
2905 			iounmap(port->membase);
2906 			port->membase = NULL;
2907 		}
2908 
2909 		release_mem_region(port->mapbase, size);
2910 		break;
2911 
2912 	case UPIO_HUB6:
2913 	case UPIO_PORT:
2914 		release_region(port->iobase, size);
2915 		break;
2916 	}
2917 }
2918 
2919 static void serial8250_release_port(struct uart_port *port)
2920 {
2921 	struct uart_8250_port *up = up_to_u8250p(port);
2922 
2923 	serial8250_release_std_resource(up);
2924 }
2925 
2926 static int serial8250_request_port(struct uart_port *port)
2927 {
2928 	struct uart_8250_port *up = up_to_u8250p(port);
2929 
2930 	return serial8250_request_std_resource(up);
2931 }
2932 
2933 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2934 {
2935 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
2936 	unsigned char bytes;
2937 
2938 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2939 
2940 	return bytes ? bytes : -EOPNOTSUPP;
2941 }
2942 
2943 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2944 {
2945 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
2946 	int i;
2947 
2948 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2949 		return -EOPNOTSUPP;
2950 
2951 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2952 		if (bytes < conf_type->rxtrig_bytes[i])
2953 			/* Use the nearest lower value */
2954 			return (--i) << UART_FCR_R_TRIG_SHIFT;
2955 	}
2956 
2957 	return UART_FCR_R_TRIG_11;
2958 }
2959 
2960 static int do_get_rxtrig(struct tty_port *port)
2961 {
2962 	struct uart_state *state = container_of(port, struct uart_state, port);
2963 	struct uart_port *uport = state->uart_port;
2964 	struct uart_8250_port *up = up_to_u8250p(uport);
2965 
2966 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2967 		return -EINVAL;
2968 
2969 	return fcr_get_rxtrig_bytes(up);
2970 }
2971 
2972 static int do_serial8250_get_rxtrig(struct tty_port *port)
2973 {
2974 	int rxtrig_bytes;
2975 
2976 	mutex_lock(&port->mutex);
2977 	rxtrig_bytes = do_get_rxtrig(port);
2978 	mutex_unlock(&port->mutex);
2979 
2980 	return rxtrig_bytes;
2981 }
2982 
2983 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2984 	struct device_attribute *attr, char *buf)
2985 {
2986 	struct tty_port *port = dev_get_drvdata(dev);
2987 	int rxtrig_bytes;
2988 
2989 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
2990 	if (rxtrig_bytes < 0)
2991 		return rxtrig_bytes;
2992 
2993 	return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2994 }
2995 
2996 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2997 {
2998 	struct uart_state *state = container_of(port, struct uart_state, port);
2999 	struct uart_port *uport = state->uart_port;
3000 	struct uart_8250_port *up = up_to_u8250p(uport);
3001 	int rxtrig;
3002 
3003 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3004 	    up->fifo_bug)
3005 		return -EINVAL;
3006 
3007 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3008 	if (rxtrig < 0)
3009 		return rxtrig;
3010 
3011 	serial8250_clear_fifos(up);
3012 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3013 	up->fcr |= (unsigned char)rxtrig;
3014 	serial_out(up, UART_FCR, up->fcr);
3015 	return 0;
3016 }
3017 
3018 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3019 {
3020 	int ret;
3021 
3022 	mutex_lock(&port->mutex);
3023 	ret = do_set_rxtrig(port, bytes);
3024 	mutex_unlock(&port->mutex);
3025 
3026 	return ret;
3027 }
3028 
3029 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
3030 	struct device_attribute *attr, const char *buf, size_t count)
3031 {
3032 	struct tty_port *port = dev_get_drvdata(dev);
3033 	unsigned char bytes;
3034 	int ret;
3035 
3036 	if (!count)
3037 		return -EINVAL;
3038 
3039 	ret = kstrtou8(buf, 10, &bytes);
3040 	if (ret < 0)
3041 		return ret;
3042 
3043 	ret = do_serial8250_set_rxtrig(port, bytes);
3044 	if (ret < 0)
3045 		return ret;
3046 
3047 	return count;
3048 }
3049 
3050 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
3051 		   serial8250_get_attr_rx_trig_bytes,
3052 		   serial8250_set_attr_rx_trig_bytes);
3053 
3054 static struct attribute *serial8250_dev_attrs[] = {
3055 	&dev_attr_rx_trig_bytes.attr,
3056 	NULL,
3057 	};
3058 
3059 static struct attribute_group serial8250_dev_attr_group = {
3060 	.attrs = serial8250_dev_attrs,
3061 	};
3062 
3063 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3064 {
3065 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3066 
3067 	if (conf_type->rxtrig_bytes[0])
3068 		up->port.attr_group = &serial8250_dev_attr_group;
3069 }
3070 
3071 static void serial8250_config_port(struct uart_port *port, int flags)
3072 {
3073 	struct uart_8250_port *up = up_to_u8250p(port);
3074 	int ret;
3075 
3076 	/*
3077 	 * Find the region that we can probe for.  This in turn
3078 	 * tells us whether we can probe for the type of port.
3079 	 */
3080 	ret = serial8250_request_std_resource(up);
3081 	if (ret < 0)
3082 		return;
3083 
3084 	if (port->iotype != up->cur_iotype)
3085 		set_io_from_upio(port);
3086 
3087 	if (flags & UART_CONFIG_TYPE)
3088 		autoconfig(up);
3089 
3090 	/* if access method is AU, it is a 16550 with a quirk */
3091 	if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3092 		up->bugs |= UART_BUG_NOMSR;
3093 
3094 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3095 	if (port->type == PORT_TEGRA)
3096 		up->bugs |= UART_BUG_NOMSR;
3097 
3098 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3099 		autoconfig_irq(up);
3100 
3101 	if (port->type == PORT_UNKNOWN)
3102 		serial8250_release_std_resource(up);
3103 
3104 	register_dev_spec_attr_grp(up);
3105 	up->fcr = uart_config[up->port.type].fcr;
3106 }
3107 
3108 static int
3109 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3110 {
3111 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3112 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3113 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3114 	    ser->type == PORT_STARTECH)
3115 		return -EINVAL;
3116 	return 0;
3117 }
3118 
3119 static const char *serial8250_type(struct uart_port *port)
3120 {
3121 	int type = port->type;
3122 
3123 	if (type >= ARRAY_SIZE(uart_config))
3124 		type = 0;
3125 	return uart_config[type].name;
3126 }
3127 
3128 static const struct uart_ops serial8250_pops = {
3129 	.tx_empty	= serial8250_tx_empty,
3130 	.set_mctrl	= serial8250_set_mctrl,
3131 	.get_mctrl	= serial8250_get_mctrl,
3132 	.stop_tx	= serial8250_stop_tx,
3133 	.start_tx	= serial8250_start_tx,
3134 	.throttle	= serial8250_throttle,
3135 	.unthrottle	= serial8250_unthrottle,
3136 	.stop_rx	= serial8250_stop_rx,
3137 	.enable_ms	= serial8250_enable_ms,
3138 	.break_ctl	= serial8250_break_ctl,
3139 	.startup	= serial8250_startup,
3140 	.shutdown	= serial8250_shutdown,
3141 	.set_termios	= serial8250_set_termios,
3142 	.set_ldisc	= serial8250_set_ldisc,
3143 	.pm		= serial8250_pm,
3144 	.type		= serial8250_type,
3145 	.release_port	= serial8250_release_port,
3146 	.request_port	= serial8250_request_port,
3147 	.config_port	= serial8250_config_port,
3148 	.verify_port	= serial8250_verify_port,
3149 #ifdef CONFIG_CONSOLE_POLL
3150 	.poll_get_char = serial8250_get_poll_char,
3151 	.poll_put_char = serial8250_put_poll_char,
3152 #endif
3153 };
3154 
3155 void serial8250_init_port(struct uart_8250_port *up)
3156 {
3157 	struct uart_port *port = &up->port;
3158 
3159 	spin_lock_init(&port->lock);
3160 	port->ops = &serial8250_pops;
3161 
3162 	up->cur_iotype = 0xFF;
3163 }
3164 EXPORT_SYMBOL_GPL(serial8250_init_port);
3165 
3166 void serial8250_set_defaults(struct uart_8250_port *up)
3167 {
3168 	struct uart_port *port = &up->port;
3169 
3170 	if (up->port.flags & UPF_FIXED_TYPE) {
3171 		unsigned int type = up->port.type;
3172 
3173 		if (!up->port.fifosize)
3174 			up->port.fifosize = uart_config[type].fifo_size;
3175 		if (!up->tx_loadsz)
3176 			up->tx_loadsz = uart_config[type].tx_loadsz;
3177 		if (!up->capabilities)
3178 			up->capabilities = uart_config[type].flags;
3179 	}
3180 
3181 	set_io_from_upio(port);
3182 
3183 	/* default dma handlers */
3184 	if (up->dma) {
3185 		if (!up->dma->tx_dma)
3186 			up->dma->tx_dma = serial8250_tx_dma;
3187 		if (!up->dma->rx_dma)
3188 			up->dma->rx_dma = serial8250_rx_dma;
3189 	}
3190 }
3191 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3192 
3193 #ifdef CONFIG_SERIAL_8250_CONSOLE
3194 
3195 static void serial8250_console_putchar(struct uart_port *port, int ch)
3196 {
3197 	struct uart_8250_port *up = up_to_u8250p(port);
3198 
3199 	wait_for_xmitr(up, UART_LSR_THRE);
3200 	serial_port_out(port, UART_TX, ch);
3201 }
3202 
3203 /*
3204  *	Restore serial console when h/w power-off detected
3205  */
3206 static void serial8250_console_restore(struct uart_8250_port *up)
3207 {
3208 	struct uart_port *port = &up->port;
3209 	struct ktermios termios;
3210 	unsigned int baud, quot, frac = 0;
3211 
3212 	termios.c_cflag = port->cons->cflag;
3213 	if (port->state->port.tty && termios.c_cflag == 0)
3214 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3215 
3216 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3217 	quot = serial8250_get_divisor(port, baud, &frac);
3218 
3219 	serial8250_set_divisor(port, baud, quot, frac);
3220 	serial_port_out(port, UART_LCR, up->lcr);
3221 	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3222 }
3223 
3224 /*
3225  *	Print a string to the serial port trying not to disturb
3226  *	any possible real use of the port...
3227  *
3228  *	The console_lock must be held when we get here.
3229  */
3230 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3231 			      unsigned int count)
3232 {
3233 	struct uart_port *port = &up->port;
3234 	unsigned long flags;
3235 	unsigned int ier;
3236 	int locked = 1;
3237 
3238 	touch_nmi_watchdog();
3239 
3240 	serial8250_rpm_get(up);
3241 
3242 	if (oops_in_progress)
3243 		locked = spin_trylock_irqsave(&port->lock, flags);
3244 	else
3245 		spin_lock_irqsave(&port->lock, flags);
3246 
3247 	/*
3248 	 *	First save the IER then disable the interrupts
3249 	 */
3250 	ier = serial_port_in(port, UART_IER);
3251 
3252 	if (up->capabilities & UART_CAP_UUE)
3253 		serial_port_out(port, UART_IER, UART_IER_UUE);
3254 	else
3255 		serial_port_out(port, UART_IER, 0);
3256 
3257 	/* check scratch reg to see if port powered off during system sleep */
3258 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3259 		serial8250_console_restore(up);
3260 		up->canary = 0;
3261 	}
3262 
3263 	uart_console_write(port, s, count, serial8250_console_putchar);
3264 
3265 	/*
3266 	 *	Finally, wait for transmitter to become empty
3267 	 *	and restore the IER
3268 	 */
3269 	wait_for_xmitr(up, BOTH_EMPTY);
3270 	serial_port_out(port, UART_IER, ier);
3271 
3272 	/*
3273 	 *	The receive handling will happen properly because the
3274 	 *	receive ready bit will still be set; it is not cleared
3275 	 *	on read.  However, modem control will not, we must
3276 	 *	call it if we have saved something in the saved flags
3277 	 *	while processing with interrupts off.
3278 	 */
3279 	if (up->msr_saved_flags)
3280 		serial8250_modem_status(up);
3281 
3282 	if (locked)
3283 		spin_unlock_irqrestore(&port->lock, flags);
3284 	serial8250_rpm_put(up);
3285 }
3286 
3287 static unsigned int probe_baud(struct uart_port *port)
3288 {
3289 	unsigned char lcr, dll, dlm;
3290 	unsigned int quot;
3291 
3292 	lcr = serial_port_in(port, UART_LCR);
3293 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3294 	dll = serial_port_in(port, UART_DLL);
3295 	dlm = serial_port_in(port, UART_DLM);
3296 	serial_port_out(port, UART_LCR, lcr);
3297 
3298 	quot = (dlm << 8) | dll;
3299 	return (port->uartclk / 16) / quot;
3300 }
3301 
3302 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3303 {
3304 	int baud = 9600;
3305 	int bits = 8;
3306 	int parity = 'n';
3307 	int flow = 'n';
3308 
3309 	if (!port->iobase && !port->membase)
3310 		return -ENODEV;
3311 
3312 	if (options)
3313 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3314 	else if (probe)
3315 		baud = probe_baud(port);
3316 
3317 	return uart_set_options(port, port->cons, baud, parity, bits, flow);
3318 }
3319 
3320 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3321 
3322 MODULE_LICENSE("GPL");
3323