1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/console.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/sysrq.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/tty.h>
25 #include <linux/ratelimit.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/nmi.h>
30 #include <linux/mutex.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/ktime.h>
35 
36 #include <asm/io.h>
37 #include <asm/irq.h>
38 
39 #include "8250.h"
40 
41 /* Nuvoton NPCM timeout register */
42 #define UART_NPCM_TOR          7
43 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
44 
45 /*
46  * Debugging.
47  */
48 #if 0
49 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
50 #else
51 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
52 #endif
53 
54 /*
55  * Here we define the default xmit fifo size used for each type of UART.
56  */
57 static const struct serial8250_config uart_config[] = {
58 	[PORT_UNKNOWN] = {
59 		.name		= "unknown",
60 		.fifo_size	= 1,
61 		.tx_loadsz	= 1,
62 	},
63 	[PORT_8250] = {
64 		.name		= "8250",
65 		.fifo_size	= 1,
66 		.tx_loadsz	= 1,
67 	},
68 	[PORT_16450] = {
69 		.name		= "16450",
70 		.fifo_size	= 1,
71 		.tx_loadsz	= 1,
72 	},
73 	[PORT_16550] = {
74 		.name		= "16550",
75 		.fifo_size	= 1,
76 		.tx_loadsz	= 1,
77 	},
78 	[PORT_16550A] = {
79 		.name		= "16550A",
80 		.fifo_size	= 16,
81 		.tx_loadsz	= 16,
82 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 		.rxtrig_bytes	= {1, 4, 8, 14},
84 		.flags		= UART_CAP_FIFO,
85 	},
86 	[PORT_CIRRUS] = {
87 		.name		= "Cirrus",
88 		.fifo_size	= 1,
89 		.tx_loadsz	= 1,
90 	},
91 	[PORT_16650] = {
92 		.name		= "ST16650",
93 		.fifo_size	= 1,
94 		.tx_loadsz	= 1,
95 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
96 	},
97 	[PORT_16650V2] = {
98 		.name		= "ST16650V2",
99 		.fifo_size	= 32,
100 		.tx_loadsz	= 16,
101 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 				  UART_FCR_T_TRIG_00,
103 		.rxtrig_bytes	= {8, 16, 24, 28},
104 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
105 	},
106 	[PORT_16750] = {
107 		.name		= "TI16750",
108 		.fifo_size	= 64,
109 		.tx_loadsz	= 64,
110 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 				  UART_FCR7_64BYTE,
112 		.rxtrig_bytes	= {1, 16, 32, 56},
113 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
114 	},
115 	[PORT_STARTECH] = {
116 		.name		= "Startech",
117 		.fifo_size	= 1,
118 		.tx_loadsz	= 1,
119 	},
120 	[PORT_16C950] = {
121 		.name		= "16C950/954",
122 		.fifo_size	= 128,
123 		.tx_loadsz	= 128,
124 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
125 		.rxtrig_bytes	= {16, 32, 112, 120},
126 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
128 	},
129 	[PORT_16654] = {
130 		.name		= "ST16654",
131 		.fifo_size	= 64,
132 		.tx_loadsz	= 32,
133 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 				  UART_FCR_T_TRIG_10,
135 		.rxtrig_bytes	= {8, 16, 56, 60},
136 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
137 	},
138 	[PORT_16850] = {
139 		.name		= "XR16850",
140 		.fifo_size	= 128,
141 		.tx_loadsz	= 128,
142 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
144 	},
145 	[PORT_RSA] = {
146 		.name		= "RSA",
147 		.fifo_size	= 2048,
148 		.tx_loadsz	= 2048,
149 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 		.flags		= UART_CAP_FIFO,
151 	},
152 	[PORT_NS16550A] = {
153 		.name		= "NS16550A",
154 		.fifo_size	= 16,
155 		.tx_loadsz	= 16,
156 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
158 	},
159 	[PORT_XSCALE] = {
160 		.name		= "XScale",
161 		.fifo_size	= 32,
162 		.tx_loadsz	= 32,
163 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
165 	},
166 	[PORT_OCTEON] = {
167 		.name		= "OCTEON",
168 		.fifo_size	= 64,
169 		.tx_loadsz	= 64,
170 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 		.flags		= UART_CAP_FIFO,
172 	},
173 	[PORT_AR7] = {
174 		.name		= "AR7",
175 		.fifo_size	= 16,
176 		.tx_loadsz	= 16,
177 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
179 	},
180 	[PORT_U6_16550A] = {
181 		.name		= "U6_16550A",
182 		.fifo_size	= 64,
183 		.tx_loadsz	= 64,
184 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
186 	},
187 	[PORT_TEGRA] = {
188 		.name		= "Tegra",
189 		.fifo_size	= 32,
190 		.tx_loadsz	= 8,
191 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 				  UART_FCR_T_TRIG_01,
193 		.rxtrig_bytes	= {1, 4, 8, 14},
194 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
195 	},
196 	[PORT_XR17D15X] = {
197 		.name		= "XR17D15X",
198 		.fifo_size	= 64,
199 		.tx_loadsz	= 64,
200 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
202 				  UART_CAP_SLEEP,
203 	},
204 	[PORT_XR17V35X] = {
205 		.name		= "XR17V35X",
206 		.fifo_size	= 256,
207 		.tx_loadsz	= 256,
208 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 				  UART_FCR_T_TRIG_11,
210 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
211 				  UART_CAP_SLEEP,
212 	},
213 	[PORT_LPC3220] = {
214 		.name		= "LPC3220",
215 		.fifo_size	= 64,
216 		.tx_loadsz	= 32,
217 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 		.flags		= UART_CAP_FIFO,
220 	},
221 	[PORT_BRCM_TRUMANAGE] = {
222 		.name		= "TruManage",
223 		.fifo_size	= 1,
224 		.tx_loadsz	= 1024,
225 		.flags		= UART_CAP_HFIFO,
226 	},
227 	[PORT_8250_CIR] = {
228 		.name		= "CIR port"
229 	},
230 	[PORT_ALTR_16550_F32] = {
231 		.name		= "Altera 16550 FIFO32",
232 		.fifo_size	= 32,
233 		.tx_loadsz	= 32,
234 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 		.rxtrig_bytes	= {1, 8, 16, 30},
236 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
237 	},
238 	[PORT_ALTR_16550_F64] = {
239 		.name		= "Altera 16550 FIFO64",
240 		.fifo_size	= 64,
241 		.tx_loadsz	= 64,
242 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 		.rxtrig_bytes	= {1, 16, 32, 62},
244 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
245 	},
246 	[PORT_ALTR_16550_F128] = {
247 		.name		= "Altera 16550 FIFO128",
248 		.fifo_size	= 128,
249 		.tx_loadsz	= 128,
250 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 		.rxtrig_bytes	= {1, 32, 64, 126},
252 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
253 	},
254 	/*
255 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 	 * workaround of errata A-008006 which states that tx_loadsz should
257 	 * be configured less than Maximum supported fifo bytes.
258 	 */
259 	[PORT_16550A_FSL64] = {
260 		.name		= "16550A_FSL64",
261 		.fifo_size	= 64,
262 		.tx_loadsz	= 63,
263 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 				  UART_FCR7_64BYTE,
265 		.flags		= UART_CAP_FIFO | UART_CAP_NOTEMT,
266 	},
267 	[PORT_RT2880] = {
268 		.name		= "Palmchip BK-3103",
269 		.fifo_size	= 16,
270 		.tx_loadsz	= 16,
271 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 		.rxtrig_bytes	= {1, 4, 8, 14},
273 		.flags		= UART_CAP_FIFO,
274 	},
275 	[PORT_DA830] = {
276 		.name		= "TI DA8xx/66AK2x",
277 		.fifo_size	= 16,
278 		.tx_loadsz	= 16,
279 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 				  UART_FCR_R_TRIG_10,
281 		.rxtrig_bytes	= {1, 4, 8, 14},
282 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
283 	},
284 	[PORT_MTK_BTIF] = {
285 		.name		= "MediaTek BTIF",
286 		.fifo_size	= 16,
287 		.tx_loadsz	= 16,
288 		.fcr		= UART_FCR_ENABLE_FIFO |
289 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 		.flags		= UART_CAP_FIFO,
291 	},
292 	[PORT_NPCM] = {
293 		.name		= "Nuvoton 16550",
294 		.fifo_size	= 16,
295 		.tx_loadsz	= 16,
296 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 		.rxtrig_bytes	= {1, 4, 8, 14},
299 		.flags		= UART_CAP_FIFO,
300 	},
301 	[PORT_SUNIX] = {
302 		.name		= "Sunix",
303 		.fifo_size	= 128,
304 		.tx_loadsz	= 128,
305 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 		.rxtrig_bytes	= {1, 32, 64, 112},
307 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
308 	},
309 	[PORT_ASPEED_VUART] = {
310 		.name		= "ASPEED VUART",
311 		.fifo_size	= 16,
312 		.tx_loadsz	= 16,
313 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
314 		.rxtrig_bytes	= {1, 4, 8, 14},
315 		.flags		= UART_CAP_FIFO,
316 	},
317 	[PORT_MCHP16550A] = {
318 		.name           = "MCHP16550A",
319 		.fifo_size      = 256,
320 		.tx_loadsz      = 256,
321 		.fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
322 		.rxtrig_bytes   = {2, 66, 130, 194},
323 		.flags          = UART_CAP_FIFO,
324 	},
325 	[PORT_BCM7271] = {
326 		.name		= "Broadcom BCM7271 UART",
327 		.fifo_size	= 32,
328 		.tx_loadsz	= 32,
329 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
330 		.rxtrig_bytes	= {1, 8, 16, 30},
331 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
332 	},
333 };
334 
335 /* Uart divisor latch read */
336 static u32 default_serial_dl_read(struct uart_8250_port *up)
337 {
338 	/* Assign these in pieces to truncate any bits above 7.  */
339 	unsigned char dll = serial_in(up, UART_DLL);
340 	unsigned char dlm = serial_in(up, UART_DLM);
341 
342 	return dll | dlm << 8;
343 }
344 
345 /* Uart divisor latch write */
346 static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
347 {
348 	serial_out(up, UART_DLL, value & 0xff);
349 	serial_out(up, UART_DLM, value >> 8 & 0xff);
350 }
351 
352 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
353 {
354 	offset = offset << p->regshift;
355 	outb(p->hub6 - 1 + offset, p->iobase);
356 	return inb(p->iobase + 1);
357 }
358 
359 static void hub6_serial_out(struct uart_port *p, int offset, int value)
360 {
361 	offset = offset << p->regshift;
362 	outb(p->hub6 - 1 + offset, p->iobase);
363 	outb(value, p->iobase + 1);
364 }
365 
366 static unsigned int mem_serial_in(struct uart_port *p, int offset)
367 {
368 	offset = offset << p->regshift;
369 	return readb(p->membase + offset);
370 }
371 
372 static void mem_serial_out(struct uart_port *p, int offset, int value)
373 {
374 	offset = offset << p->regshift;
375 	writeb(value, p->membase + offset);
376 }
377 
378 static void mem16_serial_out(struct uart_port *p, int offset, int value)
379 {
380 	offset = offset << p->regshift;
381 	writew(value, p->membase + offset);
382 }
383 
384 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
385 {
386 	offset = offset << p->regshift;
387 	return readw(p->membase + offset);
388 }
389 
390 static void mem32_serial_out(struct uart_port *p, int offset, int value)
391 {
392 	offset = offset << p->regshift;
393 	writel(value, p->membase + offset);
394 }
395 
396 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
397 {
398 	offset = offset << p->regshift;
399 	return readl(p->membase + offset);
400 }
401 
402 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
403 {
404 	offset = offset << p->regshift;
405 	iowrite32be(value, p->membase + offset);
406 }
407 
408 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
409 {
410 	offset = offset << p->regshift;
411 	return ioread32be(p->membase + offset);
412 }
413 
414 static unsigned int io_serial_in(struct uart_port *p, int offset)
415 {
416 	offset = offset << p->regshift;
417 	return inb(p->iobase + offset);
418 }
419 
420 static void io_serial_out(struct uart_port *p, int offset, int value)
421 {
422 	offset = offset << p->regshift;
423 	outb(value, p->iobase + offset);
424 }
425 
426 static int serial8250_default_handle_irq(struct uart_port *port);
427 
428 static void set_io_from_upio(struct uart_port *p)
429 {
430 	struct uart_8250_port *up = up_to_u8250p(p);
431 
432 	up->dl_read = default_serial_dl_read;
433 	up->dl_write = default_serial_dl_write;
434 
435 	switch (p->iotype) {
436 	case UPIO_HUB6:
437 		p->serial_in = hub6_serial_in;
438 		p->serial_out = hub6_serial_out;
439 		break;
440 
441 	case UPIO_MEM:
442 		p->serial_in = mem_serial_in;
443 		p->serial_out = mem_serial_out;
444 		break;
445 
446 	case UPIO_MEM16:
447 		p->serial_in = mem16_serial_in;
448 		p->serial_out = mem16_serial_out;
449 		break;
450 
451 	case UPIO_MEM32:
452 		p->serial_in = mem32_serial_in;
453 		p->serial_out = mem32_serial_out;
454 		break;
455 
456 	case UPIO_MEM32BE:
457 		p->serial_in = mem32be_serial_in;
458 		p->serial_out = mem32be_serial_out;
459 		break;
460 
461 	default:
462 		p->serial_in = io_serial_in;
463 		p->serial_out = io_serial_out;
464 		break;
465 	}
466 	/* Remember loaded iotype */
467 	up->cur_iotype = p->iotype;
468 	p->handle_irq = serial8250_default_handle_irq;
469 }
470 
471 static void
472 serial_port_out_sync(struct uart_port *p, int offset, int value)
473 {
474 	switch (p->iotype) {
475 	case UPIO_MEM:
476 	case UPIO_MEM16:
477 	case UPIO_MEM32:
478 	case UPIO_MEM32BE:
479 	case UPIO_AU:
480 		p->serial_out(p, offset, value);
481 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
482 		break;
483 	default:
484 		p->serial_out(p, offset, value);
485 	}
486 }
487 
488 /*
489  * FIFO support.
490  */
491 static void serial8250_clear_fifos(struct uart_8250_port *p)
492 {
493 	if (p->capabilities & UART_CAP_FIFO) {
494 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
495 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
496 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
497 		serial_out(p, UART_FCR, 0);
498 	}
499 }
500 
501 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
502 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
503 
504 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
505 {
506 	serial8250_clear_fifos(p);
507 	serial_out(p, UART_FCR, p->fcr);
508 }
509 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
510 
511 void serial8250_rpm_get(struct uart_8250_port *p)
512 {
513 	if (!(p->capabilities & UART_CAP_RPM))
514 		return;
515 	pm_runtime_get_sync(p->port.dev);
516 }
517 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
518 
519 void serial8250_rpm_put(struct uart_8250_port *p)
520 {
521 	if (!(p->capabilities & UART_CAP_RPM))
522 		return;
523 	pm_runtime_mark_last_busy(p->port.dev);
524 	pm_runtime_put_autosuspend(p->port.dev);
525 }
526 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
527 
528 /**
529  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
530  *	@p:	uart_8250_port port instance
531  *
532  *	The function is used to start rs485 software emulating on the
533  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
534  *	transmission. The function is idempotent, so it is safe to call it
535  *	multiple times.
536  *
537  *	The caller MUST enable interrupt on empty shift register before
538  *	calling serial8250_em485_init(). This interrupt is not a part of
539  *	8250 standard, but implementation defined.
540  *
541  *	The function is supposed to be called from .rs485_config callback
542  *	or from any other callback protected with p->port.lock spinlock.
543  *
544  *	See also serial8250_em485_destroy()
545  *
546  *	Return 0 - success, -errno - otherwise
547  */
548 static int serial8250_em485_init(struct uart_8250_port *p)
549 {
550 	/* Port locked to synchronize UART_IER access against the console. */
551 	lockdep_assert_held_once(&p->port.lock);
552 
553 	if (p->em485)
554 		goto deassert_rts;
555 
556 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
557 	if (!p->em485)
558 		return -ENOMEM;
559 
560 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
561 		     HRTIMER_MODE_REL);
562 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
563 		     HRTIMER_MODE_REL);
564 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
565 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
566 	p->em485->port = p;
567 	p->em485->active_timer = NULL;
568 	p->em485->tx_stopped = true;
569 
570 deassert_rts:
571 	if (p->em485->tx_stopped)
572 		p->rs485_stop_tx(p);
573 
574 	return 0;
575 }
576 
577 /**
578  *	serial8250_em485_destroy() - put uart_8250_port into normal state
579  *	@p:	uart_8250_port port instance
580  *
581  *	The function is used to stop rs485 software emulating on the
582  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
583  *	call it multiple times.
584  *
585  *	The function is supposed to be called from .rs485_config callback
586  *	or from any other callback protected with p->port.lock spinlock.
587  *
588  *	See also serial8250_em485_init()
589  */
590 void serial8250_em485_destroy(struct uart_8250_port *p)
591 {
592 	if (!p->em485)
593 		return;
594 
595 	hrtimer_cancel(&p->em485->start_tx_timer);
596 	hrtimer_cancel(&p->em485->stop_tx_timer);
597 
598 	kfree(p->em485);
599 	p->em485 = NULL;
600 }
601 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
602 
603 struct serial_rs485 serial8250_em485_supported = {
604 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
605 		 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
606 	.delay_rts_before_send = 1,
607 	.delay_rts_after_send = 1,
608 };
609 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
610 
611 /**
612  * serial8250_em485_config() - generic ->rs485_config() callback
613  * @port: uart port
614  * @termios: termios structure
615  * @rs485: rs485 settings
616  *
617  * Generic callback usable by 8250 uart drivers to activate rs485 settings
618  * if the uart is incapable of driving RTS as a Transmit Enable signal in
619  * hardware, relying on software emulation instead.
620  */
621 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
622 			    struct serial_rs485 *rs485)
623 {
624 	struct uart_8250_port *up = up_to_u8250p(port);
625 
626 	/* pick sane settings if the user hasn't */
627 	if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
628 	    !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
629 		rs485->flags |= SER_RS485_RTS_ON_SEND;
630 		rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
631 	}
632 
633 	/*
634 	 * Both serial8250_em485_init() and serial8250_em485_destroy()
635 	 * are idempotent.
636 	 */
637 	if (rs485->flags & SER_RS485_ENABLED)
638 		return serial8250_em485_init(up);
639 
640 	serial8250_em485_destroy(up);
641 	return 0;
642 }
643 EXPORT_SYMBOL_GPL(serial8250_em485_config);
644 
645 /*
646  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
647  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
648  * empty and the HW can idle again.
649  */
650 void serial8250_rpm_get_tx(struct uart_8250_port *p)
651 {
652 	unsigned char rpm_active;
653 
654 	if (!(p->capabilities & UART_CAP_RPM))
655 		return;
656 
657 	rpm_active = xchg(&p->rpm_tx_active, 1);
658 	if (rpm_active)
659 		return;
660 	pm_runtime_get_sync(p->port.dev);
661 }
662 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
663 
664 void serial8250_rpm_put_tx(struct uart_8250_port *p)
665 {
666 	unsigned char rpm_active;
667 
668 	if (!(p->capabilities & UART_CAP_RPM))
669 		return;
670 
671 	rpm_active = xchg(&p->rpm_tx_active, 0);
672 	if (!rpm_active)
673 		return;
674 	pm_runtime_mark_last_busy(p->port.dev);
675 	pm_runtime_put_autosuspend(p->port.dev);
676 }
677 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
678 
679 /*
680  * IER sleep support.  UARTs which have EFRs need the "extended
681  * capability" bit enabled.  Note that on XR16C850s, we need to
682  * reset LCR to write to IER.
683  */
684 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
685 {
686 	unsigned char lcr = 0, efr = 0;
687 
688 	serial8250_rpm_get(p);
689 
690 	if (p->capabilities & UART_CAP_SLEEP) {
691 		/* Synchronize UART_IER access against the console. */
692 		spin_lock_irq(&p->port.lock);
693 		if (p->capabilities & UART_CAP_EFR) {
694 			lcr = serial_in(p, UART_LCR);
695 			efr = serial_in(p, UART_EFR);
696 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
697 			serial_out(p, UART_EFR, UART_EFR_ECB);
698 			serial_out(p, UART_LCR, 0);
699 		}
700 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
701 		if (p->capabilities & UART_CAP_EFR) {
702 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
703 			serial_out(p, UART_EFR, efr);
704 			serial_out(p, UART_LCR, lcr);
705 		}
706 		spin_unlock_irq(&p->port.lock);
707 	}
708 
709 	serial8250_rpm_put(p);
710 }
711 
712 static void serial8250_clear_IER(struct uart_8250_port *up)
713 {
714 	if (up->capabilities & UART_CAP_UUE)
715 		serial_out(up, UART_IER, UART_IER_UUE);
716 	else
717 		serial_out(up, UART_IER, 0);
718 }
719 
720 #ifdef CONFIG_SERIAL_8250_RSA
721 /*
722  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
723  * We set the port uart clock rate if we succeed.
724  */
725 static int __enable_rsa(struct uart_8250_port *up)
726 {
727 	unsigned char mode;
728 	int result;
729 
730 	mode = serial_in(up, UART_RSA_MSR);
731 	result = mode & UART_RSA_MSR_FIFO;
732 
733 	if (!result) {
734 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
735 		mode = serial_in(up, UART_RSA_MSR);
736 		result = mode & UART_RSA_MSR_FIFO;
737 	}
738 
739 	if (result)
740 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
741 
742 	return result;
743 }
744 
745 static void enable_rsa(struct uart_8250_port *up)
746 {
747 	if (up->port.type == PORT_RSA) {
748 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
749 			spin_lock_irq(&up->port.lock);
750 			__enable_rsa(up);
751 			spin_unlock_irq(&up->port.lock);
752 		}
753 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
754 			serial_out(up, UART_RSA_FRR, 0);
755 	}
756 }
757 
758 /*
759  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
760  * It is unknown why interrupts were disabled in here.  However,
761  * the caller is expected to preserve this behaviour by grabbing
762  * the spinlock before calling this function.
763  */
764 static void disable_rsa(struct uart_8250_port *up)
765 {
766 	unsigned char mode;
767 	int result;
768 
769 	if (up->port.type == PORT_RSA &&
770 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
771 		spin_lock_irq(&up->port.lock);
772 
773 		mode = serial_in(up, UART_RSA_MSR);
774 		result = !(mode & UART_RSA_MSR_FIFO);
775 
776 		if (!result) {
777 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
778 			mode = serial_in(up, UART_RSA_MSR);
779 			result = !(mode & UART_RSA_MSR_FIFO);
780 		}
781 
782 		if (result)
783 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
784 		spin_unlock_irq(&up->port.lock);
785 	}
786 }
787 #endif /* CONFIG_SERIAL_8250_RSA */
788 
789 /*
790  * This is a quickie test to see how big the FIFO is.
791  * It doesn't work at all the time, more's the pity.
792  */
793 static int size_fifo(struct uart_8250_port *up)
794 {
795 	unsigned char old_fcr, old_mcr, old_lcr;
796 	u32 old_dl;
797 	int count;
798 
799 	old_lcr = serial_in(up, UART_LCR);
800 	serial_out(up, UART_LCR, 0);
801 	old_fcr = serial_in(up, UART_FCR);
802 	old_mcr = serial8250_in_MCR(up);
803 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
804 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
805 	serial8250_out_MCR(up, UART_MCR_LOOP);
806 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
807 	old_dl = serial_dl_read(up);
808 	serial_dl_write(up, 0x0001);
809 	serial_out(up, UART_LCR, UART_LCR_WLEN8);
810 	for (count = 0; count < 256; count++)
811 		serial_out(up, UART_TX, count);
812 	mdelay(20);/* FIXME - schedule_timeout */
813 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
814 	     (count < 256); count++)
815 		serial_in(up, UART_RX);
816 	serial_out(up, UART_FCR, old_fcr);
817 	serial8250_out_MCR(up, old_mcr);
818 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
819 	serial_dl_write(up, old_dl);
820 	serial_out(up, UART_LCR, old_lcr);
821 
822 	return count;
823 }
824 
825 /*
826  * Read UART ID using the divisor method - set DLL and DLM to zero
827  * and the revision will be in DLL and device type in DLM.  We
828  * preserve the device state across this.
829  */
830 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
831 {
832 	unsigned char old_lcr;
833 	unsigned int id, old_dl;
834 
835 	old_lcr = serial_in(p, UART_LCR);
836 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
837 	old_dl = serial_dl_read(p);
838 	serial_dl_write(p, 0);
839 	id = serial_dl_read(p);
840 	serial_dl_write(p, old_dl);
841 
842 	serial_out(p, UART_LCR, old_lcr);
843 
844 	return id;
845 }
846 
847 /*
848  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
849  * When this function is called we know it is at least a StarTech
850  * 16650 V2, but it might be one of several StarTech UARTs, or one of
851  * its clones.  (We treat the broken original StarTech 16650 V1 as a
852  * 16550, and why not?  Startech doesn't seem to even acknowledge its
853  * existence.)
854  *
855  * What evil have men's minds wrought...
856  */
857 static void autoconfig_has_efr(struct uart_8250_port *up)
858 {
859 	unsigned int id1, id2, id3, rev;
860 
861 	/*
862 	 * Everything with an EFR has SLEEP
863 	 */
864 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
865 
866 	/*
867 	 * First we check to see if it's an Oxford Semiconductor UART.
868 	 *
869 	 * If we have to do this here because some non-National
870 	 * Semiconductor clone chips lock up if you try writing to the
871 	 * LSR register (which serial_icr_read does)
872 	 */
873 
874 	/*
875 	 * Check for Oxford Semiconductor 16C950.
876 	 *
877 	 * EFR [4] must be set else this test fails.
878 	 *
879 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
880 	 * claims that it's needed for 952 dual UART's (which are not
881 	 * recommended for new designs).
882 	 */
883 	up->acr = 0;
884 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
885 	serial_out(up, UART_EFR, UART_EFR_ECB);
886 	serial_out(up, UART_LCR, 0x00);
887 	id1 = serial_icr_read(up, UART_ID1);
888 	id2 = serial_icr_read(up, UART_ID2);
889 	id3 = serial_icr_read(up, UART_ID3);
890 	rev = serial_icr_read(up, UART_REV);
891 
892 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
893 
894 	if (id1 == 0x16 && id2 == 0xC9 &&
895 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
896 		up->port.type = PORT_16C950;
897 
898 		/*
899 		 * Enable work around for the Oxford Semiconductor 952 rev B
900 		 * chip which causes it to seriously miscalculate baud rates
901 		 * when DLL is 0.
902 		 */
903 		if (id3 == 0x52 && rev == 0x01)
904 			up->bugs |= UART_BUG_QUOT;
905 		return;
906 	}
907 
908 	/*
909 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
910 	 * reading back DLL and DLM.  The chip type depends on the DLM
911 	 * value read back:
912 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
913 	 *  0x12 - XR16C2850.
914 	 *  0x14 - XR16C854.
915 	 */
916 	id1 = autoconfig_read_divisor_id(up);
917 	DEBUG_AUTOCONF("850id=%04x ", id1);
918 
919 	id2 = id1 >> 8;
920 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
921 		up->port.type = PORT_16850;
922 		return;
923 	}
924 
925 	/*
926 	 * It wasn't an XR16C850.
927 	 *
928 	 * We distinguish between the '654 and the '650 by counting
929 	 * how many bytes are in the FIFO.  I'm using this for now,
930 	 * since that's the technique that was sent to me in the
931 	 * serial driver update, but I'm not convinced this works.
932 	 * I've had problems doing this in the past.  -TYT
933 	 */
934 	if (size_fifo(up) == 64)
935 		up->port.type = PORT_16654;
936 	else
937 		up->port.type = PORT_16650V2;
938 }
939 
940 /*
941  * We detected a chip without a FIFO.  Only two fall into
942  * this category - the original 8250 and the 16450.  The
943  * 16450 has a scratch register (accessible with LCR=0)
944  */
945 static void autoconfig_8250(struct uart_8250_port *up)
946 {
947 	unsigned char scratch, status1, status2;
948 
949 	up->port.type = PORT_8250;
950 
951 	scratch = serial_in(up, UART_SCR);
952 	serial_out(up, UART_SCR, 0xa5);
953 	status1 = serial_in(up, UART_SCR);
954 	serial_out(up, UART_SCR, 0x5a);
955 	status2 = serial_in(up, UART_SCR);
956 	serial_out(up, UART_SCR, scratch);
957 
958 	if (status1 == 0xa5 && status2 == 0x5a)
959 		up->port.type = PORT_16450;
960 }
961 
962 static int broken_efr(struct uart_8250_port *up)
963 {
964 	/*
965 	 * Exar ST16C2550 "A2" devices incorrectly detect as
966 	 * having an EFR, and report an ID of 0x0201.  See
967 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
968 	 */
969 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
970 		return 1;
971 
972 	return 0;
973 }
974 
975 /*
976  * We know that the chip has FIFOs.  Does it have an EFR?  The
977  * EFR is located in the same register position as the IIR and
978  * we know the top two bits of the IIR are currently set.  The
979  * EFR should contain zero.  Try to read the EFR.
980  */
981 static void autoconfig_16550a(struct uart_8250_port *up)
982 {
983 	unsigned char status1, status2;
984 	unsigned int iersave;
985 
986 	/* Port locked to synchronize UART_IER access against the console. */
987 	lockdep_assert_held_once(&up->port.lock);
988 
989 	up->port.type = PORT_16550A;
990 	up->capabilities |= UART_CAP_FIFO;
991 
992 	if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
993 	    !(up->port.flags & UPF_FULL_PROBE))
994 		return;
995 
996 	/*
997 	 * Check for presence of the EFR when DLAB is set.
998 	 * Only ST16C650V1 UARTs pass this test.
999 	 */
1000 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 	if (serial_in(up, UART_EFR) == 0) {
1002 		serial_out(up, UART_EFR, 0xA8);
1003 		if (serial_in(up, UART_EFR) != 0) {
1004 			DEBUG_AUTOCONF("EFRv1 ");
1005 			up->port.type = PORT_16650;
1006 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1007 		} else {
1008 			serial_out(up, UART_LCR, 0);
1009 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1010 				   UART_FCR7_64BYTE);
1011 			status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
1012 							     UART_IIR_FIFO_ENABLED);
1013 			serial_out(up, UART_FCR, 0);
1014 			serial_out(up, UART_LCR, 0);
1015 
1016 			if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
1017 				up->port.type = PORT_16550A_FSL64;
1018 			else
1019 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1020 		}
1021 		serial_out(up, UART_EFR, 0);
1022 		return;
1023 	}
1024 
1025 	/*
1026 	 * Maybe it requires 0xbf to be written to the LCR.
1027 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1028 	 */
1029 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1030 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1031 		DEBUG_AUTOCONF("EFRv2 ");
1032 		autoconfig_has_efr(up);
1033 		return;
1034 	}
1035 
1036 	/*
1037 	 * Check for a National Semiconductor SuperIO chip.
1038 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1039 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1040 	 * switch back to bank 2, read it from EXCR1 again and check
1041 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1042 	 */
1043 	serial_out(up, UART_LCR, 0);
1044 	status1 = serial8250_in_MCR(up);
1045 	serial_out(up, UART_LCR, 0xE0);
1046 	status2 = serial_in(up, 0x02); /* EXCR1 */
1047 
1048 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1049 		serial_out(up, UART_LCR, 0);
1050 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1051 		serial_out(up, UART_LCR, 0xE0);
1052 		status2 = serial_in(up, 0x02); /* EXCR1 */
1053 		serial_out(up, UART_LCR, 0);
1054 		serial8250_out_MCR(up, status1);
1055 
1056 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1057 			unsigned short quot;
1058 
1059 			serial_out(up, UART_LCR, 0xE0);
1060 
1061 			quot = serial_dl_read(up);
1062 			quot <<= 3;
1063 
1064 			if (ns16550a_goto_highspeed(up))
1065 				serial_dl_write(up, quot);
1066 
1067 			serial_out(up, UART_LCR, 0);
1068 
1069 			up->port.uartclk = 921600*16;
1070 			up->port.type = PORT_NS16550A;
1071 			up->capabilities |= UART_NATSEMI;
1072 			return;
1073 		}
1074 	}
1075 
1076 	/*
1077 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1078 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1079 	 * Try setting it with and without DLAB set.  Cheap clones
1080 	 * set bit 5 without DLAB set.
1081 	 */
1082 	serial_out(up, UART_LCR, 0);
1083 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1084 	status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1085 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1086 
1087 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1088 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1089 	status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1090 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1091 
1092 	serial_out(up, UART_LCR, 0);
1093 
1094 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1095 
1096 	if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1097 	    status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
1098 		up->port.type = PORT_16750;
1099 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1100 		return;
1101 	}
1102 
1103 	/*
1104 	 * Try writing and reading the UART_IER_UUE bit (b6).
1105 	 * If it works, this is probably one of the Xscale platform's
1106 	 * internal UARTs.
1107 	 * We're going to explicitly set the UUE bit to 0 before
1108 	 * trying to write and read a 1 just to make sure it's not
1109 	 * already a 1 and maybe locked there before we even start.
1110 	 */
1111 	iersave = serial_in(up, UART_IER);
1112 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1113 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1114 		/*
1115 		 * OK it's in a known zero state, try writing and reading
1116 		 * without disturbing the current state of the other bits.
1117 		 */
1118 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1119 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1120 			/*
1121 			 * It's an Xscale.
1122 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1123 			 */
1124 			DEBUG_AUTOCONF("Xscale ");
1125 			up->port.type = PORT_XSCALE;
1126 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1127 			return;
1128 		}
1129 	} else {
1130 		/*
1131 		 * If we got here we couldn't force the IER_UUE bit to 0.
1132 		 * Log it and continue.
1133 		 */
1134 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1135 	}
1136 	serial_out(up, UART_IER, iersave);
1137 
1138 	/*
1139 	 * We distinguish between 16550A and U6 16550A by counting
1140 	 * how many bytes are in the FIFO.
1141 	 */
1142 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1143 		up->port.type = PORT_U6_16550A;
1144 		up->capabilities |= UART_CAP_AFE;
1145 	}
1146 }
1147 
1148 /*
1149  * This routine is called by rs_init() to initialize a specific serial
1150  * port.  It determines what type of UART chip this serial port is
1151  * using: 8250, 16450, 16550, 16550A.  The important question is
1152  * whether or not this UART is a 16550A or not, since this will
1153  * determine whether or not we can use its FIFO features or not.
1154  */
1155 static void autoconfig(struct uart_8250_port *up)
1156 {
1157 	unsigned char status1, scratch, scratch2, scratch3;
1158 	unsigned char save_lcr, save_mcr;
1159 	struct uart_port *port = &up->port;
1160 	unsigned long flags;
1161 	unsigned int old_capabilities;
1162 
1163 	if (!port->iobase && !port->mapbase && !port->membase)
1164 		return;
1165 
1166 	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1167 		       port->name, port->iobase, port->membase);
1168 
1169 	/*
1170 	 * We really do need global IRQs disabled here - we're going to
1171 	 * be frobbing the chips IRQ enable register to see if it exists.
1172 	 *
1173 	 * Synchronize UART_IER access against the console.
1174 	 */
1175 	spin_lock_irqsave(&port->lock, flags);
1176 
1177 	up->capabilities = 0;
1178 	up->bugs = 0;
1179 
1180 	if (!(port->flags & UPF_BUGGY_UART)) {
1181 		/*
1182 		 * Do a simple existence test first; if we fail this,
1183 		 * there's no point trying anything else.
1184 		 *
1185 		 * 0x80 is used as a nonsense port to prevent against
1186 		 * false positives due to ISA bus float.  The
1187 		 * assumption is that 0x80 is a non-existent port;
1188 		 * which should be safe since include/asm/io.h also
1189 		 * makes this assumption.
1190 		 *
1191 		 * Note: this is safe as long as MCR bit 4 is clear
1192 		 * and the device is in "PC" mode.
1193 		 */
1194 		scratch = serial_in(up, UART_IER);
1195 		serial_out(up, UART_IER, 0);
1196 #ifdef __i386__
1197 		outb(0xff, 0x080);
1198 #endif
1199 		/*
1200 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1201 		 * 16C754B) allow only to modify them if an EFR bit is set.
1202 		 */
1203 		scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1204 		serial_out(up, UART_IER, UART_IER_ALL_INTR);
1205 #ifdef __i386__
1206 		outb(0, 0x080);
1207 #endif
1208 		scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1209 		serial_out(up, UART_IER, scratch);
1210 		if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1211 			/*
1212 			 * We failed; there's nothing here
1213 			 */
1214 			spin_unlock_irqrestore(&port->lock, flags);
1215 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1216 				       scratch2, scratch3);
1217 			goto out;
1218 		}
1219 	}
1220 
1221 	save_mcr = serial8250_in_MCR(up);
1222 	save_lcr = serial_in(up, UART_LCR);
1223 
1224 	/*
1225 	 * Check to see if a UART is really there.  Certain broken
1226 	 * internal modems based on the Rockwell chipset fail this
1227 	 * test, because they apparently don't implement the loopback
1228 	 * test mode.  So this test is skipped on the COM 1 through
1229 	 * COM 4 ports.  This *should* be safe, since no board
1230 	 * manufacturer would be stupid enough to design a board
1231 	 * that conflicts with COM 1-4 --- we hope!
1232 	 */
1233 	if (!(port->flags & UPF_SKIP_TEST)) {
1234 		serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1235 		status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1236 		serial8250_out_MCR(up, save_mcr);
1237 		if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1238 			spin_unlock_irqrestore(&port->lock, flags);
1239 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1240 				       status1);
1241 			goto out;
1242 		}
1243 	}
1244 
1245 	/*
1246 	 * We're pretty sure there's a port here.  Lets find out what
1247 	 * type of port it is.  The IIR top two bits allows us to find
1248 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1249 	 * determines what we test for next.
1250 	 *
1251 	 * We also initialise the EFR (if any) to zero for later.  The
1252 	 * EFR occupies the same register location as the FCR and IIR.
1253 	 */
1254 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1255 	serial_out(up, UART_EFR, 0);
1256 	serial_out(up, UART_LCR, 0);
1257 
1258 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1259 
1260 	switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1261 	case UART_IIR_FIFO_ENABLED_8250:
1262 		autoconfig_8250(up);
1263 		break;
1264 	case UART_IIR_FIFO_ENABLED_16550:
1265 		port->type = PORT_16550;
1266 		break;
1267 	case UART_IIR_FIFO_ENABLED_16550A:
1268 		autoconfig_16550a(up);
1269 		break;
1270 	default:
1271 		port->type = PORT_UNKNOWN;
1272 		break;
1273 	}
1274 
1275 #ifdef CONFIG_SERIAL_8250_RSA
1276 	/*
1277 	 * Only probe for RSA ports if we got the region.
1278 	 */
1279 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1280 	    __enable_rsa(up))
1281 		port->type = PORT_RSA;
1282 #endif
1283 
1284 	serial_out(up, UART_LCR, save_lcr);
1285 
1286 	port->fifosize = uart_config[up->port.type].fifo_size;
1287 	old_capabilities = up->capabilities;
1288 	up->capabilities = uart_config[port->type].flags;
1289 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1290 
1291 	if (port->type == PORT_UNKNOWN)
1292 		goto out_unlock;
1293 
1294 	/*
1295 	 * Reset the UART.
1296 	 */
1297 #ifdef CONFIG_SERIAL_8250_RSA
1298 	if (port->type == PORT_RSA)
1299 		serial_out(up, UART_RSA_FRR, 0);
1300 #endif
1301 	serial8250_out_MCR(up, save_mcr);
1302 	serial8250_clear_fifos(up);
1303 	serial_in(up, UART_RX);
1304 	serial8250_clear_IER(up);
1305 
1306 out_unlock:
1307 	spin_unlock_irqrestore(&port->lock, flags);
1308 
1309 	/*
1310 	 * Check if the device is a Fintek F81216A
1311 	 */
1312 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1313 		fintek_8250_probe(up);
1314 
1315 	if (up->capabilities != old_capabilities) {
1316 		dev_warn(port->dev, "detected caps %08x should be %08x\n",
1317 			 old_capabilities, up->capabilities);
1318 	}
1319 out:
1320 	DEBUG_AUTOCONF("iir=%d ", scratch);
1321 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1322 }
1323 
1324 static void autoconfig_irq(struct uart_8250_port *up)
1325 {
1326 	struct uart_port *port = &up->port;
1327 	unsigned char save_mcr, save_ier;
1328 	unsigned char save_ICP = 0;
1329 	unsigned int ICP = 0;
1330 	unsigned long irqs;
1331 	int irq;
1332 
1333 	if (port->flags & UPF_FOURPORT) {
1334 		ICP = (port->iobase & 0xfe0) | 0x1f;
1335 		save_ICP = inb_p(ICP);
1336 		outb_p(0x80, ICP);
1337 		inb_p(ICP);
1338 	}
1339 
1340 	/* forget possible initially masked and pending IRQ */
1341 	probe_irq_off(probe_irq_on());
1342 	save_mcr = serial8250_in_MCR(up);
1343 	/* Synchronize UART_IER access against the console. */
1344 	spin_lock_irq(&port->lock);
1345 	save_ier = serial_in(up, UART_IER);
1346 	spin_unlock_irq(&port->lock);
1347 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1348 
1349 	irqs = probe_irq_on();
1350 	serial8250_out_MCR(up, 0);
1351 	udelay(10);
1352 	if (port->flags & UPF_FOURPORT) {
1353 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1354 	} else {
1355 		serial8250_out_MCR(up,
1356 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1357 	}
1358 	/* Synchronize UART_IER access against the console. */
1359 	spin_lock_irq(&port->lock);
1360 	serial_out(up, UART_IER, UART_IER_ALL_INTR);
1361 	spin_unlock_irq(&port->lock);
1362 	serial_in(up, UART_LSR);
1363 	serial_in(up, UART_RX);
1364 	serial_in(up, UART_IIR);
1365 	serial_in(up, UART_MSR);
1366 	serial_out(up, UART_TX, 0xFF);
1367 	udelay(20);
1368 	irq = probe_irq_off(irqs);
1369 
1370 	serial8250_out_MCR(up, save_mcr);
1371 	/* Synchronize UART_IER access against the console. */
1372 	spin_lock_irq(&port->lock);
1373 	serial_out(up, UART_IER, save_ier);
1374 	spin_unlock_irq(&port->lock);
1375 
1376 	if (port->flags & UPF_FOURPORT)
1377 		outb_p(save_ICP, ICP);
1378 
1379 	port->irq = (irq > 0) ? irq : 0;
1380 }
1381 
1382 static void serial8250_stop_rx(struct uart_port *port)
1383 {
1384 	struct uart_8250_port *up = up_to_u8250p(port);
1385 
1386 	/* Port locked to synchronize UART_IER access against the console. */
1387 	lockdep_assert_held_once(&port->lock);
1388 
1389 	serial8250_rpm_get(up);
1390 
1391 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1392 	up->port.read_status_mask &= ~UART_LSR_DR;
1393 	serial_port_out(port, UART_IER, up->ier);
1394 
1395 	serial8250_rpm_put(up);
1396 }
1397 
1398 /**
1399  * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1400  * @p: uart 8250 port
1401  *
1402  * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1403  */
1404 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1405 {
1406 	unsigned char mcr = serial8250_in_MCR(p);
1407 
1408 	/* Port locked to synchronize UART_IER access against the console. */
1409 	lockdep_assert_held_once(&p->port.lock);
1410 
1411 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1412 		mcr |= UART_MCR_RTS;
1413 	else
1414 		mcr &= ~UART_MCR_RTS;
1415 	serial8250_out_MCR(p, mcr);
1416 
1417 	/*
1418 	 * Empty the RX FIFO, we are not interested in anything
1419 	 * received during the half-duplex transmission.
1420 	 * Enable previously disabled RX interrupts.
1421 	 */
1422 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1423 		serial8250_clear_and_reinit_fifos(p);
1424 
1425 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1426 		serial_port_out(&p->port, UART_IER, p->ier);
1427 	}
1428 }
1429 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1430 
1431 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1432 {
1433 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1434 			stop_tx_timer);
1435 	struct uart_8250_port *p = em485->port;
1436 	unsigned long flags;
1437 
1438 	serial8250_rpm_get(p);
1439 	spin_lock_irqsave(&p->port.lock, flags);
1440 	if (em485->active_timer == &em485->stop_tx_timer) {
1441 		p->rs485_stop_tx(p);
1442 		em485->active_timer = NULL;
1443 		em485->tx_stopped = true;
1444 	}
1445 	spin_unlock_irqrestore(&p->port.lock, flags);
1446 	serial8250_rpm_put(p);
1447 
1448 	return HRTIMER_NORESTART;
1449 }
1450 
1451 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1452 {
1453 	hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1454 }
1455 
1456 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1457 {
1458 	struct uart_8250_em485 *em485 = p->em485;
1459 
1460 	/* Port locked to synchronize UART_IER access against the console. */
1461 	lockdep_assert_held_once(&p->port.lock);
1462 
1463 	stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1464 
1465 	/*
1466 	 * rs485_stop_tx() is going to set RTS according to config
1467 	 * AND flush RX FIFO if required.
1468 	 */
1469 	if (stop_delay > 0) {
1470 		em485->active_timer = &em485->stop_tx_timer;
1471 		hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1472 	} else {
1473 		p->rs485_stop_tx(p);
1474 		em485->active_timer = NULL;
1475 		em485->tx_stopped = true;
1476 	}
1477 }
1478 
1479 static inline void __stop_tx(struct uart_8250_port *p)
1480 {
1481 	struct uart_8250_em485 *em485 = p->em485;
1482 
1483 	if (em485) {
1484 		u16 lsr = serial_lsr_in(p);
1485 		u64 stop_delay = 0;
1486 
1487 		if (!(lsr & UART_LSR_THRE))
1488 			return;
1489 		/*
1490 		 * To provide required timing and allow FIFO transfer,
1491 		 * __stop_tx_rs485() must be called only when both FIFO and
1492 		 * shift register are empty. The device driver should either
1493 		 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1494 		 * enlarge stop_tx_timer by the tx time of one frame to cover
1495 		 * for emptying of the shift register.
1496 		 */
1497 		if (!(lsr & UART_LSR_TEMT)) {
1498 			if (!(p->capabilities & UART_CAP_NOTEMT))
1499 				return;
1500 			/*
1501 			 * RTS might get deasserted too early with the normal
1502 			 * frame timing formula. It seems to suggest THRE might
1503 			 * get asserted already during tx of the stop bit
1504 			 * rather than after it is fully sent.
1505 			 * Roughly estimate 1 extra bit here with / 7.
1506 			 */
1507 			stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1508 		}
1509 
1510 		__stop_tx_rs485(p, stop_delay);
1511 	}
1512 
1513 	if (serial8250_clear_THRI(p))
1514 		serial8250_rpm_put_tx(p);
1515 }
1516 
1517 static void serial8250_stop_tx(struct uart_port *port)
1518 {
1519 	struct uart_8250_port *up = up_to_u8250p(port);
1520 
1521 	serial8250_rpm_get(up);
1522 	__stop_tx(up);
1523 
1524 	/*
1525 	 * We really want to stop the transmitter from sending.
1526 	 */
1527 	if (port->type == PORT_16C950) {
1528 		up->acr |= UART_ACR_TXDIS;
1529 		serial_icr_write(up, UART_ACR, up->acr);
1530 	}
1531 	serial8250_rpm_put(up);
1532 }
1533 
1534 static inline void __start_tx(struct uart_port *port)
1535 {
1536 	struct uart_8250_port *up = up_to_u8250p(port);
1537 
1538 	if (up->dma && !up->dma->tx_dma(up))
1539 		return;
1540 
1541 	if (serial8250_set_THRI(up)) {
1542 		if (up->bugs & UART_BUG_TXEN) {
1543 			u16 lsr = serial_lsr_in(up);
1544 
1545 			if (lsr & UART_LSR_THRE)
1546 				serial8250_tx_chars(up);
1547 		}
1548 	}
1549 
1550 	/*
1551 	 * Re-enable the transmitter if we disabled it.
1552 	 */
1553 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1554 		up->acr &= ~UART_ACR_TXDIS;
1555 		serial_icr_write(up, UART_ACR, up->acr);
1556 	}
1557 }
1558 
1559 /**
1560  * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1561  * @up: uart 8250 port
1562  *
1563  * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1564  * Assumes that setting the RTS bit in the MCR register means RTS is high.
1565  * (Some chips use inverse semantics.)  Further assumes that reception is
1566  * stoppable by disabling the UART_IER_RDI interrupt.  (Some chips set the
1567  * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1568  */
1569 void serial8250_em485_start_tx(struct uart_8250_port *up)
1570 {
1571 	unsigned char mcr = serial8250_in_MCR(up);
1572 
1573 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1574 		serial8250_stop_rx(&up->port);
1575 
1576 	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1577 		mcr |= UART_MCR_RTS;
1578 	else
1579 		mcr &= ~UART_MCR_RTS;
1580 	serial8250_out_MCR(up, mcr);
1581 }
1582 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1583 
1584 /* Returns false, if start_tx_timer was setup to defer TX start */
1585 static bool start_tx_rs485(struct uart_port *port)
1586 {
1587 	struct uart_8250_port *up = up_to_u8250p(port);
1588 	struct uart_8250_em485 *em485 = up->em485;
1589 
1590 	/*
1591 	 * While serial8250_em485_handle_stop_tx() is a noop if
1592 	 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1593 	 * the timer is still armed and triggers only after the current bunch of
1594 	 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1595 	 * So cancel the timer. There is still a theoretical race condition if
1596 	 * the timer is already running and only comes around to check for
1597 	 * em485->active_timer when &em485->stop_tx_timer is armed again.
1598 	 */
1599 	if (em485->active_timer == &em485->stop_tx_timer)
1600 		hrtimer_try_to_cancel(&em485->stop_tx_timer);
1601 
1602 	em485->active_timer = NULL;
1603 
1604 	if (em485->tx_stopped) {
1605 		em485->tx_stopped = false;
1606 
1607 		up->rs485_start_tx(up);
1608 
1609 		if (up->port.rs485.delay_rts_before_send > 0) {
1610 			em485->active_timer = &em485->start_tx_timer;
1611 			start_hrtimer_ms(&em485->start_tx_timer,
1612 					 up->port.rs485.delay_rts_before_send);
1613 			return false;
1614 		}
1615 	}
1616 
1617 	return true;
1618 }
1619 
1620 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1621 {
1622 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1623 			start_tx_timer);
1624 	struct uart_8250_port *p = em485->port;
1625 	unsigned long flags;
1626 
1627 	spin_lock_irqsave(&p->port.lock, flags);
1628 	if (em485->active_timer == &em485->start_tx_timer) {
1629 		__start_tx(&p->port);
1630 		em485->active_timer = NULL;
1631 	}
1632 	spin_unlock_irqrestore(&p->port.lock, flags);
1633 
1634 	return HRTIMER_NORESTART;
1635 }
1636 
1637 static void serial8250_start_tx(struct uart_port *port)
1638 {
1639 	struct uart_8250_port *up = up_to_u8250p(port);
1640 	struct uart_8250_em485 *em485 = up->em485;
1641 
1642 	/* Port locked to synchronize UART_IER access against the console. */
1643 	lockdep_assert_held_once(&port->lock);
1644 
1645 	if (!port->x_char && uart_circ_empty(&port->state->xmit))
1646 		return;
1647 
1648 	serial8250_rpm_get_tx(up);
1649 
1650 	if (em485) {
1651 		if ((em485->active_timer == &em485->start_tx_timer) ||
1652 		    !start_tx_rs485(port))
1653 			return;
1654 	}
1655 	__start_tx(port);
1656 }
1657 
1658 static void serial8250_throttle(struct uart_port *port)
1659 {
1660 	port->throttle(port);
1661 }
1662 
1663 static void serial8250_unthrottle(struct uart_port *port)
1664 {
1665 	port->unthrottle(port);
1666 }
1667 
1668 static void serial8250_disable_ms(struct uart_port *port)
1669 {
1670 	struct uart_8250_port *up = up_to_u8250p(port);
1671 
1672 	/* Port locked to synchronize UART_IER access against the console. */
1673 	lockdep_assert_held_once(&port->lock);
1674 
1675 	/* no MSR capabilities */
1676 	if (up->bugs & UART_BUG_NOMSR)
1677 		return;
1678 
1679 	mctrl_gpio_disable_ms(up->gpios);
1680 
1681 	up->ier &= ~UART_IER_MSI;
1682 	serial_port_out(port, UART_IER, up->ier);
1683 }
1684 
1685 static void serial8250_enable_ms(struct uart_port *port)
1686 {
1687 	struct uart_8250_port *up = up_to_u8250p(port);
1688 
1689 	/* Port locked to synchronize UART_IER access against the console. */
1690 	lockdep_assert_held_once(&port->lock);
1691 
1692 	/* no MSR capabilities */
1693 	if (up->bugs & UART_BUG_NOMSR)
1694 		return;
1695 
1696 	mctrl_gpio_enable_ms(up->gpios);
1697 
1698 	up->ier |= UART_IER_MSI;
1699 
1700 	serial8250_rpm_get(up);
1701 	serial_port_out(port, UART_IER, up->ier);
1702 	serial8250_rpm_put(up);
1703 }
1704 
1705 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1706 {
1707 	struct uart_port *port = &up->port;
1708 	u8 ch, flag = TTY_NORMAL;
1709 
1710 	if (likely(lsr & UART_LSR_DR))
1711 		ch = serial_in(up, UART_RX);
1712 	else
1713 		/*
1714 		 * Intel 82571 has a Serial Over Lan device that will
1715 		 * set UART_LSR_BI without setting UART_LSR_DR when
1716 		 * it receives a break. To avoid reading from the
1717 		 * receive buffer without UART_LSR_DR bit set, we
1718 		 * just force the read character to be 0
1719 		 */
1720 		ch = 0;
1721 
1722 	port->icount.rx++;
1723 
1724 	lsr |= up->lsr_saved_flags;
1725 	up->lsr_saved_flags = 0;
1726 
1727 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1728 		if (lsr & UART_LSR_BI) {
1729 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1730 			port->icount.brk++;
1731 			/*
1732 			 * We do the SysRQ and SAK checking
1733 			 * here because otherwise the break
1734 			 * may get masked by ignore_status_mask
1735 			 * or read_status_mask.
1736 			 */
1737 			if (uart_handle_break(port))
1738 				return;
1739 		} else if (lsr & UART_LSR_PE)
1740 			port->icount.parity++;
1741 		else if (lsr & UART_LSR_FE)
1742 			port->icount.frame++;
1743 		if (lsr & UART_LSR_OE)
1744 			port->icount.overrun++;
1745 
1746 		/*
1747 		 * Mask off conditions which should be ignored.
1748 		 */
1749 		lsr &= port->read_status_mask;
1750 
1751 		if (lsr & UART_LSR_BI) {
1752 			dev_dbg(port->dev, "handling break\n");
1753 			flag = TTY_BREAK;
1754 		} else if (lsr & UART_LSR_PE)
1755 			flag = TTY_PARITY;
1756 		else if (lsr & UART_LSR_FE)
1757 			flag = TTY_FRAME;
1758 	}
1759 	if (uart_prepare_sysrq_char(port, ch))
1760 		return;
1761 
1762 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1763 }
1764 EXPORT_SYMBOL_GPL(serial8250_read_char);
1765 
1766 /*
1767  * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1768  *
1769  * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1770  * (such as THRE) because the LSR value might come from an already consumed
1771  * character.
1772  */
1773 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1774 {
1775 	struct uart_port *port = &up->port;
1776 	int max_count = 256;
1777 
1778 	do {
1779 		serial8250_read_char(up, lsr);
1780 		if (--max_count == 0)
1781 			break;
1782 		lsr = serial_in(up, UART_LSR);
1783 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1784 
1785 	tty_flip_buffer_push(&port->state->port);
1786 	return lsr;
1787 }
1788 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1789 
1790 void serial8250_tx_chars(struct uart_8250_port *up)
1791 {
1792 	struct uart_port *port = &up->port;
1793 	struct circ_buf *xmit = &port->state->xmit;
1794 	int count;
1795 
1796 	if (port->x_char) {
1797 		uart_xchar_out(port, UART_TX);
1798 		return;
1799 	}
1800 	if (uart_tx_stopped(port)) {
1801 		serial8250_stop_tx(port);
1802 		return;
1803 	}
1804 	if (uart_circ_empty(xmit)) {
1805 		__stop_tx(up);
1806 		return;
1807 	}
1808 
1809 	count = up->tx_loadsz;
1810 	do {
1811 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1812 		if (up->bugs & UART_BUG_TXRACE) {
1813 			/*
1814 			 * The Aspeed BMC virtual UARTs have a bug where data
1815 			 * may get stuck in the BMC's Tx FIFO from bursts of
1816 			 * writes on the APB interface.
1817 			 *
1818 			 * Delay back-to-back writes by a read cycle to avoid
1819 			 * stalling the VUART. Read a register that won't have
1820 			 * side-effects and discard the result.
1821 			 */
1822 			serial_in(up, UART_SCR);
1823 		}
1824 		uart_xmit_advance(port, 1);
1825 		if (uart_circ_empty(xmit))
1826 			break;
1827 		if ((up->capabilities & UART_CAP_HFIFO) &&
1828 		    !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1829 			break;
1830 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1831 		if ((up->capabilities & UART_CAP_MINI) &&
1832 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1833 			break;
1834 	} while (--count > 0);
1835 
1836 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1837 		uart_write_wakeup(port);
1838 
1839 	/*
1840 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1841 	 * HW can go idle. So we get here once again with empty FIFO and disable
1842 	 * the interrupt and RPM in __stop_tx()
1843 	 */
1844 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1845 		__stop_tx(up);
1846 }
1847 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1848 
1849 /* Caller holds uart port lock */
1850 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1851 {
1852 	struct uart_port *port = &up->port;
1853 	unsigned int status = serial_in(up, UART_MSR);
1854 
1855 	status |= up->msr_saved_flags;
1856 	up->msr_saved_flags = 0;
1857 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1858 	    port->state != NULL) {
1859 		if (status & UART_MSR_TERI)
1860 			port->icount.rng++;
1861 		if (status & UART_MSR_DDSR)
1862 			port->icount.dsr++;
1863 		if (status & UART_MSR_DDCD)
1864 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1865 		if (status & UART_MSR_DCTS)
1866 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1867 
1868 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1869 	}
1870 
1871 	return status;
1872 }
1873 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1874 
1875 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1876 {
1877 	switch (iir & 0x3f) {
1878 	case UART_IIR_THRI:
1879 		/*
1880 		 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1881 		 * because it's impossible to do an informed decision about
1882 		 * that with IIR_THRI.
1883 		 *
1884 		 * This also fixes one known DMA Rx corruption issue where
1885 		 * DR is asserted but DMA Rx only gets a corrupted zero byte
1886 		 * (too early DR?).
1887 		 */
1888 		return false;
1889 	case UART_IIR_RDI:
1890 		if (!up->dma->rx_running)
1891 			break;
1892 		fallthrough;
1893 	case UART_IIR_RLSI:
1894 	case UART_IIR_RX_TIMEOUT:
1895 		serial8250_rx_dma_flush(up);
1896 		return true;
1897 	}
1898 	return up->dma->rx_dma(up);
1899 }
1900 
1901 /*
1902  * This handles the interrupt from one port.
1903  */
1904 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1905 {
1906 	struct uart_8250_port *up = up_to_u8250p(port);
1907 	struct tty_port *tport = &port->state->port;
1908 	bool skip_rx = false;
1909 	unsigned long flags;
1910 	u16 status;
1911 
1912 	if (iir & UART_IIR_NO_INT)
1913 		return 0;
1914 
1915 	spin_lock_irqsave(&port->lock, flags);
1916 
1917 	status = serial_lsr_in(up);
1918 
1919 	/*
1920 	 * If port is stopped and there are no error conditions in the
1921 	 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1922 	 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1923 	 * control when FIFO occupancy reaches preset threshold, thus
1924 	 * halting RX. This only works when auto HW flow control is
1925 	 * available.
1926 	 */
1927 	if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1928 	    (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1929 	    !(port->read_status_mask & UART_LSR_DR))
1930 		skip_rx = true;
1931 
1932 	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1933 		struct irq_data *d;
1934 
1935 		d = irq_get_irq_data(port->irq);
1936 		if (d && irqd_is_wakeup_set(d))
1937 			pm_wakeup_event(tport->tty->dev, 0);
1938 		if (!up->dma || handle_rx_dma(up, iir))
1939 			status = serial8250_rx_chars(up, status);
1940 	}
1941 	serial8250_modem_status(up);
1942 	if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1943 		if (!up->dma || up->dma->tx_err)
1944 			serial8250_tx_chars(up);
1945 		else if (!up->dma->tx_running)
1946 			__stop_tx(up);
1947 	}
1948 
1949 	uart_unlock_and_check_sysrq_irqrestore(port, flags);
1950 
1951 	return 1;
1952 }
1953 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1954 
1955 static int serial8250_default_handle_irq(struct uart_port *port)
1956 {
1957 	struct uart_8250_port *up = up_to_u8250p(port);
1958 	unsigned int iir;
1959 	int ret;
1960 
1961 	serial8250_rpm_get(up);
1962 
1963 	iir = serial_port_in(port, UART_IIR);
1964 	ret = serial8250_handle_irq(port, iir);
1965 
1966 	serial8250_rpm_put(up);
1967 	return ret;
1968 }
1969 
1970 /*
1971  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1972  * have a programmable TX threshold that triggers the THRE interrupt in
1973  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1974  * has space available. Load it up with tx_loadsz bytes.
1975  */
1976 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1977 {
1978 	unsigned long flags;
1979 	unsigned int iir = serial_port_in(port, UART_IIR);
1980 
1981 	/* TX Threshold IRQ triggered so load up FIFO */
1982 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1983 		struct uart_8250_port *up = up_to_u8250p(port);
1984 
1985 		spin_lock_irqsave(&port->lock, flags);
1986 		serial8250_tx_chars(up);
1987 		spin_unlock_irqrestore(&port->lock, flags);
1988 	}
1989 
1990 	iir = serial_port_in(port, UART_IIR);
1991 	return serial8250_handle_irq(port, iir);
1992 }
1993 
1994 static unsigned int serial8250_tx_empty(struct uart_port *port)
1995 {
1996 	struct uart_8250_port *up = up_to_u8250p(port);
1997 	unsigned int result = 0;
1998 	unsigned long flags;
1999 
2000 	serial8250_rpm_get(up);
2001 
2002 	spin_lock_irqsave(&port->lock, flags);
2003 	if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
2004 		result = TIOCSER_TEMT;
2005 	spin_unlock_irqrestore(&port->lock, flags);
2006 
2007 	serial8250_rpm_put(up);
2008 
2009 	return result;
2010 }
2011 
2012 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2013 {
2014 	struct uart_8250_port *up = up_to_u8250p(port);
2015 	unsigned int status;
2016 	unsigned int val;
2017 
2018 	serial8250_rpm_get(up);
2019 	status = serial8250_modem_status(up);
2020 	serial8250_rpm_put(up);
2021 
2022 	val = serial8250_MSR_to_TIOCM(status);
2023 	if (up->gpios)
2024 		return mctrl_gpio_get(up->gpios, &val);
2025 
2026 	return val;
2027 }
2028 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2029 
2030 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2031 {
2032 	if (port->get_mctrl)
2033 		return port->get_mctrl(port);
2034 	return serial8250_do_get_mctrl(port);
2035 }
2036 
2037 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2038 {
2039 	struct uart_8250_port *up = up_to_u8250p(port);
2040 	unsigned char mcr;
2041 
2042 	mcr = serial8250_TIOCM_to_MCR(mctrl);
2043 
2044 	mcr |= up->mcr;
2045 
2046 	serial8250_out_MCR(up, mcr);
2047 }
2048 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2049 
2050 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2051 {
2052 	if (port->rs485.flags & SER_RS485_ENABLED)
2053 		return;
2054 
2055 	if (port->set_mctrl)
2056 		port->set_mctrl(port, mctrl);
2057 	else
2058 		serial8250_do_set_mctrl(port, mctrl);
2059 }
2060 
2061 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2062 {
2063 	struct uart_8250_port *up = up_to_u8250p(port);
2064 	unsigned long flags;
2065 
2066 	serial8250_rpm_get(up);
2067 	spin_lock_irqsave(&port->lock, flags);
2068 	if (break_state == -1)
2069 		up->lcr |= UART_LCR_SBC;
2070 	else
2071 		up->lcr &= ~UART_LCR_SBC;
2072 	serial_port_out(port, UART_LCR, up->lcr);
2073 	spin_unlock_irqrestore(&port->lock, flags);
2074 	serial8250_rpm_put(up);
2075 }
2076 
2077 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2078 {
2079 	unsigned int status, tmout = 10000;
2080 
2081 	/* Wait up to 10ms for the character(s) to be sent. */
2082 	for (;;) {
2083 		status = serial_lsr_in(up);
2084 
2085 		if ((status & bits) == bits)
2086 			break;
2087 		if (--tmout == 0)
2088 			break;
2089 		udelay(1);
2090 		touch_nmi_watchdog();
2091 	}
2092 }
2093 
2094 /*
2095  *	Wait for transmitter & holding register to empty
2096  */
2097 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2098 {
2099 	unsigned int tmout;
2100 
2101 	wait_for_lsr(up, bits);
2102 
2103 	/* Wait up to 1s for flow control if necessary */
2104 	if (up->port.flags & UPF_CONS_FLOW) {
2105 		for (tmout = 1000000; tmout; tmout--) {
2106 			unsigned int msr = serial_in(up, UART_MSR);
2107 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2108 			if (msr & UART_MSR_CTS)
2109 				break;
2110 			udelay(1);
2111 			touch_nmi_watchdog();
2112 		}
2113 	}
2114 }
2115 
2116 #ifdef CONFIG_CONSOLE_POLL
2117 /*
2118  * Console polling routines for writing and reading from the uart while
2119  * in an interrupt or debug context.
2120  */
2121 
2122 static int serial8250_get_poll_char(struct uart_port *port)
2123 {
2124 	struct uart_8250_port *up = up_to_u8250p(port);
2125 	int status;
2126 	u16 lsr;
2127 
2128 	serial8250_rpm_get(up);
2129 
2130 	lsr = serial_port_in(port, UART_LSR);
2131 
2132 	if (!(lsr & UART_LSR_DR)) {
2133 		status = NO_POLL_CHAR;
2134 		goto out;
2135 	}
2136 
2137 	status = serial_port_in(port, UART_RX);
2138 out:
2139 	serial8250_rpm_put(up);
2140 	return status;
2141 }
2142 
2143 
2144 static void serial8250_put_poll_char(struct uart_port *port,
2145 			 unsigned char c)
2146 {
2147 	unsigned int ier;
2148 	struct uart_8250_port *up = up_to_u8250p(port);
2149 
2150 	/*
2151 	 * Normally the port is locked to synchronize UART_IER access
2152 	 * against the console. However, this function is only used by
2153 	 * KDB/KGDB, where it may not be possible to acquire the port
2154 	 * lock because all other CPUs are quiesced. The quiescence
2155 	 * should allow safe lockless usage here.
2156 	 */
2157 
2158 	serial8250_rpm_get(up);
2159 	/*
2160 	 *	First save the IER then disable the interrupts
2161 	 */
2162 	ier = serial_port_in(port, UART_IER);
2163 	serial8250_clear_IER(up);
2164 
2165 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2166 	/*
2167 	 *	Send the character out.
2168 	 */
2169 	serial_port_out(port, UART_TX, c);
2170 
2171 	/*
2172 	 *	Finally, wait for transmitter to become empty
2173 	 *	and restore the IER
2174 	 */
2175 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2176 	serial_port_out(port, UART_IER, ier);
2177 	serial8250_rpm_put(up);
2178 }
2179 
2180 #endif /* CONFIG_CONSOLE_POLL */
2181 
2182 int serial8250_do_startup(struct uart_port *port)
2183 {
2184 	struct uart_8250_port *up = up_to_u8250p(port);
2185 	unsigned long flags;
2186 	unsigned char iir;
2187 	int retval;
2188 	u16 lsr;
2189 
2190 	if (!port->fifosize)
2191 		port->fifosize = uart_config[port->type].fifo_size;
2192 	if (!up->tx_loadsz)
2193 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2194 	if (!up->capabilities)
2195 		up->capabilities = uart_config[port->type].flags;
2196 	up->mcr = 0;
2197 
2198 	if (port->iotype != up->cur_iotype)
2199 		set_io_from_upio(port);
2200 
2201 	serial8250_rpm_get(up);
2202 	if (port->type == PORT_16C950) {
2203 		/*
2204 		 * Wake up and initialize UART
2205 		 *
2206 		 * Synchronize UART_IER access against the console.
2207 		 */
2208 		spin_lock_irqsave(&port->lock, flags);
2209 		up->acr = 0;
2210 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2211 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2212 		serial_port_out(port, UART_IER, 0);
2213 		serial_port_out(port, UART_LCR, 0);
2214 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2215 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2216 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2217 		serial_port_out(port, UART_LCR, 0);
2218 		spin_unlock_irqrestore(&port->lock, flags);
2219 	}
2220 
2221 	if (port->type == PORT_DA830) {
2222 		/*
2223 		 * Reset the port
2224 		 *
2225 		 * Synchronize UART_IER access against the console.
2226 		 */
2227 		spin_lock_irqsave(&port->lock, flags);
2228 		serial_port_out(port, UART_IER, 0);
2229 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2230 		spin_unlock_irqrestore(&port->lock, flags);
2231 		mdelay(10);
2232 
2233 		/* Enable Tx, Rx and free run mode */
2234 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2235 				UART_DA830_PWREMU_MGMT_UTRST |
2236 				UART_DA830_PWREMU_MGMT_URRST |
2237 				UART_DA830_PWREMU_MGMT_FREE);
2238 	}
2239 
2240 	if (port->type == PORT_NPCM) {
2241 		/*
2242 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2243 		 * register). Enable it, and set TIOC (timeout interrupt
2244 		 * comparator) to be 0x20 for correct operation.
2245 		 */
2246 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2247 	}
2248 
2249 #ifdef CONFIG_SERIAL_8250_RSA
2250 	/*
2251 	 * If this is an RSA port, see if we can kick it up to the
2252 	 * higher speed clock.
2253 	 */
2254 	enable_rsa(up);
2255 #endif
2256 
2257 	/*
2258 	 * Clear the FIFO buffers and disable them.
2259 	 * (they will be reenabled in set_termios())
2260 	 */
2261 	serial8250_clear_fifos(up);
2262 
2263 	/*
2264 	 * Clear the interrupt registers.
2265 	 */
2266 	serial_port_in(port, UART_LSR);
2267 	serial_port_in(port, UART_RX);
2268 	serial_port_in(port, UART_IIR);
2269 	serial_port_in(port, UART_MSR);
2270 
2271 	/*
2272 	 * At this point, there's no way the LSR could still be 0xff;
2273 	 * if it is, then bail out, because there's likely no UART
2274 	 * here.
2275 	 */
2276 	if (!(port->flags & UPF_BUGGY_UART) &&
2277 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2278 		dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2279 		retval = -ENODEV;
2280 		goto out;
2281 	}
2282 
2283 	/*
2284 	 * For a XR16C850, we need to set the trigger levels
2285 	 */
2286 	if (port->type == PORT_16850) {
2287 		unsigned char fctr;
2288 
2289 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2290 
2291 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2292 		serial_port_out(port, UART_FCTR,
2293 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2294 		serial_port_out(port, UART_TRG, UART_TRG_96);
2295 		serial_port_out(port, UART_FCTR,
2296 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2297 		serial_port_out(port, UART_TRG, UART_TRG_96);
2298 
2299 		serial_port_out(port, UART_LCR, 0);
2300 	}
2301 
2302 	/*
2303 	 * For the Altera 16550 variants, set TX threshold trigger level.
2304 	 */
2305 	if (((port->type == PORT_ALTR_16550_F32) ||
2306 	     (port->type == PORT_ALTR_16550_F64) ||
2307 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2308 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2309 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2310 			dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2311 		} else {
2312 			serial_port_out(port, UART_ALTR_AFR,
2313 					UART_ALTR_EN_TXFIFO_LW);
2314 			serial_port_out(port, UART_ALTR_TX_LOW,
2315 					port->fifosize - up->tx_loadsz);
2316 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2317 		}
2318 	}
2319 
2320 	/* Check if we need to have shared IRQs */
2321 	if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2322 		up->port.irqflags |= IRQF_SHARED;
2323 
2324 	retval = up->ops->setup_irq(up);
2325 	if (retval)
2326 		goto out;
2327 
2328 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2329 		unsigned char iir1;
2330 
2331 		if (port->irqflags & IRQF_SHARED)
2332 			disable_irq_nosync(port->irq);
2333 
2334 		/*
2335 		 * Test for UARTs that do not reassert THRE when the
2336 		 * transmitter is idle and the interrupt has already
2337 		 * been cleared.  Real 16550s should always reassert
2338 		 * this interrupt whenever the transmitter is idle and
2339 		 * the interrupt is enabled.  Delays are necessary to
2340 		 * allow register changes to become visible.
2341 		 *
2342 		 * Synchronize UART_IER access against the console.
2343 		 */
2344 		spin_lock_irqsave(&port->lock, flags);
2345 
2346 		wait_for_xmitr(up, UART_LSR_THRE);
2347 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2348 		udelay(1); /* allow THRE to set */
2349 		iir1 = serial_port_in(port, UART_IIR);
2350 		serial_port_out(port, UART_IER, 0);
2351 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2352 		udelay(1); /* allow a working UART time to re-assert THRE */
2353 		iir = serial_port_in(port, UART_IIR);
2354 		serial_port_out(port, UART_IER, 0);
2355 
2356 		spin_unlock_irqrestore(&port->lock, flags);
2357 
2358 		if (port->irqflags & IRQF_SHARED)
2359 			enable_irq(port->irq);
2360 
2361 		/*
2362 		 * If the interrupt is not reasserted, or we otherwise
2363 		 * don't trust the iir, setup a timer to kick the UART
2364 		 * on a regular basis.
2365 		 */
2366 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2367 		    up->port.flags & UPF_BUG_THRE) {
2368 			up->bugs |= UART_BUG_THRE;
2369 		}
2370 	}
2371 
2372 	up->ops->setup_timer(up);
2373 
2374 	/*
2375 	 * Now, initialize the UART
2376 	 */
2377 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2378 
2379 	spin_lock_irqsave(&port->lock, flags);
2380 	if (up->port.flags & UPF_FOURPORT) {
2381 		if (!up->port.irq)
2382 			up->port.mctrl |= TIOCM_OUT1;
2383 	} else
2384 		/*
2385 		 * Most PC uarts need OUT2 raised to enable interrupts.
2386 		 */
2387 		if (port->irq)
2388 			up->port.mctrl |= TIOCM_OUT2;
2389 
2390 	serial8250_set_mctrl(port, port->mctrl);
2391 
2392 	/*
2393 	 * Serial over Lan (SoL) hack:
2394 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2395 	 * used for Serial Over Lan.  Those chips take a longer time than a
2396 	 * normal serial device to signalize that a transmission data was
2397 	 * queued. Due to that, the above test generally fails. One solution
2398 	 * would be to delay the reading of iir. However, this is not
2399 	 * reliable, since the timeout is variable. So, let's just don't
2400 	 * test if we receive TX irq.  This way, we'll never enable
2401 	 * UART_BUG_TXEN.
2402 	 */
2403 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2404 		goto dont_test_tx_en;
2405 
2406 	/*
2407 	 * Do a quick test to see if we receive an interrupt when we enable
2408 	 * the TX irq.
2409 	 */
2410 	serial_port_out(port, UART_IER, UART_IER_THRI);
2411 	lsr = serial_port_in(port, UART_LSR);
2412 	iir = serial_port_in(port, UART_IIR);
2413 	serial_port_out(port, UART_IER, 0);
2414 
2415 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2416 		if (!(up->bugs & UART_BUG_TXEN)) {
2417 			up->bugs |= UART_BUG_TXEN;
2418 			dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2419 		}
2420 	} else {
2421 		up->bugs &= ~UART_BUG_TXEN;
2422 	}
2423 
2424 dont_test_tx_en:
2425 	spin_unlock_irqrestore(&port->lock, flags);
2426 
2427 	/*
2428 	 * Clear the interrupt registers again for luck, and clear the
2429 	 * saved flags to avoid getting false values from polling
2430 	 * routines or the previous session.
2431 	 */
2432 	serial_port_in(port, UART_LSR);
2433 	serial_port_in(port, UART_RX);
2434 	serial_port_in(port, UART_IIR);
2435 	serial_port_in(port, UART_MSR);
2436 	up->lsr_saved_flags = 0;
2437 	up->msr_saved_flags = 0;
2438 
2439 	/*
2440 	 * Request DMA channels for both RX and TX.
2441 	 */
2442 	if (up->dma) {
2443 		const char *msg = NULL;
2444 
2445 		if (uart_console(port))
2446 			msg = "forbid DMA for kernel console";
2447 		else if (serial8250_request_dma(up))
2448 			msg = "failed to request DMA";
2449 		if (msg) {
2450 			dev_warn_ratelimited(port->dev, "%s\n", msg);
2451 			up->dma = NULL;
2452 		}
2453 	}
2454 
2455 	/*
2456 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2457 	 * enable until after the FIFOs are enabled; otherwise, an already-
2458 	 * active sender can swamp the interrupt handler with "too much work".
2459 	 */
2460 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2461 
2462 	if (port->flags & UPF_FOURPORT) {
2463 		unsigned int icp;
2464 		/*
2465 		 * Enable interrupts on the AST Fourport board
2466 		 */
2467 		icp = (port->iobase & 0xfe0) | 0x01f;
2468 		outb_p(0x80, icp);
2469 		inb_p(icp);
2470 	}
2471 	retval = 0;
2472 out:
2473 	serial8250_rpm_put(up);
2474 	return retval;
2475 }
2476 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2477 
2478 static int serial8250_startup(struct uart_port *port)
2479 {
2480 	if (port->startup)
2481 		return port->startup(port);
2482 	return serial8250_do_startup(port);
2483 }
2484 
2485 void serial8250_do_shutdown(struct uart_port *port)
2486 {
2487 	struct uart_8250_port *up = up_to_u8250p(port);
2488 	unsigned long flags;
2489 
2490 	serial8250_rpm_get(up);
2491 	/*
2492 	 * Disable interrupts from this port
2493 	 *
2494 	 * Synchronize UART_IER access against the console.
2495 	 */
2496 	spin_lock_irqsave(&port->lock, flags);
2497 	up->ier = 0;
2498 	serial_port_out(port, UART_IER, 0);
2499 	spin_unlock_irqrestore(&port->lock, flags);
2500 
2501 	synchronize_irq(port->irq);
2502 
2503 	if (up->dma)
2504 		serial8250_release_dma(up);
2505 
2506 	spin_lock_irqsave(&port->lock, flags);
2507 	if (port->flags & UPF_FOURPORT) {
2508 		/* reset interrupts on the AST Fourport board */
2509 		inb((port->iobase & 0xfe0) | 0x1f);
2510 		port->mctrl |= TIOCM_OUT1;
2511 	} else
2512 		port->mctrl &= ~TIOCM_OUT2;
2513 
2514 	serial8250_set_mctrl(port, port->mctrl);
2515 	spin_unlock_irqrestore(&port->lock, flags);
2516 
2517 	/*
2518 	 * Disable break condition and FIFOs
2519 	 */
2520 	serial_port_out(port, UART_LCR,
2521 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2522 	serial8250_clear_fifos(up);
2523 
2524 #ifdef CONFIG_SERIAL_8250_RSA
2525 	/*
2526 	 * Reset the RSA board back to 115kbps compat mode.
2527 	 */
2528 	disable_rsa(up);
2529 #endif
2530 
2531 	/*
2532 	 * Read data port to reset things, and then unlink from
2533 	 * the IRQ chain.
2534 	 */
2535 	serial_port_in(port, UART_RX);
2536 	serial8250_rpm_put(up);
2537 
2538 	up->ops->release_irq(up);
2539 }
2540 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2541 
2542 static void serial8250_shutdown(struct uart_port *port)
2543 {
2544 	if (port->shutdown)
2545 		port->shutdown(port);
2546 	else
2547 		serial8250_do_shutdown(port);
2548 }
2549 
2550 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2551 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2552 		unsigned int baud)
2553 {
2554 	struct uart_port *port = &up->port;
2555 
2556 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2557 }
2558 
2559 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2560 					      unsigned int baud,
2561 					      unsigned int *frac)
2562 {
2563 	upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2564 	struct uart_8250_port *up = up_to_u8250p(port);
2565 	unsigned int quot;
2566 
2567 	/*
2568 	 * Handle magic divisors for baud rates above baud_base on SMSC
2569 	 * Super I/O chips.  We clamp custom rates from clk/6 and clk/12
2570 	 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively.  These
2571 	 * magic divisors actually reprogram the baud rate generator's
2572 	 * reference clock derived from chips's 14.318MHz clock input.
2573 	 *
2574 	 * Documentation claims that with these magic divisors the base
2575 	 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2576 	 * for the extra baud rates of 460800bps and 230400bps rather
2577 	 * than the usual base frequency of 1.8462MHz.  However empirical
2578 	 * evidence contradicts that.
2579 	 *
2580 	 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2581 	 * effectively used as a clock prescaler selection bit for the
2582 	 * base frequency of 7.3728MHz, always used.  If set to 0, then
2583 	 * the base frequency is divided by 4 for use by the Baud Rate
2584 	 * Generator, for the usual arrangement where the value of 1 of
2585 	 * the divisor produces the baud rate of 115200bps.  Conversely,
2586 	 * if set to 1 and high-speed operation has been enabled with the
2587 	 * Serial Port Mode Register in the Device Configuration Space,
2588 	 * then the base frequency is supplied directly to the Baud Rate
2589 	 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2590 	 * 0x8004, etc. the respective baud rates produced are 460800bps,
2591 	 * 230400bps, 153600bps, 115200bps, etc.
2592 	 *
2593 	 * In all cases only low 15 bits of the divisor are used to divide
2594 	 * the baud base and therefore 32767 is the maximum divisor value
2595 	 * possible, even though documentation says that the programmable
2596 	 * Baud Rate Generator is capable of dividing the internal PLL
2597 	 * clock by any divisor from 1 to 65535.
2598 	 */
2599 	if (magic_multiplier && baud >= port->uartclk / 6)
2600 		quot = 0x8001;
2601 	else if (magic_multiplier && baud >= port->uartclk / 12)
2602 		quot = 0x8002;
2603 	else if (up->port.type == PORT_NPCM)
2604 		quot = npcm_get_divisor(up, baud);
2605 	else
2606 		quot = uart_get_divisor(port, baud);
2607 
2608 	/*
2609 	 * Oxford Semi 952 rev B workaround
2610 	 */
2611 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2612 		quot++;
2613 
2614 	return quot;
2615 }
2616 
2617 static unsigned int serial8250_get_divisor(struct uart_port *port,
2618 					   unsigned int baud,
2619 					   unsigned int *frac)
2620 {
2621 	if (port->get_divisor)
2622 		return port->get_divisor(port, baud, frac);
2623 
2624 	return serial8250_do_get_divisor(port, baud, frac);
2625 }
2626 
2627 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2628 					    tcflag_t c_cflag)
2629 {
2630 	unsigned char cval;
2631 
2632 	cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2633 
2634 	if (c_cflag & CSTOPB)
2635 		cval |= UART_LCR_STOP;
2636 	if (c_cflag & PARENB)
2637 		cval |= UART_LCR_PARITY;
2638 	if (!(c_cflag & PARODD))
2639 		cval |= UART_LCR_EPAR;
2640 	if (c_cflag & CMSPAR)
2641 		cval |= UART_LCR_SPAR;
2642 
2643 	return cval;
2644 }
2645 
2646 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2647 			       unsigned int quot, unsigned int quot_frac)
2648 {
2649 	struct uart_8250_port *up = up_to_u8250p(port);
2650 
2651 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2652 	if (is_omap1510_8250(up)) {
2653 		if (baud == 115200) {
2654 			quot = 1;
2655 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2656 		} else
2657 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2658 	}
2659 
2660 	/*
2661 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2662 	 * otherwise just set DLAB
2663 	 */
2664 	if (up->capabilities & UART_NATSEMI)
2665 		serial_port_out(port, UART_LCR, 0xe0);
2666 	else
2667 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2668 
2669 	serial_dl_write(up, quot);
2670 }
2671 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2672 
2673 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2674 				   unsigned int quot, unsigned int quot_frac)
2675 {
2676 	if (port->set_divisor)
2677 		port->set_divisor(port, baud, quot, quot_frac);
2678 	else
2679 		serial8250_do_set_divisor(port, baud, quot, quot_frac);
2680 }
2681 
2682 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2683 					     struct ktermios *termios,
2684 					     const struct ktermios *old)
2685 {
2686 	unsigned int tolerance = port->uartclk / 100;
2687 	unsigned int min;
2688 	unsigned int max;
2689 
2690 	/*
2691 	 * Handle magic divisors for baud rates above baud_base on SMSC
2692 	 * Super I/O chips.  Enable custom rates of clk/4 and clk/8, but
2693 	 * disable divisor values beyond 32767, which are unavailable.
2694 	 */
2695 	if (port->flags & UPF_MAGIC_MULTIPLIER) {
2696 		min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2697 		max = (port->uartclk + tolerance) / 4;
2698 	} else {
2699 		min = port->uartclk / 16 / UART_DIV_MAX;
2700 		max = (port->uartclk + tolerance) / 16;
2701 	}
2702 
2703 	/*
2704 	 * Ask the core to calculate the divisor for us.
2705 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2706 	 * slower than nominal still match standard baud rates without
2707 	 * causing transmission errors.
2708 	 */
2709 	return uart_get_baud_rate(port, termios, old, min, max);
2710 }
2711 
2712 /*
2713  * Note in order to avoid the tty port mutex deadlock don't use the next method
2714  * within the uart port callbacks. Primarily it's supposed to be utilized to
2715  * handle a sudden reference clock rate change.
2716  */
2717 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2718 {
2719 	struct uart_8250_port *up = up_to_u8250p(port);
2720 	struct tty_port *tport = &port->state->port;
2721 	unsigned int baud, quot, frac = 0;
2722 	struct ktermios *termios;
2723 	struct tty_struct *tty;
2724 	unsigned long flags;
2725 
2726 	tty = tty_port_tty_get(tport);
2727 	if (!tty) {
2728 		mutex_lock(&tport->mutex);
2729 		port->uartclk = uartclk;
2730 		mutex_unlock(&tport->mutex);
2731 		return;
2732 	}
2733 
2734 	down_write(&tty->termios_rwsem);
2735 	mutex_lock(&tport->mutex);
2736 
2737 	if (port->uartclk == uartclk)
2738 		goto out_unlock;
2739 
2740 	port->uartclk = uartclk;
2741 
2742 	if (!tty_port_initialized(tport))
2743 		goto out_unlock;
2744 
2745 	termios = &tty->termios;
2746 
2747 	baud = serial8250_get_baud_rate(port, termios, NULL);
2748 	quot = serial8250_get_divisor(port, baud, &frac);
2749 
2750 	serial8250_rpm_get(up);
2751 	spin_lock_irqsave(&port->lock, flags);
2752 
2753 	uart_update_timeout(port, termios->c_cflag, baud);
2754 
2755 	serial8250_set_divisor(port, baud, quot, frac);
2756 	serial_port_out(port, UART_LCR, up->lcr);
2757 
2758 	spin_unlock_irqrestore(&port->lock, flags);
2759 	serial8250_rpm_put(up);
2760 
2761 out_unlock:
2762 	mutex_unlock(&tport->mutex);
2763 	up_write(&tty->termios_rwsem);
2764 	tty_kref_put(tty);
2765 }
2766 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2767 
2768 void
2769 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2770 		          const struct ktermios *old)
2771 {
2772 	struct uart_8250_port *up = up_to_u8250p(port);
2773 	unsigned char cval;
2774 	unsigned long flags;
2775 	unsigned int baud, quot, frac = 0;
2776 
2777 	if (up->capabilities & UART_CAP_MINI) {
2778 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2779 		if ((termios->c_cflag & CSIZE) == CS5 ||
2780 		    (termios->c_cflag & CSIZE) == CS6)
2781 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2782 	}
2783 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2784 
2785 	baud = serial8250_get_baud_rate(port, termios, old);
2786 	quot = serial8250_get_divisor(port, baud, &frac);
2787 
2788 	/*
2789 	 * Ok, we're now changing the port state.  Do it with
2790 	 * interrupts disabled.
2791 	 *
2792 	 * Synchronize UART_IER access against the console.
2793 	 */
2794 	serial8250_rpm_get(up);
2795 	spin_lock_irqsave(&port->lock, flags);
2796 
2797 	up->lcr = cval;					/* Save computed LCR */
2798 
2799 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2800 		if (baud < 2400 && !up->dma) {
2801 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2802 			up->fcr |= UART_FCR_TRIGGER_1;
2803 		}
2804 	}
2805 
2806 	/*
2807 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2808 	 * deasserted when the receive FIFO contains more characters than
2809 	 * the trigger, or the MCR RTS bit is cleared.
2810 	 */
2811 	if (up->capabilities & UART_CAP_AFE) {
2812 		up->mcr &= ~UART_MCR_AFE;
2813 		if (termios->c_cflag & CRTSCTS)
2814 			up->mcr |= UART_MCR_AFE;
2815 	}
2816 
2817 	/*
2818 	 * Update the per-port timeout.
2819 	 */
2820 	uart_update_timeout(port, termios->c_cflag, baud);
2821 
2822 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2823 	if (termios->c_iflag & INPCK)
2824 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2825 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2826 		port->read_status_mask |= UART_LSR_BI;
2827 
2828 	/*
2829 	 * Characters to ignore
2830 	 */
2831 	port->ignore_status_mask = 0;
2832 	if (termios->c_iflag & IGNPAR)
2833 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2834 	if (termios->c_iflag & IGNBRK) {
2835 		port->ignore_status_mask |= UART_LSR_BI;
2836 		/*
2837 		 * If we're ignoring parity and break indicators,
2838 		 * ignore overruns too (for real raw support).
2839 		 */
2840 		if (termios->c_iflag & IGNPAR)
2841 			port->ignore_status_mask |= UART_LSR_OE;
2842 	}
2843 
2844 	/*
2845 	 * ignore all characters if CREAD is not set
2846 	 */
2847 	if ((termios->c_cflag & CREAD) == 0)
2848 		port->ignore_status_mask |= UART_LSR_DR;
2849 
2850 	/*
2851 	 * CTS flow control flag and modem status interrupts
2852 	 */
2853 	up->ier &= ~UART_IER_MSI;
2854 	if (!(up->bugs & UART_BUG_NOMSR) &&
2855 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2856 		up->ier |= UART_IER_MSI;
2857 	if (up->capabilities & UART_CAP_UUE)
2858 		up->ier |= UART_IER_UUE;
2859 	if (up->capabilities & UART_CAP_RTOIE)
2860 		up->ier |= UART_IER_RTOIE;
2861 
2862 	serial_port_out(port, UART_IER, up->ier);
2863 
2864 	if (up->capabilities & UART_CAP_EFR) {
2865 		unsigned char efr = 0;
2866 		/*
2867 		 * TI16C752/Startech hardware flow control.  FIXME:
2868 		 * - TI16C752 requires control thresholds to be set.
2869 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2870 		 */
2871 		if (termios->c_cflag & CRTSCTS)
2872 			efr |= UART_EFR_CTS;
2873 
2874 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2875 		if (port->flags & UPF_EXAR_EFR)
2876 			serial_port_out(port, UART_XR_EFR, efr);
2877 		else
2878 			serial_port_out(port, UART_EFR, efr);
2879 	}
2880 
2881 	serial8250_set_divisor(port, baud, quot, frac);
2882 
2883 	/*
2884 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2885 	 * is written without DLAB set, this mode will be disabled.
2886 	 */
2887 	if (port->type == PORT_16750)
2888 		serial_port_out(port, UART_FCR, up->fcr);
2889 
2890 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2891 	if (port->type != PORT_16750) {
2892 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2893 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2894 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2895 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2896 	}
2897 	serial8250_set_mctrl(port, port->mctrl);
2898 	spin_unlock_irqrestore(&port->lock, flags);
2899 	serial8250_rpm_put(up);
2900 
2901 	/* Don't rewrite B0 */
2902 	if (tty_termios_baud_rate(termios))
2903 		tty_termios_encode_baud_rate(termios, baud, baud);
2904 }
2905 EXPORT_SYMBOL(serial8250_do_set_termios);
2906 
2907 static void
2908 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2909 		       const struct ktermios *old)
2910 {
2911 	if (port->set_termios)
2912 		port->set_termios(port, termios, old);
2913 	else
2914 		serial8250_do_set_termios(port, termios, old);
2915 }
2916 
2917 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2918 {
2919 	if (termios->c_line == N_PPS) {
2920 		port->flags |= UPF_HARDPPS_CD;
2921 		spin_lock_irq(&port->lock);
2922 		serial8250_enable_ms(port);
2923 		spin_unlock_irq(&port->lock);
2924 	} else {
2925 		port->flags &= ~UPF_HARDPPS_CD;
2926 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2927 			spin_lock_irq(&port->lock);
2928 			serial8250_disable_ms(port);
2929 			spin_unlock_irq(&port->lock);
2930 		}
2931 	}
2932 }
2933 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2934 
2935 static void
2936 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2937 {
2938 	if (port->set_ldisc)
2939 		port->set_ldisc(port, termios);
2940 	else
2941 		serial8250_do_set_ldisc(port, termios);
2942 }
2943 
2944 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2945 		      unsigned int oldstate)
2946 {
2947 	struct uart_8250_port *p = up_to_u8250p(port);
2948 
2949 	serial8250_set_sleep(p, state != 0);
2950 }
2951 EXPORT_SYMBOL(serial8250_do_pm);
2952 
2953 static void
2954 serial8250_pm(struct uart_port *port, unsigned int state,
2955 	      unsigned int oldstate)
2956 {
2957 	if (port->pm)
2958 		port->pm(port, state, oldstate);
2959 	else
2960 		serial8250_do_pm(port, state, oldstate);
2961 }
2962 
2963 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2964 {
2965 	if (pt->port.mapsize)
2966 		return pt->port.mapsize;
2967 	if (is_omap1_8250(pt))
2968 		return 0x16 << pt->port.regshift;
2969 
2970 	return 8 << pt->port.regshift;
2971 }
2972 
2973 /*
2974  * Resource handling.
2975  */
2976 static int serial8250_request_std_resource(struct uart_8250_port *up)
2977 {
2978 	unsigned int size = serial8250_port_size(up);
2979 	struct uart_port *port = &up->port;
2980 	int ret = 0;
2981 
2982 	switch (port->iotype) {
2983 	case UPIO_AU:
2984 	case UPIO_TSI:
2985 	case UPIO_MEM32:
2986 	case UPIO_MEM32BE:
2987 	case UPIO_MEM16:
2988 	case UPIO_MEM:
2989 		if (!port->mapbase) {
2990 			ret = -EINVAL;
2991 			break;
2992 		}
2993 
2994 		if (!request_mem_region(port->mapbase, size, "serial")) {
2995 			ret = -EBUSY;
2996 			break;
2997 		}
2998 
2999 		if (port->flags & UPF_IOREMAP) {
3000 			port->membase = ioremap(port->mapbase, size);
3001 			if (!port->membase) {
3002 				release_mem_region(port->mapbase, size);
3003 				ret = -ENOMEM;
3004 			}
3005 		}
3006 		break;
3007 
3008 	case UPIO_HUB6:
3009 	case UPIO_PORT:
3010 		if (!request_region(port->iobase, size, "serial"))
3011 			ret = -EBUSY;
3012 		break;
3013 	}
3014 	return ret;
3015 }
3016 
3017 static void serial8250_release_std_resource(struct uart_8250_port *up)
3018 {
3019 	unsigned int size = serial8250_port_size(up);
3020 	struct uart_port *port = &up->port;
3021 
3022 	switch (port->iotype) {
3023 	case UPIO_AU:
3024 	case UPIO_TSI:
3025 	case UPIO_MEM32:
3026 	case UPIO_MEM32BE:
3027 	case UPIO_MEM16:
3028 	case UPIO_MEM:
3029 		if (!port->mapbase)
3030 			break;
3031 
3032 		if (port->flags & UPF_IOREMAP) {
3033 			iounmap(port->membase);
3034 			port->membase = NULL;
3035 		}
3036 
3037 		release_mem_region(port->mapbase, size);
3038 		break;
3039 
3040 	case UPIO_HUB6:
3041 	case UPIO_PORT:
3042 		release_region(port->iobase, size);
3043 		break;
3044 	}
3045 }
3046 
3047 static void serial8250_release_port(struct uart_port *port)
3048 {
3049 	struct uart_8250_port *up = up_to_u8250p(port);
3050 
3051 	serial8250_release_std_resource(up);
3052 }
3053 
3054 static int serial8250_request_port(struct uart_port *port)
3055 {
3056 	struct uart_8250_port *up = up_to_u8250p(port);
3057 
3058 	return serial8250_request_std_resource(up);
3059 }
3060 
3061 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3062 {
3063 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3064 	unsigned char bytes;
3065 
3066 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3067 
3068 	return bytes ? bytes : -EOPNOTSUPP;
3069 }
3070 
3071 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3072 {
3073 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3074 	int i;
3075 
3076 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3077 		return -EOPNOTSUPP;
3078 
3079 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3080 		if (bytes < conf_type->rxtrig_bytes[i])
3081 			/* Use the nearest lower value */
3082 			return (--i) << UART_FCR_R_TRIG_SHIFT;
3083 	}
3084 
3085 	return UART_FCR_R_TRIG_11;
3086 }
3087 
3088 static int do_get_rxtrig(struct tty_port *port)
3089 {
3090 	struct uart_state *state = container_of(port, struct uart_state, port);
3091 	struct uart_port *uport = state->uart_port;
3092 	struct uart_8250_port *up = up_to_u8250p(uport);
3093 
3094 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3095 		return -EINVAL;
3096 
3097 	return fcr_get_rxtrig_bytes(up);
3098 }
3099 
3100 static int do_serial8250_get_rxtrig(struct tty_port *port)
3101 {
3102 	int rxtrig_bytes;
3103 
3104 	mutex_lock(&port->mutex);
3105 	rxtrig_bytes = do_get_rxtrig(port);
3106 	mutex_unlock(&port->mutex);
3107 
3108 	return rxtrig_bytes;
3109 }
3110 
3111 static ssize_t rx_trig_bytes_show(struct device *dev,
3112 	struct device_attribute *attr, char *buf)
3113 {
3114 	struct tty_port *port = dev_get_drvdata(dev);
3115 	int rxtrig_bytes;
3116 
3117 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
3118 	if (rxtrig_bytes < 0)
3119 		return rxtrig_bytes;
3120 
3121 	return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3122 }
3123 
3124 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3125 {
3126 	struct uart_state *state = container_of(port, struct uart_state, port);
3127 	struct uart_port *uport = state->uart_port;
3128 	struct uart_8250_port *up = up_to_u8250p(uport);
3129 	int rxtrig;
3130 
3131 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3132 		return -EINVAL;
3133 
3134 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3135 	if (rxtrig < 0)
3136 		return rxtrig;
3137 
3138 	serial8250_clear_fifos(up);
3139 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3140 	up->fcr |= (unsigned char)rxtrig;
3141 	serial_out(up, UART_FCR, up->fcr);
3142 	return 0;
3143 }
3144 
3145 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3146 {
3147 	int ret;
3148 
3149 	mutex_lock(&port->mutex);
3150 	ret = do_set_rxtrig(port, bytes);
3151 	mutex_unlock(&port->mutex);
3152 
3153 	return ret;
3154 }
3155 
3156 static ssize_t rx_trig_bytes_store(struct device *dev,
3157 	struct device_attribute *attr, const char *buf, size_t count)
3158 {
3159 	struct tty_port *port = dev_get_drvdata(dev);
3160 	unsigned char bytes;
3161 	int ret;
3162 
3163 	if (!count)
3164 		return -EINVAL;
3165 
3166 	ret = kstrtou8(buf, 10, &bytes);
3167 	if (ret < 0)
3168 		return ret;
3169 
3170 	ret = do_serial8250_set_rxtrig(port, bytes);
3171 	if (ret < 0)
3172 		return ret;
3173 
3174 	return count;
3175 }
3176 
3177 static DEVICE_ATTR_RW(rx_trig_bytes);
3178 
3179 static struct attribute *serial8250_dev_attrs[] = {
3180 	&dev_attr_rx_trig_bytes.attr,
3181 	NULL
3182 };
3183 
3184 static struct attribute_group serial8250_dev_attr_group = {
3185 	.attrs = serial8250_dev_attrs,
3186 };
3187 
3188 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3189 {
3190 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3191 
3192 	if (conf_type->rxtrig_bytes[0])
3193 		up->port.attr_group = &serial8250_dev_attr_group;
3194 }
3195 
3196 static void serial8250_config_port(struct uart_port *port, int flags)
3197 {
3198 	struct uart_8250_port *up = up_to_u8250p(port);
3199 	int ret;
3200 
3201 	/*
3202 	 * Find the region that we can probe for.  This in turn
3203 	 * tells us whether we can probe for the type of port.
3204 	 */
3205 	ret = serial8250_request_std_resource(up);
3206 	if (ret < 0)
3207 		return;
3208 
3209 	if (port->iotype != up->cur_iotype)
3210 		set_io_from_upio(port);
3211 
3212 	if (flags & UART_CONFIG_TYPE)
3213 		autoconfig(up);
3214 
3215 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3216 	if (port->type == PORT_TEGRA)
3217 		up->bugs |= UART_BUG_NOMSR;
3218 
3219 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3220 		autoconfig_irq(up);
3221 
3222 	if (port->type == PORT_UNKNOWN)
3223 		serial8250_release_std_resource(up);
3224 
3225 	register_dev_spec_attr_grp(up);
3226 	up->fcr = uart_config[up->port.type].fcr;
3227 }
3228 
3229 static int
3230 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3231 {
3232 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3233 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3234 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3235 	    ser->type == PORT_STARTECH)
3236 		return -EINVAL;
3237 	return 0;
3238 }
3239 
3240 static const char *serial8250_type(struct uart_port *port)
3241 {
3242 	int type = port->type;
3243 
3244 	if (type >= ARRAY_SIZE(uart_config))
3245 		type = 0;
3246 	return uart_config[type].name;
3247 }
3248 
3249 static const struct uart_ops serial8250_pops = {
3250 	.tx_empty	= serial8250_tx_empty,
3251 	.set_mctrl	= serial8250_set_mctrl,
3252 	.get_mctrl	= serial8250_get_mctrl,
3253 	.stop_tx	= serial8250_stop_tx,
3254 	.start_tx	= serial8250_start_tx,
3255 	.throttle	= serial8250_throttle,
3256 	.unthrottle	= serial8250_unthrottle,
3257 	.stop_rx	= serial8250_stop_rx,
3258 	.enable_ms	= serial8250_enable_ms,
3259 	.break_ctl	= serial8250_break_ctl,
3260 	.startup	= serial8250_startup,
3261 	.shutdown	= serial8250_shutdown,
3262 	.set_termios	= serial8250_set_termios,
3263 	.set_ldisc	= serial8250_set_ldisc,
3264 	.pm		= serial8250_pm,
3265 	.type		= serial8250_type,
3266 	.release_port	= serial8250_release_port,
3267 	.request_port	= serial8250_request_port,
3268 	.config_port	= serial8250_config_port,
3269 	.verify_port	= serial8250_verify_port,
3270 #ifdef CONFIG_CONSOLE_POLL
3271 	.poll_get_char = serial8250_get_poll_char,
3272 	.poll_put_char = serial8250_put_poll_char,
3273 #endif
3274 };
3275 
3276 void serial8250_init_port(struct uart_8250_port *up)
3277 {
3278 	struct uart_port *port = &up->port;
3279 
3280 	spin_lock_init(&port->lock);
3281 	port->ctrl_id = 0;
3282 	port->pm = NULL;
3283 	port->ops = &serial8250_pops;
3284 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3285 
3286 	up->cur_iotype = 0xFF;
3287 }
3288 EXPORT_SYMBOL_GPL(serial8250_init_port);
3289 
3290 void serial8250_set_defaults(struct uart_8250_port *up)
3291 {
3292 	struct uart_port *port = &up->port;
3293 
3294 	if (up->port.flags & UPF_FIXED_TYPE) {
3295 		unsigned int type = up->port.type;
3296 
3297 		if (!up->port.fifosize)
3298 			up->port.fifosize = uart_config[type].fifo_size;
3299 		if (!up->tx_loadsz)
3300 			up->tx_loadsz = uart_config[type].tx_loadsz;
3301 		if (!up->capabilities)
3302 			up->capabilities = uart_config[type].flags;
3303 	}
3304 
3305 	set_io_from_upio(port);
3306 
3307 	/* default dma handlers */
3308 	if (up->dma) {
3309 		if (!up->dma->tx_dma)
3310 			up->dma->tx_dma = serial8250_tx_dma;
3311 		if (!up->dma->rx_dma)
3312 			up->dma->rx_dma = serial8250_rx_dma;
3313 	}
3314 }
3315 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3316 
3317 #ifdef CONFIG_SERIAL_8250_CONSOLE
3318 
3319 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3320 {
3321 	struct uart_8250_port *up = up_to_u8250p(port);
3322 
3323 	wait_for_xmitr(up, UART_LSR_THRE);
3324 	serial_port_out(port, UART_TX, ch);
3325 }
3326 
3327 /*
3328  *	Restore serial console when h/w power-off detected
3329  */
3330 static void serial8250_console_restore(struct uart_8250_port *up)
3331 {
3332 	struct uart_port *port = &up->port;
3333 	struct ktermios termios;
3334 	unsigned int baud, quot, frac = 0;
3335 
3336 	termios.c_cflag = port->cons->cflag;
3337 	termios.c_ispeed = port->cons->ispeed;
3338 	termios.c_ospeed = port->cons->ospeed;
3339 	if (port->state->port.tty && termios.c_cflag == 0) {
3340 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3341 		termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3342 		termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3343 	}
3344 
3345 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3346 	quot = serial8250_get_divisor(port, baud, &frac);
3347 
3348 	serial8250_set_divisor(port, baud, quot, frac);
3349 	serial_port_out(port, UART_LCR, up->lcr);
3350 	serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3351 }
3352 
3353 /*
3354  * Print a string to the serial port using the device FIFO
3355  *
3356  * It sends fifosize bytes and then waits for the fifo
3357  * to get empty.
3358  */
3359 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3360 					  const char *s, unsigned int count)
3361 {
3362 	int i;
3363 	const char *end = s + count;
3364 	unsigned int fifosize = up->tx_loadsz;
3365 	bool cr_sent = false;
3366 
3367 	while (s != end) {
3368 		wait_for_lsr(up, UART_LSR_THRE);
3369 
3370 		for (i = 0; i < fifosize && s != end; ++i) {
3371 			if (*s == '\n' && !cr_sent) {
3372 				serial_out(up, UART_TX, '\r');
3373 				cr_sent = true;
3374 			} else {
3375 				serial_out(up, UART_TX, *s++);
3376 				cr_sent = false;
3377 			}
3378 		}
3379 	}
3380 }
3381 
3382 /*
3383  *	Print a string to the serial port trying not to disturb
3384  *	any possible real use of the port...
3385  *
3386  *	The console_lock must be held when we get here.
3387  *
3388  *	Doing runtime PM is really a bad idea for the kernel console.
3389  *	Thus, we assume the function is called when device is powered up.
3390  */
3391 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3392 			      unsigned int count)
3393 {
3394 	struct uart_8250_em485 *em485 = up->em485;
3395 	struct uart_port *port = &up->port;
3396 	unsigned long flags;
3397 	unsigned int ier, use_fifo;
3398 	int locked = 1;
3399 
3400 	touch_nmi_watchdog();
3401 
3402 	if (oops_in_progress)
3403 		locked = spin_trylock_irqsave(&port->lock, flags);
3404 	else
3405 		spin_lock_irqsave(&port->lock, flags);
3406 
3407 	/*
3408 	 *	First save the IER then disable the interrupts
3409 	 */
3410 	ier = serial_port_in(port, UART_IER);
3411 	serial8250_clear_IER(up);
3412 
3413 	/* check scratch reg to see if port powered off during system sleep */
3414 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3415 		serial8250_console_restore(up);
3416 		up->canary = 0;
3417 	}
3418 
3419 	if (em485) {
3420 		if (em485->tx_stopped)
3421 			up->rs485_start_tx(up);
3422 		mdelay(port->rs485.delay_rts_before_send);
3423 	}
3424 
3425 	use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3426 		/*
3427 		 * BCM283x requires to check the fifo
3428 		 * after each byte.
3429 		 */
3430 		!(up->capabilities & UART_CAP_MINI) &&
3431 		/*
3432 		 * tx_loadsz contains the transmit fifo size
3433 		 */
3434 		up->tx_loadsz > 1 &&
3435 		(up->fcr & UART_FCR_ENABLE_FIFO) &&
3436 		port->state &&
3437 		test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3438 		/*
3439 		 * After we put a data in the fifo, the controller will send
3440 		 * it regardless of the CTS state. Therefore, only use fifo
3441 		 * if we don't use control flow.
3442 		 */
3443 		!(up->port.flags & UPF_CONS_FLOW);
3444 
3445 	if (likely(use_fifo))
3446 		serial8250_console_fifo_write(up, s, count);
3447 	else
3448 		uart_console_write(port, s, count, serial8250_console_putchar);
3449 
3450 	/*
3451 	 *	Finally, wait for transmitter to become empty
3452 	 *	and restore the IER
3453 	 */
3454 	wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3455 
3456 	if (em485) {
3457 		mdelay(port->rs485.delay_rts_after_send);
3458 		if (em485->tx_stopped)
3459 			up->rs485_stop_tx(up);
3460 	}
3461 
3462 	serial_port_out(port, UART_IER, ier);
3463 
3464 	/*
3465 	 *	The receive handling will happen properly because the
3466 	 *	receive ready bit will still be set; it is not cleared
3467 	 *	on read.  However, modem control will not, we must
3468 	 *	call it if we have saved something in the saved flags
3469 	 *	while processing with interrupts off.
3470 	 */
3471 	if (up->msr_saved_flags)
3472 		serial8250_modem_status(up);
3473 
3474 	if (locked)
3475 		spin_unlock_irqrestore(&port->lock, flags);
3476 }
3477 
3478 static unsigned int probe_baud(struct uart_port *port)
3479 {
3480 	unsigned char lcr, dll, dlm;
3481 	unsigned int quot;
3482 
3483 	lcr = serial_port_in(port, UART_LCR);
3484 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3485 	dll = serial_port_in(port, UART_DLL);
3486 	dlm = serial_port_in(port, UART_DLM);
3487 	serial_port_out(port, UART_LCR, lcr);
3488 
3489 	quot = (dlm << 8) | dll;
3490 	return (port->uartclk / 16) / quot;
3491 }
3492 
3493 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3494 {
3495 	int baud = 9600;
3496 	int bits = 8;
3497 	int parity = 'n';
3498 	int flow = 'n';
3499 	int ret;
3500 
3501 	if (!port->iobase && !port->membase)
3502 		return -ENODEV;
3503 
3504 	if (options)
3505 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3506 	else if (probe)
3507 		baud = probe_baud(port);
3508 
3509 	ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3510 	if (ret)
3511 		return ret;
3512 
3513 	if (port->dev)
3514 		pm_runtime_get_sync(port->dev);
3515 
3516 	return 0;
3517 }
3518 
3519 int serial8250_console_exit(struct uart_port *port)
3520 {
3521 	if (port->dev)
3522 		pm_runtime_put_sync(port->dev);
3523 
3524 	return 0;
3525 }
3526 
3527 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3528 
3529 MODULE_LICENSE("GPL");
3530