1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Base port operations for 8250/16550-type serial ports
4  *
5  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6  *  Split from 8250_core.c, Copyright (C) 2001 Russell King.
7  *
8  * A note about mapbase / membase
9  *
10  *  mapbase is the physical address of the IO port.
11  *  membase is an 'ioremapped' cookie.
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
34 
35 #include <asm/io.h>
36 #include <asm/irq.h>
37 
38 #include "8250.h"
39 
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR          7
42 #define UART_NPCM_TOIE         BIT(7)  /* Timeout Interrupt Enable */
43 
44 /*
45  * Debugging.
46  */
47 #if 0
48 #define DEBUG_AUTOCONF(fmt...)	printk(fmt)
49 #else
50 #define DEBUG_AUTOCONF(fmt...)	do { } while (0)
51 #endif
52 
53 #define BOTH_EMPTY	(UART_LSR_TEMT | UART_LSR_THRE)
54 
55 /*
56  * Here we define the default xmit fifo size used for each type of UART.
57  */
58 static const struct serial8250_config uart_config[] = {
59 	[PORT_UNKNOWN] = {
60 		.name		= "unknown",
61 		.fifo_size	= 1,
62 		.tx_loadsz	= 1,
63 	},
64 	[PORT_8250] = {
65 		.name		= "8250",
66 		.fifo_size	= 1,
67 		.tx_loadsz	= 1,
68 	},
69 	[PORT_16450] = {
70 		.name		= "16450",
71 		.fifo_size	= 1,
72 		.tx_loadsz	= 1,
73 	},
74 	[PORT_16550] = {
75 		.name		= "16550",
76 		.fifo_size	= 1,
77 		.tx_loadsz	= 1,
78 	},
79 	[PORT_16550A] = {
80 		.name		= "16550A",
81 		.fifo_size	= 16,
82 		.tx_loadsz	= 16,
83 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
84 		.rxtrig_bytes	= {1, 4, 8, 14},
85 		.flags		= UART_CAP_FIFO,
86 	},
87 	[PORT_CIRRUS] = {
88 		.name		= "Cirrus",
89 		.fifo_size	= 1,
90 		.tx_loadsz	= 1,
91 	},
92 	[PORT_16650] = {
93 		.name		= "ST16650",
94 		.fifo_size	= 1,
95 		.tx_loadsz	= 1,
96 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
97 	},
98 	[PORT_16650V2] = {
99 		.name		= "ST16650V2",
100 		.fifo_size	= 32,
101 		.tx_loadsz	= 16,
102 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 				  UART_FCR_T_TRIG_00,
104 		.rxtrig_bytes	= {8, 16, 24, 28},
105 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
106 	},
107 	[PORT_16750] = {
108 		.name		= "TI16750",
109 		.fifo_size	= 64,
110 		.tx_loadsz	= 64,
111 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 				  UART_FCR7_64BYTE,
113 		.rxtrig_bytes	= {1, 16, 32, 56},
114 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
115 	},
116 	[PORT_STARTECH] = {
117 		.name		= "Startech",
118 		.fifo_size	= 1,
119 		.tx_loadsz	= 1,
120 	},
121 	[PORT_16C950] = {
122 		.name		= "16C950/954",
123 		.fifo_size	= 128,
124 		.tx_loadsz	= 128,
125 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
126 		.rxtrig_bytes	= {16, 32, 112, 120},
127 		/* UART_CAP_EFR breaks billionon CF bluetooth card. */
128 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
129 	},
130 	[PORT_16654] = {
131 		.name		= "ST16654",
132 		.fifo_size	= 64,
133 		.tx_loadsz	= 32,
134 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
135 				  UART_FCR_T_TRIG_10,
136 		.rxtrig_bytes	= {8, 16, 56, 60},
137 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
138 	},
139 	[PORT_16850] = {
140 		.name		= "XR16850",
141 		.fifo_size	= 128,
142 		.tx_loadsz	= 128,
143 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
144 		.flags		= UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
145 	},
146 	[PORT_RSA] = {
147 		.name		= "RSA",
148 		.fifo_size	= 2048,
149 		.tx_loadsz	= 2048,
150 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
151 		.flags		= UART_CAP_FIFO,
152 	},
153 	[PORT_NS16550A] = {
154 		.name		= "NS16550A",
155 		.fifo_size	= 16,
156 		.tx_loadsz	= 16,
157 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
158 		.flags		= UART_CAP_FIFO | UART_NATSEMI,
159 	},
160 	[PORT_XSCALE] = {
161 		.name		= "XScale",
162 		.fifo_size	= 32,
163 		.tx_loadsz	= 32,
164 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
165 		.flags		= UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
166 	},
167 	[PORT_OCTEON] = {
168 		.name		= "OCTEON",
169 		.fifo_size	= 64,
170 		.tx_loadsz	= 64,
171 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 		.flags		= UART_CAP_FIFO,
173 	},
174 	[PORT_AR7] = {
175 		.name		= "AR7",
176 		.fifo_size	= 16,
177 		.tx_loadsz	= 16,
178 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
179 		.flags		= UART_CAP_FIFO /* | UART_CAP_AFE */,
180 	},
181 	[PORT_U6_16550A] = {
182 		.name		= "U6_16550A",
183 		.fifo_size	= 64,
184 		.tx_loadsz	= 64,
185 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
186 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
187 	},
188 	[PORT_TEGRA] = {
189 		.name		= "Tegra",
190 		.fifo_size	= 32,
191 		.tx_loadsz	= 8,
192 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 				  UART_FCR_T_TRIG_01,
194 		.rxtrig_bytes	= {1, 4, 8, 14},
195 		.flags		= UART_CAP_FIFO | UART_CAP_RTOIE,
196 	},
197 	[PORT_XR17D15X] = {
198 		.name		= "XR17D15X",
199 		.fifo_size	= 64,
200 		.tx_loadsz	= 64,
201 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
202 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
203 				  UART_CAP_SLEEP,
204 	},
205 	[PORT_XR17V35X] = {
206 		.name		= "XR17V35X",
207 		.fifo_size	= 256,
208 		.tx_loadsz	= 256,
209 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
210 				  UART_FCR_T_TRIG_11,
211 		.flags		= UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
212 				  UART_CAP_SLEEP,
213 	},
214 	[PORT_LPC3220] = {
215 		.name		= "LPC3220",
216 		.fifo_size	= 64,
217 		.tx_loadsz	= 32,
218 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
219 				  UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
220 		.flags		= UART_CAP_FIFO,
221 	},
222 	[PORT_BRCM_TRUMANAGE] = {
223 		.name		= "TruManage",
224 		.fifo_size	= 1,
225 		.tx_loadsz	= 1024,
226 		.flags		= UART_CAP_HFIFO,
227 	},
228 	[PORT_8250_CIR] = {
229 		.name		= "CIR port"
230 	},
231 	[PORT_ALTR_16550_F32] = {
232 		.name		= "Altera 16550 FIFO32",
233 		.fifo_size	= 32,
234 		.tx_loadsz	= 32,
235 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
236 		.rxtrig_bytes	= {1, 8, 16, 30},
237 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
238 	},
239 	[PORT_ALTR_16550_F64] = {
240 		.name		= "Altera 16550 FIFO64",
241 		.fifo_size	= 64,
242 		.tx_loadsz	= 64,
243 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 		.rxtrig_bytes	= {1, 16, 32, 62},
245 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
246 	},
247 	[PORT_ALTR_16550_F128] = {
248 		.name		= "Altera 16550 FIFO128",
249 		.fifo_size	= 128,
250 		.tx_loadsz	= 128,
251 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 		.rxtrig_bytes	= {1, 32, 64, 126},
253 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
254 	},
255 	/*
256 	 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
257 	 * workaround of errata A-008006 which states that tx_loadsz should
258 	 * be configured less than Maximum supported fifo bytes.
259 	 */
260 	[PORT_16550A_FSL64] = {
261 		.name		= "16550A_FSL64",
262 		.fifo_size	= 64,
263 		.tx_loadsz	= 63,
264 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 				  UART_FCR7_64BYTE,
266 		.flags		= UART_CAP_FIFO,
267 	},
268 	[PORT_RT2880] = {
269 		.name		= "Palmchip BK-3103",
270 		.fifo_size	= 16,
271 		.tx_loadsz	= 16,
272 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 		.rxtrig_bytes	= {1, 4, 8, 14},
274 		.flags		= UART_CAP_FIFO,
275 	},
276 	[PORT_DA830] = {
277 		.name		= "TI DA8xx/66AK2x",
278 		.fifo_size	= 16,
279 		.tx_loadsz	= 16,
280 		.fcr		= UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
281 				  UART_FCR_R_TRIG_10,
282 		.rxtrig_bytes	= {1, 4, 8, 14},
283 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
284 	},
285 	[PORT_MTK_BTIF] = {
286 		.name		= "MediaTek BTIF",
287 		.fifo_size	= 16,
288 		.tx_loadsz	= 16,
289 		.fcr		= UART_FCR_ENABLE_FIFO |
290 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
291 		.flags		= UART_CAP_FIFO,
292 	},
293 	[PORT_NPCM] = {
294 		.name		= "Nuvoton 16550",
295 		.fifo_size	= 16,
296 		.tx_loadsz	= 16,
297 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
298 				  UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
299 		.rxtrig_bytes	= {1, 4, 8, 14},
300 		.flags		= UART_CAP_FIFO,
301 	},
302 	[PORT_SUNIX] = {
303 		.name		= "Sunix",
304 		.fifo_size	= 128,
305 		.tx_loadsz	= 128,
306 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
307 		.rxtrig_bytes	= {1, 32, 64, 112},
308 		.flags		= UART_CAP_FIFO | UART_CAP_SLEEP,
309 	},
310 	[PORT_ASPEED_VUART] = {
311 		.name		= "ASPEED VUART",
312 		.fifo_size	= 16,
313 		.tx_loadsz	= 16,
314 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
315 		.rxtrig_bytes	= {1, 4, 8, 14},
316 		.flags		= UART_CAP_FIFO,
317 	},
318 };
319 
320 /* Uart divisor latch read */
321 static int default_serial_dl_read(struct uart_8250_port *up)
322 {
323 	/* Assign these in pieces to truncate any bits above 7.  */
324 	unsigned char dll = serial_in(up, UART_DLL);
325 	unsigned char dlm = serial_in(up, UART_DLM);
326 
327 	return dll | dlm << 8;
328 }
329 
330 /* Uart divisor latch write */
331 static void default_serial_dl_write(struct uart_8250_port *up, int value)
332 {
333 	serial_out(up, UART_DLL, value & 0xff);
334 	serial_out(up, UART_DLM, value >> 8 & 0xff);
335 }
336 
337 #ifdef CONFIG_SERIAL_8250_RT288X
338 
339 /* Au1x00/RT288x UART hardware has a weird register layout */
340 static const s8 au_io_in_map[8] = {
341 	 0,	/* UART_RX  */
342 	 2,	/* UART_IER */
343 	 3,	/* UART_IIR */
344 	 5,	/* UART_LCR */
345 	 6,	/* UART_MCR */
346 	 7,	/* UART_LSR */
347 	 8,	/* UART_MSR */
348 	-1,	/* UART_SCR (unmapped) */
349 };
350 
351 static const s8 au_io_out_map[8] = {
352 	 1,	/* UART_TX  */
353 	 2,	/* UART_IER */
354 	 4,	/* UART_FCR */
355 	 5,	/* UART_LCR */
356 	 6,	/* UART_MCR */
357 	-1,	/* UART_LSR (unmapped) */
358 	-1,	/* UART_MSR (unmapped) */
359 	-1,	/* UART_SCR (unmapped) */
360 };
361 
362 unsigned int au_serial_in(struct uart_port *p, int offset)
363 {
364 	if (offset >= ARRAY_SIZE(au_io_in_map))
365 		return UINT_MAX;
366 	offset = au_io_in_map[offset];
367 	if (offset < 0)
368 		return UINT_MAX;
369 	return __raw_readl(p->membase + (offset << p->regshift));
370 }
371 
372 void au_serial_out(struct uart_port *p, int offset, int value)
373 {
374 	if (offset >= ARRAY_SIZE(au_io_out_map))
375 		return;
376 	offset = au_io_out_map[offset];
377 	if (offset < 0)
378 		return;
379 	__raw_writel(value, p->membase + (offset << p->regshift));
380 }
381 
382 /* Au1x00 haven't got a standard divisor latch */
383 static int au_serial_dl_read(struct uart_8250_port *up)
384 {
385 	return __raw_readl(up->port.membase + 0x28);
386 }
387 
388 static void au_serial_dl_write(struct uart_8250_port *up, int value)
389 {
390 	__raw_writel(value, up->port.membase + 0x28);
391 }
392 
393 #endif
394 
395 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
396 {
397 	offset = offset << p->regshift;
398 	outb(p->hub6 - 1 + offset, p->iobase);
399 	return inb(p->iobase + 1);
400 }
401 
402 static void hub6_serial_out(struct uart_port *p, int offset, int value)
403 {
404 	offset = offset << p->regshift;
405 	outb(p->hub6 - 1 + offset, p->iobase);
406 	outb(value, p->iobase + 1);
407 }
408 
409 static unsigned int mem_serial_in(struct uart_port *p, int offset)
410 {
411 	offset = offset << p->regshift;
412 	return readb(p->membase + offset);
413 }
414 
415 static void mem_serial_out(struct uart_port *p, int offset, int value)
416 {
417 	offset = offset << p->regshift;
418 	writeb(value, p->membase + offset);
419 }
420 
421 static void mem16_serial_out(struct uart_port *p, int offset, int value)
422 {
423 	offset = offset << p->regshift;
424 	writew(value, p->membase + offset);
425 }
426 
427 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
428 {
429 	offset = offset << p->regshift;
430 	return readw(p->membase + offset);
431 }
432 
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
434 {
435 	offset = offset << p->regshift;
436 	writel(value, p->membase + offset);
437 }
438 
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
440 {
441 	offset = offset << p->regshift;
442 	return readl(p->membase + offset);
443 }
444 
445 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
446 {
447 	offset = offset << p->regshift;
448 	iowrite32be(value, p->membase + offset);
449 }
450 
451 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
452 {
453 	offset = offset << p->regshift;
454 	return ioread32be(p->membase + offset);
455 }
456 
457 static unsigned int io_serial_in(struct uart_port *p, int offset)
458 {
459 	offset = offset << p->regshift;
460 	return inb(p->iobase + offset);
461 }
462 
463 static void io_serial_out(struct uart_port *p, int offset, int value)
464 {
465 	offset = offset << p->regshift;
466 	outb(value, p->iobase + offset);
467 }
468 
469 static int serial8250_default_handle_irq(struct uart_port *port);
470 
471 static void set_io_from_upio(struct uart_port *p)
472 {
473 	struct uart_8250_port *up = up_to_u8250p(p);
474 
475 	up->dl_read = default_serial_dl_read;
476 	up->dl_write = default_serial_dl_write;
477 
478 	switch (p->iotype) {
479 	case UPIO_HUB6:
480 		p->serial_in = hub6_serial_in;
481 		p->serial_out = hub6_serial_out;
482 		break;
483 
484 	case UPIO_MEM:
485 		p->serial_in = mem_serial_in;
486 		p->serial_out = mem_serial_out;
487 		break;
488 
489 	case UPIO_MEM16:
490 		p->serial_in = mem16_serial_in;
491 		p->serial_out = mem16_serial_out;
492 		break;
493 
494 	case UPIO_MEM32:
495 		p->serial_in = mem32_serial_in;
496 		p->serial_out = mem32_serial_out;
497 		break;
498 
499 	case UPIO_MEM32BE:
500 		p->serial_in = mem32be_serial_in;
501 		p->serial_out = mem32be_serial_out;
502 		break;
503 
504 #ifdef CONFIG_SERIAL_8250_RT288X
505 	case UPIO_AU:
506 		p->serial_in = au_serial_in;
507 		p->serial_out = au_serial_out;
508 		up->dl_read = au_serial_dl_read;
509 		up->dl_write = au_serial_dl_write;
510 		break;
511 #endif
512 
513 	default:
514 		p->serial_in = io_serial_in;
515 		p->serial_out = io_serial_out;
516 		break;
517 	}
518 	/* Remember loaded iotype */
519 	up->cur_iotype = p->iotype;
520 	p->handle_irq = serial8250_default_handle_irq;
521 }
522 
523 static void
524 serial_port_out_sync(struct uart_port *p, int offset, int value)
525 {
526 	switch (p->iotype) {
527 	case UPIO_MEM:
528 	case UPIO_MEM16:
529 	case UPIO_MEM32:
530 	case UPIO_MEM32BE:
531 	case UPIO_AU:
532 		p->serial_out(p, offset, value);
533 		p->serial_in(p, UART_LCR);	/* safe, no side-effects */
534 		break;
535 	default:
536 		p->serial_out(p, offset, value);
537 	}
538 }
539 
540 /*
541  * For the 16C950
542  */
543 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
544 {
545 	serial_out(up, UART_SCR, offset);
546 	serial_out(up, UART_ICR, value);
547 }
548 
549 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
550 {
551 	unsigned int value;
552 
553 	serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
554 	serial_out(up, UART_SCR, offset);
555 	value = serial_in(up, UART_ICR);
556 	serial_icr_write(up, UART_ACR, up->acr);
557 
558 	return value;
559 }
560 
561 /*
562  * FIFO support.
563  */
564 static void serial8250_clear_fifos(struct uart_8250_port *p)
565 {
566 	if (p->capabilities & UART_CAP_FIFO) {
567 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
568 		serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
569 			       UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
570 		serial_out(p, UART_FCR, 0);
571 	}
572 }
573 
574 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
575 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
576 
577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
578 {
579 	serial8250_clear_fifos(p);
580 	serial_out(p, UART_FCR, p->fcr);
581 }
582 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
583 
584 void serial8250_rpm_get(struct uart_8250_port *p)
585 {
586 	if (!(p->capabilities & UART_CAP_RPM))
587 		return;
588 	pm_runtime_get_sync(p->port.dev);
589 }
590 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
591 
592 void serial8250_rpm_put(struct uart_8250_port *p)
593 {
594 	if (!(p->capabilities & UART_CAP_RPM))
595 		return;
596 	pm_runtime_mark_last_busy(p->port.dev);
597 	pm_runtime_put_autosuspend(p->port.dev);
598 }
599 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
600 
601 /**
602  *	serial8250_em485_init() - put uart_8250_port into rs485 emulating
603  *	@p:	uart_8250_port port instance
604  *
605  *	The function is used to start rs485 software emulating on the
606  *	&struct uart_8250_port* @p. Namely, RTS is switched before/after
607  *	transmission. The function is idempotent, so it is safe to call it
608  *	multiple times.
609  *
610  *	The caller MUST enable interrupt on empty shift register before
611  *	calling serial8250_em485_init(). This interrupt is not a part of
612  *	8250 standard, but implementation defined.
613  *
614  *	The function is supposed to be called from .rs485_config callback
615  *	or from any other callback protected with p->port.lock spinlock.
616  *
617  *	See also serial8250_em485_destroy()
618  *
619  *	Return 0 - success, -errno - otherwise
620  */
621 static int serial8250_em485_init(struct uart_8250_port *p)
622 {
623 	if (p->em485)
624 		return 0;
625 
626 	p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
627 	if (!p->em485)
628 		return -ENOMEM;
629 
630 	hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
631 		     HRTIMER_MODE_REL);
632 	hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
633 		     HRTIMER_MODE_REL);
634 	p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
635 	p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
636 	p->em485->port = p;
637 	p->em485->active_timer = NULL;
638 	p->em485->tx_stopped = true;
639 
640 	p->rs485_stop_tx(p);
641 
642 	return 0;
643 }
644 
645 /**
646  *	serial8250_em485_destroy() - put uart_8250_port into normal state
647  *	@p:	uart_8250_port port instance
648  *
649  *	The function is used to stop rs485 software emulating on the
650  *	&struct uart_8250_port* @p. The function is idempotent, so it is safe to
651  *	call it multiple times.
652  *
653  *	The function is supposed to be called from .rs485_config callback
654  *	or from any other callback protected with p->port.lock spinlock.
655  *
656  *	See also serial8250_em485_init()
657  */
658 void serial8250_em485_destroy(struct uart_8250_port *p)
659 {
660 	if (!p->em485)
661 		return;
662 
663 	hrtimer_cancel(&p->em485->start_tx_timer);
664 	hrtimer_cancel(&p->em485->stop_tx_timer);
665 
666 	kfree(p->em485);
667 	p->em485 = NULL;
668 }
669 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
670 
671 /**
672  * serial8250_em485_config() - generic ->rs485_config() callback
673  * @port: uart port
674  * @rs485: rs485 settings
675  *
676  * Generic callback usable by 8250 uart drivers to activate rs485 settings
677  * if the uart is incapable of driving RTS as a Transmit Enable signal in
678  * hardware, relying on software emulation instead.
679  */
680 int serial8250_em485_config(struct uart_port *port, struct serial_rs485 *rs485)
681 {
682 	struct uart_8250_port *up = up_to_u8250p(port);
683 
684 	/* pick sane settings if the user hasn't */
685 	if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
686 	    !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
687 		rs485->flags |= SER_RS485_RTS_ON_SEND;
688 		rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
689 	}
690 
691 	/* clamp the delays to [0, 100ms] */
692 	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
693 	rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
694 
695 	memset(rs485->padding, 0, sizeof(rs485->padding));
696 	port->rs485 = *rs485;
697 
698 	gpiod_set_value(port->rs485_term_gpio,
699 			rs485->flags & SER_RS485_TERMINATE_BUS);
700 
701 	/*
702 	 * Both serial8250_em485_init() and serial8250_em485_destroy()
703 	 * are idempotent.
704 	 */
705 	if (rs485->flags & SER_RS485_ENABLED) {
706 		int ret = serial8250_em485_init(up);
707 
708 		if (ret) {
709 			rs485->flags &= ~SER_RS485_ENABLED;
710 			port->rs485.flags &= ~SER_RS485_ENABLED;
711 		}
712 		return ret;
713 	}
714 
715 	serial8250_em485_destroy(up);
716 	return 0;
717 }
718 EXPORT_SYMBOL_GPL(serial8250_em485_config);
719 
720 /*
721  * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
722  * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
723  * empty and the HW can idle again.
724  */
725 void serial8250_rpm_get_tx(struct uart_8250_port *p)
726 {
727 	unsigned char rpm_active;
728 
729 	if (!(p->capabilities & UART_CAP_RPM))
730 		return;
731 
732 	rpm_active = xchg(&p->rpm_tx_active, 1);
733 	if (rpm_active)
734 		return;
735 	pm_runtime_get_sync(p->port.dev);
736 }
737 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
738 
739 void serial8250_rpm_put_tx(struct uart_8250_port *p)
740 {
741 	unsigned char rpm_active;
742 
743 	if (!(p->capabilities & UART_CAP_RPM))
744 		return;
745 
746 	rpm_active = xchg(&p->rpm_tx_active, 0);
747 	if (!rpm_active)
748 		return;
749 	pm_runtime_mark_last_busy(p->port.dev);
750 	pm_runtime_put_autosuspend(p->port.dev);
751 }
752 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
753 
754 /*
755  * IER sleep support.  UARTs which have EFRs need the "extended
756  * capability" bit enabled.  Note that on XR16C850s, we need to
757  * reset LCR to write to IER.
758  */
759 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
760 {
761 	unsigned char lcr = 0, efr = 0;
762 
763 	serial8250_rpm_get(p);
764 
765 	if (p->capabilities & UART_CAP_SLEEP) {
766 		if (p->capabilities & UART_CAP_EFR) {
767 			lcr = serial_in(p, UART_LCR);
768 			efr = serial_in(p, UART_EFR);
769 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
770 			serial_out(p, UART_EFR, UART_EFR_ECB);
771 			serial_out(p, UART_LCR, 0);
772 		}
773 		serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
774 		if (p->capabilities & UART_CAP_EFR) {
775 			serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
776 			serial_out(p, UART_EFR, efr);
777 			serial_out(p, UART_LCR, lcr);
778 		}
779 	}
780 
781 	serial8250_rpm_put(p);
782 }
783 
784 #ifdef CONFIG_SERIAL_8250_RSA
785 /*
786  * Attempts to turn on the RSA FIFO.  Returns zero on failure.
787  * We set the port uart clock rate if we succeed.
788  */
789 static int __enable_rsa(struct uart_8250_port *up)
790 {
791 	unsigned char mode;
792 	int result;
793 
794 	mode = serial_in(up, UART_RSA_MSR);
795 	result = mode & UART_RSA_MSR_FIFO;
796 
797 	if (!result) {
798 		serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
799 		mode = serial_in(up, UART_RSA_MSR);
800 		result = mode & UART_RSA_MSR_FIFO;
801 	}
802 
803 	if (result)
804 		up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
805 
806 	return result;
807 }
808 
809 static void enable_rsa(struct uart_8250_port *up)
810 {
811 	if (up->port.type == PORT_RSA) {
812 		if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
813 			spin_lock_irq(&up->port.lock);
814 			__enable_rsa(up);
815 			spin_unlock_irq(&up->port.lock);
816 		}
817 		if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
818 			serial_out(up, UART_RSA_FRR, 0);
819 	}
820 }
821 
822 /*
823  * Attempts to turn off the RSA FIFO.  Returns zero on failure.
824  * It is unknown why interrupts were disabled in here.  However,
825  * the caller is expected to preserve this behaviour by grabbing
826  * the spinlock before calling this function.
827  */
828 static void disable_rsa(struct uart_8250_port *up)
829 {
830 	unsigned char mode;
831 	int result;
832 
833 	if (up->port.type == PORT_RSA &&
834 	    up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
835 		spin_lock_irq(&up->port.lock);
836 
837 		mode = serial_in(up, UART_RSA_MSR);
838 		result = !(mode & UART_RSA_MSR_FIFO);
839 
840 		if (!result) {
841 			serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
842 			mode = serial_in(up, UART_RSA_MSR);
843 			result = !(mode & UART_RSA_MSR_FIFO);
844 		}
845 
846 		if (result)
847 			up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
848 		spin_unlock_irq(&up->port.lock);
849 	}
850 }
851 #endif /* CONFIG_SERIAL_8250_RSA */
852 
853 /*
854  * This is a quickie test to see how big the FIFO is.
855  * It doesn't work at all the time, more's the pity.
856  */
857 static int size_fifo(struct uart_8250_port *up)
858 {
859 	unsigned char old_fcr, old_mcr, old_lcr;
860 	unsigned short old_dl;
861 	int count;
862 
863 	old_lcr = serial_in(up, UART_LCR);
864 	serial_out(up, UART_LCR, 0);
865 	old_fcr = serial_in(up, UART_FCR);
866 	old_mcr = serial8250_in_MCR(up);
867 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
868 		    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
869 	serial8250_out_MCR(up, UART_MCR_LOOP);
870 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
871 	old_dl = serial_dl_read(up);
872 	serial_dl_write(up, 0x0001);
873 	serial_out(up, UART_LCR, 0x03);
874 	for (count = 0; count < 256; count++)
875 		serial_out(up, UART_TX, count);
876 	mdelay(20);/* FIXME - schedule_timeout */
877 	for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
878 	     (count < 256); count++)
879 		serial_in(up, UART_RX);
880 	serial_out(up, UART_FCR, old_fcr);
881 	serial8250_out_MCR(up, old_mcr);
882 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
883 	serial_dl_write(up, old_dl);
884 	serial_out(up, UART_LCR, old_lcr);
885 
886 	return count;
887 }
888 
889 /*
890  * Read UART ID using the divisor method - set DLL and DLM to zero
891  * and the revision will be in DLL and device type in DLM.  We
892  * preserve the device state across this.
893  */
894 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
895 {
896 	unsigned char old_lcr;
897 	unsigned int id, old_dl;
898 
899 	old_lcr = serial_in(p, UART_LCR);
900 	serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
901 	old_dl = serial_dl_read(p);
902 	serial_dl_write(p, 0);
903 	id = serial_dl_read(p);
904 	serial_dl_write(p, old_dl);
905 
906 	serial_out(p, UART_LCR, old_lcr);
907 
908 	return id;
909 }
910 
911 /*
912  * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
913  * When this function is called we know it is at least a StarTech
914  * 16650 V2, but it might be one of several StarTech UARTs, or one of
915  * its clones.  (We treat the broken original StarTech 16650 V1 as a
916  * 16550, and why not?  Startech doesn't seem to even acknowledge its
917  * existence.)
918  *
919  * What evil have men's minds wrought...
920  */
921 static void autoconfig_has_efr(struct uart_8250_port *up)
922 {
923 	unsigned int id1, id2, id3, rev;
924 
925 	/*
926 	 * Everything with an EFR has SLEEP
927 	 */
928 	up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
929 
930 	/*
931 	 * First we check to see if it's an Oxford Semiconductor UART.
932 	 *
933 	 * If we have to do this here because some non-National
934 	 * Semiconductor clone chips lock up if you try writing to the
935 	 * LSR register (which serial_icr_read does)
936 	 */
937 
938 	/*
939 	 * Check for Oxford Semiconductor 16C950.
940 	 *
941 	 * EFR [4] must be set else this test fails.
942 	 *
943 	 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
944 	 * claims that it's needed for 952 dual UART's (which are not
945 	 * recommended for new designs).
946 	 */
947 	up->acr = 0;
948 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
949 	serial_out(up, UART_EFR, UART_EFR_ECB);
950 	serial_out(up, UART_LCR, 0x00);
951 	id1 = serial_icr_read(up, UART_ID1);
952 	id2 = serial_icr_read(up, UART_ID2);
953 	id3 = serial_icr_read(up, UART_ID3);
954 	rev = serial_icr_read(up, UART_REV);
955 
956 	DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
957 
958 	if (id1 == 0x16 && id2 == 0xC9 &&
959 	    (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
960 		up->port.type = PORT_16C950;
961 
962 		/*
963 		 * Enable work around for the Oxford Semiconductor 952 rev B
964 		 * chip which causes it to seriously miscalculate baud rates
965 		 * when DLL is 0.
966 		 */
967 		if (id3 == 0x52 && rev == 0x01)
968 			up->bugs |= UART_BUG_QUOT;
969 		return;
970 	}
971 
972 	/*
973 	 * We check for a XR16C850 by setting DLL and DLM to 0, and then
974 	 * reading back DLL and DLM.  The chip type depends on the DLM
975 	 * value read back:
976 	 *  0x10 - XR16C850 and the DLL contains the chip revision.
977 	 *  0x12 - XR16C2850.
978 	 *  0x14 - XR16C854.
979 	 */
980 	id1 = autoconfig_read_divisor_id(up);
981 	DEBUG_AUTOCONF("850id=%04x ", id1);
982 
983 	id2 = id1 >> 8;
984 	if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
985 		up->port.type = PORT_16850;
986 		return;
987 	}
988 
989 	/*
990 	 * It wasn't an XR16C850.
991 	 *
992 	 * We distinguish between the '654 and the '650 by counting
993 	 * how many bytes are in the FIFO.  I'm using this for now,
994 	 * since that's the technique that was sent to me in the
995 	 * serial driver update, but I'm not convinced this works.
996 	 * I've had problems doing this in the past.  -TYT
997 	 */
998 	if (size_fifo(up) == 64)
999 		up->port.type = PORT_16654;
1000 	else
1001 		up->port.type = PORT_16650V2;
1002 }
1003 
1004 /*
1005  * We detected a chip without a FIFO.  Only two fall into
1006  * this category - the original 8250 and the 16450.  The
1007  * 16450 has a scratch register (accessible with LCR=0)
1008  */
1009 static void autoconfig_8250(struct uart_8250_port *up)
1010 {
1011 	unsigned char scratch, status1, status2;
1012 
1013 	up->port.type = PORT_8250;
1014 
1015 	scratch = serial_in(up, UART_SCR);
1016 	serial_out(up, UART_SCR, 0xa5);
1017 	status1 = serial_in(up, UART_SCR);
1018 	serial_out(up, UART_SCR, 0x5a);
1019 	status2 = serial_in(up, UART_SCR);
1020 	serial_out(up, UART_SCR, scratch);
1021 
1022 	if (status1 == 0xa5 && status2 == 0x5a)
1023 		up->port.type = PORT_16450;
1024 }
1025 
1026 static int broken_efr(struct uart_8250_port *up)
1027 {
1028 	/*
1029 	 * Exar ST16C2550 "A2" devices incorrectly detect as
1030 	 * having an EFR, and report an ID of 0x0201.  See
1031 	 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1032 	 */
1033 	if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1034 		return 1;
1035 
1036 	return 0;
1037 }
1038 
1039 /*
1040  * We know that the chip has FIFOs.  Does it have an EFR?  The
1041  * EFR is located in the same register position as the IIR and
1042  * we know the top two bits of the IIR are currently set.  The
1043  * EFR should contain zero.  Try to read the EFR.
1044  */
1045 static void autoconfig_16550a(struct uart_8250_port *up)
1046 {
1047 	unsigned char status1, status2;
1048 	unsigned int iersave;
1049 
1050 	up->port.type = PORT_16550A;
1051 	up->capabilities |= UART_CAP_FIFO;
1052 
1053 	if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS))
1054 		return;
1055 
1056 	/*
1057 	 * Check for presence of the EFR when DLAB is set.
1058 	 * Only ST16C650V1 UARTs pass this test.
1059 	 */
1060 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1061 	if (serial_in(up, UART_EFR) == 0) {
1062 		serial_out(up, UART_EFR, 0xA8);
1063 		if (serial_in(up, UART_EFR) != 0) {
1064 			DEBUG_AUTOCONF("EFRv1 ");
1065 			up->port.type = PORT_16650;
1066 			up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1067 		} else {
1068 			serial_out(up, UART_LCR, 0);
1069 			serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1070 				   UART_FCR7_64BYTE);
1071 			status1 = serial_in(up, UART_IIR) >> 5;
1072 			serial_out(up, UART_FCR, 0);
1073 			serial_out(up, UART_LCR, 0);
1074 
1075 			if (status1 == 7)
1076 				up->port.type = PORT_16550A_FSL64;
1077 			else
1078 				DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1079 		}
1080 		serial_out(up, UART_EFR, 0);
1081 		return;
1082 	}
1083 
1084 	/*
1085 	 * Maybe it requires 0xbf to be written to the LCR.
1086 	 * (other ST16C650V2 UARTs, TI16C752A, etc)
1087 	 */
1088 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1089 	if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1090 		DEBUG_AUTOCONF("EFRv2 ");
1091 		autoconfig_has_efr(up);
1092 		return;
1093 	}
1094 
1095 	/*
1096 	 * Check for a National Semiconductor SuperIO chip.
1097 	 * Attempt to switch to bank 2, read the value of the LOOP bit
1098 	 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1099 	 * switch back to bank 2, read it from EXCR1 again and check
1100 	 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1101 	 */
1102 	serial_out(up, UART_LCR, 0);
1103 	status1 = serial8250_in_MCR(up);
1104 	serial_out(up, UART_LCR, 0xE0);
1105 	status2 = serial_in(up, 0x02); /* EXCR1 */
1106 
1107 	if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1108 		serial_out(up, UART_LCR, 0);
1109 		serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1110 		serial_out(up, UART_LCR, 0xE0);
1111 		status2 = serial_in(up, 0x02); /* EXCR1 */
1112 		serial_out(up, UART_LCR, 0);
1113 		serial8250_out_MCR(up, status1);
1114 
1115 		if ((status2 ^ status1) & UART_MCR_LOOP) {
1116 			unsigned short quot;
1117 
1118 			serial_out(up, UART_LCR, 0xE0);
1119 
1120 			quot = serial_dl_read(up);
1121 			quot <<= 3;
1122 
1123 			if (ns16550a_goto_highspeed(up))
1124 				serial_dl_write(up, quot);
1125 
1126 			serial_out(up, UART_LCR, 0);
1127 
1128 			up->port.uartclk = 921600*16;
1129 			up->port.type = PORT_NS16550A;
1130 			up->capabilities |= UART_NATSEMI;
1131 			return;
1132 		}
1133 	}
1134 
1135 	/*
1136 	 * No EFR.  Try to detect a TI16750, which only sets bit 5 of
1137 	 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1138 	 * Try setting it with and without DLAB set.  Cheap clones
1139 	 * set bit 5 without DLAB set.
1140 	 */
1141 	serial_out(up, UART_LCR, 0);
1142 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1143 	status1 = serial_in(up, UART_IIR) >> 5;
1144 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1145 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1146 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1147 	status2 = serial_in(up, UART_IIR) >> 5;
1148 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149 	serial_out(up, UART_LCR, 0);
1150 
1151 	DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1152 
1153 	if (status1 == 6 && status2 == 7) {
1154 		up->port.type = PORT_16750;
1155 		up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1156 		return;
1157 	}
1158 
1159 	/*
1160 	 * Try writing and reading the UART_IER_UUE bit (b6).
1161 	 * If it works, this is probably one of the Xscale platform's
1162 	 * internal UARTs.
1163 	 * We're going to explicitly set the UUE bit to 0 before
1164 	 * trying to write and read a 1 just to make sure it's not
1165 	 * already a 1 and maybe locked there before we even start start.
1166 	 */
1167 	iersave = serial_in(up, UART_IER);
1168 	serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1169 	if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1170 		/*
1171 		 * OK it's in a known zero state, try writing and reading
1172 		 * without disturbing the current state of the other bits.
1173 		 */
1174 		serial_out(up, UART_IER, iersave | UART_IER_UUE);
1175 		if (serial_in(up, UART_IER) & UART_IER_UUE) {
1176 			/*
1177 			 * It's an Xscale.
1178 			 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1179 			 */
1180 			DEBUG_AUTOCONF("Xscale ");
1181 			up->port.type = PORT_XSCALE;
1182 			up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1183 			return;
1184 		}
1185 	} else {
1186 		/*
1187 		 * If we got here we couldn't force the IER_UUE bit to 0.
1188 		 * Log it and continue.
1189 		 */
1190 		DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1191 	}
1192 	serial_out(up, UART_IER, iersave);
1193 
1194 	/*
1195 	 * We distinguish between 16550A and U6 16550A by counting
1196 	 * how many bytes are in the FIFO.
1197 	 */
1198 	if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1199 		up->port.type = PORT_U6_16550A;
1200 		up->capabilities |= UART_CAP_AFE;
1201 	}
1202 }
1203 
1204 /*
1205  * This routine is called by rs_init() to initialize a specific serial
1206  * port.  It determines what type of UART chip this serial port is
1207  * using: 8250, 16450, 16550, 16550A.  The important question is
1208  * whether or not this UART is a 16550A or not, since this will
1209  * determine whether or not we can use its FIFO features or not.
1210  */
1211 static void autoconfig(struct uart_8250_port *up)
1212 {
1213 	unsigned char status1, scratch, scratch2, scratch3;
1214 	unsigned char save_lcr, save_mcr;
1215 	struct uart_port *port = &up->port;
1216 	unsigned long flags;
1217 	unsigned int old_capabilities;
1218 
1219 	if (!port->iobase && !port->mapbase && !port->membase)
1220 		return;
1221 
1222 	DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1223 		       port->name, port->iobase, port->membase);
1224 
1225 	/*
1226 	 * We really do need global IRQs disabled here - we're going to
1227 	 * be frobbing the chips IRQ enable register to see if it exists.
1228 	 */
1229 	spin_lock_irqsave(&port->lock, flags);
1230 
1231 	up->capabilities = 0;
1232 	up->bugs = 0;
1233 
1234 	if (!(port->flags & UPF_BUGGY_UART)) {
1235 		/*
1236 		 * Do a simple existence test first; if we fail this,
1237 		 * there's no point trying anything else.
1238 		 *
1239 		 * 0x80 is used as a nonsense port to prevent against
1240 		 * false positives due to ISA bus float.  The
1241 		 * assumption is that 0x80 is a non-existent port;
1242 		 * which should be safe since include/asm/io.h also
1243 		 * makes this assumption.
1244 		 *
1245 		 * Note: this is safe as long as MCR bit 4 is clear
1246 		 * and the device is in "PC" mode.
1247 		 */
1248 		scratch = serial_in(up, UART_IER);
1249 		serial_out(up, UART_IER, 0);
1250 #ifdef __i386__
1251 		outb(0xff, 0x080);
1252 #endif
1253 		/*
1254 		 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1255 		 * 16C754B) allow only to modify them if an EFR bit is set.
1256 		 */
1257 		scratch2 = serial_in(up, UART_IER) & 0x0f;
1258 		serial_out(up, UART_IER, 0x0F);
1259 #ifdef __i386__
1260 		outb(0, 0x080);
1261 #endif
1262 		scratch3 = serial_in(up, UART_IER) & 0x0f;
1263 		serial_out(up, UART_IER, scratch);
1264 		if (scratch2 != 0 || scratch3 != 0x0F) {
1265 			/*
1266 			 * We failed; there's nothing here
1267 			 */
1268 			spin_unlock_irqrestore(&port->lock, flags);
1269 			DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1270 				       scratch2, scratch3);
1271 			goto out;
1272 		}
1273 	}
1274 
1275 	save_mcr = serial8250_in_MCR(up);
1276 	save_lcr = serial_in(up, UART_LCR);
1277 
1278 	/*
1279 	 * Check to see if a UART is really there.  Certain broken
1280 	 * internal modems based on the Rockwell chipset fail this
1281 	 * test, because they apparently don't implement the loopback
1282 	 * test mode.  So this test is skipped on the COM 1 through
1283 	 * COM 4 ports.  This *should* be safe, since no board
1284 	 * manufacturer would be stupid enough to design a board
1285 	 * that conflicts with COM 1-4 --- we hope!
1286 	 */
1287 	if (!(port->flags & UPF_SKIP_TEST)) {
1288 		serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1289 		status1 = serial_in(up, UART_MSR) & 0xF0;
1290 		serial8250_out_MCR(up, save_mcr);
1291 		if (status1 != 0x90) {
1292 			spin_unlock_irqrestore(&port->lock, flags);
1293 			DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1294 				       status1);
1295 			goto out;
1296 		}
1297 	}
1298 
1299 	/*
1300 	 * We're pretty sure there's a port here.  Lets find out what
1301 	 * type of port it is.  The IIR top two bits allows us to find
1302 	 * out if it's 8250 or 16450, 16550, 16550A or later.  This
1303 	 * determines what we test for next.
1304 	 *
1305 	 * We also initialise the EFR (if any) to zero for later.  The
1306 	 * EFR occupies the same register location as the FCR and IIR.
1307 	 */
1308 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1309 	serial_out(up, UART_EFR, 0);
1310 	serial_out(up, UART_LCR, 0);
1311 
1312 	serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1313 
1314 	/* Assign this as it is to truncate any bits above 7.  */
1315 	scratch = serial_in(up, UART_IIR);
1316 
1317 	switch (scratch >> 6) {
1318 	case 0:
1319 		autoconfig_8250(up);
1320 		break;
1321 	case 1:
1322 		port->type = PORT_UNKNOWN;
1323 		break;
1324 	case 2:
1325 		port->type = PORT_16550;
1326 		break;
1327 	case 3:
1328 		autoconfig_16550a(up);
1329 		break;
1330 	}
1331 
1332 #ifdef CONFIG_SERIAL_8250_RSA
1333 	/*
1334 	 * Only probe for RSA ports if we got the region.
1335 	 */
1336 	if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1337 	    __enable_rsa(up))
1338 		port->type = PORT_RSA;
1339 #endif
1340 
1341 	serial_out(up, UART_LCR, save_lcr);
1342 
1343 	port->fifosize = uart_config[up->port.type].fifo_size;
1344 	old_capabilities = up->capabilities;
1345 	up->capabilities = uart_config[port->type].flags;
1346 	up->tx_loadsz = uart_config[port->type].tx_loadsz;
1347 
1348 	if (port->type == PORT_UNKNOWN)
1349 		goto out_unlock;
1350 
1351 	/*
1352 	 * Reset the UART.
1353 	 */
1354 #ifdef CONFIG_SERIAL_8250_RSA
1355 	if (port->type == PORT_RSA)
1356 		serial_out(up, UART_RSA_FRR, 0);
1357 #endif
1358 	serial8250_out_MCR(up, save_mcr);
1359 	serial8250_clear_fifos(up);
1360 	serial_in(up, UART_RX);
1361 	if (up->capabilities & UART_CAP_UUE)
1362 		serial_out(up, UART_IER, UART_IER_UUE);
1363 	else
1364 		serial_out(up, UART_IER, 0);
1365 
1366 out_unlock:
1367 	spin_unlock_irqrestore(&port->lock, flags);
1368 
1369 	/*
1370 	 * Check if the device is a Fintek F81216A
1371 	 */
1372 	if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1373 		fintek_8250_probe(up);
1374 
1375 	if (up->capabilities != old_capabilities) {
1376 		dev_warn(port->dev, "detected caps %08x should be %08x\n",
1377 			 old_capabilities, up->capabilities);
1378 	}
1379 out:
1380 	DEBUG_AUTOCONF("iir=%d ", scratch);
1381 	DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1382 }
1383 
1384 static void autoconfig_irq(struct uart_8250_port *up)
1385 {
1386 	struct uart_port *port = &up->port;
1387 	unsigned char save_mcr, save_ier;
1388 	unsigned char save_ICP = 0;
1389 	unsigned int ICP = 0;
1390 	unsigned long irqs;
1391 	int irq;
1392 
1393 	if (port->flags & UPF_FOURPORT) {
1394 		ICP = (port->iobase & 0xfe0) | 0x1f;
1395 		save_ICP = inb_p(ICP);
1396 		outb_p(0x80, ICP);
1397 		inb_p(ICP);
1398 	}
1399 
1400 	if (uart_console(port))
1401 		console_lock();
1402 
1403 	/* forget possible initially masked and pending IRQ */
1404 	probe_irq_off(probe_irq_on());
1405 	save_mcr = serial8250_in_MCR(up);
1406 	save_ier = serial_in(up, UART_IER);
1407 	serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1408 
1409 	irqs = probe_irq_on();
1410 	serial8250_out_MCR(up, 0);
1411 	udelay(10);
1412 	if (port->flags & UPF_FOURPORT) {
1413 		serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1414 	} else {
1415 		serial8250_out_MCR(up,
1416 			UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1417 	}
1418 	serial_out(up, UART_IER, 0x0f);	/* enable all intrs */
1419 	serial_in(up, UART_LSR);
1420 	serial_in(up, UART_RX);
1421 	serial_in(up, UART_IIR);
1422 	serial_in(up, UART_MSR);
1423 	serial_out(up, UART_TX, 0xFF);
1424 	udelay(20);
1425 	irq = probe_irq_off(irqs);
1426 
1427 	serial8250_out_MCR(up, save_mcr);
1428 	serial_out(up, UART_IER, save_ier);
1429 
1430 	if (port->flags & UPF_FOURPORT)
1431 		outb_p(save_ICP, ICP);
1432 
1433 	if (uart_console(port))
1434 		console_unlock();
1435 
1436 	port->irq = (irq > 0) ? irq : 0;
1437 }
1438 
1439 static void serial8250_stop_rx(struct uart_port *port)
1440 {
1441 	struct uart_8250_port *up = up_to_u8250p(port);
1442 
1443 	serial8250_rpm_get(up);
1444 
1445 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1446 	up->port.read_status_mask &= ~UART_LSR_DR;
1447 	serial_port_out(port, UART_IER, up->ier);
1448 
1449 	serial8250_rpm_put(up);
1450 }
1451 
1452 /**
1453  * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1454  * @p: uart 8250 port
1455  *
1456  * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1457  */
1458 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1459 {
1460 	unsigned char mcr = serial8250_in_MCR(p);
1461 
1462 	if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1463 		mcr |= UART_MCR_RTS;
1464 	else
1465 		mcr &= ~UART_MCR_RTS;
1466 	serial8250_out_MCR(p, mcr);
1467 
1468 	/*
1469 	 * Empty the RX FIFO, we are not interested in anything
1470 	 * received during the half-duplex transmission.
1471 	 * Enable previously disabled RX interrupts.
1472 	 */
1473 	if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1474 		serial8250_clear_and_reinit_fifos(p);
1475 
1476 		p->ier |= UART_IER_RLSI | UART_IER_RDI;
1477 		serial_port_out(&p->port, UART_IER, p->ier);
1478 	}
1479 }
1480 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1481 
1482 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1483 {
1484 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1485 			stop_tx_timer);
1486 	struct uart_8250_port *p = em485->port;
1487 	unsigned long flags;
1488 
1489 	serial8250_rpm_get(p);
1490 	spin_lock_irqsave(&p->port.lock, flags);
1491 	if (em485->active_timer == &em485->stop_tx_timer) {
1492 		p->rs485_stop_tx(p);
1493 		em485->active_timer = NULL;
1494 		em485->tx_stopped = true;
1495 	}
1496 	spin_unlock_irqrestore(&p->port.lock, flags);
1497 	serial8250_rpm_put(p);
1498 
1499 	return HRTIMER_NORESTART;
1500 }
1501 
1502 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1503 {
1504 	hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1505 }
1506 
1507 static void __stop_tx_rs485(struct uart_8250_port *p)
1508 {
1509 	struct uart_8250_em485 *em485 = p->em485;
1510 
1511 	/*
1512 	 * rs485_stop_tx() is going to set RTS according to config
1513 	 * AND flush RX FIFO if required.
1514 	 */
1515 	if (p->port.rs485.delay_rts_after_send > 0) {
1516 		em485->active_timer = &em485->stop_tx_timer;
1517 		start_hrtimer_ms(&em485->stop_tx_timer,
1518 				   p->port.rs485.delay_rts_after_send);
1519 	} else {
1520 		p->rs485_stop_tx(p);
1521 		em485->active_timer = NULL;
1522 		em485->tx_stopped = true;
1523 	}
1524 }
1525 
1526 static inline void __do_stop_tx(struct uart_8250_port *p)
1527 {
1528 	if (serial8250_clear_THRI(p))
1529 		serial8250_rpm_put_tx(p);
1530 }
1531 
1532 static inline void __stop_tx(struct uart_8250_port *p)
1533 {
1534 	struct uart_8250_em485 *em485 = p->em485;
1535 
1536 	if (em485) {
1537 		unsigned char lsr = serial_in(p, UART_LSR);
1538 		/*
1539 		 * To provide required timeing and allow FIFO transfer,
1540 		 * __stop_tx_rs485() must be called only when both FIFO and
1541 		 * shift register are empty. It is for device driver to enable
1542 		 * interrupt on TEMT.
1543 		 */
1544 		if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1545 			return;
1546 
1547 		__stop_tx_rs485(p);
1548 	}
1549 	__do_stop_tx(p);
1550 }
1551 
1552 static void serial8250_stop_tx(struct uart_port *port)
1553 {
1554 	struct uart_8250_port *up = up_to_u8250p(port);
1555 
1556 	serial8250_rpm_get(up);
1557 	__stop_tx(up);
1558 
1559 	/*
1560 	 * We really want to stop the transmitter from sending.
1561 	 */
1562 	if (port->type == PORT_16C950) {
1563 		up->acr |= UART_ACR_TXDIS;
1564 		serial_icr_write(up, UART_ACR, up->acr);
1565 	}
1566 	serial8250_rpm_put(up);
1567 }
1568 
1569 static inline void __start_tx(struct uart_port *port)
1570 {
1571 	struct uart_8250_port *up = up_to_u8250p(port);
1572 
1573 	if (up->dma && !up->dma->tx_dma(up))
1574 		return;
1575 
1576 	if (serial8250_set_THRI(up)) {
1577 		if (up->bugs & UART_BUG_TXEN) {
1578 			unsigned char lsr;
1579 
1580 			lsr = serial_in(up, UART_LSR);
1581 			up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1582 			if (lsr & UART_LSR_THRE)
1583 				serial8250_tx_chars(up);
1584 		}
1585 	}
1586 
1587 	/*
1588 	 * Re-enable the transmitter if we disabled it.
1589 	 */
1590 	if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1591 		up->acr &= ~UART_ACR_TXDIS;
1592 		serial_icr_write(up, UART_ACR, up->acr);
1593 	}
1594 }
1595 
1596 /**
1597  * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1598  * @up: uart 8250 port
1599  *
1600  * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1601  * Assumes that setting the RTS bit in the MCR register means RTS is high.
1602  * (Some chips use inverse semantics.)  Further assumes that reception is
1603  * stoppable by disabling the UART_IER_RDI interrupt.  (Some chips set the
1604  * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1605  */
1606 void serial8250_em485_start_tx(struct uart_8250_port *up)
1607 {
1608 	unsigned char mcr = serial8250_in_MCR(up);
1609 
1610 	if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1611 		serial8250_stop_rx(&up->port);
1612 
1613 	if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1614 		mcr |= UART_MCR_RTS;
1615 	else
1616 		mcr &= ~UART_MCR_RTS;
1617 	serial8250_out_MCR(up, mcr);
1618 }
1619 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1620 
1621 static inline void start_tx_rs485(struct uart_port *port)
1622 {
1623 	struct uart_8250_port *up = up_to_u8250p(port);
1624 	struct uart_8250_em485 *em485 = up->em485;
1625 
1626 	/*
1627 	 * While serial8250_em485_handle_stop_tx() is a noop if
1628 	 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1629 	 * the timer is still armed and triggers only after the current bunch of
1630 	 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1631 	 * So cancel the timer. There is still a theoretical race condition if
1632 	 * the timer is already running and only comes around to check for
1633 	 * em485->active_timer when &em485->stop_tx_timer is armed again.
1634 	 */
1635 	if (em485->active_timer == &em485->stop_tx_timer)
1636 		hrtimer_try_to_cancel(&em485->stop_tx_timer);
1637 
1638 	em485->active_timer = NULL;
1639 
1640 	if (em485->tx_stopped) {
1641 		em485->tx_stopped = false;
1642 
1643 		up->rs485_start_tx(up);
1644 
1645 		if (up->port.rs485.delay_rts_before_send > 0) {
1646 			em485->active_timer = &em485->start_tx_timer;
1647 			start_hrtimer_ms(&em485->start_tx_timer,
1648 					 up->port.rs485.delay_rts_before_send);
1649 			return;
1650 		}
1651 	}
1652 
1653 	__start_tx(port);
1654 }
1655 
1656 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1657 {
1658 	struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1659 			start_tx_timer);
1660 	struct uart_8250_port *p = em485->port;
1661 	unsigned long flags;
1662 
1663 	spin_lock_irqsave(&p->port.lock, flags);
1664 	if (em485->active_timer == &em485->start_tx_timer) {
1665 		__start_tx(&p->port);
1666 		em485->active_timer = NULL;
1667 	}
1668 	spin_unlock_irqrestore(&p->port.lock, flags);
1669 
1670 	return HRTIMER_NORESTART;
1671 }
1672 
1673 static void serial8250_start_tx(struct uart_port *port)
1674 {
1675 	struct uart_8250_port *up = up_to_u8250p(port);
1676 	struct uart_8250_em485 *em485 = up->em485;
1677 
1678 	serial8250_rpm_get_tx(up);
1679 
1680 	if (!port->x_char && uart_circ_empty(&port->state->xmit))
1681 		return;
1682 
1683 	if (em485 &&
1684 	    em485->active_timer == &em485->start_tx_timer)
1685 		return;
1686 
1687 	if (em485)
1688 		start_tx_rs485(port);
1689 	else
1690 		__start_tx(port);
1691 }
1692 
1693 static void serial8250_throttle(struct uart_port *port)
1694 {
1695 	port->throttle(port);
1696 }
1697 
1698 static void serial8250_unthrottle(struct uart_port *port)
1699 {
1700 	port->unthrottle(port);
1701 }
1702 
1703 static void serial8250_disable_ms(struct uart_port *port)
1704 {
1705 	struct uart_8250_port *up = up_to_u8250p(port);
1706 
1707 	/* no MSR capabilities */
1708 	if (up->bugs & UART_BUG_NOMSR)
1709 		return;
1710 
1711 	mctrl_gpio_disable_ms(up->gpios);
1712 
1713 	up->ier &= ~UART_IER_MSI;
1714 	serial_port_out(port, UART_IER, up->ier);
1715 }
1716 
1717 static void serial8250_enable_ms(struct uart_port *port)
1718 {
1719 	struct uart_8250_port *up = up_to_u8250p(port);
1720 
1721 	/* no MSR capabilities */
1722 	if (up->bugs & UART_BUG_NOMSR)
1723 		return;
1724 
1725 	mctrl_gpio_enable_ms(up->gpios);
1726 
1727 	up->ier |= UART_IER_MSI;
1728 
1729 	serial8250_rpm_get(up);
1730 	serial_port_out(port, UART_IER, up->ier);
1731 	serial8250_rpm_put(up);
1732 }
1733 
1734 void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1735 {
1736 	struct uart_port *port = &up->port;
1737 	unsigned char ch;
1738 	char flag = TTY_NORMAL;
1739 
1740 	if (likely(lsr & UART_LSR_DR))
1741 		ch = serial_in(up, UART_RX);
1742 	else
1743 		/*
1744 		 * Intel 82571 has a Serial Over Lan device that will
1745 		 * set UART_LSR_BI without setting UART_LSR_DR when
1746 		 * it receives a break. To avoid reading from the
1747 		 * receive buffer without UART_LSR_DR bit set, we
1748 		 * just force the read character to be 0
1749 		 */
1750 		ch = 0;
1751 
1752 	port->icount.rx++;
1753 
1754 	lsr |= up->lsr_saved_flags;
1755 	up->lsr_saved_flags = 0;
1756 
1757 	if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1758 		if (lsr & UART_LSR_BI) {
1759 			lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1760 			port->icount.brk++;
1761 			/*
1762 			 * We do the SysRQ and SAK checking
1763 			 * here because otherwise the break
1764 			 * may get masked by ignore_status_mask
1765 			 * or read_status_mask.
1766 			 */
1767 			if (uart_handle_break(port))
1768 				return;
1769 		} else if (lsr & UART_LSR_PE)
1770 			port->icount.parity++;
1771 		else if (lsr & UART_LSR_FE)
1772 			port->icount.frame++;
1773 		if (lsr & UART_LSR_OE)
1774 			port->icount.overrun++;
1775 
1776 		/*
1777 		 * Mask off conditions which should be ignored.
1778 		 */
1779 		lsr &= port->read_status_mask;
1780 
1781 		if (lsr & UART_LSR_BI) {
1782 			dev_dbg(port->dev, "handling break\n");
1783 			flag = TTY_BREAK;
1784 		} else if (lsr & UART_LSR_PE)
1785 			flag = TTY_PARITY;
1786 		else if (lsr & UART_LSR_FE)
1787 			flag = TTY_FRAME;
1788 	}
1789 	if (uart_prepare_sysrq_char(port, ch))
1790 		return;
1791 
1792 	uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1793 }
1794 EXPORT_SYMBOL_GPL(serial8250_read_char);
1795 
1796 /*
1797  * serial8250_rx_chars: processes according to the passed in LSR
1798  * value, and returns the remaining LSR bits not handled
1799  * by this Rx routine.
1800  */
1801 unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1802 {
1803 	struct uart_port *port = &up->port;
1804 	int max_count = 256;
1805 
1806 	do {
1807 		serial8250_read_char(up, lsr);
1808 		if (--max_count == 0)
1809 			break;
1810 		lsr = serial_in(up, UART_LSR);
1811 	} while (lsr & (UART_LSR_DR | UART_LSR_BI));
1812 
1813 	tty_flip_buffer_push(&port->state->port);
1814 	return lsr;
1815 }
1816 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1817 
1818 void serial8250_tx_chars(struct uart_8250_port *up)
1819 {
1820 	struct uart_port *port = &up->port;
1821 	struct circ_buf *xmit = &port->state->xmit;
1822 	int count;
1823 
1824 	if (port->x_char) {
1825 		uart_xchar_out(port, UART_TX);
1826 		return;
1827 	}
1828 	if (uart_tx_stopped(port)) {
1829 		serial8250_stop_tx(port);
1830 		return;
1831 	}
1832 	if (uart_circ_empty(xmit)) {
1833 		__stop_tx(up);
1834 		return;
1835 	}
1836 
1837 	count = up->tx_loadsz;
1838 	do {
1839 		serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1840 		if (up->bugs & UART_BUG_TXRACE) {
1841 			/*
1842 			 * The Aspeed BMC virtual UARTs have a bug where data
1843 			 * may get stuck in the BMC's Tx FIFO from bursts of
1844 			 * writes on the APB interface.
1845 			 *
1846 			 * Delay back-to-back writes by a read cycle to avoid
1847 			 * stalling the VUART. Read a register that won't have
1848 			 * side-effects and discard the result.
1849 			 */
1850 			serial_in(up, UART_SCR);
1851 		}
1852 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1853 		port->icount.tx++;
1854 		if (uart_circ_empty(xmit))
1855 			break;
1856 		if ((up->capabilities & UART_CAP_HFIFO) &&
1857 		    (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1858 			break;
1859 		/* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1860 		if ((up->capabilities & UART_CAP_MINI) &&
1861 		    !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1862 			break;
1863 	} while (--count > 0);
1864 
1865 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1866 		uart_write_wakeup(port);
1867 
1868 	/*
1869 	 * With RPM enabled, we have to wait until the FIFO is empty before the
1870 	 * HW can go idle. So we get here once again with empty FIFO and disable
1871 	 * the interrupt and RPM in __stop_tx()
1872 	 */
1873 	if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1874 		__stop_tx(up);
1875 }
1876 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1877 
1878 /* Caller holds uart port lock */
1879 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1880 {
1881 	struct uart_port *port = &up->port;
1882 	unsigned int status = serial_in(up, UART_MSR);
1883 
1884 	status |= up->msr_saved_flags;
1885 	up->msr_saved_flags = 0;
1886 	if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1887 	    port->state != NULL) {
1888 		if (status & UART_MSR_TERI)
1889 			port->icount.rng++;
1890 		if (status & UART_MSR_DDSR)
1891 			port->icount.dsr++;
1892 		if (status & UART_MSR_DDCD)
1893 			uart_handle_dcd_change(port, status & UART_MSR_DCD);
1894 		if (status & UART_MSR_DCTS)
1895 			uart_handle_cts_change(port, status & UART_MSR_CTS);
1896 
1897 		wake_up_interruptible(&port->state->port.delta_msr_wait);
1898 	}
1899 
1900 	return status;
1901 }
1902 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1903 
1904 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1905 {
1906 	switch (iir & 0x3f) {
1907 	case UART_IIR_RX_TIMEOUT:
1908 		serial8250_rx_dma_flush(up);
1909 		fallthrough;
1910 	case UART_IIR_RLSI:
1911 		return true;
1912 	}
1913 	return up->dma->rx_dma(up);
1914 }
1915 
1916 /*
1917  * This handles the interrupt from one port.
1918  */
1919 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1920 {
1921 	unsigned char status;
1922 	struct uart_8250_port *up = up_to_u8250p(port);
1923 	bool skip_rx = false;
1924 	unsigned long flags;
1925 
1926 	if (iir & UART_IIR_NO_INT)
1927 		return 0;
1928 
1929 	spin_lock_irqsave(&port->lock, flags);
1930 
1931 	status = serial_port_in(port, UART_LSR);
1932 
1933 	/*
1934 	 * If port is stopped and there are no error conditions in the
1935 	 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1936 	 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1937 	 * control when FIFO occupancy reaches preset threshold, thus
1938 	 * halting RX. This only works when auto HW flow control is
1939 	 * available.
1940 	 */
1941 	if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1942 	    (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1943 	    !(port->read_status_mask & UART_LSR_DR))
1944 		skip_rx = true;
1945 
1946 	if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1947 		if (!up->dma || handle_rx_dma(up, iir))
1948 			status = serial8250_rx_chars(up, status);
1949 	}
1950 	serial8250_modem_status(up);
1951 	if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE) &&
1952 		(up->ier & UART_IER_THRI))
1953 		serial8250_tx_chars(up);
1954 
1955 	uart_unlock_and_check_sysrq_irqrestore(port, flags);
1956 
1957 	return 1;
1958 }
1959 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1960 
1961 static int serial8250_default_handle_irq(struct uart_port *port)
1962 {
1963 	struct uart_8250_port *up = up_to_u8250p(port);
1964 	unsigned int iir;
1965 	int ret;
1966 
1967 	serial8250_rpm_get(up);
1968 
1969 	iir = serial_port_in(port, UART_IIR);
1970 	ret = serial8250_handle_irq(port, iir);
1971 
1972 	serial8250_rpm_put(up);
1973 	return ret;
1974 }
1975 
1976 /*
1977  * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1978  * have a programmable TX threshold that triggers the THRE interrupt in
1979  * the IIR register. In this case, the THRE interrupt indicates the FIFO
1980  * has space available. Load it up with tx_loadsz bytes.
1981  */
1982 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1983 {
1984 	unsigned long flags;
1985 	unsigned int iir = serial_port_in(port, UART_IIR);
1986 
1987 	/* TX Threshold IRQ triggered so load up FIFO */
1988 	if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1989 		struct uart_8250_port *up = up_to_u8250p(port);
1990 
1991 		spin_lock_irqsave(&port->lock, flags);
1992 		serial8250_tx_chars(up);
1993 		spin_unlock_irqrestore(&port->lock, flags);
1994 	}
1995 
1996 	iir = serial_port_in(port, UART_IIR);
1997 	return serial8250_handle_irq(port, iir);
1998 }
1999 
2000 static unsigned int serial8250_tx_empty(struct uart_port *port)
2001 {
2002 	struct uart_8250_port *up = up_to_u8250p(port);
2003 	unsigned long flags;
2004 	unsigned int lsr;
2005 
2006 	serial8250_rpm_get(up);
2007 
2008 	spin_lock_irqsave(&port->lock, flags);
2009 	lsr = serial_port_in(port, UART_LSR);
2010 	up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
2011 	spin_unlock_irqrestore(&port->lock, flags);
2012 
2013 	serial8250_rpm_put(up);
2014 
2015 	return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
2016 }
2017 
2018 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2019 {
2020 	struct uart_8250_port *up = up_to_u8250p(port);
2021 	unsigned int status;
2022 	unsigned int val;
2023 
2024 	serial8250_rpm_get(up);
2025 	status = serial8250_modem_status(up);
2026 	serial8250_rpm_put(up);
2027 
2028 	val = serial8250_MSR_to_TIOCM(status);
2029 	if (up->gpios)
2030 		return mctrl_gpio_get(up->gpios, &val);
2031 
2032 	return val;
2033 }
2034 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2035 
2036 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2037 {
2038 	if (port->get_mctrl)
2039 		return port->get_mctrl(port);
2040 	return serial8250_do_get_mctrl(port);
2041 }
2042 
2043 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2044 {
2045 	struct uart_8250_port *up = up_to_u8250p(port);
2046 	unsigned char mcr;
2047 
2048 	mcr = serial8250_TIOCM_to_MCR(mctrl);
2049 
2050 	mcr |= up->mcr;
2051 
2052 	serial8250_out_MCR(up, mcr);
2053 }
2054 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2055 
2056 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2057 {
2058 	if (port->set_mctrl)
2059 		port->set_mctrl(port, mctrl);
2060 	else
2061 		serial8250_do_set_mctrl(port, mctrl);
2062 }
2063 
2064 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2065 {
2066 	struct uart_8250_port *up = up_to_u8250p(port);
2067 	unsigned long flags;
2068 
2069 	serial8250_rpm_get(up);
2070 	spin_lock_irqsave(&port->lock, flags);
2071 	if (break_state == -1)
2072 		up->lcr |= UART_LCR_SBC;
2073 	else
2074 		up->lcr &= ~UART_LCR_SBC;
2075 	serial_port_out(port, UART_LCR, up->lcr);
2076 	spin_unlock_irqrestore(&port->lock, flags);
2077 	serial8250_rpm_put(up);
2078 }
2079 
2080 /*
2081  *	Wait for transmitter & holding register to empty
2082  */
2083 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2084 {
2085 	unsigned int status, tmout = 10000;
2086 
2087 	/* Wait up to 10ms for the character(s) to be sent. */
2088 	for (;;) {
2089 		status = serial_in(up, UART_LSR);
2090 
2091 		up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
2092 
2093 		if ((status & bits) == bits)
2094 			break;
2095 		if (--tmout == 0)
2096 			break;
2097 		udelay(1);
2098 		touch_nmi_watchdog();
2099 	}
2100 
2101 	/* Wait up to 1s for flow control if necessary */
2102 	if (up->port.flags & UPF_CONS_FLOW) {
2103 		for (tmout = 1000000; tmout; tmout--) {
2104 			unsigned int msr = serial_in(up, UART_MSR);
2105 			up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2106 			if (msr & UART_MSR_CTS)
2107 				break;
2108 			udelay(1);
2109 			touch_nmi_watchdog();
2110 		}
2111 	}
2112 }
2113 
2114 #ifdef CONFIG_CONSOLE_POLL
2115 /*
2116  * Console polling routines for writing and reading from the uart while
2117  * in an interrupt or debug context.
2118  */
2119 
2120 static int serial8250_get_poll_char(struct uart_port *port)
2121 {
2122 	struct uart_8250_port *up = up_to_u8250p(port);
2123 	unsigned char lsr;
2124 	int status;
2125 
2126 	serial8250_rpm_get(up);
2127 
2128 	lsr = serial_port_in(port, UART_LSR);
2129 
2130 	if (!(lsr & UART_LSR_DR)) {
2131 		status = NO_POLL_CHAR;
2132 		goto out;
2133 	}
2134 
2135 	status = serial_port_in(port, UART_RX);
2136 out:
2137 	serial8250_rpm_put(up);
2138 	return status;
2139 }
2140 
2141 
2142 static void serial8250_put_poll_char(struct uart_port *port,
2143 			 unsigned char c)
2144 {
2145 	unsigned int ier;
2146 	struct uart_8250_port *up = up_to_u8250p(port);
2147 
2148 	serial8250_rpm_get(up);
2149 	/*
2150 	 *	First save the IER then disable the interrupts
2151 	 */
2152 	ier = serial_port_in(port, UART_IER);
2153 	if (up->capabilities & UART_CAP_UUE)
2154 		serial_port_out(port, UART_IER, UART_IER_UUE);
2155 	else
2156 		serial_port_out(port, UART_IER, 0);
2157 
2158 	wait_for_xmitr(up, BOTH_EMPTY);
2159 	/*
2160 	 *	Send the character out.
2161 	 */
2162 	serial_port_out(port, UART_TX, c);
2163 
2164 	/*
2165 	 *	Finally, wait for transmitter to become empty
2166 	 *	and restore the IER
2167 	 */
2168 	wait_for_xmitr(up, BOTH_EMPTY);
2169 	serial_port_out(port, UART_IER, ier);
2170 	serial8250_rpm_put(up);
2171 }
2172 
2173 #endif /* CONFIG_CONSOLE_POLL */
2174 
2175 int serial8250_do_startup(struct uart_port *port)
2176 {
2177 	struct uart_8250_port *up = up_to_u8250p(port);
2178 	unsigned long flags;
2179 	unsigned char lsr, iir;
2180 	int retval;
2181 
2182 	if (!port->fifosize)
2183 		port->fifosize = uart_config[port->type].fifo_size;
2184 	if (!up->tx_loadsz)
2185 		up->tx_loadsz = uart_config[port->type].tx_loadsz;
2186 	if (!up->capabilities)
2187 		up->capabilities = uart_config[port->type].flags;
2188 	up->mcr = 0;
2189 
2190 	if (port->iotype != up->cur_iotype)
2191 		set_io_from_upio(port);
2192 
2193 	serial8250_rpm_get(up);
2194 	if (port->type == PORT_16C950) {
2195 		/* Wake up and initialize UART */
2196 		up->acr = 0;
2197 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2198 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2199 		serial_port_out(port, UART_IER, 0);
2200 		serial_port_out(port, UART_LCR, 0);
2201 		serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2202 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2203 		serial_port_out(port, UART_EFR, UART_EFR_ECB);
2204 		serial_port_out(port, UART_LCR, 0);
2205 	}
2206 
2207 	if (port->type == PORT_DA830) {
2208 		/* Reset the port */
2209 		serial_port_out(port, UART_IER, 0);
2210 		serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2211 		mdelay(10);
2212 
2213 		/* Enable Tx, Rx and free run mode */
2214 		serial_port_out(port, UART_DA830_PWREMU_MGMT,
2215 				UART_DA830_PWREMU_MGMT_UTRST |
2216 				UART_DA830_PWREMU_MGMT_URRST |
2217 				UART_DA830_PWREMU_MGMT_FREE);
2218 	}
2219 
2220 	if (port->type == PORT_NPCM) {
2221 		/*
2222 		 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2223 		 * register). Enable it, and set TIOC (timeout interrupt
2224 		 * comparator) to be 0x20 for correct operation.
2225 		 */
2226 		serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2227 	}
2228 
2229 #ifdef CONFIG_SERIAL_8250_RSA
2230 	/*
2231 	 * If this is an RSA port, see if we can kick it up to the
2232 	 * higher speed clock.
2233 	 */
2234 	enable_rsa(up);
2235 #endif
2236 
2237 	/*
2238 	 * Clear the FIFO buffers and disable them.
2239 	 * (they will be reenabled in set_termios())
2240 	 */
2241 	serial8250_clear_fifos(up);
2242 
2243 	/*
2244 	 * Clear the interrupt registers.
2245 	 */
2246 	serial_port_in(port, UART_LSR);
2247 	serial_port_in(port, UART_RX);
2248 	serial_port_in(port, UART_IIR);
2249 	serial_port_in(port, UART_MSR);
2250 
2251 	/*
2252 	 * At this point, there's no way the LSR could still be 0xff;
2253 	 * if it is, then bail out, because there's likely no UART
2254 	 * here.
2255 	 */
2256 	if (!(port->flags & UPF_BUGGY_UART) &&
2257 	    (serial_port_in(port, UART_LSR) == 0xff)) {
2258 		dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2259 		retval = -ENODEV;
2260 		goto out;
2261 	}
2262 
2263 	/*
2264 	 * For a XR16C850, we need to set the trigger levels
2265 	 */
2266 	if (port->type == PORT_16850) {
2267 		unsigned char fctr;
2268 
2269 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2270 
2271 		fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2272 		serial_port_out(port, UART_FCTR,
2273 				fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2274 		serial_port_out(port, UART_TRG, UART_TRG_96);
2275 		serial_port_out(port, UART_FCTR,
2276 				fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2277 		serial_port_out(port, UART_TRG, UART_TRG_96);
2278 
2279 		serial_port_out(port, UART_LCR, 0);
2280 	}
2281 
2282 	/*
2283 	 * For the Altera 16550 variants, set TX threshold trigger level.
2284 	 */
2285 	if (((port->type == PORT_ALTR_16550_F32) ||
2286 	     (port->type == PORT_ALTR_16550_F64) ||
2287 	     (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2288 		/* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2289 		if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2290 			dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2291 		} else {
2292 			serial_port_out(port, UART_ALTR_AFR,
2293 					UART_ALTR_EN_TXFIFO_LW);
2294 			serial_port_out(port, UART_ALTR_TX_LOW,
2295 					port->fifosize - up->tx_loadsz);
2296 			port->handle_irq = serial8250_tx_threshold_handle_irq;
2297 		}
2298 	}
2299 
2300 	/* Check if we need to have shared IRQs */
2301 	if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2302 		up->port.irqflags |= IRQF_SHARED;
2303 
2304 	if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2305 		unsigned char iir1;
2306 
2307 		if (port->irqflags & IRQF_SHARED)
2308 			disable_irq_nosync(port->irq);
2309 
2310 		/*
2311 		 * Test for UARTs that do not reassert THRE when the
2312 		 * transmitter is idle and the interrupt has already
2313 		 * been cleared.  Real 16550s should always reassert
2314 		 * this interrupt whenever the transmitter is idle and
2315 		 * the interrupt is enabled.  Delays are necessary to
2316 		 * allow register changes to become visible.
2317 		 */
2318 		spin_lock_irqsave(&port->lock, flags);
2319 
2320 		wait_for_xmitr(up, UART_LSR_THRE);
2321 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2322 		udelay(1); /* allow THRE to set */
2323 		iir1 = serial_port_in(port, UART_IIR);
2324 		serial_port_out(port, UART_IER, 0);
2325 		serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2326 		udelay(1); /* allow a working UART time to re-assert THRE */
2327 		iir = serial_port_in(port, UART_IIR);
2328 		serial_port_out(port, UART_IER, 0);
2329 
2330 		spin_unlock_irqrestore(&port->lock, flags);
2331 
2332 		if (port->irqflags & IRQF_SHARED)
2333 			enable_irq(port->irq);
2334 
2335 		/*
2336 		 * If the interrupt is not reasserted, or we otherwise
2337 		 * don't trust the iir, setup a timer to kick the UART
2338 		 * on a regular basis.
2339 		 */
2340 		if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2341 		    up->port.flags & UPF_BUG_THRE) {
2342 			up->bugs |= UART_BUG_THRE;
2343 		}
2344 	}
2345 
2346 	retval = up->ops->setup_irq(up);
2347 	if (retval)
2348 		goto out;
2349 
2350 	/*
2351 	 * Now, initialize the UART
2352 	 */
2353 	serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2354 
2355 	spin_lock_irqsave(&port->lock, flags);
2356 	if (up->port.flags & UPF_FOURPORT) {
2357 		if (!up->port.irq)
2358 			up->port.mctrl |= TIOCM_OUT1;
2359 	} else
2360 		/*
2361 		 * Most PC uarts need OUT2 raised to enable interrupts.
2362 		 */
2363 		if (port->irq)
2364 			up->port.mctrl |= TIOCM_OUT2;
2365 
2366 	serial8250_set_mctrl(port, port->mctrl);
2367 
2368 	/*
2369 	 * Serial over Lan (SoL) hack:
2370 	 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2371 	 * used for Serial Over Lan.  Those chips take a longer time than a
2372 	 * normal serial device to signalize that a transmission data was
2373 	 * queued. Due to that, the above test generally fails. One solution
2374 	 * would be to delay the reading of iir. However, this is not
2375 	 * reliable, since the timeout is variable. So, let's just don't
2376 	 * test if we receive TX irq.  This way, we'll never enable
2377 	 * UART_BUG_TXEN.
2378 	 */
2379 	if (up->port.quirks & UPQ_NO_TXEN_TEST)
2380 		goto dont_test_tx_en;
2381 
2382 	/*
2383 	 * Do a quick test to see if we receive an interrupt when we enable
2384 	 * the TX irq.
2385 	 */
2386 	serial_port_out(port, UART_IER, UART_IER_THRI);
2387 	lsr = serial_port_in(port, UART_LSR);
2388 	iir = serial_port_in(port, UART_IIR);
2389 	serial_port_out(port, UART_IER, 0);
2390 
2391 	if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2392 		if (!(up->bugs & UART_BUG_TXEN)) {
2393 			up->bugs |= UART_BUG_TXEN;
2394 			dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2395 		}
2396 	} else {
2397 		up->bugs &= ~UART_BUG_TXEN;
2398 	}
2399 
2400 dont_test_tx_en:
2401 	spin_unlock_irqrestore(&port->lock, flags);
2402 
2403 	/*
2404 	 * Clear the interrupt registers again for luck, and clear the
2405 	 * saved flags to avoid getting false values from polling
2406 	 * routines or the previous session.
2407 	 */
2408 	serial_port_in(port, UART_LSR);
2409 	serial_port_in(port, UART_RX);
2410 	serial_port_in(port, UART_IIR);
2411 	serial_port_in(port, UART_MSR);
2412 	up->lsr_saved_flags = 0;
2413 	up->msr_saved_flags = 0;
2414 
2415 	/*
2416 	 * Request DMA channels for both RX and TX.
2417 	 */
2418 	if (up->dma) {
2419 		const char *msg = NULL;
2420 
2421 		if (uart_console(port))
2422 			msg = "forbid DMA for kernel console";
2423 		else if (serial8250_request_dma(up))
2424 			msg = "failed to request DMA";
2425 		if (msg) {
2426 			dev_warn_ratelimited(port->dev, "%s\n", msg);
2427 			up->dma = NULL;
2428 		}
2429 	}
2430 
2431 	/*
2432 	 * Set the IER shadow for rx interrupts but defer actual interrupt
2433 	 * enable until after the FIFOs are enabled; otherwise, an already-
2434 	 * active sender can swamp the interrupt handler with "too much work".
2435 	 */
2436 	up->ier = UART_IER_RLSI | UART_IER_RDI;
2437 
2438 	if (port->flags & UPF_FOURPORT) {
2439 		unsigned int icp;
2440 		/*
2441 		 * Enable interrupts on the AST Fourport board
2442 		 */
2443 		icp = (port->iobase & 0xfe0) | 0x01f;
2444 		outb_p(0x80, icp);
2445 		inb_p(icp);
2446 	}
2447 	retval = 0;
2448 out:
2449 	serial8250_rpm_put(up);
2450 	return retval;
2451 }
2452 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2453 
2454 static int serial8250_startup(struct uart_port *port)
2455 {
2456 	if (port->startup)
2457 		return port->startup(port);
2458 	return serial8250_do_startup(port);
2459 }
2460 
2461 void serial8250_do_shutdown(struct uart_port *port)
2462 {
2463 	struct uart_8250_port *up = up_to_u8250p(port);
2464 	unsigned long flags;
2465 
2466 	serial8250_rpm_get(up);
2467 	/*
2468 	 * Disable interrupts from this port
2469 	 */
2470 	spin_lock_irqsave(&port->lock, flags);
2471 	up->ier = 0;
2472 	serial_port_out(port, UART_IER, 0);
2473 	spin_unlock_irqrestore(&port->lock, flags);
2474 
2475 	synchronize_irq(port->irq);
2476 
2477 	if (up->dma)
2478 		serial8250_release_dma(up);
2479 
2480 	spin_lock_irqsave(&port->lock, flags);
2481 	if (port->flags & UPF_FOURPORT) {
2482 		/* reset interrupts on the AST Fourport board */
2483 		inb((port->iobase & 0xfe0) | 0x1f);
2484 		port->mctrl |= TIOCM_OUT1;
2485 	} else
2486 		port->mctrl &= ~TIOCM_OUT2;
2487 
2488 	serial8250_set_mctrl(port, port->mctrl);
2489 	spin_unlock_irqrestore(&port->lock, flags);
2490 
2491 	/*
2492 	 * Disable break condition and FIFOs
2493 	 */
2494 	serial_port_out(port, UART_LCR,
2495 			serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2496 	serial8250_clear_fifos(up);
2497 
2498 #ifdef CONFIG_SERIAL_8250_RSA
2499 	/*
2500 	 * Reset the RSA board back to 115kbps compat mode.
2501 	 */
2502 	disable_rsa(up);
2503 #endif
2504 
2505 	/*
2506 	 * Read data port to reset things, and then unlink from
2507 	 * the IRQ chain.
2508 	 */
2509 	serial_port_in(port, UART_RX);
2510 	serial8250_rpm_put(up);
2511 
2512 	up->ops->release_irq(up);
2513 }
2514 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2515 
2516 static void serial8250_shutdown(struct uart_port *port)
2517 {
2518 	if (port->shutdown)
2519 		port->shutdown(port);
2520 	else
2521 		serial8250_do_shutdown(port);
2522 }
2523 
2524 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2525 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2526 		unsigned int baud)
2527 {
2528 	struct uart_port *port = &up->port;
2529 
2530 	return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2531 }
2532 
2533 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2534 					      unsigned int baud,
2535 					      unsigned int *frac)
2536 {
2537 	upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2538 	struct uart_8250_port *up = up_to_u8250p(port);
2539 	unsigned int quot;
2540 
2541 	/*
2542 	 * Handle magic divisors for baud rates above baud_base on SMSC
2543 	 * Super I/O chips.  We clamp custom rates from clk/6 and clk/12
2544 	 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively.  These
2545 	 * magic divisors actually reprogram the baud rate generator's
2546 	 * reference clock derived from chips's 14.318MHz clock input.
2547 	 *
2548 	 * Documentation claims that with these magic divisors the base
2549 	 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2550 	 * for the extra baud rates of 460800bps and 230400bps rather
2551 	 * than the usual base frequency of 1.8462MHz.  However empirical
2552 	 * evidence contradicts that.
2553 	 *
2554 	 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2555 	 * effectively used as a clock prescaler selection bit for the
2556 	 * base frequency of 7.3728MHz, always used.  If set to 0, then
2557 	 * the base frequency is divided by 4 for use by the Baud Rate
2558 	 * Generator, for the usual arrangement where the value of 1 of
2559 	 * the divisor produces the baud rate of 115200bps.  Conversely,
2560 	 * if set to 1 and high-speed operation has been enabled with the
2561 	 * Serial Port Mode Register in the Device Configuration Space,
2562 	 * then the base frequency is supplied directly to the Baud Rate
2563 	 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2564 	 * 0x8004, etc. the respective baud rates produced are 460800bps,
2565 	 * 230400bps, 153600bps, 115200bps, etc.
2566 	 *
2567 	 * In all cases only low 15 bits of the divisor are used to divide
2568 	 * the baud base and therefore 32767 is the maximum divisor value
2569 	 * possible, even though documentation says that the programmable
2570 	 * Baud Rate Generator is capable of dividing the internal PLL
2571 	 * clock by any divisor from 1 to 65535.
2572 	 */
2573 	if (magic_multiplier && baud >= port->uartclk / 6)
2574 		quot = 0x8001;
2575 	else if (magic_multiplier && baud >= port->uartclk / 12)
2576 		quot = 0x8002;
2577 	else if (up->port.type == PORT_NPCM)
2578 		quot = npcm_get_divisor(up, baud);
2579 	else
2580 		quot = uart_get_divisor(port, baud);
2581 
2582 	/*
2583 	 * Oxford Semi 952 rev B workaround
2584 	 */
2585 	if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2586 		quot++;
2587 
2588 	return quot;
2589 }
2590 
2591 static unsigned int serial8250_get_divisor(struct uart_port *port,
2592 					   unsigned int baud,
2593 					   unsigned int *frac)
2594 {
2595 	if (port->get_divisor)
2596 		return port->get_divisor(port, baud, frac);
2597 
2598 	return serial8250_do_get_divisor(port, baud, frac);
2599 }
2600 
2601 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2602 					    tcflag_t c_cflag)
2603 {
2604 	unsigned char cval;
2605 
2606 	cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2607 
2608 	if (c_cflag & CSTOPB)
2609 		cval |= UART_LCR_STOP;
2610 	if (c_cflag & PARENB) {
2611 		cval |= UART_LCR_PARITY;
2612 		if (up->bugs & UART_BUG_PARITY)
2613 			up->fifo_bug = true;
2614 	}
2615 	if (!(c_cflag & PARODD))
2616 		cval |= UART_LCR_EPAR;
2617 #ifdef CMSPAR
2618 	if (c_cflag & CMSPAR)
2619 		cval |= UART_LCR_SPAR;
2620 #endif
2621 
2622 	return cval;
2623 }
2624 
2625 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2626 			       unsigned int quot, unsigned int quot_frac)
2627 {
2628 	struct uart_8250_port *up = up_to_u8250p(port);
2629 
2630 	/* Workaround to enable 115200 baud on OMAP1510 internal ports */
2631 	if (is_omap1510_8250(up)) {
2632 		if (baud == 115200) {
2633 			quot = 1;
2634 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2635 		} else
2636 			serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2637 	}
2638 
2639 	/*
2640 	 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2641 	 * otherwise just set DLAB
2642 	 */
2643 	if (up->capabilities & UART_NATSEMI)
2644 		serial_port_out(port, UART_LCR, 0xe0);
2645 	else
2646 		serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2647 
2648 	serial_dl_write(up, quot);
2649 }
2650 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2651 
2652 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2653 				   unsigned int quot, unsigned int quot_frac)
2654 {
2655 	if (port->set_divisor)
2656 		port->set_divisor(port, baud, quot, quot_frac);
2657 	else
2658 		serial8250_do_set_divisor(port, baud, quot, quot_frac);
2659 }
2660 
2661 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2662 					     struct ktermios *termios,
2663 					     struct ktermios *old)
2664 {
2665 	unsigned int tolerance = port->uartclk / 100;
2666 	unsigned int min;
2667 	unsigned int max;
2668 
2669 	/*
2670 	 * Handle magic divisors for baud rates above baud_base on SMSC
2671 	 * Super I/O chips.  Enable custom rates of clk/4 and clk/8, but
2672 	 * disable divisor values beyond 32767, which are unavailable.
2673 	 */
2674 	if (port->flags & UPF_MAGIC_MULTIPLIER) {
2675 		min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2676 		max = (port->uartclk + tolerance) / 4;
2677 	} else {
2678 		min = port->uartclk / 16 / UART_DIV_MAX;
2679 		max = (port->uartclk + tolerance) / 16;
2680 	}
2681 
2682 	/*
2683 	 * Ask the core to calculate the divisor for us.
2684 	 * Allow 1% tolerance at the upper limit so uart clks marginally
2685 	 * slower than nominal still match standard baud rates without
2686 	 * causing transmission errors.
2687 	 */
2688 	return uart_get_baud_rate(port, termios, old, min, max);
2689 }
2690 
2691 /*
2692  * Note in order to avoid the tty port mutex deadlock don't use the next method
2693  * within the uart port callbacks. Primarily it's supposed to be utilized to
2694  * handle a sudden reference clock rate change.
2695  */
2696 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2697 {
2698 	struct uart_8250_port *up = up_to_u8250p(port);
2699 	struct tty_port *tport = &port->state->port;
2700 	unsigned int baud, quot, frac = 0;
2701 	struct ktermios *termios;
2702 	struct tty_struct *tty;
2703 	unsigned long flags;
2704 
2705 	tty = tty_port_tty_get(tport);
2706 	if (!tty) {
2707 		mutex_lock(&tport->mutex);
2708 		port->uartclk = uartclk;
2709 		mutex_unlock(&tport->mutex);
2710 		return;
2711 	}
2712 
2713 	down_write(&tty->termios_rwsem);
2714 	mutex_lock(&tport->mutex);
2715 
2716 	if (port->uartclk == uartclk)
2717 		goto out_unlock;
2718 
2719 	port->uartclk = uartclk;
2720 
2721 	if (!tty_port_initialized(tport))
2722 		goto out_unlock;
2723 
2724 	termios = &tty->termios;
2725 
2726 	baud = serial8250_get_baud_rate(port, termios, NULL);
2727 	quot = serial8250_get_divisor(port, baud, &frac);
2728 
2729 	serial8250_rpm_get(up);
2730 	spin_lock_irqsave(&port->lock, flags);
2731 
2732 	uart_update_timeout(port, termios->c_cflag, baud);
2733 
2734 	serial8250_set_divisor(port, baud, quot, frac);
2735 	serial_port_out(port, UART_LCR, up->lcr);
2736 
2737 	spin_unlock_irqrestore(&port->lock, flags);
2738 	serial8250_rpm_put(up);
2739 
2740 out_unlock:
2741 	mutex_unlock(&tport->mutex);
2742 	up_write(&tty->termios_rwsem);
2743 	tty_kref_put(tty);
2744 }
2745 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2746 
2747 void
2748 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2749 			  struct ktermios *old)
2750 {
2751 	struct uart_8250_port *up = up_to_u8250p(port);
2752 	unsigned char cval;
2753 	unsigned long flags;
2754 	unsigned int baud, quot, frac = 0;
2755 
2756 	if (up->capabilities & UART_CAP_MINI) {
2757 		termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2758 		if ((termios->c_cflag & CSIZE) == CS5 ||
2759 		    (termios->c_cflag & CSIZE) == CS6)
2760 			termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2761 	}
2762 	cval = serial8250_compute_lcr(up, termios->c_cflag);
2763 
2764 	baud = serial8250_get_baud_rate(port, termios, old);
2765 	quot = serial8250_get_divisor(port, baud, &frac);
2766 
2767 	/*
2768 	 * Ok, we're now changing the port state.  Do it with
2769 	 * interrupts disabled.
2770 	 */
2771 	serial8250_rpm_get(up);
2772 	spin_lock_irqsave(&port->lock, flags);
2773 
2774 	up->lcr = cval;					/* Save computed LCR */
2775 
2776 	if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2777 		/* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2778 		if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2779 			up->fcr &= ~UART_FCR_TRIGGER_MASK;
2780 			up->fcr |= UART_FCR_TRIGGER_1;
2781 		}
2782 	}
2783 
2784 	/*
2785 	 * MCR-based auto flow control.  When AFE is enabled, RTS will be
2786 	 * deasserted when the receive FIFO contains more characters than
2787 	 * the trigger, or the MCR RTS bit is cleared.
2788 	 */
2789 	if (up->capabilities & UART_CAP_AFE) {
2790 		up->mcr &= ~UART_MCR_AFE;
2791 		if (termios->c_cflag & CRTSCTS)
2792 			up->mcr |= UART_MCR_AFE;
2793 	}
2794 
2795 	/*
2796 	 * Update the per-port timeout.
2797 	 */
2798 	uart_update_timeout(port, termios->c_cflag, baud);
2799 
2800 	port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2801 	if (termios->c_iflag & INPCK)
2802 		port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2803 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2804 		port->read_status_mask |= UART_LSR_BI;
2805 
2806 	/*
2807 	 * Characteres to ignore
2808 	 */
2809 	port->ignore_status_mask = 0;
2810 	if (termios->c_iflag & IGNPAR)
2811 		port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2812 	if (termios->c_iflag & IGNBRK) {
2813 		port->ignore_status_mask |= UART_LSR_BI;
2814 		/*
2815 		 * If we're ignoring parity and break indicators,
2816 		 * ignore overruns too (for real raw support).
2817 		 */
2818 		if (termios->c_iflag & IGNPAR)
2819 			port->ignore_status_mask |= UART_LSR_OE;
2820 	}
2821 
2822 	/*
2823 	 * ignore all characters if CREAD is not set
2824 	 */
2825 	if ((termios->c_cflag & CREAD) == 0)
2826 		port->ignore_status_mask |= UART_LSR_DR;
2827 
2828 	/*
2829 	 * CTS flow control flag and modem status interrupts
2830 	 */
2831 	up->ier &= ~UART_IER_MSI;
2832 	if (!(up->bugs & UART_BUG_NOMSR) &&
2833 			UART_ENABLE_MS(&up->port, termios->c_cflag))
2834 		up->ier |= UART_IER_MSI;
2835 	if (up->capabilities & UART_CAP_UUE)
2836 		up->ier |= UART_IER_UUE;
2837 	if (up->capabilities & UART_CAP_RTOIE)
2838 		up->ier |= UART_IER_RTOIE;
2839 
2840 	serial_port_out(port, UART_IER, up->ier);
2841 
2842 	if (up->capabilities & UART_CAP_EFR) {
2843 		unsigned char efr = 0;
2844 		/*
2845 		 * TI16C752/Startech hardware flow control.  FIXME:
2846 		 * - TI16C752 requires control thresholds to be set.
2847 		 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2848 		 */
2849 		if (termios->c_cflag & CRTSCTS)
2850 			efr |= UART_EFR_CTS;
2851 
2852 		serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2853 		if (port->flags & UPF_EXAR_EFR)
2854 			serial_port_out(port, UART_XR_EFR, efr);
2855 		else
2856 			serial_port_out(port, UART_EFR, efr);
2857 	}
2858 
2859 	serial8250_set_divisor(port, baud, quot, frac);
2860 
2861 	/*
2862 	 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2863 	 * is written without DLAB set, this mode will be disabled.
2864 	 */
2865 	if (port->type == PORT_16750)
2866 		serial_port_out(port, UART_FCR, up->fcr);
2867 
2868 	serial_port_out(port, UART_LCR, up->lcr);	/* reset DLAB */
2869 	if (port->type != PORT_16750) {
2870 		/* emulated UARTs (Lucent Venus 167x) need two steps */
2871 		if (up->fcr & UART_FCR_ENABLE_FIFO)
2872 			serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2873 		serial_port_out(port, UART_FCR, up->fcr);	/* set fcr */
2874 	}
2875 	serial8250_set_mctrl(port, port->mctrl);
2876 	spin_unlock_irqrestore(&port->lock, flags);
2877 	serial8250_rpm_put(up);
2878 
2879 	/* Don't rewrite B0 */
2880 	if (tty_termios_baud_rate(termios))
2881 		tty_termios_encode_baud_rate(termios, baud, baud);
2882 }
2883 EXPORT_SYMBOL(serial8250_do_set_termios);
2884 
2885 static void
2886 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2887 		       struct ktermios *old)
2888 {
2889 	if (port->set_termios)
2890 		port->set_termios(port, termios, old);
2891 	else
2892 		serial8250_do_set_termios(port, termios, old);
2893 }
2894 
2895 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2896 {
2897 	if (termios->c_line == N_PPS) {
2898 		port->flags |= UPF_HARDPPS_CD;
2899 		spin_lock_irq(&port->lock);
2900 		serial8250_enable_ms(port);
2901 		spin_unlock_irq(&port->lock);
2902 	} else {
2903 		port->flags &= ~UPF_HARDPPS_CD;
2904 		if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2905 			spin_lock_irq(&port->lock);
2906 			serial8250_disable_ms(port);
2907 			spin_unlock_irq(&port->lock);
2908 		}
2909 	}
2910 }
2911 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2912 
2913 static void
2914 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2915 {
2916 	if (port->set_ldisc)
2917 		port->set_ldisc(port, termios);
2918 	else
2919 		serial8250_do_set_ldisc(port, termios);
2920 }
2921 
2922 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2923 		      unsigned int oldstate)
2924 {
2925 	struct uart_8250_port *p = up_to_u8250p(port);
2926 
2927 	serial8250_set_sleep(p, state != 0);
2928 }
2929 EXPORT_SYMBOL(serial8250_do_pm);
2930 
2931 static void
2932 serial8250_pm(struct uart_port *port, unsigned int state,
2933 	      unsigned int oldstate)
2934 {
2935 	if (port->pm)
2936 		port->pm(port, state, oldstate);
2937 	else
2938 		serial8250_do_pm(port, state, oldstate);
2939 }
2940 
2941 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2942 {
2943 	if (pt->port.mapsize)
2944 		return pt->port.mapsize;
2945 	if (pt->port.iotype == UPIO_AU) {
2946 		if (pt->port.type == PORT_RT2880)
2947 			return 0x100;
2948 		return 0x1000;
2949 	}
2950 	if (is_omap1_8250(pt))
2951 		return 0x16 << pt->port.regshift;
2952 
2953 	return 8 << pt->port.regshift;
2954 }
2955 
2956 /*
2957  * Resource handling.
2958  */
2959 static int serial8250_request_std_resource(struct uart_8250_port *up)
2960 {
2961 	unsigned int size = serial8250_port_size(up);
2962 	struct uart_port *port = &up->port;
2963 	int ret = 0;
2964 
2965 	switch (port->iotype) {
2966 	case UPIO_AU:
2967 	case UPIO_TSI:
2968 	case UPIO_MEM32:
2969 	case UPIO_MEM32BE:
2970 	case UPIO_MEM16:
2971 	case UPIO_MEM:
2972 		if (!port->mapbase)
2973 			break;
2974 
2975 		if (!request_mem_region(port->mapbase, size, "serial")) {
2976 			ret = -EBUSY;
2977 			break;
2978 		}
2979 
2980 		if (port->flags & UPF_IOREMAP) {
2981 			port->membase = ioremap(port->mapbase, size);
2982 			if (!port->membase) {
2983 				release_mem_region(port->mapbase, size);
2984 				ret = -ENOMEM;
2985 			}
2986 		}
2987 		break;
2988 
2989 	case UPIO_HUB6:
2990 	case UPIO_PORT:
2991 		if (!request_region(port->iobase, size, "serial"))
2992 			ret = -EBUSY;
2993 		break;
2994 	}
2995 	return ret;
2996 }
2997 
2998 static void serial8250_release_std_resource(struct uart_8250_port *up)
2999 {
3000 	unsigned int size = serial8250_port_size(up);
3001 	struct uart_port *port = &up->port;
3002 
3003 	switch (port->iotype) {
3004 	case UPIO_AU:
3005 	case UPIO_TSI:
3006 	case UPIO_MEM32:
3007 	case UPIO_MEM32BE:
3008 	case UPIO_MEM16:
3009 	case UPIO_MEM:
3010 		if (!port->mapbase)
3011 			break;
3012 
3013 		if (port->flags & UPF_IOREMAP) {
3014 			iounmap(port->membase);
3015 			port->membase = NULL;
3016 		}
3017 
3018 		release_mem_region(port->mapbase, size);
3019 		break;
3020 
3021 	case UPIO_HUB6:
3022 	case UPIO_PORT:
3023 		release_region(port->iobase, size);
3024 		break;
3025 	}
3026 }
3027 
3028 static void serial8250_release_port(struct uart_port *port)
3029 {
3030 	struct uart_8250_port *up = up_to_u8250p(port);
3031 
3032 	serial8250_release_std_resource(up);
3033 }
3034 
3035 static int serial8250_request_port(struct uart_port *port)
3036 {
3037 	struct uart_8250_port *up = up_to_u8250p(port);
3038 
3039 	return serial8250_request_std_resource(up);
3040 }
3041 
3042 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3043 {
3044 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3045 	unsigned char bytes;
3046 
3047 	bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3048 
3049 	return bytes ? bytes : -EOPNOTSUPP;
3050 }
3051 
3052 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3053 {
3054 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3055 	int i;
3056 
3057 	if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3058 		return -EOPNOTSUPP;
3059 
3060 	for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3061 		if (bytes < conf_type->rxtrig_bytes[i])
3062 			/* Use the nearest lower value */
3063 			return (--i) << UART_FCR_R_TRIG_SHIFT;
3064 	}
3065 
3066 	return UART_FCR_R_TRIG_11;
3067 }
3068 
3069 static int do_get_rxtrig(struct tty_port *port)
3070 {
3071 	struct uart_state *state = container_of(port, struct uart_state, port);
3072 	struct uart_port *uport = state->uart_port;
3073 	struct uart_8250_port *up = up_to_u8250p(uport);
3074 
3075 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3076 		return -EINVAL;
3077 
3078 	return fcr_get_rxtrig_bytes(up);
3079 }
3080 
3081 static int do_serial8250_get_rxtrig(struct tty_port *port)
3082 {
3083 	int rxtrig_bytes;
3084 
3085 	mutex_lock(&port->mutex);
3086 	rxtrig_bytes = do_get_rxtrig(port);
3087 	mutex_unlock(&port->mutex);
3088 
3089 	return rxtrig_bytes;
3090 }
3091 
3092 static ssize_t rx_trig_bytes_show(struct device *dev,
3093 	struct device_attribute *attr, char *buf)
3094 {
3095 	struct tty_port *port = dev_get_drvdata(dev);
3096 	int rxtrig_bytes;
3097 
3098 	rxtrig_bytes = do_serial8250_get_rxtrig(port);
3099 	if (rxtrig_bytes < 0)
3100 		return rxtrig_bytes;
3101 
3102 	return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3103 }
3104 
3105 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3106 {
3107 	struct uart_state *state = container_of(port, struct uart_state, port);
3108 	struct uart_port *uport = state->uart_port;
3109 	struct uart_8250_port *up = up_to_u8250p(uport);
3110 	int rxtrig;
3111 
3112 	if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3113 	    up->fifo_bug)
3114 		return -EINVAL;
3115 
3116 	rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3117 	if (rxtrig < 0)
3118 		return rxtrig;
3119 
3120 	serial8250_clear_fifos(up);
3121 	up->fcr &= ~UART_FCR_TRIGGER_MASK;
3122 	up->fcr |= (unsigned char)rxtrig;
3123 	serial_out(up, UART_FCR, up->fcr);
3124 	return 0;
3125 }
3126 
3127 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3128 {
3129 	int ret;
3130 
3131 	mutex_lock(&port->mutex);
3132 	ret = do_set_rxtrig(port, bytes);
3133 	mutex_unlock(&port->mutex);
3134 
3135 	return ret;
3136 }
3137 
3138 static ssize_t rx_trig_bytes_store(struct device *dev,
3139 	struct device_attribute *attr, const char *buf, size_t count)
3140 {
3141 	struct tty_port *port = dev_get_drvdata(dev);
3142 	unsigned char bytes;
3143 	int ret;
3144 
3145 	if (!count)
3146 		return -EINVAL;
3147 
3148 	ret = kstrtou8(buf, 10, &bytes);
3149 	if (ret < 0)
3150 		return ret;
3151 
3152 	ret = do_serial8250_set_rxtrig(port, bytes);
3153 	if (ret < 0)
3154 		return ret;
3155 
3156 	return count;
3157 }
3158 
3159 static DEVICE_ATTR_RW(rx_trig_bytes);
3160 
3161 static struct attribute *serial8250_dev_attrs[] = {
3162 	&dev_attr_rx_trig_bytes.attr,
3163 	NULL
3164 };
3165 
3166 static struct attribute_group serial8250_dev_attr_group = {
3167 	.attrs = serial8250_dev_attrs,
3168 };
3169 
3170 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3171 {
3172 	const struct serial8250_config *conf_type = &uart_config[up->port.type];
3173 
3174 	if (conf_type->rxtrig_bytes[0])
3175 		up->port.attr_group = &serial8250_dev_attr_group;
3176 }
3177 
3178 static void serial8250_config_port(struct uart_port *port, int flags)
3179 {
3180 	struct uart_8250_port *up = up_to_u8250p(port);
3181 	int ret;
3182 
3183 	/*
3184 	 * Find the region that we can probe for.  This in turn
3185 	 * tells us whether we can probe for the type of port.
3186 	 */
3187 	ret = serial8250_request_std_resource(up);
3188 	if (ret < 0)
3189 		return;
3190 
3191 	if (port->iotype != up->cur_iotype)
3192 		set_io_from_upio(port);
3193 
3194 	if (flags & UART_CONFIG_TYPE)
3195 		autoconfig(up);
3196 
3197 	if (port->rs485.flags & SER_RS485_ENABLED)
3198 		port->rs485_config(port, &port->rs485);
3199 
3200 	/* if access method is AU, it is a 16550 with a quirk */
3201 	if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3202 		up->bugs |= UART_BUG_NOMSR;
3203 
3204 	/* HW bugs may trigger IRQ while IIR == NO_INT */
3205 	if (port->type == PORT_TEGRA)
3206 		up->bugs |= UART_BUG_NOMSR;
3207 
3208 	if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3209 		autoconfig_irq(up);
3210 
3211 	if (port->type == PORT_UNKNOWN)
3212 		serial8250_release_std_resource(up);
3213 
3214 	register_dev_spec_attr_grp(up);
3215 	up->fcr = uart_config[up->port.type].fcr;
3216 }
3217 
3218 static int
3219 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3220 {
3221 	if (ser->irq >= nr_irqs || ser->irq < 0 ||
3222 	    ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3223 	    ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3224 	    ser->type == PORT_STARTECH)
3225 		return -EINVAL;
3226 	return 0;
3227 }
3228 
3229 static const char *serial8250_type(struct uart_port *port)
3230 {
3231 	int type = port->type;
3232 
3233 	if (type >= ARRAY_SIZE(uart_config))
3234 		type = 0;
3235 	return uart_config[type].name;
3236 }
3237 
3238 static const struct uart_ops serial8250_pops = {
3239 	.tx_empty	= serial8250_tx_empty,
3240 	.set_mctrl	= serial8250_set_mctrl,
3241 	.get_mctrl	= serial8250_get_mctrl,
3242 	.stop_tx	= serial8250_stop_tx,
3243 	.start_tx	= serial8250_start_tx,
3244 	.throttle	= serial8250_throttle,
3245 	.unthrottle	= serial8250_unthrottle,
3246 	.stop_rx	= serial8250_stop_rx,
3247 	.enable_ms	= serial8250_enable_ms,
3248 	.break_ctl	= serial8250_break_ctl,
3249 	.startup	= serial8250_startup,
3250 	.shutdown	= serial8250_shutdown,
3251 	.set_termios	= serial8250_set_termios,
3252 	.set_ldisc	= serial8250_set_ldisc,
3253 	.pm		= serial8250_pm,
3254 	.type		= serial8250_type,
3255 	.release_port	= serial8250_release_port,
3256 	.request_port	= serial8250_request_port,
3257 	.config_port	= serial8250_config_port,
3258 	.verify_port	= serial8250_verify_port,
3259 #ifdef CONFIG_CONSOLE_POLL
3260 	.poll_get_char = serial8250_get_poll_char,
3261 	.poll_put_char = serial8250_put_poll_char,
3262 #endif
3263 };
3264 
3265 void serial8250_init_port(struct uart_8250_port *up)
3266 {
3267 	struct uart_port *port = &up->port;
3268 
3269 	spin_lock_init(&port->lock);
3270 	port->ops = &serial8250_pops;
3271 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3272 
3273 	up->cur_iotype = 0xFF;
3274 }
3275 EXPORT_SYMBOL_GPL(serial8250_init_port);
3276 
3277 void serial8250_set_defaults(struct uart_8250_port *up)
3278 {
3279 	struct uart_port *port = &up->port;
3280 
3281 	if (up->port.flags & UPF_FIXED_TYPE) {
3282 		unsigned int type = up->port.type;
3283 
3284 		if (!up->port.fifosize)
3285 			up->port.fifosize = uart_config[type].fifo_size;
3286 		if (!up->tx_loadsz)
3287 			up->tx_loadsz = uart_config[type].tx_loadsz;
3288 		if (!up->capabilities)
3289 			up->capabilities = uart_config[type].flags;
3290 	}
3291 
3292 	set_io_from_upio(port);
3293 
3294 	/* default dma handlers */
3295 	if (up->dma) {
3296 		if (!up->dma->tx_dma)
3297 			up->dma->tx_dma = serial8250_tx_dma;
3298 		if (!up->dma->rx_dma)
3299 			up->dma->rx_dma = serial8250_rx_dma;
3300 	}
3301 }
3302 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3303 
3304 #ifdef CONFIG_SERIAL_8250_CONSOLE
3305 
3306 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3307 {
3308 	struct uart_8250_port *up = up_to_u8250p(port);
3309 
3310 	wait_for_xmitr(up, UART_LSR_THRE);
3311 	serial_port_out(port, UART_TX, ch);
3312 }
3313 
3314 /*
3315  *	Restore serial console when h/w power-off detected
3316  */
3317 static void serial8250_console_restore(struct uart_8250_port *up)
3318 {
3319 	struct uart_port *port = &up->port;
3320 	struct ktermios termios;
3321 	unsigned int baud, quot, frac = 0;
3322 
3323 	termios.c_cflag = port->cons->cflag;
3324 	if (port->state->port.tty && termios.c_cflag == 0)
3325 		termios.c_cflag = port->state->port.tty->termios.c_cflag;
3326 
3327 	baud = serial8250_get_baud_rate(port, &termios, NULL);
3328 	quot = serial8250_get_divisor(port, baud, &frac);
3329 
3330 	serial8250_set_divisor(port, baud, quot, frac);
3331 	serial_port_out(port, UART_LCR, up->lcr);
3332 	serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
3333 }
3334 
3335 /*
3336  *	Print a string to the serial port trying not to disturb
3337  *	any possible real use of the port...
3338  *
3339  *	The console_lock must be held when we get here.
3340  *
3341  *	Doing runtime PM is really a bad idea for the kernel console.
3342  *	Thus, we assume the function is called when device is powered up.
3343  */
3344 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3345 			      unsigned int count)
3346 {
3347 	struct uart_8250_em485 *em485 = up->em485;
3348 	struct uart_port *port = &up->port;
3349 	unsigned long flags;
3350 	unsigned int ier;
3351 	int locked = 1;
3352 
3353 	touch_nmi_watchdog();
3354 
3355 	if (oops_in_progress)
3356 		locked = spin_trylock_irqsave(&port->lock, flags);
3357 	else
3358 		spin_lock_irqsave(&port->lock, flags);
3359 
3360 	/*
3361 	 *	First save the IER then disable the interrupts
3362 	 */
3363 	ier = serial_port_in(port, UART_IER);
3364 
3365 	if (up->capabilities & UART_CAP_UUE)
3366 		serial_port_out(port, UART_IER, UART_IER_UUE);
3367 	else
3368 		serial_port_out(port, UART_IER, 0);
3369 
3370 	/* check scratch reg to see if port powered off during system sleep */
3371 	if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3372 		serial8250_console_restore(up);
3373 		up->canary = 0;
3374 	}
3375 
3376 	if (em485) {
3377 		if (em485->tx_stopped)
3378 			up->rs485_start_tx(up);
3379 		mdelay(port->rs485.delay_rts_before_send);
3380 	}
3381 
3382 	uart_console_write(port, s, count, serial8250_console_putchar);
3383 
3384 	/*
3385 	 *	Finally, wait for transmitter to become empty
3386 	 *	and restore the IER
3387 	 */
3388 	wait_for_xmitr(up, BOTH_EMPTY);
3389 
3390 	if (em485) {
3391 		mdelay(port->rs485.delay_rts_after_send);
3392 		if (em485->tx_stopped)
3393 			up->rs485_stop_tx(up);
3394 	}
3395 
3396 	serial_port_out(port, UART_IER, ier);
3397 
3398 	/*
3399 	 *	The receive handling will happen properly because the
3400 	 *	receive ready bit will still be set; it is not cleared
3401 	 *	on read.  However, modem control will not, we must
3402 	 *	call it if we have saved something in the saved flags
3403 	 *	while processing with interrupts off.
3404 	 */
3405 	if (up->msr_saved_flags)
3406 		serial8250_modem_status(up);
3407 
3408 	if (locked)
3409 		spin_unlock_irqrestore(&port->lock, flags);
3410 }
3411 
3412 static unsigned int probe_baud(struct uart_port *port)
3413 {
3414 	unsigned char lcr, dll, dlm;
3415 	unsigned int quot;
3416 
3417 	lcr = serial_port_in(port, UART_LCR);
3418 	serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3419 	dll = serial_port_in(port, UART_DLL);
3420 	dlm = serial_port_in(port, UART_DLM);
3421 	serial_port_out(port, UART_LCR, lcr);
3422 
3423 	quot = (dlm << 8) | dll;
3424 	return (port->uartclk / 16) / quot;
3425 }
3426 
3427 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3428 {
3429 	int baud = 9600;
3430 	int bits = 8;
3431 	int parity = 'n';
3432 	int flow = 'n';
3433 	int ret;
3434 
3435 	if (!port->iobase && !port->membase)
3436 		return -ENODEV;
3437 
3438 	if (options)
3439 		uart_parse_options(options, &baud, &parity, &bits, &flow);
3440 	else if (probe)
3441 		baud = probe_baud(port);
3442 
3443 	ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3444 	if (ret)
3445 		return ret;
3446 
3447 	if (port->dev)
3448 		pm_runtime_get_sync(port->dev);
3449 
3450 	return 0;
3451 }
3452 
3453 int serial8250_console_exit(struct uart_port *port)
3454 {
3455 	if (port->dev)
3456 		pm_runtime_put_sync(port->dev);
3457 
3458 	return 0;
3459 }
3460 
3461 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3462 
3463 MODULE_LICENSE("GPL");
3464