1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57 }; 58 59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 60 61 static const struct pci_device_id pci_use_msi[] = { 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 69 PCI_ANY_ID, PCI_ANY_ID) }, 70 { } 71 }; 72 73 static int pci_default_setup(struct serial_private*, 74 const struct pciserial_board*, struct uart_8250_port *, int); 75 76 static void moan_device(const char *str, struct pci_dev *dev) 77 { 78 pci_err(dev, "%s\n" 79 "Please send the output of lspci -vv, this\n" 80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 81 "manufacturer and name of serial board or\n" 82 "modem board to <linux-serial@vger.kernel.org>.\n", 83 str, dev->vendor, dev->device, 84 dev->subsystem_vendor, dev->subsystem_device); 85 } 86 87 static int 88 setup_port(struct serial_private *priv, struct uart_8250_port *port, 89 u8 bar, unsigned int offset, int regshift) 90 { 91 struct pci_dev *dev = priv->dev; 92 93 if (bar >= PCI_STD_NUM_BARS) 94 return -EINVAL; 95 96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 98 return -ENOMEM; 99 100 port->port.iotype = UPIO_MEM; 101 port->port.iobase = 0; 102 port->port.mapbase = pci_resource_start(dev, bar) + offset; 103 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 104 port->port.regshift = regshift; 105 } else { 106 port->port.iotype = UPIO_PORT; 107 port->port.iobase = pci_resource_start(dev, bar) + offset; 108 port->port.mapbase = 0; 109 port->port.membase = NULL; 110 port->port.regshift = 0; 111 } 112 return 0; 113 } 114 115 /* 116 * ADDI-DATA GmbH communication cards <info@addi-data.com> 117 */ 118 static int addidata_apci7800_setup(struct serial_private *priv, 119 const struct pciserial_board *board, 120 struct uart_8250_port *port, int idx) 121 { 122 unsigned int bar = 0, offset = board->first_offset; 123 bar = FL_GET_BASE(board->flags); 124 125 if (idx < 2) { 126 offset += idx * board->uart_offset; 127 } else if ((idx >= 2) && (idx < 4)) { 128 bar += 1; 129 offset += ((idx - 2) * board->uart_offset); 130 } else if ((idx >= 4) && (idx < 6)) { 131 bar += 2; 132 offset += ((idx - 4) * board->uart_offset); 133 } else if (idx >= 6) { 134 bar += 3; 135 offset += ((idx - 6) * board->uart_offset); 136 } 137 138 return setup_port(priv, port, bar, offset, board->reg_shift); 139 } 140 141 /* 142 * AFAVLAB uses a different mixture of BARs and offsets 143 * Not that ugly ;) -- HW 144 */ 145 static int 146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 147 struct uart_8250_port *port, int idx) 148 { 149 unsigned int bar, offset = board->first_offset; 150 151 bar = FL_GET_BASE(board->flags); 152 if (idx < 4) 153 bar += idx; 154 else { 155 bar = 4; 156 offset += (idx - 4) * board->uart_offset; 157 } 158 159 return setup_port(priv, port, bar, offset, board->reg_shift); 160 } 161 162 /* 163 * HP's Remote Management Console. The Diva chip came in several 164 * different versions. N-class, L2000 and A500 have two Diva chips, each 165 * with 3 UARTs (the third UART on the second chip is unused). Superdome 166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 167 * one Diva chip, but it has been expanded to 5 UARTs. 168 */ 169 static int pci_hp_diva_init(struct pci_dev *dev) 170 { 171 int rc = 0; 172 173 switch (dev->subsystem_device) { 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 177 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 178 rc = 3; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 181 rc = 2; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 184 rc = 4; 185 break; 186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 188 rc = 1; 189 break; 190 } 191 192 return rc; 193 } 194 195 /* 196 * HP's Diva chip puts the 4th/5th serial port further out, and 197 * some serial ports are supposed to be hidden on certain models. 198 */ 199 static int 200 pci_hp_diva_setup(struct serial_private *priv, 201 const struct pciserial_board *board, 202 struct uart_8250_port *port, int idx) 203 { 204 unsigned int offset = board->first_offset; 205 unsigned int bar = FL_GET_BASE(board->flags); 206 207 switch (priv->dev->subsystem_device) { 208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 209 if (idx == 3) 210 idx++; 211 break; 212 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 213 if (idx > 0) 214 idx++; 215 if (idx > 2) 216 idx++; 217 break; 218 } 219 if (idx > 2) 220 offset = 0x18; 221 222 offset += idx * board->uart_offset; 223 224 return setup_port(priv, port, bar, offset, board->reg_shift); 225 } 226 227 /* 228 * Added for EKF Intel i960 serial boards 229 */ 230 static int pci_inteli960ni_init(struct pci_dev *dev) 231 { 232 u32 oldval; 233 234 if (!(dev->subsystem_device & 0x1000)) 235 return -ENODEV; 236 237 /* is firmware started? */ 238 pci_read_config_dword(dev, 0x44, &oldval); 239 if (oldval == 0x00001000L) { /* RESET value */ 240 pci_dbg(dev, "Local i960 firmware missing\n"); 241 return -ENODEV; 242 } 243 return 0; 244 } 245 246 /* 247 * Some PCI serial cards using the PLX 9050 PCI interface chip require 248 * that the card interrupt be explicitly enabled or disabled. This 249 * seems to be mainly needed on card using the PLX which also use I/O 250 * mapped memory. 251 */ 252 static int pci_plx9050_init(struct pci_dev *dev) 253 { 254 u8 irq_config; 255 void __iomem *p; 256 257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 258 moan_device("no memory in bar 0", dev); 259 return 0; 260 } 261 262 irq_config = 0x41; 263 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 265 irq_config = 0x43; 266 267 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 269 /* 270 * As the megawolf cards have the int pins active 271 * high, and have 2 UART chips, both ints must be 272 * enabled on the 9050. Also, the UARTS are set in 273 * 16450 mode by default, so we have to enable the 274 * 16C950 'enhanced' mode so that we can use the 275 * deep FIFOs 276 */ 277 irq_config = 0x5b; 278 /* 279 * enable/disable interrupts 280 */ 281 p = ioremap(pci_resource_start(dev, 0), 0x80); 282 if (p == NULL) 283 return -ENOMEM; 284 writel(irq_config, p + 0x4c); 285 286 /* 287 * Read the register back to ensure that it took effect. 288 */ 289 readl(p + 0x4c); 290 iounmap(p); 291 292 return 0; 293 } 294 295 static void pci_plx9050_exit(struct pci_dev *dev) 296 { 297 u8 __iomem *p; 298 299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 300 return; 301 302 /* 303 * disable interrupts 304 */ 305 p = ioremap(pci_resource_start(dev, 0), 0x80); 306 if (p != NULL) { 307 writel(0, p + 0x4c); 308 309 /* 310 * Read the register back to ensure that it took effect. 311 */ 312 readl(p + 0x4c); 313 iounmap(p); 314 } 315 } 316 317 #define NI8420_INT_ENABLE_REG 0x38 318 #define NI8420_INT_ENABLE_BIT 0x2000 319 320 static void pci_ni8420_exit(struct pci_dev *dev) 321 { 322 void __iomem *p; 323 unsigned int bar = 0; 324 325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 326 moan_device("no memory in bar", dev); 327 return; 328 } 329 330 p = pci_ioremap_bar(dev, bar); 331 if (p == NULL) 332 return; 333 334 /* Disable the CPU Interrupt */ 335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 336 p + NI8420_INT_ENABLE_REG); 337 iounmap(p); 338 } 339 340 341 /* MITE registers */ 342 #define MITE_IOWBSR1 0xc4 343 #define MITE_IOWCR1 0xf4 344 #define MITE_LCIMR1 0x08 345 #define MITE_LCIMR2 0x10 346 347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 348 349 static void pci_ni8430_exit(struct pci_dev *dev) 350 { 351 void __iomem *p; 352 unsigned int bar = 0; 353 354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 355 moan_device("no memory in bar", dev); 356 return; 357 } 358 359 p = pci_ioremap_bar(dev, bar); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366 } 367 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369 static int 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372 { 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387 } 388 389 /* 390 * This does initialization for PMC OCTALPRO cards: 391 * maps the device memory, resets the UARTs (needed, bc 392 * if the module is removed and inserted again, the card 393 * is in the sleep mode) and enables global interrupt. 394 */ 395 396 /* global control register offset for SBS PMC-OctalPro */ 397 #define OCT_REG_CR_OFF 0x500 398 399 static int sbs_init(struct pci_dev *dev) 400 { 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417 } 418 419 /* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423 static void sbs_exit(struct pci_dev *dev) 424 { 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432 } 433 434 /* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464 static int pci_siig10x_init(struct pci_dev *dev) 465 { 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489 } 490 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494 static int pci_siig20x_init(struct pci_dev *dev) 495 { 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509 } 510 511 static int pci_siig_init(struct pci_dev *dev) 512 { 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522 } 523 524 static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527 { 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536 } 537 538 /* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543 static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545 }; 546 547 static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553 }; 554 555 static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560 }; 561 562 static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565 }; 566 567 static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570 } timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575 }; 576 577 /* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583 static int pci_timedia_probe(struct pci_dev *dev) 584 { 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 591 dev->subsystem_device); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 static int pci_timedia_init(struct pci_dev *dev) 599 { 600 const unsigned short *ids; 601 int i, j; 602 603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 604 ids = timedia_data[i].ids; 605 for (j = 0; ids[j]; j++) 606 if (dev->subsystem_device == ids[j]) 607 return timedia_data[i].num; 608 } 609 return 0; 610 } 611 612 /* 613 * Timedia/SUNIX uses a mixture of BARs and offsets 614 * Ugh, this is ugly as all hell --- TYT 615 */ 616 static int 617 pci_timedia_setup(struct serial_private *priv, 618 const struct pciserial_board *board, 619 struct uart_8250_port *port, int idx) 620 { 621 unsigned int bar = 0, offset = board->first_offset; 622 623 switch (idx) { 624 case 0: 625 bar = 0; 626 break; 627 case 1: 628 offset = board->uart_offset; 629 bar = 0; 630 break; 631 case 2: 632 bar = 1; 633 break; 634 case 3: 635 offset = board->uart_offset; 636 fallthrough; 637 case 4: /* BAR 2 */ 638 case 5: /* BAR 3 */ 639 case 6: /* BAR 4 */ 640 case 7: /* BAR 5 */ 641 bar = idx - 2; 642 } 643 644 return setup_port(priv, port, bar, offset, board->reg_shift); 645 } 646 647 /* 648 * Some Titan cards are also a little weird 649 */ 650 static int 651 titan_400l_800l_setup(struct serial_private *priv, 652 const struct pciserial_board *board, 653 struct uart_8250_port *port, int idx) 654 { 655 unsigned int bar, offset = board->first_offset; 656 657 switch (idx) { 658 case 0: 659 bar = 1; 660 break; 661 case 1: 662 bar = 2; 663 break; 664 default: 665 bar = 4; 666 offset = (idx - 2) * board->uart_offset; 667 } 668 669 return setup_port(priv, port, bar, offset, board->reg_shift); 670 } 671 672 static int pci_xircom_init(struct pci_dev *dev) 673 { 674 msleep(100); 675 return 0; 676 } 677 678 static int pci_ni8420_init(struct pci_dev *dev) 679 { 680 void __iomem *p; 681 unsigned int bar = 0; 682 683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 684 moan_device("no memory in bar", dev); 685 return 0; 686 } 687 688 p = pci_ioremap_bar(dev, bar); 689 if (p == NULL) 690 return -ENOMEM; 691 692 /* Enable CPU Interrupt */ 693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 694 p + NI8420_INT_ENABLE_REG); 695 696 iounmap(p); 697 return 0; 698 } 699 700 #define MITE_IOWBSR1_WSIZE 0xa 701 #define MITE_IOWBSR1_WIN_OFFSET 0x800 702 #define MITE_IOWBSR1_WENAB (1 << 7) 703 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 706 707 static int pci_ni8430_init(struct pci_dev *dev) 708 { 709 void __iomem *p; 710 struct pci_bus_region region; 711 u32 device_window; 712 unsigned int bar = 0; 713 714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 715 moan_device("no memory in bar", dev); 716 return 0; 717 } 718 719 p = pci_ioremap_bar(dev, bar); 720 if (p == NULL) 721 return -ENOMEM; 722 723 /* 724 * Set device window address and size in BAR0, while acknowledging that 725 * the resource structure may contain a translated address that differs 726 * from the address the device responds to. 727 */ 728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 731 writel(device_window, p + MITE_IOWBSR1); 732 733 /* Set window access to go to RAMSEL IO address space */ 734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 735 p + MITE_IOWCR1); 736 737 /* Enable IO Bus Interrupt 0 */ 738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 739 740 /* Enable CPU Interrupt */ 741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 742 743 iounmap(p); 744 return 0; 745 } 746 747 /* UART Port Control Register */ 748 #define NI8430_PORTCON 0x0f 749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 750 751 static int 752 pci_ni8430_setup(struct serial_private *priv, 753 const struct pciserial_board *board, 754 struct uart_8250_port *port, int idx) 755 { 756 struct pci_dev *dev = priv->dev; 757 void __iomem *p; 758 unsigned int bar, offset = board->first_offset; 759 760 if (idx >= board->num_ports) 761 return 1; 762 763 bar = FL_GET_BASE(board->flags); 764 offset += idx * board->uart_offset; 765 766 p = pci_ioremap_bar(dev, bar); 767 if (!p) 768 return -ENOMEM; 769 770 /* enable the transceiver */ 771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 772 p + offset + NI8430_PORTCON); 773 774 iounmap(p); 775 776 return setup_port(priv, port, bar, offset, board->reg_shift); 777 } 778 779 static int pci_netmos_9900_setup(struct serial_private *priv, 780 const struct pciserial_board *board, 781 struct uart_8250_port *port, int idx) 782 { 783 unsigned int bar; 784 785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 786 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 787 /* netmos apparently orders BARs by datasheet layout, so serial 788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 789 */ 790 bar = 3 * idx; 791 792 return setup_port(priv, port, bar, 0, board->reg_shift); 793 } 794 795 return pci_default_setup(priv, board, port, idx); 796 } 797 798 /* the 99xx series comes with a range of device IDs and a variety 799 * of capabilities: 800 * 801 * 9900 has varying capabilities and can cascade to sub-controllers 802 * (cascading should be purely internal) 803 * 9904 is hardwired with 4 serial ports 804 * 9912 and 9922 are hardwired with 2 serial ports 805 */ 806 static int pci_netmos_9900_numports(struct pci_dev *dev) 807 { 808 unsigned int c = dev->class; 809 unsigned int pi; 810 unsigned short sub_serports; 811 812 pi = c & 0xff; 813 814 if (pi == 2) 815 return 1; 816 817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 818 /* two possibilities: 0x30ps encodes number of parallel and 819 * serial ports, or 0x1000 indicates *something*. This is not 820 * immediately obvious, since the 2s1p+4s configuration seems 821 * to offer all functionality on functions 0..2, while still 822 * advertising the same function 3 as the 4s+2s1p config. 823 */ 824 sub_serports = dev->subsystem_device & 0xf; 825 if (sub_serports > 0) 826 return sub_serports; 827 828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 829 return 0; 830 } 831 832 moan_device("unknown NetMos/Mostech program interface", dev); 833 return 0; 834 } 835 836 static int pci_netmos_init(struct pci_dev *dev) 837 { 838 /* subdevice 0x00PS means <P> parallel, <S> serial */ 839 unsigned int num_serial = dev->subsystem_device & 0xf; 840 841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 842 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 843 return 0; 844 845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 846 dev->subsystem_device == 0x0299) 847 return 0; 848 849 switch (dev->device) { /* FALLTHROUGH on all */ 850 case PCI_DEVICE_ID_NETMOS_9904: 851 case PCI_DEVICE_ID_NETMOS_9912: 852 case PCI_DEVICE_ID_NETMOS_9922: 853 case PCI_DEVICE_ID_NETMOS_9900: 854 num_serial = pci_netmos_9900_numports(dev); 855 break; 856 857 default: 858 break; 859 } 860 861 if (num_serial == 0) { 862 moan_device("unknown NetMos/Mostech device", dev); 863 return -ENODEV; 864 } 865 866 return num_serial; 867 } 868 869 /* 870 * These chips are available with optionally one parallel port and up to 871 * two serial ports. Unfortunately they all have the same product id. 872 * 873 * Basic configuration is done over a region of 32 I/O ports. The base 874 * ioport is called INTA or INTC, depending on docs/other drivers. 875 * 876 * The region of the 32 I/O ports is configured in POSIO0R... 877 */ 878 879 /* registers */ 880 #define ITE_887x_MISCR 0x9c 881 #define ITE_887x_INTCBAR 0x78 882 #define ITE_887x_UARTBAR 0x7c 883 #define ITE_887x_PS0BAR 0x10 884 #define ITE_887x_POSIO0 0x60 885 886 /* I/O space size */ 887 #define ITE_887x_IOSIZE 32 888 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 890 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 893 #define ITE_887x_POSIO_SPEED (3 << 29) 894 /* enable IO_Space bit */ 895 #define ITE_887x_POSIO_ENABLE (1 << 31) 896 897 /* inta_addr are the configuration addresses of the ITE */ 898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 899 static int pci_ite887x_init(struct pci_dev *dev) 900 { 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 908 "ite887x"); 909 if (iobase != NULL) { 910 /* write POSIO0R - speed | size | ioport */ 911 pci_write_config_dword(dev, ITE_887x_POSIO0, 912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 914 /* write INTCBAR - ioport */ 915 pci_write_config_dword(dev, ITE_887x_INTCBAR, 916 inta_addr[i]); 917 ret = inb(inta_addr[i]); 918 if (ret != 0xff) { 919 /* ioport connected */ 920 break; 921 } 922 release_region(iobase->start, ITE_887x_IOSIZE); 923 } 924 } 925 926 if (i == ARRAY_SIZE(inta_addr)) { 927 pci_err(dev, "could not find iobase\n"); 928 return -ENODEV; 929 } 930 931 /* start of undocumented type checking (see parport_pc.c) */ 932 type = inb(iobase->start + 0x18) & 0x0f; 933 934 switch (type) { 935 case 0x2: /* ITE8871 (1P) */ 936 case 0xa: /* ITE8875 (1P) */ 937 ret = 0; 938 break; 939 case 0xe: /* ITE8872 (2S1P) */ 940 ret = 2; 941 break; 942 case 0x6: /* ITE8873 (1S) */ 943 ret = 1; 944 break; 945 case 0x8: /* ITE8874 (2S) */ 946 ret = 2; 947 break; 948 default: 949 moan_device("Unknown ITE887x", dev); 950 ret = -ENODEV; 951 } 952 953 /* configure all serial ports */ 954 for (i = 0; i < ret; i++) { 955 /* read the I/O port from the device */ 956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 957 &ioport); 958 ioport &= 0x0000FF00; /* the actual base address */ 959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 961 ITE_887x_POSIO_IOSIZE_8 | ioport); 962 963 /* write the ioport to the UARTBAR */ 964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 966 uartbar |= (ioport << (16 * i)); /* set the ioport */ 967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 968 969 /* get current config */ 970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 971 /* disable interrupts (UARTx_Routing[3:0]) */ 972 miscr &= ~(0xf << (12 - 4 * i)); 973 /* activate the UART (UARTx_En) */ 974 miscr |= 1 << (23 - i); 975 /* write new config with activated UART */ 976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 977 } 978 979 if (ret <= 0) { 980 /* the device has no UARTs if we get here */ 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 984 return ret; 985 } 986 987 static void pci_ite887x_exit(struct pci_dev *dev) 988 { 989 u32 ioport; 990 /* the ioport is bit 0-15 in POSIO0R */ 991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 992 ioport &= 0xffff; 993 release_region(ioport, ITE_887x_IOSIZE); 994 } 995 996 /* 997 * EndRun Technologies. 998 * Determine the number of ports available on the device. 999 */ 1000 #define PCI_VENDOR_ID_ENDRUN 0x7401 1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1002 1003 static int pci_endrun_init(struct pci_dev *dev) 1004 { 1005 u8 __iomem *p; 1006 unsigned long deviceID; 1007 unsigned int number_uarts = 0; 1008 1009 /* EndRun device is all 0xexxx */ 1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1011 (dev->device & 0xf000) != 0xe000) 1012 return 0; 1013 1014 p = pci_iomap(dev, 0, 5); 1015 if (p == NULL) 1016 return -ENOMEM; 1017 1018 deviceID = ioread32(p); 1019 /* EndRun device */ 1020 if (deviceID == 0x07000200) { 1021 number_uarts = ioread8(p + 4); 1022 pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* 1029 * Oxford Semiconductor Inc. 1030 * Check that device is part of the Tornado range of devices, then determine 1031 * the number of ports available on the device. 1032 */ 1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1034 { 1035 u8 __iomem *p; 1036 unsigned long deviceID; 1037 unsigned int number_uarts = 0; 1038 1039 /* OxSemi Tornado devices are all 0xCxxx */ 1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1041 (dev->device & 0xF000) != 0xC000) 1042 return 0; 1043 1044 p = pci_iomap(dev, 0, 5); 1045 if (p == NULL) 1046 return -ENOMEM; 1047 1048 deviceID = ioread32(p); 1049 /* Tornado device */ 1050 if (deviceID == 0x07000200) { 1051 number_uarts = ioread8(p + 4); 1052 pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts); 1053 } 1054 pci_iounmap(dev, p); 1055 return number_uarts; 1056 } 1057 1058 static int pci_asix_setup(struct serial_private *priv, 1059 const struct pciserial_board *board, 1060 struct uart_8250_port *port, int idx) 1061 { 1062 port->bugs |= UART_BUG_PARITY; 1063 return pci_default_setup(priv, board, port, idx); 1064 } 1065 1066 #define QPCR_TEST_FOR1 0x3F 1067 #define QPCR_TEST_GET1 0x00 1068 #define QPCR_TEST_FOR2 0x40 1069 #define QPCR_TEST_GET2 0x40 1070 #define QPCR_TEST_FOR3 0x80 1071 #define QPCR_TEST_GET3 0x40 1072 #define QPCR_TEST_FOR4 0xC0 1073 #define QPCR_TEST_GET4 0x80 1074 1075 #define QOPR_CLOCK_X1 0x0000 1076 #define QOPR_CLOCK_X2 0x0001 1077 #define QOPR_CLOCK_X4 0x0002 1078 #define QOPR_CLOCK_X8 0x0003 1079 #define QOPR_CLOCK_RATE_MASK 0x0003 1080 1081 /* Quatech devices have their own extra interface features */ 1082 static struct pci_device_id quatech_cards[] = { 1083 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1084 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1085 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1086 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1087 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1088 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1089 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1090 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1091 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1092 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1093 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1094 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1095 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1096 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1097 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1098 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1099 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1100 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1101 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1102 { 0, } 1103 }; 1104 1105 static int pci_quatech_rqopr(struct uart_8250_port *port) 1106 { 1107 unsigned long base = port->port.iobase; 1108 u8 LCR, val; 1109 1110 LCR = inb(base + UART_LCR); 1111 outb(0xBF, base + UART_LCR); 1112 val = inb(base + UART_SCR); 1113 outb(LCR, base + UART_LCR); 1114 return val; 1115 } 1116 1117 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1118 { 1119 unsigned long base = port->port.iobase; 1120 u8 LCR; 1121 1122 LCR = inb(base + UART_LCR); 1123 outb(0xBF, base + UART_LCR); 1124 inb(base + UART_SCR); 1125 outb(qopr, base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127 } 1128 1129 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1130 { 1131 unsigned long base = port->port.iobase; 1132 u8 LCR, val, qmcr; 1133 1134 LCR = inb(base + UART_LCR); 1135 outb(0xBF, base + UART_LCR); 1136 val = inb(base + UART_SCR); 1137 outb(val | 0x10, base + UART_SCR); 1138 qmcr = inb(base + UART_MCR); 1139 outb(val, base + UART_SCR); 1140 outb(LCR, base + UART_LCR); 1141 1142 return qmcr; 1143 } 1144 1145 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1146 { 1147 unsigned long base = port->port.iobase; 1148 u8 LCR, val; 1149 1150 LCR = inb(base + UART_LCR); 1151 outb(0xBF, base + UART_LCR); 1152 val = inb(base + UART_SCR); 1153 outb(val | 0x10, base + UART_SCR); 1154 outb(qmcr, base + UART_MCR); 1155 outb(val, base + UART_SCR); 1156 outb(LCR, base + UART_LCR); 1157 } 1158 1159 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1160 { 1161 unsigned long base = port->port.iobase; 1162 u8 LCR, val; 1163 1164 LCR = inb(base + UART_LCR); 1165 outb(0xBF, base + UART_LCR); 1166 val = inb(base + UART_SCR); 1167 if (val & 0x20) { 1168 outb(0x80, UART_LCR); 1169 if (!(inb(UART_SCR) & 0x20)) { 1170 outb(LCR, base + UART_LCR); 1171 return 1; 1172 } 1173 } 1174 return 0; 1175 } 1176 1177 static int pci_quatech_test(struct uart_8250_port *port) 1178 { 1179 u8 reg, qopr; 1180 1181 qopr = pci_quatech_rqopr(port); 1182 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1183 reg = pci_quatech_rqopr(port) & 0xC0; 1184 if (reg != QPCR_TEST_GET1) 1185 return -EINVAL; 1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1187 reg = pci_quatech_rqopr(port) & 0xC0; 1188 if (reg != QPCR_TEST_GET2) 1189 return -EINVAL; 1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1191 reg = pci_quatech_rqopr(port) & 0xC0; 1192 if (reg != QPCR_TEST_GET3) 1193 return -EINVAL; 1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1195 reg = pci_quatech_rqopr(port) & 0xC0; 1196 if (reg != QPCR_TEST_GET4) 1197 return -EINVAL; 1198 1199 pci_quatech_wqopr(port, qopr); 1200 return 0; 1201 } 1202 1203 static int pci_quatech_clock(struct uart_8250_port *port) 1204 { 1205 u8 qopr, reg, set; 1206 unsigned long clock; 1207 1208 if (pci_quatech_test(port) < 0) 1209 return 1843200; 1210 1211 qopr = pci_quatech_rqopr(port); 1212 1213 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (reg & QOPR_CLOCK_X8) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1220 reg = pci_quatech_rqopr(port); 1221 if (!(reg & QOPR_CLOCK_X8)) { 1222 clock = 1843200; 1223 goto out; 1224 } 1225 reg &= QOPR_CLOCK_X8; 1226 if (reg == QOPR_CLOCK_X2) { 1227 clock = 3685400; 1228 set = QOPR_CLOCK_X2; 1229 } else if (reg == QOPR_CLOCK_X4) { 1230 clock = 7372800; 1231 set = QOPR_CLOCK_X4; 1232 } else if (reg == QOPR_CLOCK_X8) { 1233 clock = 14745600; 1234 set = QOPR_CLOCK_X8; 1235 } else { 1236 clock = 1843200; 1237 set = QOPR_CLOCK_X1; 1238 } 1239 qopr &= ~QOPR_CLOCK_RATE_MASK; 1240 qopr |= set; 1241 1242 out: 1243 pci_quatech_wqopr(port, qopr); 1244 return clock; 1245 } 1246 1247 static int pci_quatech_rs422(struct uart_8250_port *port) 1248 { 1249 u8 qmcr; 1250 int rs422 = 0; 1251 1252 if (!pci_quatech_has_qmcr(port)) 1253 return 0; 1254 qmcr = pci_quatech_rqmcr(port); 1255 pci_quatech_wqmcr(port, 0xFF); 1256 if (pci_quatech_rqmcr(port)) 1257 rs422 = 1; 1258 pci_quatech_wqmcr(port, qmcr); 1259 return rs422; 1260 } 1261 1262 static int pci_quatech_init(struct pci_dev *dev) 1263 { 1264 const struct pci_device_id *match; 1265 bool amcc = false; 1266 1267 match = pci_match_id(quatech_cards, dev); 1268 if (match) 1269 amcc = match->driver_data; 1270 else 1271 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1272 1273 if (amcc) { 1274 unsigned long base = pci_resource_start(dev, 0); 1275 if (base) { 1276 u32 tmp; 1277 1278 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1279 tmp = inl(base + 0x3c); 1280 outl(tmp | 0x01000000, base + 0x3c); 1281 outl(tmp &= ~0x01000000, base + 0x3c); 1282 } 1283 } 1284 return 0; 1285 } 1286 1287 static int pci_quatech_setup(struct serial_private *priv, 1288 const struct pciserial_board *board, 1289 struct uart_8250_port *port, int idx) 1290 { 1291 /* Needed by pci_quatech calls below */ 1292 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1293 /* Set up the clocking */ 1294 port->port.uartclk = pci_quatech_clock(port); 1295 /* For now just warn about RS422 */ 1296 if (pci_quatech_rs422(port)) 1297 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1298 return pci_default_setup(priv, board, port, idx); 1299 } 1300 1301 static int pci_default_setup(struct serial_private *priv, 1302 const struct pciserial_board *board, 1303 struct uart_8250_port *port, int idx) 1304 { 1305 unsigned int bar, offset = board->first_offset, maxnr; 1306 1307 bar = FL_GET_BASE(board->flags); 1308 if (board->flags & FL_BASE_BARS) 1309 bar += idx; 1310 else 1311 offset += idx * board->uart_offset; 1312 1313 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1314 (board->reg_shift + 3); 1315 1316 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1317 return 1; 1318 1319 return setup_port(priv, port, bar, offset, board->reg_shift); 1320 } 1321 static void 1322 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1323 unsigned int quot, unsigned int quot_frac) 1324 { 1325 int scr; 1326 int lcr; 1327 int actual_baud; 1328 int tolerance; 1329 1330 for (scr = 5 ; scr <= 15 ; scr++) { 1331 actual_baud = 921600 * 16 / scr; 1332 tolerance = actual_baud / 50; 1333 1334 if ((baud < actual_baud + tolerance) && 1335 (baud > actual_baud - tolerance)) { 1336 1337 lcr = serial_port_in(port, UART_LCR); 1338 serial_port_out(port, UART_LCR, lcr | 0x80); 1339 1340 serial_port_out(port, UART_DLL, 1); 1341 serial_port_out(port, UART_DLM, 0); 1342 serial_port_out(port, 2, 16 - scr); 1343 serial_port_out(port, UART_LCR, lcr); 1344 return; 1345 } else if (baud > actual_baud) { 1346 break; 1347 } 1348 } 1349 serial8250_do_set_divisor(port, baud, quot, quot_frac); 1350 } 1351 static int pci_pericom_setup(struct serial_private *priv, 1352 const struct pciserial_board *board, 1353 struct uart_8250_port *port, int idx) 1354 { 1355 unsigned int bar, offset = board->first_offset, maxnr; 1356 1357 bar = FL_GET_BASE(board->flags); 1358 if (board->flags & FL_BASE_BARS) 1359 bar += idx; 1360 else 1361 offset += idx * board->uart_offset; 1362 1363 1364 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1365 (board->reg_shift + 3); 1366 1367 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1368 return 1; 1369 1370 port->port.set_divisor = pericom_do_set_divisor; 1371 1372 return setup_port(priv, port, bar, offset, board->reg_shift); 1373 } 1374 1375 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1376 const struct pciserial_board *board, 1377 struct uart_8250_port *port, int idx) 1378 { 1379 unsigned int bar, offset = board->first_offset, maxnr; 1380 1381 bar = FL_GET_BASE(board->flags); 1382 if (board->flags & FL_BASE_BARS) 1383 bar += idx; 1384 else 1385 offset += idx * board->uart_offset; 1386 1387 if (idx==3) 1388 offset = 0x38; 1389 1390 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1391 (board->reg_shift + 3); 1392 1393 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1394 return 1; 1395 1396 port->port.set_divisor = pericom_do_set_divisor; 1397 1398 return setup_port(priv, port, bar, offset, board->reg_shift); 1399 } 1400 1401 static int 1402 ce4100_serial_setup(struct serial_private *priv, 1403 const struct pciserial_board *board, 1404 struct uart_8250_port *port, int idx) 1405 { 1406 int ret; 1407 1408 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1409 port->port.iotype = UPIO_MEM32; 1410 port->port.type = PORT_XSCALE; 1411 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1412 port->port.regshift = 2; 1413 1414 return ret; 1415 } 1416 1417 static int 1418 pci_omegapci_setup(struct serial_private *priv, 1419 const struct pciserial_board *board, 1420 struct uart_8250_port *port, int idx) 1421 { 1422 return setup_port(priv, port, 2, idx * 8, 0); 1423 } 1424 1425 static int 1426 pci_brcm_trumanage_setup(struct serial_private *priv, 1427 const struct pciserial_board *board, 1428 struct uart_8250_port *port, int idx) 1429 { 1430 int ret = pci_default_setup(priv, board, port, idx); 1431 1432 port->port.type = PORT_BRCM_TRUMANAGE; 1433 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1434 return ret; 1435 } 1436 1437 /* RTS will control by MCR if this bit is 0 */ 1438 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1439 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1440 #define FINTEK_RTS_INVERT BIT(5) 1441 1442 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1443 static int pci_fintek_rs485_config(struct uart_port *port, 1444 struct serial_rs485 *rs485) 1445 { 1446 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1447 u8 setting; 1448 u8 *index = (u8 *) port->private_data; 1449 1450 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1451 1452 if (!rs485) 1453 rs485 = &port->rs485; 1454 else if (rs485->flags & SER_RS485_ENABLED) 1455 memset(rs485->padding, 0, sizeof(rs485->padding)); 1456 else 1457 memset(rs485, 0, sizeof(*rs485)); 1458 1459 /* F81504/508/512 not support RTS delay before or after send */ 1460 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1461 1462 if (rs485->flags & SER_RS485_ENABLED) { 1463 /* Enable RTS H/W control mode */ 1464 setting |= FINTEK_RTS_CONTROL_BY_HW; 1465 1466 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1467 /* RTS driving high on TX */ 1468 setting &= ~FINTEK_RTS_INVERT; 1469 } else { 1470 /* RTS driving low on TX */ 1471 setting |= FINTEK_RTS_INVERT; 1472 } 1473 1474 rs485->delay_rts_after_send = 0; 1475 rs485->delay_rts_before_send = 0; 1476 } else { 1477 /* Disable RTS H/W control mode */ 1478 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1479 } 1480 1481 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1482 1483 if (rs485 != &port->rs485) 1484 port->rs485 = *rs485; 1485 1486 return 0; 1487 } 1488 1489 static int pci_fintek_setup(struct serial_private *priv, 1490 const struct pciserial_board *board, 1491 struct uart_8250_port *port, int idx) 1492 { 1493 struct pci_dev *pdev = priv->dev; 1494 u8 *data; 1495 u8 config_base; 1496 u16 iobase; 1497 1498 config_base = 0x40 + 0x08 * idx; 1499 1500 /* Get the io address from configuration space */ 1501 pci_read_config_word(pdev, config_base + 4, &iobase); 1502 1503 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1504 1505 port->port.iotype = UPIO_PORT; 1506 port->port.iobase = iobase; 1507 port->port.rs485_config = pci_fintek_rs485_config; 1508 1509 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1510 if (!data) 1511 return -ENOMEM; 1512 1513 /* preserve index in PCI configuration space */ 1514 *data = idx; 1515 port->port.private_data = data; 1516 1517 return 0; 1518 } 1519 1520 static int pci_fintek_init(struct pci_dev *dev) 1521 { 1522 unsigned long iobase; 1523 u32 max_port, i; 1524 resource_size_t bar_data[3]; 1525 u8 config_base; 1526 struct serial_private *priv = pci_get_drvdata(dev); 1527 struct uart_8250_port *port; 1528 1529 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1530 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1531 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1532 return -ENODEV; 1533 1534 switch (dev->device) { 1535 case 0x1104: /* 4 ports */ 1536 case 0x1108: /* 8 ports */ 1537 max_port = dev->device & 0xff; 1538 break; 1539 case 0x1112: /* 12 ports */ 1540 max_port = 12; 1541 break; 1542 default: 1543 return -EINVAL; 1544 } 1545 1546 /* Get the io address dispatch from the BIOS */ 1547 bar_data[0] = pci_resource_start(dev, 5); 1548 bar_data[1] = pci_resource_start(dev, 4); 1549 bar_data[2] = pci_resource_start(dev, 3); 1550 1551 for (i = 0; i < max_port; ++i) { 1552 /* UART0 configuration offset start from 0x40 */ 1553 config_base = 0x40 + 0x08 * i; 1554 1555 /* Calculate Real IO Port */ 1556 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1557 1558 /* Enable UART I/O port */ 1559 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1560 1561 /* Select 128-byte FIFO and 8x FIFO threshold */ 1562 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1563 1564 /* LSB UART */ 1565 pci_write_config_byte(dev, config_base + 0x04, 1566 (u8)(iobase & 0xff)); 1567 1568 /* MSB UART */ 1569 pci_write_config_byte(dev, config_base + 0x05, 1570 (u8)((iobase & 0xff00) >> 8)); 1571 1572 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1573 1574 if (priv) { 1575 /* re-apply RS232/485 mode when 1576 * pciserial_resume_ports() 1577 */ 1578 port = serial8250_get_port(priv->line[i]); 1579 pci_fintek_rs485_config(&port->port, NULL); 1580 } else { 1581 /* First init without port data 1582 * force init to RS232 Mode 1583 */ 1584 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1585 } 1586 } 1587 1588 return max_port; 1589 } 1590 1591 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1592 { 1593 struct f815xxa_data *data = p->private_data; 1594 unsigned long flags; 1595 1596 spin_lock_irqsave(&data->lock, flags); 1597 writeb(value, p->membase + offset); 1598 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1599 spin_unlock_irqrestore(&data->lock, flags); 1600 } 1601 1602 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1603 const struct pciserial_board *board, 1604 struct uart_8250_port *port, int idx) 1605 { 1606 struct pci_dev *pdev = priv->dev; 1607 struct f815xxa_data *data; 1608 1609 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1610 if (!data) 1611 return -ENOMEM; 1612 1613 data->idx = idx; 1614 spin_lock_init(&data->lock); 1615 1616 port->port.private_data = data; 1617 port->port.iotype = UPIO_MEM; 1618 port->port.flags |= UPF_IOREMAP; 1619 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1620 port->port.serial_out = f815xxa_mem_serial_out; 1621 1622 return 0; 1623 } 1624 1625 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1626 { 1627 u32 max_port, i; 1628 int config_base; 1629 1630 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1631 return -ENODEV; 1632 1633 switch (dev->device) { 1634 case 0x1204: /* 4 ports */ 1635 case 0x1208: /* 8 ports */ 1636 max_port = dev->device & 0xff; 1637 break; 1638 case 0x1212: /* 12 ports */ 1639 max_port = 12; 1640 break; 1641 default: 1642 return -EINVAL; 1643 } 1644 1645 /* Set to mmio decode */ 1646 pci_write_config_byte(dev, 0x209, 0x40); 1647 1648 for (i = 0; i < max_port; ++i) { 1649 /* UART0 configuration offset start from 0x2A0 */ 1650 config_base = 0x2A0 + 0x08 * i; 1651 1652 /* Select 128-byte FIFO and 8x FIFO threshold */ 1653 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1654 1655 /* Enable UART I/O port */ 1656 pci_write_config_byte(dev, config_base + 0, 0x01); 1657 } 1658 1659 return max_port; 1660 } 1661 1662 static int skip_tx_en_setup(struct serial_private *priv, 1663 const struct pciserial_board *board, 1664 struct uart_8250_port *port, int idx) 1665 { 1666 port->port.quirks |= UPQ_NO_TXEN_TEST; 1667 pci_dbg(priv->dev, 1668 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1669 priv->dev->vendor, priv->dev->device, 1670 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1671 1672 return pci_default_setup(priv, board, port, idx); 1673 } 1674 1675 static void kt_handle_break(struct uart_port *p) 1676 { 1677 struct uart_8250_port *up = up_to_u8250p(p); 1678 /* 1679 * On receipt of a BI, serial device in Intel ME (Intel 1680 * management engine) needs to have its fifos cleared for sane 1681 * SOL (Serial Over Lan) output. 1682 */ 1683 serial8250_clear_and_reinit_fifos(up); 1684 } 1685 1686 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1687 { 1688 struct uart_8250_port *up = up_to_u8250p(p); 1689 unsigned int val; 1690 1691 /* 1692 * When the Intel ME (management engine) gets reset its serial 1693 * port registers could return 0 momentarily. Functions like 1694 * serial8250_console_write, read and save the IER, perform 1695 * some operation and then restore it. In order to avoid 1696 * setting IER register inadvertently to 0, if the value read 1697 * is 0, double check with ier value in uart_8250_port and use 1698 * that instead. up->ier should be the same value as what is 1699 * currently configured. 1700 */ 1701 val = inb(p->iobase + offset); 1702 if (offset == UART_IER) { 1703 if (val == 0) 1704 val = up->ier; 1705 } 1706 return val; 1707 } 1708 1709 static int kt_serial_setup(struct serial_private *priv, 1710 const struct pciserial_board *board, 1711 struct uart_8250_port *port, int idx) 1712 { 1713 port->port.flags |= UPF_BUG_THRE; 1714 port->port.serial_in = kt_serial_in; 1715 port->port.handle_break = kt_handle_break; 1716 return skip_tx_en_setup(priv, board, port, idx); 1717 } 1718 1719 static int pci_eg20t_init(struct pci_dev *dev) 1720 { 1721 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1722 return -ENODEV; 1723 #else 1724 return 0; 1725 #endif 1726 } 1727 1728 static int 1729 pci_wch_ch353_setup(struct serial_private *priv, 1730 const struct pciserial_board *board, 1731 struct uart_8250_port *port, int idx) 1732 { 1733 port->port.flags |= UPF_FIXED_TYPE; 1734 port->port.type = PORT_16550A; 1735 return pci_default_setup(priv, board, port, idx); 1736 } 1737 1738 static int 1739 pci_wch_ch355_setup(struct serial_private *priv, 1740 const struct pciserial_board *board, 1741 struct uart_8250_port *port, int idx) 1742 { 1743 port->port.flags |= UPF_FIXED_TYPE; 1744 port->port.type = PORT_16550A; 1745 return pci_default_setup(priv, board, port, idx); 1746 } 1747 1748 static int 1749 pci_wch_ch38x_setup(struct serial_private *priv, 1750 const struct pciserial_board *board, 1751 struct uart_8250_port *port, int idx) 1752 { 1753 port->port.flags |= UPF_FIXED_TYPE; 1754 port->port.type = PORT_16850; 1755 return pci_default_setup(priv, board, port, idx); 1756 } 1757 1758 1759 #define CH384_XINT_ENABLE_REG 0xEB 1760 #define CH384_XINT_ENABLE_BIT 0x02 1761 1762 static int pci_wch_ch38x_init(struct pci_dev *dev) 1763 { 1764 int max_port; 1765 unsigned long iobase; 1766 1767 1768 switch (dev->device) { 1769 case 0x3853: /* 8 ports */ 1770 max_port = 8; 1771 break; 1772 default: 1773 return -EINVAL; 1774 } 1775 1776 iobase = pci_resource_start(dev, 0); 1777 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1778 1779 return max_port; 1780 } 1781 1782 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1783 { 1784 unsigned long iobase; 1785 1786 iobase = pci_resource_start(dev, 0); 1787 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1788 } 1789 1790 1791 static int 1792 pci_sunix_setup(struct serial_private *priv, 1793 const struct pciserial_board *board, 1794 struct uart_8250_port *port, int idx) 1795 { 1796 int bar; 1797 int offset; 1798 1799 port->port.flags |= UPF_FIXED_TYPE; 1800 port->port.type = PORT_SUNIX; 1801 1802 if (idx < 4) { 1803 bar = 0; 1804 offset = idx * board->uart_offset; 1805 } else { 1806 bar = 1; 1807 idx -= 4; 1808 idx = div_s64_rem(idx, 4, &offset); 1809 offset = idx * 64 + offset * board->uart_offset; 1810 } 1811 1812 return setup_port(priv, port, bar, offset, 0); 1813 } 1814 1815 static int 1816 pci_moxa_setup(struct serial_private *priv, 1817 const struct pciserial_board *board, 1818 struct uart_8250_port *port, int idx) 1819 { 1820 unsigned int bar = FL_GET_BASE(board->flags); 1821 int offset; 1822 1823 if (board->num_ports == 4 && idx == 3) 1824 offset = 7 * board->uart_offset; 1825 else 1826 offset = idx * board->uart_offset; 1827 1828 return setup_port(priv, port, bar, offset, 0); 1829 } 1830 1831 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1832 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1833 #define PCI_DEVICE_ID_OCTPRO 0x0001 1834 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1835 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1836 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1837 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1838 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1839 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1840 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1841 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1842 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1843 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1844 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1845 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1846 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1847 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1848 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1849 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1850 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1851 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1852 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1853 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1854 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1855 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1856 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1857 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1858 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1859 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1860 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1861 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1862 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1863 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1864 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1865 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1866 #define PCI_VENDOR_ID_WCH 0x4348 1867 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1868 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1869 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1870 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1871 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1872 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1873 #define PCI_VENDOR_ID_AGESTAR 0x5372 1874 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1875 #define PCI_VENDOR_ID_ASIX 0x9710 1876 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1877 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1878 1879 #define PCIE_VENDOR_ID_WCH 0x1c00 1880 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1881 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1882 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1883 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1884 1885 #define PCI_VENDOR_ID_ACCESIO 0x494f 1886 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1887 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1888 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1889 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1890 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1898 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1900 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1902 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1903 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1904 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1905 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1906 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1908 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1910 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1912 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1914 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1916 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1918 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1919 1920 1921 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1922 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1923 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1924 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1925 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1926 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1927 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1928 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1929 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1930 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1931 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1932 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1933 1934 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1935 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1936 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1937 1938 /* 1939 * Master list of serial port init/setup/exit quirks. 1940 * This does not describe the general nature of the port. 1941 * (ie, baud base, number and location of ports, etc) 1942 * 1943 * This list is ordered alphabetically by vendor then device. 1944 * Specific entries must come before more generic entries. 1945 */ 1946 static struct pci_serial_quirk pci_serial_quirks[] = { 1947 /* 1948 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1949 */ 1950 { 1951 .vendor = PCI_VENDOR_ID_AMCC, 1952 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1953 .subvendor = PCI_ANY_ID, 1954 .subdevice = PCI_ANY_ID, 1955 .setup = addidata_apci7800_setup, 1956 }, 1957 /* 1958 * AFAVLAB cards - these may be called via parport_serial 1959 * It is not clear whether this applies to all products. 1960 */ 1961 { 1962 .vendor = PCI_VENDOR_ID_AFAVLAB, 1963 .device = PCI_ANY_ID, 1964 .subvendor = PCI_ANY_ID, 1965 .subdevice = PCI_ANY_ID, 1966 .setup = afavlab_setup, 1967 }, 1968 /* 1969 * HP Diva 1970 */ 1971 { 1972 .vendor = PCI_VENDOR_ID_HP, 1973 .device = PCI_DEVICE_ID_HP_DIVA, 1974 .subvendor = PCI_ANY_ID, 1975 .subdevice = PCI_ANY_ID, 1976 .init = pci_hp_diva_init, 1977 .setup = pci_hp_diva_setup, 1978 }, 1979 /* 1980 * HPE PCI serial device 1981 */ 1982 { 1983 .vendor = PCI_VENDOR_ID_HP_3PAR, 1984 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 1985 .subvendor = PCI_ANY_ID, 1986 .subdevice = PCI_ANY_ID, 1987 .setup = pci_hp_diva_setup, 1988 }, 1989 /* 1990 * Intel 1991 */ 1992 { 1993 .vendor = PCI_VENDOR_ID_INTEL, 1994 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1995 .subvendor = 0xe4bf, 1996 .subdevice = PCI_ANY_ID, 1997 .init = pci_inteli960ni_init, 1998 .setup = pci_default_setup, 1999 }, 2000 { 2001 .vendor = PCI_VENDOR_ID_INTEL, 2002 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2003 .subvendor = PCI_ANY_ID, 2004 .subdevice = PCI_ANY_ID, 2005 .setup = skip_tx_en_setup, 2006 }, 2007 { 2008 .vendor = PCI_VENDOR_ID_INTEL, 2009 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2010 .subvendor = PCI_ANY_ID, 2011 .subdevice = PCI_ANY_ID, 2012 .setup = skip_tx_en_setup, 2013 }, 2014 { 2015 .vendor = PCI_VENDOR_ID_INTEL, 2016 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2017 .subvendor = PCI_ANY_ID, 2018 .subdevice = PCI_ANY_ID, 2019 .setup = skip_tx_en_setup, 2020 }, 2021 { 2022 .vendor = PCI_VENDOR_ID_INTEL, 2023 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2024 .subvendor = PCI_ANY_ID, 2025 .subdevice = PCI_ANY_ID, 2026 .setup = ce4100_serial_setup, 2027 }, 2028 { 2029 .vendor = PCI_VENDOR_ID_INTEL, 2030 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2031 .subvendor = PCI_ANY_ID, 2032 .subdevice = PCI_ANY_ID, 2033 .setup = kt_serial_setup, 2034 }, 2035 /* 2036 * ITE 2037 */ 2038 { 2039 .vendor = PCI_VENDOR_ID_ITE, 2040 .device = PCI_DEVICE_ID_ITE_8872, 2041 .subvendor = PCI_ANY_ID, 2042 .subdevice = PCI_ANY_ID, 2043 .init = pci_ite887x_init, 2044 .setup = pci_default_setup, 2045 .exit = pci_ite887x_exit, 2046 }, 2047 /* 2048 * National Instruments 2049 */ 2050 { 2051 .vendor = PCI_VENDOR_ID_NI, 2052 .device = PCI_DEVICE_ID_NI_PCI23216, 2053 .subvendor = PCI_ANY_ID, 2054 .subdevice = PCI_ANY_ID, 2055 .init = pci_ni8420_init, 2056 .setup = pci_default_setup, 2057 .exit = pci_ni8420_exit, 2058 }, 2059 { 2060 .vendor = PCI_VENDOR_ID_NI, 2061 .device = PCI_DEVICE_ID_NI_PCI2328, 2062 .subvendor = PCI_ANY_ID, 2063 .subdevice = PCI_ANY_ID, 2064 .init = pci_ni8420_init, 2065 .setup = pci_default_setup, 2066 .exit = pci_ni8420_exit, 2067 }, 2068 { 2069 .vendor = PCI_VENDOR_ID_NI, 2070 .device = PCI_DEVICE_ID_NI_PCI2324, 2071 .subvendor = PCI_ANY_ID, 2072 .subdevice = PCI_ANY_ID, 2073 .init = pci_ni8420_init, 2074 .setup = pci_default_setup, 2075 .exit = pci_ni8420_exit, 2076 }, 2077 { 2078 .vendor = PCI_VENDOR_ID_NI, 2079 .device = PCI_DEVICE_ID_NI_PCI2322, 2080 .subvendor = PCI_ANY_ID, 2081 .subdevice = PCI_ANY_ID, 2082 .init = pci_ni8420_init, 2083 .setup = pci_default_setup, 2084 .exit = pci_ni8420_exit, 2085 }, 2086 { 2087 .vendor = PCI_VENDOR_ID_NI, 2088 .device = PCI_DEVICE_ID_NI_PCI2324I, 2089 .subvendor = PCI_ANY_ID, 2090 .subdevice = PCI_ANY_ID, 2091 .init = pci_ni8420_init, 2092 .setup = pci_default_setup, 2093 .exit = pci_ni8420_exit, 2094 }, 2095 { 2096 .vendor = PCI_VENDOR_ID_NI, 2097 .device = PCI_DEVICE_ID_NI_PCI2322I, 2098 .subvendor = PCI_ANY_ID, 2099 .subdevice = PCI_ANY_ID, 2100 .init = pci_ni8420_init, 2101 .setup = pci_default_setup, 2102 .exit = pci_ni8420_exit, 2103 }, 2104 { 2105 .vendor = PCI_VENDOR_ID_NI, 2106 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2107 .subvendor = PCI_ANY_ID, 2108 .subdevice = PCI_ANY_ID, 2109 .init = pci_ni8420_init, 2110 .setup = pci_default_setup, 2111 .exit = pci_ni8420_exit, 2112 }, 2113 { 2114 .vendor = PCI_VENDOR_ID_NI, 2115 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2116 .subvendor = PCI_ANY_ID, 2117 .subdevice = PCI_ANY_ID, 2118 .init = pci_ni8420_init, 2119 .setup = pci_default_setup, 2120 .exit = pci_ni8420_exit, 2121 }, 2122 { 2123 .vendor = PCI_VENDOR_ID_NI, 2124 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2125 .subvendor = PCI_ANY_ID, 2126 .subdevice = PCI_ANY_ID, 2127 .init = pci_ni8420_init, 2128 .setup = pci_default_setup, 2129 .exit = pci_ni8420_exit, 2130 }, 2131 { 2132 .vendor = PCI_VENDOR_ID_NI, 2133 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2134 .subvendor = PCI_ANY_ID, 2135 .subdevice = PCI_ANY_ID, 2136 .init = pci_ni8420_init, 2137 .setup = pci_default_setup, 2138 .exit = pci_ni8420_exit, 2139 }, 2140 { 2141 .vendor = PCI_VENDOR_ID_NI, 2142 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2143 .subvendor = PCI_ANY_ID, 2144 .subdevice = PCI_ANY_ID, 2145 .init = pci_ni8420_init, 2146 .setup = pci_default_setup, 2147 .exit = pci_ni8420_exit, 2148 }, 2149 { 2150 .vendor = PCI_VENDOR_ID_NI, 2151 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2152 .subvendor = PCI_ANY_ID, 2153 .subdevice = PCI_ANY_ID, 2154 .init = pci_ni8420_init, 2155 .setup = pci_default_setup, 2156 .exit = pci_ni8420_exit, 2157 }, 2158 { 2159 .vendor = PCI_VENDOR_ID_NI, 2160 .device = PCI_ANY_ID, 2161 .subvendor = PCI_ANY_ID, 2162 .subdevice = PCI_ANY_ID, 2163 .init = pci_ni8430_init, 2164 .setup = pci_ni8430_setup, 2165 .exit = pci_ni8430_exit, 2166 }, 2167 /* Quatech */ 2168 { 2169 .vendor = PCI_VENDOR_ID_QUATECH, 2170 .device = PCI_ANY_ID, 2171 .subvendor = PCI_ANY_ID, 2172 .subdevice = PCI_ANY_ID, 2173 .init = pci_quatech_init, 2174 .setup = pci_quatech_setup, 2175 }, 2176 /* 2177 * Panacom 2178 */ 2179 { 2180 .vendor = PCI_VENDOR_ID_PANACOM, 2181 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2182 .subvendor = PCI_ANY_ID, 2183 .subdevice = PCI_ANY_ID, 2184 .init = pci_plx9050_init, 2185 .setup = pci_default_setup, 2186 .exit = pci_plx9050_exit, 2187 }, 2188 { 2189 .vendor = PCI_VENDOR_ID_PANACOM, 2190 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2191 .subvendor = PCI_ANY_ID, 2192 .subdevice = PCI_ANY_ID, 2193 .init = pci_plx9050_init, 2194 .setup = pci_default_setup, 2195 .exit = pci_plx9050_exit, 2196 }, 2197 /* 2198 * Pericom (Only 7954 - It have a offset jump for port 4) 2199 */ 2200 { 2201 .vendor = PCI_VENDOR_ID_PERICOM, 2202 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2203 .subvendor = PCI_ANY_ID, 2204 .subdevice = PCI_ANY_ID, 2205 .setup = pci_pericom_setup_four_at_eight, 2206 }, 2207 /* 2208 * PLX 2209 */ 2210 { 2211 .vendor = PCI_VENDOR_ID_PLX, 2212 .device = PCI_DEVICE_ID_PLX_9050, 2213 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2214 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2215 .init = pci_plx9050_init, 2216 .setup = pci_default_setup, 2217 .exit = pci_plx9050_exit, 2218 }, 2219 { 2220 .vendor = PCI_VENDOR_ID_PLX, 2221 .device = PCI_DEVICE_ID_PLX_9050, 2222 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2223 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2224 .init = pci_plx9050_init, 2225 .setup = pci_default_setup, 2226 .exit = pci_plx9050_exit, 2227 }, 2228 { 2229 .vendor = PCI_VENDOR_ID_PLX, 2230 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2231 .subvendor = PCI_VENDOR_ID_PLX, 2232 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2233 .init = pci_plx9050_init, 2234 .setup = pci_default_setup, 2235 .exit = pci_plx9050_exit, 2236 }, 2237 { 2238 .vendor = PCI_VENDOR_ID_ACCESIO, 2239 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2240 .subvendor = PCI_ANY_ID, 2241 .subdevice = PCI_ANY_ID, 2242 .setup = pci_pericom_setup_four_at_eight, 2243 }, 2244 { 2245 .vendor = PCI_VENDOR_ID_ACCESIO, 2246 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2247 .subvendor = PCI_ANY_ID, 2248 .subdevice = PCI_ANY_ID, 2249 .setup = pci_pericom_setup_four_at_eight, 2250 }, 2251 { 2252 .vendor = PCI_VENDOR_ID_ACCESIO, 2253 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2254 .subvendor = PCI_ANY_ID, 2255 .subdevice = PCI_ANY_ID, 2256 .setup = pci_pericom_setup_four_at_eight, 2257 }, 2258 { 2259 .vendor = PCI_VENDOR_ID_ACCESIO, 2260 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2261 .subvendor = PCI_ANY_ID, 2262 .subdevice = PCI_ANY_ID, 2263 .setup = pci_pericom_setup_four_at_eight, 2264 }, 2265 { 2266 .vendor = PCI_VENDOR_ID_ACCESIO, 2267 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2268 .subvendor = PCI_ANY_ID, 2269 .subdevice = PCI_ANY_ID, 2270 .setup = pci_pericom_setup_four_at_eight, 2271 }, 2272 { 2273 .vendor = PCI_VENDOR_ID_ACCESIO, 2274 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2275 .subvendor = PCI_ANY_ID, 2276 .subdevice = PCI_ANY_ID, 2277 .setup = pci_pericom_setup_four_at_eight, 2278 }, 2279 { 2280 .vendor = PCI_VENDOR_ID_ACCESIO, 2281 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2282 .subvendor = PCI_ANY_ID, 2283 .subdevice = PCI_ANY_ID, 2284 .setup = pci_pericom_setup_four_at_eight, 2285 }, 2286 { 2287 .vendor = PCI_VENDOR_ID_ACCESIO, 2288 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .setup = pci_pericom_setup_four_at_eight, 2292 }, 2293 { 2294 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2295 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2296 .subvendor = PCI_ANY_ID, 2297 .subdevice = PCI_ANY_ID, 2298 .setup = pci_pericom_setup_four_at_eight, 2299 }, 2300 { 2301 .vendor = PCI_VENDOR_ID_ACCESIO, 2302 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2303 .subvendor = PCI_ANY_ID, 2304 .subdevice = PCI_ANY_ID, 2305 .setup = pci_pericom_setup_four_at_eight, 2306 }, 2307 { 2308 .vendor = PCI_VENDOR_ID_ACCESIO, 2309 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2310 .subvendor = PCI_ANY_ID, 2311 .subdevice = PCI_ANY_ID, 2312 .setup = pci_pericom_setup_four_at_eight, 2313 }, 2314 { 2315 .vendor = PCI_VENDOR_ID_ACCESIO, 2316 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2317 .subvendor = PCI_ANY_ID, 2318 .subdevice = PCI_ANY_ID, 2319 .setup = pci_pericom_setup_four_at_eight, 2320 }, 2321 { 2322 .vendor = PCI_VENDOR_ID_ACCESIO, 2323 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2324 .subvendor = PCI_ANY_ID, 2325 .subdevice = PCI_ANY_ID, 2326 .setup = pci_pericom_setup_four_at_eight, 2327 }, 2328 { 2329 .vendor = PCI_VENDOR_ID_ACCESIO, 2330 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2331 .subvendor = PCI_ANY_ID, 2332 .subdevice = PCI_ANY_ID, 2333 .setup = pci_pericom_setup_four_at_eight, 2334 }, 2335 { 2336 .vendor = PCI_VENDOR_ID_ACCESIO, 2337 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2338 .subvendor = PCI_ANY_ID, 2339 .subdevice = PCI_ANY_ID, 2340 .setup = pci_pericom_setup_four_at_eight, 2341 }, 2342 { 2343 .vendor = PCI_VENDOR_ID_ACCESIO, 2344 .device = PCI_ANY_ID, 2345 .subvendor = PCI_ANY_ID, 2346 .subdevice = PCI_ANY_ID, 2347 .setup = pci_pericom_setup, 2348 }, /* 2349 * SBS Technologies, Inc., PMC-OCTALPRO 232 2350 */ 2351 { 2352 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2353 .device = PCI_DEVICE_ID_OCTPRO, 2354 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2355 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2356 .init = sbs_init, 2357 .setup = sbs_setup, 2358 .exit = sbs_exit, 2359 }, 2360 /* 2361 * SBS Technologies, Inc., PMC-OCTALPRO 422 2362 */ 2363 { 2364 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2365 .device = PCI_DEVICE_ID_OCTPRO, 2366 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2367 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2368 .init = sbs_init, 2369 .setup = sbs_setup, 2370 .exit = sbs_exit, 2371 }, 2372 /* 2373 * SBS Technologies, Inc., P-Octal 232 2374 */ 2375 { 2376 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2377 .device = PCI_DEVICE_ID_OCTPRO, 2378 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2379 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2380 .init = sbs_init, 2381 .setup = sbs_setup, 2382 .exit = sbs_exit, 2383 }, 2384 /* 2385 * SBS Technologies, Inc., P-Octal 422 2386 */ 2387 { 2388 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2389 .device = PCI_DEVICE_ID_OCTPRO, 2390 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2391 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2392 .init = sbs_init, 2393 .setup = sbs_setup, 2394 .exit = sbs_exit, 2395 }, 2396 /* 2397 * SIIG cards - these may be called via parport_serial 2398 */ 2399 { 2400 .vendor = PCI_VENDOR_ID_SIIG, 2401 .device = PCI_ANY_ID, 2402 .subvendor = PCI_ANY_ID, 2403 .subdevice = PCI_ANY_ID, 2404 .init = pci_siig_init, 2405 .setup = pci_siig_setup, 2406 }, 2407 /* 2408 * Titan cards 2409 */ 2410 { 2411 .vendor = PCI_VENDOR_ID_TITAN, 2412 .device = PCI_DEVICE_ID_TITAN_400L, 2413 .subvendor = PCI_ANY_ID, 2414 .subdevice = PCI_ANY_ID, 2415 .setup = titan_400l_800l_setup, 2416 }, 2417 { 2418 .vendor = PCI_VENDOR_ID_TITAN, 2419 .device = PCI_DEVICE_ID_TITAN_800L, 2420 .subvendor = PCI_ANY_ID, 2421 .subdevice = PCI_ANY_ID, 2422 .setup = titan_400l_800l_setup, 2423 }, 2424 /* 2425 * Timedia cards 2426 */ 2427 { 2428 .vendor = PCI_VENDOR_ID_TIMEDIA, 2429 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2430 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2431 .subdevice = PCI_ANY_ID, 2432 .probe = pci_timedia_probe, 2433 .init = pci_timedia_init, 2434 .setup = pci_timedia_setup, 2435 }, 2436 { 2437 .vendor = PCI_VENDOR_ID_TIMEDIA, 2438 .device = PCI_ANY_ID, 2439 .subvendor = PCI_ANY_ID, 2440 .subdevice = PCI_ANY_ID, 2441 .setup = pci_timedia_setup, 2442 }, 2443 /* 2444 * Sunix PCI serial boards 2445 */ 2446 { 2447 .vendor = PCI_VENDOR_ID_SUNIX, 2448 .device = PCI_DEVICE_ID_SUNIX_1999, 2449 .subvendor = PCI_VENDOR_ID_SUNIX, 2450 .subdevice = PCI_ANY_ID, 2451 .setup = pci_sunix_setup, 2452 }, 2453 /* 2454 * Xircom cards 2455 */ 2456 { 2457 .vendor = PCI_VENDOR_ID_XIRCOM, 2458 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2459 .subvendor = PCI_ANY_ID, 2460 .subdevice = PCI_ANY_ID, 2461 .init = pci_xircom_init, 2462 .setup = pci_default_setup, 2463 }, 2464 /* 2465 * Netmos cards - these may be called via parport_serial 2466 */ 2467 { 2468 .vendor = PCI_VENDOR_ID_NETMOS, 2469 .device = PCI_ANY_ID, 2470 .subvendor = PCI_ANY_ID, 2471 .subdevice = PCI_ANY_ID, 2472 .init = pci_netmos_init, 2473 .setup = pci_netmos_9900_setup, 2474 }, 2475 /* 2476 * EndRun Technologies 2477 */ 2478 { 2479 .vendor = PCI_VENDOR_ID_ENDRUN, 2480 .device = PCI_ANY_ID, 2481 .subvendor = PCI_ANY_ID, 2482 .subdevice = PCI_ANY_ID, 2483 .init = pci_endrun_init, 2484 .setup = pci_default_setup, 2485 }, 2486 /* 2487 * For Oxford Semiconductor Tornado based devices 2488 */ 2489 { 2490 .vendor = PCI_VENDOR_ID_OXSEMI, 2491 .device = PCI_ANY_ID, 2492 .subvendor = PCI_ANY_ID, 2493 .subdevice = PCI_ANY_ID, 2494 .init = pci_oxsemi_tornado_init, 2495 .setup = pci_default_setup, 2496 }, 2497 { 2498 .vendor = PCI_VENDOR_ID_MAINPINE, 2499 .device = PCI_ANY_ID, 2500 .subvendor = PCI_ANY_ID, 2501 .subdevice = PCI_ANY_ID, 2502 .init = pci_oxsemi_tornado_init, 2503 .setup = pci_default_setup, 2504 }, 2505 { 2506 .vendor = PCI_VENDOR_ID_DIGI, 2507 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2508 .subvendor = PCI_SUBVENDOR_ID_IBM, 2509 .subdevice = PCI_ANY_ID, 2510 .init = pci_oxsemi_tornado_init, 2511 .setup = pci_default_setup, 2512 }, 2513 { 2514 .vendor = PCI_VENDOR_ID_INTEL, 2515 .device = 0x8811, 2516 .subvendor = PCI_ANY_ID, 2517 .subdevice = PCI_ANY_ID, 2518 .init = pci_eg20t_init, 2519 .setup = pci_default_setup, 2520 }, 2521 { 2522 .vendor = PCI_VENDOR_ID_INTEL, 2523 .device = 0x8812, 2524 .subvendor = PCI_ANY_ID, 2525 .subdevice = PCI_ANY_ID, 2526 .init = pci_eg20t_init, 2527 .setup = pci_default_setup, 2528 }, 2529 { 2530 .vendor = PCI_VENDOR_ID_INTEL, 2531 .device = 0x8813, 2532 .subvendor = PCI_ANY_ID, 2533 .subdevice = PCI_ANY_ID, 2534 .init = pci_eg20t_init, 2535 .setup = pci_default_setup, 2536 }, 2537 { 2538 .vendor = PCI_VENDOR_ID_INTEL, 2539 .device = 0x8814, 2540 .subvendor = PCI_ANY_ID, 2541 .subdevice = PCI_ANY_ID, 2542 .init = pci_eg20t_init, 2543 .setup = pci_default_setup, 2544 }, 2545 { 2546 .vendor = 0x10DB, 2547 .device = 0x8027, 2548 .subvendor = PCI_ANY_ID, 2549 .subdevice = PCI_ANY_ID, 2550 .init = pci_eg20t_init, 2551 .setup = pci_default_setup, 2552 }, 2553 { 2554 .vendor = 0x10DB, 2555 .device = 0x8028, 2556 .subvendor = PCI_ANY_ID, 2557 .subdevice = PCI_ANY_ID, 2558 .init = pci_eg20t_init, 2559 .setup = pci_default_setup, 2560 }, 2561 { 2562 .vendor = 0x10DB, 2563 .device = 0x8029, 2564 .subvendor = PCI_ANY_ID, 2565 .subdevice = PCI_ANY_ID, 2566 .init = pci_eg20t_init, 2567 .setup = pci_default_setup, 2568 }, 2569 { 2570 .vendor = 0x10DB, 2571 .device = 0x800C, 2572 .subvendor = PCI_ANY_ID, 2573 .subdevice = PCI_ANY_ID, 2574 .init = pci_eg20t_init, 2575 .setup = pci_default_setup, 2576 }, 2577 { 2578 .vendor = 0x10DB, 2579 .device = 0x800D, 2580 .subvendor = PCI_ANY_ID, 2581 .subdevice = PCI_ANY_ID, 2582 .init = pci_eg20t_init, 2583 .setup = pci_default_setup, 2584 }, 2585 /* 2586 * Cronyx Omega PCI (PLX-chip based) 2587 */ 2588 { 2589 .vendor = PCI_VENDOR_ID_PLX, 2590 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2591 .subvendor = PCI_ANY_ID, 2592 .subdevice = PCI_ANY_ID, 2593 .setup = pci_omegapci_setup, 2594 }, 2595 /* WCH CH353 1S1P card (16550 clone) */ 2596 { 2597 .vendor = PCI_VENDOR_ID_WCH, 2598 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .setup = pci_wch_ch353_setup, 2602 }, 2603 /* WCH CH353 2S1P card (16550 clone) */ 2604 { 2605 .vendor = PCI_VENDOR_ID_WCH, 2606 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .setup = pci_wch_ch353_setup, 2610 }, 2611 /* WCH CH353 4S card (16550 clone) */ 2612 { 2613 .vendor = PCI_VENDOR_ID_WCH, 2614 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .setup = pci_wch_ch353_setup, 2618 }, 2619 /* WCH CH353 2S1PF card (16550 clone) */ 2620 { 2621 .vendor = PCI_VENDOR_ID_WCH, 2622 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .setup = pci_wch_ch353_setup, 2626 }, 2627 /* WCH CH352 2S card (16550 clone) */ 2628 { 2629 .vendor = PCI_VENDOR_ID_WCH, 2630 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2631 .subvendor = PCI_ANY_ID, 2632 .subdevice = PCI_ANY_ID, 2633 .setup = pci_wch_ch353_setup, 2634 }, 2635 /* WCH CH355 4S card (16550 clone) */ 2636 { 2637 .vendor = PCI_VENDOR_ID_WCH, 2638 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .setup = pci_wch_ch355_setup, 2642 }, 2643 /* WCH CH382 2S card (16850 clone) */ 2644 { 2645 .vendor = PCIE_VENDOR_ID_WCH, 2646 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2647 .subvendor = PCI_ANY_ID, 2648 .subdevice = PCI_ANY_ID, 2649 .setup = pci_wch_ch38x_setup, 2650 }, 2651 /* WCH CH382 2S1P card (16850 clone) */ 2652 { 2653 .vendor = PCIE_VENDOR_ID_WCH, 2654 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2655 .subvendor = PCI_ANY_ID, 2656 .subdevice = PCI_ANY_ID, 2657 .setup = pci_wch_ch38x_setup, 2658 }, 2659 /* WCH CH384 4S card (16850 clone) */ 2660 { 2661 .vendor = PCIE_VENDOR_ID_WCH, 2662 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2663 .subvendor = PCI_ANY_ID, 2664 .subdevice = PCI_ANY_ID, 2665 .setup = pci_wch_ch38x_setup, 2666 }, 2667 /* WCH CH384 8S card (16850 clone) */ 2668 { 2669 .vendor = PCIE_VENDOR_ID_WCH, 2670 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2671 .subvendor = PCI_ANY_ID, 2672 .subdevice = PCI_ANY_ID, 2673 .init = pci_wch_ch38x_init, 2674 .exit = pci_wch_ch38x_exit, 2675 .setup = pci_wch_ch38x_setup, 2676 }, 2677 /* 2678 * ASIX devices with FIFO bug 2679 */ 2680 { 2681 .vendor = PCI_VENDOR_ID_ASIX, 2682 .device = PCI_ANY_ID, 2683 .subvendor = PCI_ANY_ID, 2684 .subdevice = PCI_ANY_ID, 2685 .setup = pci_asix_setup, 2686 }, 2687 /* 2688 * Broadcom TruManage (NetXtreme) 2689 */ 2690 { 2691 .vendor = PCI_VENDOR_ID_BROADCOM, 2692 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2693 .subvendor = PCI_ANY_ID, 2694 .subdevice = PCI_ANY_ID, 2695 .setup = pci_brcm_trumanage_setup, 2696 }, 2697 { 2698 .vendor = 0x1c29, 2699 .device = 0x1104, 2700 .subvendor = PCI_ANY_ID, 2701 .subdevice = PCI_ANY_ID, 2702 .setup = pci_fintek_setup, 2703 .init = pci_fintek_init, 2704 }, 2705 { 2706 .vendor = 0x1c29, 2707 .device = 0x1108, 2708 .subvendor = PCI_ANY_ID, 2709 .subdevice = PCI_ANY_ID, 2710 .setup = pci_fintek_setup, 2711 .init = pci_fintek_init, 2712 }, 2713 { 2714 .vendor = 0x1c29, 2715 .device = 0x1112, 2716 .subvendor = PCI_ANY_ID, 2717 .subdevice = PCI_ANY_ID, 2718 .setup = pci_fintek_setup, 2719 .init = pci_fintek_init, 2720 }, 2721 /* 2722 * MOXA 2723 */ 2724 { 2725 .vendor = PCI_VENDOR_ID_MOXA, 2726 .device = PCI_ANY_ID, 2727 .subvendor = PCI_ANY_ID, 2728 .subdevice = PCI_ANY_ID, 2729 .setup = pci_moxa_setup, 2730 }, 2731 { 2732 .vendor = 0x1c29, 2733 .device = 0x1204, 2734 .subvendor = PCI_ANY_ID, 2735 .subdevice = PCI_ANY_ID, 2736 .setup = pci_fintek_f815xxa_setup, 2737 .init = pci_fintek_f815xxa_init, 2738 }, 2739 { 2740 .vendor = 0x1c29, 2741 .device = 0x1208, 2742 .subvendor = PCI_ANY_ID, 2743 .subdevice = PCI_ANY_ID, 2744 .setup = pci_fintek_f815xxa_setup, 2745 .init = pci_fintek_f815xxa_init, 2746 }, 2747 { 2748 .vendor = 0x1c29, 2749 .device = 0x1212, 2750 .subvendor = PCI_ANY_ID, 2751 .subdevice = PCI_ANY_ID, 2752 .setup = pci_fintek_f815xxa_setup, 2753 .init = pci_fintek_f815xxa_init, 2754 }, 2755 2756 /* 2757 * Default "match everything" terminator entry 2758 */ 2759 { 2760 .vendor = PCI_ANY_ID, 2761 .device = PCI_ANY_ID, 2762 .subvendor = PCI_ANY_ID, 2763 .subdevice = PCI_ANY_ID, 2764 .setup = pci_default_setup, 2765 } 2766 }; 2767 2768 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2769 { 2770 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2771 } 2772 2773 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2774 { 2775 struct pci_serial_quirk *quirk; 2776 2777 for (quirk = pci_serial_quirks; ; quirk++) 2778 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2779 quirk_id_matches(quirk->device, dev->device) && 2780 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2781 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2782 break; 2783 return quirk; 2784 } 2785 2786 /* 2787 * This is the configuration table for all of the PCI serial boards 2788 * which we support. It is directly indexed by the pci_board_num_t enum 2789 * value, which is encoded in the pci_device_id PCI probe table's 2790 * driver_data member. 2791 * 2792 * The makeup of these names are: 2793 * pbn_bn{_bt}_n_baud{_offsetinhex} 2794 * 2795 * bn = PCI BAR number 2796 * bt = Index using PCI BARs 2797 * n = number of serial ports 2798 * baud = baud rate 2799 * offsetinhex = offset for each sequential port (in hex) 2800 * 2801 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2802 * 2803 * Please note: in theory if n = 1, _bt infix should make no difference. 2804 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2805 */ 2806 enum pci_board_num_t { 2807 pbn_default = 0, 2808 2809 pbn_b0_1_115200, 2810 pbn_b0_2_115200, 2811 pbn_b0_4_115200, 2812 pbn_b0_5_115200, 2813 pbn_b0_8_115200, 2814 2815 pbn_b0_1_921600, 2816 pbn_b0_2_921600, 2817 pbn_b0_4_921600, 2818 2819 pbn_b0_2_1130000, 2820 2821 pbn_b0_4_1152000, 2822 2823 pbn_b0_4_1250000, 2824 2825 pbn_b0_2_1843200, 2826 pbn_b0_4_1843200, 2827 2828 pbn_b0_1_3906250, 2829 2830 pbn_b0_bt_1_115200, 2831 pbn_b0_bt_2_115200, 2832 pbn_b0_bt_4_115200, 2833 pbn_b0_bt_8_115200, 2834 2835 pbn_b0_bt_1_460800, 2836 pbn_b0_bt_2_460800, 2837 pbn_b0_bt_4_460800, 2838 2839 pbn_b0_bt_1_921600, 2840 pbn_b0_bt_2_921600, 2841 pbn_b0_bt_4_921600, 2842 pbn_b0_bt_8_921600, 2843 2844 pbn_b1_1_115200, 2845 pbn_b1_2_115200, 2846 pbn_b1_4_115200, 2847 pbn_b1_8_115200, 2848 pbn_b1_16_115200, 2849 2850 pbn_b1_1_921600, 2851 pbn_b1_2_921600, 2852 pbn_b1_4_921600, 2853 pbn_b1_8_921600, 2854 2855 pbn_b1_2_1250000, 2856 2857 pbn_b1_bt_1_115200, 2858 pbn_b1_bt_2_115200, 2859 pbn_b1_bt_4_115200, 2860 2861 pbn_b1_bt_2_921600, 2862 2863 pbn_b1_1_1382400, 2864 pbn_b1_2_1382400, 2865 pbn_b1_4_1382400, 2866 pbn_b1_8_1382400, 2867 2868 pbn_b2_1_115200, 2869 pbn_b2_2_115200, 2870 pbn_b2_4_115200, 2871 pbn_b2_8_115200, 2872 2873 pbn_b2_1_460800, 2874 pbn_b2_4_460800, 2875 pbn_b2_8_460800, 2876 pbn_b2_16_460800, 2877 2878 pbn_b2_1_921600, 2879 pbn_b2_4_921600, 2880 pbn_b2_8_921600, 2881 2882 pbn_b2_8_1152000, 2883 2884 pbn_b2_bt_1_115200, 2885 pbn_b2_bt_2_115200, 2886 pbn_b2_bt_4_115200, 2887 2888 pbn_b2_bt_2_921600, 2889 pbn_b2_bt_4_921600, 2890 2891 pbn_b3_2_115200, 2892 pbn_b3_4_115200, 2893 pbn_b3_8_115200, 2894 2895 pbn_b4_bt_2_921600, 2896 pbn_b4_bt_4_921600, 2897 pbn_b4_bt_8_921600, 2898 2899 /* 2900 * Board-specific versions. 2901 */ 2902 pbn_panacom, 2903 pbn_panacom2, 2904 pbn_panacom4, 2905 pbn_plx_romulus, 2906 pbn_endrun_2_4000000, 2907 pbn_oxsemi, 2908 pbn_oxsemi_1_3906250, 2909 pbn_oxsemi_2_3906250, 2910 pbn_oxsemi_4_3906250, 2911 pbn_oxsemi_8_3906250, 2912 pbn_intel_i960, 2913 pbn_sgi_ioc3, 2914 pbn_computone_4, 2915 pbn_computone_6, 2916 pbn_computone_8, 2917 pbn_sbsxrsio, 2918 pbn_pasemi_1682M, 2919 pbn_ni8430_2, 2920 pbn_ni8430_4, 2921 pbn_ni8430_8, 2922 pbn_ni8430_16, 2923 pbn_ADDIDATA_PCIe_1_3906250, 2924 pbn_ADDIDATA_PCIe_2_3906250, 2925 pbn_ADDIDATA_PCIe_4_3906250, 2926 pbn_ADDIDATA_PCIe_8_3906250, 2927 pbn_ce4100_1_115200, 2928 pbn_omegapci, 2929 pbn_NETMOS9900_2s_115200, 2930 pbn_brcm_trumanage, 2931 pbn_fintek_4, 2932 pbn_fintek_8, 2933 pbn_fintek_12, 2934 pbn_fintek_F81504A, 2935 pbn_fintek_F81508A, 2936 pbn_fintek_F81512A, 2937 pbn_wch382_2, 2938 pbn_wch384_4, 2939 pbn_wch384_8, 2940 pbn_pericom_PI7C9X7951, 2941 pbn_pericom_PI7C9X7952, 2942 pbn_pericom_PI7C9X7954, 2943 pbn_pericom_PI7C9X7958, 2944 pbn_sunix_pci_1s, 2945 pbn_sunix_pci_2s, 2946 pbn_sunix_pci_4s, 2947 pbn_sunix_pci_8s, 2948 pbn_sunix_pci_16s, 2949 pbn_titan_1_4000000, 2950 pbn_titan_2_4000000, 2951 pbn_titan_4_4000000, 2952 pbn_titan_8_4000000, 2953 pbn_moxa8250_2p, 2954 pbn_moxa8250_4p, 2955 pbn_moxa8250_8p, 2956 }; 2957 2958 /* 2959 * uart_offset - the space between channels 2960 * reg_shift - describes how the UART registers are mapped 2961 * to PCI memory by the card. 2962 * For example IER register on SBS, Inc. PMC-OctPro is located at 2963 * offset 0x10 from the UART base, while UART_IER is defined as 1 2964 * in include/linux/serial_reg.h, 2965 * see first lines of serial_in() and serial_out() in 8250.c 2966 */ 2967 2968 static struct pciserial_board pci_boards[] = { 2969 [pbn_default] = { 2970 .flags = FL_BASE0, 2971 .num_ports = 1, 2972 .base_baud = 115200, 2973 .uart_offset = 8, 2974 }, 2975 [pbn_b0_1_115200] = { 2976 .flags = FL_BASE0, 2977 .num_ports = 1, 2978 .base_baud = 115200, 2979 .uart_offset = 8, 2980 }, 2981 [pbn_b0_2_115200] = { 2982 .flags = FL_BASE0, 2983 .num_ports = 2, 2984 .base_baud = 115200, 2985 .uart_offset = 8, 2986 }, 2987 [pbn_b0_4_115200] = { 2988 .flags = FL_BASE0, 2989 .num_ports = 4, 2990 .base_baud = 115200, 2991 .uart_offset = 8, 2992 }, 2993 [pbn_b0_5_115200] = { 2994 .flags = FL_BASE0, 2995 .num_ports = 5, 2996 .base_baud = 115200, 2997 .uart_offset = 8, 2998 }, 2999 [pbn_b0_8_115200] = { 3000 .flags = FL_BASE0, 3001 .num_ports = 8, 3002 .base_baud = 115200, 3003 .uart_offset = 8, 3004 }, 3005 [pbn_b0_1_921600] = { 3006 .flags = FL_BASE0, 3007 .num_ports = 1, 3008 .base_baud = 921600, 3009 .uart_offset = 8, 3010 }, 3011 [pbn_b0_2_921600] = { 3012 .flags = FL_BASE0, 3013 .num_ports = 2, 3014 .base_baud = 921600, 3015 .uart_offset = 8, 3016 }, 3017 [pbn_b0_4_921600] = { 3018 .flags = FL_BASE0, 3019 .num_ports = 4, 3020 .base_baud = 921600, 3021 .uart_offset = 8, 3022 }, 3023 3024 [pbn_b0_2_1130000] = { 3025 .flags = FL_BASE0, 3026 .num_ports = 2, 3027 .base_baud = 1130000, 3028 .uart_offset = 8, 3029 }, 3030 3031 [pbn_b0_4_1152000] = { 3032 .flags = FL_BASE0, 3033 .num_ports = 4, 3034 .base_baud = 1152000, 3035 .uart_offset = 8, 3036 }, 3037 3038 [pbn_b0_4_1250000] = { 3039 .flags = FL_BASE0, 3040 .num_ports = 4, 3041 .base_baud = 1250000, 3042 .uart_offset = 8, 3043 }, 3044 3045 [pbn_b0_2_1843200] = { 3046 .flags = FL_BASE0, 3047 .num_ports = 2, 3048 .base_baud = 1843200, 3049 .uart_offset = 8, 3050 }, 3051 [pbn_b0_4_1843200] = { 3052 .flags = FL_BASE0, 3053 .num_ports = 4, 3054 .base_baud = 1843200, 3055 .uart_offset = 8, 3056 }, 3057 3058 [pbn_b0_1_3906250] = { 3059 .flags = FL_BASE0, 3060 .num_ports = 1, 3061 .base_baud = 3906250, 3062 .uart_offset = 8, 3063 }, 3064 3065 [pbn_b0_bt_1_115200] = { 3066 .flags = FL_BASE0|FL_BASE_BARS, 3067 .num_ports = 1, 3068 .base_baud = 115200, 3069 .uart_offset = 8, 3070 }, 3071 [pbn_b0_bt_2_115200] = { 3072 .flags = FL_BASE0|FL_BASE_BARS, 3073 .num_ports = 2, 3074 .base_baud = 115200, 3075 .uart_offset = 8, 3076 }, 3077 [pbn_b0_bt_4_115200] = { 3078 .flags = FL_BASE0|FL_BASE_BARS, 3079 .num_ports = 4, 3080 .base_baud = 115200, 3081 .uart_offset = 8, 3082 }, 3083 [pbn_b0_bt_8_115200] = { 3084 .flags = FL_BASE0|FL_BASE_BARS, 3085 .num_ports = 8, 3086 .base_baud = 115200, 3087 .uart_offset = 8, 3088 }, 3089 3090 [pbn_b0_bt_1_460800] = { 3091 .flags = FL_BASE0|FL_BASE_BARS, 3092 .num_ports = 1, 3093 .base_baud = 460800, 3094 .uart_offset = 8, 3095 }, 3096 [pbn_b0_bt_2_460800] = { 3097 .flags = FL_BASE0|FL_BASE_BARS, 3098 .num_ports = 2, 3099 .base_baud = 460800, 3100 .uart_offset = 8, 3101 }, 3102 [pbn_b0_bt_4_460800] = { 3103 .flags = FL_BASE0|FL_BASE_BARS, 3104 .num_ports = 4, 3105 .base_baud = 460800, 3106 .uart_offset = 8, 3107 }, 3108 3109 [pbn_b0_bt_1_921600] = { 3110 .flags = FL_BASE0|FL_BASE_BARS, 3111 .num_ports = 1, 3112 .base_baud = 921600, 3113 .uart_offset = 8, 3114 }, 3115 [pbn_b0_bt_2_921600] = { 3116 .flags = FL_BASE0|FL_BASE_BARS, 3117 .num_ports = 2, 3118 .base_baud = 921600, 3119 .uart_offset = 8, 3120 }, 3121 [pbn_b0_bt_4_921600] = { 3122 .flags = FL_BASE0|FL_BASE_BARS, 3123 .num_ports = 4, 3124 .base_baud = 921600, 3125 .uart_offset = 8, 3126 }, 3127 [pbn_b0_bt_8_921600] = { 3128 .flags = FL_BASE0|FL_BASE_BARS, 3129 .num_ports = 8, 3130 .base_baud = 921600, 3131 .uart_offset = 8, 3132 }, 3133 3134 [pbn_b1_1_115200] = { 3135 .flags = FL_BASE1, 3136 .num_ports = 1, 3137 .base_baud = 115200, 3138 .uart_offset = 8, 3139 }, 3140 [pbn_b1_2_115200] = { 3141 .flags = FL_BASE1, 3142 .num_ports = 2, 3143 .base_baud = 115200, 3144 .uart_offset = 8, 3145 }, 3146 [pbn_b1_4_115200] = { 3147 .flags = FL_BASE1, 3148 .num_ports = 4, 3149 .base_baud = 115200, 3150 .uart_offset = 8, 3151 }, 3152 [pbn_b1_8_115200] = { 3153 .flags = FL_BASE1, 3154 .num_ports = 8, 3155 .base_baud = 115200, 3156 .uart_offset = 8, 3157 }, 3158 [pbn_b1_16_115200] = { 3159 .flags = FL_BASE1, 3160 .num_ports = 16, 3161 .base_baud = 115200, 3162 .uart_offset = 8, 3163 }, 3164 3165 [pbn_b1_1_921600] = { 3166 .flags = FL_BASE1, 3167 .num_ports = 1, 3168 .base_baud = 921600, 3169 .uart_offset = 8, 3170 }, 3171 [pbn_b1_2_921600] = { 3172 .flags = FL_BASE1, 3173 .num_ports = 2, 3174 .base_baud = 921600, 3175 .uart_offset = 8, 3176 }, 3177 [pbn_b1_4_921600] = { 3178 .flags = FL_BASE1, 3179 .num_ports = 4, 3180 .base_baud = 921600, 3181 .uart_offset = 8, 3182 }, 3183 [pbn_b1_8_921600] = { 3184 .flags = FL_BASE1, 3185 .num_ports = 8, 3186 .base_baud = 921600, 3187 .uart_offset = 8, 3188 }, 3189 [pbn_b1_2_1250000] = { 3190 .flags = FL_BASE1, 3191 .num_ports = 2, 3192 .base_baud = 1250000, 3193 .uart_offset = 8, 3194 }, 3195 3196 [pbn_b1_bt_1_115200] = { 3197 .flags = FL_BASE1|FL_BASE_BARS, 3198 .num_ports = 1, 3199 .base_baud = 115200, 3200 .uart_offset = 8, 3201 }, 3202 [pbn_b1_bt_2_115200] = { 3203 .flags = FL_BASE1|FL_BASE_BARS, 3204 .num_ports = 2, 3205 .base_baud = 115200, 3206 .uart_offset = 8, 3207 }, 3208 [pbn_b1_bt_4_115200] = { 3209 .flags = FL_BASE1|FL_BASE_BARS, 3210 .num_ports = 4, 3211 .base_baud = 115200, 3212 .uart_offset = 8, 3213 }, 3214 3215 [pbn_b1_bt_2_921600] = { 3216 .flags = FL_BASE1|FL_BASE_BARS, 3217 .num_ports = 2, 3218 .base_baud = 921600, 3219 .uart_offset = 8, 3220 }, 3221 3222 [pbn_b1_1_1382400] = { 3223 .flags = FL_BASE1, 3224 .num_ports = 1, 3225 .base_baud = 1382400, 3226 .uart_offset = 8, 3227 }, 3228 [pbn_b1_2_1382400] = { 3229 .flags = FL_BASE1, 3230 .num_ports = 2, 3231 .base_baud = 1382400, 3232 .uart_offset = 8, 3233 }, 3234 [pbn_b1_4_1382400] = { 3235 .flags = FL_BASE1, 3236 .num_ports = 4, 3237 .base_baud = 1382400, 3238 .uart_offset = 8, 3239 }, 3240 [pbn_b1_8_1382400] = { 3241 .flags = FL_BASE1, 3242 .num_ports = 8, 3243 .base_baud = 1382400, 3244 .uart_offset = 8, 3245 }, 3246 3247 [pbn_b2_1_115200] = { 3248 .flags = FL_BASE2, 3249 .num_ports = 1, 3250 .base_baud = 115200, 3251 .uart_offset = 8, 3252 }, 3253 [pbn_b2_2_115200] = { 3254 .flags = FL_BASE2, 3255 .num_ports = 2, 3256 .base_baud = 115200, 3257 .uart_offset = 8, 3258 }, 3259 [pbn_b2_4_115200] = { 3260 .flags = FL_BASE2, 3261 .num_ports = 4, 3262 .base_baud = 115200, 3263 .uart_offset = 8, 3264 }, 3265 [pbn_b2_8_115200] = { 3266 .flags = FL_BASE2, 3267 .num_ports = 8, 3268 .base_baud = 115200, 3269 .uart_offset = 8, 3270 }, 3271 3272 [pbn_b2_1_460800] = { 3273 .flags = FL_BASE2, 3274 .num_ports = 1, 3275 .base_baud = 460800, 3276 .uart_offset = 8, 3277 }, 3278 [pbn_b2_4_460800] = { 3279 .flags = FL_BASE2, 3280 .num_ports = 4, 3281 .base_baud = 460800, 3282 .uart_offset = 8, 3283 }, 3284 [pbn_b2_8_460800] = { 3285 .flags = FL_BASE2, 3286 .num_ports = 8, 3287 .base_baud = 460800, 3288 .uart_offset = 8, 3289 }, 3290 [pbn_b2_16_460800] = { 3291 .flags = FL_BASE2, 3292 .num_ports = 16, 3293 .base_baud = 460800, 3294 .uart_offset = 8, 3295 }, 3296 3297 [pbn_b2_1_921600] = { 3298 .flags = FL_BASE2, 3299 .num_ports = 1, 3300 .base_baud = 921600, 3301 .uart_offset = 8, 3302 }, 3303 [pbn_b2_4_921600] = { 3304 .flags = FL_BASE2, 3305 .num_ports = 4, 3306 .base_baud = 921600, 3307 .uart_offset = 8, 3308 }, 3309 [pbn_b2_8_921600] = { 3310 .flags = FL_BASE2, 3311 .num_ports = 8, 3312 .base_baud = 921600, 3313 .uart_offset = 8, 3314 }, 3315 3316 [pbn_b2_8_1152000] = { 3317 .flags = FL_BASE2, 3318 .num_ports = 8, 3319 .base_baud = 1152000, 3320 .uart_offset = 8, 3321 }, 3322 3323 [pbn_b2_bt_1_115200] = { 3324 .flags = FL_BASE2|FL_BASE_BARS, 3325 .num_ports = 1, 3326 .base_baud = 115200, 3327 .uart_offset = 8, 3328 }, 3329 [pbn_b2_bt_2_115200] = { 3330 .flags = FL_BASE2|FL_BASE_BARS, 3331 .num_ports = 2, 3332 .base_baud = 115200, 3333 .uart_offset = 8, 3334 }, 3335 [pbn_b2_bt_4_115200] = { 3336 .flags = FL_BASE2|FL_BASE_BARS, 3337 .num_ports = 4, 3338 .base_baud = 115200, 3339 .uart_offset = 8, 3340 }, 3341 3342 [pbn_b2_bt_2_921600] = { 3343 .flags = FL_BASE2|FL_BASE_BARS, 3344 .num_ports = 2, 3345 .base_baud = 921600, 3346 .uart_offset = 8, 3347 }, 3348 [pbn_b2_bt_4_921600] = { 3349 .flags = FL_BASE2|FL_BASE_BARS, 3350 .num_ports = 4, 3351 .base_baud = 921600, 3352 .uart_offset = 8, 3353 }, 3354 3355 [pbn_b3_2_115200] = { 3356 .flags = FL_BASE3, 3357 .num_ports = 2, 3358 .base_baud = 115200, 3359 .uart_offset = 8, 3360 }, 3361 [pbn_b3_4_115200] = { 3362 .flags = FL_BASE3, 3363 .num_ports = 4, 3364 .base_baud = 115200, 3365 .uart_offset = 8, 3366 }, 3367 [pbn_b3_8_115200] = { 3368 .flags = FL_BASE3, 3369 .num_ports = 8, 3370 .base_baud = 115200, 3371 .uart_offset = 8, 3372 }, 3373 3374 [pbn_b4_bt_2_921600] = { 3375 .flags = FL_BASE4, 3376 .num_ports = 2, 3377 .base_baud = 921600, 3378 .uart_offset = 8, 3379 }, 3380 [pbn_b4_bt_4_921600] = { 3381 .flags = FL_BASE4, 3382 .num_ports = 4, 3383 .base_baud = 921600, 3384 .uart_offset = 8, 3385 }, 3386 [pbn_b4_bt_8_921600] = { 3387 .flags = FL_BASE4, 3388 .num_ports = 8, 3389 .base_baud = 921600, 3390 .uart_offset = 8, 3391 }, 3392 3393 /* 3394 * Entries following this are board-specific. 3395 */ 3396 3397 /* 3398 * Panacom - IOMEM 3399 */ 3400 [pbn_panacom] = { 3401 .flags = FL_BASE2, 3402 .num_ports = 2, 3403 .base_baud = 921600, 3404 .uart_offset = 0x400, 3405 .reg_shift = 7, 3406 }, 3407 [pbn_panacom2] = { 3408 .flags = FL_BASE2|FL_BASE_BARS, 3409 .num_ports = 2, 3410 .base_baud = 921600, 3411 .uart_offset = 0x400, 3412 .reg_shift = 7, 3413 }, 3414 [pbn_panacom4] = { 3415 .flags = FL_BASE2|FL_BASE_BARS, 3416 .num_ports = 4, 3417 .base_baud = 921600, 3418 .uart_offset = 0x400, 3419 .reg_shift = 7, 3420 }, 3421 3422 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3423 [pbn_plx_romulus] = { 3424 .flags = FL_BASE2, 3425 .num_ports = 4, 3426 .base_baud = 921600, 3427 .uart_offset = 8 << 2, 3428 .reg_shift = 2, 3429 .first_offset = 0x03, 3430 }, 3431 3432 /* 3433 * EndRun Technologies 3434 * Uses the size of PCI Base region 0 to 3435 * signal now many ports are available 3436 * 2 port 952 Uart support 3437 */ 3438 [pbn_endrun_2_4000000] = { 3439 .flags = FL_BASE0, 3440 .num_ports = 2, 3441 .base_baud = 4000000, 3442 .uart_offset = 0x200, 3443 .first_offset = 0x1000, 3444 }, 3445 3446 /* 3447 * This board uses the size of PCI Base region 0 to 3448 * signal now many ports are available 3449 */ 3450 [pbn_oxsemi] = { 3451 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3452 .num_ports = 32, 3453 .base_baud = 115200, 3454 .uart_offset = 8, 3455 }, 3456 [pbn_oxsemi_1_3906250] = { 3457 .flags = FL_BASE0, 3458 .num_ports = 1, 3459 .base_baud = 3906250, 3460 .uart_offset = 0x200, 3461 .first_offset = 0x1000, 3462 }, 3463 [pbn_oxsemi_2_3906250] = { 3464 .flags = FL_BASE0, 3465 .num_ports = 2, 3466 .base_baud = 3906250, 3467 .uart_offset = 0x200, 3468 .first_offset = 0x1000, 3469 }, 3470 [pbn_oxsemi_4_3906250] = { 3471 .flags = FL_BASE0, 3472 .num_ports = 4, 3473 .base_baud = 3906250, 3474 .uart_offset = 0x200, 3475 .first_offset = 0x1000, 3476 }, 3477 [pbn_oxsemi_8_3906250] = { 3478 .flags = FL_BASE0, 3479 .num_ports = 8, 3480 .base_baud = 3906250, 3481 .uart_offset = 0x200, 3482 .first_offset = 0x1000, 3483 }, 3484 3485 3486 /* 3487 * EKF addition for i960 Boards form EKF with serial port. 3488 * Max 256 ports. 3489 */ 3490 [pbn_intel_i960] = { 3491 .flags = FL_BASE0, 3492 .num_ports = 32, 3493 .base_baud = 921600, 3494 .uart_offset = 8 << 2, 3495 .reg_shift = 2, 3496 .first_offset = 0x10000, 3497 }, 3498 [pbn_sgi_ioc3] = { 3499 .flags = FL_BASE0|FL_NOIRQ, 3500 .num_ports = 1, 3501 .base_baud = 458333, 3502 .uart_offset = 8, 3503 .reg_shift = 0, 3504 .first_offset = 0x20178, 3505 }, 3506 3507 /* 3508 * Computone - uses IOMEM. 3509 */ 3510 [pbn_computone_4] = { 3511 .flags = FL_BASE0, 3512 .num_ports = 4, 3513 .base_baud = 921600, 3514 .uart_offset = 0x40, 3515 .reg_shift = 2, 3516 .first_offset = 0x200, 3517 }, 3518 [pbn_computone_6] = { 3519 .flags = FL_BASE0, 3520 .num_ports = 6, 3521 .base_baud = 921600, 3522 .uart_offset = 0x40, 3523 .reg_shift = 2, 3524 .first_offset = 0x200, 3525 }, 3526 [pbn_computone_8] = { 3527 .flags = FL_BASE0, 3528 .num_ports = 8, 3529 .base_baud = 921600, 3530 .uart_offset = 0x40, 3531 .reg_shift = 2, 3532 .first_offset = 0x200, 3533 }, 3534 [pbn_sbsxrsio] = { 3535 .flags = FL_BASE0, 3536 .num_ports = 8, 3537 .base_baud = 460800, 3538 .uart_offset = 256, 3539 .reg_shift = 4, 3540 }, 3541 /* 3542 * PA Semi PWRficient PA6T-1682M on-chip UART 3543 */ 3544 [pbn_pasemi_1682M] = { 3545 .flags = FL_BASE0, 3546 .num_ports = 1, 3547 .base_baud = 8333333, 3548 }, 3549 /* 3550 * National Instruments 843x 3551 */ 3552 [pbn_ni8430_16] = { 3553 .flags = FL_BASE0, 3554 .num_ports = 16, 3555 .base_baud = 3686400, 3556 .uart_offset = 0x10, 3557 .first_offset = 0x800, 3558 }, 3559 [pbn_ni8430_8] = { 3560 .flags = FL_BASE0, 3561 .num_ports = 8, 3562 .base_baud = 3686400, 3563 .uart_offset = 0x10, 3564 .first_offset = 0x800, 3565 }, 3566 [pbn_ni8430_4] = { 3567 .flags = FL_BASE0, 3568 .num_ports = 4, 3569 .base_baud = 3686400, 3570 .uart_offset = 0x10, 3571 .first_offset = 0x800, 3572 }, 3573 [pbn_ni8430_2] = { 3574 .flags = FL_BASE0, 3575 .num_ports = 2, 3576 .base_baud = 3686400, 3577 .uart_offset = 0x10, 3578 .first_offset = 0x800, 3579 }, 3580 /* 3581 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3582 */ 3583 [pbn_ADDIDATA_PCIe_1_3906250] = { 3584 .flags = FL_BASE0, 3585 .num_ports = 1, 3586 .base_baud = 3906250, 3587 .uart_offset = 0x200, 3588 .first_offset = 0x1000, 3589 }, 3590 [pbn_ADDIDATA_PCIe_2_3906250] = { 3591 .flags = FL_BASE0, 3592 .num_ports = 2, 3593 .base_baud = 3906250, 3594 .uart_offset = 0x200, 3595 .first_offset = 0x1000, 3596 }, 3597 [pbn_ADDIDATA_PCIe_4_3906250] = { 3598 .flags = FL_BASE0, 3599 .num_ports = 4, 3600 .base_baud = 3906250, 3601 .uart_offset = 0x200, 3602 .first_offset = 0x1000, 3603 }, 3604 [pbn_ADDIDATA_PCIe_8_3906250] = { 3605 .flags = FL_BASE0, 3606 .num_ports = 8, 3607 .base_baud = 3906250, 3608 .uart_offset = 0x200, 3609 .first_offset = 0x1000, 3610 }, 3611 [pbn_ce4100_1_115200] = { 3612 .flags = FL_BASE_BARS, 3613 .num_ports = 2, 3614 .base_baud = 921600, 3615 .reg_shift = 2, 3616 }, 3617 [pbn_omegapci] = { 3618 .flags = FL_BASE0, 3619 .num_ports = 8, 3620 .base_baud = 115200, 3621 .uart_offset = 0x200, 3622 }, 3623 [pbn_NETMOS9900_2s_115200] = { 3624 .flags = FL_BASE0, 3625 .num_ports = 2, 3626 .base_baud = 115200, 3627 }, 3628 [pbn_brcm_trumanage] = { 3629 .flags = FL_BASE0, 3630 .num_ports = 1, 3631 .reg_shift = 2, 3632 .base_baud = 115200, 3633 }, 3634 [pbn_fintek_4] = { 3635 .num_ports = 4, 3636 .uart_offset = 8, 3637 .base_baud = 115200, 3638 .first_offset = 0x40, 3639 }, 3640 [pbn_fintek_8] = { 3641 .num_ports = 8, 3642 .uart_offset = 8, 3643 .base_baud = 115200, 3644 .first_offset = 0x40, 3645 }, 3646 [pbn_fintek_12] = { 3647 .num_ports = 12, 3648 .uart_offset = 8, 3649 .base_baud = 115200, 3650 .first_offset = 0x40, 3651 }, 3652 [pbn_fintek_F81504A] = { 3653 .num_ports = 4, 3654 .uart_offset = 8, 3655 .base_baud = 115200, 3656 }, 3657 [pbn_fintek_F81508A] = { 3658 .num_ports = 8, 3659 .uart_offset = 8, 3660 .base_baud = 115200, 3661 }, 3662 [pbn_fintek_F81512A] = { 3663 .num_ports = 12, 3664 .uart_offset = 8, 3665 .base_baud = 115200, 3666 }, 3667 [pbn_wch382_2] = { 3668 .flags = FL_BASE0, 3669 .num_ports = 2, 3670 .base_baud = 115200, 3671 .uart_offset = 8, 3672 .first_offset = 0xC0, 3673 }, 3674 [pbn_wch384_4] = { 3675 .flags = FL_BASE0, 3676 .num_ports = 4, 3677 .base_baud = 115200, 3678 .uart_offset = 8, 3679 .first_offset = 0xC0, 3680 }, 3681 [pbn_wch384_8] = { 3682 .flags = FL_BASE0, 3683 .num_ports = 8, 3684 .base_baud = 115200, 3685 .uart_offset = 8, 3686 .first_offset = 0x00, 3687 }, 3688 /* 3689 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3690 */ 3691 [pbn_pericom_PI7C9X7951] = { 3692 .flags = FL_BASE0, 3693 .num_ports = 1, 3694 .base_baud = 921600, 3695 .uart_offset = 0x8, 3696 }, 3697 [pbn_pericom_PI7C9X7952] = { 3698 .flags = FL_BASE0, 3699 .num_ports = 2, 3700 .base_baud = 921600, 3701 .uart_offset = 0x8, 3702 }, 3703 [pbn_pericom_PI7C9X7954] = { 3704 .flags = FL_BASE0, 3705 .num_ports = 4, 3706 .base_baud = 921600, 3707 .uart_offset = 0x8, 3708 }, 3709 [pbn_pericom_PI7C9X7958] = { 3710 .flags = FL_BASE0, 3711 .num_ports = 8, 3712 .base_baud = 921600, 3713 .uart_offset = 0x8, 3714 }, 3715 [pbn_sunix_pci_1s] = { 3716 .num_ports = 1, 3717 .base_baud = 921600, 3718 .uart_offset = 0x8, 3719 }, 3720 [pbn_sunix_pci_2s] = { 3721 .num_ports = 2, 3722 .base_baud = 921600, 3723 .uart_offset = 0x8, 3724 }, 3725 [pbn_sunix_pci_4s] = { 3726 .num_ports = 4, 3727 .base_baud = 921600, 3728 .uart_offset = 0x8, 3729 }, 3730 [pbn_sunix_pci_8s] = { 3731 .num_ports = 8, 3732 .base_baud = 921600, 3733 .uart_offset = 0x8, 3734 }, 3735 [pbn_sunix_pci_16s] = { 3736 .num_ports = 16, 3737 .base_baud = 921600, 3738 .uart_offset = 0x8, 3739 }, 3740 [pbn_titan_1_4000000] = { 3741 .flags = FL_BASE0, 3742 .num_ports = 1, 3743 .base_baud = 4000000, 3744 .uart_offset = 0x200, 3745 .first_offset = 0x1000, 3746 }, 3747 [pbn_titan_2_4000000] = { 3748 .flags = FL_BASE0, 3749 .num_ports = 2, 3750 .base_baud = 4000000, 3751 .uart_offset = 0x200, 3752 .first_offset = 0x1000, 3753 }, 3754 [pbn_titan_4_4000000] = { 3755 .flags = FL_BASE0, 3756 .num_ports = 4, 3757 .base_baud = 4000000, 3758 .uart_offset = 0x200, 3759 .first_offset = 0x1000, 3760 }, 3761 [pbn_titan_8_4000000] = { 3762 .flags = FL_BASE0, 3763 .num_ports = 8, 3764 .base_baud = 4000000, 3765 .uart_offset = 0x200, 3766 .first_offset = 0x1000, 3767 }, 3768 [pbn_moxa8250_2p] = { 3769 .flags = FL_BASE1, 3770 .num_ports = 2, 3771 .base_baud = 921600, 3772 .uart_offset = 0x200, 3773 }, 3774 [pbn_moxa8250_4p] = { 3775 .flags = FL_BASE1, 3776 .num_ports = 4, 3777 .base_baud = 921600, 3778 .uart_offset = 0x200, 3779 }, 3780 [pbn_moxa8250_8p] = { 3781 .flags = FL_BASE1, 3782 .num_ports = 8, 3783 .base_baud = 921600, 3784 .uart_offset = 0x200, 3785 }, 3786 }; 3787 3788 static const struct pci_device_id blacklist[] = { 3789 /* softmodems */ 3790 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3791 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3792 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3793 3794 /* multi-io cards handled by parport_serial */ 3795 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3796 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3797 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3798 3799 /* Intel platforms with MID UART */ 3800 { PCI_VDEVICE(INTEL, 0x081b), }, 3801 { PCI_VDEVICE(INTEL, 0x081c), }, 3802 { PCI_VDEVICE(INTEL, 0x081d), }, 3803 { PCI_VDEVICE(INTEL, 0x1191), }, 3804 { PCI_VDEVICE(INTEL, 0x18d8), }, 3805 { PCI_VDEVICE(INTEL, 0x19d8), }, 3806 3807 /* Intel platforms with DesignWare UART */ 3808 { PCI_VDEVICE(INTEL, 0x0936), }, 3809 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3810 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3811 { PCI_VDEVICE(INTEL, 0x228a), }, 3812 { PCI_VDEVICE(INTEL, 0x228c), }, 3813 { PCI_VDEVICE(INTEL, 0x4b96), }, 3814 { PCI_VDEVICE(INTEL, 0x4b97), }, 3815 { PCI_VDEVICE(INTEL, 0x4b98), }, 3816 { PCI_VDEVICE(INTEL, 0x4b99), }, 3817 { PCI_VDEVICE(INTEL, 0x4b9a), }, 3818 { PCI_VDEVICE(INTEL, 0x4b9b), }, 3819 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3820 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3821 3822 /* Exar devices */ 3823 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3824 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3825 3826 /* End of the black list */ 3827 { } 3828 }; 3829 3830 static int serial_pci_is_class_communication(struct pci_dev *dev) 3831 { 3832 /* 3833 * If it is not a communications device or the programming 3834 * interface is greater than 6, give up. 3835 */ 3836 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3837 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3838 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3839 (dev->class & 0xff) > 6) 3840 return -ENODEV; 3841 3842 return 0; 3843 } 3844 3845 /* 3846 * Given a complete unknown PCI device, try to use some heuristics to 3847 * guess what the configuration might be, based on the pitiful PCI 3848 * serial specs. Returns 0 on success, -ENODEV on failure. 3849 */ 3850 static int 3851 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3852 { 3853 int num_iomem, num_port, first_port = -1, i; 3854 int rc; 3855 3856 rc = serial_pci_is_class_communication(dev); 3857 if (rc) 3858 return rc; 3859 3860 /* 3861 * Should we try to make guesses for multiport serial devices later? 3862 */ 3863 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3864 return -ENODEV; 3865 3866 num_iomem = num_port = 0; 3867 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3868 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3869 num_port++; 3870 if (first_port == -1) 3871 first_port = i; 3872 } 3873 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3874 num_iomem++; 3875 } 3876 3877 /* 3878 * If there is 1 or 0 iomem regions, and exactly one port, 3879 * use it. We guess the number of ports based on the IO 3880 * region size. 3881 */ 3882 if (num_iomem <= 1 && num_port == 1) { 3883 board->flags = first_port; 3884 board->num_ports = pci_resource_len(dev, first_port) / 8; 3885 return 0; 3886 } 3887 3888 /* 3889 * Now guess if we've got a board which indexes by BARs. 3890 * Each IO BAR should be 8 bytes, and they should follow 3891 * consecutively. 3892 */ 3893 first_port = -1; 3894 num_port = 0; 3895 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3896 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3897 pci_resource_len(dev, i) == 8 && 3898 (first_port == -1 || (first_port + num_port) == i)) { 3899 num_port++; 3900 if (first_port == -1) 3901 first_port = i; 3902 } 3903 } 3904 3905 if (num_port > 1) { 3906 board->flags = first_port | FL_BASE_BARS; 3907 board->num_ports = num_port; 3908 return 0; 3909 } 3910 3911 return -ENODEV; 3912 } 3913 3914 static inline int 3915 serial_pci_matches(const struct pciserial_board *board, 3916 const struct pciserial_board *guessed) 3917 { 3918 return 3919 board->num_ports == guessed->num_ports && 3920 board->base_baud == guessed->base_baud && 3921 board->uart_offset == guessed->uart_offset && 3922 board->reg_shift == guessed->reg_shift && 3923 board->first_offset == guessed->first_offset; 3924 } 3925 3926 struct serial_private * 3927 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3928 { 3929 struct uart_8250_port uart; 3930 struct serial_private *priv; 3931 struct pci_serial_quirk *quirk; 3932 int rc, nr_ports, i; 3933 3934 nr_ports = board->num_ports; 3935 3936 /* 3937 * Find an init and setup quirks. 3938 */ 3939 quirk = find_quirk(dev); 3940 3941 /* 3942 * Run the new-style initialization function. 3943 * The initialization function returns: 3944 * <0 - error 3945 * 0 - use board->num_ports 3946 * >0 - number of ports 3947 */ 3948 if (quirk->init) { 3949 rc = quirk->init(dev); 3950 if (rc < 0) { 3951 priv = ERR_PTR(rc); 3952 goto err_out; 3953 } 3954 if (rc) 3955 nr_ports = rc; 3956 } 3957 3958 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3959 if (!priv) { 3960 priv = ERR_PTR(-ENOMEM); 3961 goto err_deinit; 3962 } 3963 3964 priv->dev = dev; 3965 priv->quirk = quirk; 3966 3967 memset(&uart, 0, sizeof(uart)); 3968 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3969 uart.port.uartclk = board->base_baud * 16; 3970 3971 if (board->flags & FL_NOIRQ) { 3972 uart.port.irq = 0; 3973 } else { 3974 if (pci_match_id(pci_use_msi, dev)) { 3975 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3976 pci_set_master(dev); 3977 uart.port.flags &= ~UPF_SHARE_IRQ; 3978 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3979 } else { 3980 pci_dbg(dev, "Using legacy interrupts\n"); 3981 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3982 } 3983 if (rc < 0) { 3984 kfree(priv); 3985 priv = ERR_PTR(rc); 3986 goto err_deinit; 3987 } 3988 3989 uart.port.irq = pci_irq_vector(dev, 0); 3990 } 3991 3992 uart.port.dev = &dev->dev; 3993 3994 for (i = 0; i < nr_ports; i++) { 3995 if (quirk->setup(priv, board, &uart, i)) 3996 break; 3997 3998 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3999 uart.port.iobase, uart.port.irq, uart.port.iotype); 4000 4001 priv->line[i] = serial8250_register_8250_port(&uart); 4002 if (priv->line[i] < 0) { 4003 pci_err(dev, 4004 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4005 uart.port.iobase, uart.port.irq, 4006 uart.port.iotype, priv->line[i]); 4007 break; 4008 } 4009 } 4010 priv->nr = i; 4011 priv->board = board; 4012 return priv; 4013 4014 err_deinit: 4015 if (quirk->exit) 4016 quirk->exit(dev); 4017 err_out: 4018 return priv; 4019 } 4020 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4021 4022 static void pciserial_detach_ports(struct serial_private *priv) 4023 { 4024 struct pci_serial_quirk *quirk; 4025 int i; 4026 4027 for (i = 0; i < priv->nr; i++) 4028 serial8250_unregister_port(priv->line[i]); 4029 4030 /* 4031 * Find the exit quirks. 4032 */ 4033 quirk = find_quirk(priv->dev); 4034 if (quirk->exit) 4035 quirk->exit(priv->dev); 4036 } 4037 4038 void pciserial_remove_ports(struct serial_private *priv) 4039 { 4040 pciserial_detach_ports(priv); 4041 kfree(priv); 4042 } 4043 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4044 4045 void pciserial_suspend_ports(struct serial_private *priv) 4046 { 4047 int i; 4048 4049 for (i = 0; i < priv->nr; i++) 4050 if (priv->line[i] >= 0) 4051 serial8250_suspend_port(priv->line[i]); 4052 4053 /* 4054 * Ensure that every init quirk is properly torn down 4055 */ 4056 if (priv->quirk->exit) 4057 priv->quirk->exit(priv->dev); 4058 } 4059 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4060 4061 void pciserial_resume_ports(struct serial_private *priv) 4062 { 4063 int i; 4064 4065 /* 4066 * Ensure that the board is correctly configured. 4067 */ 4068 if (priv->quirk->init) 4069 priv->quirk->init(priv->dev); 4070 4071 for (i = 0; i < priv->nr; i++) 4072 if (priv->line[i] >= 0) 4073 serial8250_resume_port(priv->line[i]); 4074 } 4075 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4076 4077 /* 4078 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4079 * to the arrangement of serial ports on a PCI card. 4080 */ 4081 static int 4082 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4083 { 4084 struct pci_serial_quirk *quirk; 4085 struct serial_private *priv; 4086 const struct pciserial_board *board; 4087 const struct pci_device_id *exclude; 4088 struct pciserial_board tmp; 4089 int rc; 4090 4091 quirk = find_quirk(dev); 4092 if (quirk->probe) { 4093 rc = quirk->probe(dev); 4094 if (rc) 4095 return rc; 4096 } 4097 4098 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4099 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4100 return -EINVAL; 4101 } 4102 4103 board = &pci_boards[ent->driver_data]; 4104 4105 exclude = pci_match_id(blacklist, dev); 4106 if (exclude) 4107 return -ENODEV; 4108 4109 rc = pcim_enable_device(dev); 4110 pci_save_state(dev); 4111 if (rc) 4112 return rc; 4113 4114 if (ent->driver_data == pbn_default) { 4115 /* 4116 * Use a copy of the pci_board entry for this; 4117 * avoid changing entries in the table. 4118 */ 4119 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4120 board = &tmp; 4121 4122 /* 4123 * We matched one of our class entries. Try to 4124 * determine the parameters of this board. 4125 */ 4126 rc = serial_pci_guess_board(dev, &tmp); 4127 if (rc) 4128 return rc; 4129 } else { 4130 /* 4131 * We matched an explicit entry. If we are able to 4132 * detect this boards settings with our heuristic, 4133 * then we no longer need this entry. 4134 */ 4135 memcpy(&tmp, &pci_boards[pbn_default], 4136 sizeof(struct pciserial_board)); 4137 rc = serial_pci_guess_board(dev, &tmp); 4138 if (rc == 0 && serial_pci_matches(board, &tmp)) 4139 moan_device("Redundant entry in serial pci_table.", 4140 dev); 4141 } 4142 4143 priv = pciserial_init_ports(dev, board); 4144 if (IS_ERR(priv)) 4145 return PTR_ERR(priv); 4146 4147 pci_set_drvdata(dev, priv); 4148 return 0; 4149 } 4150 4151 static void pciserial_remove_one(struct pci_dev *dev) 4152 { 4153 struct serial_private *priv = pci_get_drvdata(dev); 4154 4155 pciserial_remove_ports(priv); 4156 } 4157 4158 #ifdef CONFIG_PM_SLEEP 4159 static int pciserial_suspend_one(struct device *dev) 4160 { 4161 struct serial_private *priv = dev_get_drvdata(dev); 4162 4163 if (priv) 4164 pciserial_suspend_ports(priv); 4165 4166 return 0; 4167 } 4168 4169 static int pciserial_resume_one(struct device *dev) 4170 { 4171 struct pci_dev *pdev = to_pci_dev(dev); 4172 struct serial_private *priv = pci_get_drvdata(pdev); 4173 int err; 4174 4175 if (priv) { 4176 /* 4177 * The device may have been disabled. Re-enable it. 4178 */ 4179 err = pci_enable_device(pdev); 4180 /* FIXME: We cannot simply error out here */ 4181 if (err) 4182 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4183 pciserial_resume_ports(priv); 4184 } 4185 return 0; 4186 } 4187 #endif 4188 4189 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4190 pciserial_resume_one); 4191 4192 static const struct pci_device_id serial_pci_tbl[] = { 4193 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4194 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4195 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4196 pbn_b2_8_921600 }, 4197 /* Advantech also use 0x3618 and 0xf618 */ 4198 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4199 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4200 pbn_b0_4_921600 }, 4201 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4202 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4203 pbn_b0_4_921600 }, 4204 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4205 PCI_SUBVENDOR_ID_CONNECT_TECH, 4206 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4207 pbn_b1_8_1382400 }, 4208 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4209 PCI_SUBVENDOR_ID_CONNECT_TECH, 4210 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4211 pbn_b1_4_1382400 }, 4212 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4213 PCI_SUBVENDOR_ID_CONNECT_TECH, 4214 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4215 pbn_b1_2_1382400 }, 4216 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4217 PCI_SUBVENDOR_ID_CONNECT_TECH, 4218 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4219 pbn_b1_8_1382400 }, 4220 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4221 PCI_SUBVENDOR_ID_CONNECT_TECH, 4222 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4223 pbn_b1_4_1382400 }, 4224 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4225 PCI_SUBVENDOR_ID_CONNECT_TECH, 4226 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4227 pbn_b1_2_1382400 }, 4228 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4229 PCI_SUBVENDOR_ID_CONNECT_TECH, 4230 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4231 pbn_b1_8_921600 }, 4232 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4233 PCI_SUBVENDOR_ID_CONNECT_TECH, 4234 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4235 pbn_b1_8_921600 }, 4236 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4237 PCI_SUBVENDOR_ID_CONNECT_TECH, 4238 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4239 pbn_b1_4_921600 }, 4240 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4241 PCI_SUBVENDOR_ID_CONNECT_TECH, 4242 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4243 pbn_b1_4_921600 }, 4244 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4245 PCI_SUBVENDOR_ID_CONNECT_TECH, 4246 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4247 pbn_b1_2_921600 }, 4248 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4249 PCI_SUBVENDOR_ID_CONNECT_TECH, 4250 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4251 pbn_b1_8_921600 }, 4252 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4253 PCI_SUBVENDOR_ID_CONNECT_TECH, 4254 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4255 pbn_b1_8_921600 }, 4256 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4257 PCI_SUBVENDOR_ID_CONNECT_TECH, 4258 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4259 pbn_b1_4_921600 }, 4260 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4261 PCI_SUBVENDOR_ID_CONNECT_TECH, 4262 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4263 pbn_b1_2_1250000 }, 4264 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4265 PCI_SUBVENDOR_ID_CONNECT_TECH, 4266 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4267 pbn_b0_2_1843200 }, 4268 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4269 PCI_SUBVENDOR_ID_CONNECT_TECH, 4270 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4271 pbn_b0_4_1843200 }, 4272 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4273 PCI_VENDOR_ID_AFAVLAB, 4274 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4275 pbn_b0_4_1152000 }, 4276 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4278 pbn_b2_bt_1_115200 }, 4279 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4281 pbn_b2_bt_2_115200 }, 4282 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4284 pbn_b2_bt_4_115200 }, 4285 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4287 pbn_b2_bt_2_115200 }, 4288 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4290 pbn_b2_bt_4_115200 }, 4291 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_b2_8_115200 }, 4294 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_b2_8_460800 }, 4297 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4299 pbn_b2_8_115200 }, 4300 4301 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_b2_bt_2_115200 }, 4304 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_b2_bt_2_921600 }, 4307 /* 4308 * VScom SPCOM800, from sl@s.pl 4309 */ 4310 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4312 pbn_b2_8_921600 }, 4313 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_b2_4_921600 }, 4316 /* Unknown card - subdevice 0x1584 */ 4317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4318 PCI_VENDOR_ID_PLX, 4319 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4320 pbn_b2_4_115200 }, 4321 /* Unknown card - subdevice 0x1588 */ 4322 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4323 PCI_VENDOR_ID_PLX, 4324 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4325 pbn_b2_8_115200 }, 4326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4327 PCI_SUBVENDOR_ID_KEYSPAN, 4328 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4329 pbn_panacom }, 4330 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4332 pbn_panacom4 }, 4333 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4335 pbn_panacom2 }, 4336 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4337 PCI_VENDOR_ID_ESDGMBH, 4338 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4339 pbn_b2_4_115200 }, 4340 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4341 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4342 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4343 pbn_b2_4_460800 }, 4344 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4345 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4346 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4347 pbn_b2_8_460800 }, 4348 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4349 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4350 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4351 pbn_b2_16_460800 }, 4352 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4353 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4354 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4355 pbn_b2_16_460800 }, 4356 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4357 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4358 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4359 pbn_b2_4_460800 }, 4360 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4361 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4362 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4363 pbn_b2_8_460800 }, 4364 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4365 PCI_SUBVENDOR_ID_EXSYS, 4366 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4367 pbn_b2_4_115200 }, 4368 /* 4369 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4370 * (Exoray@isys.ca) 4371 */ 4372 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4373 0x10b5, 0x106a, 0, 0, 4374 pbn_plx_romulus }, 4375 /* 4376 * EndRun Technologies. PCI express device range. 4377 * EndRun PTP/1588 has 2 Native UARTs. 4378 */ 4379 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4381 pbn_endrun_2_4000000 }, 4382 /* 4383 * Quatech cards. These actually have configurable clocks but for 4384 * now we just use the default. 4385 * 4386 * 100 series are RS232, 200 series RS422, 4387 */ 4388 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_b1_4_115200 }, 4391 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4393 pbn_b1_2_115200 }, 4394 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4396 pbn_b2_2_115200 }, 4397 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4399 pbn_b1_2_115200 }, 4400 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4402 pbn_b2_2_115200 }, 4403 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4405 pbn_b1_4_115200 }, 4406 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4408 pbn_b1_8_115200 }, 4409 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_b1_8_115200 }, 4412 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b1_4_115200 }, 4415 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_b1_2_115200 }, 4418 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_b1_4_115200 }, 4421 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b1_2_115200 }, 4424 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_b2_4_115200 }, 4427 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_b2_2_115200 }, 4430 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_b2_1_115200 }, 4433 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_b2_4_115200 }, 4436 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_b2_2_115200 }, 4439 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_b2_1_115200 }, 4442 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_b0_8_115200 }, 4445 4446 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4447 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4448 0, 0, 4449 pbn_b0_4_921600 }, 4450 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4451 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4452 0, 0, 4453 pbn_b0_4_1152000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_b0_bt_2_921600 }, 4457 4458 /* 4459 * The below card is a little controversial since it is the 4460 * subject of a PCI vendor/device ID clash. (See 4461 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4462 * For now just used the hex ID 0x950a. 4463 */ 4464 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4465 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4466 0, 0, pbn_b0_2_115200 }, 4467 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4468 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4469 0, 0, pbn_b0_2_115200 }, 4470 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_b0_2_1130000 }, 4473 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4474 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4475 pbn_b0_1_921600 }, 4476 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_b0_4_115200 }, 4479 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b0_bt_2_921600 }, 4482 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_b2_8_1152000 }, 4485 4486 /* 4487 * Oxford Semiconductor Inc. Tornado PCI express device range. 4488 */ 4489 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_b0_1_3906250 }, 4492 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_b0_1_3906250 }, 4495 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_oxsemi_1_3906250 }, 4498 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_oxsemi_1_3906250 }, 4501 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_b0_1_3906250 }, 4504 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_b0_1_3906250 }, 4507 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_oxsemi_1_3906250 }, 4510 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_oxsemi_1_3906250 }, 4513 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4515 pbn_b0_1_3906250 }, 4516 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4518 pbn_b0_1_3906250 }, 4519 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4521 pbn_b0_1_3906250 }, 4522 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4524 pbn_b0_1_3906250 }, 4525 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4527 pbn_oxsemi_2_3906250 }, 4528 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4530 pbn_oxsemi_2_3906250 }, 4531 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4533 pbn_oxsemi_4_3906250 }, 4534 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4536 pbn_oxsemi_4_3906250 }, 4537 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_oxsemi_8_3906250 }, 4540 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4542 pbn_oxsemi_8_3906250 }, 4543 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4545 pbn_oxsemi_1_3906250 }, 4546 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4548 pbn_oxsemi_1_3906250 }, 4549 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_oxsemi_1_3906250 }, 4552 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4554 pbn_oxsemi_1_3906250 }, 4555 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4557 pbn_oxsemi_1_3906250 }, 4558 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4560 pbn_oxsemi_1_3906250 }, 4561 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4563 pbn_oxsemi_1_3906250 }, 4564 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4566 pbn_oxsemi_1_3906250 }, 4567 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4569 pbn_oxsemi_1_3906250 }, 4570 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4572 pbn_oxsemi_1_3906250 }, 4573 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4575 pbn_oxsemi_1_3906250 }, 4576 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4578 pbn_oxsemi_1_3906250 }, 4579 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_oxsemi_1_3906250 }, 4582 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_oxsemi_1_3906250 }, 4585 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4587 pbn_oxsemi_1_3906250 }, 4588 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4590 pbn_oxsemi_1_3906250 }, 4591 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_oxsemi_1_3906250 }, 4594 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4596 pbn_oxsemi_1_3906250 }, 4597 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_oxsemi_1_3906250 }, 4600 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_oxsemi_1_3906250 }, 4603 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4605 pbn_oxsemi_1_3906250 }, 4606 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_oxsemi_1_3906250 }, 4609 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_oxsemi_1_3906250 }, 4612 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_oxsemi_1_3906250 }, 4615 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4617 pbn_oxsemi_1_3906250 }, 4618 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4620 pbn_oxsemi_1_3906250 }, 4621 /* 4622 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4623 */ 4624 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4625 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4626 pbn_oxsemi_1_3906250 }, 4627 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4628 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4629 pbn_oxsemi_2_3906250 }, 4630 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4631 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4632 pbn_oxsemi_4_3906250 }, 4633 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4634 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4635 pbn_oxsemi_8_3906250 }, 4636 4637 /* 4638 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4639 */ 4640 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4641 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4642 pbn_oxsemi_2_3906250 }, 4643 4644 /* 4645 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4646 * from skokodyn@yahoo.com 4647 */ 4648 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4649 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4650 pbn_sbsxrsio }, 4651 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4652 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4653 pbn_sbsxrsio }, 4654 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4655 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4656 pbn_sbsxrsio }, 4657 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4658 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4659 pbn_sbsxrsio }, 4660 4661 /* 4662 * Digitan DS560-558, from jimd@esoft.com 4663 */ 4664 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b1_1_115200 }, 4667 4668 /* 4669 * Titan Electronic cards 4670 * The 400L and 800L have a custom setup quirk. 4671 */ 4672 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_b0_1_921600 }, 4675 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b0_2_921600 }, 4678 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b0_4_921600 }, 4681 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_b0_4_921600 }, 4684 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b1_1_921600 }, 4687 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b1_bt_2_921600 }, 4690 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_b0_bt_4_921600 }, 4693 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b0_bt_8_921600 }, 4696 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b4_bt_2_921600 }, 4699 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b4_bt_4_921600 }, 4702 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b4_bt_8_921600 }, 4705 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_4_921600 }, 4708 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_b0_4_921600 }, 4711 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_4_921600 }, 4714 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_titan_1_4000000 }, 4717 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4719 pbn_titan_2_4000000 }, 4720 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_titan_4_4000000 }, 4723 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_titan_8_4000000 }, 4726 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4728 pbn_titan_2_4000000 }, 4729 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4731 pbn_titan_2_4000000 }, 4732 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4734 pbn_b0_bt_2_921600 }, 4735 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4737 pbn_b0_4_921600 }, 4738 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4740 pbn_b0_4_921600 }, 4741 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_b0_4_921600 }, 4744 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_b0_4_921600 }, 4747 4748 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_b2_1_460800 }, 4751 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_b2_1_460800 }, 4754 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_b2_1_460800 }, 4757 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_b2_bt_2_921600 }, 4760 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_b2_bt_2_921600 }, 4763 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_b2_bt_2_921600 }, 4766 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_b2_bt_4_921600 }, 4769 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_b2_bt_4_921600 }, 4772 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_b2_bt_4_921600 }, 4775 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_b0_1_921600 }, 4778 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_b0_1_921600 }, 4781 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_b0_1_921600 }, 4784 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_b0_bt_2_921600 }, 4787 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_b0_bt_2_921600 }, 4790 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_b0_bt_2_921600 }, 4793 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_b0_bt_4_921600 }, 4796 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_b0_bt_4_921600 }, 4799 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_b0_bt_4_921600 }, 4802 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_b0_bt_8_921600 }, 4805 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_b0_bt_8_921600 }, 4808 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4810 pbn_b0_bt_8_921600 }, 4811 4812 /* 4813 * Computone devices submitted by Doug McNash dmcnash@computone.com 4814 */ 4815 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4816 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4817 0, 0, pbn_computone_4 }, 4818 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4819 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4820 0, 0, pbn_computone_8 }, 4821 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4822 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4823 0, 0, pbn_computone_6 }, 4824 4825 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4826 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4827 pbn_oxsemi }, 4828 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4829 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4830 pbn_b0_bt_1_921600 }, 4831 4832 /* 4833 * Sunix PCI serial boards 4834 */ 4835 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4836 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4837 pbn_sunix_pci_1s }, 4838 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4839 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4840 pbn_sunix_pci_2s }, 4841 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4842 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4843 pbn_sunix_pci_4s }, 4844 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4845 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4846 pbn_sunix_pci_4s }, 4847 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4848 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4849 pbn_sunix_pci_8s }, 4850 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4851 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4852 pbn_sunix_pci_8s }, 4853 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4854 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4855 pbn_sunix_pci_16s }, 4856 4857 /* 4858 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4859 */ 4860 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_bt_8_115200 }, 4863 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_bt_8_115200 }, 4866 4867 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4869 pbn_b0_bt_2_115200 }, 4870 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4871 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4872 pbn_b0_bt_2_115200 }, 4873 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4874 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4875 pbn_b0_bt_2_115200 }, 4876 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4877 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4878 pbn_b0_bt_2_115200 }, 4879 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4880 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4881 pbn_b0_bt_2_115200 }, 4882 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4883 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4884 pbn_b0_bt_4_460800 }, 4885 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4887 pbn_b0_bt_4_460800 }, 4888 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b0_bt_2_460800 }, 4891 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4893 pbn_b0_bt_2_460800 }, 4894 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4896 pbn_b0_bt_2_460800 }, 4897 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4899 pbn_b0_bt_1_115200 }, 4900 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4902 pbn_b0_bt_1_460800 }, 4903 4904 /* 4905 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4906 * Cards are identified by their subsystem vendor IDs, which 4907 * (in hex) match the model number. 4908 * 4909 * Note that JC140x are RS422/485 cards which require ox950 4910 * ACR = 0x10, and as such are not currently fully supported. 4911 */ 4912 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4913 0x1204, 0x0004, 0, 0, 4914 pbn_b0_4_921600 }, 4915 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4916 0x1208, 0x0004, 0, 0, 4917 pbn_b0_4_921600 }, 4918 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4919 0x1402, 0x0002, 0, 0, 4920 pbn_b0_2_921600 }, */ 4921 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4922 0x1404, 0x0004, 0, 0, 4923 pbn_b0_4_921600 }, */ 4924 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4925 0x1208, 0x0004, 0, 0, 4926 pbn_b0_4_921600 }, 4927 4928 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4929 0x1204, 0x0004, 0, 0, 4930 pbn_b0_4_921600 }, 4931 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4932 0x1208, 0x0004, 0, 0, 4933 pbn_b0_4_921600 }, 4934 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4935 0x1208, 0x0004, 0, 0, 4936 pbn_b0_4_921600 }, 4937 /* 4938 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4939 */ 4940 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b1_1_1382400 }, 4943 4944 /* 4945 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4946 */ 4947 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4949 pbn_b1_1_1382400 }, 4950 4951 /* 4952 * RAStel 2 port modem, gerg@moreton.com.au 4953 */ 4954 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4956 pbn_b2_bt_2_115200 }, 4957 4958 /* 4959 * EKF addition for i960 Boards form EKF with serial port 4960 */ 4961 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4962 0xE4BF, PCI_ANY_ID, 0, 0, 4963 pbn_intel_i960 }, 4964 4965 /* 4966 * Xircom Cardbus/Ethernet combos 4967 */ 4968 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4970 pbn_b0_1_115200 }, 4971 /* 4972 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4973 */ 4974 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4976 pbn_b0_1_115200 }, 4977 4978 /* 4979 * Untested PCI modems, sent in from various folks... 4980 */ 4981 4982 /* 4983 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4984 */ 4985 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4986 0x1048, 0x1500, 0, 0, 4987 pbn_b1_1_115200 }, 4988 4989 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4990 0xFF00, 0, 0, 0, 4991 pbn_sgi_ioc3 }, 4992 4993 /* 4994 * HP Diva card 4995 */ 4996 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4997 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4998 pbn_b1_1_115200 }, 4999 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5001 pbn_b0_5_115200 }, 5002 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5004 pbn_b2_1_115200 }, 5005 /* HPE PCI serial device */ 5006 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5008 pbn_b1_1_115200 }, 5009 5010 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_b3_2_115200 }, 5013 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_b3_4_115200 }, 5016 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_b3_8_115200 }, 5019 /* 5020 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5021 */ 5022 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5023 PCI_ANY_ID, PCI_ANY_ID, 5024 0, 5025 0, pbn_pericom_PI7C9X7951 }, 5026 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5027 PCI_ANY_ID, PCI_ANY_ID, 5028 0, 5029 0, pbn_pericom_PI7C9X7952 }, 5030 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5031 PCI_ANY_ID, PCI_ANY_ID, 5032 0, 5033 0, pbn_pericom_PI7C9X7954 }, 5034 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5035 PCI_ANY_ID, PCI_ANY_ID, 5036 0, 5037 0, pbn_pericom_PI7C9X7958 }, 5038 /* 5039 * ACCES I/O Products quad 5040 */ 5041 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5043 pbn_pericom_PI7C9X7952 }, 5044 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5046 pbn_pericom_PI7C9X7952 }, 5047 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5048 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5049 pbn_pericom_PI7C9X7954 }, 5050 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5052 pbn_pericom_PI7C9X7954 }, 5053 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5055 pbn_pericom_PI7C9X7952 }, 5056 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5058 pbn_pericom_PI7C9X7952 }, 5059 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5060 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5061 pbn_pericom_PI7C9X7954 }, 5062 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5063 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5064 pbn_pericom_PI7C9X7954 }, 5065 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5067 pbn_pericom_PI7C9X7952 }, 5068 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5070 pbn_pericom_PI7C9X7952 }, 5071 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5073 pbn_pericom_PI7C9X7954 }, 5074 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5076 pbn_pericom_PI7C9X7954 }, 5077 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5079 pbn_pericom_PI7C9X7951 }, 5080 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5082 pbn_pericom_PI7C9X7952 }, 5083 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5085 pbn_pericom_PI7C9X7952 }, 5086 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5088 pbn_pericom_PI7C9X7954 }, 5089 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5091 pbn_pericom_PI7C9X7954 }, 5092 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5094 pbn_pericom_PI7C9X7952 }, 5095 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5097 pbn_pericom_PI7C9X7954 }, 5098 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5100 pbn_pericom_PI7C9X7952 }, 5101 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5103 pbn_pericom_PI7C9X7952 }, 5104 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5106 pbn_pericom_PI7C9X7954 }, 5107 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5109 pbn_pericom_PI7C9X7954 }, 5110 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5112 pbn_pericom_PI7C9X7952 }, 5113 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5115 pbn_pericom_PI7C9X7954 }, 5116 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5118 pbn_pericom_PI7C9X7954 }, 5119 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5121 pbn_pericom_PI7C9X7958 }, 5122 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5124 pbn_pericom_PI7C9X7958 }, 5125 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5127 pbn_pericom_PI7C9X7954 }, 5128 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5130 pbn_pericom_PI7C9X7958 }, 5131 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5133 pbn_pericom_PI7C9X7954 }, 5134 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5136 pbn_pericom_PI7C9X7958 }, 5137 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5139 pbn_pericom_PI7C9X7954 }, 5140 /* 5141 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5142 */ 5143 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5145 pbn_b0_1_115200 }, 5146 /* 5147 * ITE 5148 */ 5149 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5150 PCI_ANY_ID, PCI_ANY_ID, 5151 0, 0, 5152 pbn_b1_bt_1_115200 }, 5153 5154 /* 5155 * IntaShield IS-200 5156 */ 5157 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5159 pbn_b2_2_115200 }, 5160 /* 5161 * IntaShield IS-400 5162 */ 5163 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5165 pbn_b2_4_115200 }, 5166 /* 5167 * BrainBoxes UC-260 5168 */ 5169 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5170 PCI_ANY_ID, PCI_ANY_ID, 5171 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5172 pbn_b2_4_115200 }, 5173 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5174 PCI_ANY_ID, PCI_ANY_ID, 5175 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5176 pbn_b2_4_115200 }, 5177 /* 5178 * Perle PCI-RAS cards 5179 */ 5180 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5181 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5182 0, 0, pbn_b2_4_921600 }, 5183 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5184 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5185 0, 0, pbn_b2_8_921600 }, 5186 5187 /* 5188 * Mainpine series cards: Fairly standard layout but fools 5189 * parts of the autodetect in some cases and uses otherwise 5190 * unmatched communications subclasses in the PCI Express case 5191 */ 5192 5193 { /* RockForceDUO */ 5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5195 PCI_VENDOR_ID_MAINPINE, 0x0200, 5196 0, 0, pbn_b0_2_115200 }, 5197 { /* RockForceQUATRO */ 5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5199 PCI_VENDOR_ID_MAINPINE, 0x0300, 5200 0, 0, pbn_b0_4_115200 }, 5201 { /* RockForceDUO+ */ 5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5203 PCI_VENDOR_ID_MAINPINE, 0x0400, 5204 0, 0, pbn_b0_2_115200 }, 5205 { /* RockForceQUATRO+ */ 5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5207 PCI_VENDOR_ID_MAINPINE, 0x0500, 5208 0, 0, pbn_b0_4_115200 }, 5209 { /* RockForce+ */ 5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5211 PCI_VENDOR_ID_MAINPINE, 0x0600, 5212 0, 0, pbn_b0_2_115200 }, 5213 { /* RockForce+ */ 5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5215 PCI_VENDOR_ID_MAINPINE, 0x0700, 5216 0, 0, pbn_b0_4_115200 }, 5217 { /* RockForceOCTO+ */ 5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5219 PCI_VENDOR_ID_MAINPINE, 0x0800, 5220 0, 0, pbn_b0_8_115200 }, 5221 { /* RockForceDUO+ */ 5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5223 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5224 0, 0, pbn_b0_2_115200 }, 5225 { /* RockForceQUARTRO+ */ 5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5227 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5228 0, 0, pbn_b0_4_115200 }, 5229 { /* RockForceOCTO+ */ 5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5231 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5232 0, 0, pbn_b0_8_115200 }, 5233 { /* RockForceD1 */ 5234 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5235 PCI_VENDOR_ID_MAINPINE, 0x2000, 5236 0, 0, pbn_b0_1_115200 }, 5237 { /* RockForceF1 */ 5238 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5239 PCI_VENDOR_ID_MAINPINE, 0x2100, 5240 0, 0, pbn_b0_1_115200 }, 5241 { /* RockForceD2 */ 5242 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5243 PCI_VENDOR_ID_MAINPINE, 0x2200, 5244 0, 0, pbn_b0_2_115200 }, 5245 { /* RockForceF2 */ 5246 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5247 PCI_VENDOR_ID_MAINPINE, 0x2300, 5248 0, 0, pbn_b0_2_115200 }, 5249 { /* RockForceD4 */ 5250 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5251 PCI_VENDOR_ID_MAINPINE, 0x2400, 5252 0, 0, pbn_b0_4_115200 }, 5253 { /* RockForceF4 */ 5254 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5255 PCI_VENDOR_ID_MAINPINE, 0x2500, 5256 0, 0, pbn_b0_4_115200 }, 5257 { /* RockForceD8 */ 5258 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5259 PCI_VENDOR_ID_MAINPINE, 0x2600, 5260 0, 0, pbn_b0_8_115200 }, 5261 { /* RockForceF8 */ 5262 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5263 PCI_VENDOR_ID_MAINPINE, 0x2700, 5264 0, 0, pbn_b0_8_115200 }, 5265 { /* IQ Express D1 */ 5266 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5267 PCI_VENDOR_ID_MAINPINE, 0x3000, 5268 0, 0, pbn_b0_1_115200 }, 5269 { /* IQ Express F1 */ 5270 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5271 PCI_VENDOR_ID_MAINPINE, 0x3100, 5272 0, 0, pbn_b0_1_115200 }, 5273 { /* IQ Express D2 */ 5274 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5275 PCI_VENDOR_ID_MAINPINE, 0x3200, 5276 0, 0, pbn_b0_2_115200 }, 5277 { /* IQ Express F2 */ 5278 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5279 PCI_VENDOR_ID_MAINPINE, 0x3300, 5280 0, 0, pbn_b0_2_115200 }, 5281 { /* IQ Express D4 */ 5282 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5283 PCI_VENDOR_ID_MAINPINE, 0x3400, 5284 0, 0, pbn_b0_4_115200 }, 5285 { /* IQ Express F4 */ 5286 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5287 PCI_VENDOR_ID_MAINPINE, 0x3500, 5288 0, 0, pbn_b0_4_115200 }, 5289 { /* IQ Express D8 */ 5290 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5291 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5292 0, 0, pbn_b0_8_115200 }, 5293 { /* IQ Express F8 */ 5294 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5295 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5296 0, 0, pbn_b0_8_115200 }, 5297 5298 5299 /* 5300 * PA Semi PA6T-1682M on-chip UART 5301 */ 5302 { PCI_VENDOR_ID_PASEMI, 0xa004, 5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5304 pbn_pasemi_1682M }, 5305 5306 /* 5307 * National Instruments 5308 */ 5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5311 pbn_b1_16_115200 }, 5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5314 pbn_b1_8_115200 }, 5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5317 pbn_b1_bt_4_115200 }, 5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5320 pbn_b1_bt_2_115200 }, 5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5323 pbn_b1_bt_4_115200 }, 5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5326 pbn_b1_bt_2_115200 }, 5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5329 pbn_b1_16_115200 }, 5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5332 pbn_b1_8_115200 }, 5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5335 pbn_b1_bt_4_115200 }, 5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5338 pbn_b1_bt_2_115200 }, 5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5341 pbn_b1_bt_4_115200 }, 5342 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5344 pbn_b1_bt_2_115200 }, 5345 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5347 pbn_ni8430_2 }, 5348 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5350 pbn_ni8430_2 }, 5351 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5353 pbn_ni8430_4 }, 5354 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5356 pbn_ni8430_4 }, 5357 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5359 pbn_ni8430_8 }, 5360 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5362 pbn_ni8430_8 }, 5363 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5365 pbn_ni8430_16 }, 5366 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5368 pbn_ni8430_16 }, 5369 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5371 pbn_ni8430_2 }, 5372 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5374 pbn_ni8430_2 }, 5375 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5377 pbn_ni8430_4 }, 5378 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5380 pbn_ni8430_4 }, 5381 5382 /* 5383 * MOXA 5384 */ 5385 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5387 pbn_moxa8250_2p }, 5388 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5390 pbn_moxa8250_2p }, 5391 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5393 pbn_moxa8250_4p }, 5394 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5396 pbn_moxa8250_4p }, 5397 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5399 pbn_moxa8250_8p }, 5400 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5402 pbn_moxa8250_8p }, 5403 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5405 pbn_moxa8250_8p }, 5406 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5408 pbn_moxa8250_8p }, 5409 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5411 pbn_moxa8250_2p }, 5412 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5414 pbn_moxa8250_4p }, 5415 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5417 pbn_moxa8250_8p }, 5418 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5420 pbn_moxa8250_8p }, 5421 5422 /* 5423 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5424 */ 5425 { PCI_VENDOR_ID_ADDIDATA, 5426 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5427 PCI_ANY_ID, 5428 PCI_ANY_ID, 5429 0, 5430 0, 5431 pbn_b0_4_115200 }, 5432 5433 { PCI_VENDOR_ID_ADDIDATA, 5434 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5435 PCI_ANY_ID, 5436 PCI_ANY_ID, 5437 0, 5438 0, 5439 pbn_b0_2_115200 }, 5440 5441 { PCI_VENDOR_ID_ADDIDATA, 5442 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5443 PCI_ANY_ID, 5444 PCI_ANY_ID, 5445 0, 5446 0, 5447 pbn_b0_1_115200 }, 5448 5449 { PCI_VENDOR_ID_AMCC, 5450 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5451 PCI_ANY_ID, 5452 PCI_ANY_ID, 5453 0, 5454 0, 5455 pbn_b1_8_115200 }, 5456 5457 { PCI_VENDOR_ID_ADDIDATA, 5458 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5459 PCI_ANY_ID, 5460 PCI_ANY_ID, 5461 0, 5462 0, 5463 pbn_b0_4_115200 }, 5464 5465 { PCI_VENDOR_ID_ADDIDATA, 5466 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5467 PCI_ANY_ID, 5468 PCI_ANY_ID, 5469 0, 5470 0, 5471 pbn_b0_2_115200 }, 5472 5473 { PCI_VENDOR_ID_ADDIDATA, 5474 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5475 PCI_ANY_ID, 5476 PCI_ANY_ID, 5477 0, 5478 0, 5479 pbn_b0_1_115200 }, 5480 5481 { PCI_VENDOR_ID_ADDIDATA, 5482 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5483 PCI_ANY_ID, 5484 PCI_ANY_ID, 5485 0, 5486 0, 5487 pbn_b0_4_115200 }, 5488 5489 { PCI_VENDOR_ID_ADDIDATA, 5490 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5491 PCI_ANY_ID, 5492 PCI_ANY_ID, 5493 0, 5494 0, 5495 pbn_b0_2_115200 }, 5496 5497 { PCI_VENDOR_ID_ADDIDATA, 5498 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5499 PCI_ANY_ID, 5500 PCI_ANY_ID, 5501 0, 5502 0, 5503 pbn_b0_1_115200 }, 5504 5505 { PCI_VENDOR_ID_ADDIDATA, 5506 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5507 PCI_ANY_ID, 5508 PCI_ANY_ID, 5509 0, 5510 0, 5511 pbn_b0_8_115200 }, 5512 5513 { PCI_VENDOR_ID_ADDIDATA, 5514 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5515 PCI_ANY_ID, 5516 PCI_ANY_ID, 5517 0, 5518 0, 5519 pbn_ADDIDATA_PCIe_4_3906250 }, 5520 5521 { PCI_VENDOR_ID_ADDIDATA, 5522 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5523 PCI_ANY_ID, 5524 PCI_ANY_ID, 5525 0, 5526 0, 5527 pbn_ADDIDATA_PCIe_2_3906250 }, 5528 5529 { PCI_VENDOR_ID_ADDIDATA, 5530 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5531 PCI_ANY_ID, 5532 PCI_ANY_ID, 5533 0, 5534 0, 5535 pbn_ADDIDATA_PCIe_1_3906250 }, 5536 5537 { PCI_VENDOR_ID_ADDIDATA, 5538 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5539 PCI_ANY_ID, 5540 PCI_ANY_ID, 5541 0, 5542 0, 5543 pbn_ADDIDATA_PCIe_8_3906250 }, 5544 5545 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5546 PCI_VENDOR_ID_IBM, 0x0299, 5547 0, 0, pbn_b0_bt_2_115200 }, 5548 5549 /* 5550 * other NetMos 9835 devices are most likely handled by the 5551 * parport_serial driver, check drivers/parport/parport_serial.c 5552 * before adding them here. 5553 */ 5554 5555 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5556 0xA000, 0x1000, 5557 0, 0, pbn_b0_1_115200 }, 5558 5559 /* the 9901 is a rebranded 9912 */ 5560 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5561 0xA000, 0x1000, 5562 0, 0, pbn_b0_1_115200 }, 5563 5564 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5565 0xA000, 0x1000, 5566 0, 0, pbn_b0_1_115200 }, 5567 5568 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5569 0xA000, 0x1000, 5570 0, 0, pbn_b0_1_115200 }, 5571 5572 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5573 0xA000, 0x1000, 5574 0, 0, pbn_b0_1_115200 }, 5575 5576 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5577 0xA000, 0x3002, 5578 0, 0, pbn_NETMOS9900_2s_115200 }, 5579 5580 /* 5581 * Best Connectivity and Rosewill PCI Multi I/O cards 5582 */ 5583 5584 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5585 0xA000, 0x1000, 5586 0, 0, pbn_b0_1_115200 }, 5587 5588 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5589 0xA000, 0x3002, 5590 0, 0, pbn_b0_bt_2_115200 }, 5591 5592 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5593 0xA000, 0x3004, 5594 0, 0, pbn_b0_bt_4_115200 }, 5595 /* Intel CE4100 */ 5596 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5598 pbn_ce4100_1_115200 }, 5599 5600 /* 5601 * Cronyx Omega PCI 5602 */ 5603 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5605 pbn_omegapci }, 5606 5607 /* 5608 * Broadcom TruManage 5609 */ 5610 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5612 pbn_brcm_trumanage }, 5613 5614 /* 5615 * AgeStar as-prs2-009 5616 */ 5617 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5618 PCI_ANY_ID, PCI_ANY_ID, 5619 0, 0, pbn_b0_bt_2_115200 }, 5620 5621 /* 5622 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5623 * so not listed here. 5624 */ 5625 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5626 PCI_ANY_ID, PCI_ANY_ID, 5627 0, 0, pbn_b0_bt_4_115200 }, 5628 5629 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5630 PCI_ANY_ID, PCI_ANY_ID, 5631 0, 0, pbn_b0_bt_2_115200 }, 5632 5633 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5634 PCI_ANY_ID, PCI_ANY_ID, 5635 0, 0, pbn_b0_bt_4_115200 }, 5636 5637 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5638 PCI_ANY_ID, PCI_ANY_ID, 5639 0, 0, pbn_wch382_2 }, 5640 5641 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5642 PCI_ANY_ID, PCI_ANY_ID, 5643 0, 0, pbn_wch384_4 }, 5644 5645 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5646 PCI_ANY_ID, PCI_ANY_ID, 5647 0, 0, pbn_wch384_8 }, 5648 /* 5649 * Realtek RealManage 5650 */ 5651 { PCI_VENDOR_ID_REALTEK, 0x816a, 5652 PCI_ANY_ID, PCI_ANY_ID, 5653 0, 0, pbn_b0_1_115200 }, 5654 5655 { PCI_VENDOR_ID_REALTEK, 0x816b, 5656 PCI_ANY_ID, PCI_ANY_ID, 5657 0, 0, pbn_b0_1_115200 }, 5658 5659 /* Fintek PCI serial cards */ 5660 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5661 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5662 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5663 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5664 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5665 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5666 5667 /* MKS Tenta SCOM-080x serial cards */ 5668 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5669 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5670 5671 /* Amazon PCI serial device */ 5672 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5673 5674 /* 5675 * These entries match devices with class COMMUNICATION_SERIAL, 5676 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5677 */ 5678 { PCI_ANY_ID, PCI_ANY_ID, 5679 PCI_ANY_ID, PCI_ANY_ID, 5680 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5681 0xffff00, pbn_default }, 5682 { PCI_ANY_ID, PCI_ANY_ID, 5683 PCI_ANY_ID, PCI_ANY_ID, 5684 PCI_CLASS_COMMUNICATION_MODEM << 8, 5685 0xffff00, pbn_default }, 5686 { PCI_ANY_ID, PCI_ANY_ID, 5687 PCI_ANY_ID, PCI_ANY_ID, 5688 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5689 0xffff00, pbn_default }, 5690 { 0, } 5691 }; 5692 5693 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5694 pci_channel_state_t state) 5695 { 5696 struct serial_private *priv = pci_get_drvdata(dev); 5697 5698 if (state == pci_channel_io_perm_failure) 5699 return PCI_ERS_RESULT_DISCONNECT; 5700 5701 if (priv) 5702 pciserial_detach_ports(priv); 5703 5704 pci_disable_device(dev); 5705 5706 return PCI_ERS_RESULT_NEED_RESET; 5707 } 5708 5709 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5710 { 5711 int rc; 5712 5713 rc = pci_enable_device(dev); 5714 5715 if (rc) 5716 return PCI_ERS_RESULT_DISCONNECT; 5717 5718 pci_restore_state(dev); 5719 pci_save_state(dev); 5720 5721 return PCI_ERS_RESULT_RECOVERED; 5722 } 5723 5724 static void serial8250_io_resume(struct pci_dev *dev) 5725 { 5726 struct serial_private *priv = pci_get_drvdata(dev); 5727 struct serial_private *new; 5728 5729 if (!priv) 5730 return; 5731 5732 new = pciserial_init_ports(dev, priv->board); 5733 if (!IS_ERR(new)) { 5734 pci_set_drvdata(dev, new); 5735 kfree(priv); 5736 } 5737 } 5738 5739 static const struct pci_error_handlers serial8250_err_handler = { 5740 .error_detected = serial8250_io_error_detected, 5741 .slot_reset = serial8250_io_slot_reset, 5742 .resume = serial8250_io_resume, 5743 }; 5744 5745 static struct pci_driver serial_pci_driver = { 5746 .name = "serial", 5747 .probe = pciserial_init_one, 5748 .remove = pciserial_remove_one, 5749 .driver = { 5750 .pm = &pciserial_pm_ops, 5751 }, 5752 .id_table = serial_pci_tbl, 5753 .err_handler = &serial8250_err_handler, 5754 }; 5755 5756 module_pci_driver(serial_pci_driver); 5757 5758 MODULE_LICENSE("GPL"); 5759 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5760 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5761