xref: /openbmc/linux/drivers/tty/serial/8250/8250_pci.c (revision fc28ab18)
1 /*
2  *  Probe module for 8250/16550-type PCI serial ports.
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License.
11  */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27 
28 #include "8250.h"
29 
30 /*
31  * init function returns:
32  *  > 0 - number of ports
33  *  = 0 - use board->num_ports
34  *  < 0 - error
35  */
36 struct pci_serial_quirk {
37 	u32	vendor;
38 	u32	device;
39 	u32	subvendor;
40 	u32	subdevice;
41 	int	(*probe)(struct pci_dev *dev);
42 	int	(*init)(struct pci_dev *dev);
43 	int	(*setup)(struct serial_private *,
44 			 const struct pciserial_board *,
45 			 struct uart_8250_port *, int);
46 	void	(*exit)(struct pci_dev *dev);
47 };
48 
49 #define PCI_NUM_BAR_RESOURCES	6
50 
51 struct serial_private {
52 	struct pci_dev		*dev;
53 	unsigned int		nr;
54 	struct pci_serial_quirk	*quirk;
55 	const struct pciserial_board *board;
56 	int			line[0];
57 };
58 
59 static int pci_default_setup(struct serial_private*,
60 	  const struct pciserial_board*, struct uart_8250_port *, int);
61 
62 static void moan_device(const char *str, struct pci_dev *dev)
63 {
64 	dev_err(&dev->dev,
65 	       "%s: %s\n"
66 	       "Please send the output of lspci -vv, this\n"
67 	       "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 	       "manufacturer and name of serial board or\n"
69 	       "modem board to <linux-serial@vger.kernel.org>.\n",
70 	       pci_name(dev), str, dev->vendor, dev->device,
71 	       dev->subsystem_vendor, dev->subsystem_device);
72 }
73 
74 static int
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 	   int bar, int offset, int regshift)
77 {
78 	struct pci_dev *dev = priv->dev;
79 
80 	if (bar >= PCI_NUM_BAR_RESOURCES)
81 		return -EINVAL;
82 
83 	if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 		if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
85 			return -ENOMEM;
86 
87 		port->port.iotype = UPIO_MEM;
88 		port->port.iobase = 0;
89 		port->port.mapbase = pci_resource_start(dev, bar) + offset;
90 		port->port.membase = pcim_iomap_table(dev)[bar] + offset;
91 		port->port.regshift = regshift;
92 	} else {
93 		port->port.iotype = UPIO_PORT;
94 		port->port.iobase = pci_resource_start(dev, bar) + offset;
95 		port->port.mapbase = 0;
96 		port->port.membase = NULL;
97 		port->port.regshift = 0;
98 	}
99 	return 0;
100 }
101 
102 /*
103  * ADDI-DATA GmbH communication cards <info@addi-data.com>
104  */
105 static int addidata_apci7800_setup(struct serial_private *priv,
106 				const struct pciserial_board *board,
107 				struct uart_8250_port *port, int idx)
108 {
109 	unsigned int bar = 0, offset = board->first_offset;
110 	bar = FL_GET_BASE(board->flags);
111 
112 	if (idx < 2) {
113 		offset += idx * board->uart_offset;
114 	} else if ((idx >= 2) && (idx < 4)) {
115 		bar += 1;
116 		offset += ((idx - 2) * board->uart_offset);
117 	} else if ((idx >= 4) && (idx < 6)) {
118 		bar += 2;
119 		offset += ((idx - 4) * board->uart_offset);
120 	} else if (idx >= 6) {
121 		bar += 3;
122 		offset += ((idx - 6) * board->uart_offset);
123 	}
124 
125 	return setup_port(priv, port, bar, offset, board->reg_shift);
126 }
127 
128 /*
129  * AFAVLAB uses a different mixture of BARs and offsets
130  * Not that ugly ;) -- HW
131  */
132 static int
133 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
134 	      struct uart_8250_port *port, int idx)
135 {
136 	unsigned int bar, offset = board->first_offset;
137 
138 	bar = FL_GET_BASE(board->flags);
139 	if (idx < 4)
140 		bar += idx;
141 	else {
142 		bar = 4;
143 		offset += (idx - 4) * board->uart_offset;
144 	}
145 
146 	return setup_port(priv, port, bar, offset, board->reg_shift);
147 }
148 
149 /*
150  * HP's Remote Management Console.  The Diva chip came in several
151  * different versions.  N-class, L2000 and A500 have two Diva chips, each
152  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
153  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
154  * one Diva chip, but it has been expanded to 5 UARTs.
155  */
156 static int pci_hp_diva_init(struct pci_dev *dev)
157 {
158 	int rc = 0;
159 
160 	switch (dev->subsystem_device) {
161 	case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
162 	case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
163 	case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
164 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
165 		rc = 3;
166 		break;
167 	case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
168 		rc = 2;
169 		break;
170 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
171 		rc = 4;
172 		break;
173 	case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
174 	case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
175 		rc = 1;
176 		break;
177 	}
178 
179 	return rc;
180 }
181 
182 /*
183  * HP's Diva chip puts the 4th/5th serial port further out, and
184  * some serial ports are supposed to be hidden on certain models.
185  */
186 static int
187 pci_hp_diva_setup(struct serial_private *priv,
188 		const struct pciserial_board *board,
189 		struct uart_8250_port *port, int idx)
190 {
191 	unsigned int offset = board->first_offset;
192 	unsigned int bar = FL_GET_BASE(board->flags);
193 
194 	switch (priv->dev->subsystem_device) {
195 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
196 		if (idx == 3)
197 			idx++;
198 		break;
199 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
200 		if (idx > 0)
201 			idx++;
202 		if (idx > 2)
203 			idx++;
204 		break;
205 	}
206 	if (idx > 2)
207 		offset = 0x18;
208 
209 	offset += idx * board->uart_offset;
210 
211 	return setup_port(priv, port, bar, offset, board->reg_shift);
212 }
213 
214 /*
215  * Added for EKF Intel i960 serial boards
216  */
217 static int pci_inteli960ni_init(struct pci_dev *dev)
218 {
219 	u32 oldval;
220 
221 	if (!(dev->subsystem_device & 0x1000))
222 		return -ENODEV;
223 
224 	/* is firmware started? */
225 	pci_read_config_dword(dev, 0x44, &oldval);
226 	if (oldval == 0x00001000L) { /* RESET value */
227 		dev_dbg(&dev->dev, "Local i960 firmware missing\n");
228 		return -ENODEV;
229 	}
230 	return 0;
231 }
232 
233 /*
234  * Some PCI serial cards using the PLX 9050 PCI interface chip require
235  * that the card interrupt be explicitly enabled or disabled.  This
236  * seems to be mainly needed on card using the PLX which also use I/O
237  * mapped memory.
238  */
239 static int pci_plx9050_init(struct pci_dev *dev)
240 {
241 	u8 irq_config;
242 	void __iomem *p;
243 
244 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
245 		moan_device("no memory in bar 0", dev);
246 		return 0;
247 	}
248 
249 	irq_config = 0x41;
250 	if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
251 	    dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
252 		irq_config = 0x43;
253 
254 	if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
255 	    (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
256 		/*
257 		 * As the megawolf cards have the int pins active
258 		 * high, and have 2 UART chips, both ints must be
259 		 * enabled on the 9050. Also, the UARTS are set in
260 		 * 16450 mode by default, so we have to enable the
261 		 * 16C950 'enhanced' mode so that we can use the
262 		 * deep FIFOs
263 		 */
264 		irq_config = 0x5b;
265 	/*
266 	 * enable/disable interrupts
267 	 */
268 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
269 	if (p == NULL)
270 		return -ENOMEM;
271 	writel(irq_config, p + 0x4c);
272 
273 	/*
274 	 * Read the register back to ensure that it took effect.
275 	 */
276 	readl(p + 0x4c);
277 	iounmap(p);
278 
279 	return 0;
280 }
281 
282 static void pci_plx9050_exit(struct pci_dev *dev)
283 {
284 	u8 __iomem *p;
285 
286 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
287 		return;
288 
289 	/*
290 	 * disable interrupts
291 	 */
292 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
293 	if (p != NULL) {
294 		writel(0, p + 0x4c);
295 
296 		/*
297 		 * Read the register back to ensure that it took effect.
298 		 */
299 		readl(p + 0x4c);
300 		iounmap(p);
301 	}
302 }
303 
304 #define NI8420_INT_ENABLE_REG	0x38
305 #define NI8420_INT_ENABLE_BIT	0x2000
306 
307 static void pci_ni8420_exit(struct pci_dev *dev)
308 {
309 	void __iomem *p;
310 	unsigned int bar = 0;
311 
312 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
313 		moan_device("no memory in bar", dev);
314 		return;
315 	}
316 
317 	p = pci_ioremap_bar(dev, bar);
318 	if (p == NULL)
319 		return;
320 
321 	/* Disable the CPU Interrupt */
322 	writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
323 	       p + NI8420_INT_ENABLE_REG);
324 	iounmap(p);
325 }
326 
327 
328 /* MITE registers */
329 #define MITE_IOWBSR1	0xc4
330 #define MITE_IOWCR1	0xf4
331 #define MITE_LCIMR1	0x08
332 #define MITE_LCIMR2	0x10
333 
334 #define MITE_LCIMR2_CLR_CPU_IE	(1 << 30)
335 
336 static void pci_ni8430_exit(struct pci_dev *dev)
337 {
338 	void __iomem *p;
339 	unsigned int bar = 0;
340 
341 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
342 		moan_device("no memory in bar", dev);
343 		return;
344 	}
345 
346 	p = pci_ioremap_bar(dev, bar);
347 	if (p == NULL)
348 		return;
349 
350 	/* Disable the CPU Interrupt */
351 	writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
352 	iounmap(p);
353 }
354 
355 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
356 static int
357 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
358 		struct uart_8250_port *port, int idx)
359 {
360 	unsigned int bar, offset = board->first_offset;
361 
362 	bar = 0;
363 
364 	if (idx < 4) {
365 		/* first four channels map to 0, 0x100, 0x200, 0x300 */
366 		offset += idx * board->uart_offset;
367 	} else if (idx < 8) {
368 		/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
369 		offset += idx * board->uart_offset + 0xC00;
370 	} else /* we have only 8 ports on PMC-OCTALPRO */
371 		return 1;
372 
373 	return setup_port(priv, port, bar, offset, board->reg_shift);
374 }
375 
376 /*
377 * This does initialization for PMC OCTALPRO cards:
378 * maps the device memory, resets the UARTs (needed, bc
379 * if the module is removed and inserted again, the card
380 * is in the sleep mode) and enables global interrupt.
381 */
382 
383 /* global control register offset for SBS PMC-OctalPro */
384 #define OCT_REG_CR_OFF		0x500
385 
386 static int sbs_init(struct pci_dev *dev)
387 {
388 	u8 __iomem *p;
389 
390 	p = pci_ioremap_bar(dev, 0);
391 
392 	if (p == NULL)
393 		return -ENOMEM;
394 	/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
395 	writeb(0x10, p + OCT_REG_CR_OFF);
396 	udelay(50);
397 	writeb(0x0, p + OCT_REG_CR_OFF);
398 
399 	/* Set bit-2 (INTENABLE) of Control Register */
400 	writeb(0x4, p + OCT_REG_CR_OFF);
401 	iounmap(p);
402 
403 	return 0;
404 }
405 
406 /*
407  * Disables the global interrupt of PMC-OctalPro
408  */
409 
410 static void sbs_exit(struct pci_dev *dev)
411 {
412 	u8 __iomem *p;
413 
414 	p = pci_ioremap_bar(dev, 0);
415 	/* FIXME: What if resource_len < OCT_REG_CR_OFF */
416 	if (p != NULL)
417 		writeb(0, p + OCT_REG_CR_OFF);
418 	iounmap(p);
419 }
420 
421 /*
422  * SIIG serial cards have an PCI interface chip which also controls
423  * the UART clocking frequency. Each UART can be clocked independently
424  * (except cards equipped with 4 UARTs) and initial clocking settings
425  * are stored in the EEPROM chip. It can cause problems because this
426  * version of serial driver doesn't support differently clocked UART's
427  * on single PCI card. To prevent this, initialization functions set
428  * high frequency clocking for all UART's on given card. It is safe (I
429  * hope) because it doesn't touch EEPROM settings to prevent conflicts
430  * with other OSes (like M$ DOS).
431  *
432  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
433  *
434  * There is two family of SIIG serial cards with different PCI
435  * interface chip and different configuration methods:
436  *     - 10x cards have control registers in IO and/or memory space;
437  *     - 20x cards have control registers in standard PCI configuration space.
438  *
439  * Note: all 10x cards have PCI device ids 0x10..
440  *       all 20x cards have PCI device ids 0x20..
441  *
442  * There are also Quartet Serial cards which use Oxford Semiconductor
443  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
444  *
445  * Note: some SIIG cards are probed by the parport_serial object.
446  */
447 
448 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
449 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
450 
451 static int pci_siig10x_init(struct pci_dev *dev)
452 {
453 	u16 data;
454 	void __iomem *p;
455 
456 	switch (dev->device & 0xfff8) {
457 	case PCI_DEVICE_ID_SIIG_1S_10x:	/* 1S */
458 		data = 0xffdf;
459 		break;
460 	case PCI_DEVICE_ID_SIIG_2S_10x:	/* 2S, 2S1P */
461 		data = 0xf7ff;
462 		break;
463 	default:			/* 1S1P, 4S */
464 		data = 0xfffb;
465 		break;
466 	}
467 
468 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
469 	if (p == NULL)
470 		return -ENOMEM;
471 
472 	writew(readw(p + 0x28) & data, p + 0x28);
473 	readw(p + 0x28);
474 	iounmap(p);
475 	return 0;
476 }
477 
478 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
479 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
480 
481 static int pci_siig20x_init(struct pci_dev *dev)
482 {
483 	u8 data;
484 
485 	/* Change clock frequency for the first UART. */
486 	pci_read_config_byte(dev, 0x6f, &data);
487 	pci_write_config_byte(dev, 0x6f, data & 0xef);
488 
489 	/* If this card has 2 UART, we have to do the same with second UART. */
490 	if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
491 	    ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
492 		pci_read_config_byte(dev, 0x73, &data);
493 		pci_write_config_byte(dev, 0x73, data & 0xef);
494 	}
495 	return 0;
496 }
497 
498 static int pci_siig_init(struct pci_dev *dev)
499 {
500 	unsigned int type = dev->device & 0xff00;
501 
502 	if (type == 0x1000)
503 		return pci_siig10x_init(dev);
504 	else if (type == 0x2000)
505 		return pci_siig20x_init(dev);
506 
507 	moan_device("Unknown SIIG card", dev);
508 	return -ENODEV;
509 }
510 
511 static int pci_siig_setup(struct serial_private *priv,
512 			  const struct pciserial_board *board,
513 			  struct uart_8250_port *port, int idx)
514 {
515 	unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
516 
517 	if (idx > 3) {
518 		bar = 4;
519 		offset = (idx - 4) * 8;
520 	}
521 
522 	return setup_port(priv, port, bar, offset, 0);
523 }
524 
525 /*
526  * Timedia has an explosion of boards, and to avoid the PCI table from
527  * growing *huge*, we use this function to collapse some 70 entries
528  * in the PCI table into one, for sanity's and compactness's sake.
529  */
530 static const unsigned short timedia_single_port[] = {
531 	0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
532 };
533 
534 static const unsigned short timedia_dual_port[] = {
535 	0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
536 	0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
537 	0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
538 	0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
539 	0xD079, 0
540 };
541 
542 static const unsigned short timedia_quad_port[] = {
543 	0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
544 	0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
545 	0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
546 	0xB157, 0
547 };
548 
549 static const unsigned short timedia_eight_port[] = {
550 	0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
551 	0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
552 };
553 
554 static const struct timedia_struct {
555 	int num;
556 	const unsigned short *ids;
557 } timedia_data[] = {
558 	{ 1, timedia_single_port },
559 	{ 2, timedia_dual_port },
560 	{ 4, timedia_quad_port },
561 	{ 8, timedia_eight_port }
562 };
563 
564 /*
565  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
566  * listing them individually, this driver merely grabs them all with
567  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
568  * and should be left free to be claimed by parport_serial instead.
569  */
570 static int pci_timedia_probe(struct pci_dev *dev)
571 {
572 	/*
573 	 * Check the third digit of the subdevice ID
574 	 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
575 	 */
576 	if ((dev->subsystem_device & 0x00f0) >= 0x70) {
577 		dev_info(&dev->dev,
578 			"ignoring Timedia subdevice %04x for parport_serial\n",
579 			dev->subsystem_device);
580 		return -ENODEV;
581 	}
582 
583 	return 0;
584 }
585 
586 static int pci_timedia_init(struct pci_dev *dev)
587 {
588 	const unsigned short *ids;
589 	int i, j;
590 
591 	for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
592 		ids = timedia_data[i].ids;
593 		for (j = 0; ids[j]; j++)
594 			if (dev->subsystem_device == ids[j])
595 				return timedia_data[i].num;
596 	}
597 	return 0;
598 }
599 
600 /*
601  * Timedia/SUNIX uses a mixture of BARs and offsets
602  * Ugh, this is ugly as all hell --- TYT
603  */
604 static int
605 pci_timedia_setup(struct serial_private *priv,
606 		  const struct pciserial_board *board,
607 		  struct uart_8250_port *port, int idx)
608 {
609 	unsigned int bar = 0, offset = board->first_offset;
610 
611 	switch (idx) {
612 	case 0:
613 		bar = 0;
614 		break;
615 	case 1:
616 		offset = board->uart_offset;
617 		bar = 0;
618 		break;
619 	case 2:
620 		bar = 1;
621 		break;
622 	case 3:
623 		offset = board->uart_offset;
624 		/* FALLTHROUGH */
625 	case 4: /* BAR 2 */
626 	case 5: /* BAR 3 */
627 	case 6: /* BAR 4 */
628 	case 7: /* BAR 5 */
629 		bar = idx - 2;
630 	}
631 
632 	return setup_port(priv, port, bar, offset, board->reg_shift);
633 }
634 
635 /*
636  * Some Titan cards are also a little weird
637  */
638 static int
639 titan_400l_800l_setup(struct serial_private *priv,
640 		      const struct pciserial_board *board,
641 		      struct uart_8250_port *port, int idx)
642 {
643 	unsigned int bar, offset = board->first_offset;
644 
645 	switch (idx) {
646 	case 0:
647 		bar = 1;
648 		break;
649 	case 1:
650 		bar = 2;
651 		break;
652 	default:
653 		bar = 4;
654 		offset = (idx - 2) * board->uart_offset;
655 	}
656 
657 	return setup_port(priv, port, bar, offset, board->reg_shift);
658 }
659 
660 static int pci_xircom_init(struct pci_dev *dev)
661 {
662 	msleep(100);
663 	return 0;
664 }
665 
666 static int pci_ni8420_init(struct pci_dev *dev)
667 {
668 	void __iomem *p;
669 	unsigned int bar = 0;
670 
671 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
672 		moan_device("no memory in bar", dev);
673 		return 0;
674 	}
675 
676 	p = pci_ioremap_bar(dev, bar);
677 	if (p == NULL)
678 		return -ENOMEM;
679 
680 	/* Enable CPU Interrupt */
681 	writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
682 	       p + NI8420_INT_ENABLE_REG);
683 
684 	iounmap(p);
685 	return 0;
686 }
687 
688 #define MITE_IOWBSR1_WSIZE	0xa
689 #define MITE_IOWBSR1_WIN_OFFSET	0x800
690 #define MITE_IOWBSR1_WENAB	(1 << 7)
691 #define MITE_LCIMR1_IO_IE_0	(1 << 24)
692 #define MITE_LCIMR2_SET_CPU_IE	(1 << 31)
693 #define MITE_IOWCR1_RAMSEL_MASK	0xfffffffe
694 
695 static int pci_ni8430_init(struct pci_dev *dev)
696 {
697 	void __iomem *p;
698 	struct pci_bus_region region;
699 	u32 device_window;
700 	unsigned int bar = 0;
701 
702 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
703 		moan_device("no memory in bar", dev);
704 		return 0;
705 	}
706 
707 	p = pci_ioremap_bar(dev, bar);
708 	if (p == NULL)
709 		return -ENOMEM;
710 
711 	/*
712 	 * Set device window address and size in BAR0, while acknowledging that
713 	 * the resource structure may contain a translated address that differs
714 	 * from the address the device responds to.
715 	 */
716 	pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
717 	device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
718 			| MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
719 	writel(device_window, p + MITE_IOWBSR1);
720 
721 	/* Set window access to go to RAMSEL IO address space */
722 	writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
723 	       p + MITE_IOWCR1);
724 
725 	/* Enable IO Bus Interrupt 0 */
726 	writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
727 
728 	/* Enable CPU Interrupt */
729 	writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
730 
731 	iounmap(p);
732 	return 0;
733 }
734 
735 /* UART Port Control Register */
736 #define NI8430_PORTCON	0x0f
737 #define NI8430_PORTCON_TXVR_ENABLE	(1 << 3)
738 
739 static int
740 pci_ni8430_setup(struct serial_private *priv,
741 		 const struct pciserial_board *board,
742 		 struct uart_8250_port *port, int idx)
743 {
744 	struct pci_dev *dev = priv->dev;
745 	void __iomem *p;
746 	unsigned int bar, offset = board->first_offset;
747 
748 	if (idx >= board->num_ports)
749 		return 1;
750 
751 	bar = FL_GET_BASE(board->flags);
752 	offset += idx * board->uart_offset;
753 
754 	p = pci_ioremap_bar(dev, bar);
755 	if (!p)
756 		return -ENOMEM;
757 
758 	/* enable the transceiver */
759 	writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
760 	       p + offset + NI8430_PORTCON);
761 
762 	iounmap(p);
763 
764 	return setup_port(priv, port, bar, offset, board->reg_shift);
765 }
766 
767 static int pci_netmos_9900_setup(struct serial_private *priv,
768 				const struct pciserial_board *board,
769 				struct uart_8250_port *port, int idx)
770 {
771 	unsigned int bar;
772 
773 	if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
774 	    (priv->dev->subsystem_device & 0xff00) == 0x3000) {
775 		/* netmos apparently orders BARs by datasheet layout, so serial
776 		 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
777 		 */
778 		bar = 3 * idx;
779 
780 		return setup_port(priv, port, bar, 0, board->reg_shift);
781 	} else {
782 		return pci_default_setup(priv, board, port, idx);
783 	}
784 }
785 
786 /* the 99xx series comes with a range of device IDs and a variety
787  * of capabilities:
788  *
789  * 9900 has varying capabilities and can cascade to sub-controllers
790  *   (cascading should be purely internal)
791  * 9904 is hardwired with 4 serial ports
792  * 9912 and 9922 are hardwired with 2 serial ports
793  */
794 static int pci_netmos_9900_numports(struct pci_dev *dev)
795 {
796 	unsigned int c = dev->class;
797 	unsigned int pi;
798 	unsigned short sub_serports;
799 
800 	pi = c & 0xff;
801 
802 	if (pi == 2)
803 		return 1;
804 
805 	if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
806 		/* two possibilities: 0x30ps encodes number of parallel and
807 		 * serial ports, or 0x1000 indicates *something*. This is not
808 		 * immediately obvious, since the 2s1p+4s configuration seems
809 		 * to offer all functionality on functions 0..2, while still
810 		 * advertising the same function 3 as the 4s+2s1p config.
811 		 */
812 		sub_serports = dev->subsystem_device & 0xf;
813 		if (sub_serports > 0)
814 			return sub_serports;
815 
816 		dev_err(&dev->dev,
817 			"NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
818 		return 0;
819 	}
820 
821 	moan_device("unknown NetMos/Mostech program interface", dev);
822 	return 0;
823 }
824 
825 static int pci_netmos_init(struct pci_dev *dev)
826 {
827 	/* subdevice 0x00PS means <P> parallel, <S> serial */
828 	unsigned int num_serial = dev->subsystem_device & 0xf;
829 
830 	if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
831 		(dev->device == PCI_DEVICE_ID_NETMOS_9865))
832 		return 0;
833 
834 	if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
835 			dev->subsystem_device == 0x0299)
836 		return 0;
837 
838 	switch (dev->device) { /* FALLTHROUGH on all */
839 	case PCI_DEVICE_ID_NETMOS_9904:
840 	case PCI_DEVICE_ID_NETMOS_9912:
841 	case PCI_DEVICE_ID_NETMOS_9922:
842 	case PCI_DEVICE_ID_NETMOS_9900:
843 		num_serial = pci_netmos_9900_numports(dev);
844 		break;
845 
846 	default:
847 		break;
848 	}
849 
850 	if (num_serial == 0) {
851 		moan_device("unknown NetMos/Mostech device", dev);
852 		return -ENODEV;
853 	}
854 
855 	return num_serial;
856 }
857 
858 /*
859  * These chips are available with optionally one parallel port and up to
860  * two serial ports. Unfortunately they all have the same product id.
861  *
862  * Basic configuration is done over a region of 32 I/O ports. The base
863  * ioport is called INTA or INTC, depending on docs/other drivers.
864  *
865  * The region of the 32 I/O ports is configured in POSIO0R...
866  */
867 
868 /* registers */
869 #define ITE_887x_MISCR		0x9c
870 #define ITE_887x_INTCBAR	0x78
871 #define ITE_887x_UARTBAR	0x7c
872 #define ITE_887x_PS0BAR		0x10
873 #define ITE_887x_POSIO0		0x60
874 
875 /* I/O space size */
876 #define ITE_887x_IOSIZE		32
877 /* I/O space size (bits 26-24; 8 bytes = 011b) */
878 #define ITE_887x_POSIO_IOSIZE_8		(3 << 24)
879 /* I/O space size (bits 26-24; 32 bytes = 101b) */
880 #define ITE_887x_POSIO_IOSIZE_32	(5 << 24)
881 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
882 #define ITE_887x_POSIO_SPEED		(3 << 29)
883 /* enable IO_Space bit */
884 #define ITE_887x_POSIO_ENABLE		(1 << 31)
885 
886 static int pci_ite887x_init(struct pci_dev *dev)
887 {
888 	/* inta_addr are the configuration addresses of the ITE */
889 	static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
890 							0x200, 0x280, 0 };
891 	int ret, i, type;
892 	struct resource *iobase = NULL;
893 	u32 miscr, uartbar, ioport;
894 
895 	/* search for the base-ioport */
896 	i = 0;
897 	while (inta_addr[i] && iobase == NULL) {
898 		iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
899 								"ite887x");
900 		if (iobase != NULL) {
901 			/* write POSIO0R - speed | size | ioport */
902 			pci_write_config_dword(dev, ITE_887x_POSIO0,
903 				ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
904 				ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
905 			/* write INTCBAR - ioport */
906 			pci_write_config_dword(dev, ITE_887x_INTCBAR,
907 								inta_addr[i]);
908 			ret = inb(inta_addr[i]);
909 			if (ret != 0xff) {
910 				/* ioport connected */
911 				break;
912 			}
913 			release_region(iobase->start, ITE_887x_IOSIZE);
914 			iobase = NULL;
915 		}
916 		i++;
917 	}
918 
919 	if (!inta_addr[i]) {
920 		dev_err(&dev->dev, "ite887x: could not find iobase\n");
921 		return -ENODEV;
922 	}
923 
924 	/* start of undocumented type checking (see parport_pc.c) */
925 	type = inb(iobase->start + 0x18) & 0x0f;
926 
927 	switch (type) {
928 	case 0x2:	/* ITE8871 (1P) */
929 	case 0xa:	/* ITE8875 (1P) */
930 		ret = 0;
931 		break;
932 	case 0xe:	/* ITE8872 (2S1P) */
933 		ret = 2;
934 		break;
935 	case 0x6:	/* ITE8873 (1S) */
936 		ret = 1;
937 		break;
938 	case 0x8:	/* ITE8874 (2S) */
939 		ret = 2;
940 		break;
941 	default:
942 		moan_device("Unknown ITE887x", dev);
943 		ret = -ENODEV;
944 	}
945 
946 	/* configure all serial ports */
947 	for (i = 0; i < ret; i++) {
948 		/* read the I/O port from the device */
949 		pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
950 								&ioport);
951 		ioport &= 0x0000FF00;	/* the actual base address */
952 		pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
953 			ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
954 			ITE_887x_POSIO_IOSIZE_8 | ioport);
955 
956 		/* write the ioport to the UARTBAR */
957 		pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
958 		uartbar &= ~(0xffff << (16 * i));	/* clear half the reg */
959 		uartbar |= (ioport << (16 * i));	/* set the ioport */
960 		pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
961 
962 		/* get current config */
963 		pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
964 		/* disable interrupts (UARTx_Routing[3:0]) */
965 		miscr &= ~(0xf << (12 - 4 * i));
966 		/* activate the UART (UARTx_En) */
967 		miscr |= 1 << (23 - i);
968 		/* write new config with activated UART */
969 		pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
970 	}
971 
972 	if (ret <= 0) {
973 		/* the device has no UARTs if we get here */
974 		release_region(iobase->start, ITE_887x_IOSIZE);
975 	}
976 
977 	return ret;
978 }
979 
980 static void pci_ite887x_exit(struct pci_dev *dev)
981 {
982 	u32 ioport;
983 	/* the ioport is bit 0-15 in POSIO0R */
984 	pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
985 	ioport &= 0xffff;
986 	release_region(ioport, ITE_887x_IOSIZE);
987 }
988 
989 /*
990  * EndRun Technologies.
991  * Determine the number of ports available on the device.
992  */
993 #define PCI_VENDOR_ID_ENDRUN			0x7401
994 #define PCI_DEVICE_ID_ENDRUN_1588	0xe100
995 
996 static int pci_endrun_init(struct pci_dev *dev)
997 {
998 	u8 __iomem *p;
999 	unsigned long deviceID;
1000 	unsigned int  number_uarts = 0;
1001 
1002 	/* EndRun device is all 0xexxx */
1003 	if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1004 		(dev->device & 0xf000) != 0xe000)
1005 		return 0;
1006 
1007 	p = pci_iomap(dev, 0, 5);
1008 	if (p == NULL)
1009 		return -ENOMEM;
1010 
1011 	deviceID = ioread32(p);
1012 	/* EndRun device */
1013 	if (deviceID == 0x07000200) {
1014 		number_uarts = ioread8(p + 4);
1015 		dev_dbg(&dev->dev,
1016 			"%d ports detected on EndRun PCI Express device\n",
1017 			number_uarts);
1018 	}
1019 	pci_iounmap(dev, p);
1020 	return number_uarts;
1021 }
1022 
1023 /*
1024  * Oxford Semiconductor Inc.
1025  * Check that device is part of the Tornado range of devices, then determine
1026  * the number of ports available on the device.
1027  */
1028 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1029 {
1030 	u8 __iomem *p;
1031 	unsigned long deviceID;
1032 	unsigned int  number_uarts = 0;
1033 
1034 	/* OxSemi Tornado devices are all 0xCxxx */
1035 	if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1036 	    (dev->device & 0xF000) != 0xC000)
1037 		return 0;
1038 
1039 	p = pci_iomap(dev, 0, 5);
1040 	if (p == NULL)
1041 		return -ENOMEM;
1042 
1043 	deviceID = ioread32(p);
1044 	/* Tornado device */
1045 	if (deviceID == 0x07000200) {
1046 		number_uarts = ioread8(p + 4);
1047 		dev_dbg(&dev->dev,
1048 			"%d ports detected on Oxford PCI Express device\n",
1049 			number_uarts);
1050 	}
1051 	pci_iounmap(dev, p);
1052 	return number_uarts;
1053 }
1054 
1055 static int pci_asix_setup(struct serial_private *priv,
1056 		  const struct pciserial_board *board,
1057 		  struct uart_8250_port *port, int idx)
1058 {
1059 	port->bugs |= UART_BUG_PARITY;
1060 	return pci_default_setup(priv, board, port, idx);
1061 }
1062 
1063 /* Quatech devices have their own extra interface features */
1064 
1065 struct quatech_feature {
1066 	u16 devid;
1067 	bool amcc;
1068 };
1069 
1070 #define QPCR_TEST_FOR1		0x3F
1071 #define QPCR_TEST_GET1		0x00
1072 #define QPCR_TEST_FOR2		0x40
1073 #define QPCR_TEST_GET2		0x40
1074 #define QPCR_TEST_FOR3		0x80
1075 #define QPCR_TEST_GET3		0x40
1076 #define QPCR_TEST_FOR4		0xC0
1077 #define QPCR_TEST_GET4		0x80
1078 
1079 #define QOPR_CLOCK_X1		0x0000
1080 #define QOPR_CLOCK_X2		0x0001
1081 #define QOPR_CLOCK_X4		0x0002
1082 #define QOPR_CLOCK_X8		0x0003
1083 #define QOPR_CLOCK_RATE_MASK	0x0003
1084 
1085 
1086 static struct quatech_feature quatech_cards[] = {
1087 	{ PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1088 	{ PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1089 	{ PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1090 	{ PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1091 	{ PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1092 	{ PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1093 	{ PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1094 	{ PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1095 	{ PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1096 	{ PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1097 	{ PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1098 	{ PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1099 	{ PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1100 	{ PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1101 	{ PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1102 	{ PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1103 	{ PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1104 	{ PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1105 	{ PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1106 	{ 0, }
1107 };
1108 
1109 static int pci_quatech_amcc(u16 devid)
1110 {
1111 	struct quatech_feature *qf = &quatech_cards[0];
1112 	while (qf->devid) {
1113 		if (qf->devid == devid)
1114 			return qf->amcc;
1115 		qf++;
1116 	}
1117 	pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1118 	return 0;
1119 };
1120 
1121 static int pci_quatech_rqopr(struct uart_8250_port *port)
1122 {
1123 	unsigned long base = port->port.iobase;
1124 	u8 LCR, val;
1125 
1126 	LCR = inb(base + UART_LCR);
1127 	outb(0xBF, base + UART_LCR);
1128 	val = inb(base + UART_SCR);
1129 	outb(LCR, base + UART_LCR);
1130 	return val;
1131 }
1132 
1133 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1134 {
1135 	unsigned long base = port->port.iobase;
1136 	u8 LCR;
1137 
1138 	LCR = inb(base + UART_LCR);
1139 	outb(0xBF, base + UART_LCR);
1140 	inb(base + UART_SCR);
1141 	outb(qopr, base + UART_SCR);
1142 	outb(LCR, base + UART_LCR);
1143 }
1144 
1145 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1146 {
1147 	unsigned long base = port->port.iobase;
1148 	u8 LCR, val, qmcr;
1149 
1150 	LCR = inb(base + UART_LCR);
1151 	outb(0xBF, base + UART_LCR);
1152 	val = inb(base + UART_SCR);
1153 	outb(val | 0x10, base + UART_SCR);
1154 	qmcr = inb(base + UART_MCR);
1155 	outb(val, base + UART_SCR);
1156 	outb(LCR, base + UART_LCR);
1157 
1158 	return qmcr;
1159 }
1160 
1161 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1162 {
1163 	unsigned long base = port->port.iobase;
1164 	u8 LCR, val;
1165 
1166 	LCR = inb(base + UART_LCR);
1167 	outb(0xBF, base + UART_LCR);
1168 	val = inb(base + UART_SCR);
1169 	outb(val | 0x10, base + UART_SCR);
1170 	outb(qmcr, base + UART_MCR);
1171 	outb(val, base + UART_SCR);
1172 	outb(LCR, base + UART_LCR);
1173 }
1174 
1175 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1176 {
1177 	unsigned long base = port->port.iobase;
1178 	u8 LCR, val;
1179 
1180 	LCR = inb(base + UART_LCR);
1181 	outb(0xBF, base + UART_LCR);
1182 	val = inb(base + UART_SCR);
1183 	if (val & 0x20) {
1184 		outb(0x80, UART_LCR);
1185 		if (!(inb(UART_SCR) & 0x20)) {
1186 			outb(LCR, base + UART_LCR);
1187 			return 1;
1188 		}
1189 	}
1190 	return 0;
1191 }
1192 
1193 static int pci_quatech_test(struct uart_8250_port *port)
1194 {
1195 	u8 reg, qopr;
1196 
1197 	qopr = pci_quatech_rqopr(port);
1198 	pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1199 	reg = pci_quatech_rqopr(port) & 0xC0;
1200 	if (reg != QPCR_TEST_GET1)
1201 		return -EINVAL;
1202 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1203 	reg = pci_quatech_rqopr(port) & 0xC0;
1204 	if (reg != QPCR_TEST_GET2)
1205 		return -EINVAL;
1206 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1207 	reg = pci_quatech_rqopr(port) & 0xC0;
1208 	if (reg != QPCR_TEST_GET3)
1209 		return -EINVAL;
1210 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1211 	reg = pci_quatech_rqopr(port) & 0xC0;
1212 	if (reg != QPCR_TEST_GET4)
1213 		return -EINVAL;
1214 
1215 	pci_quatech_wqopr(port, qopr);
1216 	return 0;
1217 }
1218 
1219 static int pci_quatech_clock(struct uart_8250_port *port)
1220 {
1221 	u8 qopr, reg, set;
1222 	unsigned long clock;
1223 
1224 	if (pci_quatech_test(port) < 0)
1225 		return 1843200;
1226 
1227 	qopr = pci_quatech_rqopr(port);
1228 
1229 	pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1230 	reg = pci_quatech_rqopr(port);
1231 	if (reg & QOPR_CLOCK_X8) {
1232 		clock = 1843200;
1233 		goto out;
1234 	}
1235 	pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1236 	reg = pci_quatech_rqopr(port);
1237 	if (!(reg & QOPR_CLOCK_X8)) {
1238 		clock = 1843200;
1239 		goto out;
1240 	}
1241 	reg &= QOPR_CLOCK_X8;
1242 	if (reg == QOPR_CLOCK_X2) {
1243 		clock =  3685400;
1244 		set = QOPR_CLOCK_X2;
1245 	} else if (reg == QOPR_CLOCK_X4) {
1246 		clock = 7372800;
1247 		set = QOPR_CLOCK_X4;
1248 	} else if (reg == QOPR_CLOCK_X8) {
1249 		clock = 14745600;
1250 		set = QOPR_CLOCK_X8;
1251 	} else {
1252 		clock = 1843200;
1253 		set = QOPR_CLOCK_X1;
1254 	}
1255 	qopr &= ~QOPR_CLOCK_RATE_MASK;
1256 	qopr |= set;
1257 
1258 out:
1259 	pci_quatech_wqopr(port, qopr);
1260 	return clock;
1261 }
1262 
1263 static int pci_quatech_rs422(struct uart_8250_port *port)
1264 {
1265 	u8 qmcr;
1266 	int rs422 = 0;
1267 
1268 	if (!pci_quatech_has_qmcr(port))
1269 		return 0;
1270 	qmcr = pci_quatech_rqmcr(port);
1271 	pci_quatech_wqmcr(port, 0xFF);
1272 	if (pci_quatech_rqmcr(port))
1273 		rs422 = 1;
1274 	pci_quatech_wqmcr(port, qmcr);
1275 	return rs422;
1276 }
1277 
1278 static int pci_quatech_init(struct pci_dev *dev)
1279 {
1280 	if (pci_quatech_amcc(dev->device)) {
1281 		unsigned long base = pci_resource_start(dev, 0);
1282 		if (base) {
1283 			u32 tmp;
1284 
1285 			outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1286 			tmp = inl(base + 0x3c);
1287 			outl(tmp | 0x01000000, base + 0x3c);
1288 			outl(tmp &= ~0x01000000, base + 0x3c);
1289 		}
1290 	}
1291 	return 0;
1292 }
1293 
1294 static int pci_quatech_setup(struct serial_private *priv,
1295 		  const struct pciserial_board *board,
1296 		  struct uart_8250_port *port, int idx)
1297 {
1298 	/* Needed by pci_quatech calls below */
1299 	port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1300 	/* Set up the clocking */
1301 	port->port.uartclk = pci_quatech_clock(port);
1302 	/* For now just warn about RS422 */
1303 	if (pci_quatech_rs422(port))
1304 		pr_warn("quatech: software control of RS422 features not currently supported.\n");
1305 	return pci_default_setup(priv, board, port, idx);
1306 }
1307 
1308 static void pci_quatech_exit(struct pci_dev *dev)
1309 {
1310 }
1311 
1312 static int pci_default_setup(struct serial_private *priv,
1313 		  const struct pciserial_board *board,
1314 		  struct uart_8250_port *port, int idx)
1315 {
1316 	unsigned int bar, offset = board->first_offset, maxnr;
1317 
1318 	bar = FL_GET_BASE(board->flags);
1319 	if (board->flags & FL_BASE_BARS)
1320 		bar += idx;
1321 	else
1322 		offset += idx * board->uart_offset;
1323 
1324 	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1325 		(board->reg_shift + 3);
1326 
1327 	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1328 		return 1;
1329 
1330 	return setup_port(priv, port, bar, offset, board->reg_shift);
1331 }
1332 
1333 static int pci_pericom_setup(struct serial_private *priv,
1334 		  const struct pciserial_board *board,
1335 		  struct uart_8250_port *port, int idx)
1336 {
1337 	unsigned int bar, offset = board->first_offset, maxnr;
1338 
1339 	bar = FL_GET_BASE(board->flags);
1340 	if (board->flags & FL_BASE_BARS)
1341 		bar += idx;
1342 	else
1343 		offset += idx * board->uart_offset;
1344 
1345 	if (idx==3)
1346 		offset = 0x38;
1347 
1348 	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 		(board->reg_shift + 3);
1350 
1351 	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1352 		return 1;
1353 
1354 	return setup_port(priv, port, bar, offset, board->reg_shift);
1355 }
1356 
1357 static int
1358 ce4100_serial_setup(struct serial_private *priv,
1359 		  const struct pciserial_board *board,
1360 		  struct uart_8250_port *port, int idx)
1361 {
1362 	int ret;
1363 
1364 	ret = setup_port(priv, port, idx, 0, board->reg_shift);
1365 	port->port.iotype = UPIO_MEM32;
1366 	port->port.type = PORT_XSCALE;
1367 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1368 	port->port.regshift = 2;
1369 
1370 	return ret;
1371 }
1372 
1373 static int
1374 pci_omegapci_setup(struct serial_private *priv,
1375 		      const struct pciserial_board *board,
1376 		      struct uart_8250_port *port, int idx)
1377 {
1378 	return setup_port(priv, port, 2, idx * 8, 0);
1379 }
1380 
1381 static int
1382 pci_brcm_trumanage_setup(struct serial_private *priv,
1383 			 const struct pciserial_board *board,
1384 			 struct uart_8250_port *port, int idx)
1385 {
1386 	int ret = pci_default_setup(priv, board, port, idx);
1387 
1388 	port->port.type = PORT_BRCM_TRUMANAGE;
1389 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1390 	return ret;
1391 }
1392 
1393 /* RTS will control by MCR if this bit is 0 */
1394 #define FINTEK_RTS_CONTROL_BY_HW	BIT(4)
1395 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1396 #define FINTEK_RTS_INVERT		BIT(5)
1397 
1398 /* We should do proper H/W transceiver setting before change to RS485 mode */
1399 static int pci_fintek_rs485_config(struct uart_port *port,
1400 			       struct serial_rs485 *rs485)
1401 {
1402 	struct pci_dev *pci_dev = to_pci_dev(port->dev);
1403 	u8 setting;
1404 	u8 *index = (u8 *) port->private_data;
1405 
1406 	pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1407 
1408 	if (!rs485)
1409 		rs485 = &port->rs485;
1410 	else if (rs485->flags & SER_RS485_ENABLED)
1411 		memset(rs485->padding, 0, sizeof(rs485->padding));
1412 	else
1413 		memset(rs485, 0, sizeof(*rs485));
1414 
1415 	/* F81504/508/512 not support RTS delay before or after send */
1416 	rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1417 
1418 	if (rs485->flags & SER_RS485_ENABLED) {
1419 		/* Enable RTS H/W control mode */
1420 		setting |= FINTEK_RTS_CONTROL_BY_HW;
1421 
1422 		if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1423 			/* RTS driving high on TX */
1424 			setting &= ~FINTEK_RTS_INVERT;
1425 		} else {
1426 			/* RTS driving low on TX */
1427 			setting |= FINTEK_RTS_INVERT;
1428 		}
1429 
1430 		rs485->delay_rts_after_send = 0;
1431 		rs485->delay_rts_before_send = 0;
1432 	} else {
1433 		/* Disable RTS H/W control mode */
1434 		setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1435 	}
1436 
1437 	pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1438 
1439 	if (rs485 != &port->rs485)
1440 		port->rs485 = *rs485;
1441 
1442 	return 0;
1443 }
1444 
1445 static int pci_fintek_setup(struct serial_private *priv,
1446 			    const struct pciserial_board *board,
1447 			    struct uart_8250_port *port, int idx)
1448 {
1449 	struct pci_dev *pdev = priv->dev;
1450 	u8 *data;
1451 	u8 config_base;
1452 	u16 iobase;
1453 
1454 	config_base = 0x40 + 0x08 * idx;
1455 
1456 	/* Get the io address from configuration space */
1457 	pci_read_config_word(pdev, config_base + 4, &iobase);
1458 
1459 	dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1460 
1461 	port->port.iotype = UPIO_PORT;
1462 	port->port.iobase = iobase;
1463 	port->port.rs485_config = pci_fintek_rs485_config;
1464 
1465 	data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1466 	if (!data)
1467 		return -ENOMEM;
1468 
1469 	/* preserve index in PCI configuration space */
1470 	*data = idx;
1471 	port->port.private_data = data;
1472 
1473 	return 0;
1474 }
1475 
1476 static int pci_fintek_init(struct pci_dev *dev)
1477 {
1478 	unsigned long iobase;
1479 	u32 max_port, i;
1480 	u32 bar_data[3];
1481 	u8 config_base;
1482 	struct serial_private *priv = pci_get_drvdata(dev);
1483 	struct uart_8250_port *port;
1484 
1485 	switch (dev->device) {
1486 	case 0x1104: /* 4 ports */
1487 	case 0x1108: /* 8 ports */
1488 		max_port = dev->device & 0xff;
1489 		break;
1490 	case 0x1112: /* 12 ports */
1491 		max_port = 12;
1492 		break;
1493 	default:
1494 		return -EINVAL;
1495 	}
1496 
1497 	/* Get the io address dispatch from the BIOS */
1498 	pci_read_config_dword(dev, 0x24, &bar_data[0]);
1499 	pci_read_config_dword(dev, 0x20, &bar_data[1]);
1500 	pci_read_config_dword(dev, 0x1c, &bar_data[2]);
1501 
1502 	for (i = 0; i < max_port; ++i) {
1503 		/* UART0 configuration offset start from 0x40 */
1504 		config_base = 0x40 + 0x08 * i;
1505 
1506 		/* Calculate Real IO Port */
1507 		iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1508 
1509 		/* Enable UART I/O port */
1510 		pci_write_config_byte(dev, config_base + 0x00, 0x01);
1511 
1512 		/* Select 128-byte FIFO and 8x FIFO threshold */
1513 		pci_write_config_byte(dev, config_base + 0x01, 0x33);
1514 
1515 		/* LSB UART */
1516 		pci_write_config_byte(dev, config_base + 0x04,
1517 				(u8)(iobase & 0xff));
1518 
1519 		/* MSB UART */
1520 		pci_write_config_byte(dev, config_base + 0x05,
1521 				(u8)((iobase & 0xff00) >> 8));
1522 
1523 		pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1524 
1525 		if (priv) {
1526 			/* re-apply RS232/485 mode when
1527 			 * pciserial_resume_ports()
1528 			 */
1529 			port = serial8250_get_port(priv->line[i]);
1530 			pci_fintek_rs485_config(&port->port, NULL);
1531 		} else {
1532 			/* First init without port data
1533 			 * force init to RS232 Mode
1534 			 */
1535 			pci_write_config_byte(dev, config_base + 0x07, 0x01);
1536 		}
1537 	}
1538 
1539 	return max_port;
1540 }
1541 
1542 static int skip_tx_en_setup(struct serial_private *priv,
1543 			const struct pciserial_board *board,
1544 			struct uart_8250_port *port, int idx)
1545 {
1546 	port->port.flags |= UPF_NO_TXEN_TEST;
1547 	dev_dbg(&priv->dev->dev,
1548 		"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1549 		priv->dev->vendor, priv->dev->device,
1550 		priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1551 
1552 	return pci_default_setup(priv, board, port, idx);
1553 }
1554 
1555 static void kt_handle_break(struct uart_port *p)
1556 {
1557 	struct uart_8250_port *up = up_to_u8250p(p);
1558 	/*
1559 	 * On receipt of a BI, serial device in Intel ME (Intel
1560 	 * management engine) needs to have its fifos cleared for sane
1561 	 * SOL (Serial Over Lan) output.
1562 	 */
1563 	serial8250_clear_and_reinit_fifos(up);
1564 }
1565 
1566 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1567 {
1568 	struct uart_8250_port *up = up_to_u8250p(p);
1569 	unsigned int val;
1570 
1571 	/*
1572 	 * When the Intel ME (management engine) gets reset its serial
1573 	 * port registers could return 0 momentarily.  Functions like
1574 	 * serial8250_console_write, read and save the IER, perform
1575 	 * some operation and then restore it.  In order to avoid
1576 	 * setting IER register inadvertently to 0, if the value read
1577 	 * is 0, double check with ier value in uart_8250_port and use
1578 	 * that instead.  up->ier should be the same value as what is
1579 	 * currently configured.
1580 	 */
1581 	val = inb(p->iobase + offset);
1582 	if (offset == UART_IER) {
1583 		if (val == 0)
1584 			val = up->ier;
1585 	}
1586 	return val;
1587 }
1588 
1589 static int kt_serial_setup(struct serial_private *priv,
1590 			   const struct pciserial_board *board,
1591 			   struct uart_8250_port *port, int idx)
1592 {
1593 	port->port.flags |= UPF_BUG_THRE;
1594 	port->port.serial_in = kt_serial_in;
1595 	port->port.handle_break = kt_handle_break;
1596 	return skip_tx_en_setup(priv, board, port, idx);
1597 }
1598 
1599 static int pci_eg20t_init(struct pci_dev *dev)
1600 {
1601 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1602 	return -ENODEV;
1603 #else
1604 	return 0;
1605 #endif
1606 }
1607 
1608 #define PCI_DEVICE_ID_EXAR_XR17V4358	0x4358
1609 #define PCI_DEVICE_ID_EXAR_XR17V8358	0x8358
1610 
1611 #define UART_EXAR_MPIOINT_7_0	0x8f	/* MPIOINT[7:0] */
1612 #define UART_EXAR_MPIOLVL_7_0	0x90	/* MPIOLVL[7:0] */
1613 #define UART_EXAR_MPIO3T_7_0	0x91	/* MPIO3T[7:0] */
1614 #define UART_EXAR_MPIOINV_7_0	0x92	/* MPIOINV[7:0] */
1615 #define UART_EXAR_MPIOSEL_7_0	0x93	/* MPIOSEL[7:0] */
1616 #define UART_EXAR_MPIOOD_7_0	0x94	/* MPIOOD[7:0] */
1617 #define UART_EXAR_MPIOINT_15_8	0x95	/* MPIOINT[15:8] */
1618 #define UART_EXAR_MPIOLVL_15_8	0x96	/* MPIOLVL[15:8] */
1619 #define UART_EXAR_MPIO3T_15_8	0x97	/* MPIO3T[15:8] */
1620 #define UART_EXAR_MPIOINV_15_8	0x98	/* MPIOINV[15:8] */
1621 #define UART_EXAR_MPIOSEL_15_8	0x99	/* MPIOSEL[15:8] */
1622 #define UART_EXAR_MPIOOD_15_8	0x9a	/* MPIOOD[15:8] */
1623 
1624 static int
1625 pci_xr17c154_setup(struct serial_private *priv,
1626 		  const struct pciserial_board *board,
1627 		  struct uart_8250_port *port, int idx)
1628 {
1629 	port->port.flags |= UPF_EXAR_EFR;
1630 	return pci_default_setup(priv, board, port, idx);
1631 }
1632 
1633 static inline int
1634 xr17v35x_has_slave(struct serial_private *priv)
1635 {
1636 	const int dev_id = priv->dev->device;
1637 
1638 	return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1639 		(dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1640 }
1641 
1642 static int
1643 pci_xr17v35x_setup(struct serial_private *priv,
1644 		  const struct pciserial_board *board,
1645 		  struct uart_8250_port *port, int idx)
1646 {
1647 	u8 __iomem *p;
1648 
1649 	p = pci_ioremap_bar(priv->dev, 0);
1650 	if (p == NULL)
1651 		return -ENOMEM;
1652 
1653 	port->port.flags |= UPF_EXAR_EFR;
1654 
1655 	/*
1656 	 * Setup the uart clock for the devices on expansion slot to
1657 	 * half the clock speed of the main chip (which is 125MHz)
1658 	 */
1659 	if (xr17v35x_has_slave(priv) && idx >= 8)
1660 		port->port.uartclk = (7812500 * 16 / 2);
1661 
1662 	/*
1663 	 * Setup Multipurpose Input/Output pins.
1664 	 */
1665 	if (idx == 0) {
1666 		writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1667 		writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1668 		writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1669 		writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1670 		writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1671 		writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1672 		writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
1673 		writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
1674 		writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
1675 		writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
1676 		writeb(0x00, p + UART_EXAR_MPIOSEL_15_8);
1677 		writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
1678 	}
1679 	writeb(0x00, p + UART_EXAR_8XMODE);
1680 	writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1681 	writeb(128, p + UART_EXAR_TXTRG);
1682 	writeb(128, p + UART_EXAR_RXTRG);
1683 	iounmap(p);
1684 
1685 	return pci_default_setup(priv, board, port, idx);
1686 }
1687 
1688 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1689 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1690 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1691 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1692 
1693 static int
1694 pci_fastcom335_setup(struct serial_private *priv,
1695 		  const struct pciserial_board *board,
1696 		  struct uart_8250_port *port, int idx)
1697 {
1698 	u8 __iomem *p;
1699 
1700 	p = pci_ioremap_bar(priv->dev, 0);
1701 	if (p == NULL)
1702 		return -ENOMEM;
1703 
1704 	port->port.flags |= UPF_EXAR_EFR;
1705 
1706 	/*
1707 	 * Setup Multipurpose Input/Output pins.
1708 	 */
1709 	if (idx == 0) {
1710 		switch (priv->dev->device) {
1711 		case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1712 		case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1713 			writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
1714 			writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
1715 			writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
1716 			break;
1717 		case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1718 		case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1719 			writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
1720 			writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
1721 			writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
1722 			break;
1723 		}
1724 		writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
1725 		writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
1726 		writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
1727 	}
1728 	writeb(0x00, p + UART_EXAR_8XMODE);
1729 	writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1730 	writeb(32, p + UART_EXAR_TXTRG);
1731 	writeb(32, p + UART_EXAR_RXTRG);
1732 	iounmap(p);
1733 
1734 	return pci_default_setup(priv, board, port, idx);
1735 }
1736 
1737 static int
1738 pci_wch_ch353_setup(struct serial_private *priv,
1739 		    const struct pciserial_board *board,
1740 		    struct uart_8250_port *port, int idx)
1741 {
1742 	port->port.flags |= UPF_FIXED_TYPE;
1743 	port->port.type = PORT_16550A;
1744 	return pci_default_setup(priv, board, port, idx);
1745 }
1746 
1747 static int
1748 pci_wch_ch355_setup(struct serial_private *priv,
1749 		const struct pciserial_board *board,
1750 		struct uart_8250_port *port, int idx)
1751 {
1752 	port->port.flags |= UPF_FIXED_TYPE;
1753 	port->port.type = PORT_16550A;
1754 	return pci_default_setup(priv, board, port, idx);
1755 }
1756 
1757 static int
1758 pci_wch_ch38x_setup(struct serial_private *priv,
1759 		    const struct pciserial_board *board,
1760 		    struct uart_8250_port *port, int idx)
1761 {
1762 	port->port.flags |= UPF_FIXED_TYPE;
1763 	port->port.type = PORT_16850;
1764 	return pci_default_setup(priv, board, port, idx);
1765 }
1766 
1767 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
1768 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
1769 #define PCI_DEVICE_ID_OCTPRO		0x0001
1770 #define PCI_SUBDEVICE_ID_OCTPRO232	0x0108
1771 #define PCI_SUBDEVICE_ID_OCTPRO422	0x0208
1772 #define PCI_SUBDEVICE_ID_POCTAL232	0x0308
1773 #define PCI_SUBDEVICE_ID_POCTAL422	0x0408
1774 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00	0x2500
1775 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30	0x2530
1776 #define PCI_VENDOR_ID_ADVANTECH		0x13fe
1777 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1778 #define PCI_DEVICE_ID_ADVANTECH_PCI3620	0x3620
1779 #define PCI_DEVICE_ID_ADVANTECH_PCI3618	0x3618
1780 #define PCI_DEVICE_ID_ADVANTECH_PCIf618	0xf618
1781 #define PCI_DEVICE_ID_TITAN_200I	0x8028
1782 #define PCI_DEVICE_ID_TITAN_400I	0x8048
1783 #define PCI_DEVICE_ID_TITAN_800I	0x8088
1784 #define PCI_DEVICE_ID_TITAN_800EH	0xA007
1785 #define PCI_DEVICE_ID_TITAN_800EHB	0xA008
1786 #define PCI_DEVICE_ID_TITAN_400EH	0xA009
1787 #define PCI_DEVICE_ID_TITAN_100E	0xA010
1788 #define PCI_DEVICE_ID_TITAN_200E	0xA012
1789 #define PCI_DEVICE_ID_TITAN_400E	0xA013
1790 #define PCI_DEVICE_ID_TITAN_800E	0xA014
1791 #define PCI_DEVICE_ID_TITAN_200EI	0xA016
1792 #define PCI_DEVICE_ID_TITAN_200EISI	0xA017
1793 #define PCI_DEVICE_ID_TITAN_200V3	0xA306
1794 #define PCI_DEVICE_ID_TITAN_400V3	0xA310
1795 #define PCI_DEVICE_ID_TITAN_410V3	0xA312
1796 #define PCI_DEVICE_ID_TITAN_800V3	0xA314
1797 #define PCI_DEVICE_ID_TITAN_800V3B	0xA315
1798 #define PCI_DEVICE_ID_OXSEMI_16PCI958	0x9538
1799 #define PCIE_DEVICE_ID_NEO_2_OX_IBM	0x00F6
1800 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA	0xc001
1801 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1802 #define PCI_VENDOR_ID_WCH		0x4348
1803 #define PCI_DEVICE_ID_WCH_CH352_2S	0x3253
1804 #define PCI_DEVICE_ID_WCH_CH353_4S	0x3453
1805 #define PCI_DEVICE_ID_WCH_CH353_2S1PF	0x5046
1806 #define PCI_DEVICE_ID_WCH_CH353_1S1P	0x5053
1807 #define PCI_DEVICE_ID_WCH_CH353_2S1P	0x7053
1808 #define PCI_DEVICE_ID_WCH_CH355_4S	0x7173
1809 #define PCI_VENDOR_ID_AGESTAR		0x5372
1810 #define PCI_DEVICE_ID_AGESTAR_9375	0x6872
1811 #define PCI_VENDOR_ID_ASIX		0x9710
1812 #define PCI_DEVICE_ID_COMMTECH_4224PCIE	0x0020
1813 #define PCI_DEVICE_ID_COMMTECH_4228PCIE	0x0021
1814 #define PCI_DEVICE_ID_COMMTECH_4222PCIE	0x0022
1815 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1816 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1817 
1818 #define PCI_VENDOR_ID_SUNIX		0x1fd4
1819 #define PCI_DEVICE_ID_SUNIX_1999	0x1999
1820 
1821 #define PCIE_VENDOR_ID_WCH		0x1c00
1822 #define PCIE_DEVICE_ID_WCH_CH382_2S1P	0x3250
1823 #define PCIE_DEVICE_ID_WCH_CH384_4S	0x3470
1824 #define PCIE_DEVICE_ID_WCH_CH382_2S	0x3253
1825 
1826 #define PCI_VENDOR_ID_PERICOM			0x12D8
1827 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951	0x7951
1828 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952	0x7952
1829 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954	0x7954
1830 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958	0x7958
1831 
1832 #define PCI_VENDOR_ID_ACCESIO			0x494f
1833 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB	0x1051
1834 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S	0x1053
1835 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB	0x105C
1836 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S	0x105E
1837 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB	0x1091
1838 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2	0x1093
1839 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB	0x1099
1840 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4	0x109B
1841 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB	0x10D1
1842 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM	0x10D3
1843 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB	0x10DA
1844 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM	0x10DC
1845 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1	0x1108
1846 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2	0x1110
1847 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2	0x1111
1848 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4	0x1118
1849 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4	0x1119
1850 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S	0x1152
1851 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S	0x115A
1852 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2	0x1190
1853 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2	0x1191
1854 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4	0x1198
1855 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4	0x1199
1856 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM	0x11D0
1857 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4	0x105A
1858 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4	0x105B
1859 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8	0x106A
1860 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8	0x106B
1861 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4	0x1098
1862 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8	0x10A9
1863 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM	0x10D9
1864 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM	0x10E9
1865 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM	0x11D8
1866 
1867 
1868 
1869 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1870 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584	0x1584
1871 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588	0x1588
1872 
1873 /*
1874  * Master list of serial port init/setup/exit quirks.
1875  * This does not describe the general nature of the port.
1876  * (ie, baud base, number and location of ports, etc)
1877  *
1878  * This list is ordered alphabetically by vendor then device.
1879  * Specific entries must come before more generic entries.
1880  */
1881 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1882 	/*
1883 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
1884 	*/
1885 	{
1886 		.vendor         = PCI_VENDOR_ID_AMCC,
1887 		.device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1888 		.subvendor      = PCI_ANY_ID,
1889 		.subdevice      = PCI_ANY_ID,
1890 		.setup          = addidata_apci7800_setup,
1891 	},
1892 	/*
1893 	 * AFAVLAB cards - these may be called via parport_serial
1894 	 *  It is not clear whether this applies to all products.
1895 	 */
1896 	{
1897 		.vendor		= PCI_VENDOR_ID_AFAVLAB,
1898 		.device		= PCI_ANY_ID,
1899 		.subvendor	= PCI_ANY_ID,
1900 		.subdevice	= PCI_ANY_ID,
1901 		.setup		= afavlab_setup,
1902 	},
1903 	/*
1904 	 * HP Diva
1905 	 */
1906 	{
1907 		.vendor		= PCI_VENDOR_ID_HP,
1908 		.device		= PCI_DEVICE_ID_HP_DIVA,
1909 		.subvendor	= PCI_ANY_ID,
1910 		.subdevice	= PCI_ANY_ID,
1911 		.init		= pci_hp_diva_init,
1912 		.setup		= pci_hp_diva_setup,
1913 	},
1914 	/*
1915 	 * Intel
1916 	 */
1917 	{
1918 		.vendor		= PCI_VENDOR_ID_INTEL,
1919 		.device		= PCI_DEVICE_ID_INTEL_80960_RP,
1920 		.subvendor	= 0xe4bf,
1921 		.subdevice	= PCI_ANY_ID,
1922 		.init		= pci_inteli960ni_init,
1923 		.setup		= pci_default_setup,
1924 	},
1925 	{
1926 		.vendor		= PCI_VENDOR_ID_INTEL,
1927 		.device		= PCI_DEVICE_ID_INTEL_8257X_SOL,
1928 		.subvendor	= PCI_ANY_ID,
1929 		.subdevice	= PCI_ANY_ID,
1930 		.setup		= skip_tx_en_setup,
1931 	},
1932 	{
1933 		.vendor		= PCI_VENDOR_ID_INTEL,
1934 		.device		= PCI_DEVICE_ID_INTEL_82573L_SOL,
1935 		.subvendor	= PCI_ANY_ID,
1936 		.subdevice	= PCI_ANY_ID,
1937 		.setup		= skip_tx_en_setup,
1938 	},
1939 	{
1940 		.vendor		= PCI_VENDOR_ID_INTEL,
1941 		.device		= PCI_DEVICE_ID_INTEL_82573E_SOL,
1942 		.subvendor	= PCI_ANY_ID,
1943 		.subdevice	= PCI_ANY_ID,
1944 		.setup		= skip_tx_en_setup,
1945 	},
1946 	{
1947 		.vendor		= PCI_VENDOR_ID_INTEL,
1948 		.device		= PCI_DEVICE_ID_INTEL_CE4100_UART,
1949 		.subvendor	= PCI_ANY_ID,
1950 		.subdevice	= PCI_ANY_ID,
1951 		.setup		= ce4100_serial_setup,
1952 	},
1953 	{
1954 		.vendor		= PCI_VENDOR_ID_INTEL,
1955 		.device		= PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1956 		.subvendor	= PCI_ANY_ID,
1957 		.subdevice	= PCI_ANY_ID,
1958 		.setup		= kt_serial_setup,
1959 	},
1960 	/*
1961 	 * ITE
1962 	 */
1963 	{
1964 		.vendor		= PCI_VENDOR_ID_ITE,
1965 		.device		= PCI_DEVICE_ID_ITE_8872,
1966 		.subvendor	= PCI_ANY_ID,
1967 		.subdevice	= PCI_ANY_ID,
1968 		.init		= pci_ite887x_init,
1969 		.setup		= pci_default_setup,
1970 		.exit		= pci_ite887x_exit,
1971 	},
1972 	/*
1973 	 * National Instruments
1974 	 */
1975 	{
1976 		.vendor		= PCI_VENDOR_ID_NI,
1977 		.device		= PCI_DEVICE_ID_NI_PCI23216,
1978 		.subvendor	= PCI_ANY_ID,
1979 		.subdevice	= PCI_ANY_ID,
1980 		.init		= pci_ni8420_init,
1981 		.setup		= pci_default_setup,
1982 		.exit		= pci_ni8420_exit,
1983 	},
1984 	{
1985 		.vendor		= PCI_VENDOR_ID_NI,
1986 		.device		= PCI_DEVICE_ID_NI_PCI2328,
1987 		.subvendor	= PCI_ANY_ID,
1988 		.subdevice	= PCI_ANY_ID,
1989 		.init		= pci_ni8420_init,
1990 		.setup		= pci_default_setup,
1991 		.exit		= pci_ni8420_exit,
1992 	},
1993 	{
1994 		.vendor		= PCI_VENDOR_ID_NI,
1995 		.device		= PCI_DEVICE_ID_NI_PCI2324,
1996 		.subvendor	= PCI_ANY_ID,
1997 		.subdevice	= PCI_ANY_ID,
1998 		.init		= pci_ni8420_init,
1999 		.setup		= pci_default_setup,
2000 		.exit		= pci_ni8420_exit,
2001 	},
2002 	{
2003 		.vendor		= PCI_VENDOR_ID_NI,
2004 		.device		= PCI_DEVICE_ID_NI_PCI2322,
2005 		.subvendor	= PCI_ANY_ID,
2006 		.subdevice	= PCI_ANY_ID,
2007 		.init		= pci_ni8420_init,
2008 		.setup		= pci_default_setup,
2009 		.exit		= pci_ni8420_exit,
2010 	},
2011 	{
2012 		.vendor		= PCI_VENDOR_ID_NI,
2013 		.device		= PCI_DEVICE_ID_NI_PCI2324I,
2014 		.subvendor	= PCI_ANY_ID,
2015 		.subdevice	= PCI_ANY_ID,
2016 		.init		= pci_ni8420_init,
2017 		.setup		= pci_default_setup,
2018 		.exit		= pci_ni8420_exit,
2019 	},
2020 	{
2021 		.vendor		= PCI_VENDOR_ID_NI,
2022 		.device		= PCI_DEVICE_ID_NI_PCI2322I,
2023 		.subvendor	= PCI_ANY_ID,
2024 		.subdevice	= PCI_ANY_ID,
2025 		.init		= pci_ni8420_init,
2026 		.setup		= pci_default_setup,
2027 		.exit		= pci_ni8420_exit,
2028 	},
2029 	{
2030 		.vendor		= PCI_VENDOR_ID_NI,
2031 		.device		= PCI_DEVICE_ID_NI_PXI8420_23216,
2032 		.subvendor	= PCI_ANY_ID,
2033 		.subdevice	= PCI_ANY_ID,
2034 		.init		= pci_ni8420_init,
2035 		.setup		= pci_default_setup,
2036 		.exit		= pci_ni8420_exit,
2037 	},
2038 	{
2039 		.vendor		= PCI_VENDOR_ID_NI,
2040 		.device		= PCI_DEVICE_ID_NI_PXI8420_2328,
2041 		.subvendor	= PCI_ANY_ID,
2042 		.subdevice	= PCI_ANY_ID,
2043 		.init		= pci_ni8420_init,
2044 		.setup		= pci_default_setup,
2045 		.exit		= pci_ni8420_exit,
2046 	},
2047 	{
2048 		.vendor		= PCI_VENDOR_ID_NI,
2049 		.device		= PCI_DEVICE_ID_NI_PXI8420_2324,
2050 		.subvendor	= PCI_ANY_ID,
2051 		.subdevice	= PCI_ANY_ID,
2052 		.init		= pci_ni8420_init,
2053 		.setup		= pci_default_setup,
2054 		.exit		= pci_ni8420_exit,
2055 	},
2056 	{
2057 		.vendor		= PCI_VENDOR_ID_NI,
2058 		.device		= PCI_DEVICE_ID_NI_PXI8420_2322,
2059 		.subvendor	= PCI_ANY_ID,
2060 		.subdevice	= PCI_ANY_ID,
2061 		.init		= pci_ni8420_init,
2062 		.setup		= pci_default_setup,
2063 		.exit		= pci_ni8420_exit,
2064 	},
2065 	{
2066 		.vendor		= PCI_VENDOR_ID_NI,
2067 		.device		= PCI_DEVICE_ID_NI_PXI8422_2324,
2068 		.subvendor	= PCI_ANY_ID,
2069 		.subdevice	= PCI_ANY_ID,
2070 		.init		= pci_ni8420_init,
2071 		.setup		= pci_default_setup,
2072 		.exit		= pci_ni8420_exit,
2073 	},
2074 	{
2075 		.vendor		= PCI_VENDOR_ID_NI,
2076 		.device		= PCI_DEVICE_ID_NI_PXI8422_2322,
2077 		.subvendor	= PCI_ANY_ID,
2078 		.subdevice	= PCI_ANY_ID,
2079 		.init		= pci_ni8420_init,
2080 		.setup		= pci_default_setup,
2081 		.exit		= pci_ni8420_exit,
2082 	},
2083 	{
2084 		.vendor		= PCI_VENDOR_ID_NI,
2085 		.device		= PCI_ANY_ID,
2086 		.subvendor	= PCI_ANY_ID,
2087 		.subdevice	= PCI_ANY_ID,
2088 		.init		= pci_ni8430_init,
2089 		.setup		= pci_ni8430_setup,
2090 		.exit		= pci_ni8430_exit,
2091 	},
2092 	/* Quatech */
2093 	{
2094 		.vendor		= PCI_VENDOR_ID_QUATECH,
2095 		.device		= PCI_ANY_ID,
2096 		.subvendor	= PCI_ANY_ID,
2097 		.subdevice	= PCI_ANY_ID,
2098 		.init		= pci_quatech_init,
2099 		.setup		= pci_quatech_setup,
2100 		.exit		= pci_quatech_exit,
2101 	},
2102 	/*
2103 	 * Panacom
2104 	 */
2105 	{
2106 		.vendor		= PCI_VENDOR_ID_PANACOM,
2107 		.device		= PCI_DEVICE_ID_PANACOM_QUADMODEM,
2108 		.subvendor	= PCI_ANY_ID,
2109 		.subdevice	= PCI_ANY_ID,
2110 		.init		= pci_plx9050_init,
2111 		.setup		= pci_default_setup,
2112 		.exit		= pci_plx9050_exit,
2113 	},
2114 	{
2115 		.vendor		= PCI_VENDOR_ID_PANACOM,
2116 		.device		= PCI_DEVICE_ID_PANACOM_DUALMODEM,
2117 		.subvendor	= PCI_ANY_ID,
2118 		.subdevice	= PCI_ANY_ID,
2119 		.init		= pci_plx9050_init,
2120 		.setup		= pci_default_setup,
2121 		.exit		= pci_plx9050_exit,
2122 	},
2123 	/*
2124 	 * Pericom (Only 7954 - It have a offset jump for port 4)
2125 	 */
2126 	{
2127 		.vendor		= PCI_VENDOR_ID_PERICOM,
2128 		.device		= PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2129 		.subvendor	= PCI_ANY_ID,
2130 		.subdevice	= PCI_ANY_ID,
2131 		.setup		= pci_pericom_setup,
2132 	},
2133 	/*
2134 	 * PLX
2135 	 */
2136 	{
2137 		.vendor		= PCI_VENDOR_ID_PLX,
2138 		.device		= PCI_DEVICE_ID_PLX_9050,
2139 		.subvendor	= PCI_SUBVENDOR_ID_EXSYS,
2140 		.subdevice	= PCI_SUBDEVICE_ID_EXSYS_4055,
2141 		.init		= pci_plx9050_init,
2142 		.setup		= pci_default_setup,
2143 		.exit		= pci_plx9050_exit,
2144 	},
2145 	{
2146 		.vendor		= PCI_VENDOR_ID_PLX,
2147 		.device		= PCI_DEVICE_ID_PLX_9050,
2148 		.subvendor	= PCI_SUBVENDOR_ID_KEYSPAN,
2149 		.subdevice	= PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2150 		.init		= pci_plx9050_init,
2151 		.setup		= pci_default_setup,
2152 		.exit		= pci_plx9050_exit,
2153 	},
2154 	{
2155 		.vendor		= PCI_VENDOR_ID_PLX,
2156 		.device		= PCI_DEVICE_ID_PLX_ROMULUS,
2157 		.subvendor	= PCI_VENDOR_ID_PLX,
2158 		.subdevice	= PCI_DEVICE_ID_PLX_ROMULUS,
2159 		.init		= pci_plx9050_init,
2160 		.setup		= pci_default_setup,
2161 		.exit		= pci_plx9050_exit,
2162 	},
2163 	/*
2164 	 * SBS Technologies, Inc., PMC-OCTALPRO 232
2165 	 */
2166 	{
2167 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2168 		.device		= PCI_DEVICE_ID_OCTPRO,
2169 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2170 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO232,
2171 		.init		= sbs_init,
2172 		.setup		= sbs_setup,
2173 		.exit		= sbs_exit,
2174 	},
2175 	/*
2176 	 * SBS Technologies, Inc., PMC-OCTALPRO 422
2177 	 */
2178 	{
2179 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2180 		.device		= PCI_DEVICE_ID_OCTPRO,
2181 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2182 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO422,
2183 		.init		= sbs_init,
2184 		.setup		= sbs_setup,
2185 		.exit		= sbs_exit,
2186 	},
2187 	/*
2188 	 * SBS Technologies, Inc., P-Octal 232
2189 	 */
2190 	{
2191 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2192 		.device		= PCI_DEVICE_ID_OCTPRO,
2193 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2194 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL232,
2195 		.init		= sbs_init,
2196 		.setup		= sbs_setup,
2197 		.exit		= sbs_exit,
2198 	},
2199 	/*
2200 	 * SBS Technologies, Inc., P-Octal 422
2201 	 */
2202 	{
2203 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2204 		.device		= PCI_DEVICE_ID_OCTPRO,
2205 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2206 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL422,
2207 		.init		= sbs_init,
2208 		.setup		= sbs_setup,
2209 		.exit		= sbs_exit,
2210 	},
2211 	/*
2212 	 * SIIG cards - these may be called via parport_serial
2213 	 */
2214 	{
2215 		.vendor		= PCI_VENDOR_ID_SIIG,
2216 		.device		= PCI_ANY_ID,
2217 		.subvendor	= PCI_ANY_ID,
2218 		.subdevice	= PCI_ANY_ID,
2219 		.init		= pci_siig_init,
2220 		.setup		= pci_siig_setup,
2221 	},
2222 	/*
2223 	 * Titan cards
2224 	 */
2225 	{
2226 		.vendor		= PCI_VENDOR_ID_TITAN,
2227 		.device		= PCI_DEVICE_ID_TITAN_400L,
2228 		.subvendor	= PCI_ANY_ID,
2229 		.subdevice	= PCI_ANY_ID,
2230 		.setup		= titan_400l_800l_setup,
2231 	},
2232 	{
2233 		.vendor		= PCI_VENDOR_ID_TITAN,
2234 		.device		= PCI_DEVICE_ID_TITAN_800L,
2235 		.subvendor	= PCI_ANY_ID,
2236 		.subdevice	= PCI_ANY_ID,
2237 		.setup		= titan_400l_800l_setup,
2238 	},
2239 	/*
2240 	 * Timedia cards
2241 	 */
2242 	{
2243 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2244 		.device		= PCI_DEVICE_ID_TIMEDIA_1889,
2245 		.subvendor	= PCI_VENDOR_ID_TIMEDIA,
2246 		.subdevice	= PCI_ANY_ID,
2247 		.probe		= pci_timedia_probe,
2248 		.init		= pci_timedia_init,
2249 		.setup		= pci_timedia_setup,
2250 	},
2251 	{
2252 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2253 		.device		= PCI_ANY_ID,
2254 		.subvendor	= PCI_ANY_ID,
2255 		.subdevice	= PCI_ANY_ID,
2256 		.setup		= pci_timedia_setup,
2257 	},
2258 	/*
2259 	 * SUNIX (Timedia) cards
2260 	 * Do not "probe" for these cards as there is at least one combination
2261 	 * card that should be handled by parport_pc that doesn't match the
2262 	 * rule in pci_timedia_probe.
2263 	 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2264 	 * There are some boards with part number SER5037AL that report
2265 	 * subdevice ID 0x0002.
2266 	 */
2267 	{
2268 		.vendor		= PCI_VENDOR_ID_SUNIX,
2269 		.device		= PCI_DEVICE_ID_SUNIX_1999,
2270 		.subvendor	= PCI_VENDOR_ID_SUNIX,
2271 		.subdevice	= PCI_ANY_ID,
2272 		.init		= pci_timedia_init,
2273 		.setup		= pci_timedia_setup,
2274 	},
2275 	/*
2276 	 * Exar cards
2277 	 */
2278 	{
2279 		.vendor = PCI_VENDOR_ID_EXAR,
2280 		.device = PCI_DEVICE_ID_EXAR_XR17C152,
2281 		.subvendor	= PCI_ANY_ID,
2282 		.subdevice	= PCI_ANY_ID,
2283 		.setup		= pci_xr17c154_setup,
2284 	},
2285 	{
2286 		.vendor = PCI_VENDOR_ID_EXAR,
2287 		.device = PCI_DEVICE_ID_EXAR_XR17C154,
2288 		.subvendor	= PCI_ANY_ID,
2289 		.subdevice	= PCI_ANY_ID,
2290 		.setup		= pci_xr17c154_setup,
2291 	},
2292 	{
2293 		.vendor = PCI_VENDOR_ID_EXAR,
2294 		.device = PCI_DEVICE_ID_EXAR_XR17C158,
2295 		.subvendor	= PCI_ANY_ID,
2296 		.subdevice	= PCI_ANY_ID,
2297 		.setup		= pci_xr17c154_setup,
2298 	},
2299 	{
2300 		.vendor = PCI_VENDOR_ID_EXAR,
2301 		.device = PCI_DEVICE_ID_EXAR_XR17V352,
2302 		.subvendor	= PCI_ANY_ID,
2303 		.subdevice	= PCI_ANY_ID,
2304 		.setup		= pci_xr17v35x_setup,
2305 	},
2306 	{
2307 		.vendor = PCI_VENDOR_ID_EXAR,
2308 		.device = PCI_DEVICE_ID_EXAR_XR17V354,
2309 		.subvendor	= PCI_ANY_ID,
2310 		.subdevice	= PCI_ANY_ID,
2311 		.setup		= pci_xr17v35x_setup,
2312 	},
2313 	{
2314 		.vendor = PCI_VENDOR_ID_EXAR,
2315 		.device = PCI_DEVICE_ID_EXAR_XR17V358,
2316 		.subvendor	= PCI_ANY_ID,
2317 		.subdevice	= PCI_ANY_ID,
2318 		.setup		= pci_xr17v35x_setup,
2319 	},
2320 	{
2321 		.vendor = PCI_VENDOR_ID_EXAR,
2322 		.device = PCI_DEVICE_ID_EXAR_XR17V4358,
2323 		.subvendor	= PCI_ANY_ID,
2324 		.subdevice	= PCI_ANY_ID,
2325 		.setup		= pci_xr17v35x_setup,
2326 	},
2327 	{
2328 		.vendor = PCI_VENDOR_ID_EXAR,
2329 		.device = PCI_DEVICE_ID_EXAR_XR17V8358,
2330 		.subvendor	= PCI_ANY_ID,
2331 		.subdevice	= PCI_ANY_ID,
2332 		.setup		= pci_xr17v35x_setup,
2333 	},
2334 	/*
2335 	 * Xircom cards
2336 	 */
2337 	{
2338 		.vendor		= PCI_VENDOR_ID_XIRCOM,
2339 		.device		= PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2340 		.subvendor	= PCI_ANY_ID,
2341 		.subdevice	= PCI_ANY_ID,
2342 		.init		= pci_xircom_init,
2343 		.setup		= pci_default_setup,
2344 	},
2345 	/*
2346 	 * Netmos cards - these may be called via parport_serial
2347 	 */
2348 	{
2349 		.vendor		= PCI_VENDOR_ID_NETMOS,
2350 		.device		= PCI_ANY_ID,
2351 		.subvendor	= PCI_ANY_ID,
2352 		.subdevice	= PCI_ANY_ID,
2353 		.init		= pci_netmos_init,
2354 		.setup		= pci_netmos_9900_setup,
2355 	},
2356 	/*
2357 	 * EndRun Technologies
2358 	*/
2359 	{
2360 		.vendor		= PCI_VENDOR_ID_ENDRUN,
2361 		.device		= PCI_ANY_ID,
2362 		.subvendor	= PCI_ANY_ID,
2363 		.subdevice	= PCI_ANY_ID,
2364 		.init		= pci_endrun_init,
2365 		.setup		= pci_default_setup,
2366 	},
2367 	/*
2368 	 * For Oxford Semiconductor Tornado based devices
2369 	 */
2370 	{
2371 		.vendor		= PCI_VENDOR_ID_OXSEMI,
2372 		.device		= PCI_ANY_ID,
2373 		.subvendor	= PCI_ANY_ID,
2374 		.subdevice	= PCI_ANY_ID,
2375 		.init		= pci_oxsemi_tornado_init,
2376 		.setup		= pci_default_setup,
2377 	},
2378 	{
2379 		.vendor		= PCI_VENDOR_ID_MAINPINE,
2380 		.device		= PCI_ANY_ID,
2381 		.subvendor	= PCI_ANY_ID,
2382 		.subdevice	= PCI_ANY_ID,
2383 		.init		= pci_oxsemi_tornado_init,
2384 		.setup		= pci_default_setup,
2385 	},
2386 	{
2387 		.vendor		= PCI_VENDOR_ID_DIGI,
2388 		.device		= PCIE_DEVICE_ID_NEO_2_OX_IBM,
2389 		.subvendor		= PCI_SUBVENDOR_ID_IBM,
2390 		.subdevice		= PCI_ANY_ID,
2391 		.init			= pci_oxsemi_tornado_init,
2392 		.setup		= pci_default_setup,
2393 	},
2394 	{
2395 		.vendor         = PCI_VENDOR_ID_INTEL,
2396 		.device         = 0x8811,
2397 		.subvendor	= PCI_ANY_ID,
2398 		.subdevice	= PCI_ANY_ID,
2399 		.init		= pci_eg20t_init,
2400 		.setup		= pci_default_setup,
2401 	},
2402 	{
2403 		.vendor         = PCI_VENDOR_ID_INTEL,
2404 		.device         = 0x8812,
2405 		.subvendor	= PCI_ANY_ID,
2406 		.subdevice	= PCI_ANY_ID,
2407 		.init		= pci_eg20t_init,
2408 		.setup		= pci_default_setup,
2409 	},
2410 	{
2411 		.vendor         = PCI_VENDOR_ID_INTEL,
2412 		.device         = 0x8813,
2413 		.subvendor	= PCI_ANY_ID,
2414 		.subdevice	= PCI_ANY_ID,
2415 		.init		= pci_eg20t_init,
2416 		.setup		= pci_default_setup,
2417 	},
2418 	{
2419 		.vendor         = PCI_VENDOR_ID_INTEL,
2420 		.device         = 0x8814,
2421 		.subvendor	= PCI_ANY_ID,
2422 		.subdevice	= PCI_ANY_ID,
2423 		.init		= pci_eg20t_init,
2424 		.setup		= pci_default_setup,
2425 	},
2426 	{
2427 		.vendor         = 0x10DB,
2428 		.device         = 0x8027,
2429 		.subvendor	= PCI_ANY_ID,
2430 		.subdevice	= PCI_ANY_ID,
2431 		.init		= pci_eg20t_init,
2432 		.setup		= pci_default_setup,
2433 	},
2434 	{
2435 		.vendor         = 0x10DB,
2436 		.device         = 0x8028,
2437 		.subvendor	= PCI_ANY_ID,
2438 		.subdevice	= PCI_ANY_ID,
2439 		.init		= pci_eg20t_init,
2440 		.setup		= pci_default_setup,
2441 	},
2442 	{
2443 		.vendor         = 0x10DB,
2444 		.device         = 0x8029,
2445 		.subvendor	= PCI_ANY_ID,
2446 		.subdevice	= PCI_ANY_ID,
2447 		.init		= pci_eg20t_init,
2448 		.setup		= pci_default_setup,
2449 	},
2450 	{
2451 		.vendor         = 0x10DB,
2452 		.device         = 0x800C,
2453 		.subvendor	= PCI_ANY_ID,
2454 		.subdevice	= PCI_ANY_ID,
2455 		.init		= pci_eg20t_init,
2456 		.setup		= pci_default_setup,
2457 	},
2458 	{
2459 		.vendor         = 0x10DB,
2460 		.device         = 0x800D,
2461 		.subvendor	= PCI_ANY_ID,
2462 		.subdevice	= PCI_ANY_ID,
2463 		.init		= pci_eg20t_init,
2464 		.setup		= pci_default_setup,
2465 	},
2466 	/*
2467 	 * Cronyx Omega PCI (PLX-chip based)
2468 	 */
2469 	{
2470 		.vendor		= PCI_VENDOR_ID_PLX,
2471 		.device		= PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2472 		.subvendor	= PCI_ANY_ID,
2473 		.subdevice	= PCI_ANY_ID,
2474 		.setup		= pci_omegapci_setup,
2475 	},
2476 	/* WCH CH353 1S1P card (16550 clone) */
2477 	{
2478 		.vendor         = PCI_VENDOR_ID_WCH,
2479 		.device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2480 		.subvendor      = PCI_ANY_ID,
2481 		.subdevice      = PCI_ANY_ID,
2482 		.setup          = pci_wch_ch353_setup,
2483 	},
2484 	/* WCH CH353 2S1P card (16550 clone) */
2485 	{
2486 		.vendor         = PCI_VENDOR_ID_WCH,
2487 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2488 		.subvendor      = PCI_ANY_ID,
2489 		.subdevice      = PCI_ANY_ID,
2490 		.setup          = pci_wch_ch353_setup,
2491 	},
2492 	/* WCH CH353 4S card (16550 clone) */
2493 	{
2494 		.vendor         = PCI_VENDOR_ID_WCH,
2495 		.device         = PCI_DEVICE_ID_WCH_CH353_4S,
2496 		.subvendor      = PCI_ANY_ID,
2497 		.subdevice      = PCI_ANY_ID,
2498 		.setup          = pci_wch_ch353_setup,
2499 	},
2500 	/* WCH CH353 2S1PF card (16550 clone) */
2501 	{
2502 		.vendor         = PCI_VENDOR_ID_WCH,
2503 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2504 		.subvendor      = PCI_ANY_ID,
2505 		.subdevice      = PCI_ANY_ID,
2506 		.setup          = pci_wch_ch353_setup,
2507 	},
2508 	/* WCH CH352 2S card (16550 clone) */
2509 	{
2510 		.vendor		= PCI_VENDOR_ID_WCH,
2511 		.device		= PCI_DEVICE_ID_WCH_CH352_2S,
2512 		.subvendor	= PCI_ANY_ID,
2513 		.subdevice	= PCI_ANY_ID,
2514 		.setup		= pci_wch_ch353_setup,
2515 	},
2516 	/* WCH CH355 4S card (16550 clone) */
2517 	{
2518 		.vendor		= PCI_VENDOR_ID_WCH,
2519 		.device		= PCI_DEVICE_ID_WCH_CH355_4S,
2520 		.subvendor	= PCI_ANY_ID,
2521 		.subdevice	= PCI_ANY_ID,
2522 		.setup		= pci_wch_ch355_setup,
2523 	},
2524 	/* WCH CH382 2S card (16850 clone) */
2525 	{
2526 		.vendor         = PCIE_VENDOR_ID_WCH,
2527 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2528 		.subvendor      = PCI_ANY_ID,
2529 		.subdevice      = PCI_ANY_ID,
2530 		.setup          = pci_wch_ch38x_setup,
2531 	},
2532 	/* WCH CH382 2S1P card (16850 clone) */
2533 	{
2534 		.vendor         = PCIE_VENDOR_ID_WCH,
2535 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2536 		.subvendor      = PCI_ANY_ID,
2537 		.subdevice      = PCI_ANY_ID,
2538 		.setup          = pci_wch_ch38x_setup,
2539 	},
2540 	/* WCH CH384 4S card (16850 clone) */
2541 	{
2542 		.vendor         = PCIE_VENDOR_ID_WCH,
2543 		.device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2544 		.subvendor      = PCI_ANY_ID,
2545 		.subdevice      = PCI_ANY_ID,
2546 		.setup          = pci_wch_ch38x_setup,
2547 	},
2548 	/*
2549 	 * ASIX devices with FIFO bug
2550 	 */
2551 	{
2552 		.vendor		= PCI_VENDOR_ID_ASIX,
2553 		.device		= PCI_ANY_ID,
2554 		.subvendor	= PCI_ANY_ID,
2555 		.subdevice	= PCI_ANY_ID,
2556 		.setup		= pci_asix_setup,
2557 	},
2558 	/*
2559 	 * Commtech, Inc. Fastcom adapters
2560 	 *
2561 	 */
2562 	{
2563 		.vendor = PCI_VENDOR_ID_COMMTECH,
2564 		.device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2565 		.subvendor	= PCI_ANY_ID,
2566 		.subdevice	= PCI_ANY_ID,
2567 		.setup		= pci_fastcom335_setup,
2568 	},
2569 	{
2570 		.vendor = PCI_VENDOR_ID_COMMTECH,
2571 		.device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2572 		.subvendor	= PCI_ANY_ID,
2573 		.subdevice	= PCI_ANY_ID,
2574 		.setup		= pci_fastcom335_setup,
2575 	},
2576 	{
2577 		.vendor = PCI_VENDOR_ID_COMMTECH,
2578 		.device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2579 		.subvendor	= PCI_ANY_ID,
2580 		.subdevice	= PCI_ANY_ID,
2581 		.setup		= pci_fastcom335_setup,
2582 	},
2583 	{
2584 		.vendor = PCI_VENDOR_ID_COMMTECH,
2585 		.device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2586 		.subvendor	= PCI_ANY_ID,
2587 		.subdevice	= PCI_ANY_ID,
2588 		.setup		= pci_fastcom335_setup,
2589 	},
2590 	{
2591 		.vendor = PCI_VENDOR_ID_COMMTECH,
2592 		.device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2593 		.subvendor	= PCI_ANY_ID,
2594 		.subdevice	= PCI_ANY_ID,
2595 		.setup		= pci_xr17v35x_setup,
2596 	},
2597 	{
2598 		.vendor = PCI_VENDOR_ID_COMMTECH,
2599 		.device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2600 		.subvendor	= PCI_ANY_ID,
2601 		.subdevice	= PCI_ANY_ID,
2602 		.setup		= pci_xr17v35x_setup,
2603 	},
2604 	{
2605 		.vendor = PCI_VENDOR_ID_COMMTECH,
2606 		.device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2607 		.subvendor	= PCI_ANY_ID,
2608 		.subdevice	= PCI_ANY_ID,
2609 		.setup		= pci_xr17v35x_setup,
2610 	},
2611 	/*
2612 	 * Broadcom TruManage (NetXtreme)
2613 	 */
2614 	{
2615 		.vendor		= PCI_VENDOR_ID_BROADCOM,
2616 		.device		= PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2617 		.subvendor	= PCI_ANY_ID,
2618 		.subdevice	= PCI_ANY_ID,
2619 		.setup		= pci_brcm_trumanage_setup,
2620 	},
2621 	{
2622 		.vendor		= 0x1c29,
2623 		.device		= 0x1104,
2624 		.subvendor	= PCI_ANY_ID,
2625 		.subdevice	= PCI_ANY_ID,
2626 		.setup		= pci_fintek_setup,
2627 		.init		= pci_fintek_init,
2628 	},
2629 	{
2630 		.vendor		= 0x1c29,
2631 		.device		= 0x1108,
2632 		.subvendor	= PCI_ANY_ID,
2633 		.subdevice	= PCI_ANY_ID,
2634 		.setup		= pci_fintek_setup,
2635 		.init		= pci_fintek_init,
2636 	},
2637 	{
2638 		.vendor		= 0x1c29,
2639 		.device		= 0x1112,
2640 		.subvendor	= PCI_ANY_ID,
2641 		.subdevice	= PCI_ANY_ID,
2642 		.setup		= pci_fintek_setup,
2643 		.init		= pci_fintek_init,
2644 	},
2645 
2646 	/*
2647 	 * Default "match everything" terminator entry
2648 	 */
2649 	{
2650 		.vendor		= PCI_ANY_ID,
2651 		.device		= PCI_ANY_ID,
2652 		.subvendor	= PCI_ANY_ID,
2653 		.subdevice	= PCI_ANY_ID,
2654 		.setup		= pci_default_setup,
2655 	}
2656 };
2657 
2658 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2659 {
2660 	return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2661 }
2662 
2663 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2664 {
2665 	struct pci_serial_quirk *quirk;
2666 
2667 	for (quirk = pci_serial_quirks; ; quirk++)
2668 		if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2669 		    quirk_id_matches(quirk->device, dev->device) &&
2670 		    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2671 		    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2672 			break;
2673 	return quirk;
2674 }
2675 
2676 static inline int get_pci_irq(struct pci_dev *dev,
2677 				const struct pciserial_board *board)
2678 {
2679 	if (board->flags & FL_NOIRQ)
2680 		return 0;
2681 	else
2682 		return dev->irq;
2683 }
2684 
2685 /*
2686  * This is the configuration table for all of the PCI serial boards
2687  * which we support.  It is directly indexed by the pci_board_num_t enum
2688  * value, which is encoded in the pci_device_id PCI probe table's
2689  * driver_data member.
2690  *
2691  * The makeup of these names are:
2692  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2693  *
2694  *  bn		= PCI BAR number
2695  *  bt		= Index using PCI BARs
2696  *  n		= number of serial ports
2697  *  baud	= baud rate
2698  *  offsetinhex	= offset for each sequential port (in hex)
2699  *
2700  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2701  *
2702  * Please note: in theory if n = 1, _bt infix should make no difference.
2703  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2704  */
2705 enum pci_board_num_t {
2706 	pbn_default = 0,
2707 
2708 	pbn_b0_1_115200,
2709 	pbn_b0_2_115200,
2710 	pbn_b0_4_115200,
2711 	pbn_b0_5_115200,
2712 	pbn_b0_8_115200,
2713 
2714 	pbn_b0_1_921600,
2715 	pbn_b0_2_921600,
2716 	pbn_b0_4_921600,
2717 
2718 	pbn_b0_2_1130000,
2719 
2720 	pbn_b0_4_1152000,
2721 
2722 	pbn_b0_2_1152000_200,
2723 	pbn_b0_4_1152000_200,
2724 	pbn_b0_8_1152000_200,
2725 
2726 	pbn_b0_2_1843200,
2727 	pbn_b0_4_1843200,
2728 
2729 	pbn_b0_2_1843200_200,
2730 	pbn_b0_4_1843200_200,
2731 	pbn_b0_8_1843200_200,
2732 
2733 	pbn_b0_1_4000000,
2734 
2735 	pbn_b0_bt_1_115200,
2736 	pbn_b0_bt_2_115200,
2737 	pbn_b0_bt_4_115200,
2738 	pbn_b0_bt_8_115200,
2739 
2740 	pbn_b0_bt_1_460800,
2741 	pbn_b0_bt_2_460800,
2742 	pbn_b0_bt_4_460800,
2743 
2744 	pbn_b0_bt_1_921600,
2745 	pbn_b0_bt_2_921600,
2746 	pbn_b0_bt_4_921600,
2747 	pbn_b0_bt_8_921600,
2748 
2749 	pbn_b1_1_115200,
2750 	pbn_b1_2_115200,
2751 	pbn_b1_4_115200,
2752 	pbn_b1_8_115200,
2753 	pbn_b1_16_115200,
2754 
2755 	pbn_b1_1_921600,
2756 	pbn_b1_2_921600,
2757 	pbn_b1_4_921600,
2758 	pbn_b1_8_921600,
2759 
2760 	pbn_b1_2_1250000,
2761 
2762 	pbn_b1_bt_1_115200,
2763 	pbn_b1_bt_2_115200,
2764 	pbn_b1_bt_4_115200,
2765 
2766 	pbn_b1_bt_2_921600,
2767 
2768 	pbn_b1_1_1382400,
2769 	pbn_b1_2_1382400,
2770 	pbn_b1_4_1382400,
2771 	pbn_b1_8_1382400,
2772 
2773 	pbn_b2_1_115200,
2774 	pbn_b2_2_115200,
2775 	pbn_b2_4_115200,
2776 	pbn_b2_8_115200,
2777 
2778 	pbn_b2_1_460800,
2779 	pbn_b2_4_460800,
2780 	pbn_b2_8_460800,
2781 	pbn_b2_16_460800,
2782 
2783 	pbn_b2_1_921600,
2784 	pbn_b2_4_921600,
2785 	pbn_b2_8_921600,
2786 
2787 	pbn_b2_8_1152000,
2788 
2789 	pbn_b2_bt_1_115200,
2790 	pbn_b2_bt_2_115200,
2791 	pbn_b2_bt_4_115200,
2792 
2793 	pbn_b2_bt_2_921600,
2794 	pbn_b2_bt_4_921600,
2795 
2796 	pbn_b3_2_115200,
2797 	pbn_b3_4_115200,
2798 	pbn_b3_8_115200,
2799 
2800 	pbn_b4_bt_2_921600,
2801 	pbn_b4_bt_4_921600,
2802 	pbn_b4_bt_8_921600,
2803 
2804 	/*
2805 	 * Board-specific versions.
2806 	 */
2807 	pbn_panacom,
2808 	pbn_panacom2,
2809 	pbn_panacom4,
2810 	pbn_plx_romulus,
2811 	pbn_endrun_2_4000000,
2812 	pbn_oxsemi,
2813 	pbn_oxsemi_1_4000000,
2814 	pbn_oxsemi_2_4000000,
2815 	pbn_oxsemi_4_4000000,
2816 	pbn_oxsemi_8_4000000,
2817 	pbn_intel_i960,
2818 	pbn_sgi_ioc3,
2819 	pbn_computone_4,
2820 	pbn_computone_6,
2821 	pbn_computone_8,
2822 	pbn_sbsxrsio,
2823 	pbn_exar_XR17C152,
2824 	pbn_exar_XR17C154,
2825 	pbn_exar_XR17C158,
2826 	pbn_exar_XR17V352,
2827 	pbn_exar_XR17V354,
2828 	pbn_exar_XR17V358,
2829 	pbn_exar_XR17V4358,
2830 	pbn_exar_XR17V8358,
2831 	pbn_exar_ibm_saturn,
2832 	pbn_pasemi_1682M,
2833 	pbn_ni8430_2,
2834 	pbn_ni8430_4,
2835 	pbn_ni8430_8,
2836 	pbn_ni8430_16,
2837 	pbn_ADDIDATA_PCIe_1_3906250,
2838 	pbn_ADDIDATA_PCIe_2_3906250,
2839 	pbn_ADDIDATA_PCIe_4_3906250,
2840 	pbn_ADDIDATA_PCIe_8_3906250,
2841 	pbn_ce4100_1_115200,
2842 	pbn_omegapci,
2843 	pbn_NETMOS9900_2s_115200,
2844 	pbn_brcm_trumanage,
2845 	pbn_fintek_4,
2846 	pbn_fintek_8,
2847 	pbn_fintek_12,
2848 	pbn_wch382_2,
2849 	pbn_wch384_4,
2850 	pbn_pericom_PI7C9X7951,
2851 	pbn_pericom_PI7C9X7952,
2852 	pbn_pericom_PI7C9X7954,
2853 	pbn_pericom_PI7C9X7958,
2854 };
2855 
2856 /*
2857  * uart_offset - the space between channels
2858  * reg_shift   - describes how the UART registers are mapped
2859  *               to PCI memory by the card.
2860  * For example IER register on SBS, Inc. PMC-OctPro is located at
2861  * offset 0x10 from the UART base, while UART_IER is defined as 1
2862  * in include/linux/serial_reg.h,
2863  * see first lines of serial_in() and serial_out() in 8250.c
2864 */
2865 
2866 static struct pciserial_board pci_boards[] = {
2867 	[pbn_default] = {
2868 		.flags		= FL_BASE0,
2869 		.num_ports	= 1,
2870 		.base_baud	= 115200,
2871 		.uart_offset	= 8,
2872 	},
2873 	[pbn_b0_1_115200] = {
2874 		.flags		= FL_BASE0,
2875 		.num_ports	= 1,
2876 		.base_baud	= 115200,
2877 		.uart_offset	= 8,
2878 	},
2879 	[pbn_b0_2_115200] = {
2880 		.flags		= FL_BASE0,
2881 		.num_ports	= 2,
2882 		.base_baud	= 115200,
2883 		.uart_offset	= 8,
2884 	},
2885 	[pbn_b0_4_115200] = {
2886 		.flags		= FL_BASE0,
2887 		.num_ports	= 4,
2888 		.base_baud	= 115200,
2889 		.uart_offset	= 8,
2890 	},
2891 	[pbn_b0_5_115200] = {
2892 		.flags		= FL_BASE0,
2893 		.num_ports	= 5,
2894 		.base_baud	= 115200,
2895 		.uart_offset	= 8,
2896 	},
2897 	[pbn_b0_8_115200] = {
2898 		.flags		= FL_BASE0,
2899 		.num_ports	= 8,
2900 		.base_baud	= 115200,
2901 		.uart_offset	= 8,
2902 	},
2903 	[pbn_b0_1_921600] = {
2904 		.flags		= FL_BASE0,
2905 		.num_ports	= 1,
2906 		.base_baud	= 921600,
2907 		.uart_offset	= 8,
2908 	},
2909 	[pbn_b0_2_921600] = {
2910 		.flags		= FL_BASE0,
2911 		.num_ports	= 2,
2912 		.base_baud	= 921600,
2913 		.uart_offset	= 8,
2914 	},
2915 	[pbn_b0_4_921600] = {
2916 		.flags		= FL_BASE0,
2917 		.num_ports	= 4,
2918 		.base_baud	= 921600,
2919 		.uart_offset	= 8,
2920 	},
2921 
2922 	[pbn_b0_2_1130000] = {
2923 		.flags          = FL_BASE0,
2924 		.num_ports      = 2,
2925 		.base_baud      = 1130000,
2926 		.uart_offset    = 8,
2927 	},
2928 
2929 	[pbn_b0_4_1152000] = {
2930 		.flags		= FL_BASE0,
2931 		.num_ports	= 4,
2932 		.base_baud	= 1152000,
2933 		.uart_offset	= 8,
2934 	},
2935 
2936 	[pbn_b0_2_1152000_200] = {
2937 		.flags		= FL_BASE0,
2938 		.num_ports	= 2,
2939 		.base_baud	= 1152000,
2940 		.uart_offset	= 0x200,
2941 	},
2942 
2943 	[pbn_b0_4_1152000_200] = {
2944 		.flags		= FL_BASE0,
2945 		.num_ports	= 4,
2946 		.base_baud	= 1152000,
2947 		.uart_offset	= 0x200,
2948 	},
2949 
2950 	[pbn_b0_8_1152000_200] = {
2951 		.flags		= FL_BASE0,
2952 		.num_ports	= 8,
2953 		.base_baud	= 1152000,
2954 		.uart_offset	= 0x200,
2955 	},
2956 
2957 	[pbn_b0_2_1843200] = {
2958 		.flags		= FL_BASE0,
2959 		.num_ports	= 2,
2960 		.base_baud	= 1843200,
2961 		.uart_offset	= 8,
2962 	},
2963 	[pbn_b0_4_1843200] = {
2964 		.flags		= FL_BASE0,
2965 		.num_ports	= 4,
2966 		.base_baud	= 1843200,
2967 		.uart_offset	= 8,
2968 	},
2969 
2970 	[pbn_b0_2_1843200_200] = {
2971 		.flags		= FL_BASE0,
2972 		.num_ports	= 2,
2973 		.base_baud	= 1843200,
2974 		.uart_offset	= 0x200,
2975 	},
2976 	[pbn_b0_4_1843200_200] = {
2977 		.flags		= FL_BASE0,
2978 		.num_ports	= 4,
2979 		.base_baud	= 1843200,
2980 		.uart_offset	= 0x200,
2981 	},
2982 	[pbn_b0_8_1843200_200] = {
2983 		.flags		= FL_BASE0,
2984 		.num_ports	= 8,
2985 		.base_baud	= 1843200,
2986 		.uart_offset	= 0x200,
2987 	},
2988 	[pbn_b0_1_4000000] = {
2989 		.flags		= FL_BASE0,
2990 		.num_ports	= 1,
2991 		.base_baud	= 4000000,
2992 		.uart_offset	= 8,
2993 	},
2994 
2995 	[pbn_b0_bt_1_115200] = {
2996 		.flags		= FL_BASE0|FL_BASE_BARS,
2997 		.num_ports	= 1,
2998 		.base_baud	= 115200,
2999 		.uart_offset	= 8,
3000 	},
3001 	[pbn_b0_bt_2_115200] = {
3002 		.flags		= FL_BASE0|FL_BASE_BARS,
3003 		.num_ports	= 2,
3004 		.base_baud	= 115200,
3005 		.uart_offset	= 8,
3006 	},
3007 	[pbn_b0_bt_4_115200] = {
3008 		.flags		= FL_BASE0|FL_BASE_BARS,
3009 		.num_ports	= 4,
3010 		.base_baud	= 115200,
3011 		.uart_offset	= 8,
3012 	},
3013 	[pbn_b0_bt_8_115200] = {
3014 		.flags		= FL_BASE0|FL_BASE_BARS,
3015 		.num_ports	= 8,
3016 		.base_baud	= 115200,
3017 		.uart_offset	= 8,
3018 	},
3019 
3020 	[pbn_b0_bt_1_460800] = {
3021 		.flags		= FL_BASE0|FL_BASE_BARS,
3022 		.num_ports	= 1,
3023 		.base_baud	= 460800,
3024 		.uart_offset	= 8,
3025 	},
3026 	[pbn_b0_bt_2_460800] = {
3027 		.flags		= FL_BASE0|FL_BASE_BARS,
3028 		.num_ports	= 2,
3029 		.base_baud	= 460800,
3030 		.uart_offset	= 8,
3031 	},
3032 	[pbn_b0_bt_4_460800] = {
3033 		.flags		= FL_BASE0|FL_BASE_BARS,
3034 		.num_ports	= 4,
3035 		.base_baud	= 460800,
3036 		.uart_offset	= 8,
3037 	},
3038 
3039 	[pbn_b0_bt_1_921600] = {
3040 		.flags		= FL_BASE0|FL_BASE_BARS,
3041 		.num_ports	= 1,
3042 		.base_baud	= 921600,
3043 		.uart_offset	= 8,
3044 	},
3045 	[pbn_b0_bt_2_921600] = {
3046 		.flags		= FL_BASE0|FL_BASE_BARS,
3047 		.num_ports	= 2,
3048 		.base_baud	= 921600,
3049 		.uart_offset	= 8,
3050 	},
3051 	[pbn_b0_bt_4_921600] = {
3052 		.flags		= FL_BASE0|FL_BASE_BARS,
3053 		.num_ports	= 4,
3054 		.base_baud	= 921600,
3055 		.uart_offset	= 8,
3056 	},
3057 	[pbn_b0_bt_8_921600] = {
3058 		.flags		= FL_BASE0|FL_BASE_BARS,
3059 		.num_ports	= 8,
3060 		.base_baud	= 921600,
3061 		.uart_offset	= 8,
3062 	},
3063 
3064 	[pbn_b1_1_115200] = {
3065 		.flags		= FL_BASE1,
3066 		.num_ports	= 1,
3067 		.base_baud	= 115200,
3068 		.uart_offset	= 8,
3069 	},
3070 	[pbn_b1_2_115200] = {
3071 		.flags		= FL_BASE1,
3072 		.num_ports	= 2,
3073 		.base_baud	= 115200,
3074 		.uart_offset	= 8,
3075 	},
3076 	[pbn_b1_4_115200] = {
3077 		.flags		= FL_BASE1,
3078 		.num_ports	= 4,
3079 		.base_baud	= 115200,
3080 		.uart_offset	= 8,
3081 	},
3082 	[pbn_b1_8_115200] = {
3083 		.flags		= FL_BASE1,
3084 		.num_ports	= 8,
3085 		.base_baud	= 115200,
3086 		.uart_offset	= 8,
3087 	},
3088 	[pbn_b1_16_115200] = {
3089 		.flags		= FL_BASE1,
3090 		.num_ports	= 16,
3091 		.base_baud	= 115200,
3092 		.uart_offset	= 8,
3093 	},
3094 
3095 	[pbn_b1_1_921600] = {
3096 		.flags		= FL_BASE1,
3097 		.num_ports	= 1,
3098 		.base_baud	= 921600,
3099 		.uart_offset	= 8,
3100 	},
3101 	[pbn_b1_2_921600] = {
3102 		.flags		= FL_BASE1,
3103 		.num_ports	= 2,
3104 		.base_baud	= 921600,
3105 		.uart_offset	= 8,
3106 	},
3107 	[pbn_b1_4_921600] = {
3108 		.flags		= FL_BASE1,
3109 		.num_ports	= 4,
3110 		.base_baud	= 921600,
3111 		.uart_offset	= 8,
3112 	},
3113 	[pbn_b1_8_921600] = {
3114 		.flags		= FL_BASE1,
3115 		.num_ports	= 8,
3116 		.base_baud	= 921600,
3117 		.uart_offset	= 8,
3118 	},
3119 	[pbn_b1_2_1250000] = {
3120 		.flags		= FL_BASE1,
3121 		.num_ports	= 2,
3122 		.base_baud	= 1250000,
3123 		.uart_offset	= 8,
3124 	},
3125 
3126 	[pbn_b1_bt_1_115200] = {
3127 		.flags		= FL_BASE1|FL_BASE_BARS,
3128 		.num_ports	= 1,
3129 		.base_baud	= 115200,
3130 		.uart_offset	= 8,
3131 	},
3132 	[pbn_b1_bt_2_115200] = {
3133 		.flags		= FL_BASE1|FL_BASE_BARS,
3134 		.num_ports	= 2,
3135 		.base_baud	= 115200,
3136 		.uart_offset	= 8,
3137 	},
3138 	[pbn_b1_bt_4_115200] = {
3139 		.flags		= FL_BASE1|FL_BASE_BARS,
3140 		.num_ports	= 4,
3141 		.base_baud	= 115200,
3142 		.uart_offset	= 8,
3143 	},
3144 
3145 	[pbn_b1_bt_2_921600] = {
3146 		.flags		= FL_BASE1|FL_BASE_BARS,
3147 		.num_ports	= 2,
3148 		.base_baud	= 921600,
3149 		.uart_offset	= 8,
3150 	},
3151 
3152 	[pbn_b1_1_1382400] = {
3153 		.flags		= FL_BASE1,
3154 		.num_ports	= 1,
3155 		.base_baud	= 1382400,
3156 		.uart_offset	= 8,
3157 	},
3158 	[pbn_b1_2_1382400] = {
3159 		.flags		= FL_BASE1,
3160 		.num_ports	= 2,
3161 		.base_baud	= 1382400,
3162 		.uart_offset	= 8,
3163 	},
3164 	[pbn_b1_4_1382400] = {
3165 		.flags		= FL_BASE1,
3166 		.num_ports	= 4,
3167 		.base_baud	= 1382400,
3168 		.uart_offset	= 8,
3169 	},
3170 	[pbn_b1_8_1382400] = {
3171 		.flags		= FL_BASE1,
3172 		.num_ports	= 8,
3173 		.base_baud	= 1382400,
3174 		.uart_offset	= 8,
3175 	},
3176 
3177 	[pbn_b2_1_115200] = {
3178 		.flags		= FL_BASE2,
3179 		.num_ports	= 1,
3180 		.base_baud	= 115200,
3181 		.uart_offset	= 8,
3182 	},
3183 	[pbn_b2_2_115200] = {
3184 		.flags		= FL_BASE2,
3185 		.num_ports	= 2,
3186 		.base_baud	= 115200,
3187 		.uart_offset	= 8,
3188 	},
3189 	[pbn_b2_4_115200] = {
3190 		.flags          = FL_BASE2,
3191 		.num_ports      = 4,
3192 		.base_baud      = 115200,
3193 		.uart_offset    = 8,
3194 	},
3195 	[pbn_b2_8_115200] = {
3196 		.flags		= FL_BASE2,
3197 		.num_ports	= 8,
3198 		.base_baud	= 115200,
3199 		.uart_offset	= 8,
3200 	},
3201 
3202 	[pbn_b2_1_460800] = {
3203 		.flags		= FL_BASE2,
3204 		.num_ports	= 1,
3205 		.base_baud	= 460800,
3206 		.uart_offset	= 8,
3207 	},
3208 	[pbn_b2_4_460800] = {
3209 		.flags		= FL_BASE2,
3210 		.num_ports	= 4,
3211 		.base_baud	= 460800,
3212 		.uart_offset	= 8,
3213 	},
3214 	[pbn_b2_8_460800] = {
3215 		.flags		= FL_BASE2,
3216 		.num_ports	= 8,
3217 		.base_baud	= 460800,
3218 		.uart_offset	= 8,
3219 	},
3220 	[pbn_b2_16_460800] = {
3221 		.flags		= FL_BASE2,
3222 		.num_ports	= 16,
3223 		.base_baud	= 460800,
3224 		.uart_offset	= 8,
3225 	 },
3226 
3227 	[pbn_b2_1_921600] = {
3228 		.flags		= FL_BASE2,
3229 		.num_ports	= 1,
3230 		.base_baud	= 921600,
3231 		.uart_offset	= 8,
3232 	},
3233 	[pbn_b2_4_921600] = {
3234 		.flags		= FL_BASE2,
3235 		.num_ports	= 4,
3236 		.base_baud	= 921600,
3237 		.uart_offset	= 8,
3238 	},
3239 	[pbn_b2_8_921600] = {
3240 		.flags		= FL_BASE2,
3241 		.num_ports	= 8,
3242 		.base_baud	= 921600,
3243 		.uart_offset	= 8,
3244 	},
3245 
3246 	[pbn_b2_8_1152000] = {
3247 		.flags		= FL_BASE2,
3248 		.num_ports	= 8,
3249 		.base_baud	= 1152000,
3250 		.uart_offset	= 8,
3251 	},
3252 
3253 	[pbn_b2_bt_1_115200] = {
3254 		.flags		= FL_BASE2|FL_BASE_BARS,
3255 		.num_ports	= 1,
3256 		.base_baud	= 115200,
3257 		.uart_offset	= 8,
3258 	},
3259 	[pbn_b2_bt_2_115200] = {
3260 		.flags		= FL_BASE2|FL_BASE_BARS,
3261 		.num_ports	= 2,
3262 		.base_baud	= 115200,
3263 		.uart_offset	= 8,
3264 	},
3265 	[pbn_b2_bt_4_115200] = {
3266 		.flags		= FL_BASE2|FL_BASE_BARS,
3267 		.num_ports	= 4,
3268 		.base_baud	= 115200,
3269 		.uart_offset	= 8,
3270 	},
3271 
3272 	[pbn_b2_bt_2_921600] = {
3273 		.flags		= FL_BASE2|FL_BASE_BARS,
3274 		.num_ports	= 2,
3275 		.base_baud	= 921600,
3276 		.uart_offset	= 8,
3277 	},
3278 	[pbn_b2_bt_4_921600] = {
3279 		.flags		= FL_BASE2|FL_BASE_BARS,
3280 		.num_ports	= 4,
3281 		.base_baud	= 921600,
3282 		.uart_offset	= 8,
3283 	},
3284 
3285 	[pbn_b3_2_115200] = {
3286 		.flags		= FL_BASE3,
3287 		.num_ports	= 2,
3288 		.base_baud	= 115200,
3289 		.uart_offset	= 8,
3290 	},
3291 	[pbn_b3_4_115200] = {
3292 		.flags		= FL_BASE3,
3293 		.num_ports	= 4,
3294 		.base_baud	= 115200,
3295 		.uart_offset	= 8,
3296 	},
3297 	[pbn_b3_8_115200] = {
3298 		.flags		= FL_BASE3,
3299 		.num_ports	= 8,
3300 		.base_baud	= 115200,
3301 		.uart_offset	= 8,
3302 	},
3303 
3304 	[pbn_b4_bt_2_921600] = {
3305 		.flags		= FL_BASE4,
3306 		.num_ports	= 2,
3307 		.base_baud	= 921600,
3308 		.uart_offset	= 8,
3309 	},
3310 	[pbn_b4_bt_4_921600] = {
3311 		.flags		= FL_BASE4,
3312 		.num_ports	= 4,
3313 		.base_baud	= 921600,
3314 		.uart_offset	= 8,
3315 	},
3316 	[pbn_b4_bt_8_921600] = {
3317 		.flags		= FL_BASE4,
3318 		.num_ports	= 8,
3319 		.base_baud	= 921600,
3320 		.uart_offset	= 8,
3321 	},
3322 
3323 	/*
3324 	 * Entries following this are board-specific.
3325 	 */
3326 
3327 	/*
3328 	 * Panacom - IOMEM
3329 	 */
3330 	[pbn_panacom] = {
3331 		.flags		= FL_BASE2,
3332 		.num_ports	= 2,
3333 		.base_baud	= 921600,
3334 		.uart_offset	= 0x400,
3335 		.reg_shift	= 7,
3336 	},
3337 	[pbn_panacom2] = {
3338 		.flags		= FL_BASE2|FL_BASE_BARS,
3339 		.num_ports	= 2,
3340 		.base_baud	= 921600,
3341 		.uart_offset	= 0x400,
3342 		.reg_shift	= 7,
3343 	},
3344 	[pbn_panacom4] = {
3345 		.flags		= FL_BASE2|FL_BASE_BARS,
3346 		.num_ports	= 4,
3347 		.base_baud	= 921600,
3348 		.uart_offset	= 0x400,
3349 		.reg_shift	= 7,
3350 	},
3351 
3352 	/* I think this entry is broken - the first_offset looks wrong --rmk */
3353 	[pbn_plx_romulus] = {
3354 		.flags		= FL_BASE2,
3355 		.num_ports	= 4,
3356 		.base_baud	= 921600,
3357 		.uart_offset	= 8 << 2,
3358 		.reg_shift	= 2,
3359 		.first_offset	= 0x03,
3360 	},
3361 
3362 	/*
3363 	 * EndRun Technologies
3364 	* Uses the size of PCI Base region 0 to
3365 	* signal now many ports are available
3366 	* 2 port 952 Uart support
3367 	*/
3368 	[pbn_endrun_2_4000000] = {
3369 		.flags		= FL_BASE0,
3370 		.num_ports	= 2,
3371 		.base_baud	= 4000000,
3372 		.uart_offset	= 0x200,
3373 		.first_offset	= 0x1000,
3374 	},
3375 
3376 	/*
3377 	 * This board uses the size of PCI Base region 0 to
3378 	 * signal now many ports are available
3379 	 */
3380 	[pbn_oxsemi] = {
3381 		.flags		= FL_BASE0|FL_REGION_SZ_CAP,
3382 		.num_ports	= 32,
3383 		.base_baud	= 115200,
3384 		.uart_offset	= 8,
3385 	},
3386 	[pbn_oxsemi_1_4000000] = {
3387 		.flags		= FL_BASE0,
3388 		.num_ports	= 1,
3389 		.base_baud	= 4000000,
3390 		.uart_offset	= 0x200,
3391 		.first_offset	= 0x1000,
3392 	},
3393 	[pbn_oxsemi_2_4000000] = {
3394 		.flags		= FL_BASE0,
3395 		.num_ports	= 2,
3396 		.base_baud	= 4000000,
3397 		.uart_offset	= 0x200,
3398 		.first_offset	= 0x1000,
3399 	},
3400 	[pbn_oxsemi_4_4000000] = {
3401 		.flags		= FL_BASE0,
3402 		.num_ports	= 4,
3403 		.base_baud	= 4000000,
3404 		.uart_offset	= 0x200,
3405 		.first_offset	= 0x1000,
3406 	},
3407 	[pbn_oxsemi_8_4000000] = {
3408 		.flags		= FL_BASE0,
3409 		.num_ports	= 8,
3410 		.base_baud	= 4000000,
3411 		.uart_offset	= 0x200,
3412 		.first_offset	= 0x1000,
3413 	},
3414 
3415 
3416 	/*
3417 	 * EKF addition for i960 Boards form EKF with serial port.
3418 	 * Max 256 ports.
3419 	 */
3420 	[pbn_intel_i960] = {
3421 		.flags		= FL_BASE0,
3422 		.num_ports	= 32,
3423 		.base_baud	= 921600,
3424 		.uart_offset	= 8 << 2,
3425 		.reg_shift	= 2,
3426 		.first_offset	= 0x10000,
3427 	},
3428 	[pbn_sgi_ioc3] = {
3429 		.flags		= FL_BASE0|FL_NOIRQ,
3430 		.num_ports	= 1,
3431 		.base_baud	= 458333,
3432 		.uart_offset	= 8,
3433 		.reg_shift	= 0,
3434 		.first_offset	= 0x20178,
3435 	},
3436 
3437 	/*
3438 	 * Computone - uses IOMEM.
3439 	 */
3440 	[pbn_computone_4] = {
3441 		.flags		= FL_BASE0,
3442 		.num_ports	= 4,
3443 		.base_baud	= 921600,
3444 		.uart_offset	= 0x40,
3445 		.reg_shift	= 2,
3446 		.first_offset	= 0x200,
3447 	},
3448 	[pbn_computone_6] = {
3449 		.flags		= FL_BASE0,
3450 		.num_ports	= 6,
3451 		.base_baud	= 921600,
3452 		.uart_offset	= 0x40,
3453 		.reg_shift	= 2,
3454 		.first_offset	= 0x200,
3455 	},
3456 	[pbn_computone_8] = {
3457 		.flags		= FL_BASE0,
3458 		.num_ports	= 8,
3459 		.base_baud	= 921600,
3460 		.uart_offset	= 0x40,
3461 		.reg_shift	= 2,
3462 		.first_offset	= 0x200,
3463 	},
3464 	[pbn_sbsxrsio] = {
3465 		.flags		= FL_BASE0,
3466 		.num_ports	= 8,
3467 		.base_baud	= 460800,
3468 		.uart_offset	= 256,
3469 		.reg_shift	= 4,
3470 	},
3471 	/*
3472 	 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3473 	 *  Only basic 16550A support.
3474 	 *  XR17C15[24] are not tested, but they should work.
3475 	 */
3476 	[pbn_exar_XR17C152] = {
3477 		.flags		= FL_BASE0,
3478 		.num_ports	= 2,
3479 		.base_baud	= 921600,
3480 		.uart_offset	= 0x200,
3481 	},
3482 	[pbn_exar_XR17C154] = {
3483 		.flags		= FL_BASE0,
3484 		.num_ports	= 4,
3485 		.base_baud	= 921600,
3486 		.uart_offset	= 0x200,
3487 	},
3488 	[pbn_exar_XR17C158] = {
3489 		.flags		= FL_BASE0,
3490 		.num_ports	= 8,
3491 		.base_baud	= 921600,
3492 		.uart_offset	= 0x200,
3493 	},
3494 	[pbn_exar_XR17V352] = {
3495 		.flags		= FL_BASE0,
3496 		.num_ports	= 2,
3497 		.base_baud	= 7812500,
3498 		.uart_offset	= 0x400,
3499 		.reg_shift	= 0,
3500 		.first_offset	= 0,
3501 	},
3502 	[pbn_exar_XR17V354] = {
3503 		.flags		= FL_BASE0,
3504 		.num_ports	= 4,
3505 		.base_baud	= 7812500,
3506 		.uart_offset	= 0x400,
3507 		.reg_shift	= 0,
3508 		.first_offset	= 0,
3509 	},
3510 	[pbn_exar_XR17V358] = {
3511 		.flags		= FL_BASE0,
3512 		.num_ports	= 8,
3513 		.base_baud	= 7812500,
3514 		.uart_offset	= 0x400,
3515 		.reg_shift	= 0,
3516 		.first_offset	= 0,
3517 	},
3518 	[pbn_exar_XR17V4358] = {
3519 		.flags		= FL_BASE0,
3520 		.num_ports	= 12,
3521 		.base_baud	= 7812500,
3522 		.uart_offset	= 0x400,
3523 		.reg_shift	= 0,
3524 		.first_offset	= 0,
3525 	},
3526 	[pbn_exar_XR17V8358] = {
3527 		.flags		= FL_BASE0,
3528 		.num_ports	= 16,
3529 		.base_baud	= 7812500,
3530 		.uart_offset	= 0x400,
3531 		.reg_shift	= 0,
3532 		.first_offset	= 0,
3533 	},
3534 	[pbn_exar_ibm_saturn] = {
3535 		.flags		= FL_BASE0,
3536 		.num_ports	= 1,
3537 		.base_baud	= 921600,
3538 		.uart_offset	= 0x200,
3539 	},
3540 
3541 	/*
3542 	 * PA Semi PWRficient PA6T-1682M on-chip UART
3543 	 */
3544 	[pbn_pasemi_1682M] = {
3545 		.flags		= FL_BASE0,
3546 		.num_ports	= 1,
3547 		.base_baud	= 8333333,
3548 	},
3549 	/*
3550 	 * National Instruments 843x
3551 	 */
3552 	[pbn_ni8430_16] = {
3553 		.flags		= FL_BASE0,
3554 		.num_ports	= 16,
3555 		.base_baud	= 3686400,
3556 		.uart_offset	= 0x10,
3557 		.first_offset	= 0x800,
3558 	},
3559 	[pbn_ni8430_8] = {
3560 		.flags		= FL_BASE0,
3561 		.num_ports	= 8,
3562 		.base_baud	= 3686400,
3563 		.uart_offset	= 0x10,
3564 		.first_offset	= 0x800,
3565 	},
3566 	[pbn_ni8430_4] = {
3567 		.flags		= FL_BASE0,
3568 		.num_ports	= 4,
3569 		.base_baud	= 3686400,
3570 		.uart_offset	= 0x10,
3571 		.first_offset	= 0x800,
3572 	},
3573 	[pbn_ni8430_2] = {
3574 		.flags		= FL_BASE0,
3575 		.num_ports	= 2,
3576 		.base_baud	= 3686400,
3577 		.uart_offset	= 0x10,
3578 		.first_offset	= 0x800,
3579 	},
3580 	/*
3581 	 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3582 	 */
3583 	[pbn_ADDIDATA_PCIe_1_3906250] = {
3584 		.flags		= FL_BASE0,
3585 		.num_ports	= 1,
3586 		.base_baud	= 3906250,
3587 		.uart_offset	= 0x200,
3588 		.first_offset	= 0x1000,
3589 	},
3590 	[pbn_ADDIDATA_PCIe_2_3906250] = {
3591 		.flags		= FL_BASE0,
3592 		.num_ports	= 2,
3593 		.base_baud	= 3906250,
3594 		.uart_offset	= 0x200,
3595 		.first_offset	= 0x1000,
3596 	},
3597 	[pbn_ADDIDATA_PCIe_4_3906250] = {
3598 		.flags		= FL_BASE0,
3599 		.num_ports	= 4,
3600 		.base_baud	= 3906250,
3601 		.uart_offset	= 0x200,
3602 		.first_offset	= 0x1000,
3603 	},
3604 	[pbn_ADDIDATA_PCIe_8_3906250] = {
3605 		.flags		= FL_BASE0,
3606 		.num_ports	= 8,
3607 		.base_baud	= 3906250,
3608 		.uart_offset	= 0x200,
3609 		.first_offset	= 0x1000,
3610 	},
3611 	[pbn_ce4100_1_115200] = {
3612 		.flags		= FL_BASE_BARS,
3613 		.num_ports	= 2,
3614 		.base_baud	= 921600,
3615 		.reg_shift      = 2,
3616 	},
3617 	[pbn_omegapci] = {
3618 		.flags		= FL_BASE0,
3619 		.num_ports	= 8,
3620 		.base_baud	= 115200,
3621 		.uart_offset	= 0x200,
3622 	},
3623 	[pbn_NETMOS9900_2s_115200] = {
3624 		.flags		= FL_BASE0,
3625 		.num_ports	= 2,
3626 		.base_baud	= 115200,
3627 	},
3628 	[pbn_brcm_trumanage] = {
3629 		.flags		= FL_BASE0,
3630 		.num_ports	= 1,
3631 		.reg_shift	= 2,
3632 		.base_baud	= 115200,
3633 	},
3634 	[pbn_fintek_4] = {
3635 		.num_ports	= 4,
3636 		.uart_offset	= 8,
3637 		.base_baud	= 115200,
3638 		.first_offset	= 0x40,
3639 	},
3640 	[pbn_fintek_8] = {
3641 		.num_ports	= 8,
3642 		.uart_offset	= 8,
3643 		.base_baud	= 115200,
3644 		.first_offset	= 0x40,
3645 	},
3646 	[pbn_fintek_12] = {
3647 		.num_ports	= 12,
3648 		.uart_offset	= 8,
3649 		.base_baud	= 115200,
3650 		.first_offset	= 0x40,
3651 	},
3652 	[pbn_wch382_2] = {
3653 		.flags		= FL_BASE0,
3654 		.num_ports	= 2,
3655 		.base_baud	= 115200,
3656 		.uart_offset	= 8,
3657 		.first_offset	= 0xC0,
3658 	},
3659 	[pbn_wch384_4] = {
3660 		.flags		= FL_BASE0,
3661 		.num_ports	= 4,
3662 		.base_baud      = 115200,
3663 		.uart_offset    = 8,
3664 		.first_offset   = 0xC0,
3665 	},
3666 	/*
3667 	 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3668 	 */
3669 	[pbn_pericom_PI7C9X7951] = {
3670 		.flags          = FL_BASE0,
3671 		.num_ports      = 1,
3672 		.base_baud      = 921600,
3673 		.uart_offset	= 0x8,
3674 	},
3675 	[pbn_pericom_PI7C9X7952] = {
3676 		.flags          = FL_BASE0,
3677 		.num_ports      = 2,
3678 		.base_baud      = 921600,
3679 		.uart_offset	= 0x8,
3680 	},
3681 	[pbn_pericom_PI7C9X7954] = {
3682 		.flags          = FL_BASE0,
3683 		.num_ports      = 4,
3684 		.base_baud      = 921600,
3685 		.uart_offset	= 0x8,
3686 	},
3687 	[pbn_pericom_PI7C9X7958] = {
3688 		.flags          = FL_BASE0,
3689 		.num_ports      = 8,
3690 		.base_baud      = 921600,
3691 		.uart_offset	= 0x8,
3692 	},
3693 };
3694 
3695 static const struct pci_device_id blacklist[] = {
3696 	/* softmodems */
3697 	{ PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3698 	{ PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3699 	{ PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3700 
3701 	/* multi-io cards handled by parport_serial */
3702 	{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3703 	{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3704 	{ PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3705 	{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3706 	{ PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3707 
3708 	/* Moxa Smartio MUE boards handled by 8250_moxa */
3709 	{ PCI_VDEVICE(MOXA, 0x1024), },
3710 	{ PCI_VDEVICE(MOXA, 0x1025), },
3711 	{ PCI_VDEVICE(MOXA, 0x1045), },
3712 	{ PCI_VDEVICE(MOXA, 0x1144), },
3713 	{ PCI_VDEVICE(MOXA, 0x1160), },
3714 	{ PCI_VDEVICE(MOXA, 0x1161), },
3715 	{ PCI_VDEVICE(MOXA, 0x1182), },
3716 	{ PCI_VDEVICE(MOXA, 0x1183), },
3717 	{ PCI_VDEVICE(MOXA, 0x1322), },
3718 	{ PCI_VDEVICE(MOXA, 0x1342), },
3719 	{ PCI_VDEVICE(MOXA, 0x1381), },
3720 	{ PCI_VDEVICE(MOXA, 0x1683), },
3721 
3722 	/* Intel platforms with MID UART */
3723 	{ PCI_VDEVICE(INTEL, 0x081b), },
3724 	{ PCI_VDEVICE(INTEL, 0x081c), },
3725 	{ PCI_VDEVICE(INTEL, 0x081d), },
3726 	{ PCI_VDEVICE(INTEL, 0x1191), },
3727 	{ PCI_VDEVICE(INTEL, 0x19d8), },
3728 
3729 	/* Intel platforms with DesignWare UART */
3730 	{ PCI_VDEVICE(INTEL, 0x0936), },
3731 	{ PCI_VDEVICE(INTEL, 0x0f0a), },
3732 	{ PCI_VDEVICE(INTEL, 0x0f0c), },
3733 	{ PCI_VDEVICE(INTEL, 0x228a), },
3734 	{ PCI_VDEVICE(INTEL, 0x228c), },
3735 	{ PCI_VDEVICE(INTEL, 0x9ce3), },
3736 	{ PCI_VDEVICE(INTEL, 0x9ce4), },
3737 };
3738 
3739 /*
3740  * Given a complete unknown PCI device, try to use some heuristics to
3741  * guess what the configuration might be, based on the pitiful PCI
3742  * serial specs.  Returns 0 on success, 1 on failure.
3743  */
3744 static int
3745 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3746 {
3747 	const struct pci_device_id *bldev;
3748 	int num_iomem, num_port, first_port = -1, i;
3749 
3750 	/*
3751 	 * If it is not a communications device or the programming
3752 	 * interface is greater than 6, give up.
3753 	 *
3754 	 * (Should we try to make guesses for multiport serial devices
3755 	 * later?)
3756 	 */
3757 	if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3758 	     ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3759 	    (dev->class & 0xff) > 6)
3760 		return -ENODEV;
3761 
3762 	/*
3763 	 * Do not access blacklisted devices that are known not to
3764 	 * feature serial ports or are handled by other modules.
3765 	 */
3766 	for (bldev = blacklist;
3767 	     bldev < blacklist + ARRAY_SIZE(blacklist);
3768 	     bldev++) {
3769 		if (dev->vendor == bldev->vendor &&
3770 		    dev->device == bldev->device)
3771 			return -ENODEV;
3772 	}
3773 
3774 	num_iomem = num_port = 0;
3775 	for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3776 		if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3777 			num_port++;
3778 			if (first_port == -1)
3779 				first_port = i;
3780 		}
3781 		if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3782 			num_iomem++;
3783 	}
3784 
3785 	/*
3786 	 * If there is 1 or 0 iomem regions, and exactly one port,
3787 	 * use it.  We guess the number of ports based on the IO
3788 	 * region size.
3789 	 */
3790 	if (num_iomem <= 1 && num_port == 1) {
3791 		board->flags = first_port;
3792 		board->num_ports = pci_resource_len(dev, first_port) / 8;
3793 		return 0;
3794 	}
3795 
3796 	/*
3797 	 * Now guess if we've got a board which indexes by BARs.
3798 	 * Each IO BAR should be 8 bytes, and they should follow
3799 	 * consecutively.
3800 	 */
3801 	first_port = -1;
3802 	num_port = 0;
3803 	for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3804 		if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3805 		    pci_resource_len(dev, i) == 8 &&
3806 		    (first_port == -1 || (first_port + num_port) == i)) {
3807 			num_port++;
3808 			if (first_port == -1)
3809 				first_port = i;
3810 		}
3811 	}
3812 
3813 	if (num_port > 1) {
3814 		board->flags = first_port | FL_BASE_BARS;
3815 		board->num_ports = num_port;
3816 		return 0;
3817 	}
3818 
3819 	return -ENODEV;
3820 }
3821 
3822 static inline int
3823 serial_pci_matches(const struct pciserial_board *board,
3824 		   const struct pciserial_board *guessed)
3825 {
3826 	return
3827 	    board->num_ports == guessed->num_ports &&
3828 	    board->base_baud == guessed->base_baud &&
3829 	    board->uart_offset == guessed->uart_offset &&
3830 	    board->reg_shift == guessed->reg_shift &&
3831 	    board->first_offset == guessed->first_offset;
3832 }
3833 
3834 struct serial_private *
3835 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3836 {
3837 	struct uart_8250_port uart;
3838 	struct serial_private *priv;
3839 	struct pci_serial_quirk *quirk;
3840 	int rc, nr_ports, i;
3841 
3842 	nr_ports = board->num_ports;
3843 
3844 	/*
3845 	 * Find an init and setup quirks.
3846 	 */
3847 	quirk = find_quirk(dev);
3848 
3849 	/*
3850 	 * Run the new-style initialization function.
3851 	 * The initialization function returns:
3852 	 *  <0  - error
3853 	 *   0  - use board->num_ports
3854 	 *  >0  - number of ports
3855 	 */
3856 	if (quirk->init) {
3857 		rc = quirk->init(dev);
3858 		if (rc < 0) {
3859 			priv = ERR_PTR(rc);
3860 			goto err_out;
3861 		}
3862 		if (rc)
3863 			nr_ports = rc;
3864 	}
3865 
3866 	priv = kzalloc(sizeof(struct serial_private) +
3867 		       sizeof(unsigned int) * nr_ports,
3868 		       GFP_KERNEL);
3869 	if (!priv) {
3870 		priv = ERR_PTR(-ENOMEM);
3871 		goto err_deinit;
3872 	}
3873 
3874 	priv->dev = dev;
3875 	priv->quirk = quirk;
3876 
3877 	memset(&uart, 0, sizeof(uart));
3878 	uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3879 	uart.port.uartclk = board->base_baud * 16;
3880 	uart.port.irq = get_pci_irq(dev, board);
3881 	uart.port.dev = &dev->dev;
3882 
3883 	for (i = 0; i < nr_ports; i++) {
3884 		if (quirk->setup(priv, board, &uart, i))
3885 			break;
3886 
3887 		dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3888 			uart.port.iobase, uart.port.irq, uart.port.iotype);
3889 
3890 		priv->line[i] = serial8250_register_8250_port(&uart);
3891 		if (priv->line[i] < 0) {
3892 			dev_err(&dev->dev,
3893 				"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3894 				uart.port.iobase, uart.port.irq,
3895 				uart.port.iotype, priv->line[i]);
3896 			break;
3897 		}
3898 	}
3899 	priv->nr = i;
3900 	priv->board = board;
3901 	return priv;
3902 
3903 err_deinit:
3904 	if (quirk->exit)
3905 		quirk->exit(dev);
3906 err_out:
3907 	return priv;
3908 }
3909 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3910 
3911 void pciserial_detach_ports(struct serial_private *priv)
3912 {
3913 	struct pci_serial_quirk *quirk;
3914 	int i;
3915 
3916 	for (i = 0; i < priv->nr; i++)
3917 		serial8250_unregister_port(priv->line[i]);
3918 
3919 	/*
3920 	 * Find the exit quirks.
3921 	 */
3922 	quirk = find_quirk(priv->dev);
3923 	if (quirk->exit)
3924 		quirk->exit(priv->dev);
3925 }
3926 
3927 void pciserial_remove_ports(struct serial_private *priv)
3928 {
3929 	pciserial_detach_ports(priv);
3930 	kfree(priv);
3931 }
3932 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3933 
3934 void pciserial_suspend_ports(struct serial_private *priv)
3935 {
3936 	int i;
3937 
3938 	for (i = 0; i < priv->nr; i++)
3939 		if (priv->line[i] >= 0)
3940 			serial8250_suspend_port(priv->line[i]);
3941 
3942 	/*
3943 	 * Ensure that every init quirk is properly torn down
3944 	 */
3945 	if (priv->quirk->exit)
3946 		priv->quirk->exit(priv->dev);
3947 }
3948 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3949 
3950 void pciserial_resume_ports(struct serial_private *priv)
3951 {
3952 	int i;
3953 
3954 	/*
3955 	 * Ensure that the board is correctly configured.
3956 	 */
3957 	if (priv->quirk->init)
3958 		priv->quirk->init(priv->dev);
3959 
3960 	for (i = 0; i < priv->nr; i++)
3961 		if (priv->line[i] >= 0)
3962 			serial8250_resume_port(priv->line[i]);
3963 }
3964 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3965 
3966 /*
3967  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3968  * to the arrangement of serial ports on a PCI card.
3969  */
3970 static int
3971 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3972 {
3973 	struct pci_serial_quirk *quirk;
3974 	struct serial_private *priv;
3975 	const struct pciserial_board *board;
3976 	struct pciserial_board tmp;
3977 	int rc;
3978 
3979 	quirk = find_quirk(dev);
3980 	if (quirk->probe) {
3981 		rc = quirk->probe(dev);
3982 		if (rc)
3983 			return rc;
3984 	}
3985 
3986 	if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3987 		dev_err(&dev->dev, "invalid driver_data: %ld\n",
3988 			ent->driver_data);
3989 		return -EINVAL;
3990 	}
3991 
3992 	board = &pci_boards[ent->driver_data];
3993 
3994 	rc = pcim_enable_device(dev);
3995 	pci_save_state(dev);
3996 	if (rc)
3997 		return rc;
3998 
3999 	if (ent->driver_data == pbn_default) {
4000 		/*
4001 		 * Use a copy of the pci_board entry for this;
4002 		 * avoid changing entries in the table.
4003 		 */
4004 		memcpy(&tmp, board, sizeof(struct pciserial_board));
4005 		board = &tmp;
4006 
4007 		/*
4008 		 * We matched one of our class entries.  Try to
4009 		 * determine the parameters of this board.
4010 		 */
4011 		rc = serial_pci_guess_board(dev, &tmp);
4012 		if (rc)
4013 			return rc;
4014 	} else {
4015 		/*
4016 		 * We matched an explicit entry.  If we are able to
4017 		 * detect this boards settings with our heuristic,
4018 		 * then we no longer need this entry.
4019 		 */
4020 		memcpy(&tmp, &pci_boards[pbn_default],
4021 		       sizeof(struct pciserial_board));
4022 		rc = serial_pci_guess_board(dev, &tmp);
4023 		if (rc == 0 && serial_pci_matches(board, &tmp))
4024 			moan_device("Redundant entry in serial pci_table.",
4025 				    dev);
4026 	}
4027 
4028 	priv = pciserial_init_ports(dev, board);
4029 	if (IS_ERR(priv))
4030 		return PTR_ERR(priv);
4031 
4032 	pci_set_drvdata(dev, priv);
4033 	return 0;
4034 }
4035 
4036 static void pciserial_remove_one(struct pci_dev *dev)
4037 {
4038 	struct serial_private *priv = pci_get_drvdata(dev);
4039 
4040 	pciserial_remove_ports(priv);
4041 }
4042 
4043 #ifdef CONFIG_PM_SLEEP
4044 static int pciserial_suspend_one(struct device *dev)
4045 {
4046 	struct pci_dev *pdev = to_pci_dev(dev);
4047 	struct serial_private *priv = pci_get_drvdata(pdev);
4048 
4049 	if (priv)
4050 		pciserial_suspend_ports(priv);
4051 
4052 	return 0;
4053 }
4054 
4055 static int pciserial_resume_one(struct device *dev)
4056 {
4057 	struct pci_dev *pdev = to_pci_dev(dev);
4058 	struct serial_private *priv = pci_get_drvdata(pdev);
4059 	int err;
4060 
4061 	if (priv) {
4062 		/*
4063 		 * The device may have been disabled.  Re-enable it.
4064 		 */
4065 		err = pci_enable_device(pdev);
4066 		/* FIXME: We cannot simply error out here */
4067 		if (err)
4068 			dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4069 		pciserial_resume_ports(priv);
4070 	}
4071 	return 0;
4072 }
4073 #endif
4074 
4075 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4076 			 pciserial_resume_one);
4077 
4078 static struct pci_device_id serial_pci_tbl[] = {
4079 	/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4080 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4081 		PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4082 		pbn_b2_8_921600 },
4083 	/* Advantech also use 0x3618 and 0xf618 */
4084 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4085 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4086 		pbn_b0_4_921600 },
4087 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4088 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4089 		pbn_b0_4_921600 },
4090 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4091 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4092 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4093 		pbn_b1_8_1382400 },
4094 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4095 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4096 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4097 		pbn_b1_4_1382400 },
4098 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4099 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4100 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4101 		pbn_b1_2_1382400 },
4102 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4103 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4104 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4105 		pbn_b1_8_1382400 },
4106 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4107 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4108 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4109 		pbn_b1_4_1382400 },
4110 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4111 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4112 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4113 		pbn_b1_2_1382400 },
4114 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4115 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4116 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4117 		pbn_b1_8_921600 },
4118 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4119 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4120 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4121 		pbn_b1_8_921600 },
4122 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4123 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4124 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4125 		pbn_b1_4_921600 },
4126 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4127 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4128 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4129 		pbn_b1_4_921600 },
4130 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4131 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4132 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4133 		pbn_b1_2_921600 },
4134 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4135 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4136 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4137 		pbn_b1_8_921600 },
4138 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4139 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4140 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4141 		pbn_b1_8_921600 },
4142 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4143 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4144 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4145 		pbn_b1_4_921600 },
4146 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4147 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4148 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4149 		pbn_b1_2_1250000 },
4150 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4151 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4152 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4153 		pbn_b0_2_1843200 },
4154 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4155 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4156 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4157 		pbn_b0_4_1843200 },
4158 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4159 		PCI_VENDOR_ID_AFAVLAB,
4160 		PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4161 		pbn_b0_4_1152000 },
4162 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4163 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4164 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4165 		pbn_b0_2_1843200_200 },
4166 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4167 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4168 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4169 		pbn_b0_4_1843200_200 },
4170 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4171 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4172 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4173 		pbn_b0_8_1843200_200 },
4174 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4175 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4176 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4177 		pbn_b0_2_1843200_200 },
4178 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4179 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4180 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4181 		pbn_b0_4_1843200_200 },
4182 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4183 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4184 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4185 		pbn_b0_8_1843200_200 },
4186 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4187 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4188 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4189 		pbn_b0_2_1843200_200 },
4190 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4191 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4192 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4193 		pbn_b0_4_1843200_200 },
4194 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4195 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4196 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4197 		pbn_b0_8_1843200_200 },
4198 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4199 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4200 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4201 		pbn_b0_2_1843200_200 },
4202 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4203 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4204 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4205 		pbn_b0_4_1843200_200 },
4206 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4207 		PCI_SUBVENDOR_ID_CONNECT_TECH,
4208 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4209 		pbn_b0_8_1843200_200 },
4210 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4211 		PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4212 		0, 0, pbn_exar_ibm_saturn },
4213 
4214 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4215 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 		pbn_b2_bt_1_115200 },
4217 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4218 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 		pbn_b2_bt_2_115200 },
4220 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4221 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 		pbn_b2_bt_4_115200 },
4223 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4224 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 		pbn_b2_bt_2_115200 },
4226 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4227 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 		pbn_b2_bt_4_115200 },
4229 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4230 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 		pbn_b2_8_115200 },
4232 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4233 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 		pbn_b2_8_460800 },
4235 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4236 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 		pbn_b2_8_115200 },
4238 
4239 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4240 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241 		pbn_b2_bt_2_115200 },
4242 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4243 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244 		pbn_b2_bt_2_921600 },
4245 	/*
4246 	 * VScom SPCOM800, from sl@s.pl
4247 	 */
4248 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4249 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250 		pbn_b2_8_921600 },
4251 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4252 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253 		pbn_b2_4_921600 },
4254 	/* Unknown card - subdevice 0x1584 */
4255 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4256 		PCI_VENDOR_ID_PLX,
4257 		PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4258 		pbn_b2_4_115200 },
4259 	/* Unknown card - subdevice 0x1588 */
4260 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4261 		PCI_VENDOR_ID_PLX,
4262 		PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4263 		pbn_b2_8_115200 },
4264 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4265 		PCI_SUBVENDOR_ID_KEYSPAN,
4266 		PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4267 		pbn_panacom },
4268 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4269 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 		pbn_panacom4 },
4271 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4272 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 		pbn_panacom2 },
4274 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4275 		PCI_VENDOR_ID_ESDGMBH,
4276 		PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4277 		pbn_b2_4_115200 },
4278 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4279 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4280 		PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4281 		pbn_b2_4_460800 },
4282 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4283 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4284 		PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4285 		pbn_b2_8_460800 },
4286 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4287 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4288 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4289 		pbn_b2_16_460800 },
4290 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4291 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4292 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4293 		pbn_b2_16_460800 },
4294 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4295 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4296 		PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4297 		pbn_b2_4_460800 },
4298 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4299 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4300 		PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4301 		pbn_b2_8_460800 },
4302 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4303 		PCI_SUBVENDOR_ID_EXSYS,
4304 		PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4305 		pbn_b2_4_115200 },
4306 	/*
4307 	 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4308 	 * (Exoray@isys.ca)
4309 	 */
4310 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4311 		0x10b5, 0x106a, 0, 0,
4312 		pbn_plx_romulus },
4313 	/*
4314 	* EndRun Technologies. PCI express device range.
4315 	*    EndRun PTP/1588 has 2 Native UARTs.
4316 	*/
4317 	{	PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4318 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 		pbn_endrun_2_4000000 },
4320 	/*
4321 	 * Quatech cards. These actually have configurable clocks but for
4322 	 * now we just use the default.
4323 	 *
4324 	 * 100 series are RS232, 200 series RS422,
4325 	 */
4326 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4327 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 		pbn_b1_4_115200 },
4329 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4330 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 		pbn_b1_2_115200 },
4332 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4333 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 		pbn_b2_2_115200 },
4335 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4336 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337 		pbn_b1_2_115200 },
4338 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4339 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 		pbn_b2_2_115200 },
4341 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4342 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4343 		pbn_b1_4_115200 },
4344 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4345 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346 		pbn_b1_8_115200 },
4347 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4348 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 		pbn_b1_8_115200 },
4350 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4351 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4352 		pbn_b1_4_115200 },
4353 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4354 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 		pbn_b1_2_115200 },
4356 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4357 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 		pbn_b1_4_115200 },
4359 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4360 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361 		pbn_b1_2_115200 },
4362 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4363 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364 		pbn_b2_4_115200 },
4365 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4366 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 		pbn_b2_2_115200 },
4368 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4369 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 		pbn_b2_1_115200 },
4371 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4372 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373 		pbn_b2_4_115200 },
4374 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4375 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 		pbn_b2_2_115200 },
4377 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4378 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 		pbn_b2_1_115200 },
4380 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4381 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 		pbn_b0_8_115200 },
4383 
4384 	{	PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4385 		PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4386 		0, 0,
4387 		pbn_b0_4_921600 },
4388 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4389 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4390 		0, 0,
4391 		pbn_b0_4_1152000 },
4392 	{	PCI_VENDOR_ID_OXSEMI, 0x9505,
4393 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 		pbn_b0_bt_2_921600 },
4395 
4396 		/*
4397 		 * The below card is a little controversial since it is the
4398 		 * subject of a PCI vendor/device ID clash.  (See
4399 		 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4400 		 * For now just used the hex ID 0x950a.
4401 		 */
4402 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4403 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4404 		0, 0, pbn_b0_2_115200 },
4405 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4406 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4407 		0, 0, pbn_b0_2_115200 },
4408 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4409 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 		pbn_b0_2_1130000 },
4411 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4412 		PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4413 		pbn_b0_1_921600 },
4414 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4415 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 		pbn_b0_4_115200 },
4417 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4418 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 		pbn_b0_bt_2_921600 },
4420 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4421 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 		pbn_b2_8_1152000 },
4423 
4424 	/*
4425 	 * Oxford Semiconductor Inc. Tornado PCI express device range.
4426 	 */
4427 	{	PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4428 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 		pbn_b0_1_4000000 },
4430 	{	PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4431 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 		pbn_b0_1_4000000 },
4433 	{	PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4434 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 		pbn_oxsemi_1_4000000 },
4436 	{	PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4437 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 		pbn_oxsemi_1_4000000 },
4439 	{	PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4440 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 		pbn_b0_1_4000000 },
4442 	{	PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4443 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 		pbn_b0_1_4000000 },
4445 	{	PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4446 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 		pbn_oxsemi_1_4000000 },
4448 	{	PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4449 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4450 		pbn_oxsemi_1_4000000 },
4451 	{	PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4452 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4453 		pbn_b0_1_4000000 },
4454 	{	PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4455 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4456 		pbn_b0_1_4000000 },
4457 	{	PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4458 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4459 		pbn_b0_1_4000000 },
4460 	{	PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4461 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4462 		pbn_b0_1_4000000 },
4463 	{	PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4464 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4465 		pbn_oxsemi_2_4000000 },
4466 	{	PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4467 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4468 		pbn_oxsemi_2_4000000 },
4469 	{	PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4470 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 		pbn_oxsemi_4_4000000 },
4472 	{	PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4473 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 		pbn_oxsemi_4_4000000 },
4475 	{	PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4476 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 		pbn_oxsemi_8_4000000 },
4478 	{	PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4479 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 		pbn_oxsemi_8_4000000 },
4481 	{	PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4482 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 		pbn_oxsemi_1_4000000 },
4484 	{	PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4485 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 		pbn_oxsemi_1_4000000 },
4487 	{	PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4488 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 		pbn_oxsemi_1_4000000 },
4490 	{	PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4491 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 		pbn_oxsemi_1_4000000 },
4493 	{	PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4494 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4495 		pbn_oxsemi_1_4000000 },
4496 	{	PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4497 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4498 		pbn_oxsemi_1_4000000 },
4499 	{	PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4500 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4501 		pbn_oxsemi_1_4000000 },
4502 	{	PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4503 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4504 		pbn_oxsemi_1_4000000 },
4505 	{	PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4506 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 		pbn_oxsemi_1_4000000 },
4508 	{	PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4509 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 		pbn_oxsemi_1_4000000 },
4511 	{	PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4512 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 		pbn_oxsemi_1_4000000 },
4514 	{	PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4515 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 		pbn_oxsemi_1_4000000 },
4517 	{	PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4518 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 		pbn_oxsemi_1_4000000 },
4520 	{	PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4521 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 		pbn_oxsemi_1_4000000 },
4523 	{	PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4524 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 		pbn_oxsemi_1_4000000 },
4526 	{	PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4527 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 		pbn_oxsemi_1_4000000 },
4529 	{	PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4530 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 		pbn_oxsemi_1_4000000 },
4532 	{	PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4533 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 		pbn_oxsemi_1_4000000 },
4535 	{	PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4536 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 		pbn_oxsemi_1_4000000 },
4538 	{	PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4539 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 		pbn_oxsemi_1_4000000 },
4541 	{	PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4542 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4543 		pbn_oxsemi_1_4000000 },
4544 	{	PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4545 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4546 		pbn_oxsemi_1_4000000 },
4547 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4548 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 		pbn_oxsemi_1_4000000 },
4550 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4551 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 		pbn_oxsemi_1_4000000 },
4553 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4554 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 		pbn_oxsemi_1_4000000 },
4556 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4557 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 		pbn_oxsemi_1_4000000 },
4559 	/*
4560 	 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4561 	 */
4562 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 1 Port V.34 Super-G3 Fax */
4563 		PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4564 		pbn_oxsemi_1_4000000 },
4565 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 2 Port V.34 Super-G3 Fax */
4566 		PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4567 		pbn_oxsemi_2_4000000 },
4568 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 4 Port V.34 Super-G3 Fax */
4569 		PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4570 		pbn_oxsemi_4_4000000 },
4571 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 8 Port V.34 Super-G3 Fax */
4572 		PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4573 		pbn_oxsemi_8_4000000 },
4574 
4575 	/*
4576 	 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4577 	 */
4578 	{	PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4579 		PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4580 		pbn_oxsemi_2_4000000 },
4581 
4582 	/*
4583 	 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4584 	 * from skokodyn@yahoo.com
4585 	 */
4586 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4587 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4588 		pbn_sbsxrsio },
4589 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4590 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4591 		pbn_sbsxrsio },
4592 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4593 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4594 		pbn_sbsxrsio },
4595 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4596 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4597 		pbn_sbsxrsio },
4598 
4599 	/*
4600 	 * Digitan DS560-558, from jimd@esoft.com
4601 	 */
4602 	{	PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4603 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 		pbn_b1_1_115200 },
4605 
4606 	/*
4607 	 * Titan Electronic cards
4608 	 *  The 400L and 800L have a custom setup quirk.
4609 	 */
4610 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4611 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 		pbn_b0_1_921600 },
4613 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4614 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 		pbn_b0_2_921600 },
4616 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4617 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 		pbn_b0_4_921600 },
4619 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4620 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 		pbn_b0_4_921600 },
4622 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4623 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 		pbn_b1_1_921600 },
4625 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4626 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 		pbn_b1_bt_2_921600 },
4628 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4629 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 		pbn_b0_bt_4_921600 },
4631 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4632 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 		pbn_b0_bt_8_921600 },
4634 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4635 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 		pbn_b4_bt_2_921600 },
4637 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4638 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 		pbn_b4_bt_4_921600 },
4640 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4641 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 		pbn_b4_bt_8_921600 },
4643 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4644 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 		pbn_b0_4_921600 },
4646 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4647 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 		pbn_b0_4_921600 },
4649 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4650 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 		pbn_b0_4_921600 },
4652 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4653 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 		pbn_oxsemi_1_4000000 },
4655 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4656 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 		pbn_oxsemi_2_4000000 },
4658 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4659 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 		pbn_oxsemi_4_4000000 },
4661 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4662 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 		pbn_oxsemi_8_4000000 },
4664 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4665 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 		pbn_oxsemi_2_4000000 },
4667 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4668 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 		pbn_oxsemi_2_4000000 },
4670 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4671 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 		pbn_b0_bt_2_921600 },
4673 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4674 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 		pbn_b0_4_921600 },
4676 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4677 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 		pbn_b0_4_921600 },
4679 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4680 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 		pbn_b0_4_921600 },
4682 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4683 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 		pbn_b0_4_921600 },
4685 
4686 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4687 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4688 		pbn_b2_1_460800 },
4689 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4690 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 		pbn_b2_1_460800 },
4692 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4693 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 		pbn_b2_1_460800 },
4695 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4696 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 		pbn_b2_bt_2_921600 },
4698 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4699 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 		pbn_b2_bt_2_921600 },
4701 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4702 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 		pbn_b2_bt_2_921600 },
4704 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4705 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 		pbn_b2_bt_4_921600 },
4707 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4708 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 		pbn_b2_bt_4_921600 },
4710 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4711 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 		pbn_b2_bt_4_921600 },
4713 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4714 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 		pbn_b0_1_921600 },
4716 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4717 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 		pbn_b0_1_921600 },
4719 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4720 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 		pbn_b0_1_921600 },
4722 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4723 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 		pbn_b0_bt_2_921600 },
4725 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4726 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 		pbn_b0_bt_2_921600 },
4728 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4729 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 		pbn_b0_bt_2_921600 },
4731 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4732 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 		pbn_b0_bt_4_921600 },
4734 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4735 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 		pbn_b0_bt_4_921600 },
4737 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4738 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 		pbn_b0_bt_4_921600 },
4740 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4741 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 		pbn_b0_bt_8_921600 },
4743 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4744 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 		pbn_b0_bt_8_921600 },
4746 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4747 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 		pbn_b0_bt_8_921600 },
4749 
4750 	/*
4751 	 * Computone devices submitted by Doug McNash dmcnash@computone.com
4752 	 */
4753 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4754 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4755 		0, 0, pbn_computone_4 },
4756 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4757 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4758 		0, 0, pbn_computone_8 },
4759 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4760 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4761 		0, 0, pbn_computone_6 },
4762 
4763 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4764 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 		pbn_oxsemi },
4766 	{	PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4767 		PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4768 		pbn_b0_bt_1_921600 },
4769 
4770 	/*
4771 	 * SUNIX (TIMEDIA)
4772 	 */
4773 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4774 		PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4775 		PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4776 		pbn_b0_bt_1_921600 },
4777 
4778 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4779 		PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4780 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4781 		pbn_b0_bt_1_921600 },
4782 
4783 	/*
4784 	 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4785 	 */
4786 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4787 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 		pbn_b0_bt_8_115200 },
4789 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4790 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 		pbn_b0_bt_8_115200 },
4792 
4793 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4794 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 		pbn_b0_bt_2_115200 },
4796 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4797 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 		pbn_b0_bt_2_115200 },
4799 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4800 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 		pbn_b0_bt_2_115200 },
4802 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4803 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 		pbn_b0_bt_2_115200 },
4805 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4806 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 		pbn_b0_bt_2_115200 },
4808 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4809 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 		pbn_b0_bt_4_460800 },
4811 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4812 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 		pbn_b0_bt_4_460800 },
4814 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4815 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4816 		pbn_b0_bt_2_460800 },
4817 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4818 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 		pbn_b0_bt_2_460800 },
4820 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4821 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4822 		pbn_b0_bt_2_460800 },
4823 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4824 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4825 		pbn_b0_bt_1_115200 },
4826 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4827 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4828 		pbn_b0_bt_1_460800 },
4829 
4830 	/*
4831 	 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4832 	 * Cards are identified by their subsystem vendor IDs, which
4833 	 * (in hex) match the model number.
4834 	 *
4835 	 * Note that JC140x are RS422/485 cards which require ox950
4836 	 * ACR = 0x10, and as such are not currently fully supported.
4837 	 */
4838 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4839 		0x1204, 0x0004, 0, 0,
4840 		pbn_b0_4_921600 },
4841 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4842 		0x1208, 0x0004, 0, 0,
4843 		pbn_b0_4_921600 },
4844 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4845 		0x1402, 0x0002, 0, 0,
4846 		pbn_b0_2_921600 }, */
4847 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4848 		0x1404, 0x0004, 0, 0,
4849 		pbn_b0_4_921600 }, */
4850 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4851 		0x1208, 0x0004, 0, 0,
4852 		pbn_b0_4_921600 },
4853 
4854 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4855 		0x1204, 0x0004, 0, 0,
4856 		pbn_b0_4_921600 },
4857 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4858 		0x1208, 0x0004, 0, 0,
4859 		pbn_b0_4_921600 },
4860 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4861 		0x1208, 0x0004, 0, 0,
4862 		pbn_b0_4_921600 },
4863 	/*
4864 	 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4865 	 */
4866 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4867 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 		pbn_b1_1_1382400 },
4869 
4870 	/*
4871 	 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4872 	 */
4873 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4874 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4875 		pbn_b1_1_1382400 },
4876 
4877 	/*
4878 	 * RAStel 2 port modem, gerg@moreton.com.au
4879 	 */
4880 	{	PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4881 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 		pbn_b2_bt_2_115200 },
4883 
4884 	/*
4885 	 * EKF addition for i960 Boards form EKF with serial port
4886 	 */
4887 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4888 		0xE4BF, PCI_ANY_ID, 0, 0,
4889 		pbn_intel_i960 },
4890 
4891 	/*
4892 	 * Xircom Cardbus/Ethernet combos
4893 	 */
4894 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4895 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 		pbn_b0_1_115200 },
4897 	/*
4898 	 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4899 	 */
4900 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4901 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 		pbn_b0_1_115200 },
4903 
4904 	/*
4905 	 * Untested PCI modems, sent in from various folks...
4906 	 */
4907 
4908 	/*
4909 	 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4910 	 */
4911 	{	PCI_VENDOR_ID_ROCKWELL, 0x1004,
4912 		0x1048, 0x1500, 0, 0,
4913 		pbn_b1_1_115200 },
4914 
4915 	{	PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4916 		0xFF00, 0, 0, 0,
4917 		pbn_sgi_ioc3 },
4918 
4919 	/*
4920 	 * HP Diva card
4921 	 */
4922 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4923 		PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4924 		pbn_b1_1_115200 },
4925 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4926 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 		pbn_b0_5_115200 },
4928 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4929 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 		pbn_b2_1_115200 },
4931 
4932 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4933 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 		pbn_b3_2_115200 },
4935 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4936 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 		pbn_b3_4_115200 },
4938 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4939 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 		pbn_b3_8_115200 },
4941 
4942 	/*
4943 	 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4944 	 */
4945 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4946 		PCI_ANY_ID, PCI_ANY_ID,
4947 		0,
4948 		0, pbn_exar_XR17C152 },
4949 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4950 		PCI_ANY_ID, PCI_ANY_ID,
4951 		0,
4952 		0, pbn_exar_XR17C154 },
4953 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4954 		PCI_ANY_ID, PCI_ANY_ID,
4955 		0,
4956 		0, pbn_exar_XR17C158 },
4957 	/*
4958 	 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
4959 	 */
4960 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4961 		PCI_ANY_ID, PCI_ANY_ID,
4962 		0,
4963 		0, pbn_exar_XR17V352 },
4964 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4965 		PCI_ANY_ID, PCI_ANY_ID,
4966 		0,
4967 		0, pbn_exar_XR17V354 },
4968 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4969 		PCI_ANY_ID, PCI_ANY_ID,
4970 		0,
4971 		0, pbn_exar_XR17V358 },
4972 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
4973 		PCI_ANY_ID, PCI_ANY_ID,
4974 		0,
4975 		0, pbn_exar_XR17V4358 },
4976 	{	PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
4977 		PCI_ANY_ID, PCI_ANY_ID,
4978 		0,
4979 		0, pbn_exar_XR17V8358 },
4980 	/*
4981 	 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4982 	 */
4983 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4984 		PCI_ANY_ID, PCI_ANY_ID,
4985 		0,
4986 		0, pbn_pericom_PI7C9X7951 },
4987 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4988 		PCI_ANY_ID, PCI_ANY_ID,
4989 		0,
4990 		0, pbn_pericom_PI7C9X7952 },
4991 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4992 		PCI_ANY_ID, PCI_ANY_ID,
4993 		0,
4994 		0, pbn_pericom_PI7C9X7954 },
4995 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4996 		PCI_ANY_ID, PCI_ANY_ID,
4997 		0,
4998 		0, pbn_pericom_PI7C9X7958 },
4999 	/*
5000 	 * ACCES I/O Products quad
5001 	 */
5002 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5003 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 		pbn_pericom_PI7C9X7954 },
5005 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5006 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 		pbn_pericom_PI7C9X7954 },
5008 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5009 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 		pbn_pericom_PI7C9X7954 },
5011 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5012 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5013 		pbn_pericom_PI7C9X7954 },
5014 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5015 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5016 		pbn_pericom_PI7C9X7954 },
5017 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5018 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5019 		pbn_pericom_PI7C9X7954 },
5020 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5021 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5022 		pbn_pericom_PI7C9X7954 },
5023 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5024 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5025 		pbn_pericom_PI7C9X7954 },
5026 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5027 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5028 		pbn_pericom_PI7C9X7954 },
5029 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5030 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5031 		pbn_pericom_PI7C9X7954 },
5032 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5033 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5034 		pbn_pericom_PI7C9X7954 },
5035 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5036 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5037 		pbn_pericom_PI7C9X7954 },
5038 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5039 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5040 		pbn_pericom_PI7C9X7954 },
5041 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5042 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5043 		pbn_pericom_PI7C9X7954 },
5044 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5045 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5046 		pbn_pericom_PI7C9X7954 },
5047 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5048 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5049 		pbn_pericom_PI7C9X7954 },
5050 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5051 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5052 		pbn_pericom_PI7C9X7954 },
5053 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5054 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055 		pbn_pericom_PI7C9X7954 },
5056 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5057 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 		pbn_pericom_PI7C9X7954 },
5059 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5060 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5061 		pbn_pericom_PI7C9X7954 },
5062 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5063 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5064 		pbn_pericom_PI7C9X7954 },
5065 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5066 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5067 		pbn_pericom_PI7C9X7954 },
5068 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5069 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5070 		pbn_pericom_PI7C9X7954 },
5071 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5072 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5073 		pbn_pericom_PI7C9X7954 },
5074 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5075 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 		pbn_pericom_PI7C9X7958 },
5077 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5078 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 		pbn_pericom_PI7C9X7958 },
5080 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5081 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 		pbn_pericom_PI7C9X7958 },
5083 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5084 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 		pbn_pericom_PI7C9X7958 },
5086 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5087 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 		pbn_pericom_PI7C9X7958 },
5089 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5090 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 		pbn_pericom_PI7C9X7958 },
5092 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5093 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 		pbn_pericom_PI7C9X7958 },
5095 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5096 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 		pbn_pericom_PI7C9X7958 },
5098 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5099 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 		pbn_pericom_PI7C9X7958 },
5101 	/*
5102 	 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5103 	 */
5104 	{	PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5105 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 		pbn_b0_1_115200 },
5107 	/*
5108 	 * ITE
5109 	 */
5110 	{	PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5111 		PCI_ANY_ID, PCI_ANY_ID,
5112 		0, 0,
5113 		pbn_b1_bt_1_115200 },
5114 
5115 	/*
5116 	 * IntaShield IS-200
5117 	 */
5118 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5119 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,	/* 135a.0811 */
5120 		pbn_b2_2_115200 },
5121 	/*
5122 	 * IntaShield IS-400
5123 	 */
5124 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5125 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
5126 		pbn_b2_4_115200 },
5127 	/*
5128 	 * Perle PCI-RAS cards
5129 	 */
5130 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5131 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5132 		0, 0, pbn_b2_4_921600 },
5133 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5134 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5135 		0, 0, pbn_b2_8_921600 },
5136 
5137 	/*
5138 	 * Mainpine series cards: Fairly standard layout but fools
5139 	 * parts of the autodetect in some cases and uses otherwise
5140 	 * unmatched communications subclasses in the PCI Express case
5141 	 */
5142 
5143 	{	/* RockForceDUO */
5144 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5145 		PCI_VENDOR_ID_MAINPINE, 0x0200,
5146 		0, 0, pbn_b0_2_115200 },
5147 	{	/* RockForceQUATRO */
5148 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5149 		PCI_VENDOR_ID_MAINPINE, 0x0300,
5150 		0, 0, pbn_b0_4_115200 },
5151 	{	/* RockForceDUO+ */
5152 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5153 		PCI_VENDOR_ID_MAINPINE, 0x0400,
5154 		0, 0, pbn_b0_2_115200 },
5155 	{	/* RockForceQUATRO+ */
5156 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5157 		PCI_VENDOR_ID_MAINPINE, 0x0500,
5158 		0, 0, pbn_b0_4_115200 },
5159 	{	/* RockForce+ */
5160 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5161 		PCI_VENDOR_ID_MAINPINE, 0x0600,
5162 		0, 0, pbn_b0_2_115200 },
5163 	{	/* RockForce+ */
5164 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5165 		PCI_VENDOR_ID_MAINPINE, 0x0700,
5166 		0, 0, pbn_b0_4_115200 },
5167 	{	/* RockForceOCTO+ */
5168 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5169 		PCI_VENDOR_ID_MAINPINE, 0x0800,
5170 		0, 0, pbn_b0_8_115200 },
5171 	{	/* RockForceDUO+ */
5172 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5173 		PCI_VENDOR_ID_MAINPINE, 0x0C00,
5174 		0, 0, pbn_b0_2_115200 },
5175 	{	/* RockForceQUARTRO+ */
5176 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5177 		PCI_VENDOR_ID_MAINPINE, 0x0D00,
5178 		0, 0, pbn_b0_4_115200 },
5179 	{	/* RockForceOCTO+ */
5180 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5181 		PCI_VENDOR_ID_MAINPINE, 0x1D00,
5182 		0, 0, pbn_b0_8_115200 },
5183 	{	/* RockForceD1 */
5184 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5185 		PCI_VENDOR_ID_MAINPINE, 0x2000,
5186 		0, 0, pbn_b0_1_115200 },
5187 	{	/* RockForceF1 */
5188 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5189 		PCI_VENDOR_ID_MAINPINE, 0x2100,
5190 		0, 0, pbn_b0_1_115200 },
5191 	{	/* RockForceD2 */
5192 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5193 		PCI_VENDOR_ID_MAINPINE, 0x2200,
5194 		0, 0, pbn_b0_2_115200 },
5195 	{	/* RockForceF2 */
5196 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5197 		PCI_VENDOR_ID_MAINPINE, 0x2300,
5198 		0, 0, pbn_b0_2_115200 },
5199 	{	/* RockForceD4 */
5200 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5201 		PCI_VENDOR_ID_MAINPINE, 0x2400,
5202 		0, 0, pbn_b0_4_115200 },
5203 	{	/* RockForceF4 */
5204 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5205 		PCI_VENDOR_ID_MAINPINE, 0x2500,
5206 		0, 0, pbn_b0_4_115200 },
5207 	{	/* RockForceD8 */
5208 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5209 		PCI_VENDOR_ID_MAINPINE, 0x2600,
5210 		0, 0, pbn_b0_8_115200 },
5211 	{	/* RockForceF8 */
5212 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5213 		PCI_VENDOR_ID_MAINPINE, 0x2700,
5214 		0, 0, pbn_b0_8_115200 },
5215 	{	/* IQ Express D1 */
5216 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5217 		PCI_VENDOR_ID_MAINPINE, 0x3000,
5218 		0, 0, pbn_b0_1_115200 },
5219 	{	/* IQ Express F1 */
5220 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5221 		PCI_VENDOR_ID_MAINPINE, 0x3100,
5222 		0, 0, pbn_b0_1_115200 },
5223 	{	/* IQ Express D2 */
5224 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5225 		PCI_VENDOR_ID_MAINPINE, 0x3200,
5226 		0, 0, pbn_b0_2_115200 },
5227 	{	/* IQ Express F2 */
5228 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5229 		PCI_VENDOR_ID_MAINPINE, 0x3300,
5230 		0, 0, pbn_b0_2_115200 },
5231 	{	/* IQ Express D4 */
5232 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5233 		PCI_VENDOR_ID_MAINPINE, 0x3400,
5234 		0, 0, pbn_b0_4_115200 },
5235 	{	/* IQ Express F4 */
5236 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5237 		PCI_VENDOR_ID_MAINPINE, 0x3500,
5238 		0, 0, pbn_b0_4_115200 },
5239 	{	/* IQ Express D8 */
5240 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5241 		PCI_VENDOR_ID_MAINPINE, 0x3C00,
5242 		0, 0, pbn_b0_8_115200 },
5243 	{	/* IQ Express F8 */
5244 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5245 		PCI_VENDOR_ID_MAINPINE, 0x3D00,
5246 		0, 0, pbn_b0_8_115200 },
5247 
5248 
5249 	/*
5250 	 * PA Semi PA6T-1682M on-chip UART
5251 	 */
5252 	{	PCI_VENDOR_ID_PASEMI, 0xa004,
5253 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5254 		pbn_pasemi_1682M },
5255 
5256 	/*
5257 	 * National Instruments
5258 	 */
5259 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5260 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5261 		pbn_b1_16_115200 },
5262 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5263 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5264 		pbn_b1_8_115200 },
5265 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5266 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5267 		pbn_b1_bt_4_115200 },
5268 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5269 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5270 		pbn_b1_bt_2_115200 },
5271 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5272 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5273 		pbn_b1_bt_4_115200 },
5274 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5275 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5276 		pbn_b1_bt_2_115200 },
5277 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5278 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5279 		pbn_b1_16_115200 },
5280 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5281 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5282 		pbn_b1_8_115200 },
5283 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5284 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5285 		pbn_b1_bt_4_115200 },
5286 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5287 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5288 		pbn_b1_bt_2_115200 },
5289 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5290 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5291 		pbn_b1_bt_4_115200 },
5292 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5293 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5294 		pbn_b1_bt_2_115200 },
5295 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5296 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5297 		pbn_ni8430_2 },
5298 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5299 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5300 		pbn_ni8430_2 },
5301 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5302 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5303 		pbn_ni8430_4 },
5304 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5305 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5306 		pbn_ni8430_4 },
5307 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5308 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5309 		pbn_ni8430_8 },
5310 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5311 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5312 		pbn_ni8430_8 },
5313 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5314 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5315 		pbn_ni8430_16 },
5316 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5317 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5318 		pbn_ni8430_16 },
5319 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5320 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5321 		pbn_ni8430_2 },
5322 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5323 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5324 		pbn_ni8430_2 },
5325 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5326 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5327 		pbn_ni8430_4 },
5328 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5329 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5330 		pbn_ni8430_4 },
5331 
5332 	/*
5333 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
5334 	*/
5335 	{	PCI_VENDOR_ID_ADDIDATA,
5336 		PCI_DEVICE_ID_ADDIDATA_APCI7500,
5337 		PCI_ANY_ID,
5338 		PCI_ANY_ID,
5339 		0,
5340 		0,
5341 		pbn_b0_4_115200 },
5342 
5343 	{	PCI_VENDOR_ID_ADDIDATA,
5344 		PCI_DEVICE_ID_ADDIDATA_APCI7420,
5345 		PCI_ANY_ID,
5346 		PCI_ANY_ID,
5347 		0,
5348 		0,
5349 		pbn_b0_2_115200 },
5350 
5351 	{	PCI_VENDOR_ID_ADDIDATA,
5352 		PCI_DEVICE_ID_ADDIDATA_APCI7300,
5353 		PCI_ANY_ID,
5354 		PCI_ANY_ID,
5355 		0,
5356 		0,
5357 		pbn_b0_1_115200 },
5358 
5359 	{	PCI_VENDOR_ID_AMCC,
5360 		PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5361 		PCI_ANY_ID,
5362 		PCI_ANY_ID,
5363 		0,
5364 		0,
5365 		pbn_b1_8_115200 },
5366 
5367 	{	PCI_VENDOR_ID_ADDIDATA,
5368 		PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5369 		PCI_ANY_ID,
5370 		PCI_ANY_ID,
5371 		0,
5372 		0,
5373 		pbn_b0_4_115200 },
5374 
5375 	{	PCI_VENDOR_ID_ADDIDATA,
5376 		PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5377 		PCI_ANY_ID,
5378 		PCI_ANY_ID,
5379 		0,
5380 		0,
5381 		pbn_b0_2_115200 },
5382 
5383 	{	PCI_VENDOR_ID_ADDIDATA,
5384 		PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5385 		PCI_ANY_ID,
5386 		PCI_ANY_ID,
5387 		0,
5388 		0,
5389 		pbn_b0_1_115200 },
5390 
5391 	{	PCI_VENDOR_ID_ADDIDATA,
5392 		PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5393 		PCI_ANY_ID,
5394 		PCI_ANY_ID,
5395 		0,
5396 		0,
5397 		pbn_b0_4_115200 },
5398 
5399 	{	PCI_VENDOR_ID_ADDIDATA,
5400 		PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5401 		PCI_ANY_ID,
5402 		PCI_ANY_ID,
5403 		0,
5404 		0,
5405 		pbn_b0_2_115200 },
5406 
5407 	{	PCI_VENDOR_ID_ADDIDATA,
5408 		PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5409 		PCI_ANY_ID,
5410 		PCI_ANY_ID,
5411 		0,
5412 		0,
5413 		pbn_b0_1_115200 },
5414 
5415 	{	PCI_VENDOR_ID_ADDIDATA,
5416 		PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5417 		PCI_ANY_ID,
5418 		PCI_ANY_ID,
5419 		0,
5420 		0,
5421 		pbn_b0_8_115200 },
5422 
5423 	{	PCI_VENDOR_ID_ADDIDATA,
5424 		PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5425 		PCI_ANY_ID,
5426 		PCI_ANY_ID,
5427 		0,
5428 		0,
5429 		pbn_ADDIDATA_PCIe_4_3906250 },
5430 
5431 	{	PCI_VENDOR_ID_ADDIDATA,
5432 		PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5433 		PCI_ANY_ID,
5434 		PCI_ANY_ID,
5435 		0,
5436 		0,
5437 		pbn_ADDIDATA_PCIe_2_3906250 },
5438 
5439 	{	PCI_VENDOR_ID_ADDIDATA,
5440 		PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5441 		PCI_ANY_ID,
5442 		PCI_ANY_ID,
5443 		0,
5444 		0,
5445 		pbn_ADDIDATA_PCIe_1_3906250 },
5446 
5447 	{	PCI_VENDOR_ID_ADDIDATA,
5448 		PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5449 		PCI_ANY_ID,
5450 		PCI_ANY_ID,
5451 		0,
5452 		0,
5453 		pbn_ADDIDATA_PCIe_8_3906250 },
5454 
5455 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5456 		PCI_VENDOR_ID_IBM, 0x0299,
5457 		0, 0, pbn_b0_bt_2_115200 },
5458 
5459 	/*
5460 	 * other NetMos 9835 devices are most likely handled by the
5461 	 * parport_serial driver, check drivers/parport/parport_serial.c
5462 	 * before adding them here.
5463 	 */
5464 
5465 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5466 		0xA000, 0x1000,
5467 		0, 0, pbn_b0_1_115200 },
5468 
5469 	/* the 9901 is a rebranded 9912 */
5470 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5471 		0xA000, 0x1000,
5472 		0, 0, pbn_b0_1_115200 },
5473 
5474 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5475 		0xA000, 0x1000,
5476 		0, 0, pbn_b0_1_115200 },
5477 
5478 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5479 		0xA000, 0x1000,
5480 		0, 0, pbn_b0_1_115200 },
5481 
5482 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5483 		0xA000, 0x1000,
5484 		0, 0, pbn_b0_1_115200 },
5485 
5486 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5487 		0xA000, 0x3002,
5488 		0, 0, pbn_NETMOS9900_2s_115200 },
5489 
5490 	/*
5491 	 * Best Connectivity and Rosewill PCI Multi I/O cards
5492 	 */
5493 
5494 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5495 		0xA000, 0x1000,
5496 		0, 0, pbn_b0_1_115200 },
5497 
5498 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5499 		0xA000, 0x3002,
5500 		0, 0, pbn_b0_bt_2_115200 },
5501 
5502 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5503 		0xA000, 0x3004,
5504 		0, 0, pbn_b0_bt_4_115200 },
5505 	/* Intel CE4100 */
5506 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5507 		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5508 		pbn_ce4100_1_115200 },
5509 
5510 	/*
5511 	 * Cronyx Omega PCI
5512 	 */
5513 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5514 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5515 		pbn_omegapci },
5516 
5517 	/*
5518 	 * Broadcom TruManage
5519 	 */
5520 	{	PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5521 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5522 		pbn_brcm_trumanage },
5523 
5524 	/*
5525 	 * AgeStar as-prs2-009
5526 	 */
5527 	{	PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5528 		PCI_ANY_ID, PCI_ANY_ID,
5529 		0, 0, pbn_b0_bt_2_115200 },
5530 
5531 	/*
5532 	 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5533 	 * so not listed here.
5534 	 */
5535 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5536 		PCI_ANY_ID, PCI_ANY_ID,
5537 		0, 0, pbn_b0_bt_4_115200 },
5538 
5539 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5540 		PCI_ANY_ID, PCI_ANY_ID,
5541 		0, 0, pbn_b0_bt_2_115200 },
5542 
5543 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5544 		PCI_ANY_ID, PCI_ANY_ID,
5545 		0, 0, pbn_b0_bt_4_115200 },
5546 
5547 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5548 		PCI_ANY_ID, PCI_ANY_ID,
5549 		0, 0, pbn_wch382_2 },
5550 
5551 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5552 		PCI_ANY_ID, PCI_ANY_ID,
5553 		0, 0, pbn_wch384_4 },
5554 
5555 	/*
5556 	 * Commtech, Inc. Fastcom adapters
5557 	 */
5558 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5559 		PCI_ANY_ID, PCI_ANY_ID,
5560 		0,
5561 		0, pbn_b0_2_1152000_200 },
5562 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5563 		PCI_ANY_ID, PCI_ANY_ID,
5564 		0,
5565 		0, pbn_b0_4_1152000_200 },
5566 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5567 		PCI_ANY_ID, PCI_ANY_ID,
5568 		0,
5569 		0, pbn_b0_4_1152000_200 },
5570 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5571 		PCI_ANY_ID, PCI_ANY_ID,
5572 		0,
5573 		0, pbn_b0_8_1152000_200 },
5574 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5575 		PCI_ANY_ID, PCI_ANY_ID,
5576 		0,
5577 		0, pbn_exar_XR17V352 },
5578 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5579 		PCI_ANY_ID, PCI_ANY_ID,
5580 		0,
5581 		0, pbn_exar_XR17V354 },
5582 	{	PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5583 		PCI_ANY_ID, PCI_ANY_ID,
5584 		0,
5585 		0, pbn_exar_XR17V358 },
5586 
5587 	/* Fintek PCI serial cards */
5588 	{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5589 	{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5590 	{ PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5591 
5592 	/*
5593 	 * These entries match devices with class COMMUNICATION_SERIAL,
5594 	 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5595 	 */
5596 	{	PCI_ANY_ID, PCI_ANY_ID,
5597 		PCI_ANY_ID, PCI_ANY_ID,
5598 		PCI_CLASS_COMMUNICATION_SERIAL << 8,
5599 		0xffff00, pbn_default },
5600 	{	PCI_ANY_ID, PCI_ANY_ID,
5601 		PCI_ANY_ID, PCI_ANY_ID,
5602 		PCI_CLASS_COMMUNICATION_MODEM << 8,
5603 		0xffff00, pbn_default },
5604 	{	PCI_ANY_ID, PCI_ANY_ID,
5605 		PCI_ANY_ID, PCI_ANY_ID,
5606 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5607 		0xffff00, pbn_default },
5608 	{ 0, }
5609 };
5610 
5611 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5612 						pci_channel_state_t state)
5613 {
5614 	struct serial_private *priv = pci_get_drvdata(dev);
5615 
5616 	if (state == pci_channel_io_perm_failure)
5617 		return PCI_ERS_RESULT_DISCONNECT;
5618 
5619 	if (priv)
5620 		pciserial_detach_ports(priv);
5621 
5622 	pci_disable_device(dev);
5623 
5624 	return PCI_ERS_RESULT_NEED_RESET;
5625 }
5626 
5627 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5628 {
5629 	int rc;
5630 
5631 	rc = pci_enable_device(dev);
5632 
5633 	if (rc)
5634 		return PCI_ERS_RESULT_DISCONNECT;
5635 
5636 	pci_restore_state(dev);
5637 	pci_save_state(dev);
5638 
5639 	return PCI_ERS_RESULT_RECOVERED;
5640 }
5641 
5642 static void serial8250_io_resume(struct pci_dev *dev)
5643 {
5644 	struct serial_private *priv = pci_get_drvdata(dev);
5645 	struct serial_private *new;
5646 
5647 	if (!priv)
5648 		return;
5649 
5650 	new = pciserial_init_ports(dev, priv->board);
5651 	if (!IS_ERR(new)) {
5652 		pci_set_drvdata(dev, new);
5653 		kfree(priv);
5654 	}
5655 }
5656 
5657 static const struct pci_error_handlers serial8250_err_handler = {
5658 	.error_detected = serial8250_io_error_detected,
5659 	.slot_reset = serial8250_io_slot_reset,
5660 	.resume = serial8250_io_resume,
5661 };
5662 
5663 static struct pci_driver serial_pci_driver = {
5664 	.name		= "serial",
5665 	.probe		= pciserial_init_one,
5666 	.remove		= pciserial_remove_one,
5667 	.driver         = {
5668 		.pm     = &pciserial_pm_ops,
5669 	},
5670 	.id_table	= serial_pci_tbl,
5671 	.err_handler	= &serial8250_err_handler,
5672 };
5673 
5674 module_pci_driver(serial_pci_driver);
5675 
5676 MODULE_LICENSE("GPL");
5677 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5678 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5679