1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include "8250.h" 29 30 /* 31 * init function returns: 32 * > 0 - number of ports 33 * = 0 - use board->num_ports 34 * < 0 - error 35 */ 36 struct pci_serial_quirk { 37 u32 vendor; 38 u32 device; 39 u32 subvendor; 40 u32 subdevice; 41 int (*probe)(struct pci_dev *dev); 42 int (*init)(struct pci_dev *dev); 43 int (*setup)(struct serial_private *, 44 const struct pciserial_board *, 45 struct uart_8250_port *, int); 46 void (*exit)(struct pci_dev *dev); 47 }; 48 49 #define PCI_NUM_BAR_RESOURCES 6 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 int line[0]; 56 }; 57 58 static int pci_default_setup(struct serial_private*, 59 const struct pciserial_board*, struct uart_8250_port *, int); 60 61 static void moan_device(const char *str, struct pci_dev *dev) 62 { 63 dev_err(&dev->dev, 64 "%s: %s\n" 65 "Please send the output of lspci -vv, this\n" 66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 67 "manufacturer and name of serial board or\n" 68 "modem board to <linux-serial@vger.kernel.org>.\n", 69 pci_name(dev), str, dev->vendor, dev->device, 70 dev->subsystem_vendor, dev->subsystem_device); 71 } 72 73 static int 74 setup_port(struct serial_private *priv, struct uart_8250_port *port, 75 int bar, int offset, int regshift) 76 { 77 struct pci_dev *dev = priv->dev; 78 79 if (bar >= PCI_NUM_BAR_RESOURCES) 80 return -EINVAL; 81 82 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 83 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 84 return -ENOMEM; 85 86 port->port.iotype = UPIO_MEM; 87 port->port.iobase = 0; 88 port->port.mapbase = pci_resource_start(dev, bar) + offset; 89 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 90 port->port.regshift = regshift; 91 } else { 92 port->port.iotype = UPIO_PORT; 93 port->port.iobase = pci_resource_start(dev, bar) + offset; 94 port->port.mapbase = 0; 95 port->port.membase = NULL; 96 port->port.regshift = 0; 97 } 98 return 0; 99 } 100 101 /* 102 * ADDI-DATA GmbH communication cards <info@addi-data.com> 103 */ 104 static int addidata_apci7800_setup(struct serial_private *priv, 105 const struct pciserial_board *board, 106 struct uart_8250_port *port, int idx) 107 { 108 unsigned int bar = 0, offset = board->first_offset; 109 bar = FL_GET_BASE(board->flags); 110 111 if (idx < 2) { 112 offset += idx * board->uart_offset; 113 } else if ((idx >= 2) && (idx < 4)) { 114 bar += 1; 115 offset += ((idx - 2) * board->uart_offset); 116 } else if ((idx >= 4) && (idx < 6)) { 117 bar += 2; 118 offset += ((idx - 4) * board->uart_offset); 119 } else if (idx >= 6) { 120 bar += 3; 121 offset += ((idx - 6) * board->uart_offset); 122 } 123 124 return setup_port(priv, port, bar, offset, board->reg_shift); 125 } 126 127 /* 128 * AFAVLAB uses a different mixture of BARs and offsets 129 * Not that ugly ;) -- HW 130 */ 131 static int 132 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 133 struct uart_8250_port *port, int idx) 134 { 135 unsigned int bar, offset = board->first_offset; 136 137 bar = FL_GET_BASE(board->flags); 138 if (idx < 4) 139 bar += idx; 140 else { 141 bar = 4; 142 offset += (idx - 4) * board->uart_offset; 143 } 144 145 return setup_port(priv, port, bar, offset, board->reg_shift); 146 } 147 148 /* 149 * HP's Remote Management Console. The Diva chip came in several 150 * different versions. N-class, L2000 and A500 have two Diva chips, each 151 * with 3 UARTs (the third UART on the second chip is unused). Superdome 152 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 153 * one Diva chip, but it has been expanded to 5 UARTs. 154 */ 155 static int pci_hp_diva_init(struct pci_dev *dev) 156 { 157 int rc = 0; 158 159 switch (dev->subsystem_device) { 160 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 161 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 162 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 163 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 164 rc = 3; 165 break; 166 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 167 rc = 2; 168 break; 169 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 170 rc = 4; 171 break; 172 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 173 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 174 rc = 1; 175 break; 176 } 177 178 return rc; 179 } 180 181 /* 182 * HP's Diva chip puts the 4th/5th serial port further out, and 183 * some serial ports are supposed to be hidden on certain models. 184 */ 185 static int 186 pci_hp_diva_setup(struct serial_private *priv, 187 const struct pciserial_board *board, 188 struct uart_8250_port *port, int idx) 189 { 190 unsigned int offset = board->first_offset; 191 unsigned int bar = FL_GET_BASE(board->flags); 192 193 switch (priv->dev->subsystem_device) { 194 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 195 if (idx == 3) 196 idx++; 197 break; 198 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 199 if (idx > 0) 200 idx++; 201 if (idx > 2) 202 idx++; 203 break; 204 } 205 if (idx > 2) 206 offset = 0x18; 207 208 offset += idx * board->uart_offset; 209 210 return setup_port(priv, port, bar, offset, board->reg_shift); 211 } 212 213 /* 214 * Added for EKF Intel i960 serial boards 215 */ 216 static int pci_inteli960ni_init(struct pci_dev *dev) 217 { 218 u32 oldval; 219 220 if (!(dev->subsystem_device & 0x1000)) 221 return -ENODEV; 222 223 /* is firmware started? */ 224 pci_read_config_dword(dev, 0x44, &oldval); 225 if (oldval == 0x00001000L) { /* RESET value */ 226 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 227 return -ENODEV; 228 } 229 return 0; 230 } 231 232 /* 233 * Some PCI serial cards using the PLX 9050 PCI interface chip require 234 * that the card interrupt be explicitly enabled or disabled. This 235 * seems to be mainly needed on card using the PLX which also use I/O 236 * mapped memory. 237 */ 238 static int pci_plx9050_init(struct pci_dev *dev) 239 { 240 u8 irq_config; 241 void __iomem *p; 242 243 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 244 moan_device("no memory in bar 0", dev); 245 return 0; 246 } 247 248 irq_config = 0x41; 249 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 250 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 251 irq_config = 0x43; 252 253 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 254 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 255 /* 256 * As the megawolf cards have the int pins active 257 * high, and have 2 UART chips, both ints must be 258 * enabled on the 9050. Also, the UARTS are set in 259 * 16450 mode by default, so we have to enable the 260 * 16C950 'enhanced' mode so that we can use the 261 * deep FIFOs 262 */ 263 irq_config = 0x5b; 264 /* 265 * enable/disable interrupts 266 */ 267 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 268 if (p == NULL) 269 return -ENOMEM; 270 writel(irq_config, p + 0x4c); 271 272 /* 273 * Read the register back to ensure that it took effect. 274 */ 275 readl(p + 0x4c); 276 iounmap(p); 277 278 return 0; 279 } 280 281 static void pci_plx9050_exit(struct pci_dev *dev) 282 { 283 u8 __iomem *p; 284 285 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 286 return; 287 288 /* 289 * disable interrupts 290 */ 291 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 292 if (p != NULL) { 293 writel(0, p + 0x4c); 294 295 /* 296 * Read the register back to ensure that it took effect. 297 */ 298 readl(p + 0x4c); 299 iounmap(p); 300 } 301 } 302 303 #define NI8420_INT_ENABLE_REG 0x38 304 #define NI8420_INT_ENABLE_BIT 0x2000 305 306 static void pci_ni8420_exit(struct pci_dev *dev) 307 { 308 void __iomem *p; 309 unsigned int bar = 0; 310 311 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 312 moan_device("no memory in bar", dev); 313 return; 314 } 315 316 p = pci_ioremap_bar(dev, bar); 317 if (p == NULL) 318 return; 319 320 /* Disable the CPU Interrupt */ 321 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 322 p + NI8420_INT_ENABLE_REG); 323 iounmap(p); 324 } 325 326 327 /* MITE registers */ 328 #define MITE_IOWBSR1 0xc4 329 #define MITE_IOWCR1 0xf4 330 #define MITE_LCIMR1 0x08 331 #define MITE_LCIMR2 0x10 332 333 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 334 335 static void pci_ni8430_exit(struct pci_dev *dev) 336 { 337 void __iomem *p; 338 unsigned int bar = 0; 339 340 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 341 moan_device("no memory in bar", dev); 342 return; 343 } 344 345 p = pci_ioremap_bar(dev, bar); 346 if (p == NULL) 347 return; 348 349 /* Disable the CPU Interrupt */ 350 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 351 iounmap(p); 352 } 353 354 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 355 static int 356 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 357 struct uart_8250_port *port, int idx) 358 { 359 unsigned int bar, offset = board->first_offset; 360 361 bar = 0; 362 363 if (idx < 4) { 364 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 365 offset += idx * board->uart_offset; 366 } else if (idx < 8) { 367 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 368 offset += idx * board->uart_offset + 0xC00; 369 } else /* we have only 8 ports on PMC-OCTALPRO */ 370 return 1; 371 372 return setup_port(priv, port, bar, offset, board->reg_shift); 373 } 374 375 /* 376 * This does initialization for PMC OCTALPRO cards: 377 * maps the device memory, resets the UARTs (needed, bc 378 * if the module is removed and inserted again, the card 379 * is in the sleep mode) and enables global interrupt. 380 */ 381 382 /* global control register offset for SBS PMC-OctalPro */ 383 #define OCT_REG_CR_OFF 0x500 384 385 static int sbs_init(struct pci_dev *dev) 386 { 387 u8 __iomem *p; 388 389 p = pci_ioremap_bar(dev, 0); 390 391 if (p == NULL) 392 return -ENOMEM; 393 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 394 writeb(0x10, p + OCT_REG_CR_OFF); 395 udelay(50); 396 writeb(0x0, p + OCT_REG_CR_OFF); 397 398 /* Set bit-2 (INTENABLE) of Control Register */ 399 writeb(0x4, p + OCT_REG_CR_OFF); 400 iounmap(p); 401 402 return 0; 403 } 404 405 /* 406 * Disables the global interrupt of PMC-OctalPro 407 */ 408 409 static void sbs_exit(struct pci_dev *dev) 410 { 411 u8 __iomem *p; 412 413 p = pci_ioremap_bar(dev, 0); 414 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 415 if (p != NULL) 416 writeb(0, p + OCT_REG_CR_OFF); 417 iounmap(p); 418 } 419 420 /* 421 * SIIG serial cards have an PCI interface chip which also controls 422 * the UART clocking frequency. Each UART can be clocked independently 423 * (except cards equipped with 4 UARTs) and initial clocking settings 424 * are stored in the EEPROM chip. It can cause problems because this 425 * version of serial driver doesn't support differently clocked UART's 426 * on single PCI card. To prevent this, initialization functions set 427 * high frequency clocking for all UART's on given card. It is safe (I 428 * hope) because it doesn't touch EEPROM settings to prevent conflicts 429 * with other OSes (like M$ DOS). 430 * 431 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 432 * 433 * There is two family of SIIG serial cards with different PCI 434 * interface chip and different configuration methods: 435 * - 10x cards have control registers in IO and/or memory space; 436 * - 20x cards have control registers in standard PCI configuration space. 437 * 438 * Note: all 10x cards have PCI device ids 0x10.. 439 * all 20x cards have PCI device ids 0x20.. 440 * 441 * There are also Quartet Serial cards which use Oxford Semiconductor 442 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 443 * 444 * Note: some SIIG cards are probed by the parport_serial object. 445 */ 446 447 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 448 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 449 450 static int pci_siig10x_init(struct pci_dev *dev) 451 { 452 u16 data; 453 void __iomem *p; 454 455 switch (dev->device & 0xfff8) { 456 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 457 data = 0xffdf; 458 break; 459 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 460 data = 0xf7ff; 461 break; 462 default: /* 1S1P, 4S */ 463 data = 0xfffb; 464 break; 465 } 466 467 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 468 if (p == NULL) 469 return -ENOMEM; 470 471 writew(readw(p + 0x28) & data, p + 0x28); 472 readw(p + 0x28); 473 iounmap(p); 474 return 0; 475 } 476 477 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 478 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 479 480 static int pci_siig20x_init(struct pci_dev *dev) 481 { 482 u8 data; 483 484 /* Change clock frequency for the first UART. */ 485 pci_read_config_byte(dev, 0x6f, &data); 486 pci_write_config_byte(dev, 0x6f, data & 0xef); 487 488 /* If this card has 2 UART, we have to do the same with second UART. */ 489 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 490 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 491 pci_read_config_byte(dev, 0x73, &data); 492 pci_write_config_byte(dev, 0x73, data & 0xef); 493 } 494 return 0; 495 } 496 497 static int pci_siig_init(struct pci_dev *dev) 498 { 499 unsigned int type = dev->device & 0xff00; 500 501 if (type == 0x1000) 502 return pci_siig10x_init(dev); 503 else if (type == 0x2000) 504 return pci_siig20x_init(dev); 505 506 moan_device("Unknown SIIG card", dev); 507 return -ENODEV; 508 } 509 510 static int pci_siig_setup(struct serial_private *priv, 511 const struct pciserial_board *board, 512 struct uart_8250_port *port, int idx) 513 { 514 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 515 516 if (idx > 3) { 517 bar = 4; 518 offset = (idx - 4) * 8; 519 } 520 521 return setup_port(priv, port, bar, offset, 0); 522 } 523 524 /* 525 * Timedia has an explosion of boards, and to avoid the PCI table from 526 * growing *huge*, we use this function to collapse some 70 entries 527 * in the PCI table into one, for sanity's and compactness's sake. 528 */ 529 static const unsigned short timedia_single_port[] = { 530 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 531 }; 532 533 static const unsigned short timedia_dual_port[] = { 534 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 535 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 536 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 537 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 538 0xD079, 0 539 }; 540 541 static const unsigned short timedia_quad_port[] = { 542 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 543 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 544 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 545 0xB157, 0 546 }; 547 548 static const unsigned short timedia_eight_port[] = { 549 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 550 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 551 }; 552 553 static const struct timedia_struct { 554 int num; 555 const unsigned short *ids; 556 } timedia_data[] = { 557 { 1, timedia_single_port }, 558 { 2, timedia_dual_port }, 559 { 4, timedia_quad_port }, 560 { 8, timedia_eight_port } 561 }; 562 563 /* 564 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 565 * listing them individually, this driver merely grabs them all with 566 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 567 * and should be left free to be claimed by parport_serial instead. 568 */ 569 static int pci_timedia_probe(struct pci_dev *dev) 570 { 571 /* 572 * Check the third digit of the subdevice ID 573 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 574 */ 575 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 576 dev_info(&dev->dev, 577 "ignoring Timedia subdevice %04x for parport_serial\n", 578 dev->subsystem_device); 579 return -ENODEV; 580 } 581 582 return 0; 583 } 584 585 static int pci_timedia_init(struct pci_dev *dev) 586 { 587 const unsigned short *ids; 588 int i, j; 589 590 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 591 ids = timedia_data[i].ids; 592 for (j = 0; ids[j]; j++) 593 if (dev->subsystem_device == ids[j]) 594 return timedia_data[i].num; 595 } 596 return 0; 597 } 598 599 /* 600 * Timedia/SUNIX uses a mixture of BARs and offsets 601 * Ugh, this is ugly as all hell --- TYT 602 */ 603 static int 604 pci_timedia_setup(struct serial_private *priv, 605 const struct pciserial_board *board, 606 struct uart_8250_port *port, int idx) 607 { 608 unsigned int bar = 0, offset = board->first_offset; 609 610 switch (idx) { 611 case 0: 612 bar = 0; 613 break; 614 case 1: 615 offset = board->uart_offset; 616 bar = 0; 617 break; 618 case 2: 619 bar = 1; 620 break; 621 case 3: 622 offset = board->uart_offset; 623 /* FALLTHROUGH */ 624 case 4: /* BAR 2 */ 625 case 5: /* BAR 3 */ 626 case 6: /* BAR 4 */ 627 case 7: /* BAR 5 */ 628 bar = idx - 2; 629 } 630 631 return setup_port(priv, port, bar, offset, board->reg_shift); 632 } 633 634 /* 635 * Some Titan cards are also a little weird 636 */ 637 static int 638 titan_400l_800l_setup(struct serial_private *priv, 639 const struct pciserial_board *board, 640 struct uart_8250_port *port, int idx) 641 { 642 unsigned int bar, offset = board->first_offset; 643 644 switch (idx) { 645 case 0: 646 bar = 1; 647 break; 648 case 1: 649 bar = 2; 650 break; 651 default: 652 bar = 4; 653 offset = (idx - 2) * board->uart_offset; 654 } 655 656 return setup_port(priv, port, bar, offset, board->reg_shift); 657 } 658 659 static int pci_xircom_init(struct pci_dev *dev) 660 { 661 msleep(100); 662 return 0; 663 } 664 665 static int pci_ni8420_init(struct pci_dev *dev) 666 { 667 void __iomem *p; 668 unsigned int bar = 0; 669 670 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 671 moan_device("no memory in bar", dev); 672 return 0; 673 } 674 675 p = pci_ioremap_bar(dev, bar); 676 if (p == NULL) 677 return -ENOMEM; 678 679 /* Enable CPU Interrupt */ 680 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 681 p + NI8420_INT_ENABLE_REG); 682 683 iounmap(p); 684 return 0; 685 } 686 687 #define MITE_IOWBSR1_WSIZE 0xa 688 #define MITE_IOWBSR1_WIN_OFFSET 0x800 689 #define MITE_IOWBSR1_WENAB (1 << 7) 690 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 691 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 692 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 693 694 static int pci_ni8430_init(struct pci_dev *dev) 695 { 696 void __iomem *p; 697 struct pci_bus_region region; 698 u32 device_window; 699 unsigned int bar = 0; 700 701 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 702 moan_device("no memory in bar", dev); 703 return 0; 704 } 705 706 p = pci_ioremap_bar(dev, bar); 707 if (p == NULL) 708 return -ENOMEM; 709 710 /* 711 * Set device window address and size in BAR0, while acknowledging that 712 * the resource structure may contain a translated address that differs 713 * from the address the device responds to. 714 */ 715 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 716 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 717 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 718 writel(device_window, p + MITE_IOWBSR1); 719 720 /* Set window access to go to RAMSEL IO address space */ 721 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 722 p + MITE_IOWCR1); 723 724 /* Enable IO Bus Interrupt 0 */ 725 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 726 727 /* Enable CPU Interrupt */ 728 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 729 730 iounmap(p); 731 return 0; 732 } 733 734 /* UART Port Control Register */ 735 #define NI8430_PORTCON 0x0f 736 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 737 738 static int 739 pci_ni8430_setup(struct serial_private *priv, 740 const struct pciserial_board *board, 741 struct uart_8250_port *port, int idx) 742 { 743 struct pci_dev *dev = priv->dev; 744 void __iomem *p; 745 unsigned int bar, offset = board->first_offset; 746 747 if (idx >= board->num_ports) 748 return 1; 749 750 bar = FL_GET_BASE(board->flags); 751 offset += idx * board->uart_offset; 752 753 p = pci_ioremap_bar(dev, bar); 754 if (!p) 755 return -ENOMEM; 756 757 /* enable the transceiver */ 758 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 759 p + offset + NI8430_PORTCON); 760 761 iounmap(p); 762 763 return setup_port(priv, port, bar, offset, board->reg_shift); 764 } 765 766 static int pci_netmos_9900_setup(struct serial_private *priv, 767 const struct pciserial_board *board, 768 struct uart_8250_port *port, int idx) 769 { 770 unsigned int bar; 771 772 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 773 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 774 /* netmos apparently orders BARs by datasheet layout, so serial 775 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 776 */ 777 bar = 3 * idx; 778 779 return setup_port(priv, port, bar, 0, board->reg_shift); 780 } else { 781 return pci_default_setup(priv, board, port, idx); 782 } 783 } 784 785 /* the 99xx series comes with a range of device IDs and a variety 786 * of capabilities: 787 * 788 * 9900 has varying capabilities and can cascade to sub-controllers 789 * (cascading should be purely internal) 790 * 9904 is hardwired with 4 serial ports 791 * 9912 and 9922 are hardwired with 2 serial ports 792 */ 793 static int pci_netmos_9900_numports(struct pci_dev *dev) 794 { 795 unsigned int c = dev->class; 796 unsigned int pi; 797 unsigned short sub_serports; 798 799 pi = c & 0xff; 800 801 if (pi == 2) 802 return 1; 803 804 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 805 /* two possibilities: 0x30ps encodes number of parallel and 806 * serial ports, or 0x1000 indicates *something*. This is not 807 * immediately obvious, since the 2s1p+4s configuration seems 808 * to offer all functionality on functions 0..2, while still 809 * advertising the same function 3 as the 4s+2s1p config. 810 */ 811 sub_serports = dev->subsystem_device & 0xf; 812 if (sub_serports > 0) 813 return sub_serports; 814 815 dev_err(&dev->dev, 816 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 817 return 0; 818 } 819 820 moan_device("unknown NetMos/Mostech program interface", dev); 821 return 0; 822 } 823 824 static int pci_netmos_init(struct pci_dev *dev) 825 { 826 /* subdevice 0x00PS means <P> parallel, <S> serial */ 827 unsigned int num_serial = dev->subsystem_device & 0xf; 828 829 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 830 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 831 return 0; 832 833 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 834 dev->subsystem_device == 0x0299) 835 return 0; 836 837 switch (dev->device) { /* FALLTHROUGH on all */ 838 case PCI_DEVICE_ID_NETMOS_9904: 839 case PCI_DEVICE_ID_NETMOS_9912: 840 case PCI_DEVICE_ID_NETMOS_9922: 841 case PCI_DEVICE_ID_NETMOS_9900: 842 num_serial = pci_netmos_9900_numports(dev); 843 break; 844 845 default: 846 break; 847 } 848 849 if (num_serial == 0) { 850 moan_device("unknown NetMos/Mostech device", dev); 851 return -ENODEV; 852 } 853 854 return num_serial; 855 } 856 857 /* 858 * These chips are available with optionally one parallel port and up to 859 * two serial ports. Unfortunately they all have the same product id. 860 * 861 * Basic configuration is done over a region of 32 I/O ports. The base 862 * ioport is called INTA or INTC, depending on docs/other drivers. 863 * 864 * The region of the 32 I/O ports is configured in POSIO0R... 865 */ 866 867 /* registers */ 868 #define ITE_887x_MISCR 0x9c 869 #define ITE_887x_INTCBAR 0x78 870 #define ITE_887x_UARTBAR 0x7c 871 #define ITE_887x_PS0BAR 0x10 872 #define ITE_887x_POSIO0 0x60 873 874 /* I/O space size */ 875 #define ITE_887x_IOSIZE 32 876 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 877 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 878 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 879 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 880 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 881 #define ITE_887x_POSIO_SPEED (3 << 29) 882 /* enable IO_Space bit */ 883 #define ITE_887x_POSIO_ENABLE (1 << 31) 884 885 static int pci_ite887x_init(struct pci_dev *dev) 886 { 887 /* inta_addr are the configuration addresses of the ITE */ 888 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 889 0x200, 0x280, 0 }; 890 int ret, i, type; 891 struct resource *iobase = NULL; 892 u32 miscr, uartbar, ioport; 893 894 /* search for the base-ioport */ 895 i = 0; 896 while (inta_addr[i] && iobase == NULL) { 897 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 898 "ite887x"); 899 if (iobase != NULL) { 900 /* write POSIO0R - speed | size | ioport */ 901 pci_write_config_dword(dev, ITE_887x_POSIO0, 902 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 903 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 904 /* write INTCBAR - ioport */ 905 pci_write_config_dword(dev, ITE_887x_INTCBAR, 906 inta_addr[i]); 907 ret = inb(inta_addr[i]); 908 if (ret != 0xff) { 909 /* ioport connected */ 910 break; 911 } 912 release_region(iobase->start, ITE_887x_IOSIZE); 913 iobase = NULL; 914 } 915 i++; 916 } 917 918 if (!inta_addr[i]) { 919 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 920 return -ENODEV; 921 } 922 923 /* start of undocumented type checking (see parport_pc.c) */ 924 type = inb(iobase->start + 0x18) & 0x0f; 925 926 switch (type) { 927 case 0x2: /* ITE8871 (1P) */ 928 case 0xa: /* ITE8875 (1P) */ 929 ret = 0; 930 break; 931 case 0xe: /* ITE8872 (2S1P) */ 932 ret = 2; 933 break; 934 case 0x6: /* ITE8873 (1S) */ 935 ret = 1; 936 break; 937 case 0x8: /* ITE8874 (2S) */ 938 ret = 2; 939 break; 940 default: 941 moan_device("Unknown ITE887x", dev); 942 ret = -ENODEV; 943 } 944 945 /* configure all serial ports */ 946 for (i = 0; i < ret; i++) { 947 /* read the I/O port from the device */ 948 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 949 &ioport); 950 ioport &= 0x0000FF00; /* the actual base address */ 951 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 952 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 953 ITE_887x_POSIO_IOSIZE_8 | ioport); 954 955 /* write the ioport to the UARTBAR */ 956 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 957 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 958 uartbar |= (ioport << (16 * i)); /* set the ioport */ 959 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 960 961 /* get current config */ 962 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 963 /* disable interrupts (UARTx_Routing[3:0]) */ 964 miscr &= ~(0xf << (12 - 4 * i)); 965 /* activate the UART (UARTx_En) */ 966 miscr |= 1 << (23 - i); 967 /* write new config with activated UART */ 968 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 969 } 970 971 if (ret <= 0) { 972 /* the device has no UARTs if we get here */ 973 release_region(iobase->start, ITE_887x_IOSIZE); 974 } 975 976 return ret; 977 } 978 979 static void pci_ite887x_exit(struct pci_dev *dev) 980 { 981 u32 ioport; 982 /* the ioport is bit 0-15 in POSIO0R */ 983 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 984 ioport &= 0xffff; 985 release_region(ioport, ITE_887x_IOSIZE); 986 } 987 988 /* 989 * EndRun Technologies. 990 * Determine the number of ports available on the device. 991 */ 992 #define PCI_VENDOR_ID_ENDRUN 0x7401 993 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 994 995 static int pci_endrun_init(struct pci_dev *dev) 996 { 997 u8 __iomem *p; 998 unsigned long deviceID; 999 unsigned int number_uarts = 0; 1000 1001 /* EndRun device is all 0xexxx */ 1002 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1003 (dev->device & 0xf000) != 0xe000) 1004 return 0; 1005 1006 p = pci_iomap(dev, 0, 5); 1007 if (p == NULL) 1008 return -ENOMEM; 1009 1010 deviceID = ioread32(p); 1011 /* EndRun device */ 1012 if (deviceID == 0x07000200) { 1013 number_uarts = ioread8(p + 4); 1014 dev_dbg(&dev->dev, 1015 "%d ports detected on EndRun PCI Express device\n", 1016 number_uarts); 1017 } 1018 pci_iounmap(dev, p); 1019 return number_uarts; 1020 } 1021 1022 /* 1023 * Oxford Semiconductor Inc. 1024 * Check that device is part of the Tornado range of devices, then determine 1025 * the number of ports available on the device. 1026 */ 1027 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1028 { 1029 u8 __iomem *p; 1030 unsigned long deviceID; 1031 unsigned int number_uarts = 0; 1032 1033 /* OxSemi Tornado devices are all 0xCxxx */ 1034 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1035 (dev->device & 0xF000) != 0xC000) 1036 return 0; 1037 1038 p = pci_iomap(dev, 0, 5); 1039 if (p == NULL) 1040 return -ENOMEM; 1041 1042 deviceID = ioread32(p); 1043 /* Tornado device */ 1044 if (deviceID == 0x07000200) { 1045 number_uarts = ioread8(p + 4); 1046 dev_dbg(&dev->dev, 1047 "%d ports detected on Oxford PCI Express device\n", 1048 number_uarts); 1049 } 1050 pci_iounmap(dev, p); 1051 return number_uarts; 1052 } 1053 1054 static int pci_asix_setup(struct serial_private *priv, 1055 const struct pciserial_board *board, 1056 struct uart_8250_port *port, int idx) 1057 { 1058 port->bugs |= UART_BUG_PARITY; 1059 return pci_default_setup(priv, board, port, idx); 1060 } 1061 1062 /* Quatech devices have their own extra interface features */ 1063 1064 struct quatech_feature { 1065 u16 devid; 1066 bool amcc; 1067 }; 1068 1069 #define QPCR_TEST_FOR1 0x3F 1070 #define QPCR_TEST_GET1 0x00 1071 #define QPCR_TEST_FOR2 0x40 1072 #define QPCR_TEST_GET2 0x40 1073 #define QPCR_TEST_FOR3 0x80 1074 #define QPCR_TEST_GET3 0x40 1075 #define QPCR_TEST_FOR4 0xC0 1076 #define QPCR_TEST_GET4 0x80 1077 1078 #define QOPR_CLOCK_X1 0x0000 1079 #define QOPR_CLOCK_X2 0x0001 1080 #define QOPR_CLOCK_X4 0x0002 1081 #define QOPR_CLOCK_X8 0x0003 1082 #define QOPR_CLOCK_RATE_MASK 0x0003 1083 1084 1085 static struct quatech_feature quatech_cards[] = { 1086 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1087 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1088 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1089 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1090 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1091 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1092 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1096 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1097 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1098 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1099 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1101 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1103 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1104 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1105 { 0, } 1106 }; 1107 1108 static int pci_quatech_amcc(u16 devid) 1109 { 1110 struct quatech_feature *qf = &quatech_cards[0]; 1111 while (qf->devid) { 1112 if (qf->devid == devid) 1113 return qf->amcc; 1114 qf++; 1115 } 1116 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1117 return 0; 1118 }; 1119 1120 static int pci_quatech_rqopr(struct uart_8250_port *port) 1121 { 1122 unsigned long base = port->port.iobase; 1123 u8 LCR, val; 1124 1125 LCR = inb(base + UART_LCR); 1126 outb(0xBF, base + UART_LCR); 1127 val = inb(base + UART_SCR); 1128 outb(LCR, base + UART_LCR); 1129 return val; 1130 } 1131 1132 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1133 { 1134 unsigned long base = port->port.iobase; 1135 u8 LCR; 1136 1137 LCR = inb(base + UART_LCR); 1138 outb(0xBF, base + UART_LCR); 1139 inb(base + UART_SCR); 1140 outb(qopr, base + UART_SCR); 1141 outb(LCR, base + UART_LCR); 1142 } 1143 1144 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1145 { 1146 unsigned long base = port->port.iobase; 1147 u8 LCR, val, qmcr; 1148 1149 LCR = inb(base + UART_LCR); 1150 outb(0xBF, base + UART_LCR); 1151 val = inb(base + UART_SCR); 1152 outb(val | 0x10, base + UART_SCR); 1153 qmcr = inb(base + UART_MCR); 1154 outb(val, base + UART_SCR); 1155 outb(LCR, base + UART_LCR); 1156 1157 return qmcr; 1158 } 1159 1160 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1161 { 1162 unsigned long base = port->port.iobase; 1163 u8 LCR, val; 1164 1165 LCR = inb(base + UART_LCR); 1166 outb(0xBF, base + UART_LCR); 1167 val = inb(base + UART_SCR); 1168 outb(val | 0x10, base + UART_SCR); 1169 outb(qmcr, base + UART_MCR); 1170 outb(val, base + UART_SCR); 1171 outb(LCR, base + UART_LCR); 1172 } 1173 1174 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1175 { 1176 unsigned long base = port->port.iobase; 1177 u8 LCR, val; 1178 1179 LCR = inb(base + UART_LCR); 1180 outb(0xBF, base + UART_LCR); 1181 val = inb(base + UART_SCR); 1182 if (val & 0x20) { 1183 outb(0x80, UART_LCR); 1184 if (!(inb(UART_SCR) & 0x20)) { 1185 outb(LCR, base + UART_LCR); 1186 return 1; 1187 } 1188 } 1189 return 0; 1190 } 1191 1192 static int pci_quatech_test(struct uart_8250_port *port) 1193 { 1194 u8 reg, qopr; 1195 1196 qopr = pci_quatech_rqopr(port); 1197 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1198 reg = pci_quatech_rqopr(port) & 0xC0; 1199 if (reg != QPCR_TEST_GET1) 1200 return -EINVAL; 1201 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1202 reg = pci_quatech_rqopr(port) & 0xC0; 1203 if (reg != QPCR_TEST_GET2) 1204 return -EINVAL; 1205 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1206 reg = pci_quatech_rqopr(port) & 0xC0; 1207 if (reg != QPCR_TEST_GET3) 1208 return -EINVAL; 1209 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1210 reg = pci_quatech_rqopr(port) & 0xC0; 1211 if (reg != QPCR_TEST_GET4) 1212 return -EINVAL; 1213 1214 pci_quatech_wqopr(port, qopr); 1215 return 0; 1216 } 1217 1218 static int pci_quatech_clock(struct uart_8250_port *port) 1219 { 1220 u8 qopr, reg, set; 1221 unsigned long clock; 1222 1223 if (pci_quatech_test(port) < 0) 1224 return 1843200; 1225 1226 qopr = pci_quatech_rqopr(port); 1227 1228 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1229 reg = pci_quatech_rqopr(port); 1230 if (reg & QOPR_CLOCK_X8) { 1231 clock = 1843200; 1232 goto out; 1233 } 1234 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1235 reg = pci_quatech_rqopr(port); 1236 if (!(reg & QOPR_CLOCK_X8)) { 1237 clock = 1843200; 1238 goto out; 1239 } 1240 reg &= QOPR_CLOCK_X8; 1241 if (reg == QOPR_CLOCK_X2) { 1242 clock = 3685400; 1243 set = QOPR_CLOCK_X2; 1244 } else if (reg == QOPR_CLOCK_X4) { 1245 clock = 7372800; 1246 set = QOPR_CLOCK_X4; 1247 } else if (reg == QOPR_CLOCK_X8) { 1248 clock = 14745600; 1249 set = QOPR_CLOCK_X8; 1250 } else { 1251 clock = 1843200; 1252 set = QOPR_CLOCK_X1; 1253 } 1254 qopr &= ~QOPR_CLOCK_RATE_MASK; 1255 qopr |= set; 1256 1257 out: 1258 pci_quatech_wqopr(port, qopr); 1259 return clock; 1260 } 1261 1262 static int pci_quatech_rs422(struct uart_8250_port *port) 1263 { 1264 u8 qmcr; 1265 int rs422 = 0; 1266 1267 if (!pci_quatech_has_qmcr(port)) 1268 return 0; 1269 qmcr = pci_quatech_rqmcr(port); 1270 pci_quatech_wqmcr(port, 0xFF); 1271 if (pci_quatech_rqmcr(port)) 1272 rs422 = 1; 1273 pci_quatech_wqmcr(port, qmcr); 1274 return rs422; 1275 } 1276 1277 static int pci_quatech_init(struct pci_dev *dev) 1278 { 1279 if (pci_quatech_amcc(dev->device)) { 1280 unsigned long base = pci_resource_start(dev, 0); 1281 if (base) { 1282 u32 tmp; 1283 1284 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1285 tmp = inl(base + 0x3c); 1286 outl(tmp | 0x01000000, base + 0x3c); 1287 outl(tmp &= ~0x01000000, base + 0x3c); 1288 } 1289 } 1290 return 0; 1291 } 1292 1293 static int pci_quatech_setup(struct serial_private *priv, 1294 const struct pciserial_board *board, 1295 struct uart_8250_port *port, int idx) 1296 { 1297 /* Needed by pci_quatech calls below */ 1298 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1299 /* Set up the clocking */ 1300 port->port.uartclk = pci_quatech_clock(port); 1301 /* For now just warn about RS422 */ 1302 if (pci_quatech_rs422(port)) 1303 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1304 return pci_default_setup(priv, board, port, idx); 1305 } 1306 1307 static void pci_quatech_exit(struct pci_dev *dev) 1308 { 1309 } 1310 1311 static int pci_default_setup(struct serial_private *priv, 1312 const struct pciserial_board *board, 1313 struct uart_8250_port *port, int idx) 1314 { 1315 unsigned int bar, offset = board->first_offset, maxnr; 1316 1317 bar = FL_GET_BASE(board->flags); 1318 if (board->flags & FL_BASE_BARS) 1319 bar += idx; 1320 else 1321 offset += idx * board->uart_offset; 1322 1323 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1324 (board->reg_shift + 3); 1325 1326 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1327 return 1; 1328 1329 return setup_port(priv, port, bar, offset, board->reg_shift); 1330 } 1331 1332 static int 1333 ce4100_serial_setup(struct serial_private *priv, 1334 const struct pciserial_board *board, 1335 struct uart_8250_port *port, int idx) 1336 { 1337 int ret; 1338 1339 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1340 port->port.iotype = UPIO_MEM32; 1341 port->port.type = PORT_XSCALE; 1342 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1343 port->port.regshift = 2; 1344 1345 return ret; 1346 } 1347 1348 static int 1349 pci_omegapci_setup(struct serial_private *priv, 1350 const struct pciserial_board *board, 1351 struct uart_8250_port *port, int idx) 1352 { 1353 return setup_port(priv, port, 2, idx * 8, 0); 1354 } 1355 1356 static int 1357 pci_brcm_trumanage_setup(struct serial_private *priv, 1358 const struct pciserial_board *board, 1359 struct uart_8250_port *port, int idx) 1360 { 1361 int ret = pci_default_setup(priv, board, port, idx); 1362 1363 port->port.type = PORT_BRCM_TRUMANAGE; 1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1365 return ret; 1366 } 1367 1368 /* RTS will control by MCR if this bit is 0 */ 1369 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1370 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1371 #define FINTEK_RTS_INVERT BIT(5) 1372 1373 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1374 static int pci_fintek_rs485_config(struct uart_port *port, 1375 struct serial_rs485 *rs485) 1376 { 1377 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1378 u8 setting; 1379 u8 *index = (u8 *) port->private_data; 1380 1381 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1382 1383 if (!rs485) 1384 rs485 = &port->rs485; 1385 else if (rs485->flags & SER_RS485_ENABLED) 1386 memset(rs485->padding, 0, sizeof(rs485->padding)); 1387 else 1388 memset(rs485, 0, sizeof(*rs485)); 1389 1390 /* F81504/508/512 not support RTS delay before or after send */ 1391 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1392 1393 if (rs485->flags & SER_RS485_ENABLED) { 1394 /* Enable RTS H/W control mode */ 1395 setting |= FINTEK_RTS_CONTROL_BY_HW; 1396 1397 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1398 /* RTS driving high on TX */ 1399 setting &= ~FINTEK_RTS_INVERT; 1400 } else { 1401 /* RTS driving low on TX */ 1402 setting |= FINTEK_RTS_INVERT; 1403 } 1404 1405 rs485->delay_rts_after_send = 0; 1406 rs485->delay_rts_before_send = 0; 1407 } else { 1408 /* Disable RTS H/W control mode */ 1409 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1410 } 1411 1412 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1413 1414 if (rs485 != &port->rs485) 1415 port->rs485 = *rs485; 1416 1417 return 0; 1418 } 1419 1420 static int pci_fintek_setup(struct serial_private *priv, 1421 const struct pciserial_board *board, 1422 struct uart_8250_port *port, int idx) 1423 { 1424 struct pci_dev *pdev = priv->dev; 1425 u8 *data; 1426 u8 config_base; 1427 u16 iobase; 1428 1429 config_base = 0x40 + 0x08 * idx; 1430 1431 /* Get the io address from configuration space */ 1432 pci_read_config_word(pdev, config_base + 4, &iobase); 1433 1434 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1435 1436 port->port.iotype = UPIO_PORT; 1437 port->port.iobase = iobase; 1438 port->port.rs485_config = pci_fintek_rs485_config; 1439 1440 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1441 if (!data) 1442 return -ENOMEM; 1443 1444 /* preserve index in PCI configuration space */ 1445 *data = idx; 1446 port->port.private_data = data; 1447 1448 return 0; 1449 } 1450 1451 static int pci_fintek_init(struct pci_dev *dev) 1452 { 1453 unsigned long iobase; 1454 u32 max_port, i; 1455 u32 bar_data[3]; 1456 u8 config_base; 1457 struct serial_private *priv = pci_get_drvdata(dev); 1458 struct uart_8250_port *port; 1459 1460 switch (dev->device) { 1461 case 0x1104: /* 4 ports */ 1462 case 0x1108: /* 8 ports */ 1463 max_port = dev->device & 0xff; 1464 break; 1465 case 0x1112: /* 12 ports */ 1466 max_port = 12; 1467 break; 1468 default: 1469 return -EINVAL; 1470 } 1471 1472 /* Get the io address dispatch from the BIOS */ 1473 pci_read_config_dword(dev, 0x24, &bar_data[0]); 1474 pci_read_config_dword(dev, 0x20, &bar_data[1]); 1475 pci_read_config_dword(dev, 0x1c, &bar_data[2]); 1476 1477 for (i = 0; i < max_port; ++i) { 1478 /* UART0 configuration offset start from 0x40 */ 1479 config_base = 0x40 + 0x08 * i; 1480 1481 /* Calculate Real IO Port */ 1482 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1483 1484 /* Enable UART I/O port */ 1485 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1486 1487 /* Select 128-byte FIFO and 8x FIFO threshold */ 1488 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1489 1490 /* LSB UART */ 1491 pci_write_config_byte(dev, config_base + 0x04, 1492 (u8)(iobase & 0xff)); 1493 1494 /* MSB UART */ 1495 pci_write_config_byte(dev, config_base + 0x05, 1496 (u8)((iobase & 0xff00) >> 8)); 1497 1498 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1499 1500 if (priv) { 1501 /* re-apply RS232/485 mode when 1502 * pciserial_resume_ports() 1503 */ 1504 port = serial8250_get_port(priv->line[i]); 1505 pci_fintek_rs485_config(&port->port, NULL); 1506 } else { 1507 /* First init without port data 1508 * force init to RS232 Mode 1509 */ 1510 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1511 } 1512 } 1513 1514 return max_port; 1515 } 1516 1517 static int skip_tx_en_setup(struct serial_private *priv, 1518 const struct pciserial_board *board, 1519 struct uart_8250_port *port, int idx) 1520 { 1521 port->port.flags |= UPF_NO_TXEN_TEST; 1522 dev_dbg(&priv->dev->dev, 1523 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1524 priv->dev->vendor, priv->dev->device, 1525 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1526 1527 return pci_default_setup(priv, board, port, idx); 1528 } 1529 1530 static void kt_handle_break(struct uart_port *p) 1531 { 1532 struct uart_8250_port *up = up_to_u8250p(p); 1533 /* 1534 * On receipt of a BI, serial device in Intel ME (Intel 1535 * management engine) needs to have its fifos cleared for sane 1536 * SOL (Serial Over Lan) output. 1537 */ 1538 serial8250_clear_and_reinit_fifos(up); 1539 } 1540 1541 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1542 { 1543 struct uart_8250_port *up = up_to_u8250p(p); 1544 unsigned int val; 1545 1546 /* 1547 * When the Intel ME (management engine) gets reset its serial 1548 * port registers could return 0 momentarily. Functions like 1549 * serial8250_console_write, read and save the IER, perform 1550 * some operation and then restore it. In order to avoid 1551 * setting IER register inadvertently to 0, if the value read 1552 * is 0, double check with ier value in uart_8250_port and use 1553 * that instead. up->ier should be the same value as what is 1554 * currently configured. 1555 */ 1556 val = inb(p->iobase + offset); 1557 if (offset == UART_IER) { 1558 if (val == 0) 1559 val = up->ier; 1560 } 1561 return val; 1562 } 1563 1564 static int kt_serial_setup(struct serial_private *priv, 1565 const struct pciserial_board *board, 1566 struct uart_8250_port *port, int idx) 1567 { 1568 port->port.flags |= UPF_BUG_THRE; 1569 port->port.serial_in = kt_serial_in; 1570 port->port.handle_break = kt_handle_break; 1571 return skip_tx_en_setup(priv, board, port, idx); 1572 } 1573 1574 static int pci_eg20t_init(struct pci_dev *dev) 1575 { 1576 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1577 return -ENODEV; 1578 #else 1579 return 0; 1580 #endif 1581 } 1582 1583 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 1584 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 1585 1586 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 1587 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 1588 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 1589 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 1590 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 1591 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 1592 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 1593 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 1594 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 1595 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 1596 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 1597 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 1598 1599 static int 1600 pci_xr17c154_setup(struct serial_private *priv, 1601 const struct pciserial_board *board, 1602 struct uart_8250_port *port, int idx) 1603 { 1604 port->port.flags |= UPF_EXAR_EFR; 1605 return pci_default_setup(priv, board, port, idx); 1606 } 1607 1608 static inline int 1609 xr17v35x_has_slave(struct serial_private *priv) 1610 { 1611 const int dev_id = priv->dev->device; 1612 1613 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) || 1614 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358)); 1615 } 1616 1617 static int 1618 pci_xr17v35x_setup(struct serial_private *priv, 1619 const struct pciserial_board *board, 1620 struct uart_8250_port *port, int idx) 1621 { 1622 u8 __iomem *p; 1623 1624 p = pci_ioremap_bar(priv->dev, 0); 1625 if (p == NULL) 1626 return -ENOMEM; 1627 1628 port->port.flags |= UPF_EXAR_EFR; 1629 1630 /* 1631 * Setup the uart clock for the devices on expansion slot to 1632 * half the clock speed of the main chip (which is 125MHz) 1633 */ 1634 if (xr17v35x_has_slave(priv) && idx >= 8) 1635 port->port.uartclk = (7812500 * 16 / 2); 1636 1637 /* 1638 * Setup Multipurpose Input/Output pins. 1639 */ 1640 if (idx == 0) { 1641 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 1642 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 1643 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 1644 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 1645 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 1646 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 1647 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 1648 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 1649 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 1650 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 1651 writeb(0x00, p + UART_EXAR_MPIOSEL_15_8); 1652 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 1653 } 1654 writeb(0x00, p + UART_EXAR_8XMODE); 1655 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1656 writeb(128, p + UART_EXAR_TXTRG); 1657 writeb(128, p + UART_EXAR_RXTRG); 1658 iounmap(p); 1659 1660 return pci_default_setup(priv, board, port, idx); 1661 } 1662 1663 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1664 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1665 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1666 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1667 1668 static int 1669 pci_fastcom335_setup(struct serial_private *priv, 1670 const struct pciserial_board *board, 1671 struct uart_8250_port *port, int idx) 1672 { 1673 u8 __iomem *p; 1674 1675 p = pci_ioremap_bar(priv->dev, 0); 1676 if (p == NULL) 1677 return -ENOMEM; 1678 1679 port->port.flags |= UPF_EXAR_EFR; 1680 1681 /* 1682 * Setup Multipurpose Input/Output pins. 1683 */ 1684 if (idx == 0) { 1685 switch (priv->dev->device) { 1686 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1687 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1688 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 1689 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 1690 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 1691 break; 1692 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1693 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1694 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 1695 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 1696 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 1697 break; 1698 } 1699 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 1700 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 1701 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 1702 } 1703 writeb(0x00, p + UART_EXAR_8XMODE); 1704 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1705 writeb(32, p + UART_EXAR_TXTRG); 1706 writeb(32, p + UART_EXAR_RXTRG); 1707 iounmap(p); 1708 1709 return pci_default_setup(priv, board, port, idx); 1710 } 1711 1712 static int 1713 pci_wch_ch353_setup(struct serial_private *priv, 1714 const struct pciserial_board *board, 1715 struct uart_8250_port *port, int idx) 1716 { 1717 port->port.flags |= UPF_FIXED_TYPE; 1718 port->port.type = PORT_16550A; 1719 return pci_default_setup(priv, board, port, idx); 1720 } 1721 1722 static int 1723 pci_wch_ch355_setup(struct serial_private *priv, 1724 const struct pciserial_board *board, 1725 struct uart_8250_port *port, int idx) 1726 { 1727 port->port.flags |= UPF_FIXED_TYPE; 1728 port->port.type = PORT_16550A; 1729 return pci_default_setup(priv, board, port, idx); 1730 } 1731 1732 static int 1733 pci_wch_ch38x_setup(struct serial_private *priv, 1734 const struct pciserial_board *board, 1735 struct uart_8250_port *port, int idx) 1736 { 1737 port->port.flags |= UPF_FIXED_TYPE; 1738 port->port.type = PORT_16850; 1739 return pci_default_setup(priv, board, port, idx); 1740 } 1741 1742 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1743 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1744 #define PCI_DEVICE_ID_OCTPRO 0x0001 1745 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1746 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1747 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1748 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1749 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1750 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1751 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1752 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1753 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1754 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1755 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1756 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1757 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1758 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1759 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1760 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1761 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1762 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1763 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1764 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1765 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1766 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1767 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1768 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1769 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1770 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1771 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1772 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1773 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1774 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1775 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1776 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1777 #define PCI_VENDOR_ID_WCH 0x4348 1778 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1779 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1780 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1781 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1782 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1783 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1784 #define PCI_VENDOR_ID_AGESTAR 0x5372 1785 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1786 #define PCI_VENDOR_ID_ASIX 0x9710 1787 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1788 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1789 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1790 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1791 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1792 1793 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1794 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1795 1796 #define PCIE_VENDOR_ID_WCH 0x1c00 1797 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1798 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1799 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1800 1801 #define PCI_VENDOR_ID_PERICOM 0x12D8 1802 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1803 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1804 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1805 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1806 1807 #define PCI_VENDOR_ID_ACCESIO 0x494f 1808 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1809 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1810 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1811 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1812 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1813 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1814 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1815 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1816 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1817 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1818 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1819 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1820 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1821 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1822 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1823 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1824 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1825 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1826 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1827 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1828 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1829 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1830 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1831 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1832 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1833 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1834 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1835 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1836 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1837 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1838 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1839 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1840 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1841 1842 1843 1844 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1845 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1846 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1847 1848 /* 1849 * Master list of serial port init/setup/exit quirks. 1850 * This does not describe the general nature of the port. 1851 * (ie, baud base, number and location of ports, etc) 1852 * 1853 * This list is ordered alphabetically by vendor then device. 1854 * Specific entries must come before more generic entries. 1855 */ 1856 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1857 /* 1858 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1859 */ 1860 { 1861 .vendor = PCI_VENDOR_ID_AMCC, 1862 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1863 .subvendor = PCI_ANY_ID, 1864 .subdevice = PCI_ANY_ID, 1865 .setup = addidata_apci7800_setup, 1866 }, 1867 /* 1868 * AFAVLAB cards - these may be called via parport_serial 1869 * It is not clear whether this applies to all products. 1870 */ 1871 { 1872 .vendor = PCI_VENDOR_ID_AFAVLAB, 1873 .device = PCI_ANY_ID, 1874 .subvendor = PCI_ANY_ID, 1875 .subdevice = PCI_ANY_ID, 1876 .setup = afavlab_setup, 1877 }, 1878 /* 1879 * HP Diva 1880 */ 1881 { 1882 .vendor = PCI_VENDOR_ID_HP, 1883 .device = PCI_DEVICE_ID_HP_DIVA, 1884 .subvendor = PCI_ANY_ID, 1885 .subdevice = PCI_ANY_ID, 1886 .init = pci_hp_diva_init, 1887 .setup = pci_hp_diva_setup, 1888 }, 1889 /* 1890 * Intel 1891 */ 1892 { 1893 .vendor = PCI_VENDOR_ID_INTEL, 1894 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1895 .subvendor = 0xe4bf, 1896 .subdevice = PCI_ANY_ID, 1897 .init = pci_inteli960ni_init, 1898 .setup = pci_default_setup, 1899 }, 1900 { 1901 .vendor = PCI_VENDOR_ID_INTEL, 1902 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1903 .subvendor = PCI_ANY_ID, 1904 .subdevice = PCI_ANY_ID, 1905 .setup = skip_tx_en_setup, 1906 }, 1907 { 1908 .vendor = PCI_VENDOR_ID_INTEL, 1909 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1910 .subvendor = PCI_ANY_ID, 1911 .subdevice = PCI_ANY_ID, 1912 .setup = skip_tx_en_setup, 1913 }, 1914 { 1915 .vendor = PCI_VENDOR_ID_INTEL, 1916 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1917 .subvendor = PCI_ANY_ID, 1918 .subdevice = PCI_ANY_ID, 1919 .setup = skip_tx_en_setup, 1920 }, 1921 { 1922 .vendor = PCI_VENDOR_ID_INTEL, 1923 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1924 .subvendor = PCI_ANY_ID, 1925 .subdevice = PCI_ANY_ID, 1926 .setup = ce4100_serial_setup, 1927 }, 1928 { 1929 .vendor = PCI_VENDOR_ID_INTEL, 1930 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1931 .subvendor = PCI_ANY_ID, 1932 .subdevice = PCI_ANY_ID, 1933 .setup = kt_serial_setup, 1934 }, 1935 /* 1936 * ITE 1937 */ 1938 { 1939 .vendor = PCI_VENDOR_ID_ITE, 1940 .device = PCI_DEVICE_ID_ITE_8872, 1941 .subvendor = PCI_ANY_ID, 1942 .subdevice = PCI_ANY_ID, 1943 .init = pci_ite887x_init, 1944 .setup = pci_default_setup, 1945 .exit = pci_ite887x_exit, 1946 }, 1947 /* 1948 * National Instruments 1949 */ 1950 { 1951 .vendor = PCI_VENDOR_ID_NI, 1952 .device = PCI_DEVICE_ID_NI_PCI23216, 1953 .subvendor = PCI_ANY_ID, 1954 .subdevice = PCI_ANY_ID, 1955 .init = pci_ni8420_init, 1956 .setup = pci_default_setup, 1957 .exit = pci_ni8420_exit, 1958 }, 1959 { 1960 .vendor = PCI_VENDOR_ID_NI, 1961 .device = PCI_DEVICE_ID_NI_PCI2328, 1962 .subvendor = PCI_ANY_ID, 1963 .subdevice = PCI_ANY_ID, 1964 .init = pci_ni8420_init, 1965 .setup = pci_default_setup, 1966 .exit = pci_ni8420_exit, 1967 }, 1968 { 1969 .vendor = PCI_VENDOR_ID_NI, 1970 .device = PCI_DEVICE_ID_NI_PCI2324, 1971 .subvendor = PCI_ANY_ID, 1972 .subdevice = PCI_ANY_ID, 1973 .init = pci_ni8420_init, 1974 .setup = pci_default_setup, 1975 .exit = pci_ni8420_exit, 1976 }, 1977 { 1978 .vendor = PCI_VENDOR_ID_NI, 1979 .device = PCI_DEVICE_ID_NI_PCI2322, 1980 .subvendor = PCI_ANY_ID, 1981 .subdevice = PCI_ANY_ID, 1982 .init = pci_ni8420_init, 1983 .setup = pci_default_setup, 1984 .exit = pci_ni8420_exit, 1985 }, 1986 { 1987 .vendor = PCI_VENDOR_ID_NI, 1988 .device = PCI_DEVICE_ID_NI_PCI2324I, 1989 .subvendor = PCI_ANY_ID, 1990 .subdevice = PCI_ANY_ID, 1991 .init = pci_ni8420_init, 1992 .setup = pci_default_setup, 1993 .exit = pci_ni8420_exit, 1994 }, 1995 { 1996 .vendor = PCI_VENDOR_ID_NI, 1997 .device = PCI_DEVICE_ID_NI_PCI2322I, 1998 .subvendor = PCI_ANY_ID, 1999 .subdevice = PCI_ANY_ID, 2000 .init = pci_ni8420_init, 2001 .setup = pci_default_setup, 2002 .exit = pci_ni8420_exit, 2003 }, 2004 { 2005 .vendor = PCI_VENDOR_ID_NI, 2006 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2007 .subvendor = PCI_ANY_ID, 2008 .subdevice = PCI_ANY_ID, 2009 .init = pci_ni8420_init, 2010 .setup = pci_default_setup, 2011 .exit = pci_ni8420_exit, 2012 }, 2013 { 2014 .vendor = PCI_VENDOR_ID_NI, 2015 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2016 .subvendor = PCI_ANY_ID, 2017 .subdevice = PCI_ANY_ID, 2018 .init = pci_ni8420_init, 2019 .setup = pci_default_setup, 2020 .exit = pci_ni8420_exit, 2021 }, 2022 { 2023 .vendor = PCI_VENDOR_ID_NI, 2024 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2025 .subvendor = PCI_ANY_ID, 2026 .subdevice = PCI_ANY_ID, 2027 .init = pci_ni8420_init, 2028 .setup = pci_default_setup, 2029 .exit = pci_ni8420_exit, 2030 }, 2031 { 2032 .vendor = PCI_VENDOR_ID_NI, 2033 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2034 .subvendor = PCI_ANY_ID, 2035 .subdevice = PCI_ANY_ID, 2036 .init = pci_ni8420_init, 2037 .setup = pci_default_setup, 2038 .exit = pci_ni8420_exit, 2039 }, 2040 { 2041 .vendor = PCI_VENDOR_ID_NI, 2042 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2043 .subvendor = PCI_ANY_ID, 2044 .subdevice = PCI_ANY_ID, 2045 .init = pci_ni8420_init, 2046 .setup = pci_default_setup, 2047 .exit = pci_ni8420_exit, 2048 }, 2049 { 2050 .vendor = PCI_VENDOR_ID_NI, 2051 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2052 .subvendor = PCI_ANY_ID, 2053 .subdevice = PCI_ANY_ID, 2054 .init = pci_ni8420_init, 2055 .setup = pci_default_setup, 2056 .exit = pci_ni8420_exit, 2057 }, 2058 { 2059 .vendor = PCI_VENDOR_ID_NI, 2060 .device = PCI_ANY_ID, 2061 .subvendor = PCI_ANY_ID, 2062 .subdevice = PCI_ANY_ID, 2063 .init = pci_ni8430_init, 2064 .setup = pci_ni8430_setup, 2065 .exit = pci_ni8430_exit, 2066 }, 2067 /* Quatech */ 2068 { 2069 .vendor = PCI_VENDOR_ID_QUATECH, 2070 .device = PCI_ANY_ID, 2071 .subvendor = PCI_ANY_ID, 2072 .subdevice = PCI_ANY_ID, 2073 .init = pci_quatech_init, 2074 .setup = pci_quatech_setup, 2075 .exit = pci_quatech_exit, 2076 }, 2077 /* 2078 * Panacom 2079 */ 2080 { 2081 .vendor = PCI_VENDOR_ID_PANACOM, 2082 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2083 .subvendor = PCI_ANY_ID, 2084 .subdevice = PCI_ANY_ID, 2085 .init = pci_plx9050_init, 2086 .setup = pci_default_setup, 2087 .exit = pci_plx9050_exit, 2088 }, 2089 { 2090 .vendor = PCI_VENDOR_ID_PANACOM, 2091 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2092 .subvendor = PCI_ANY_ID, 2093 .subdevice = PCI_ANY_ID, 2094 .init = pci_plx9050_init, 2095 .setup = pci_default_setup, 2096 .exit = pci_plx9050_exit, 2097 }, 2098 /* 2099 * PLX 2100 */ 2101 { 2102 .vendor = PCI_VENDOR_ID_PLX, 2103 .device = PCI_DEVICE_ID_PLX_9050, 2104 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2105 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2106 .init = pci_plx9050_init, 2107 .setup = pci_default_setup, 2108 .exit = pci_plx9050_exit, 2109 }, 2110 { 2111 .vendor = PCI_VENDOR_ID_PLX, 2112 .device = PCI_DEVICE_ID_PLX_9050, 2113 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2114 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2115 .init = pci_plx9050_init, 2116 .setup = pci_default_setup, 2117 .exit = pci_plx9050_exit, 2118 }, 2119 { 2120 .vendor = PCI_VENDOR_ID_PLX, 2121 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2122 .subvendor = PCI_VENDOR_ID_PLX, 2123 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2124 .init = pci_plx9050_init, 2125 .setup = pci_default_setup, 2126 .exit = pci_plx9050_exit, 2127 }, 2128 /* 2129 * SBS Technologies, Inc., PMC-OCTALPRO 232 2130 */ 2131 { 2132 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2133 .device = PCI_DEVICE_ID_OCTPRO, 2134 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2135 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2136 .init = sbs_init, 2137 .setup = sbs_setup, 2138 .exit = sbs_exit, 2139 }, 2140 /* 2141 * SBS Technologies, Inc., PMC-OCTALPRO 422 2142 */ 2143 { 2144 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2145 .device = PCI_DEVICE_ID_OCTPRO, 2146 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2147 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2148 .init = sbs_init, 2149 .setup = sbs_setup, 2150 .exit = sbs_exit, 2151 }, 2152 /* 2153 * SBS Technologies, Inc., P-Octal 232 2154 */ 2155 { 2156 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2157 .device = PCI_DEVICE_ID_OCTPRO, 2158 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2159 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2160 .init = sbs_init, 2161 .setup = sbs_setup, 2162 .exit = sbs_exit, 2163 }, 2164 /* 2165 * SBS Technologies, Inc., P-Octal 422 2166 */ 2167 { 2168 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2169 .device = PCI_DEVICE_ID_OCTPRO, 2170 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2171 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2172 .init = sbs_init, 2173 .setup = sbs_setup, 2174 .exit = sbs_exit, 2175 }, 2176 /* 2177 * SIIG cards - these may be called via parport_serial 2178 */ 2179 { 2180 .vendor = PCI_VENDOR_ID_SIIG, 2181 .device = PCI_ANY_ID, 2182 .subvendor = PCI_ANY_ID, 2183 .subdevice = PCI_ANY_ID, 2184 .init = pci_siig_init, 2185 .setup = pci_siig_setup, 2186 }, 2187 /* 2188 * Titan cards 2189 */ 2190 { 2191 .vendor = PCI_VENDOR_ID_TITAN, 2192 .device = PCI_DEVICE_ID_TITAN_400L, 2193 .subvendor = PCI_ANY_ID, 2194 .subdevice = PCI_ANY_ID, 2195 .setup = titan_400l_800l_setup, 2196 }, 2197 { 2198 .vendor = PCI_VENDOR_ID_TITAN, 2199 .device = PCI_DEVICE_ID_TITAN_800L, 2200 .subvendor = PCI_ANY_ID, 2201 .subdevice = PCI_ANY_ID, 2202 .setup = titan_400l_800l_setup, 2203 }, 2204 /* 2205 * Timedia cards 2206 */ 2207 { 2208 .vendor = PCI_VENDOR_ID_TIMEDIA, 2209 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2210 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2211 .subdevice = PCI_ANY_ID, 2212 .probe = pci_timedia_probe, 2213 .init = pci_timedia_init, 2214 .setup = pci_timedia_setup, 2215 }, 2216 { 2217 .vendor = PCI_VENDOR_ID_TIMEDIA, 2218 .device = PCI_ANY_ID, 2219 .subvendor = PCI_ANY_ID, 2220 .subdevice = PCI_ANY_ID, 2221 .setup = pci_timedia_setup, 2222 }, 2223 /* 2224 * SUNIX (Timedia) cards 2225 * Do not "probe" for these cards as there is at least one combination 2226 * card that should be handled by parport_pc that doesn't match the 2227 * rule in pci_timedia_probe. 2228 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2229 * There are some boards with part number SER5037AL that report 2230 * subdevice ID 0x0002. 2231 */ 2232 { 2233 .vendor = PCI_VENDOR_ID_SUNIX, 2234 .device = PCI_DEVICE_ID_SUNIX_1999, 2235 .subvendor = PCI_VENDOR_ID_SUNIX, 2236 .subdevice = PCI_ANY_ID, 2237 .init = pci_timedia_init, 2238 .setup = pci_timedia_setup, 2239 }, 2240 /* 2241 * Exar cards 2242 */ 2243 { 2244 .vendor = PCI_VENDOR_ID_EXAR, 2245 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2246 .subvendor = PCI_ANY_ID, 2247 .subdevice = PCI_ANY_ID, 2248 .setup = pci_xr17c154_setup, 2249 }, 2250 { 2251 .vendor = PCI_VENDOR_ID_EXAR, 2252 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2253 .subvendor = PCI_ANY_ID, 2254 .subdevice = PCI_ANY_ID, 2255 .setup = pci_xr17c154_setup, 2256 }, 2257 { 2258 .vendor = PCI_VENDOR_ID_EXAR, 2259 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2260 .subvendor = PCI_ANY_ID, 2261 .subdevice = PCI_ANY_ID, 2262 .setup = pci_xr17c154_setup, 2263 }, 2264 { 2265 .vendor = PCI_VENDOR_ID_EXAR, 2266 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2267 .subvendor = PCI_ANY_ID, 2268 .subdevice = PCI_ANY_ID, 2269 .setup = pci_xr17v35x_setup, 2270 }, 2271 { 2272 .vendor = PCI_VENDOR_ID_EXAR, 2273 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2274 .subvendor = PCI_ANY_ID, 2275 .subdevice = PCI_ANY_ID, 2276 .setup = pci_xr17v35x_setup, 2277 }, 2278 { 2279 .vendor = PCI_VENDOR_ID_EXAR, 2280 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2281 .subvendor = PCI_ANY_ID, 2282 .subdevice = PCI_ANY_ID, 2283 .setup = pci_xr17v35x_setup, 2284 }, 2285 { 2286 .vendor = PCI_VENDOR_ID_EXAR, 2287 .device = PCI_DEVICE_ID_EXAR_XR17V4358, 2288 .subvendor = PCI_ANY_ID, 2289 .subdevice = PCI_ANY_ID, 2290 .setup = pci_xr17v35x_setup, 2291 }, 2292 { 2293 .vendor = PCI_VENDOR_ID_EXAR, 2294 .device = PCI_DEVICE_ID_EXAR_XR17V8358, 2295 .subvendor = PCI_ANY_ID, 2296 .subdevice = PCI_ANY_ID, 2297 .setup = pci_xr17v35x_setup, 2298 }, 2299 /* 2300 * Xircom cards 2301 */ 2302 { 2303 .vendor = PCI_VENDOR_ID_XIRCOM, 2304 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2305 .subvendor = PCI_ANY_ID, 2306 .subdevice = PCI_ANY_ID, 2307 .init = pci_xircom_init, 2308 .setup = pci_default_setup, 2309 }, 2310 /* 2311 * Netmos cards - these may be called via parport_serial 2312 */ 2313 { 2314 .vendor = PCI_VENDOR_ID_NETMOS, 2315 .device = PCI_ANY_ID, 2316 .subvendor = PCI_ANY_ID, 2317 .subdevice = PCI_ANY_ID, 2318 .init = pci_netmos_init, 2319 .setup = pci_netmos_9900_setup, 2320 }, 2321 /* 2322 * EndRun Technologies 2323 */ 2324 { 2325 .vendor = PCI_VENDOR_ID_ENDRUN, 2326 .device = PCI_ANY_ID, 2327 .subvendor = PCI_ANY_ID, 2328 .subdevice = PCI_ANY_ID, 2329 .init = pci_endrun_init, 2330 .setup = pci_default_setup, 2331 }, 2332 /* 2333 * For Oxford Semiconductor Tornado based devices 2334 */ 2335 { 2336 .vendor = PCI_VENDOR_ID_OXSEMI, 2337 .device = PCI_ANY_ID, 2338 .subvendor = PCI_ANY_ID, 2339 .subdevice = PCI_ANY_ID, 2340 .init = pci_oxsemi_tornado_init, 2341 .setup = pci_default_setup, 2342 }, 2343 { 2344 .vendor = PCI_VENDOR_ID_MAINPINE, 2345 .device = PCI_ANY_ID, 2346 .subvendor = PCI_ANY_ID, 2347 .subdevice = PCI_ANY_ID, 2348 .init = pci_oxsemi_tornado_init, 2349 .setup = pci_default_setup, 2350 }, 2351 { 2352 .vendor = PCI_VENDOR_ID_DIGI, 2353 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2354 .subvendor = PCI_SUBVENDOR_ID_IBM, 2355 .subdevice = PCI_ANY_ID, 2356 .init = pci_oxsemi_tornado_init, 2357 .setup = pci_default_setup, 2358 }, 2359 { 2360 .vendor = PCI_VENDOR_ID_INTEL, 2361 .device = 0x8811, 2362 .subvendor = PCI_ANY_ID, 2363 .subdevice = PCI_ANY_ID, 2364 .init = pci_eg20t_init, 2365 .setup = pci_default_setup, 2366 }, 2367 { 2368 .vendor = PCI_VENDOR_ID_INTEL, 2369 .device = 0x8812, 2370 .subvendor = PCI_ANY_ID, 2371 .subdevice = PCI_ANY_ID, 2372 .init = pci_eg20t_init, 2373 .setup = pci_default_setup, 2374 }, 2375 { 2376 .vendor = PCI_VENDOR_ID_INTEL, 2377 .device = 0x8813, 2378 .subvendor = PCI_ANY_ID, 2379 .subdevice = PCI_ANY_ID, 2380 .init = pci_eg20t_init, 2381 .setup = pci_default_setup, 2382 }, 2383 { 2384 .vendor = PCI_VENDOR_ID_INTEL, 2385 .device = 0x8814, 2386 .subvendor = PCI_ANY_ID, 2387 .subdevice = PCI_ANY_ID, 2388 .init = pci_eg20t_init, 2389 .setup = pci_default_setup, 2390 }, 2391 { 2392 .vendor = 0x10DB, 2393 .device = 0x8027, 2394 .subvendor = PCI_ANY_ID, 2395 .subdevice = PCI_ANY_ID, 2396 .init = pci_eg20t_init, 2397 .setup = pci_default_setup, 2398 }, 2399 { 2400 .vendor = 0x10DB, 2401 .device = 0x8028, 2402 .subvendor = PCI_ANY_ID, 2403 .subdevice = PCI_ANY_ID, 2404 .init = pci_eg20t_init, 2405 .setup = pci_default_setup, 2406 }, 2407 { 2408 .vendor = 0x10DB, 2409 .device = 0x8029, 2410 .subvendor = PCI_ANY_ID, 2411 .subdevice = PCI_ANY_ID, 2412 .init = pci_eg20t_init, 2413 .setup = pci_default_setup, 2414 }, 2415 { 2416 .vendor = 0x10DB, 2417 .device = 0x800C, 2418 .subvendor = PCI_ANY_ID, 2419 .subdevice = PCI_ANY_ID, 2420 .init = pci_eg20t_init, 2421 .setup = pci_default_setup, 2422 }, 2423 { 2424 .vendor = 0x10DB, 2425 .device = 0x800D, 2426 .subvendor = PCI_ANY_ID, 2427 .subdevice = PCI_ANY_ID, 2428 .init = pci_eg20t_init, 2429 .setup = pci_default_setup, 2430 }, 2431 /* 2432 * Cronyx Omega PCI (PLX-chip based) 2433 */ 2434 { 2435 .vendor = PCI_VENDOR_ID_PLX, 2436 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2437 .subvendor = PCI_ANY_ID, 2438 .subdevice = PCI_ANY_ID, 2439 .setup = pci_omegapci_setup, 2440 }, 2441 /* WCH CH353 1S1P card (16550 clone) */ 2442 { 2443 .vendor = PCI_VENDOR_ID_WCH, 2444 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2445 .subvendor = PCI_ANY_ID, 2446 .subdevice = PCI_ANY_ID, 2447 .setup = pci_wch_ch353_setup, 2448 }, 2449 /* WCH CH353 2S1P card (16550 clone) */ 2450 { 2451 .vendor = PCI_VENDOR_ID_WCH, 2452 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2453 .subvendor = PCI_ANY_ID, 2454 .subdevice = PCI_ANY_ID, 2455 .setup = pci_wch_ch353_setup, 2456 }, 2457 /* WCH CH353 4S card (16550 clone) */ 2458 { 2459 .vendor = PCI_VENDOR_ID_WCH, 2460 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2461 .subvendor = PCI_ANY_ID, 2462 .subdevice = PCI_ANY_ID, 2463 .setup = pci_wch_ch353_setup, 2464 }, 2465 /* WCH CH353 2S1PF card (16550 clone) */ 2466 { 2467 .vendor = PCI_VENDOR_ID_WCH, 2468 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2469 .subvendor = PCI_ANY_ID, 2470 .subdevice = PCI_ANY_ID, 2471 .setup = pci_wch_ch353_setup, 2472 }, 2473 /* WCH CH352 2S card (16550 clone) */ 2474 { 2475 .vendor = PCI_VENDOR_ID_WCH, 2476 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2477 .subvendor = PCI_ANY_ID, 2478 .subdevice = PCI_ANY_ID, 2479 .setup = pci_wch_ch353_setup, 2480 }, 2481 /* WCH CH355 4S card (16550 clone) */ 2482 { 2483 .vendor = PCI_VENDOR_ID_WCH, 2484 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2485 .subvendor = PCI_ANY_ID, 2486 .subdevice = PCI_ANY_ID, 2487 .setup = pci_wch_ch355_setup, 2488 }, 2489 /* WCH CH382 2S card (16850 clone) */ 2490 { 2491 .vendor = PCIE_VENDOR_ID_WCH, 2492 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2493 .subvendor = PCI_ANY_ID, 2494 .subdevice = PCI_ANY_ID, 2495 .setup = pci_wch_ch38x_setup, 2496 }, 2497 /* WCH CH382 2S1P card (16850 clone) */ 2498 { 2499 .vendor = PCIE_VENDOR_ID_WCH, 2500 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2501 .subvendor = PCI_ANY_ID, 2502 .subdevice = PCI_ANY_ID, 2503 .setup = pci_wch_ch38x_setup, 2504 }, 2505 /* WCH CH384 4S card (16850 clone) */ 2506 { 2507 .vendor = PCIE_VENDOR_ID_WCH, 2508 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2509 .subvendor = PCI_ANY_ID, 2510 .subdevice = PCI_ANY_ID, 2511 .setup = pci_wch_ch38x_setup, 2512 }, 2513 /* 2514 * ASIX devices with FIFO bug 2515 */ 2516 { 2517 .vendor = PCI_VENDOR_ID_ASIX, 2518 .device = PCI_ANY_ID, 2519 .subvendor = PCI_ANY_ID, 2520 .subdevice = PCI_ANY_ID, 2521 .setup = pci_asix_setup, 2522 }, 2523 /* 2524 * Commtech, Inc. Fastcom adapters 2525 * 2526 */ 2527 { 2528 .vendor = PCI_VENDOR_ID_COMMTECH, 2529 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2530 .subvendor = PCI_ANY_ID, 2531 .subdevice = PCI_ANY_ID, 2532 .setup = pci_fastcom335_setup, 2533 }, 2534 { 2535 .vendor = PCI_VENDOR_ID_COMMTECH, 2536 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2537 .subvendor = PCI_ANY_ID, 2538 .subdevice = PCI_ANY_ID, 2539 .setup = pci_fastcom335_setup, 2540 }, 2541 { 2542 .vendor = PCI_VENDOR_ID_COMMTECH, 2543 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2544 .subvendor = PCI_ANY_ID, 2545 .subdevice = PCI_ANY_ID, 2546 .setup = pci_fastcom335_setup, 2547 }, 2548 { 2549 .vendor = PCI_VENDOR_ID_COMMTECH, 2550 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2551 .subvendor = PCI_ANY_ID, 2552 .subdevice = PCI_ANY_ID, 2553 .setup = pci_fastcom335_setup, 2554 }, 2555 { 2556 .vendor = PCI_VENDOR_ID_COMMTECH, 2557 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2558 .subvendor = PCI_ANY_ID, 2559 .subdevice = PCI_ANY_ID, 2560 .setup = pci_xr17v35x_setup, 2561 }, 2562 { 2563 .vendor = PCI_VENDOR_ID_COMMTECH, 2564 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2565 .subvendor = PCI_ANY_ID, 2566 .subdevice = PCI_ANY_ID, 2567 .setup = pci_xr17v35x_setup, 2568 }, 2569 { 2570 .vendor = PCI_VENDOR_ID_COMMTECH, 2571 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2572 .subvendor = PCI_ANY_ID, 2573 .subdevice = PCI_ANY_ID, 2574 .setup = pci_xr17v35x_setup, 2575 }, 2576 /* 2577 * Broadcom TruManage (NetXtreme) 2578 */ 2579 { 2580 .vendor = PCI_VENDOR_ID_BROADCOM, 2581 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2582 .subvendor = PCI_ANY_ID, 2583 .subdevice = PCI_ANY_ID, 2584 .setup = pci_brcm_trumanage_setup, 2585 }, 2586 { 2587 .vendor = 0x1c29, 2588 .device = 0x1104, 2589 .subvendor = PCI_ANY_ID, 2590 .subdevice = PCI_ANY_ID, 2591 .setup = pci_fintek_setup, 2592 .init = pci_fintek_init, 2593 }, 2594 { 2595 .vendor = 0x1c29, 2596 .device = 0x1108, 2597 .subvendor = PCI_ANY_ID, 2598 .subdevice = PCI_ANY_ID, 2599 .setup = pci_fintek_setup, 2600 .init = pci_fintek_init, 2601 }, 2602 { 2603 .vendor = 0x1c29, 2604 .device = 0x1112, 2605 .subvendor = PCI_ANY_ID, 2606 .subdevice = PCI_ANY_ID, 2607 .setup = pci_fintek_setup, 2608 .init = pci_fintek_init, 2609 }, 2610 2611 /* 2612 * Default "match everything" terminator entry 2613 */ 2614 { 2615 .vendor = PCI_ANY_ID, 2616 .device = PCI_ANY_ID, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .setup = pci_default_setup, 2620 } 2621 }; 2622 2623 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2624 { 2625 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2626 } 2627 2628 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2629 { 2630 struct pci_serial_quirk *quirk; 2631 2632 for (quirk = pci_serial_quirks; ; quirk++) 2633 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2634 quirk_id_matches(quirk->device, dev->device) && 2635 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2636 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2637 break; 2638 return quirk; 2639 } 2640 2641 static inline int get_pci_irq(struct pci_dev *dev, 2642 const struct pciserial_board *board) 2643 { 2644 if (board->flags & FL_NOIRQ) 2645 return 0; 2646 else 2647 return dev->irq; 2648 } 2649 2650 /* 2651 * This is the configuration table for all of the PCI serial boards 2652 * which we support. It is directly indexed by the pci_board_num_t enum 2653 * value, which is encoded in the pci_device_id PCI probe table's 2654 * driver_data member. 2655 * 2656 * The makeup of these names are: 2657 * pbn_bn{_bt}_n_baud{_offsetinhex} 2658 * 2659 * bn = PCI BAR number 2660 * bt = Index using PCI BARs 2661 * n = number of serial ports 2662 * baud = baud rate 2663 * offsetinhex = offset for each sequential port (in hex) 2664 * 2665 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2666 * 2667 * Please note: in theory if n = 1, _bt infix should make no difference. 2668 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2669 */ 2670 enum pci_board_num_t { 2671 pbn_default = 0, 2672 2673 pbn_b0_1_115200, 2674 pbn_b0_2_115200, 2675 pbn_b0_4_115200, 2676 pbn_b0_5_115200, 2677 pbn_b0_8_115200, 2678 2679 pbn_b0_1_921600, 2680 pbn_b0_2_921600, 2681 pbn_b0_4_921600, 2682 2683 pbn_b0_2_1130000, 2684 2685 pbn_b0_4_1152000, 2686 2687 pbn_b0_2_1152000_200, 2688 pbn_b0_4_1152000_200, 2689 pbn_b0_8_1152000_200, 2690 2691 pbn_b0_2_1843200, 2692 pbn_b0_4_1843200, 2693 2694 pbn_b0_2_1843200_200, 2695 pbn_b0_4_1843200_200, 2696 pbn_b0_8_1843200_200, 2697 2698 pbn_b0_1_4000000, 2699 2700 pbn_b0_bt_1_115200, 2701 pbn_b0_bt_2_115200, 2702 pbn_b0_bt_4_115200, 2703 pbn_b0_bt_8_115200, 2704 2705 pbn_b0_bt_1_460800, 2706 pbn_b0_bt_2_460800, 2707 pbn_b0_bt_4_460800, 2708 2709 pbn_b0_bt_1_921600, 2710 pbn_b0_bt_2_921600, 2711 pbn_b0_bt_4_921600, 2712 pbn_b0_bt_8_921600, 2713 2714 pbn_b1_1_115200, 2715 pbn_b1_2_115200, 2716 pbn_b1_4_115200, 2717 pbn_b1_8_115200, 2718 pbn_b1_16_115200, 2719 2720 pbn_b1_1_921600, 2721 pbn_b1_2_921600, 2722 pbn_b1_4_921600, 2723 pbn_b1_8_921600, 2724 2725 pbn_b1_2_1250000, 2726 2727 pbn_b1_bt_1_115200, 2728 pbn_b1_bt_2_115200, 2729 pbn_b1_bt_4_115200, 2730 2731 pbn_b1_bt_2_921600, 2732 2733 pbn_b1_1_1382400, 2734 pbn_b1_2_1382400, 2735 pbn_b1_4_1382400, 2736 pbn_b1_8_1382400, 2737 2738 pbn_b2_1_115200, 2739 pbn_b2_2_115200, 2740 pbn_b2_4_115200, 2741 pbn_b2_8_115200, 2742 2743 pbn_b2_1_460800, 2744 pbn_b2_4_460800, 2745 pbn_b2_8_460800, 2746 pbn_b2_16_460800, 2747 2748 pbn_b2_1_921600, 2749 pbn_b2_4_921600, 2750 pbn_b2_8_921600, 2751 2752 pbn_b2_8_1152000, 2753 2754 pbn_b2_bt_1_115200, 2755 pbn_b2_bt_2_115200, 2756 pbn_b2_bt_4_115200, 2757 2758 pbn_b2_bt_2_921600, 2759 pbn_b2_bt_4_921600, 2760 2761 pbn_b3_2_115200, 2762 pbn_b3_4_115200, 2763 pbn_b3_8_115200, 2764 2765 pbn_b4_bt_2_921600, 2766 pbn_b4_bt_4_921600, 2767 pbn_b4_bt_8_921600, 2768 2769 /* 2770 * Board-specific versions. 2771 */ 2772 pbn_panacom, 2773 pbn_panacom2, 2774 pbn_panacom4, 2775 pbn_plx_romulus, 2776 pbn_endrun_2_4000000, 2777 pbn_oxsemi, 2778 pbn_oxsemi_1_4000000, 2779 pbn_oxsemi_2_4000000, 2780 pbn_oxsemi_4_4000000, 2781 pbn_oxsemi_8_4000000, 2782 pbn_intel_i960, 2783 pbn_sgi_ioc3, 2784 pbn_computone_4, 2785 pbn_computone_6, 2786 pbn_computone_8, 2787 pbn_sbsxrsio, 2788 pbn_exar_XR17C152, 2789 pbn_exar_XR17C154, 2790 pbn_exar_XR17C158, 2791 pbn_exar_XR17V352, 2792 pbn_exar_XR17V354, 2793 pbn_exar_XR17V358, 2794 pbn_exar_XR17V4358, 2795 pbn_exar_XR17V8358, 2796 pbn_exar_ibm_saturn, 2797 pbn_pasemi_1682M, 2798 pbn_ni8430_2, 2799 pbn_ni8430_4, 2800 pbn_ni8430_8, 2801 pbn_ni8430_16, 2802 pbn_ADDIDATA_PCIe_1_3906250, 2803 pbn_ADDIDATA_PCIe_2_3906250, 2804 pbn_ADDIDATA_PCIe_4_3906250, 2805 pbn_ADDIDATA_PCIe_8_3906250, 2806 pbn_ce4100_1_115200, 2807 pbn_omegapci, 2808 pbn_NETMOS9900_2s_115200, 2809 pbn_brcm_trumanage, 2810 pbn_fintek_4, 2811 pbn_fintek_8, 2812 pbn_fintek_12, 2813 pbn_wch382_2, 2814 pbn_wch384_4, 2815 pbn_pericom_PI7C9X7951, 2816 pbn_pericom_PI7C9X7952, 2817 pbn_pericom_PI7C9X7954, 2818 pbn_pericom_PI7C9X7958, 2819 }; 2820 2821 /* 2822 * uart_offset - the space between channels 2823 * reg_shift - describes how the UART registers are mapped 2824 * to PCI memory by the card. 2825 * For example IER register on SBS, Inc. PMC-OctPro is located at 2826 * offset 0x10 from the UART base, while UART_IER is defined as 1 2827 * in include/linux/serial_reg.h, 2828 * see first lines of serial_in() and serial_out() in 8250.c 2829 */ 2830 2831 static struct pciserial_board pci_boards[] = { 2832 [pbn_default] = { 2833 .flags = FL_BASE0, 2834 .num_ports = 1, 2835 .base_baud = 115200, 2836 .uart_offset = 8, 2837 }, 2838 [pbn_b0_1_115200] = { 2839 .flags = FL_BASE0, 2840 .num_ports = 1, 2841 .base_baud = 115200, 2842 .uart_offset = 8, 2843 }, 2844 [pbn_b0_2_115200] = { 2845 .flags = FL_BASE0, 2846 .num_ports = 2, 2847 .base_baud = 115200, 2848 .uart_offset = 8, 2849 }, 2850 [pbn_b0_4_115200] = { 2851 .flags = FL_BASE0, 2852 .num_ports = 4, 2853 .base_baud = 115200, 2854 .uart_offset = 8, 2855 }, 2856 [pbn_b0_5_115200] = { 2857 .flags = FL_BASE0, 2858 .num_ports = 5, 2859 .base_baud = 115200, 2860 .uart_offset = 8, 2861 }, 2862 [pbn_b0_8_115200] = { 2863 .flags = FL_BASE0, 2864 .num_ports = 8, 2865 .base_baud = 115200, 2866 .uart_offset = 8, 2867 }, 2868 [pbn_b0_1_921600] = { 2869 .flags = FL_BASE0, 2870 .num_ports = 1, 2871 .base_baud = 921600, 2872 .uart_offset = 8, 2873 }, 2874 [pbn_b0_2_921600] = { 2875 .flags = FL_BASE0, 2876 .num_ports = 2, 2877 .base_baud = 921600, 2878 .uart_offset = 8, 2879 }, 2880 [pbn_b0_4_921600] = { 2881 .flags = FL_BASE0, 2882 .num_ports = 4, 2883 .base_baud = 921600, 2884 .uart_offset = 8, 2885 }, 2886 2887 [pbn_b0_2_1130000] = { 2888 .flags = FL_BASE0, 2889 .num_ports = 2, 2890 .base_baud = 1130000, 2891 .uart_offset = 8, 2892 }, 2893 2894 [pbn_b0_4_1152000] = { 2895 .flags = FL_BASE0, 2896 .num_ports = 4, 2897 .base_baud = 1152000, 2898 .uart_offset = 8, 2899 }, 2900 2901 [pbn_b0_2_1152000_200] = { 2902 .flags = FL_BASE0, 2903 .num_ports = 2, 2904 .base_baud = 1152000, 2905 .uart_offset = 0x200, 2906 }, 2907 2908 [pbn_b0_4_1152000_200] = { 2909 .flags = FL_BASE0, 2910 .num_ports = 4, 2911 .base_baud = 1152000, 2912 .uart_offset = 0x200, 2913 }, 2914 2915 [pbn_b0_8_1152000_200] = { 2916 .flags = FL_BASE0, 2917 .num_ports = 8, 2918 .base_baud = 1152000, 2919 .uart_offset = 0x200, 2920 }, 2921 2922 [pbn_b0_2_1843200] = { 2923 .flags = FL_BASE0, 2924 .num_ports = 2, 2925 .base_baud = 1843200, 2926 .uart_offset = 8, 2927 }, 2928 [pbn_b0_4_1843200] = { 2929 .flags = FL_BASE0, 2930 .num_ports = 4, 2931 .base_baud = 1843200, 2932 .uart_offset = 8, 2933 }, 2934 2935 [pbn_b0_2_1843200_200] = { 2936 .flags = FL_BASE0, 2937 .num_ports = 2, 2938 .base_baud = 1843200, 2939 .uart_offset = 0x200, 2940 }, 2941 [pbn_b0_4_1843200_200] = { 2942 .flags = FL_BASE0, 2943 .num_ports = 4, 2944 .base_baud = 1843200, 2945 .uart_offset = 0x200, 2946 }, 2947 [pbn_b0_8_1843200_200] = { 2948 .flags = FL_BASE0, 2949 .num_ports = 8, 2950 .base_baud = 1843200, 2951 .uart_offset = 0x200, 2952 }, 2953 [pbn_b0_1_4000000] = { 2954 .flags = FL_BASE0, 2955 .num_ports = 1, 2956 .base_baud = 4000000, 2957 .uart_offset = 8, 2958 }, 2959 2960 [pbn_b0_bt_1_115200] = { 2961 .flags = FL_BASE0|FL_BASE_BARS, 2962 .num_ports = 1, 2963 .base_baud = 115200, 2964 .uart_offset = 8, 2965 }, 2966 [pbn_b0_bt_2_115200] = { 2967 .flags = FL_BASE0|FL_BASE_BARS, 2968 .num_ports = 2, 2969 .base_baud = 115200, 2970 .uart_offset = 8, 2971 }, 2972 [pbn_b0_bt_4_115200] = { 2973 .flags = FL_BASE0|FL_BASE_BARS, 2974 .num_ports = 4, 2975 .base_baud = 115200, 2976 .uart_offset = 8, 2977 }, 2978 [pbn_b0_bt_8_115200] = { 2979 .flags = FL_BASE0|FL_BASE_BARS, 2980 .num_ports = 8, 2981 .base_baud = 115200, 2982 .uart_offset = 8, 2983 }, 2984 2985 [pbn_b0_bt_1_460800] = { 2986 .flags = FL_BASE0|FL_BASE_BARS, 2987 .num_ports = 1, 2988 .base_baud = 460800, 2989 .uart_offset = 8, 2990 }, 2991 [pbn_b0_bt_2_460800] = { 2992 .flags = FL_BASE0|FL_BASE_BARS, 2993 .num_ports = 2, 2994 .base_baud = 460800, 2995 .uart_offset = 8, 2996 }, 2997 [pbn_b0_bt_4_460800] = { 2998 .flags = FL_BASE0|FL_BASE_BARS, 2999 .num_ports = 4, 3000 .base_baud = 460800, 3001 .uart_offset = 8, 3002 }, 3003 3004 [pbn_b0_bt_1_921600] = { 3005 .flags = FL_BASE0|FL_BASE_BARS, 3006 .num_ports = 1, 3007 .base_baud = 921600, 3008 .uart_offset = 8, 3009 }, 3010 [pbn_b0_bt_2_921600] = { 3011 .flags = FL_BASE0|FL_BASE_BARS, 3012 .num_ports = 2, 3013 .base_baud = 921600, 3014 .uart_offset = 8, 3015 }, 3016 [pbn_b0_bt_4_921600] = { 3017 .flags = FL_BASE0|FL_BASE_BARS, 3018 .num_ports = 4, 3019 .base_baud = 921600, 3020 .uart_offset = 8, 3021 }, 3022 [pbn_b0_bt_8_921600] = { 3023 .flags = FL_BASE0|FL_BASE_BARS, 3024 .num_ports = 8, 3025 .base_baud = 921600, 3026 .uart_offset = 8, 3027 }, 3028 3029 [pbn_b1_1_115200] = { 3030 .flags = FL_BASE1, 3031 .num_ports = 1, 3032 .base_baud = 115200, 3033 .uart_offset = 8, 3034 }, 3035 [pbn_b1_2_115200] = { 3036 .flags = FL_BASE1, 3037 .num_ports = 2, 3038 .base_baud = 115200, 3039 .uart_offset = 8, 3040 }, 3041 [pbn_b1_4_115200] = { 3042 .flags = FL_BASE1, 3043 .num_ports = 4, 3044 .base_baud = 115200, 3045 .uart_offset = 8, 3046 }, 3047 [pbn_b1_8_115200] = { 3048 .flags = FL_BASE1, 3049 .num_ports = 8, 3050 .base_baud = 115200, 3051 .uart_offset = 8, 3052 }, 3053 [pbn_b1_16_115200] = { 3054 .flags = FL_BASE1, 3055 .num_ports = 16, 3056 .base_baud = 115200, 3057 .uart_offset = 8, 3058 }, 3059 3060 [pbn_b1_1_921600] = { 3061 .flags = FL_BASE1, 3062 .num_ports = 1, 3063 .base_baud = 921600, 3064 .uart_offset = 8, 3065 }, 3066 [pbn_b1_2_921600] = { 3067 .flags = FL_BASE1, 3068 .num_ports = 2, 3069 .base_baud = 921600, 3070 .uart_offset = 8, 3071 }, 3072 [pbn_b1_4_921600] = { 3073 .flags = FL_BASE1, 3074 .num_ports = 4, 3075 .base_baud = 921600, 3076 .uart_offset = 8, 3077 }, 3078 [pbn_b1_8_921600] = { 3079 .flags = FL_BASE1, 3080 .num_ports = 8, 3081 .base_baud = 921600, 3082 .uart_offset = 8, 3083 }, 3084 [pbn_b1_2_1250000] = { 3085 .flags = FL_BASE1, 3086 .num_ports = 2, 3087 .base_baud = 1250000, 3088 .uart_offset = 8, 3089 }, 3090 3091 [pbn_b1_bt_1_115200] = { 3092 .flags = FL_BASE1|FL_BASE_BARS, 3093 .num_ports = 1, 3094 .base_baud = 115200, 3095 .uart_offset = 8, 3096 }, 3097 [pbn_b1_bt_2_115200] = { 3098 .flags = FL_BASE1|FL_BASE_BARS, 3099 .num_ports = 2, 3100 .base_baud = 115200, 3101 .uart_offset = 8, 3102 }, 3103 [pbn_b1_bt_4_115200] = { 3104 .flags = FL_BASE1|FL_BASE_BARS, 3105 .num_ports = 4, 3106 .base_baud = 115200, 3107 .uart_offset = 8, 3108 }, 3109 3110 [pbn_b1_bt_2_921600] = { 3111 .flags = FL_BASE1|FL_BASE_BARS, 3112 .num_ports = 2, 3113 .base_baud = 921600, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b1_1_1382400] = { 3118 .flags = FL_BASE1, 3119 .num_ports = 1, 3120 .base_baud = 1382400, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b1_2_1382400] = { 3124 .flags = FL_BASE1, 3125 .num_ports = 2, 3126 .base_baud = 1382400, 3127 .uart_offset = 8, 3128 }, 3129 [pbn_b1_4_1382400] = { 3130 .flags = FL_BASE1, 3131 .num_ports = 4, 3132 .base_baud = 1382400, 3133 .uart_offset = 8, 3134 }, 3135 [pbn_b1_8_1382400] = { 3136 .flags = FL_BASE1, 3137 .num_ports = 8, 3138 .base_baud = 1382400, 3139 .uart_offset = 8, 3140 }, 3141 3142 [pbn_b2_1_115200] = { 3143 .flags = FL_BASE2, 3144 .num_ports = 1, 3145 .base_baud = 115200, 3146 .uart_offset = 8, 3147 }, 3148 [pbn_b2_2_115200] = { 3149 .flags = FL_BASE2, 3150 .num_ports = 2, 3151 .base_baud = 115200, 3152 .uart_offset = 8, 3153 }, 3154 [pbn_b2_4_115200] = { 3155 .flags = FL_BASE2, 3156 .num_ports = 4, 3157 .base_baud = 115200, 3158 .uart_offset = 8, 3159 }, 3160 [pbn_b2_8_115200] = { 3161 .flags = FL_BASE2, 3162 .num_ports = 8, 3163 .base_baud = 115200, 3164 .uart_offset = 8, 3165 }, 3166 3167 [pbn_b2_1_460800] = { 3168 .flags = FL_BASE2, 3169 .num_ports = 1, 3170 .base_baud = 460800, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b2_4_460800] = { 3174 .flags = FL_BASE2, 3175 .num_ports = 4, 3176 .base_baud = 460800, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b2_8_460800] = { 3180 .flags = FL_BASE2, 3181 .num_ports = 8, 3182 .base_baud = 460800, 3183 .uart_offset = 8, 3184 }, 3185 [pbn_b2_16_460800] = { 3186 .flags = FL_BASE2, 3187 .num_ports = 16, 3188 .base_baud = 460800, 3189 .uart_offset = 8, 3190 }, 3191 3192 [pbn_b2_1_921600] = { 3193 .flags = FL_BASE2, 3194 .num_ports = 1, 3195 .base_baud = 921600, 3196 .uart_offset = 8, 3197 }, 3198 [pbn_b2_4_921600] = { 3199 .flags = FL_BASE2, 3200 .num_ports = 4, 3201 .base_baud = 921600, 3202 .uart_offset = 8, 3203 }, 3204 [pbn_b2_8_921600] = { 3205 .flags = FL_BASE2, 3206 .num_ports = 8, 3207 .base_baud = 921600, 3208 .uart_offset = 8, 3209 }, 3210 3211 [pbn_b2_8_1152000] = { 3212 .flags = FL_BASE2, 3213 .num_ports = 8, 3214 .base_baud = 1152000, 3215 .uart_offset = 8, 3216 }, 3217 3218 [pbn_b2_bt_1_115200] = { 3219 .flags = FL_BASE2|FL_BASE_BARS, 3220 .num_ports = 1, 3221 .base_baud = 115200, 3222 .uart_offset = 8, 3223 }, 3224 [pbn_b2_bt_2_115200] = { 3225 .flags = FL_BASE2|FL_BASE_BARS, 3226 .num_ports = 2, 3227 .base_baud = 115200, 3228 .uart_offset = 8, 3229 }, 3230 [pbn_b2_bt_4_115200] = { 3231 .flags = FL_BASE2|FL_BASE_BARS, 3232 .num_ports = 4, 3233 .base_baud = 115200, 3234 .uart_offset = 8, 3235 }, 3236 3237 [pbn_b2_bt_2_921600] = { 3238 .flags = FL_BASE2|FL_BASE_BARS, 3239 .num_ports = 2, 3240 .base_baud = 921600, 3241 .uart_offset = 8, 3242 }, 3243 [pbn_b2_bt_4_921600] = { 3244 .flags = FL_BASE2|FL_BASE_BARS, 3245 .num_ports = 4, 3246 .base_baud = 921600, 3247 .uart_offset = 8, 3248 }, 3249 3250 [pbn_b3_2_115200] = { 3251 .flags = FL_BASE3, 3252 .num_ports = 2, 3253 .base_baud = 115200, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b3_4_115200] = { 3257 .flags = FL_BASE3, 3258 .num_ports = 4, 3259 .base_baud = 115200, 3260 .uart_offset = 8, 3261 }, 3262 [pbn_b3_8_115200] = { 3263 .flags = FL_BASE3, 3264 .num_ports = 8, 3265 .base_baud = 115200, 3266 .uart_offset = 8, 3267 }, 3268 3269 [pbn_b4_bt_2_921600] = { 3270 .flags = FL_BASE4, 3271 .num_ports = 2, 3272 .base_baud = 921600, 3273 .uart_offset = 8, 3274 }, 3275 [pbn_b4_bt_4_921600] = { 3276 .flags = FL_BASE4, 3277 .num_ports = 4, 3278 .base_baud = 921600, 3279 .uart_offset = 8, 3280 }, 3281 [pbn_b4_bt_8_921600] = { 3282 .flags = FL_BASE4, 3283 .num_ports = 8, 3284 .base_baud = 921600, 3285 .uart_offset = 8, 3286 }, 3287 3288 /* 3289 * Entries following this are board-specific. 3290 */ 3291 3292 /* 3293 * Panacom - IOMEM 3294 */ 3295 [pbn_panacom] = { 3296 .flags = FL_BASE2, 3297 .num_ports = 2, 3298 .base_baud = 921600, 3299 .uart_offset = 0x400, 3300 .reg_shift = 7, 3301 }, 3302 [pbn_panacom2] = { 3303 .flags = FL_BASE2|FL_BASE_BARS, 3304 .num_ports = 2, 3305 .base_baud = 921600, 3306 .uart_offset = 0x400, 3307 .reg_shift = 7, 3308 }, 3309 [pbn_panacom4] = { 3310 .flags = FL_BASE2|FL_BASE_BARS, 3311 .num_ports = 4, 3312 .base_baud = 921600, 3313 .uart_offset = 0x400, 3314 .reg_shift = 7, 3315 }, 3316 3317 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3318 [pbn_plx_romulus] = { 3319 .flags = FL_BASE2, 3320 .num_ports = 4, 3321 .base_baud = 921600, 3322 .uart_offset = 8 << 2, 3323 .reg_shift = 2, 3324 .first_offset = 0x03, 3325 }, 3326 3327 /* 3328 * EndRun Technologies 3329 * Uses the size of PCI Base region 0 to 3330 * signal now many ports are available 3331 * 2 port 952 Uart support 3332 */ 3333 [pbn_endrun_2_4000000] = { 3334 .flags = FL_BASE0, 3335 .num_ports = 2, 3336 .base_baud = 4000000, 3337 .uart_offset = 0x200, 3338 .first_offset = 0x1000, 3339 }, 3340 3341 /* 3342 * This board uses the size of PCI Base region 0 to 3343 * signal now many ports are available 3344 */ 3345 [pbn_oxsemi] = { 3346 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3347 .num_ports = 32, 3348 .base_baud = 115200, 3349 .uart_offset = 8, 3350 }, 3351 [pbn_oxsemi_1_4000000] = { 3352 .flags = FL_BASE0, 3353 .num_ports = 1, 3354 .base_baud = 4000000, 3355 .uart_offset = 0x200, 3356 .first_offset = 0x1000, 3357 }, 3358 [pbn_oxsemi_2_4000000] = { 3359 .flags = FL_BASE0, 3360 .num_ports = 2, 3361 .base_baud = 4000000, 3362 .uart_offset = 0x200, 3363 .first_offset = 0x1000, 3364 }, 3365 [pbn_oxsemi_4_4000000] = { 3366 .flags = FL_BASE0, 3367 .num_ports = 4, 3368 .base_baud = 4000000, 3369 .uart_offset = 0x200, 3370 .first_offset = 0x1000, 3371 }, 3372 [pbn_oxsemi_8_4000000] = { 3373 .flags = FL_BASE0, 3374 .num_ports = 8, 3375 .base_baud = 4000000, 3376 .uart_offset = 0x200, 3377 .first_offset = 0x1000, 3378 }, 3379 3380 3381 /* 3382 * EKF addition for i960 Boards form EKF with serial port. 3383 * Max 256 ports. 3384 */ 3385 [pbn_intel_i960] = { 3386 .flags = FL_BASE0, 3387 .num_ports = 32, 3388 .base_baud = 921600, 3389 .uart_offset = 8 << 2, 3390 .reg_shift = 2, 3391 .first_offset = 0x10000, 3392 }, 3393 [pbn_sgi_ioc3] = { 3394 .flags = FL_BASE0|FL_NOIRQ, 3395 .num_ports = 1, 3396 .base_baud = 458333, 3397 .uart_offset = 8, 3398 .reg_shift = 0, 3399 .first_offset = 0x20178, 3400 }, 3401 3402 /* 3403 * Computone - uses IOMEM. 3404 */ 3405 [pbn_computone_4] = { 3406 .flags = FL_BASE0, 3407 .num_ports = 4, 3408 .base_baud = 921600, 3409 .uart_offset = 0x40, 3410 .reg_shift = 2, 3411 .first_offset = 0x200, 3412 }, 3413 [pbn_computone_6] = { 3414 .flags = FL_BASE0, 3415 .num_ports = 6, 3416 .base_baud = 921600, 3417 .uart_offset = 0x40, 3418 .reg_shift = 2, 3419 .first_offset = 0x200, 3420 }, 3421 [pbn_computone_8] = { 3422 .flags = FL_BASE0, 3423 .num_ports = 8, 3424 .base_baud = 921600, 3425 .uart_offset = 0x40, 3426 .reg_shift = 2, 3427 .first_offset = 0x200, 3428 }, 3429 [pbn_sbsxrsio] = { 3430 .flags = FL_BASE0, 3431 .num_ports = 8, 3432 .base_baud = 460800, 3433 .uart_offset = 256, 3434 .reg_shift = 4, 3435 }, 3436 /* 3437 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3438 * Only basic 16550A support. 3439 * XR17C15[24] are not tested, but they should work. 3440 */ 3441 [pbn_exar_XR17C152] = { 3442 .flags = FL_BASE0, 3443 .num_ports = 2, 3444 .base_baud = 921600, 3445 .uart_offset = 0x200, 3446 }, 3447 [pbn_exar_XR17C154] = { 3448 .flags = FL_BASE0, 3449 .num_ports = 4, 3450 .base_baud = 921600, 3451 .uart_offset = 0x200, 3452 }, 3453 [pbn_exar_XR17C158] = { 3454 .flags = FL_BASE0, 3455 .num_ports = 8, 3456 .base_baud = 921600, 3457 .uart_offset = 0x200, 3458 }, 3459 [pbn_exar_XR17V352] = { 3460 .flags = FL_BASE0, 3461 .num_ports = 2, 3462 .base_baud = 7812500, 3463 .uart_offset = 0x400, 3464 .reg_shift = 0, 3465 .first_offset = 0, 3466 }, 3467 [pbn_exar_XR17V354] = { 3468 .flags = FL_BASE0, 3469 .num_ports = 4, 3470 .base_baud = 7812500, 3471 .uart_offset = 0x400, 3472 .reg_shift = 0, 3473 .first_offset = 0, 3474 }, 3475 [pbn_exar_XR17V358] = { 3476 .flags = FL_BASE0, 3477 .num_ports = 8, 3478 .base_baud = 7812500, 3479 .uart_offset = 0x400, 3480 .reg_shift = 0, 3481 .first_offset = 0, 3482 }, 3483 [pbn_exar_XR17V4358] = { 3484 .flags = FL_BASE0, 3485 .num_ports = 12, 3486 .base_baud = 7812500, 3487 .uart_offset = 0x400, 3488 .reg_shift = 0, 3489 .first_offset = 0, 3490 }, 3491 [pbn_exar_XR17V8358] = { 3492 .flags = FL_BASE0, 3493 .num_ports = 16, 3494 .base_baud = 7812500, 3495 .uart_offset = 0x400, 3496 .reg_shift = 0, 3497 .first_offset = 0, 3498 }, 3499 [pbn_exar_ibm_saturn] = { 3500 .flags = FL_BASE0, 3501 .num_ports = 1, 3502 .base_baud = 921600, 3503 .uart_offset = 0x200, 3504 }, 3505 3506 /* 3507 * PA Semi PWRficient PA6T-1682M on-chip UART 3508 */ 3509 [pbn_pasemi_1682M] = { 3510 .flags = FL_BASE0, 3511 .num_ports = 1, 3512 .base_baud = 8333333, 3513 }, 3514 /* 3515 * National Instruments 843x 3516 */ 3517 [pbn_ni8430_16] = { 3518 .flags = FL_BASE0, 3519 .num_ports = 16, 3520 .base_baud = 3686400, 3521 .uart_offset = 0x10, 3522 .first_offset = 0x800, 3523 }, 3524 [pbn_ni8430_8] = { 3525 .flags = FL_BASE0, 3526 .num_ports = 8, 3527 .base_baud = 3686400, 3528 .uart_offset = 0x10, 3529 .first_offset = 0x800, 3530 }, 3531 [pbn_ni8430_4] = { 3532 .flags = FL_BASE0, 3533 .num_ports = 4, 3534 .base_baud = 3686400, 3535 .uart_offset = 0x10, 3536 .first_offset = 0x800, 3537 }, 3538 [pbn_ni8430_2] = { 3539 .flags = FL_BASE0, 3540 .num_ports = 2, 3541 .base_baud = 3686400, 3542 .uart_offset = 0x10, 3543 .first_offset = 0x800, 3544 }, 3545 /* 3546 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3547 */ 3548 [pbn_ADDIDATA_PCIe_1_3906250] = { 3549 .flags = FL_BASE0, 3550 .num_ports = 1, 3551 .base_baud = 3906250, 3552 .uart_offset = 0x200, 3553 .first_offset = 0x1000, 3554 }, 3555 [pbn_ADDIDATA_PCIe_2_3906250] = { 3556 .flags = FL_BASE0, 3557 .num_ports = 2, 3558 .base_baud = 3906250, 3559 .uart_offset = 0x200, 3560 .first_offset = 0x1000, 3561 }, 3562 [pbn_ADDIDATA_PCIe_4_3906250] = { 3563 .flags = FL_BASE0, 3564 .num_ports = 4, 3565 .base_baud = 3906250, 3566 .uart_offset = 0x200, 3567 .first_offset = 0x1000, 3568 }, 3569 [pbn_ADDIDATA_PCIe_8_3906250] = { 3570 .flags = FL_BASE0, 3571 .num_ports = 8, 3572 .base_baud = 3906250, 3573 .uart_offset = 0x200, 3574 .first_offset = 0x1000, 3575 }, 3576 [pbn_ce4100_1_115200] = { 3577 .flags = FL_BASE_BARS, 3578 .num_ports = 2, 3579 .base_baud = 921600, 3580 .reg_shift = 2, 3581 }, 3582 [pbn_omegapci] = { 3583 .flags = FL_BASE0, 3584 .num_ports = 8, 3585 .base_baud = 115200, 3586 .uart_offset = 0x200, 3587 }, 3588 [pbn_NETMOS9900_2s_115200] = { 3589 .flags = FL_BASE0, 3590 .num_ports = 2, 3591 .base_baud = 115200, 3592 }, 3593 [pbn_brcm_trumanage] = { 3594 .flags = FL_BASE0, 3595 .num_ports = 1, 3596 .reg_shift = 2, 3597 .base_baud = 115200, 3598 }, 3599 [pbn_fintek_4] = { 3600 .num_ports = 4, 3601 .uart_offset = 8, 3602 .base_baud = 115200, 3603 .first_offset = 0x40, 3604 }, 3605 [pbn_fintek_8] = { 3606 .num_ports = 8, 3607 .uart_offset = 8, 3608 .base_baud = 115200, 3609 .first_offset = 0x40, 3610 }, 3611 [pbn_fintek_12] = { 3612 .num_ports = 12, 3613 .uart_offset = 8, 3614 .base_baud = 115200, 3615 .first_offset = 0x40, 3616 }, 3617 [pbn_wch382_2] = { 3618 .flags = FL_BASE0, 3619 .num_ports = 2, 3620 .base_baud = 115200, 3621 .uart_offset = 8, 3622 .first_offset = 0xC0, 3623 }, 3624 [pbn_wch384_4] = { 3625 .flags = FL_BASE0, 3626 .num_ports = 4, 3627 .base_baud = 115200, 3628 .uart_offset = 8, 3629 .first_offset = 0xC0, 3630 }, 3631 /* 3632 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3633 */ 3634 [pbn_pericom_PI7C9X7951] = { 3635 .flags = FL_BASE0, 3636 .num_ports = 1, 3637 .base_baud = 921600, 3638 .uart_offset = 0x8, 3639 }, 3640 [pbn_pericom_PI7C9X7952] = { 3641 .flags = FL_BASE0, 3642 .num_ports = 2, 3643 .base_baud = 921600, 3644 .uart_offset = 0x8, 3645 }, 3646 [pbn_pericom_PI7C9X7954] = { 3647 .flags = FL_BASE0, 3648 .num_ports = 4, 3649 .base_baud = 921600, 3650 .uart_offset = 0x8, 3651 }, 3652 [pbn_pericom_PI7C9X7958] = { 3653 .flags = FL_BASE0, 3654 .num_ports = 8, 3655 .base_baud = 921600, 3656 .uart_offset = 0x8, 3657 }, 3658 }; 3659 3660 static const struct pci_device_id blacklist[] = { 3661 /* softmodems */ 3662 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3663 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3664 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3665 3666 /* multi-io cards handled by parport_serial */ 3667 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3668 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3669 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */ 3670 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3671 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ 3672 3673 /* Moxa Smartio MUE boards handled by 8250_moxa */ 3674 { PCI_VDEVICE(MOXA, 0x1024), }, 3675 { PCI_VDEVICE(MOXA, 0x1025), }, 3676 { PCI_VDEVICE(MOXA, 0x1045), }, 3677 { PCI_VDEVICE(MOXA, 0x1144), }, 3678 { PCI_VDEVICE(MOXA, 0x1160), }, 3679 { PCI_VDEVICE(MOXA, 0x1161), }, 3680 { PCI_VDEVICE(MOXA, 0x1182), }, 3681 { PCI_VDEVICE(MOXA, 0x1183), }, 3682 { PCI_VDEVICE(MOXA, 0x1322), }, 3683 { PCI_VDEVICE(MOXA, 0x1342), }, 3684 { PCI_VDEVICE(MOXA, 0x1381), }, 3685 { PCI_VDEVICE(MOXA, 0x1683), }, 3686 3687 /* Intel platforms with MID UART */ 3688 { PCI_VDEVICE(INTEL, 0x081b), }, 3689 { PCI_VDEVICE(INTEL, 0x081c), }, 3690 { PCI_VDEVICE(INTEL, 0x081d), }, 3691 { PCI_VDEVICE(INTEL, 0x1191), }, 3692 { PCI_VDEVICE(INTEL, 0x19d8), }, 3693 3694 /* Intel platforms with DesignWare UART */ 3695 { PCI_VDEVICE(INTEL, 0x0936), }, 3696 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3697 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3698 { PCI_VDEVICE(INTEL, 0x228a), }, 3699 { PCI_VDEVICE(INTEL, 0x228c), }, 3700 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3701 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3702 }; 3703 3704 /* 3705 * Given a complete unknown PCI device, try to use some heuristics to 3706 * guess what the configuration might be, based on the pitiful PCI 3707 * serial specs. Returns 0 on success, 1 on failure. 3708 */ 3709 static int 3710 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3711 { 3712 const struct pci_device_id *bldev; 3713 int num_iomem, num_port, first_port = -1, i; 3714 3715 /* 3716 * If it is not a communications device or the programming 3717 * interface is greater than 6, give up. 3718 * 3719 * (Should we try to make guesses for multiport serial devices 3720 * later?) 3721 */ 3722 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3723 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3724 (dev->class & 0xff) > 6) 3725 return -ENODEV; 3726 3727 /* 3728 * Do not access blacklisted devices that are known not to 3729 * feature serial ports or are handled by other modules. 3730 */ 3731 for (bldev = blacklist; 3732 bldev < blacklist + ARRAY_SIZE(blacklist); 3733 bldev++) { 3734 if (dev->vendor == bldev->vendor && 3735 dev->device == bldev->device) 3736 return -ENODEV; 3737 } 3738 3739 num_iomem = num_port = 0; 3740 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3741 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3742 num_port++; 3743 if (first_port == -1) 3744 first_port = i; 3745 } 3746 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3747 num_iomem++; 3748 } 3749 3750 /* 3751 * If there is 1 or 0 iomem regions, and exactly one port, 3752 * use it. We guess the number of ports based on the IO 3753 * region size. 3754 */ 3755 if (num_iomem <= 1 && num_port == 1) { 3756 board->flags = first_port; 3757 board->num_ports = pci_resource_len(dev, first_port) / 8; 3758 return 0; 3759 } 3760 3761 /* 3762 * Now guess if we've got a board which indexes by BARs. 3763 * Each IO BAR should be 8 bytes, and they should follow 3764 * consecutively. 3765 */ 3766 first_port = -1; 3767 num_port = 0; 3768 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3769 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3770 pci_resource_len(dev, i) == 8 && 3771 (first_port == -1 || (first_port + num_port) == i)) { 3772 num_port++; 3773 if (first_port == -1) 3774 first_port = i; 3775 } 3776 } 3777 3778 if (num_port > 1) { 3779 board->flags = first_port | FL_BASE_BARS; 3780 board->num_ports = num_port; 3781 return 0; 3782 } 3783 3784 return -ENODEV; 3785 } 3786 3787 static inline int 3788 serial_pci_matches(const struct pciserial_board *board, 3789 const struct pciserial_board *guessed) 3790 { 3791 return 3792 board->num_ports == guessed->num_ports && 3793 board->base_baud == guessed->base_baud && 3794 board->uart_offset == guessed->uart_offset && 3795 board->reg_shift == guessed->reg_shift && 3796 board->first_offset == guessed->first_offset; 3797 } 3798 3799 struct serial_private * 3800 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3801 { 3802 struct uart_8250_port uart; 3803 struct serial_private *priv; 3804 struct pci_serial_quirk *quirk; 3805 int rc, nr_ports, i; 3806 3807 nr_ports = board->num_ports; 3808 3809 /* 3810 * Find an init and setup quirks. 3811 */ 3812 quirk = find_quirk(dev); 3813 3814 /* 3815 * Run the new-style initialization function. 3816 * The initialization function returns: 3817 * <0 - error 3818 * 0 - use board->num_ports 3819 * >0 - number of ports 3820 */ 3821 if (quirk->init) { 3822 rc = quirk->init(dev); 3823 if (rc < 0) { 3824 priv = ERR_PTR(rc); 3825 goto err_out; 3826 } 3827 if (rc) 3828 nr_ports = rc; 3829 } 3830 3831 priv = kzalloc(sizeof(struct serial_private) + 3832 sizeof(unsigned int) * nr_ports, 3833 GFP_KERNEL); 3834 if (!priv) { 3835 priv = ERR_PTR(-ENOMEM); 3836 goto err_deinit; 3837 } 3838 3839 priv->dev = dev; 3840 priv->quirk = quirk; 3841 3842 memset(&uart, 0, sizeof(uart)); 3843 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3844 uart.port.uartclk = board->base_baud * 16; 3845 uart.port.irq = get_pci_irq(dev, board); 3846 uart.port.dev = &dev->dev; 3847 3848 for (i = 0; i < nr_ports; i++) { 3849 if (quirk->setup(priv, board, &uart, i)) 3850 break; 3851 3852 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3853 uart.port.iobase, uart.port.irq, uart.port.iotype); 3854 3855 priv->line[i] = serial8250_register_8250_port(&uart); 3856 if (priv->line[i] < 0) { 3857 dev_err(&dev->dev, 3858 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3859 uart.port.iobase, uart.port.irq, 3860 uart.port.iotype, priv->line[i]); 3861 break; 3862 } 3863 } 3864 priv->nr = i; 3865 return priv; 3866 3867 err_deinit: 3868 if (quirk->exit) 3869 quirk->exit(dev); 3870 err_out: 3871 return priv; 3872 } 3873 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3874 3875 void pciserial_remove_ports(struct serial_private *priv) 3876 { 3877 struct pci_serial_quirk *quirk; 3878 int i; 3879 3880 for (i = 0; i < priv->nr; i++) 3881 serial8250_unregister_port(priv->line[i]); 3882 3883 /* 3884 * Find the exit quirks. 3885 */ 3886 quirk = find_quirk(priv->dev); 3887 if (quirk->exit) 3888 quirk->exit(priv->dev); 3889 3890 kfree(priv); 3891 } 3892 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3893 3894 void pciserial_suspend_ports(struct serial_private *priv) 3895 { 3896 int i; 3897 3898 for (i = 0; i < priv->nr; i++) 3899 if (priv->line[i] >= 0) 3900 serial8250_suspend_port(priv->line[i]); 3901 3902 /* 3903 * Ensure that every init quirk is properly torn down 3904 */ 3905 if (priv->quirk->exit) 3906 priv->quirk->exit(priv->dev); 3907 } 3908 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3909 3910 void pciserial_resume_ports(struct serial_private *priv) 3911 { 3912 int i; 3913 3914 /* 3915 * Ensure that the board is correctly configured. 3916 */ 3917 if (priv->quirk->init) 3918 priv->quirk->init(priv->dev); 3919 3920 for (i = 0; i < priv->nr; i++) 3921 if (priv->line[i] >= 0) 3922 serial8250_resume_port(priv->line[i]); 3923 } 3924 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3925 3926 /* 3927 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3928 * to the arrangement of serial ports on a PCI card. 3929 */ 3930 static int 3931 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3932 { 3933 struct pci_serial_quirk *quirk; 3934 struct serial_private *priv; 3935 const struct pciserial_board *board; 3936 struct pciserial_board tmp; 3937 int rc; 3938 3939 quirk = find_quirk(dev); 3940 if (quirk->probe) { 3941 rc = quirk->probe(dev); 3942 if (rc) 3943 return rc; 3944 } 3945 3946 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3947 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3948 ent->driver_data); 3949 return -EINVAL; 3950 } 3951 3952 board = &pci_boards[ent->driver_data]; 3953 3954 rc = pcim_enable_device(dev); 3955 pci_save_state(dev); 3956 if (rc) 3957 return rc; 3958 3959 if (ent->driver_data == pbn_default) { 3960 /* 3961 * Use a copy of the pci_board entry for this; 3962 * avoid changing entries in the table. 3963 */ 3964 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3965 board = &tmp; 3966 3967 /* 3968 * We matched one of our class entries. Try to 3969 * determine the parameters of this board. 3970 */ 3971 rc = serial_pci_guess_board(dev, &tmp); 3972 if (rc) 3973 return rc; 3974 } else { 3975 /* 3976 * We matched an explicit entry. If we are able to 3977 * detect this boards settings with our heuristic, 3978 * then we no longer need this entry. 3979 */ 3980 memcpy(&tmp, &pci_boards[pbn_default], 3981 sizeof(struct pciserial_board)); 3982 rc = serial_pci_guess_board(dev, &tmp); 3983 if (rc == 0 && serial_pci_matches(board, &tmp)) 3984 moan_device("Redundant entry in serial pci_table.", 3985 dev); 3986 } 3987 3988 priv = pciserial_init_ports(dev, board); 3989 if (IS_ERR(priv)) 3990 return PTR_ERR(priv); 3991 3992 pci_set_drvdata(dev, priv); 3993 return 0; 3994 } 3995 3996 static void pciserial_remove_one(struct pci_dev *dev) 3997 { 3998 struct serial_private *priv = pci_get_drvdata(dev); 3999 4000 pciserial_remove_ports(priv); 4001 } 4002 4003 #ifdef CONFIG_PM_SLEEP 4004 static int pciserial_suspend_one(struct device *dev) 4005 { 4006 struct pci_dev *pdev = to_pci_dev(dev); 4007 struct serial_private *priv = pci_get_drvdata(pdev); 4008 4009 if (priv) 4010 pciserial_suspend_ports(priv); 4011 4012 return 0; 4013 } 4014 4015 static int pciserial_resume_one(struct device *dev) 4016 { 4017 struct pci_dev *pdev = to_pci_dev(dev); 4018 struct serial_private *priv = pci_get_drvdata(pdev); 4019 int err; 4020 4021 if (priv) { 4022 /* 4023 * The device may have been disabled. Re-enable it. 4024 */ 4025 err = pci_enable_device(pdev); 4026 /* FIXME: We cannot simply error out here */ 4027 if (err) 4028 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4029 pciserial_resume_ports(priv); 4030 } 4031 return 0; 4032 } 4033 #endif 4034 4035 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4036 pciserial_resume_one); 4037 4038 static struct pci_device_id serial_pci_tbl[] = { 4039 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4040 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4041 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4042 pbn_b2_8_921600 }, 4043 /* Advantech also use 0x3618 and 0xf618 */ 4044 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4045 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4046 pbn_b0_4_921600 }, 4047 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4048 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4049 pbn_b0_4_921600 }, 4050 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4051 PCI_SUBVENDOR_ID_CONNECT_TECH, 4052 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4053 pbn_b1_8_1382400 }, 4054 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4055 PCI_SUBVENDOR_ID_CONNECT_TECH, 4056 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4057 pbn_b1_4_1382400 }, 4058 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4059 PCI_SUBVENDOR_ID_CONNECT_TECH, 4060 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4061 pbn_b1_2_1382400 }, 4062 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4063 PCI_SUBVENDOR_ID_CONNECT_TECH, 4064 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4065 pbn_b1_8_1382400 }, 4066 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4067 PCI_SUBVENDOR_ID_CONNECT_TECH, 4068 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4069 pbn_b1_4_1382400 }, 4070 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4071 PCI_SUBVENDOR_ID_CONNECT_TECH, 4072 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4073 pbn_b1_2_1382400 }, 4074 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4075 PCI_SUBVENDOR_ID_CONNECT_TECH, 4076 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4077 pbn_b1_8_921600 }, 4078 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4079 PCI_SUBVENDOR_ID_CONNECT_TECH, 4080 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4081 pbn_b1_8_921600 }, 4082 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4083 PCI_SUBVENDOR_ID_CONNECT_TECH, 4084 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4085 pbn_b1_4_921600 }, 4086 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4087 PCI_SUBVENDOR_ID_CONNECT_TECH, 4088 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4089 pbn_b1_4_921600 }, 4090 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4091 PCI_SUBVENDOR_ID_CONNECT_TECH, 4092 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4093 pbn_b1_2_921600 }, 4094 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4095 PCI_SUBVENDOR_ID_CONNECT_TECH, 4096 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4097 pbn_b1_8_921600 }, 4098 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4099 PCI_SUBVENDOR_ID_CONNECT_TECH, 4100 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4101 pbn_b1_8_921600 }, 4102 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4103 PCI_SUBVENDOR_ID_CONNECT_TECH, 4104 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4105 pbn_b1_4_921600 }, 4106 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4107 PCI_SUBVENDOR_ID_CONNECT_TECH, 4108 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4109 pbn_b1_2_1250000 }, 4110 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4111 PCI_SUBVENDOR_ID_CONNECT_TECH, 4112 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4113 pbn_b0_2_1843200 }, 4114 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4115 PCI_SUBVENDOR_ID_CONNECT_TECH, 4116 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4117 pbn_b0_4_1843200 }, 4118 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4119 PCI_VENDOR_ID_AFAVLAB, 4120 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4121 pbn_b0_4_1152000 }, 4122 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4123 PCI_SUBVENDOR_ID_CONNECT_TECH, 4124 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4125 pbn_b0_2_1843200_200 }, 4126 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4127 PCI_SUBVENDOR_ID_CONNECT_TECH, 4128 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4129 pbn_b0_4_1843200_200 }, 4130 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4131 PCI_SUBVENDOR_ID_CONNECT_TECH, 4132 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4133 pbn_b0_8_1843200_200 }, 4134 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4135 PCI_SUBVENDOR_ID_CONNECT_TECH, 4136 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4137 pbn_b0_2_1843200_200 }, 4138 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4139 PCI_SUBVENDOR_ID_CONNECT_TECH, 4140 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4141 pbn_b0_4_1843200_200 }, 4142 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4143 PCI_SUBVENDOR_ID_CONNECT_TECH, 4144 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4145 pbn_b0_8_1843200_200 }, 4146 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4147 PCI_SUBVENDOR_ID_CONNECT_TECH, 4148 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4149 pbn_b0_2_1843200_200 }, 4150 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4151 PCI_SUBVENDOR_ID_CONNECT_TECH, 4152 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4153 pbn_b0_4_1843200_200 }, 4154 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4155 PCI_SUBVENDOR_ID_CONNECT_TECH, 4156 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4157 pbn_b0_8_1843200_200 }, 4158 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4159 PCI_SUBVENDOR_ID_CONNECT_TECH, 4160 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4161 pbn_b0_2_1843200_200 }, 4162 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4163 PCI_SUBVENDOR_ID_CONNECT_TECH, 4164 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4165 pbn_b0_4_1843200_200 }, 4166 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4167 PCI_SUBVENDOR_ID_CONNECT_TECH, 4168 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4169 pbn_b0_8_1843200_200 }, 4170 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4171 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4172 0, 0, pbn_exar_ibm_saturn }, 4173 4174 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4176 pbn_b2_bt_1_115200 }, 4177 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4179 pbn_b2_bt_2_115200 }, 4180 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4182 pbn_b2_bt_4_115200 }, 4183 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4185 pbn_b2_bt_2_115200 }, 4186 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4188 pbn_b2_bt_4_115200 }, 4189 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4191 pbn_b2_8_115200 }, 4192 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4194 pbn_b2_8_460800 }, 4195 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4197 pbn_b2_8_115200 }, 4198 4199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4201 pbn_b2_bt_2_115200 }, 4202 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4204 pbn_b2_bt_2_921600 }, 4205 /* 4206 * VScom SPCOM800, from sl@s.pl 4207 */ 4208 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4210 pbn_b2_8_921600 }, 4211 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_b2_4_921600 }, 4214 /* Unknown card - subdevice 0x1584 */ 4215 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4216 PCI_VENDOR_ID_PLX, 4217 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4218 pbn_b2_4_115200 }, 4219 /* Unknown card - subdevice 0x1588 */ 4220 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4221 PCI_VENDOR_ID_PLX, 4222 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4223 pbn_b2_8_115200 }, 4224 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4225 PCI_SUBVENDOR_ID_KEYSPAN, 4226 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4227 pbn_panacom }, 4228 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_panacom4 }, 4231 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4233 pbn_panacom2 }, 4234 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4235 PCI_VENDOR_ID_ESDGMBH, 4236 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4237 pbn_b2_4_115200 }, 4238 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4239 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4240 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4241 pbn_b2_4_460800 }, 4242 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4243 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4244 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4245 pbn_b2_8_460800 }, 4246 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4247 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4248 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4249 pbn_b2_16_460800 }, 4250 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4251 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4252 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4253 pbn_b2_16_460800 }, 4254 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4255 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4256 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4257 pbn_b2_4_460800 }, 4258 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4259 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4260 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4261 pbn_b2_8_460800 }, 4262 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4263 PCI_SUBVENDOR_ID_EXSYS, 4264 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4265 pbn_b2_4_115200 }, 4266 /* 4267 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4268 * (Exoray@isys.ca) 4269 */ 4270 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4271 0x10b5, 0x106a, 0, 0, 4272 pbn_plx_romulus }, 4273 /* 4274 * EndRun Technologies. PCI express device range. 4275 * EndRun PTP/1588 has 2 Native UARTs. 4276 */ 4277 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4279 pbn_endrun_2_4000000 }, 4280 /* 4281 * Quatech cards. These actually have configurable clocks but for 4282 * now we just use the default. 4283 * 4284 * 100 series are RS232, 200 series RS422, 4285 */ 4286 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4288 pbn_b1_4_115200 }, 4289 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4291 pbn_b1_2_115200 }, 4292 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4294 pbn_b2_2_115200 }, 4295 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4297 pbn_b1_2_115200 }, 4298 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4300 pbn_b2_2_115200 }, 4301 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_b1_4_115200 }, 4304 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_b1_8_115200 }, 4307 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4309 pbn_b1_8_115200 }, 4310 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4312 pbn_b1_4_115200 }, 4313 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_b1_2_115200 }, 4316 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4318 pbn_b1_4_115200 }, 4319 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4321 pbn_b1_2_115200 }, 4322 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4324 pbn_b2_4_115200 }, 4325 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4327 pbn_b2_2_115200 }, 4328 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_b2_1_115200 }, 4331 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4333 pbn_b2_4_115200 }, 4334 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4336 pbn_b2_2_115200 }, 4337 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_b2_1_115200 }, 4340 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_b0_8_115200 }, 4343 4344 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4345 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4346 0, 0, 4347 pbn_b0_4_921600 }, 4348 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4349 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4350 0, 0, 4351 pbn_b0_4_1152000 }, 4352 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_b0_bt_2_921600 }, 4355 4356 /* 4357 * The below card is a little controversial since it is the 4358 * subject of a PCI vendor/device ID clash. (See 4359 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4360 * For now just used the hex ID 0x950a. 4361 */ 4362 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4363 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4364 0, 0, pbn_b0_2_115200 }, 4365 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4366 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4367 0, 0, pbn_b0_2_115200 }, 4368 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4370 pbn_b0_2_1130000 }, 4371 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4372 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4373 pbn_b0_1_921600 }, 4374 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b0_4_115200 }, 4377 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b0_bt_2_921600 }, 4380 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b2_8_1152000 }, 4383 4384 /* 4385 * Oxford Semiconductor Inc. Tornado PCI express device range. 4386 */ 4387 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4389 pbn_b0_1_4000000 }, 4390 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b0_1_4000000 }, 4393 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4395 pbn_oxsemi_1_4000000 }, 4396 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4398 pbn_oxsemi_1_4000000 }, 4399 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b0_1_4000000 }, 4402 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b0_1_4000000 }, 4405 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_oxsemi_1_4000000 }, 4408 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_oxsemi_1_4000000 }, 4411 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b0_1_4000000 }, 4414 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b0_1_4000000 }, 4417 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_b0_1_4000000 }, 4420 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_b0_1_4000000 }, 4423 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_oxsemi_2_4000000 }, 4426 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_oxsemi_2_4000000 }, 4429 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_oxsemi_4_4000000 }, 4432 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_oxsemi_4_4000000 }, 4435 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_oxsemi_8_4000000 }, 4438 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_oxsemi_8_4000000 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_oxsemi_1_4000000 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_oxsemi_1_4000000 }, 4447 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_oxsemi_1_4000000 }, 4450 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_oxsemi_1_4000000 }, 4453 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_oxsemi_1_4000000 }, 4456 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_oxsemi_1_4000000 }, 4459 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_oxsemi_1_4000000 }, 4462 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_oxsemi_1_4000000 }, 4465 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_oxsemi_1_4000000 }, 4468 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_oxsemi_1_4000000 }, 4471 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_oxsemi_1_4000000 }, 4474 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4476 pbn_oxsemi_1_4000000 }, 4477 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4479 pbn_oxsemi_1_4000000 }, 4480 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4482 pbn_oxsemi_1_4000000 }, 4483 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_oxsemi_1_4000000 }, 4486 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_oxsemi_1_4000000 }, 4489 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_oxsemi_1_4000000 }, 4492 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_oxsemi_1_4000000 }, 4495 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_oxsemi_1_4000000 }, 4498 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_oxsemi_1_4000000 }, 4501 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_oxsemi_1_4000000 }, 4504 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_oxsemi_1_4000000 }, 4507 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_oxsemi_1_4000000 }, 4510 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_oxsemi_1_4000000 }, 4513 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4515 pbn_oxsemi_1_4000000 }, 4516 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4518 pbn_oxsemi_1_4000000 }, 4519 /* 4520 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4521 */ 4522 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4523 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4524 pbn_oxsemi_1_4000000 }, 4525 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4526 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4527 pbn_oxsemi_2_4000000 }, 4528 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4529 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4530 pbn_oxsemi_4_4000000 }, 4531 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4532 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4533 pbn_oxsemi_8_4000000 }, 4534 4535 /* 4536 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4537 */ 4538 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4539 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4540 pbn_oxsemi_2_4000000 }, 4541 4542 /* 4543 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4544 * from skokodyn@yahoo.com 4545 */ 4546 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4547 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4548 pbn_sbsxrsio }, 4549 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4550 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4551 pbn_sbsxrsio }, 4552 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4553 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4554 pbn_sbsxrsio }, 4555 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4556 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4557 pbn_sbsxrsio }, 4558 4559 /* 4560 * Digitan DS560-558, from jimd@esoft.com 4561 */ 4562 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_b1_1_115200 }, 4565 4566 /* 4567 * Titan Electronic cards 4568 * The 400L and 800L have a custom setup quirk. 4569 */ 4570 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4572 pbn_b0_1_921600 }, 4573 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4575 pbn_b0_2_921600 }, 4576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4578 pbn_b0_4_921600 }, 4579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_b0_4_921600 }, 4582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_b1_1_921600 }, 4585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4587 pbn_b1_bt_2_921600 }, 4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4590 pbn_b0_bt_4_921600 }, 4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_b0_bt_8_921600 }, 4594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4596 pbn_b4_bt_2_921600 }, 4597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b4_bt_4_921600 }, 4600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b4_bt_8_921600 }, 4603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4605 pbn_b0_4_921600 }, 4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_b0_4_921600 }, 4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_b0_4_921600 }, 4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_oxsemi_1_4000000 }, 4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4617 pbn_oxsemi_2_4000000 }, 4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4620 pbn_oxsemi_4_4000000 }, 4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4623 pbn_oxsemi_8_4000000 }, 4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4626 pbn_oxsemi_2_4000000 }, 4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4629 pbn_oxsemi_2_4000000 }, 4630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4632 pbn_b0_bt_2_921600 }, 4633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4635 pbn_b0_4_921600 }, 4636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4638 pbn_b0_4_921600 }, 4639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4641 pbn_b0_4_921600 }, 4642 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4644 pbn_b0_4_921600 }, 4645 4646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_b2_1_460800 }, 4649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_b2_1_460800 }, 4652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b2_1_460800 }, 4655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_b2_bt_2_921600 }, 4658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_b2_bt_2_921600 }, 4661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_b2_bt_2_921600 }, 4664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b2_bt_4_921600 }, 4667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_b2_bt_4_921600 }, 4670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_b2_bt_4_921600 }, 4673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_b0_1_921600 }, 4676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b0_1_921600 }, 4679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_b0_1_921600 }, 4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_b0_bt_2_921600 }, 4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_b0_bt_2_921600 }, 4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_b0_bt_2_921600 }, 4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_b0_bt_4_921600 }, 4694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_b0_bt_4_921600 }, 4697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_b0_bt_4_921600 }, 4700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_b0_bt_8_921600 }, 4703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_b0_bt_8_921600 }, 4706 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_b0_bt_8_921600 }, 4709 4710 /* 4711 * Computone devices submitted by Doug McNash dmcnash@computone.com 4712 */ 4713 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4714 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4715 0, 0, pbn_computone_4 }, 4716 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4717 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4718 0, 0, pbn_computone_8 }, 4719 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4720 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4721 0, 0, pbn_computone_6 }, 4722 4723 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_oxsemi }, 4726 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4727 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4728 pbn_b0_bt_1_921600 }, 4729 4730 /* 4731 * SUNIX (TIMEDIA) 4732 */ 4733 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4734 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4735 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4736 pbn_b0_bt_1_921600 }, 4737 4738 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4739 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4740 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4741 pbn_b0_bt_1_921600 }, 4742 4743 /* 4744 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4745 */ 4746 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4748 pbn_b0_bt_8_115200 }, 4749 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4751 pbn_b0_bt_8_115200 }, 4752 4753 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4755 pbn_b0_bt_2_115200 }, 4756 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4758 pbn_b0_bt_2_115200 }, 4759 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_b0_bt_2_115200 }, 4762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b0_bt_2_115200 }, 4765 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4767 pbn_b0_bt_2_115200 }, 4768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b0_bt_4_460800 }, 4771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4773 pbn_b0_bt_4_460800 }, 4774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4776 pbn_b0_bt_2_460800 }, 4777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b0_bt_2_460800 }, 4780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_2_460800 }, 4783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b0_bt_1_115200 }, 4786 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4788 pbn_b0_bt_1_460800 }, 4789 4790 /* 4791 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4792 * Cards are identified by their subsystem vendor IDs, which 4793 * (in hex) match the model number. 4794 * 4795 * Note that JC140x are RS422/485 cards which require ox950 4796 * ACR = 0x10, and as such are not currently fully supported. 4797 */ 4798 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4799 0x1204, 0x0004, 0, 0, 4800 pbn_b0_4_921600 }, 4801 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4802 0x1208, 0x0004, 0, 0, 4803 pbn_b0_4_921600 }, 4804 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4805 0x1402, 0x0002, 0, 0, 4806 pbn_b0_2_921600 }, */ 4807 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4808 0x1404, 0x0004, 0, 0, 4809 pbn_b0_4_921600 }, */ 4810 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4811 0x1208, 0x0004, 0, 0, 4812 pbn_b0_4_921600 }, 4813 4814 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4815 0x1204, 0x0004, 0, 0, 4816 pbn_b0_4_921600 }, 4817 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4818 0x1208, 0x0004, 0, 0, 4819 pbn_b0_4_921600 }, 4820 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4821 0x1208, 0x0004, 0, 0, 4822 pbn_b0_4_921600 }, 4823 /* 4824 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4825 */ 4826 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4827 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4828 pbn_b1_1_1382400 }, 4829 4830 /* 4831 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4832 */ 4833 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4834 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4835 pbn_b1_1_1382400 }, 4836 4837 /* 4838 * RAStel 2 port modem, gerg@moreton.com.au 4839 */ 4840 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4842 pbn_b2_bt_2_115200 }, 4843 4844 /* 4845 * EKF addition for i960 Boards form EKF with serial port 4846 */ 4847 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4848 0xE4BF, PCI_ANY_ID, 0, 0, 4849 pbn_intel_i960 }, 4850 4851 /* 4852 * Xircom Cardbus/Ethernet combos 4853 */ 4854 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b0_1_115200 }, 4857 /* 4858 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4859 */ 4860 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b0_1_115200 }, 4863 4864 /* 4865 * Untested PCI modems, sent in from various folks... 4866 */ 4867 4868 /* 4869 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4870 */ 4871 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4872 0x1048, 0x1500, 0, 0, 4873 pbn_b1_1_115200 }, 4874 4875 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4876 0xFF00, 0, 0, 0, 4877 pbn_sgi_ioc3 }, 4878 4879 /* 4880 * HP Diva card 4881 */ 4882 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4883 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4884 pbn_b1_1_115200 }, 4885 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4887 pbn_b0_5_115200 }, 4888 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4889 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4890 pbn_b2_1_115200 }, 4891 4892 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4894 pbn_b3_2_115200 }, 4895 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4897 pbn_b3_4_115200 }, 4898 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4900 pbn_b3_8_115200 }, 4901 4902 /* 4903 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4904 */ 4905 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4906 PCI_ANY_ID, PCI_ANY_ID, 4907 0, 4908 0, pbn_exar_XR17C152 }, 4909 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4910 PCI_ANY_ID, PCI_ANY_ID, 4911 0, 4912 0, pbn_exar_XR17C154 }, 4913 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4914 PCI_ANY_ID, PCI_ANY_ID, 4915 0, 4916 0, pbn_exar_XR17C158 }, 4917 /* 4918 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs 4919 */ 4920 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4921 PCI_ANY_ID, PCI_ANY_ID, 4922 0, 4923 0, pbn_exar_XR17V352 }, 4924 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4925 PCI_ANY_ID, PCI_ANY_ID, 4926 0, 4927 0, pbn_exar_XR17V354 }, 4928 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4929 PCI_ANY_ID, PCI_ANY_ID, 4930 0, 4931 0, pbn_exar_XR17V358 }, 4932 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358, 4933 PCI_ANY_ID, PCI_ANY_ID, 4934 0, 4935 0, pbn_exar_XR17V4358 }, 4936 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358, 4937 PCI_ANY_ID, PCI_ANY_ID, 4938 0, 4939 0, pbn_exar_XR17V8358 }, 4940 /* 4941 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4942 */ 4943 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4944 PCI_ANY_ID, PCI_ANY_ID, 4945 0, 4946 0, pbn_pericom_PI7C9X7951 }, 4947 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4948 PCI_ANY_ID, PCI_ANY_ID, 4949 0, 4950 0, pbn_pericom_PI7C9X7952 }, 4951 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4952 PCI_ANY_ID, PCI_ANY_ID, 4953 0, 4954 0, pbn_pericom_PI7C9X7954 }, 4955 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 4956 PCI_ANY_ID, PCI_ANY_ID, 4957 0, 4958 0, pbn_pericom_PI7C9X7958 }, 4959 /* 4960 * ACCES I/O Products quad 4961 */ 4962 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4964 pbn_pericom_PI7C9X7954 }, 4965 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4967 pbn_pericom_PI7C9X7954 }, 4968 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4970 pbn_pericom_PI7C9X7954 }, 4971 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4973 pbn_pericom_PI7C9X7954 }, 4974 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4976 pbn_pericom_PI7C9X7954 }, 4977 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4979 pbn_pericom_PI7C9X7954 }, 4980 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_pericom_PI7C9X7954 }, 4983 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_pericom_PI7C9X7954 }, 4986 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4988 pbn_pericom_PI7C9X7954 }, 4989 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4991 pbn_pericom_PI7C9X7954 }, 4992 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4994 pbn_pericom_PI7C9X7954 }, 4995 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4997 pbn_pericom_PI7C9X7954 }, 4998 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5000 pbn_pericom_PI7C9X7954 }, 5001 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5003 pbn_pericom_PI7C9X7954 }, 5004 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5006 pbn_pericom_PI7C9X7954 }, 5007 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5009 pbn_pericom_PI7C9X7954 }, 5010 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_pericom_PI7C9X7954 }, 5013 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_pericom_PI7C9X7954 }, 5016 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_pericom_PI7C9X7954 }, 5019 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5021 pbn_pericom_PI7C9X7954 }, 5022 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_pericom_PI7C9X7954 }, 5025 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_pericom_PI7C9X7954 }, 5028 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_pericom_PI7C9X7954 }, 5031 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_pericom_PI7C9X7954 }, 5034 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_pericom_PI7C9X7958 }, 5037 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_pericom_PI7C9X7958 }, 5040 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_pericom_PI7C9X7958 }, 5043 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_pericom_PI7C9X7958 }, 5046 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_pericom_PI7C9X7958 }, 5049 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_pericom_PI7C9X7958 }, 5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_pericom_PI7C9X7958 }, 5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_pericom_PI7C9X7958 }, 5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_pericom_PI7C9X7958 }, 5061 /* 5062 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5063 */ 5064 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_b0_1_115200 }, 5067 /* 5068 * ITE 5069 */ 5070 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5071 PCI_ANY_ID, PCI_ANY_ID, 5072 0, 0, 5073 pbn_b1_bt_1_115200 }, 5074 5075 /* 5076 * IntaShield IS-200 5077 */ 5078 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5080 pbn_b2_2_115200 }, 5081 /* 5082 * IntaShield IS-400 5083 */ 5084 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5086 pbn_b2_4_115200 }, 5087 /* 5088 * Perle PCI-RAS cards 5089 */ 5090 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5091 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5092 0, 0, pbn_b2_4_921600 }, 5093 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5094 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5095 0, 0, pbn_b2_8_921600 }, 5096 5097 /* 5098 * Mainpine series cards: Fairly standard layout but fools 5099 * parts of the autodetect in some cases and uses otherwise 5100 * unmatched communications subclasses in the PCI Express case 5101 */ 5102 5103 { /* RockForceDUO */ 5104 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5105 PCI_VENDOR_ID_MAINPINE, 0x0200, 5106 0, 0, pbn_b0_2_115200 }, 5107 { /* RockForceQUATRO */ 5108 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5109 PCI_VENDOR_ID_MAINPINE, 0x0300, 5110 0, 0, pbn_b0_4_115200 }, 5111 { /* RockForceDUO+ */ 5112 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5113 PCI_VENDOR_ID_MAINPINE, 0x0400, 5114 0, 0, pbn_b0_2_115200 }, 5115 { /* RockForceQUATRO+ */ 5116 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5117 PCI_VENDOR_ID_MAINPINE, 0x0500, 5118 0, 0, pbn_b0_4_115200 }, 5119 { /* RockForce+ */ 5120 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5121 PCI_VENDOR_ID_MAINPINE, 0x0600, 5122 0, 0, pbn_b0_2_115200 }, 5123 { /* RockForce+ */ 5124 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5125 PCI_VENDOR_ID_MAINPINE, 0x0700, 5126 0, 0, pbn_b0_4_115200 }, 5127 { /* RockForceOCTO+ */ 5128 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5129 PCI_VENDOR_ID_MAINPINE, 0x0800, 5130 0, 0, pbn_b0_8_115200 }, 5131 { /* RockForceDUO+ */ 5132 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5133 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5134 0, 0, pbn_b0_2_115200 }, 5135 { /* RockForceQUARTRO+ */ 5136 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5137 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5138 0, 0, pbn_b0_4_115200 }, 5139 { /* RockForceOCTO+ */ 5140 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5141 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5142 0, 0, pbn_b0_8_115200 }, 5143 { /* RockForceD1 */ 5144 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5145 PCI_VENDOR_ID_MAINPINE, 0x2000, 5146 0, 0, pbn_b0_1_115200 }, 5147 { /* RockForceF1 */ 5148 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5149 PCI_VENDOR_ID_MAINPINE, 0x2100, 5150 0, 0, pbn_b0_1_115200 }, 5151 { /* RockForceD2 */ 5152 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5153 PCI_VENDOR_ID_MAINPINE, 0x2200, 5154 0, 0, pbn_b0_2_115200 }, 5155 { /* RockForceF2 */ 5156 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5157 PCI_VENDOR_ID_MAINPINE, 0x2300, 5158 0, 0, pbn_b0_2_115200 }, 5159 { /* RockForceD4 */ 5160 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5161 PCI_VENDOR_ID_MAINPINE, 0x2400, 5162 0, 0, pbn_b0_4_115200 }, 5163 { /* RockForceF4 */ 5164 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5165 PCI_VENDOR_ID_MAINPINE, 0x2500, 5166 0, 0, pbn_b0_4_115200 }, 5167 { /* RockForceD8 */ 5168 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5169 PCI_VENDOR_ID_MAINPINE, 0x2600, 5170 0, 0, pbn_b0_8_115200 }, 5171 { /* RockForceF8 */ 5172 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5173 PCI_VENDOR_ID_MAINPINE, 0x2700, 5174 0, 0, pbn_b0_8_115200 }, 5175 { /* IQ Express D1 */ 5176 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5177 PCI_VENDOR_ID_MAINPINE, 0x3000, 5178 0, 0, pbn_b0_1_115200 }, 5179 { /* IQ Express F1 */ 5180 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5181 PCI_VENDOR_ID_MAINPINE, 0x3100, 5182 0, 0, pbn_b0_1_115200 }, 5183 { /* IQ Express D2 */ 5184 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5185 PCI_VENDOR_ID_MAINPINE, 0x3200, 5186 0, 0, pbn_b0_2_115200 }, 5187 { /* IQ Express F2 */ 5188 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5189 PCI_VENDOR_ID_MAINPINE, 0x3300, 5190 0, 0, pbn_b0_2_115200 }, 5191 { /* IQ Express D4 */ 5192 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5193 PCI_VENDOR_ID_MAINPINE, 0x3400, 5194 0, 0, pbn_b0_4_115200 }, 5195 { /* IQ Express F4 */ 5196 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5197 PCI_VENDOR_ID_MAINPINE, 0x3500, 5198 0, 0, pbn_b0_4_115200 }, 5199 { /* IQ Express D8 */ 5200 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5201 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5202 0, 0, pbn_b0_8_115200 }, 5203 { /* IQ Express F8 */ 5204 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5205 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5206 0, 0, pbn_b0_8_115200 }, 5207 5208 5209 /* 5210 * PA Semi PA6T-1682M on-chip UART 5211 */ 5212 { PCI_VENDOR_ID_PASEMI, 0xa004, 5213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5214 pbn_pasemi_1682M }, 5215 5216 /* 5217 * National Instruments 5218 */ 5219 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5221 pbn_b1_16_115200 }, 5222 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5224 pbn_b1_8_115200 }, 5225 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5227 pbn_b1_bt_4_115200 }, 5228 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5230 pbn_b1_bt_2_115200 }, 5231 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5233 pbn_b1_bt_4_115200 }, 5234 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5236 pbn_b1_bt_2_115200 }, 5237 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5239 pbn_b1_16_115200 }, 5240 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5242 pbn_b1_8_115200 }, 5243 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5245 pbn_b1_bt_4_115200 }, 5246 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5248 pbn_b1_bt_2_115200 }, 5249 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5251 pbn_b1_bt_4_115200 }, 5252 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5254 pbn_b1_bt_2_115200 }, 5255 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5257 pbn_ni8430_2 }, 5258 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5260 pbn_ni8430_2 }, 5261 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5263 pbn_ni8430_4 }, 5264 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5266 pbn_ni8430_4 }, 5267 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5269 pbn_ni8430_8 }, 5270 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5272 pbn_ni8430_8 }, 5273 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5275 pbn_ni8430_16 }, 5276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5278 pbn_ni8430_16 }, 5279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5281 pbn_ni8430_2 }, 5282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5284 pbn_ni8430_2 }, 5285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5287 pbn_ni8430_4 }, 5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5290 pbn_ni8430_4 }, 5291 5292 /* 5293 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5294 */ 5295 { PCI_VENDOR_ID_ADDIDATA, 5296 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5297 PCI_ANY_ID, 5298 PCI_ANY_ID, 5299 0, 5300 0, 5301 pbn_b0_4_115200 }, 5302 5303 { PCI_VENDOR_ID_ADDIDATA, 5304 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5305 PCI_ANY_ID, 5306 PCI_ANY_ID, 5307 0, 5308 0, 5309 pbn_b0_2_115200 }, 5310 5311 { PCI_VENDOR_ID_ADDIDATA, 5312 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5313 PCI_ANY_ID, 5314 PCI_ANY_ID, 5315 0, 5316 0, 5317 pbn_b0_1_115200 }, 5318 5319 { PCI_VENDOR_ID_AMCC, 5320 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5321 PCI_ANY_ID, 5322 PCI_ANY_ID, 5323 0, 5324 0, 5325 pbn_b1_8_115200 }, 5326 5327 { PCI_VENDOR_ID_ADDIDATA, 5328 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5329 PCI_ANY_ID, 5330 PCI_ANY_ID, 5331 0, 5332 0, 5333 pbn_b0_4_115200 }, 5334 5335 { PCI_VENDOR_ID_ADDIDATA, 5336 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5337 PCI_ANY_ID, 5338 PCI_ANY_ID, 5339 0, 5340 0, 5341 pbn_b0_2_115200 }, 5342 5343 { PCI_VENDOR_ID_ADDIDATA, 5344 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5345 PCI_ANY_ID, 5346 PCI_ANY_ID, 5347 0, 5348 0, 5349 pbn_b0_1_115200 }, 5350 5351 { PCI_VENDOR_ID_ADDIDATA, 5352 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5353 PCI_ANY_ID, 5354 PCI_ANY_ID, 5355 0, 5356 0, 5357 pbn_b0_4_115200 }, 5358 5359 { PCI_VENDOR_ID_ADDIDATA, 5360 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5361 PCI_ANY_ID, 5362 PCI_ANY_ID, 5363 0, 5364 0, 5365 pbn_b0_2_115200 }, 5366 5367 { PCI_VENDOR_ID_ADDIDATA, 5368 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5369 PCI_ANY_ID, 5370 PCI_ANY_ID, 5371 0, 5372 0, 5373 pbn_b0_1_115200 }, 5374 5375 { PCI_VENDOR_ID_ADDIDATA, 5376 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5377 PCI_ANY_ID, 5378 PCI_ANY_ID, 5379 0, 5380 0, 5381 pbn_b0_8_115200 }, 5382 5383 { PCI_VENDOR_ID_ADDIDATA, 5384 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5385 PCI_ANY_ID, 5386 PCI_ANY_ID, 5387 0, 5388 0, 5389 pbn_ADDIDATA_PCIe_4_3906250 }, 5390 5391 { PCI_VENDOR_ID_ADDIDATA, 5392 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5393 PCI_ANY_ID, 5394 PCI_ANY_ID, 5395 0, 5396 0, 5397 pbn_ADDIDATA_PCIe_2_3906250 }, 5398 5399 { PCI_VENDOR_ID_ADDIDATA, 5400 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5401 PCI_ANY_ID, 5402 PCI_ANY_ID, 5403 0, 5404 0, 5405 pbn_ADDIDATA_PCIe_1_3906250 }, 5406 5407 { PCI_VENDOR_ID_ADDIDATA, 5408 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5409 PCI_ANY_ID, 5410 PCI_ANY_ID, 5411 0, 5412 0, 5413 pbn_ADDIDATA_PCIe_8_3906250 }, 5414 5415 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5416 PCI_VENDOR_ID_IBM, 0x0299, 5417 0, 0, pbn_b0_bt_2_115200 }, 5418 5419 /* 5420 * other NetMos 9835 devices are most likely handled by the 5421 * parport_serial driver, check drivers/parport/parport_serial.c 5422 * before adding them here. 5423 */ 5424 5425 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5426 0xA000, 0x1000, 5427 0, 0, pbn_b0_1_115200 }, 5428 5429 /* the 9901 is a rebranded 9912 */ 5430 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5431 0xA000, 0x1000, 5432 0, 0, pbn_b0_1_115200 }, 5433 5434 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5435 0xA000, 0x1000, 5436 0, 0, pbn_b0_1_115200 }, 5437 5438 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5439 0xA000, 0x1000, 5440 0, 0, pbn_b0_1_115200 }, 5441 5442 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5443 0xA000, 0x1000, 5444 0, 0, pbn_b0_1_115200 }, 5445 5446 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5447 0xA000, 0x3002, 5448 0, 0, pbn_NETMOS9900_2s_115200 }, 5449 5450 /* 5451 * Best Connectivity and Rosewill PCI Multi I/O cards 5452 */ 5453 5454 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5455 0xA000, 0x1000, 5456 0, 0, pbn_b0_1_115200 }, 5457 5458 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5459 0xA000, 0x3002, 5460 0, 0, pbn_b0_bt_2_115200 }, 5461 5462 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5463 0xA000, 0x3004, 5464 0, 0, pbn_b0_bt_4_115200 }, 5465 /* Intel CE4100 */ 5466 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5468 pbn_ce4100_1_115200 }, 5469 5470 /* 5471 * Cronyx Omega PCI 5472 */ 5473 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5475 pbn_omegapci }, 5476 5477 /* 5478 * Broadcom TruManage 5479 */ 5480 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5482 pbn_brcm_trumanage }, 5483 5484 /* 5485 * AgeStar as-prs2-009 5486 */ 5487 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5488 PCI_ANY_ID, PCI_ANY_ID, 5489 0, 0, pbn_b0_bt_2_115200 }, 5490 5491 /* 5492 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5493 * so not listed here. 5494 */ 5495 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5496 PCI_ANY_ID, PCI_ANY_ID, 5497 0, 0, pbn_b0_bt_4_115200 }, 5498 5499 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5500 PCI_ANY_ID, PCI_ANY_ID, 5501 0, 0, pbn_b0_bt_2_115200 }, 5502 5503 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5504 PCI_ANY_ID, PCI_ANY_ID, 5505 0, 0, pbn_b0_bt_4_115200 }, 5506 5507 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5508 PCI_ANY_ID, PCI_ANY_ID, 5509 0, 0, pbn_wch382_2 }, 5510 5511 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5512 PCI_ANY_ID, PCI_ANY_ID, 5513 0, 0, pbn_wch384_4 }, 5514 5515 /* 5516 * Commtech, Inc. Fastcom adapters 5517 */ 5518 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5519 PCI_ANY_ID, PCI_ANY_ID, 5520 0, 5521 0, pbn_b0_2_1152000_200 }, 5522 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5523 PCI_ANY_ID, PCI_ANY_ID, 5524 0, 5525 0, pbn_b0_4_1152000_200 }, 5526 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5527 PCI_ANY_ID, PCI_ANY_ID, 5528 0, 5529 0, pbn_b0_4_1152000_200 }, 5530 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5531 PCI_ANY_ID, PCI_ANY_ID, 5532 0, 5533 0, pbn_b0_8_1152000_200 }, 5534 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5535 PCI_ANY_ID, PCI_ANY_ID, 5536 0, 5537 0, pbn_exar_XR17V352 }, 5538 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5539 PCI_ANY_ID, PCI_ANY_ID, 5540 0, 5541 0, pbn_exar_XR17V354 }, 5542 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5543 PCI_ANY_ID, PCI_ANY_ID, 5544 0, 5545 0, pbn_exar_XR17V358 }, 5546 5547 /* Fintek PCI serial cards */ 5548 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5549 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5550 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5551 5552 /* 5553 * These entries match devices with class COMMUNICATION_SERIAL, 5554 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5555 */ 5556 { PCI_ANY_ID, PCI_ANY_ID, 5557 PCI_ANY_ID, PCI_ANY_ID, 5558 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5559 0xffff00, pbn_default }, 5560 { PCI_ANY_ID, PCI_ANY_ID, 5561 PCI_ANY_ID, PCI_ANY_ID, 5562 PCI_CLASS_COMMUNICATION_MODEM << 8, 5563 0xffff00, pbn_default }, 5564 { PCI_ANY_ID, PCI_ANY_ID, 5565 PCI_ANY_ID, PCI_ANY_ID, 5566 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5567 0xffff00, pbn_default }, 5568 { 0, } 5569 }; 5570 5571 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5572 pci_channel_state_t state) 5573 { 5574 struct serial_private *priv = pci_get_drvdata(dev); 5575 5576 if (state == pci_channel_io_perm_failure) 5577 return PCI_ERS_RESULT_DISCONNECT; 5578 5579 if (priv) 5580 pciserial_suspend_ports(priv); 5581 5582 pci_disable_device(dev); 5583 5584 return PCI_ERS_RESULT_NEED_RESET; 5585 } 5586 5587 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5588 { 5589 int rc; 5590 5591 rc = pci_enable_device(dev); 5592 5593 if (rc) 5594 return PCI_ERS_RESULT_DISCONNECT; 5595 5596 pci_restore_state(dev); 5597 pci_save_state(dev); 5598 5599 return PCI_ERS_RESULT_RECOVERED; 5600 } 5601 5602 static void serial8250_io_resume(struct pci_dev *dev) 5603 { 5604 struct serial_private *priv = pci_get_drvdata(dev); 5605 5606 if (priv) 5607 pciserial_resume_ports(priv); 5608 } 5609 5610 static const struct pci_error_handlers serial8250_err_handler = { 5611 .error_detected = serial8250_io_error_detected, 5612 .slot_reset = serial8250_io_slot_reset, 5613 .resume = serial8250_io_resume, 5614 }; 5615 5616 static struct pci_driver serial_pci_driver = { 5617 .name = "serial", 5618 .probe = pciserial_init_one, 5619 .remove = pciserial_remove_one, 5620 .driver = { 5621 .pm = &pciserial_pm_ops, 5622 }, 5623 .id_table = serial_pci_tbl, 5624 .err_handler = &serial8250_err_handler, 5625 }; 5626 5627 module_pci_driver(serial_pci_driver); 5628 5629 MODULE_LICENSE("GPL"); 5630 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5631 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5632