1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 28 /* 29 * init function returns: 30 * > 0 - number of ports 31 * = 0 - use board->num_ports 32 * < 0 - error 33 */ 34 struct pci_serial_quirk { 35 u32 vendor; 36 u32 device; 37 u32 subvendor; 38 u32 subdevice; 39 int (*probe)(struct pci_dev *dev); 40 int (*init)(struct pci_dev *dev); 41 int (*setup)(struct serial_private *, 42 const struct pciserial_board *, 43 struct uart_8250_port *, int); 44 void (*exit)(struct pci_dev *dev); 45 }; 46 47 struct f815xxa_data { 48 spinlock_t lock; 49 int idx; 50 }; 51 52 struct serial_private { 53 struct pci_dev *dev; 54 unsigned int nr; 55 struct pci_serial_quirk *quirk; 56 const struct pciserial_board *board; 57 int line[]; 58 }; 59 60 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 61 62 static const struct pci_device_id pci_use_msi[] = { 63 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 64 0xA000, 0x1000) }, 65 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 66 0xA000, 0x1000) }, 67 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 68 0xA000, 0x1000) }, 69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 70 PCI_ANY_ID, PCI_ANY_ID) }, 71 { } 72 }; 73 74 static int pci_default_setup(struct serial_private*, 75 const struct pciserial_board*, struct uart_8250_port *, int); 76 77 static void moan_device(const char *str, struct pci_dev *dev) 78 { 79 pci_err(dev, "%s\n" 80 "Please send the output of lspci -vv, this\n" 81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 82 "manufacturer and name of serial board or\n" 83 "modem board to <linux-serial@vger.kernel.org>.\n", 84 str, dev->vendor, dev->device, 85 dev->subsystem_vendor, dev->subsystem_device); 86 } 87 88 static int 89 setup_port(struct serial_private *priv, struct uart_8250_port *port, 90 u8 bar, unsigned int offset, int regshift) 91 { 92 struct pci_dev *dev = priv->dev; 93 94 if (bar >= PCI_STD_NUM_BARS) 95 return -EINVAL; 96 97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 99 return -ENOMEM; 100 101 port->port.iotype = UPIO_MEM; 102 port->port.iobase = 0; 103 port->port.mapbase = pci_resource_start(dev, bar) + offset; 104 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 105 port->port.regshift = regshift; 106 } else { 107 port->port.iotype = UPIO_PORT; 108 port->port.iobase = pci_resource_start(dev, bar) + offset; 109 port->port.mapbase = 0; 110 port->port.membase = NULL; 111 port->port.regshift = 0; 112 } 113 return 0; 114 } 115 116 /* 117 * ADDI-DATA GmbH communication cards <info@addi-data.com> 118 */ 119 static int addidata_apci7800_setup(struct serial_private *priv, 120 const struct pciserial_board *board, 121 struct uart_8250_port *port, int idx) 122 { 123 unsigned int bar = 0, offset = board->first_offset; 124 bar = FL_GET_BASE(board->flags); 125 126 if (idx < 2) { 127 offset += idx * board->uart_offset; 128 } else if ((idx >= 2) && (idx < 4)) { 129 bar += 1; 130 offset += ((idx - 2) * board->uart_offset); 131 } else if ((idx >= 4) && (idx < 6)) { 132 bar += 2; 133 offset += ((idx - 4) * board->uart_offset); 134 } else if (idx >= 6) { 135 bar += 3; 136 offset += ((idx - 6) * board->uart_offset); 137 } 138 139 return setup_port(priv, port, bar, offset, board->reg_shift); 140 } 141 142 /* 143 * AFAVLAB uses a different mixture of BARs and offsets 144 * Not that ugly ;) -- HW 145 */ 146 static int 147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 148 struct uart_8250_port *port, int idx) 149 { 150 unsigned int bar, offset = board->first_offset; 151 152 bar = FL_GET_BASE(board->flags); 153 if (idx < 4) 154 bar += idx; 155 else { 156 bar = 4; 157 offset += (idx - 4) * board->uart_offset; 158 } 159 160 return setup_port(priv, port, bar, offset, board->reg_shift); 161 } 162 163 /* 164 * HP's Remote Management Console. The Diva chip came in several 165 * different versions. N-class, L2000 and A500 have two Diva chips, each 166 * with 3 UARTs (the third UART on the second chip is unused). Superdome 167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 168 * one Diva chip, but it has been expanded to 5 UARTs. 169 */ 170 static int pci_hp_diva_init(struct pci_dev *dev) 171 { 172 int rc = 0; 173 174 switch (dev->subsystem_device) { 175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 178 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 179 rc = 3; 180 break; 181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 182 rc = 2; 183 break; 184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 185 rc = 4; 186 break; 187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 189 rc = 1; 190 break; 191 } 192 193 return rc; 194 } 195 196 /* 197 * HP's Diva chip puts the 4th/5th serial port further out, and 198 * some serial ports are supposed to be hidden on certain models. 199 */ 200 static int 201 pci_hp_diva_setup(struct serial_private *priv, 202 const struct pciserial_board *board, 203 struct uart_8250_port *port, int idx) 204 { 205 unsigned int offset = board->first_offset; 206 unsigned int bar = FL_GET_BASE(board->flags); 207 208 switch (priv->dev->subsystem_device) { 209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 210 if (idx == 3) 211 idx++; 212 break; 213 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 214 if (idx > 0) 215 idx++; 216 if (idx > 2) 217 idx++; 218 break; 219 } 220 if (idx > 2) 221 offset = 0x18; 222 223 offset += idx * board->uart_offset; 224 225 return setup_port(priv, port, bar, offset, board->reg_shift); 226 } 227 228 /* 229 * Added for EKF Intel i960 serial boards 230 */ 231 static int pci_inteli960ni_init(struct pci_dev *dev) 232 { 233 u32 oldval; 234 235 if (!(dev->subsystem_device & 0x1000)) 236 return -ENODEV; 237 238 /* is firmware started? */ 239 pci_read_config_dword(dev, 0x44, &oldval); 240 if (oldval == 0x00001000L) { /* RESET value */ 241 pci_dbg(dev, "Local i960 firmware missing\n"); 242 return -ENODEV; 243 } 244 return 0; 245 } 246 247 /* 248 * Some PCI serial cards using the PLX 9050 PCI interface chip require 249 * that the card interrupt be explicitly enabled or disabled. This 250 * seems to be mainly needed on card using the PLX which also use I/O 251 * mapped memory. 252 */ 253 static int pci_plx9050_init(struct pci_dev *dev) 254 { 255 u8 irq_config; 256 void __iomem *p; 257 258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 259 moan_device("no memory in bar 0", dev); 260 return 0; 261 } 262 263 irq_config = 0x41; 264 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 266 irq_config = 0x43; 267 268 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 270 /* 271 * As the megawolf cards have the int pins active 272 * high, and have 2 UART chips, both ints must be 273 * enabled on the 9050. Also, the UARTS are set in 274 * 16450 mode by default, so we have to enable the 275 * 16C950 'enhanced' mode so that we can use the 276 * deep FIFOs 277 */ 278 irq_config = 0x5b; 279 /* 280 * enable/disable interrupts 281 */ 282 p = ioremap(pci_resource_start(dev, 0), 0x80); 283 if (p == NULL) 284 return -ENOMEM; 285 writel(irq_config, p + 0x4c); 286 287 /* 288 * Read the register back to ensure that it took effect. 289 */ 290 readl(p + 0x4c); 291 iounmap(p); 292 293 return 0; 294 } 295 296 static void pci_plx9050_exit(struct pci_dev *dev) 297 { 298 u8 __iomem *p; 299 300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 301 return; 302 303 /* 304 * disable interrupts 305 */ 306 p = ioremap(pci_resource_start(dev, 0), 0x80); 307 if (p != NULL) { 308 writel(0, p + 0x4c); 309 310 /* 311 * Read the register back to ensure that it took effect. 312 */ 313 readl(p + 0x4c); 314 iounmap(p); 315 } 316 } 317 318 #define NI8420_INT_ENABLE_REG 0x38 319 #define NI8420_INT_ENABLE_BIT 0x2000 320 321 static void pci_ni8420_exit(struct pci_dev *dev) 322 { 323 void __iomem *p; 324 unsigned int bar = 0; 325 326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 327 moan_device("no memory in bar", dev); 328 return; 329 } 330 331 p = pci_ioremap_bar(dev, bar); 332 if (p == NULL) 333 return; 334 335 /* Disable the CPU Interrupt */ 336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 337 p + NI8420_INT_ENABLE_REG); 338 iounmap(p); 339 } 340 341 342 /* MITE registers */ 343 #define MITE_IOWBSR1 0xc4 344 #define MITE_IOWCR1 0xf4 345 #define MITE_LCIMR1 0x08 346 #define MITE_LCIMR2 0x10 347 348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 349 350 static void pci_ni8430_exit(struct pci_dev *dev) 351 { 352 void __iomem *p; 353 unsigned int bar = 0; 354 355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 356 moan_device("no memory in bar", dev); 357 return; 358 } 359 360 p = pci_ioremap_bar(dev, bar); 361 if (p == NULL) 362 return; 363 364 /* Disable the CPU Interrupt */ 365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 366 iounmap(p); 367 } 368 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 370 static int 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 372 struct uart_8250_port *port, int idx) 373 { 374 unsigned int bar, offset = board->first_offset; 375 376 bar = 0; 377 378 if (idx < 4) { 379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 380 offset += idx * board->uart_offset; 381 } else if (idx < 8) { 382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 383 offset += idx * board->uart_offset + 0xC00; 384 } else /* we have only 8 ports on PMC-OCTALPRO */ 385 return 1; 386 387 return setup_port(priv, port, bar, offset, board->reg_shift); 388 } 389 390 /* 391 * This does initialization for PMC OCTALPRO cards: 392 * maps the device memory, resets the UARTs (needed, bc 393 * if the module is removed and inserted again, the card 394 * is in the sleep mode) and enables global interrupt. 395 */ 396 397 /* global control register offset for SBS PMC-OctalPro */ 398 #define OCT_REG_CR_OFF 0x500 399 400 static int sbs_init(struct pci_dev *dev) 401 { 402 u8 __iomem *p; 403 404 p = pci_ioremap_bar(dev, 0); 405 406 if (p == NULL) 407 return -ENOMEM; 408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 409 writeb(0x10, p + OCT_REG_CR_OFF); 410 udelay(50); 411 writeb(0x0, p + OCT_REG_CR_OFF); 412 413 /* Set bit-2 (INTENABLE) of Control Register */ 414 writeb(0x4, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 417 return 0; 418 } 419 420 /* 421 * Disables the global interrupt of PMC-OctalPro 422 */ 423 424 static void sbs_exit(struct pci_dev *dev) 425 { 426 u8 __iomem *p; 427 428 p = pci_ioremap_bar(dev, 0); 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 430 if (p != NULL) 431 writeb(0, p + OCT_REG_CR_OFF); 432 iounmap(p); 433 } 434 435 /* 436 * SIIG serial cards have an PCI interface chip which also controls 437 * the UART clocking frequency. Each UART can be clocked independently 438 * (except cards equipped with 4 UARTs) and initial clocking settings 439 * are stored in the EEPROM chip. It can cause problems because this 440 * version of serial driver doesn't support differently clocked UART's 441 * on single PCI card. To prevent this, initialization functions set 442 * high frequency clocking for all UART's on given card. It is safe (I 443 * hope) because it doesn't touch EEPROM settings to prevent conflicts 444 * with other OSes (like M$ DOS). 445 * 446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 447 * 448 * There is two family of SIIG serial cards with different PCI 449 * interface chip and different configuration methods: 450 * - 10x cards have control registers in IO and/or memory space; 451 * - 20x cards have control registers in standard PCI configuration space. 452 * 453 * Note: all 10x cards have PCI device ids 0x10.. 454 * all 20x cards have PCI device ids 0x20.. 455 * 456 * There are also Quartet Serial cards which use Oxford Semiconductor 457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 458 * 459 * Note: some SIIG cards are probed by the parport_serial object. 460 */ 461 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 464 465 static int pci_siig10x_init(struct pci_dev *dev) 466 { 467 u16 data; 468 void __iomem *p; 469 470 switch (dev->device & 0xfff8) { 471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 472 data = 0xffdf; 473 break; 474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 475 data = 0xf7ff; 476 break; 477 default: /* 1S1P, 4S */ 478 data = 0xfffb; 479 break; 480 } 481 482 p = ioremap(pci_resource_start(dev, 0), 0x80); 483 if (p == NULL) 484 return -ENOMEM; 485 486 writew(readw(p + 0x28) & data, p + 0x28); 487 readw(p + 0x28); 488 iounmap(p); 489 return 0; 490 } 491 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 494 495 static int pci_siig20x_init(struct pci_dev *dev) 496 { 497 u8 data; 498 499 /* Change clock frequency for the first UART. */ 500 pci_read_config_byte(dev, 0x6f, &data); 501 pci_write_config_byte(dev, 0x6f, data & 0xef); 502 503 /* If this card has 2 UART, we have to do the same with second UART. */ 504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 506 pci_read_config_byte(dev, 0x73, &data); 507 pci_write_config_byte(dev, 0x73, data & 0xef); 508 } 509 return 0; 510 } 511 512 static int pci_siig_init(struct pci_dev *dev) 513 { 514 unsigned int type = dev->device & 0xff00; 515 516 if (type == 0x1000) 517 return pci_siig10x_init(dev); 518 if (type == 0x2000) 519 return pci_siig20x_init(dev); 520 521 moan_device("Unknown SIIG card", dev); 522 return -ENODEV; 523 } 524 525 static int pci_siig_setup(struct serial_private *priv, 526 const struct pciserial_board *board, 527 struct uart_8250_port *port, int idx) 528 { 529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 530 531 if (idx > 3) { 532 bar = 4; 533 offset = (idx - 4) * 8; 534 } 535 536 return setup_port(priv, port, bar, offset, 0); 537 } 538 539 /* 540 * Timedia has an explosion of boards, and to avoid the PCI table from 541 * growing *huge*, we use this function to collapse some 70 entries 542 * in the PCI table into one, for sanity's and compactness's sake. 543 */ 544 static const unsigned short timedia_single_port[] = { 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 546 }; 547 548 static const unsigned short timedia_dual_port[] = { 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 553 0xD079, 0 554 }; 555 556 static const unsigned short timedia_quad_port[] = { 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 560 0xB157, 0 561 }; 562 563 static const unsigned short timedia_eight_port[] = { 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 566 }; 567 568 static const struct timedia_struct { 569 int num; 570 const unsigned short *ids; 571 } timedia_data[] = { 572 { 1, timedia_single_port }, 573 { 2, timedia_dual_port }, 574 { 4, timedia_quad_port }, 575 { 8, timedia_eight_port } 576 }; 577 578 /* 579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 580 * listing them individually, this driver merely grabs them all with 581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 582 * and should be left free to be claimed by parport_serial instead. 583 */ 584 static int pci_timedia_probe(struct pci_dev *dev) 585 { 586 /* 587 * Check the third digit of the subdevice ID 588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 589 */ 590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 591 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 592 dev->subsystem_device); 593 return -ENODEV; 594 } 595 596 return 0; 597 } 598 599 static int pci_timedia_init(struct pci_dev *dev) 600 { 601 const unsigned short *ids; 602 int i, j; 603 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 605 ids = timedia_data[i].ids; 606 for (j = 0; ids[j]; j++) 607 if (dev->subsystem_device == ids[j]) 608 return timedia_data[i].num; 609 } 610 return 0; 611 } 612 613 /* 614 * Timedia/SUNIX uses a mixture of BARs and offsets 615 * Ugh, this is ugly as all hell --- TYT 616 */ 617 static int 618 pci_timedia_setup(struct serial_private *priv, 619 const struct pciserial_board *board, 620 struct uart_8250_port *port, int idx) 621 { 622 unsigned int bar = 0, offset = board->first_offset; 623 624 switch (idx) { 625 case 0: 626 bar = 0; 627 break; 628 case 1: 629 offset = board->uart_offset; 630 bar = 0; 631 break; 632 case 2: 633 bar = 1; 634 break; 635 case 3: 636 offset = board->uart_offset; 637 fallthrough; 638 case 4: /* BAR 2 */ 639 case 5: /* BAR 3 */ 640 case 6: /* BAR 4 */ 641 case 7: /* BAR 5 */ 642 bar = idx - 2; 643 } 644 645 return setup_port(priv, port, bar, offset, board->reg_shift); 646 } 647 648 /* 649 * Some Titan cards are also a little weird 650 */ 651 static int 652 titan_400l_800l_setup(struct serial_private *priv, 653 const struct pciserial_board *board, 654 struct uart_8250_port *port, int idx) 655 { 656 unsigned int bar, offset = board->first_offset; 657 658 switch (idx) { 659 case 0: 660 bar = 1; 661 break; 662 case 1: 663 bar = 2; 664 break; 665 default: 666 bar = 4; 667 offset = (idx - 2) * board->uart_offset; 668 } 669 670 return setup_port(priv, port, bar, offset, board->reg_shift); 671 } 672 673 static int pci_xircom_init(struct pci_dev *dev) 674 { 675 msleep(100); 676 return 0; 677 } 678 679 static int pci_ni8420_init(struct pci_dev *dev) 680 { 681 void __iomem *p; 682 unsigned int bar = 0; 683 684 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 685 moan_device("no memory in bar", dev); 686 return 0; 687 } 688 689 p = pci_ioremap_bar(dev, bar); 690 if (p == NULL) 691 return -ENOMEM; 692 693 /* Enable CPU Interrupt */ 694 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 695 p + NI8420_INT_ENABLE_REG); 696 697 iounmap(p); 698 return 0; 699 } 700 701 #define MITE_IOWBSR1_WSIZE 0xa 702 #define MITE_IOWBSR1_WIN_OFFSET 0x800 703 #define MITE_IOWBSR1_WENAB (1 << 7) 704 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 705 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 706 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 707 708 static int pci_ni8430_init(struct pci_dev *dev) 709 { 710 void __iomem *p; 711 struct pci_bus_region region; 712 u32 device_window; 713 unsigned int bar = 0; 714 715 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 716 moan_device("no memory in bar", dev); 717 return 0; 718 } 719 720 p = pci_ioremap_bar(dev, bar); 721 if (p == NULL) 722 return -ENOMEM; 723 724 /* 725 * Set device window address and size in BAR0, while acknowledging that 726 * the resource structure may contain a translated address that differs 727 * from the address the device responds to. 728 */ 729 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 730 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 732 writel(device_window, p + MITE_IOWBSR1); 733 734 /* Set window access to go to RAMSEL IO address space */ 735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 736 p + MITE_IOWCR1); 737 738 /* Enable IO Bus Interrupt 0 */ 739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 740 741 /* Enable CPU Interrupt */ 742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 743 744 iounmap(p); 745 return 0; 746 } 747 748 /* UART Port Control Register */ 749 #define NI8430_PORTCON 0x0f 750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 751 752 static int 753 pci_ni8430_setup(struct serial_private *priv, 754 const struct pciserial_board *board, 755 struct uart_8250_port *port, int idx) 756 { 757 struct pci_dev *dev = priv->dev; 758 void __iomem *p; 759 unsigned int bar, offset = board->first_offset; 760 761 if (idx >= board->num_ports) 762 return 1; 763 764 bar = FL_GET_BASE(board->flags); 765 offset += idx * board->uart_offset; 766 767 p = pci_ioremap_bar(dev, bar); 768 if (!p) 769 return -ENOMEM; 770 771 /* enable the transceiver */ 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 773 p + offset + NI8430_PORTCON); 774 775 iounmap(p); 776 777 return setup_port(priv, port, bar, offset, board->reg_shift); 778 } 779 780 static int pci_netmos_9900_setup(struct serial_private *priv, 781 const struct pciserial_board *board, 782 struct uart_8250_port *port, int idx) 783 { 784 unsigned int bar; 785 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 788 /* netmos apparently orders BARs by datasheet layout, so serial 789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 790 */ 791 bar = 3 * idx; 792 793 return setup_port(priv, port, bar, 0, board->reg_shift); 794 } 795 796 return pci_default_setup(priv, board, port, idx); 797 } 798 799 /* the 99xx series comes with a range of device IDs and a variety 800 * of capabilities: 801 * 802 * 9900 has varying capabilities and can cascade to sub-controllers 803 * (cascading should be purely internal) 804 * 9904 is hardwired with 4 serial ports 805 * 9912 and 9922 are hardwired with 2 serial ports 806 */ 807 static int pci_netmos_9900_numports(struct pci_dev *dev) 808 { 809 unsigned int c = dev->class; 810 unsigned int pi; 811 unsigned short sub_serports; 812 813 pi = c & 0xff; 814 815 if (pi == 2) 816 return 1; 817 818 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 819 /* two possibilities: 0x30ps encodes number of parallel and 820 * serial ports, or 0x1000 indicates *something*. This is not 821 * immediately obvious, since the 2s1p+4s configuration seems 822 * to offer all functionality on functions 0..2, while still 823 * advertising the same function 3 as the 4s+2s1p config. 824 */ 825 sub_serports = dev->subsystem_device & 0xf; 826 if (sub_serports > 0) 827 return sub_serports; 828 829 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 830 return 0; 831 } 832 833 moan_device("unknown NetMos/Mostech program interface", dev); 834 return 0; 835 } 836 837 static int pci_netmos_init(struct pci_dev *dev) 838 { 839 /* subdevice 0x00PS means <P> parallel, <S> serial */ 840 unsigned int num_serial = dev->subsystem_device & 0xf; 841 842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 843 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 844 return 0; 845 846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 847 dev->subsystem_device == 0x0299) 848 return 0; 849 850 switch (dev->device) { /* FALLTHROUGH on all */ 851 case PCI_DEVICE_ID_NETMOS_9904: 852 case PCI_DEVICE_ID_NETMOS_9912: 853 case PCI_DEVICE_ID_NETMOS_9922: 854 case PCI_DEVICE_ID_NETMOS_9900: 855 num_serial = pci_netmos_9900_numports(dev); 856 break; 857 858 default: 859 break; 860 } 861 862 if (num_serial == 0) { 863 moan_device("unknown NetMos/Mostech device", dev); 864 return -ENODEV; 865 } 866 867 return num_serial; 868 } 869 870 /* 871 * These chips are available with optionally one parallel port and up to 872 * two serial ports. Unfortunately they all have the same product id. 873 * 874 * Basic configuration is done over a region of 32 I/O ports. The base 875 * ioport is called INTA or INTC, depending on docs/other drivers. 876 * 877 * The region of the 32 I/O ports is configured in POSIO0R... 878 */ 879 880 /* registers */ 881 #define ITE_887x_MISCR 0x9c 882 #define ITE_887x_INTCBAR 0x78 883 #define ITE_887x_UARTBAR 0x7c 884 #define ITE_887x_PS0BAR 0x10 885 #define ITE_887x_POSIO0 0x60 886 887 /* I/O space size */ 888 #define ITE_887x_IOSIZE 32 889 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 890 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 891 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 892 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 893 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 894 #define ITE_887x_POSIO_SPEED (3 << 29) 895 /* enable IO_Space bit */ 896 #define ITE_887x_POSIO_ENABLE (1 << 31) 897 898 /* inta_addr are the configuration addresses of the ITE */ 899 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 900 static int pci_ite887x_init(struct pci_dev *dev) 901 { 902 int ret, i, type; 903 struct resource *iobase = NULL; 904 u32 miscr, uartbar, ioport; 905 906 /* search for the base-ioport */ 907 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 908 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 909 "ite887x"); 910 if (iobase != NULL) { 911 /* write POSIO0R - speed | size | ioport */ 912 pci_write_config_dword(dev, ITE_887x_POSIO0, 913 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 914 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 915 /* write INTCBAR - ioport */ 916 pci_write_config_dword(dev, ITE_887x_INTCBAR, 917 inta_addr[i]); 918 ret = inb(inta_addr[i]); 919 if (ret != 0xff) { 920 /* ioport connected */ 921 break; 922 } 923 release_region(iobase->start, ITE_887x_IOSIZE); 924 } 925 } 926 927 if (i == ARRAY_SIZE(inta_addr)) { 928 pci_err(dev, "could not find iobase\n"); 929 return -ENODEV; 930 } 931 932 /* start of undocumented type checking (see parport_pc.c) */ 933 type = inb(iobase->start + 0x18) & 0x0f; 934 935 switch (type) { 936 case 0x2: /* ITE8871 (1P) */ 937 case 0xa: /* ITE8875 (1P) */ 938 ret = 0; 939 break; 940 case 0xe: /* ITE8872 (2S1P) */ 941 ret = 2; 942 break; 943 case 0x6: /* ITE8873 (1S) */ 944 ret = 1; 945 break; 946 case 0x8: /* ITE8874 (2S) */ 947 ret = 2; 948 break; 949 default: 950 moan_device("Unknown ITE887x", dev); 951 ret = -ENODEV; 952 } 953 954 /* configure all serial ports */ 955 for (i = 0; i < ret; i++) { 956 /* read the I/O port from the device */ 957 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 958 &ioport); 959 ioport &= 0x0000FF00; /* the actual base address */ 960 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 961 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 962 ITE_887x_POSIO_IOSIZE_8 | ioport); 963 964 /* write the ioport to the UARTBAR */ 965 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 966 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 967 uartbar |= (ioport << (16 * i)); /* set the ioport */ 968 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 969 970 /* get current config */ 971 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 972 /* disable interrupts (UARTx_Routing[3:0]) */ 973 miscr &= ~(0xf << (12 - 4 * i)); 974 /* activate the UART (UARTx_En) */ 975 miscr |= 1 << (23 - i); 976 /* write new config with activated UART */ 977 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 978 } 979 980 if (ret <= 0) { 981 /* the device has no UARTs if we get here */ 982 release_region(iobase->start, ITE_887x_IOSIZE); 983 } 984 985 return ret; 986 } 987 988 static void pci_ite887x_exit(struct pci_dev *dev) 989 { 990 u32 ioport; 991 /* the ioport is bit 0-15 in POSIO0R */ 992 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 993 ioport &= 0xffff; 994 release_region(ioport, ITE_887x_IOSIZE); 995 } 996 997 /* 998 * Oxford Semiconductor Inc. 999 * Check if an OxSemi device is part of the Tornado range of devices. 1000 */ 1001 #define PCI_VENDOR_ID_ENDRUN 0x7401 1002 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1003 1004 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1005 { 1006 /* OxSemi Tornado devices are all 0xCxxx */ 1007 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1008 (dev->device & 0xf000) != 0xc000) 1009 return false; 1010 1011 /* EndRun devices are all 0xExxx */ 1012 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1013 (dev->device & 0xf000) != 0xe000) 1014 return false; 1015 1016 return true; 1017 } 1018 1019 /* 1020 * Determine the number of ports available on a Tornado device. 1021 */ 1022 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1023 { 1024 u8 __iomem *p; 1025 unsigned long deviceID; 1026 unsigned int number_uarts = 0; 1027 1028 if (!pci_oxsemi_tornado_p(dev)) 1029 return 0; 1030 1031 p = pci_iomap(dev, 0, 5); 1032 if (p == NULL) 1033 return -ENOMEM; 1034 1035 deviceID = ioread32(p); 1036 /* Tornado device */ 1037 if (deviceID == 0x07000200) { 1038 number_uarts = ioread8(p + 4); 1039 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1040 number_uarts, 1041 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1042 "EndRun" : "Oxford"); 1043 } 1044 pci_iounmap(dev, p); 1045 return number_uarts; 1046 } 1047 1048 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1049 #define OXSEMI_TORNADO_TCR_MASK 0xf 1050 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1051 #define OXSEMI_TORNADO_CPR_MIN 0x008 1052 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1053 1054 /* 1055 * Determine the oversampling rate, the clock prescaler, and the clock 1056 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1057 * which is four times the baud base, and the prescaler increments in 1058 * steps of 1/8. Therefore to make calculations on integers we need 1059 * to use a scaled clock rate, which is the baud base multiplied by 32 1060 * (or our assumed UART clock rate multiplied by 2). 1061 * 1062 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1063 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1064 * values between 1.000 and 63.875 inclusive (operation for values from 1065 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1066 * unsigned 16-bit integer. 1067 * 1068 * For the most accurate baud rate we use a table of predetermined 1069 * oversampling rates and clock prescalers that records all possible 1070 * products of the two parameters in the range from 4 up to 255 inclusive, 1071 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1072 * by 8. The table is sorted by the decreasing value of the oversampling 1073 * rate and ties are resolved by sorting by the decreasing value of the 1074 * product. This way preference is given to higher oversampling rates. 1075 * 1076 * We iterate over the table and choose the product of an oversampling 1077 * rate and a clock prescaler that gives the lowest integer division 1078 * result deviation, or if an exact integer divider is found we stop 1079 * looking for it right away. We do some fixup if the resulting clock 1080 * divisor required would be out of its unsigned 16-bit integer range. 1081 * 1082 * Finally we abuse the supposed fractional part returned to encode the 1083 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1084 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1085 */ 1086 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1087 unsigned int baud, 1088 unsigned int *frac) 1089 { 1090 static u8 p[][2] = { 1091 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1092 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1093 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1094 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1095 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1096 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1097 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1098 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1099 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1100 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1101 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1102 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1103 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1104 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1105 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1106 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1107 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1108 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1109 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1110 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1111 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1112 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1113 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1114 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1115 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1116 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1117 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1118 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1119 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1120 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1121 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1122 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1123 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1124 { 4, 9, }, { 4, 8, }, 1125 }; 1126 /* Scale the quotient for comparison to get the fractional part. */ 1127 const unsigned int quot_scale = 65536; 1128 unsigned int sclk = port->uartclk * 2; 1129 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1130 unsigned int best_squot; 1131 unsigned int squot; 1132 unsigned int quot; 1133 u16 cpr; 1134 u8 tcr; 1135 int i; 1136 1137 /* Old custom speed handling. */ 1138 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1139 unsigned int cust_div = port->custom_divisor; 1140 1141 quot = cust_div & UART_DIV_MAX; 1142 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1143 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1144 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1145 cpr = OXSEMI_TORNADO_CPR_DEF; 1146 } else { 1147 best_squot = quot_scale; 1148 for (i = 0; i < ARRAY_SIZE(p); i++) { 1149 unsigned int spre; 1150 unsigned int srem; 1151 u8 cp; 1152 u8 tc; 1153 1154 tc = p[i][0]; 1155 cp = p[i][1]; 1156 spre = tc * cp; 1157 1158 srem = sdiv % spre; 1159 if (srem > spre / 2) 1160 srem = spre - srem; 1161 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1162 1163 if (srem == 0) { 1164 tcr = tc; 1165 cpr = cp; 1166 quot = sdiv / spre; 1167 break; 1168 } else if (squot < best_squot) { 1169 best_squot = squot; 1170 tcr = tc; 1171 cpr = cp; 1172 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1173 } 1174 } 1175 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1176 quot % 2 == 0) { 1177 quot >>= 1; 1178 tcr <<= 1; 1179 } 1180 while (quot > UART_DIV_MAX) { 1181 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1182 quot >>= 1; 1183 tcr <<= 1; 1184 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1185 quot >>= 1; 1186 cpr <<= 1; 1187 } else { 1188 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1189 cpr = OXSEMI_TORNADO_CPR_MASK; 1190 } 1191 } 1192 } 1193 1194 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1195 return quot; 1196 } 1197 1198 /* 1199 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1200 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1201 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1202 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1203 * has to be written first, followed by CPR2, which occupies the location 1204 * of CKS used with earlier UART designs. 1205 */ 1206 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1207 unsigned int baud, 1208 unsigned int quot, 1209 unsigned int quot_frac) 1210 { 1211 struct uart_8250_port *up = up_to_u8250p(port); 1212 u8 cpr2 = quot_frac >> 16; 1213 u8 cpr = quot_frac >> 8; 1214 u8 tcr = quot_frac; 1215 1216 serial_icr_write(up, UART_TCR, tcr); 1217 serial_icr_write(up, UART_CPR, cpr); 1218 serial_icr_write(up, UART_CKS, cpr2); 1219 serial8250_do_set_divisor(port, baud, quot, 0); 1220 } 1221 1222 /* 1223 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1224 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1225 */ 1226 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1227 unsigned int mctrl) 1228 { 1229 struct uart_8250_port *up = up_to_u8250p(port); 1230 1231 up->mcr |= UART_MCR_CLKSEL; 1232 serial8250_do_set_mctrl(port, mctrl); 1233 } 1234 1235 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1236 const struct pciserial_board *board, 1237 struct uart_8250_port *up, int idx) 1238 { 1239 struct pci_dev *dev = priv->dev; 1240 1241 if (pci_oxsemi_tornado_p(dev)) { 1242 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1243 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1244 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1245 } 1246 1247 return pci_default_setup(priv, board, up, idx); 1248 } 1249 1250 static int pci_asix_setup(struct serial_private *priv, 1251 const struct pciserial_board *board, 1252 struct uart_8250_port *port, int idx) 1253 { 1254 port->bugs |= UART_BUG_PARITY; 1255 return pci_default_setup(priv, board, port, idx); 1256 } 1257 1258 #define QPCR_TEST_FOR1 0x3F 1259 #define QPCR_TEST_GET1 0x00 1260 #define QPCR_TEST_FOR2 0x40 1261 #define QPCR_TEST_GET2 0x40 1262 #define QPCR_TEST_FOR3 0x80 1263 #define QPCR_TEST_GET3 0x40 1264 #define QPCR_TEST_FOR4 0xC0 1265 #define QPCR_TEST_GET4 0x80 1266 1267 #define QOPR_CLOCK_X1 0x0000 1268 #define QOPR_CLOCK_X2 0x0001 1269 #define QOPR_CLOCK_X4 0x0002 1270 #define QOPR_CLOCK_X8 0x0003 1271 #define QOPR_CLOCK_RATE_MASK 0x0003 1272 1273 /* Quatech devices have their own extra interface features */ 1274 static struct pci_device_id quatech_cards[] = { 1275 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1276 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1277 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1278 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1279 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1280 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1281 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1282 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1283 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1284 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1285 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1286 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1287 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1288 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1289 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1290 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1291 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1292 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1293 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1294 { 0, } 1295 }; 1296 1297 static int pci_quatech_rqopr(struct uart_8250_port *port) 1298 { 1299 unsigned long base = port->port.iobase; 1300 u8 LCR, val; 1301 1302 LCR = inb(base + UART_LCR); 1303 outb(0xBF, base + UART_LCR); 1304 val = inb(base + UART_SCR); 1305 outb(LCR, base + UART_LCR); 1306 return val; 1307 } 1308 1309 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1310 { 1311 unsigned long base = port->port.iobase; 1312 u8 LCR; 1313 1314 LCR = inb(base + UART_LCR); 1315 outb(0xBF, base + UART_LCR); 1316 inb(base + UART_SCR); 1317 outb(qopr, base + UART_SCR); 1318 outb(LCR, base + UART_LCR); 1319 } 1320 1321 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1322 { 1323 unsigned long base = port->port.iobase; 1324 u8 LCR, val, qmcr; 1325 1326 LCR = inb(base + UART_LCR); 1327 outb(0xBF, base + UART_LCR); 1328 val = inb(base + UART_SCR); 1329 outb(val | 0x10, base + UART_SCR); 1330 qmcr = inb(base + UART_MCR); 1331 outb(val, base + UART_SCR); 1332 outb(LCR, base + UART_LCR); 1333 1334 return qmcr; 1335 } 1336 1337 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1338 { 1339 unsigned long base = port->port.iobase; 1340 u8 LCR, val; 1341 1342 LCR = inb(base + UART_LCR); 1343 outb(0xBF, base + UART_LCR); 1344 val = inb(base + UART_SCR); 1345 outb(val | 0x10, base + UART_SCR); 1346 outb(qmcr, base + UART_MCR); 1347 outb(val, base + UART_SCR); 1348 outb(LCR, base + UART_LCR); 1349 } 1350 1351 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1352 { 1353 unsigned long base = port->port.iobase; 1354 u8 LCR, val; 1355 1356 LCR = inb(base + UART_LCR); 1357 outb(0xBF, base + UART_LCR); 1358 val = inb(base + UART_SCR); 1359 if (val & 0x20) { 1360 outb(0x80, UART_LCR); 1361 if (!(inb(UART_SCR) & 0x20)) { 1362 outb(LCR, base + UART_LCR); 1363 return 1; 1364 } 1365 } 1366 return 0; 1367 } 1368 1369 static int pci_quatech_test(struct uart_8250_port *port) 1370 { 1371 u8 reg, qopr; 1372 1373 qopr = pci_quatech_rqopr(port); 1374 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1375 reg = pci_quatech_rqopr(port) & 0xC0; 1376 if (reg != QPCR_TEST_GET1) 1377 return -EINVAL; 1378 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1379 reg = pci_quatech_rqopr(port) & 0xC0; 1380 if (reg != QPCR_TEST_GET2) 1381 return -EINVAL; 1382 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1383 reg = pci_quatech_rqopr(port) & 0xC0; 1384 if (reg != QPCR_TEST_GET3) 1385 return -EINVAL; 1386 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1387 reg = pci_quatech_rqopr(port) & 0xC0; 1388 if (reg != QPCR_TEST_GET4) 1389 return -EINVAL; 1390 1391 pci_quatech_wqopr(port, qopr); 1392 return 0; 1393 } 1394 1395 static int pci_quatech_clock(struct uart_8250_port *port) 1396 { 1397 u8 qopr, reg, set; 1398 unsigned long clock; 1399 1400 if (pci_quatech_test(port) < 0) 1401 return 1843200; 1402 1403 qopr = pci_quatech_rqopr(port); 1404 1405 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1406 reg = pci_quatech_rqopr(port); 1407 if (reg & QOPR_CLOCK_X8) { 1408 clock = 1843200; 1409 goto out; 1410 } 1411 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1412 reg = pci_quatech_rqopr(port); 1413 if (!(reg & QOPR_CLOCK_X8)) { 1414 clock = 1843200; 1415 goto out; 1416 } 1417 reg &= QOPR_CLOCK_X8; 1418 if (reg == QOPR_CLOCK_X2) { 1419 clock = 3685400; 1420 set = QOPR_CLOCK_X2; 1421 } else if (reg == QOPR_CLOCK_X4) { 1422 clock = 7372800; 1423 set = QOPR_CLOCK_X4; 1424 } else if (reg == QOPR_CLOCK_X8) { 1425 clock = 14745600; 1426 set = QOPR_CLOCK_X8; 1427 } else { 1428 clock = 1843200; 1429 set = QOPR_CLOCK_X1; 1430 } 1431 qopr &= ~QOPR_CLOCK_RATE_MASK; 1432 qopr |= set; 1433 1434 out: 1435 pci_quatech_wqopr(port, qopr); 1436 return clock; 1437 } 1438 1439 static int pci_quatech_rs422(struct uart_8250_port *port) 1440 { 1441 u8 qmcr; 1442 int rs422 = 0; 1443 1444 if (!pci_quatech_has_qmcr(port)) 1445 return 0; 1446 qmcr = pci_quatech_rqmcr(port); 1447 pci_quatech_wqmcr(port, 0xFF); 1448 if (pci_quatech_rqmcr(port)) 1449 rs422 = 1; 1450 pci_quatech_wqmcr(port, qmcr); 1451 return rs422; 1452 } 1453 1454 static int pci_quatech_init(struct pci_dev *dev) 1455 { 1456 const struct pci_device_id *match; 1457 bool amcc = false; 1458 1459 match = pci_match_id(quatech_cards, dev); 1460 if (match) 1461 amcc = match->driver_data; 1462 else 1463 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1464 1465 if (amcc) { 1466 unsigned long base = pci_resource_start(dev, 0); 1467 if (base) { 1468 u32 tmp; 1469 1470 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1471 tmp = inl(base + 0x3c); 1472 outl(tmp | 0x01000000, base + 0x3c); 1473 outl(tmp & ~0x01000000, base + 0x3c); 1474 } 1475 } 1476 return 0; 1477 } 1478 1479 static int pci_quatech_setup(struct serial_private *priv, 1480 const struct pciserial_board *board, 1481 struct uart_8250_port *port, int idx) 1482 { 1483 /* Needed by pci_quatech calls below */ 1484 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1485 /* Set up the clocking */ 1486 port->port.uartclk = pci_quatech_clock(port); 1487 /* For now just warn about RS422 */ 1488 if (pci_quatech_rs422(port)) 1489 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1490 return pci_default_setup(priv, board, port, idx); 1491 } 1492 1493 static int pci_default_setup(struct serial_private *priv, 1494 const struct pciserial_board *board, 1495 struct uart_8250_port *port, int idx) 1496 { 1497 unsigned int bar, offset = board->first_offset, maxnr; 1498 1499 bar = FL_GET_BASE(board->flags); 1500 if (board->flags & FL_BASE_BARS) 1501 bar += idx; 1502 else 1503 offset += idx * board->uart_offset; 1504 1505 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1506 (board->reg_shift + 3); 1507 1508 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1509 return 1; 1510 1511 return setup_port(priv, port, bar, offset, board->reg_shift); 1512 } 1513 1514 static int 1515 ce4100_serial_setup(struct serial_private *priv, 1516 const struct pciserial_board *board, 1517 struct uart_8250_port *port, int idx) 1518 { 1519 int ret; 1520 1521 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1522 port->port.iotype = UPIO_MEM32; 1523 port->port.type = PORT_XSCALE; 1524 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1525 port->port.regshift = 2; 1526 1527 return ret; 1528 } 1529 1530 static int 1531 pci_omegapci_setup(struct serial_private *priv, 1532 const struct pciserial_board *board, 1533 struct uart_8250_port *port, int idx) 1534 { 1535 return setup_port(priv, port, 2, idx * 8, 0); 1536 } 1537 1538 static int 1539 pci_brcm_trumanage_setup(struct serial_private *priv, 1540 const struct pciserial_board *board, 1541 struct uart_8250_port *port, int idx) 1542 { 1543 int ret = pci_default_setup(priv, board, port, idx); 1544 1545 port->port.type = PORT_BRCM_TRUMANAGE; 1546 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1547 return ret; 1548 } 1549 1550 /* RTS will control by MCR if this bit is 0 */ 1551 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1552 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1553 #define FINTEK_RTS_INVERT BIT(5) 1554 1555 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1556 static int pci_fintek_rs485_config(struct uart_port *port, 1557 struct serial_rs485 *rs485) 1558 { 1559 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1560 u8 setting; 1561 u8 *index = (u8 *) port->private_data; 1562 1563 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1564 1565 if (!rs485) 1566 rs485 = &port->rs485; 1567 else if (rs485->flags & SER_RS485_ENABLED) 1568 memset(rs485->padding, 0, sizeof(rs485->padding)); 1569 else 1570 memset(rs485, 0, sizeof(*rs485)); 1571 1572 /* F81504/508/512 not support RTS delay before or after send */ 1573 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1574 1575 if (rs485->flags & SER_RS485_ENABLED) { 1576 /* Enable RTS H/W control mode */ 1577 setting |= FINTEK_RTS_CONTROL_BY_HW; 1578 1579 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1580 /* RTS driving high on TX */ 1581 setting &= ~FINTEK_RTS_INVERT; 1582 } else { 1583 /* RTS driving low on TX */ 1584 setting |= FINTEK_RTS_INVERT; 1585 } 1586 1587 rs485->delay_rts_after_send = 0; 1588 rs485->delay_rts_before_send = 0; 1589 } else { 1590 /* Disable RTS H/W control mode */ 1591 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1592 } 1593 1594 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1595 1596 if (rs485 != &port->rs485) 1597 port->rs485 = *rs485; 1598 1599 return 0; 1600 } 1601 1602 static int pci_fintek_setup(struct serial_private *priv, 1603 const struct pciserial_board *board, 1604 struct uart_8250_port *port, int idx) 1605 { 1606 struct pci_dev *pdev = priv->dev; 1607 u8 *data; 1608 u8 config_base; 1609 u16 iobase; 1610 1611 config_base = 0x40 + 0x08 * idx; 1612 1613 /* Get the io address from configuration space */ 1614 pci_read_config_word(pdev, config_base + 4, &iobase); 1615 1616 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1617 1618 port->port.iotype = UPIO_PORT; 1619 port->port.iobase = iobase; 1620 port->port.rs485_config = pci_fintek_rs485_config; 1621 1622 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1623 if (!data) 1624 return -ENOMEM; 1625 1626 /* preserve index in PCI configuration space */ 1627 *data = idx; 1628 port->port.private_data = data; 1629 1630 return 0; 1631 } 1632 1633 static int pci_fintek_init(struct pci_dev *dev) 1634 { 1635 unsigned long iobase; 1636 u32 max_port, i; 1637 resource_size_t bar_data[3]; 1638 u8 config_base; 1639 struct serial_private *priv = pci_get_drvdata(dev); 1640 struct uart_8250_port *port; 1641 1642 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1643 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1644 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1645 return -ENODEV; 1646 1647 switch (dev->device) { 1648 case 0x1104: /* 4 ports */ 1649 case 0x1108: /* 8 ports */ 1650 max_port = dev->device & 0xff; 1651 break; 1652 case 0x1112: /* 12 ports */ 1653 max_port = 12; 1654 break; 1655 default: 1656 return -EINVAL; 1657 } 1658 1659 /* Get the io address dispatch from the BIOS */ 1660 bar_data[0] = pci_resource_start(dev, 5); 1661 bar_data[1] = pci_resource_start(dev, 4); 1662 bar_data[2] = pci_resource_start(dev, 3); 1663 1664 for (i = 0; i < max_port; ++i) { 1665 /* UART0 configuration offset start from 0x40 */ 1666 config_base = 0x40 + 0x08 * i; 1667 1668 /* Calculate Real IO Port */ 1669 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1670 1671 /* Enable UART I/O port */ 1672 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1673 1674 /* Select 128-byte FIFO and 8x FIFO threshold */ 1675 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1676 1677 /* LSB UART */ 1678 pci_write_config_byte(dev, config_base + 0x04, 1679 (u8)(iobase & 0xff)); 1680 1681 /* MSB UART */ 1682 pci_write_config_byte(dev, config_base + 0x05, 1683 (u8)((iobase & 0xff00) >> 8)); 1684 1685 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1686 1687 if (priv) { 1688 /* re-apply RS232/485 mode when 1689 * pciserial_resume_ports() 1690 */ 1691 port = serial8250_get_port(priv->line[i]); 1692 pci_fintek_rs485_config(&port->port, NULL); 1693 } else { 1694 /* First init without port data 1695 * force init to RS232 Mode 1696 */ 1697 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1698 } 1699 } 1700 1701 return max_port; 1702 } 1703 1704 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1705 { 1706 struct f815xxa_data *data = p->private_data; 1707 unsigned long flags; 1708 1709 spin_lock_irqsave(&data->lock, flags); 1710 writeb(value, p->membase + offset); 1711 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1712 spin_unlock_irqrestore(&data->lock, flags); 1713 } 1714 1715 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1716 const struct pciserial_board *board, 1717 struct uart_8250_port *port, int idx) 1718 { 1719 struct pci_dev *pdev = priv->dev; 1720 struct f815xxa_data *data; 1721 1722 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1723 if (!data) 1724 return -ENOMEM; 1725 1726 data->idx = idx; 1727 spin_lock_init(&data->lock); 1728 1729 port->port.private_data = data; 1730 port->port.iotype = UPIO_MEM; 1731 port->port.flags |= UPF_IOREMAP; 1732 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1733 port->port.serial_out = f815xxa_mem_serial_out; 1734 1735 return 0; 1736 } 1737 1738 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1739 { 1740 u32 max_port, i; 1741 int config_base; 1742 1743 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1744 return -ENODEV; 1745 1746 switch (dev->device) { 1747 case 0x1204: /* 4 ports */ 1748 case 0x1208: /* 8 ports */ 1749 max_port = dev->device & 0xff; 1750 break; 1751 case 0x1212: /* 12 ports */ 1752 max_port = 12; 1753 break; 1754 default: 1755 return -EINVAL; 1756 } 1757 1758 /* Set to mmio decode */ 1759 pci_write_config_byte(dev, 0x209, 0x40); 1760 1761 for (i = 0; i < max_port; ++i) { 1762 /* UART0 configuration offset start from 0x2A0 */ 1763 config_base = 0x2A0 + 0x08 * i; 1764 1765 /* Select 128-byte FIFO and 8x FIFO threshold */ 1766 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1767 1768 /* Enable UART I/O port */ 1769 pci_write_config_byte(dev, config_base + 0, 0x01); 1770 } 1771 1772 return max_port; 1773 } 1774 1775 static int skip_tx_en_setup(struct serial_private *priv, 1776 const struct pciserial_board *board, 1777 struct uart_8250_port *port, int idx) 1778 { 1779 port->port.quirks |= UPQ_NO_TXEN_TEST; 1780 pci_dbg(priv->dev, 1781 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1782 priv->dev->vendor, priv->dev->device, 1783 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1784 1785 return pci_default_setup(priv, board, port, idx); 1786 } 1787 1788 static void kt_handle_break(struct uart_port *p) 1789 { 1790 struct uart_8250_port *up = up_to_u8250p(p); 1791 /* 1792 * On receipt of a BI, serial device in Intel ME (Intel 1793 * management engine) needs to have its fifos cleared for sane 1794 * SOL (Serial Over Lan) output. 1795 */ 1796 serial8250_clear_and_reinit_fifos(up); 1797 } 1798 1799 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1800 { 1801 struct uart_8250_port *up = up_to_u8250p(p); 1802 unsigned int val; 1803 1804 /* 1805 * When the Intel ME (management engine) gets reset its serial 1806 * port registers could return 0 momentarily. Functions like 1807 * serial8250_console_write, read and save the IER, perform 1808 * some operation and then restore it. In order to avoid 1809 * setting IER register inadvertently to 0, if the value read 1810 * is 0, double check with ier value in uart_8250_port and use 1811 * that instead. up->ier should be the same value as what is 1812 * currently configured. 1813 */ 1814 val = inb(p->iobase + offset); 1815 if (offset == UART_IER) { 1816 if (val == 0) 1817 val = up->ier; 1818 } 1819 return val; 1820 } 1821 1822 static int kt_serial_setup(struct serial_private *priv, 1823 const struct pciserial_board *board, 1824 struct uart_8250_port *port, int idx) 1825 { 1826 port->port.flags |= UPF_BUG_THRE; 1827 port->port.serial_in = kt_serial_in; 1828 port->port.handle_break = kt_handle_break; 1829 return skip_tx_en_setup(priv, board, port, idx); 1830 } 1831 1832 static int pci_eg20t_init(struct pci_dev *dev) 1833 { 1834 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1835 return -ENODEV; 1836 #else 1837 return 0; 1838 #endif 1839 } 1840 1841 static int 1842 pci_wch_ch353_setup(struct serial_private *priv, 1843 const struct pciserial_board *board, 1844 struct uart_8250_port *port, int idx) 1845 { 1846 port->port.flags |= UPF_FIXED_TYPE; 1847 port->port.type = PORT_16550A; 1848 return pci_default_setup(priv, board, port, idx); 1849 } 1850 1851 static int 1852 pci_wch_ch355_setup(struct serial_private *priv, 1853 const struct pciserial_board *board, 1854 struct uart_8250_port *port, int idx) 1855 { 1856 port->port.flags |= UPF_FIXED_TYPE; 1857 port->port.type = PORT_16550A; 1858 return pci_default_setup(priv, board, port, idx); 1859 } 1860 1861 static int 1862 pci_wch_ch38x_setup(struct serial_private *priv, 1863 const struct pciserial_board *board, 1864 struct uart_8250_port *port, int idx) 1865 { 1866 port->port.flags |= UPF_FIXED_TYPE; 1867 port->port.type = PORT_16850; 1868 return pci_default_setup(priv, board, port, idx); 1869 } 1870 1871 1872 #define CH384_XINT_ENABLE_REG 0xEB 1873 #define CH384_XINT_ENABLE_BIT 0x02 1874 1875 static int pci_wch_ch38x_init(struct pci_dev *dev) 1876 { 1877 int max_port; 1878 unsigned long iobase; 1879 1880 1881 switch (dev->device) { 1882 case 0x3853: /* 8 ports */ 1883 max_port = 8; 1884 break; 1885 default: 1886 return -EINVAL; 1887 } 1888 1889 iobase = pci_resource_start(dev, 0); 1890 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1891 1892 return max_port; 1893 } 1894 1895 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1896 { 1897 unsigned long iobase; 1898 1899 iobase = pci_resource_start(dev, 0); 1900 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1901 } 1902 1903 1904 static int 1905 pci_sunix_setup(struct serial_private *priv, 1906 const struct pciserial_board *board, 1907 struct uart_8250_port *port, int idx) 1908 { 1909 int bar; 1910 int offset; 1911 1912 port->port.flags |= UPF_FIXED_TYPE; 1913 port->port.type = PORT_SUNIX; 1914 1915 if (idx < 4) { 1916 bar = 0; 1917 offset = idx * board->uart_offset; 1918 } else { 1919 bar = 1; 1920 idx -= 4; 1921 idx = div_s64_rem(idx, 4, &offset); 1922 offset = idx * 64 + offset * board->uart_offset; 1923 } 1924 1925 return setup_port(priv, port, bar, offset, 0); 1926 } 1927 1928 static int 1929 pci_moxa_setup(struct serial_private *priv, 1930 const struct pciserial_board *board, 1931 struct uart_8250_port *port, int idx) 1932 { 1933 unsigned int bar = FL_GET_BASE(board->flags); 1934 int offset; 1935 1936 if (board->num_ports == 4 && idx == 3) 1937 offset = 7 * board->uart_offset; 1938 else 1939 offset = idx * board->uart_offset; 1940 1941 return setup_port(priv, port, bar, offset, 0); 1942 } 1943 1944 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1945 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1946 #define PCI_DEVICE_ID_OCTPRO 0x0001 1947 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1948 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1949 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1950 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1951 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1952 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1953 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1954 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1955 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1956 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1957 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1958 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1959 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1960 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1961 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1962 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1963 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1964 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1965 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1966 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1967 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1968 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1969 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1970 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1971 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1972 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1973 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1974 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1975 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1976 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1977 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1978 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1979 #define PCI_VENDOR_ID_WCH 0x4348 1980 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1981 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1982 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1983 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1984 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1985 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1986 #define PCI_VENDOR_ID_AGESTAR 0x5372 1987 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1988 #define PCI_VENDOR_ID_ASIX 0x9710 1989 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1990 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1991 1992 #define PCIE_VENDOR_ID_WCH 0x1c00 1993 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1994 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1995 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1996 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1997 1998 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1999 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 2000 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 2001 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 2002 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 2003 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 2004 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 2005 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 2006 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 2007 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 2008 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 2009 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 2010 2011 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 2012 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 2013 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 2014 2015 /* 2016 * Master list of serial port init/setup/exit quirks. 2017 * This does not describe the general nature of the port. 2018 * (ie, baud base, number and location of ports, etc) 2019 * 2020 * This list is ordered alphabetically by vendor then device. 2021 * Specific entries must come before more generic entries. 2022 */ 2023 static struct pci_serial_quirk pci_serial_quirks[] = { 2024 /* 2025 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2026 */ 2027 { 2028 .vendor = PCI_VENDOR_ID_AMCC, 2029 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2030 .subvendor = PCI_ANY_ID, 2031 .subdevice = PCI_ANY_ID, 2032 .setup = addidata_apci7800_setup, 2033 }, 2034 /* 2035 * AFAVLAB cards - these may be called via parport_serial 2036 * It is not clear whether this applies to all products. 2037 */ 2038 { 2039 .vendor = PCI_VENDOR_ID_AFAVLAB, 2040 .device = PCI_ANY_ID, 2041 .subvendor = PCI_ANY_ID, 2042 .subdevice = PCI_ANY_ID, 2043 .setup = afavlab_setup, 2044 }, 2045 /* 2046 * HP Diva 2047 */ 2048 { 2049 .vendor = PCI_VENDOR_ID_HP, 2050 .device = PCI_DEVICE_ID_HP_DIVA, 2051 .subvendor = PCI_ANY_ID, 2052 .subdevice = PCI_ANY_ID, 2053 .init = pci_hp_diva_init, 2054 .setup = pci_hp_diva_setup, 2055 }, 2056 /* 2057 * HPE PCI serial device 2058 */ 2059 { 2060 .vendor = PCI_VENDOR_ID_HP_3PAR, 2061 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2062 .subvendor = PCI_ANY_ID, 2063 .subdevice = PCI_ANY_ID, 2064 .setup = pci_hp_diva_setup, 2065 }, 2066 /* 2067 * Intel 2068 */ 2069 { 2070 .vendor = PCI_VENDOR_ID_INTEL, 2071 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2072 .subvendor = 0xe4bf, 2073 .subdevice = PCI_ANY_ID, 2074 .init = pci_inteli960ni_init, 2075 .setup = pci_default_setup, 2076 }, 2077 { 2078 .vendor = PCI_VENDOR_ID_INTEL, 2079 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2080 .subvendor = PCI_ANY_ID, 2081 .subdevice = PCI_ANY_ID, 2082 .setup = skip_tx_en_setup, 2083 }, 2084 { 2085 .vendor = PCI_VENDOR_ID_INTEL, 2086 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2087 .subvendor = PCI_ANY_ID, 2088 .subdevice = PCI_ANY_ID, 2089 .setup = skip_tx_en_setup, 2090 }, 2091 { 2092 .vendor = PCI_VENDOR_ID_INTEL, 2093 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2094 .subvendor = PCI_ANY_ID, 2095 .subdevice = PCI_ANY_ID, 2096 .setup = skip_tx_en_setup, 2097 }, 2098 { 2099 .vendor = PCI_VENDOR_ID_INTEL, 2100 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2101 .subvendor = PCI_ANY_ID, 2102 .subdevice = PCI_ANY_ID, 2103 .setup = ce4100_serial_setup, 2104 }, 2105 { 2106 .vendor = PCI_VENDOR_ID_INTEL, 2107 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2108 .subvendor = PCI_ANY_ID, 2109 .subdevice = PCI_ANY_ID, 2110 .setup = kt_serial_setup, 2111 }, 2112 /* 2113 * ITE 2114 */ 2115 { 2116 .vendor = PCI_VENDOR_ID_ITE, 2117 .device = PCI_DEVICE_ID_ITE_8872, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ite887x_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ite887x_exit, 2123 }, 2124 /* 2125 * National Instruments 2126 */ 2127 { 2128 .vendor = PCI_VENDOR_ID_NI, 2129 .device = PCI_DEVICE_ID_NI_PCI23216, 2130 .subvendor = PCI_ANY_ID, 2131 .subdevice = PCI_ANY_ID, 2132 .init = pci_ni8420_init, 2133 .setup = pci_default_setup, 2134 .exit = pci_ni8420_exit, 2135 }, 2136 { 2137 .vendor = PCI_VENDOR_ID_NI, 2138 .device = PCI_DEVICE_ID_NI_PCI2328, 2139 .subvendor = PCI_ANY_ID, 2140 .subdevice = PCI_ANY_ID, 2141 .init = pci_ni8420_init, 2142 .setup = pci_default_setup, 2143 .exit = pci_ni8420_exit, 2144 }, 2145 { 2146 .vendor = PCI_VENDOR_ID_NI, 2147 .device = PCI_DEVICE_ID_NI_PCI2324, 2148 .subvendor = PCI_ANY_ID, 2149 .subdevice = PCI_ANY_ID, 2150 .init = pci_ni8420_init, 2151 .setup = pci_default_setup, 2152 .exit = pci_ni8420_exit, 2153 }, 2154 { 2155 .vendor = PCI_VENDOR_ID_NI, 2156 .device = PCI_DEVICE_ID_NI_PCI2322, 2157 .subvendor = PCI_ANY_ID, 2158 .subdevice = PCI_ANY_ID, 2159 .init = pci_ni8420_init, 2160 .setup = pci_default_setup, 2161 .exit = pci_ni8420_exit, 2162 }, 2163 { 2164 .vendor = PCI_VENDOR_ID_NI, 2165 .device = PCI_DEVICE_ID_NI_PCI2324I, 2166 .subvendor = PCI_ANY_ID, 2167 .subdevice = PCI_ANY_ID, 2168 .init = pci_ni8420_init, 2169 .setup = pci_default_setup, 2170 .exit = pci_ni8420_exit, 2171 }, 2172 { 2173 .vendor = PCI_VENDOR_ID_NI, 2174 .device = PCI_DEVICE_ID_NI_PCI2322I, 2175 .subvendor = PCI_ANY_ID, 2176 .subdevice = PCI_ANY_ID, 2177 .init = pci_ni8420_init, 2178 .setup = pci_default_setup, 2179 .exit = pci_ni8420_exit, 2180 }, 2181 { 2182 .vendor = PCI_VENDOR_ID_NI, 2183 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2184 .subvendor = PCI_ANY_ID, 2185 .subdevice = PCI_ANY_ID, 2186 .init = pci_ni8420_init, 2187 .setup = pci_default_setup, 2188 .exit = pci_ni8420_exit, 2189 }, 2190 { 2191 .vendor = PCI_VENDOR_ID_NI, 2192 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2193 .subvendor = PCI_ANY_ID, 2194 .subdevice = PCI_ANY_ID, 2195 .init = pci_ni8420_init, 2196 .setup = pci_default_setup, 2197 .exit = pci_ni8420_exit, 2198 }, 2199 { 2200 .vendor = PCI_VENDOR_ID_NI, 2201 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2202 .subvendor = PCI_ANY_ID, 2203 .subdevice = PCI_ANY_ID, 2204 .init = pci_ni8420_init, 2205 .setup = pci_default_setup, 2206 .exit = pci_ni8420_exit, 2207 }, 2208 { 2209 .vendor = PCI_VENDOR_ID_NI, 2210 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2211 .subvendor = PCI_ANY_ID, 2212 .subdevice = PCI_ANY_ID, 2213 .init = pci_ni8420_init, 2214 .setup = pci_default_setup, 2215 .exit = pci_ni8420_exit, 2216 }, 2217 { 2218 .vendor = PCI_VENDOR_ID_NI, 2219 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2220 .subvendor = PCI_ANY_ID, 2221 .subdevice = PCI_ANY_ID, 2222 .init = pci_ni8420_init, 2223 .setup = pci_default_setup, 2224 .exit = pci_ni8420_exit, 2225 }, 2226 { 2227 .vendor = PCI_VENDOR_ID_NI, 2228 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2229 .subvendor = PCI_ANY_ID, 2230 .subdevice = PCI_ANY_ID, 2231 .init = pci_ni8420_init, 2232 .setup = pci_default_setup, 2233 .exit = pci_ni8420_exit, 2234 }, 2235 { 2236 .vendor = PCI_VENDOR_ID_NI, 2237 .device = PCI_ANY_ID, 2238 .subvendor = PCI_ANY_ID, 2239 .subdevice = PCI_ANY_ID, 2240 .init = pci_ni8430_init, 2241 .setup = pci_ni8430_setup, 2242 .exit = pci_ni8430_exit, 2243 }, 2244 /* Quatech */ 2245 { 2246 .vendor = PCI_VENDOR_ID_QUATECH, 2247 .device = PCI_ANY_ID, 2248 .subvendor = PCI_ANY_ID, 2249 .subdevice = PCI_ANY_ID, 2250 .init = pci_quatech_init, 2251 .setup = pci_quatech_setup, 2252 }, 2253 /* 2254 * Panacom 2255 */ 2256 { 2257 .vendor = PCI_VENDOR_ID_PANACOM, 2258 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2259 .subvendor = PCI_ANY_ID, 2260 .subdevice = PCI_ANY_ID, 2261 .init = pci_plx9050_init, 2262 .setup = pci_default_setup, 2263 .exit = pci_plx9050_exit, 2264 }, 2265 { 2266 .vendor = PCI_VENDOR_ID_PANACOM, 2267 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2268 .subvendor = PCI_ANY_ID, 2269 .subdevice = PCI_ANY_ID, 2270 .init = pci_plx9050_init, 2271 .setup = pci_default_setup, 2272 .exit = pci_plx9050_exit, 2273 }, 2274 /* 2275 * PLX 2276 */ 2277 { 2278 .vendor = PCI_VENDOR_ID_PLX, 2279 .device = PCI_DEVICE_ID_PLX_9050, 2280 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2281 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2282 .init = pci_plx9050_init, 2283 .setup = pci_default_setup, 2284 .exit = pci_plx9050_exit, 2285 }, 2286 { 2287 .vendor = PCI_VENDOR_ID_PLX, 2288 .device = PCI_DEVICE_ID_PLX_9050, 2289 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2290 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2291 .init = pci_plx9050_init, 2292 .setup = pci_default_setup, 2293 .exit = pci_plx9050_exit, 2294 }, 2295 { 2296 .vendor = PCI_VENDOR_ID_PLX, 2297 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2298 .subvendor = PCI_VENDOR_ID_PLX, 2299 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2300 .init = pci_plx9050_init, 2301 .setup = pci_default_setup, 2302 .exit = pci_plx9050_exit, 2303 }, 2304 /* 2305 * SBS Technologies, Inc., PMC-OCTALPRO 232 2306 */ 2307 { 2308 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2309 .device = PCI_DEVICE_ID_OCTPRO, 2310 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2311 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2312 .init = sbs_init, 2313 .setup = sbs_setup, 2314 .exit = sbs_exit, 2315 }, 2316 /* 2317 * SBS Technologies, Inc., PMC-OCTALPRO 422 2318 */ 2319 { 2320 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2321 .device = PCI_DEVICE_ID_OCTPRO, 2322 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2323 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2324 .init = sbs_init, 2325 .setup = sbs_setup, 2326 .exit = sbs_exit, 2327 }, 2328 /* 2329 * SBS Technologies, Inc., P-Octal 232 2330 */ 2331 { 2332 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2333 .device = PCI_DEVICE_ID_OCTPRO, 2334 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2335 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2336 .init = sbs_init, 2337 .setup = sbs_setup, 2338 .exit = sbs_exit, 2339 }, 2340 /* 2341 * SBS Technologies, Inc., P-Octal 422 2342 */ 2343 { 2344 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2345 .device = PCI_DEVICE_ID_OCTPRO, 2346 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2347 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2348 .init = sbs_init, 2349 .setup = sbs_setup, 2350 .exit = sbs_exit, 2351 }, 2352 /* 2353 * SIIG cards - these may be called via parport_serial 2354 */ 2355 { 2356 .vendor = PCI_VENDOR_ID_SIIG, 2357 .device = PCI_ANY_ID, 2358 .subvendor = PCI_ANY_ID, 2359 .subdevice = PCI_ANY_ID, 2360 .init = pci_siig_init, 2361 .setup = pci_siig_setup, 2362 }, 2363 /* 2364 * Titan cards 2365 */ 2366 { 2367 .vendor = PCI_VENDOR_ID_TITAN, 2368 .device = PCI_DEVICE_ID_TITAN_400L, 2369 .subvendor = PCI_ANY_ID, 2370 .subdevice = PCI_ANY_ID, 2371 .setup = titan_400l_800l_setup, 2372 }, 2373 { 2374 .vendor = PCI_VENDOR_ID_TITAN, 2375 .device = PCI_DEVICE_ID_TITAN_800L, 2376 .subvendor = PCI_ANY_ID, 2377 .subdevice = PCI_ANY_ID, 2378 .setup = titan_400l_800l_setup, 2379 }, 2380 /* 2381 * Timedia cards 2382 */ 2383 { 2384 .vendor = PCI_VENDOR_ID_TIMEDIA, 2385 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2386 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2387 .subdevice = PCI_ANY_ID, 2388 .probe = pci_timedia_probe, 2389 .init = pci_timedia_init, 2390 .setup = pci_timedia_setup, 2391 }, 2392 { 2393 .vendor = PCI_VENDOR_ID_TIMEDIA, 2394 .device = PCI_ANY_ID, 2395 .subvendor = PCI_ANY_ID, 2396 .subdevice = PCI_ANY_ID, 2397 .setup = pci_timedia_setup, 2398 }, 2399 /* 2400 * Sunix PCI serial boards 2401 */ 2402 { 2403 .vendor = PCI_VENDOR_ID_SUNIX, 2404 .device = PCI_DEVICE_ID_SUNIX_1999, 2405 .subvendor = PCI_VENDOR_ID_SUNIX, 2406 .subdevice = PCI_ANY_ID, 2407 .setup = pci_sunix_setup, 2408 }, 2409 /* 2410 * Xircom cards 2411 */ 2412 { 2413 .vendor = PCI_VENDOR_ID_XIRCOM, 2414 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2415 .subvendor = PCI_ANY_ID, 2416 .subdevice = PCI_ANY_ID, 2417 .init = pci_xircom_init, 2418 .setup = pci_default_setup, 2419 }, 2420 /* 2421 * Netmos cards - these may be called via parport_serial 2422 */ 2423 { 2424 .vendor = PCI_VENDOR_ID_NETMOS, 2425 .device = PCI_ANY_ID, 2426 .subvendor = PCI_ANY_ID, 2427 .subdevice = PCI_ANY_ID, 2428 .init = pci_netmos_init, 2429 .setup = pci_netmos_9900_setup, 2430 }, 2431 /* 2432 * EndRun Technologies 2433 */ 2434 { 2435 .vendor = PCI_VENDOR_ID_ENDRUN, 2436 .device = PCI_ANY_ID, 2437 .subvendor = PCI_ANY_ID, 2438 .subdevice = PCI_ANY_ID, 2439 .init = pci_oxsemi_tornado_init, 2440 .setup = pci_default_setup, 2441 }, 2442 /* 2443 * For Oxford Semiconductor Tornado based devices 2444 */ 2445 { 2446 .vendor = PCI_VENDOR_ID_OXSEMI, 2447 .device = PCI_ANY_ID, 2448 .subvendor = PCI_ANY_ID, 2449 .subdevice = PCI_ANY_ID, 2450 .init = pci_oxsemi_tornado_init, 2451 .setup = pci_oxsemi_tornado_setup, 2452 }, 2453 { 2454 .vendor = PCI_VENDOR_ID_MAINPINE, 2455 .device = PCI_ANY_ID, 2456 .subvendor = PCI_ANY_ID, 2457 .subdevice = PCI_ANY_ID, 2458 .init = pci_oxsemi_tornado_init, 2459 .setup = pci_oxsemi_tornado_setup, 2460 }, 2461 { 2462 .vendor = PCI_VENDOR_ID_DIGI, 2463 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2464 .subvendor = PCI_SUBVENDOR_ID_IBM, 2465 .subdevice = PCI_ANY_ID, 2466 .init = pci_oxsemi_tornado_init, 2467 .setup = pci_oxsemi_tornado_setup, 2468 }, 2469 { 2470 .vendor = PCI_VENDOR_ID_INTEL, 2471 .device = 0x8811, 2472 .subvendor = PCI_ANY_ID, 2473 .subdevice = PCI_ANY_ID, 2474 .init = pci_eg20t_init, 2475 .setup = pci_default_setup, 2476 }, 2477 { 2478 .vendor = PCI_VENDOR_ID_INTEL, 2479 .device = 0x8812, 2480 .subvendor = PCI_ANY_ID, 2481 .subdevice = PCI_ANY_ID, 2482 .init = pci_eg20t_init, 2483 .setup = pci_default_setup, 2484 }, 2485 { 2486 .vendor = PCI_VENDOR_ID_INTEL, 2487 .device = 0x8813, 2488 .subvendor = PCI_ANY_ID, 2489 .subdevice = PCI_ANY_ID, 2490 .init = pci_eg20t_init, 2491 .setup = pci_default_setup, 2492 }, 2493 { 2494 .vendor = PCI_VENDOR_ID_INTEL, 2495 .device = 0x8814, 2496 .subvendor = PCI_ANY_ID, 2497 .subdevice = PCI_ANY_ID, 2498 .init = pci_eg20t_init, 2499 .setup = pci_default_setup, 2500 }, 2501 { 2502 .vendor = 0x10DB, 2503 .device = 0x8027, 2504 .subvendor = PCI_ANY_ID, 2505 .subdevice = PCI_ANY_ID, 2506 .init = pci_eg20t_init, 2507 .setup = pci_default_setup, 2508 }, 2509 { 2510 .vendor = 0x10DB, 2511 .device = 0x8028, 2512 .subvendor = PCI_ANY_ID, 2513 .subdevice = PCI_ANY_ID, 2514 .init = pci_eg20t_init, 2515 .setup = pci_default_setup, 2516 }, 2517 { 2518 .vendor = 0x10DB, 2519 .device = 0x8029, 2520 .subvendor = PCI_ANY_ID, 2521 .subdevice = PCI_ANY_ID, 2522 .init = pci_eg20t_init, 2523 .setup = pci_default_setup, 2524 }, 2525 { 2526 .vendor = 0x10DB, 2527 .device = 0x800C, 2528 .subvendor = PCI_ANY_ID, 2529 .subdevice = PCI_ANY_ID, 2530 .init = pci_eg20t_init, 2531 .setup = pci_default_setup, 2532 }, 2533 { 2534 .vendor = 0x10DB, 2535 .device = 0x800D, 2536 .subvendor = PCI_ANY_ID, 2537 .subdevice = PCI_ANY_ID, 2538 .init = pci_eg20t_init, 2539 .setup = pci_default_setup, 2540 }, 2541 /* 2542 * Cronyx Omega PCI (PLX-chip based) 2543 */ 2544 { 2545 .vendor = PCI_VENDOR_ID_PLX, 2546 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2547 .subvendor = PCI_ANY_ID, 2548 .subdevice = PCI_ANY_ID, 2549 .setup = pci_omegapci_setup, 2550 }, 2551 /* WCH CH353 1S1P card (16550 clone) */ 2552 { 2553 .vendor = PCI_VENDOR_ID_WCH, 2554 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2555 .subvendor = PCI_ANY_ID, 2556 .subdevice = PCI_ANY_ID, 2557 .setup = pci_wch_ch353_setup, 2558 }, 2559 /* WCH CH353 2S1P card (16550 clone) */ 2560 { 2561 .vendor = PCI_VENDOR_ID_WCH, 2562 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2563 .subvendor = PCI_ANY_ID, 2564 .subdevice = PCI_ANY_ID, 2565 .setup = pci_wch_ch353_setup, 2566 }, 2567 /* WCH CH353 4S card (16550 clone) */ 2568 { 2569 .vendor = PCI_VENDOR_ID_WCH, 2570 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2571 .subvendor = PCI_ANY_ID, 2572 .subdevice = PCI_ANY_ID, 2573 .setup = pci_wch_ch353_setup, 2574 }, 2575 /* WCH CH353 2S1PF card (16550 clone) */ 2576 { 2577 .vendor = PCI_VENDOR_ID_WCH, 2578 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2579 .subvendor = PCI_ANY_ID, 2580 .subdevice = PCI_ANY_ID, 2581 .setup = pci_wch_ch353_setup, 2582 }, 2583 /* WCH CH352 2S card (16550 clone) */ 2584 { 2585 .vendor = PCI_VENDOR_ID_WCH, 2586 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2587 .subvendor = PCI_ANY_ID, 2588 .subdevice = PCI_ANY_ID, 2589 .setup = pci_wch_ch353_setup, 2590 }, 2591 /* WCH CH355 4S card (16550 clone) */ 2592 { 2593 .vendor = PCI_VENDOR_ID_WCH, 2594 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2595 .subvendor = PCI_ANY_ID, 2596 .subdevice = PCI_ANY_ID, 2597 .setup = pci_wch_ch355_setup, 2598 }, 2599 /* WCH CH382 2S card (16850 clone) */ 2600 { 2601 .vendor = PCIE_VENDOR_ID_WCH, 2602 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2603 .subvendor = PCI_ANY_ID, 2604 .subdevice = PCI_ANY_ID, 2605 .setup = pci_wch_ch38x_setup, 2606 }, 2607 /* WCH CH382 2S1P card (16850 clone) */ 2608 { 2609 .vendor = PCIE_VENDOR_ID_WCH, 2610 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2611 .subvendor = PCI_ANY_ID, 2612 .subdevice = PCI_ANY_ID, 2613 .setup = pci_wch_ch38x_setup, 2614 }, 2615 /* WCH CH384 4S card (16850 clone) */ 2616 { 2617 .vendor = PCIE_VENDOR_ID_WCH, 2618 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2619 .subvendor = PCI_ANY_ID, 2620 .subdevice = PCI_ANY_ID, 2621 .setup = pci_wch_ch38x_setup, 2622 }, 2623 /* WCH CH384 8S card (16850 clone) */ 2624 { 2625 .vendor = PCIE_VENDOR_ID_WCH, 2626 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2627 .subvendor = PCI_ANY_ID, 2628 .subdevice = PCI_ANY_ID, 2629 .init = pci_wch_ch38x_init, 2630 .exit = pci_wch_ch38x_exit, 2631 .setup = pci_wch_ch38x_setup, 2632 }, 2633 /* 2634 * ASIX devices with FIFO bug 2635 */ 2636 { 2637 .vendor = PCI_VENDOR_ID_ASIX, 2638 .device = PCI_ANY_ID, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .setup = pci_asix_setup, 2642 }, 2643 /* 2644 * Broadcom TruManage (NetXtreme) 2645 */ 2646 { 2647 .vendor = PCI_VENDOR_ID_BROADCOM, 2648 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2649 .subvendor = PCI_ANY_ID, 2650 .subdevice = PCI_ANY_ID, 2651 .setup = pci_brcm_trumanage_setup, 2652 }, 2653 { 2654 .vendor = 0x1c29, 2655 .device = 0x1104, 2656 .subvendor = PCI_ANY_ID, 2657 .subdevice = PCI_ANY_ID, 2658 .setup = pci_fintek_setup, 2659 .init = pci_fintek_init, 2660 }, 2661 { 2662 .vendor = 0x1c29, 2663 .device = 0x1108, 2664 .subvendor = PCI_ANY_ID, 2665 .subdevice = PCI_ANY_ID, 2666 .setup = pci_fintek_setup, 2667 .init = pci_fintek_init, 2668 }, 2669 { 2670 .vendor = 0x1c29, 2671 .device = 0x1112, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .setup = pci_fintek_setup, 2675 .init = pci_fintek_init, 2676 }, 2677 /* 2678 * MOXA 2679 */ 2680 { 2681 .vendor = PCI_VENDOR_ID_MOXA, 2682 .device = PCI_ANY_ID, 2683 .subvendor = PCI_ANY_ID, 2684 .subdevice = PCI_ANY_ID, 2685 .setup = pci_moxa_setup, 2686 }, 2687 { 2688 .vendor = 0x1c29, 2689 .device = 0x1204, 2690 .subvendor = PCI_ANY_ID, 2691 .subdevice = PCI_ANY_ID, 2692 .setup = pci_fintek_f815xxa_setup, 2693 .init = pci_fintek_f815xxa_init, 2694 }, 2695 { 2696 .vendor = 0x1c29, 2697 .device = 0x1208, 2698 .subvendor = PCI_ANY_ID, 2699 .subdevice = PCI_ANY_ID, 2700 .setup = pci_fintek_f815xxa_setup, 2701 .init = pci_fintek_f815xxa_init, 2702 }, 2703 { 2704 .vendor = 0x1c29, 2705 .device = 0x1212, 2706 .subvendor = PCI_ANY_ID, 2707 .subdevice = PCI_ANY_ID, 2708 .setup = pci_fintek_f815xxa_setup, 2709 .init = pci_fintek_f815xxa_init, 2710 }, 2711 2712 /* 2713 * Default "match everything" terminator entry 2714 */ 2715 { 2716 .vendor = PCI_ANY_ID, 2717 .device = PCI_ANY_ID, 2718 .subvendor = PCI_ANY_ID, 2719 .subdevice = PCI_ANY_ID, 2720 .setup = pci_default_setup, 2721 } 2722 }; 2723 2724 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2725 { 2726 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2727 } 2728 2729 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2730 { 2731 struct pci_serial_quirk *quirk; 2732 2733 for (quirk = pci_serial_quirks; ; quirk++) 2734 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2735 quirk_id_matches(quirk->device, dev->device) && 2736 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2737 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2738 break; 2739 return quirk; 2740 } 2741 2742 /* 2743 * This is the configuration table for all of the PCI serial boards 2744 * which we support. It is directly indexed by the pci_board_num_t enum 2745 * value, which is encoded in the pci_device_id PCI probe table's 2746 * driver_data member. 2747 * 2748 * The makeup of these names are: 2749 * pbn_bn{_bt}_n_baud{_offsetinhex} 2750 * 2751 * bn = PCI BAR number 2752 * bt = Index using PCI BARs 2753 * n = number of serial ports 2754 * baud = baud rate 2755 * offsetinhex = offset for each sequential port (in hex) 2756 * 2757 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2758 * 2759 * Please note: in theory if n = 1, _bt infix should make no difference. 2760 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2761 */ 2762 enum pci_board_num_t { 2763 pbn_default = 0, 2764 2765 pbn_b0_1_115200, 2766 pbn_b0_2_115200, 2767 pbn_b0_4_115200, 2768 pbn_b0_5_115200, 2769 pbn_b0_8_115200, 2770 2771 pbn_b0_1_921600, 2772 pbn_b0_2_921600, 2773 pbn_b0_4_921600, 2774 2775 pbn_b0_2_1130000, 2776 2777 pbn_b0_4_1152000, 2778 2779 pbn_b0_4_1250000, 2780 2781 pbn_b0_2_1843200, 2782 pbn_b0_4_1843200, 2783 2784 pbn_b0_1_15625000, 2785 2786 pbn_b0_bt_1_115200, 2787 pbn_b0_bt_2_115200, 2788 pbn_b0_bt_4_115200, 2789 pbn_b0_bt_8_115200, 2790 2791 pbn_b0_bt_1_460800, 2792 pbn_b0_bt_2_460800, 2793 pbn_b0_bt_4_460800, 2794 2795 pbn_b0_bt_1_921600, 2796 pbn_b0_bt_2_921600, 2797 pbn_b0_bt_4_921600, 2798 pbn_b0_bt_8_921600, 2799 2800 pbn_b1_1_115200, 2801 pbn_b1_2_115200, 2802 pbn_b1_4_115200, 2803 pbn_b1_8_115200, 2804 pbn_b1_16_115200, 2805 2806 pbn_b1_1_921600, 2807 pbn_b1_2_921600, 2808 pbn_b1_4_921600, 2809 pbn_b1_8_921600, 2810 2811 pbn_b1_2_1250000, 2812 2813 pbn_b1_bt_1_115200, 2814 pbn_b1_bt_2_115200, 2815 pbn_b1_bt_4_115200, 2816 2817 pbn_b1_bt_2_921600, 2818 2819 pbn_b1_1_1382400, 2820 pbn_b1_2_1382400, 2821 pbn_b1_4_1382400, 2822 pbn_b1_8_1382400, 2823 2824 pbn_b2_1_115200, 2825 pbn_b2_2_115200, 2826 pbn_b2_4_115200, 2827 pbn_b2_8_115200, 2828 2829 pbn_b2_1_460800, 2830 pbn_b2_4_460800, 2831 pbn_b2_8_460800, 2832 pbn_b2_16_460800, 2833 2834 pbn_b2_1_921600, 2835 pbn_b2_4_921600, 2836 pbn_b2_8_921600, 2837 2838 pbn_b2_8_1152000, 2839 2840 pbn_b2_bt_1_115200, 2841 pbn_b2_bt_2_115200, 2842 pbn_b2_bt_4_115200, 2843 2844 pbn_b2_bt_2_921600, 2845 pbn_b2_bt_4_921600, 2846 2847 pbn_b3_2_115200, 2848 pbn_b3_4_115200, 2849 pbn_b3_8_115200, 2850 2851 pbn_b4_bt_2_921600, 2852 pbn_b4_bt_4_921600, 2853 pbn_b4_bt_8_921600, 2854 2855 /* 2856 * Board-specific versions. 2857 */ 2858 pbn_panacom, 2859 pbn_panacom2, 2860 pbn_panacom4, 2861 pbn_plx_romulus, 2862 pbn_oxsemi, 2863 pbn_oxsemi_1_15625000, 2864 pbn_oxsemi_2_15625000, 2865 pbn_oxsemi_4_15625000, 2866 pbn_oxsemi_8_15625000, 2867 pbn_intel_i960, 2868 pbn_sgi_ioc3, 2869 pbn_computone_4, 2870 pbn_computone_6, 2871 pbn_computone_8, 2872 pbn_sbsxrsio, 2873 pbn_pasemi_1682M, 2874 pbn_ni8430_2, 2875 pbn_ni8430_4, 2876 pbn_ni8430_8, 2877 pbn_ni8430_16, 2878 pbn_ADDIDATA_PCIe_1_3906250, 2879 pbn_ADDIDATA_PCIe_2_3906250, 2880 pbn_ADDIDATA_PCIe_4_3906250, 2881 pbn_ADDIDATA_PCIe_8_3906250, 2882 pbn_ce4100_1_115200, 2883 pbn_omegapci, 2884 pbn_NETMOS9900_2s_115200, 2885 pbn_brcm_trumanage, 2886 pbn_fintek_4, 2887 pbn_fintek_8, 2888 pbn_fintek_12, 2889 pbn_fintek_F81504A, 2890 pbn_fintek_F81508A, 2891 pbn_fintek_F81512A, 2892 pbn_wch382_2, 2893 pbn_wch384_4, 2894 pbn_wch384_8, 2895 pbn_sunix_pci_1s, 2896 pbn_sunix_pci_2s, 2897 pbn_sunix_pci_4s, 2898 pbn_sunix_pci_8s, 2899 pbn_sunix_pci_16s, 2900 pbn_titan_1_4000000, 2901 pbn_titan_2_4000000, 2902 pbn_titan_4_4000000, 2903 pbn_titan_8_4000000, 2904 pbn_moxa8250_2p, 2905 pbn_moxa8250_4p, 2906 pbn_moxa8250_8p, 2907 }; 2908 2909 /* 2910 * uart_offset - the space between channels 2911 * reg_shift - describes how the UART registers are mapped 2912 * to PCI memory by the card. 2913 * For example IER register on SBS, Inc. PMC-OctPro is located at 2914 * offset 0x10 from the UART base, while UART_IER is defined as 1 2915 * in include/linux/serial_reg.h, 2916 * see first lines of serial_in() and serial_out() in 8250.c 2917 */ 2918 2919 static struct pciserial_board pci_boards[] = { 2920 [pbn_default] = { 2921 .flags = FL_BASE0, 2922 .num_ports = 1, 2923 .base_baud = 115200, 2924 .uart_offset = 8, 2925 }, 2926 [pbn_b0_1_115200] = { 2927 .flags = FL_BASE0, 2928 .num_ports = 1, 2929 .base_baud = 115200, 2930 .uart_offset = 8, 2931 }, 2932 [pbn_b0_2_115200] = { 2933 .flags = FL_BASE0, 2934 .num_ports = 2, 2935 .base_baud = 115200, 2936 .uart_offset = 8, 2937 }, 2938 [pbn_b0_4_115200] = { 2939 .flags = FL_BASE0, 2940 .num_ports = 4, 2941 .base_baud = 115200, 2942 .uart_offset = 8, 2943 }, 2944 [pbn_b0_5_115200] = { 2945 .flags = FL_BASE0, 2946 .num_ports = 5, 2947 .base_baud = 115200, 2948 .uart_offset = 8, 2949 }, 2950 [pbn_b0_8_115200] = { 2951 .flags = FL_BASE0, 2952 .num_ports = 8, 2953 .base_baud = 115200, 2954 .uart_offset = 8, 2955 }, 2956 [pbn_b0_1_921600] = { 2957 .flags = FL_BASE0, 2958 .num_ports = 1, 2959 .base_baud = 921600, 2960 .uart_offset = 8, 2961 }, 2962 [pbn_b0_2_921600] = { 2963 .flags = FL_BASE0, 2964 .num_ports = 2, 2965 .base_baud = 921600, 2966 .uart_offset = 8, 2967 }, 2968 [pbn_b0_4_921600] = { 2969 .flags = FL_BASE0, 2970 .num_ports = 4, 2971 .base_baud = 921600, 2972 .uart_offset = 8, 2973 }, 2974 2975 [pbn_b0_2_1130000] = { 2976 .flags = FL_BASE0, 2977 .num_ports = 2, 2978 .base_baud = 1130000, 2979 .uart_offset = 8, 2980 }, 2981 2982 [pbn_b0_4_1152000] = { 2983 .flags = FL_BASE0, 2984 .num_ports = 4, 2985 .base_baud = 1152000, 2986 .uart_offset = 8, 2987 }, 2988 2989 [pbn_b0_4_1250000] = { 2990 .flags = FL_BASE0, 2991 .num_ports = 4, 2992 .base_baud = 1250000, 2993 .uart_offset = 8, 2994 }, 2995 2996 [pbn_b0_2_1843200] = { 2997 .flags = FL_BASE0, 2998 .num_ports = 2, 2999 .base_baud = 1843200, 3000 .uart_offset = 8, 3001 }, 3002 [pbn_b0_4_1843200] = { 3003 .flags = FL_BASE0, 3004 .num_ports = 4, 3005 .base_baud = 1843200, 3006 .uart_offset = 8, 3007 }, 3008 3009 [pbn_b0_1_15625000] = { 3010 .flags = FL_BASE0, 3011 .num_ports = 1, 3012 .base_baud = 15625000, 3013 .uart_offset = 8, 3014 }, 3015 3016 [pbn_b0_bt_1_115200] = { 3017 .flags = FL_BASE0|FL_BASE_BARS, 3018 .num_ports = 1, 3019 .base_baud = 115200, 3020 .uart_offset = 8, 3021 }, 3022 [pbn_b0_bt_2_115200] = { 3023 .flags = FL_BASE0|FL_BASE_BARS, 3024 .num_ports = 2, 3025 .base_baud = 115200, 3026 .uart_offset = 8, 3027 }, 3028 [pbn_b0_bt_4_115200] = { 3029 .flags = FL_BASE0|FL_BASE_BARS, 3030 .num_ports = 4, 3031 .base_baud = 115200, 3032 .uart_offset = 8, 3033 }, 3034 [pbn_b0_bt_8_115200] = { 3035 .flags = FL_BASE0|FL_BASE_BARS, 3036 .num_ports = 8, 3037 .base_baud = 115200, 3038 .uart_offset = 8, 3039 }, 3040 3041 [pbn_b0_bt_1_460800] = { 3042 .flags = FL_BASE0|FL_BASE_BARS, 3043 .num_ports = 1, 3044 .base_baud = 460800, 3045 .uart_offset = 8, 3046 }, 3047 [pbn_b0_bt_2_460800] = { 3048 .flags = FL_BASE0|FL_BASE_BARS, 3049 .num_ports = 2, 3050 .base_baud = 460800, 3051 .uart_offset = 8, 3052 }, 3053 [pbn_b0_bt_4_460800] = { 3054 .flags = FL_BASE0|FL_BASE_BARS, 3055 .num_ports = 4, 3056 .base_baud = 460800, 3057 .uart_offset = 8, 3058 }, 3059 3060 [pbn_b0_bt_1_921600] = { 3061 .flags = FL_BASE0|FL_BASE_BARS, 3062 .num_ports = 1, 3063 .base_baud = 921600, 3064 .uart_offset = 8, 3065 }, 3066 [pbn_b0_bt_2_921600] = { 3067 .flags = FL_BASE0|FL_BASE_BARS, 3068 .num_ports = 2, 3069 .base_baud = 921600, 3070 .uart_offset = 8, 3071 }, 3072 [pbn_b0_bt_4_921600] = { 3073 .flags = FL_BASE0|FL_BASE_BARS, 3074 .num_ports = 4, 3075 .base_baud = 921600, 3076 .uart_offset = 8, 3077 }, 3078 [pbn_b0_bt_8_921600] = { 3079 .flags = FL_BASE0|FL_BASE_BARS, 3080 .num_ports = 8, 3081 .base_baud = 921600, 3082 .uart_offset = 8, 3083 }, 3084 3085 [pbn_b1_1_115200] = { 3086 .flags = FL_BASE1, 3087 .num_ports = 1, 3088 .base_baud = 115200, 3089 .uart_offset = 8, 3090 }, 3091 [pbn_b1_2_115200] = { 3092 .flags = FL_BASE1, 3093 .num_ports = 2, 3094 .base_baud = 115200, 3095 .uart_offset = 8, 3096 }, 3097 [pbn_b1_4_115200] = { 3098 .flags = FL_BASE1, 3099 .num_ports = 4, 3100 .base_baud = 115200, 3101 .uart_offset = 8, 3102 }, 3103 [pbn_b1_8_115200] = { 3104 .flags = FL_BASE1, 3105 .num_ports = 8, 3106 .base_baud = 115200, 3107 .uart_offset = 8, 3108 }, 3109 [pbn_b1_16_115200] = { 3110 .flags = FL_BASE1, 3111 .num_ports = 16, 3112 .base_baud = 115200, 3113 .uart_offset = 8, 3114 }, 3115 3116 [pbn_b1_1_921600] = { 3117 .flags = FL_BASE1, 3118 .num_ports = 1, 3119 .base_baud = 921600, 3120 .uart_offset = 8, 3121 }, 3122 [pbn_b1_2_921600] = { 3123 .flags = FL_BASE1, 3124 .num_ports = 2, 3125 .base_baud = 921600, 3126 .uart_offset = 8, 3127 }, 3128 [pbn_b1_4_921600] = { 3129 .flags = FL_BASE1, 3130 .num_ports = 4, 3131 .base_baud = 921600, 3132 .uart_offset = 8, 3133 }, 3134 [pbn_b1_8_921600] = { 3135 .flags = FL_BASE1, 3136 .num_ports = 8, 3137 .base_baud = 921600, 3138 .uart_offset = 8, 3139 }, 3140 [pbn_b1_2_1250000] = { 3141 .flags = FL_BASE1, 3142 .num_ports = 2, 3143 .base_baud = 1250000, 3144 .uart_offset = 8, 3145 }, 3146 3147 [pbn_b1_bt_1_115200] = { 3148 .flags = FL_BASE1|FL_BASE_BARS, 3149 .num_ports = 1, 3150 .base_baud = 115200, 3151 .uart_offset = 8, 3152 }, 3153 [pbn_b1_bt_2_115200] = { 3154 .flags = FL_BASE1|FL_BASE_BARS, 3155 .num_ports = 2, 3156 .base_baud = 115200, 3157 .uart_offset = 8, 3158 }, 3159 [pbn_b1_bt_4_115200] = { 3160 .flags = FL_BASE1|FL_BASE_BARS, 3161 .num_ports = 4, 3162 .base_baud = 115200, 3163 .uart_offset = 8, 3164 }, 3165 3166 [pbn_b1_bt_2_921600] = { 3167 .flags = FL_BASE1|FL_BASE_BARS, 3168 .num_ports = 2, 3169 .base_baud = 921600, 3170 .uart_offset = 8, 3171 }, 3172 3173 [pbn_b1_1_1382400] = { 3174 .flags = FL_BASE1, 3175 .num_ports = 1, 3176 .base_baud = 1382400, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b1_2_1382400] = { 3180 .flags = FL_BASE1, 3181 .num_ports = 2, 3182 .base_baud = 1382400, 3183 .uart_offset = 8, 3184 }, 3185 [pbn_b1_4_1382400] = { 3186 .flags = FL_BASE1, 3187 .num_ports = 4, 3188 .base_baud = 1382400, 3189 .uart_offset = 8, 3190 }, 3191 [pbn_b1_8_1382400] = { 3192 .flags = FL_BASE1, 3193 .num_ports = 8, 3194 .base_baud = 1382400, 3195 .uart_offset = 8, 3196 }, 3197 3198 [pbn_b2_1_115200] = { 3199 .flags = FL_BASE2, 3200 .num_ports = 1, 3201 .base_baud = 115200, 3202 .uart_offset = 8, 3203 }, 3204 [pbn_b2_2_115200] = { 3205 .flags = FL_BASE2, 3206 .num_ports = 2, 3207 .base_baud = 115200, 3208 .uart_offset = 8, 3209 }, 3210 [pbn_b2_4_115200] = { 3211 .flags = FL_BASE2, 3212 .num_ports = 4, 3213 .base_baud = 115200, 3214 .uart_offset = 8, 3215 }, 3216 [pbn_b2_8_115200] = { 3217 .flags = FL_BASE2, 3218 .num_ports = 8, 3219 .base_baud = 115200, 3220 .uart_offset = 8, 3221 }, 3222 3223 [pbn_b2_1_460800] = { 3224 .flags = FL_BASE2, 3225 .num_ports = 1, 3226 .base_baud = 460800, 3227 .uart_offset = 8, 3228 }, 3229 [pbn_b2_4_460800] = { 3230 .flags = FL_BASE2, 3231 .num_ports = 4, 3232 .base_baud = 460800, 3233 .uart_offset = 8, 3234 }, 3235 [pbn_b2_8_460800] = { 3236 .flags = FL_BASE2, 3237 .num_ports = 8, 3238 .base_baud = 460800, 3239 .uart_offset = 8, 3240 }, 3241 [pbn_b2_16_460800] = { 3242 .flags = FL_BASE2, 3243 .num_ports = 16, 3244 .base_baud = 460800, 3245 .uart_offset = 8, 3246 }, 3247 3248 [pbn_b2_1_921600] = { 3249 .flags = FL_BASE2, 3250 .num_ports = 1, 3251 .base_baud = 921600, 3252 .uart_offset = 8, 3253 }, 3254 [pbn_b2_4_921600] = { 3255 .flags = FL_BASE2, 3256 .num_ports = 4, 3257 .base_baud = 921600, 3258 .uart_offset = 8, 3259 }, 3260 [pbn_b2_8_921600] = { 3261 .flags = FL_BASE2, 3262 .num_ports = 8, 3263 .base_baud = 921600, 3264 .uart_offset = 8, 3265 }, 3266 3267 [pbn_b2_8_1152000] = { 3268 .flags = FL_BASE2, 3269 .num_ports = 8, 3270 .base_baud = 1152000, 3271 .uart_offset = 8, 3272 }, 3273 3274 [pbn_b2_bt_1_115200] = { 3275 .flags = FL_BASE2|FL_BASE_BARS, 3276 .num_ports = 1, 3277 .base_baud = 115200, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b2_bt_2_115200] = { 3281 .flags = FL_BASE2|FL_BASE_BARS, 3282 .num_ports = 2, 3283 .base_baud = 115200, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b2_bt_4_115200] = { 3287 .flags = FL_BASE2|FL_BASE_BARS, 3288 .num_ports = 4, 3289 .base_baud = 115200, 3290 .uart_offset = 8, 3291 }, 3292 3293 [pbn_b2_bt_2_921600] = { 3294 .flags = FL_BASE2|FL_BASE_BARS, 3295 .num_ports = 2, 3296 .base_baud = 921600, 3297 .uart_offset = 8, 3298 }, 3299 [pbn_b2_bt_4_921600] = { 3300 .flags = FL_BASE2|FL_BASE_BARS, 3301 .num_ports = 4, 3302 .base_baud = 921600, 3303 .uart_offset = 8, 3304 }, 3305 3306 [pbn_b3_2_115200] = { 3307 .flags = FL_BASE3, 3308 .num_ports = 2, 3309 .base_baud = 115200, 3310 .uart_offset = 8, 3311 }, 3312 [pbn_b3_4_115200] = { 3313 .flags = FL_BASE3, 3314 .num_ports = 4, 3315 .base_baud = 115200, 3316 .uart_offset = 8, 3317 }, 3318 [pbn_b3_8_115200] = { 3319 .flags = FL_BASE3, 3320 .num_ports = 8, 3321 .base_baud = 115200, 3322 .uart_offset = 8, 3323 }, 3324 3325 [pbn_b4_bt_2_921600] = { 3326 .flags = FL_BASE4, 3327 .num_ports = 2, 3328 .base_baud = 921600, 3329 .uart_offset = 8, 3330 }, 3331 [pbn_b4_bt_4_921600] = { 3332 .flags = FL_BASE4, 3333 .num_ports = 4, 3334 .base_baud = 921600, 3335 .uart_offset = 8, 3336 }, 3337 [pbn_b4_bt_8_921600] = { 3338 .flags = FL_BASE4, 3339 .num_ports = 8, 3340 .base_baud = 921600, 3341 .uart_offset = 8, 3342 }, 3343 3344 /* 3345 * Entries following this are board-specific. 3346 */ 3347 3348 /* 3349 * Panacom - IOMEM 3350 */ 3351 [pbn_panacom] = { 3352 .flags = FL_BASE2, 3353 .num_ports = 2, 3354 .base_baud = 921600, 3355 .uart_offset = 0x400, 3356 .reg_shift = 7, 3357 }, 3358 [pbn_panacom2] = { 3359 .flags = FL_BASE2|FL_BASE_BARS, 3360 .num_ports = 2, 3361 .base_baud = 921600, 3362 .uart_offset = 0x400, 3363 .reg_shift = 7, 3364 }, 3365 [pbn_panacom4] = { 3366 .flags = FL_BASE2|FL_BASE_BARS, 3367 .num_ports = 4, 3368 .base_baud = 921600, 3369 .uart_offset = 0x400, 3370 .reg_shift = 7, 3371 }, 3372 3373 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3374 [pbn_plx_romulus] = { 3375 .flags = FL_BASE2, 3376 .num_ports = 4, 3377 .base_baud = 921600, 3378 .uart_offset = 8 << 2, 3379 .reg_shift = 2, 3380 .first_offset = 0x03, 3381 }, 3382 3383 /* 3384 * This board uses the size of PCI Base region 0 to 3385 * signal now many ports are available 3386 */ 3387 [pbn_oxsemi] = { 3388 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3389 .num_ports = 32, 3390 .base_baud = 115200, 3391 .uart_offset = 8, 3392 }, 3393 [pbn_oxsemi_1_15625000] = { 3394 .flags = FL_BASE0, 3395 .num_ports = 1, 3396 .base_baud = 15625000, 3397 .uart_offset = 0x200, 3398 .first_offset = 0x1000, 3399 }, 3400 [pbn_oxsemi_2_15625000] = { 3401 .flags = FL_BASE0, 3402 .num_ports = 2, 3403 .base_baud = 15625000, 3404 .uart_offset = 0x200, 3405 .first_offset = 0x1000, 3406 }, 3407 [pbn_oxsemi_4_15625000] = { 3408 .flags = FL_BASE0, 3409 .num_ports = 4, 3410 .base_baud = 15625000, 3411 .uart_offset = 0x200, 3412 .first_offset = 0x1000, 3413 }, 3414 [pbn_oxsemi_8_15625000] = { 3415 .flags = FL_BASE0, 3416 .num_ports = 8, 3417 .base_baud = 15625000, 3418 .uart_offset = 0x200, 3419 .first_offset = 0x1000, 3420 }, 3421 3422 3423 /* 3424 * EKF addition for i960 Boards form EKF with serial port. 3425 * Max 256 ports. 3426 */ 3427 [pbn_intel_i960] = { 3428 .flags = FL_BASE0, 3429 .num_ports = 32, 3430 .base_baud = 921600, 3431 .uart_offset = 8 << 2, 3432 .reg_shift = 2, 3433 .first_offset = 0x10000, 3434 }, 3435 [pbn_sgi_ioc3] = { 3436 .flags = FL_BASE0|FL_NOIRQ, 3437 .num_ports = 1, 3438 .base_baud = 458333, 3439 .uart_offset = 8, 3440 .reg_shift = 0, 3441 .first_offset = 0x20178, 3442 }, 3443 3444 /* 3445 * Computone - uses IOMEM. 3446 */ 3447 [pbn_computone_4] = { 3448 .flags = FL_BASE0, 3449 .num_ports = 4, 3450 .base_baud = 921600, 3451 .uart_offset = 0x40, 3452 .reg_shift = 2, 3453 .first_offset = 0x200, 3454 }, 3455 [pbn_computone_6] = { 3456 .flags = FL_BASE0, 3457 .num_ports = 6, 3458 .base_baud = 921600, 3459 .uart_offset = 0x40, 3460 .reg_shift = 2, 3461 .first_offset = 0x200, 3462 }, 3463 [pbn_computone_8] = { 3464 .flags = FL_BASE0, 3465 .num_ports = 8, 3466 .base_baud = 921600, 3467 .uart_offset = 0x40, 3468 .reg_shift = 2, 3469 .first_offset = 0x200, 3470 }, 3471 [pbn_sbsxrsio] = { 3472 .flags = FL_BASE0, 3473 .num_ports = 8, 3474 .base_baud = 460800, 3475 .uart_offset = 256, 3476 .reg_shift = 4, 3477 }, 3478 /* 3479 * PA Semi PWRficient PA6T-1682M on-chip UART 3480 */ 3481 [pbn_pasemi_1682M] = { 3482 .flags = FL_BASE0, 3483 .num_ports = 1, 3484 .base_baud = 8333333, 3485 }, 3486 /* 3487 * National Instruments 843x 3488 */ 3489 [pbn_ni8430_16] = { 3490 .flags = FL_BASE0, 3491 .num_ports = 16, 3492 .base_baud = 3686400, 3493 .uart_offset = 0x10, 3494 .first_offset = 0x800, 3495 }, 3496 [pbn_ni8430_8] = { 3497 .flags = FL_BASE0, 3498 .num_ports = 8, 3499 .base_baud = 3686400, 3500 .uart_offset = 0x10, 3501 .first_offset = 0x800, 3502 }, 3503 [pbn_ni8430_4] = { 3504 .flags = FL_BASE0, 3505 .num_ports = 4, 3506 .base_baud = 3686400, 3507 .uart_offset = 0x10, 3508 .first_offset = 0x800, 3509 }, 3510 [pbn_ni8430_2] = { 3511 .flags = FL_BASE0, 3512 .num_ports = 2, 3513 .base_baud = 3686400, 3514 .uart_offset = 0x10, 3515 .first_offset = 0x800, 3516 }, 3517 /* 3518 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3519 */ 3520 [pbn_ADDIDATA_PCIe_1_3906250] = { 3521 .flags = FL_BASE0, 3522 .num_ports = 1, 3523 .base_baud = 3906250, 3524 .uart_offset = 0x200, 3525 .first_offset = 0x1000, 3526 }, 3527 [pbn_ADDIDATA_PCIe_2_3906250] = { 3528 .flags = FL_BASE0, 3529 .num_ports = 2, 3530 .base_baud = 3906250, 3531 .uart_offset = 0x200, 3532 .first_offset = 0x1000, 3533 }, 3534 [pbn_ADDIDATA_PCIe_4_3906250] = { 3535 .flags = FL_BASE0, 3536 .num_ports = 4, 3537 .base_baud = 3906250, 3538 .uart_offset = 0x200, 3539 .first_offset = 0x1000, 3540 }, 3541 [pbn_ADDIDATA_PCIe_8_3906250] = { 3542 .flags = FL_BASE0, 3543 .num_ports = 8, 3544 .base_baud = 3906250, 3545 .uart_offset = 0x200, 3546 .first_offset = 0x1000, 3547 }, 3548 [pbn_ce4100_1_115200] = { 3549 .flags = FL_BASE_BARS, 3550 .num_ports = 2, 3551 .base_baud = 921600, 3552 .reg_shift = 2, 3553 }, 3554 [pbn_omegapci] = { 3555 .flags = FL_BASE0, 3556 .num_ports = 8, 3557 .base_baud = 115200, 3558 .uart_offset = 0x200, 3559 }, 3560 [pbn_NETMOS9900_2s_115200] = { 3561 .flags = FL_BASE0, 3562 .num_ports = 2, 3563 .base_baud = 115200, 3564 }, 3565 [pbn_brcm_trumanage] = { 3566 .flags = FL_BASE0, 3567 .num_ports = 1, 3568 .reg_shift = 2, 3569 .base_baud = 115200, 3570 }, 3571 [pbn_fintek_4] = { 3572 .num_ports = 4, 3573 .uart_offset = 8, 3574 .base_baud = 115200, 3575 .first_offset = 0x40, 3576 }, 3577 [pbn_fintek_8] = { 3578 .num_ports = 8, 3579 .uart_offset = 8, 3580 .base_baud = 115200, 3581 .first_offset = 0x40, 3582 }, 3583 [pbn_fintek_12] = { 3584 .num_ports = 12, 3585 .uart_offset = 8, 3586 .base_baud = 115200, 3587 .first_offset = 0x40, 3588 }, 3589 [pbn_fintek_F81504A] = { 3590 .num_ports = 4, 3591 .uart_offset = 8, 3592 .base_baud = 115200, 3593 }, 3594 [pbn_fintek_F81508A] = { 3595 .num_ports = 8, 3596 .uart_offset = 8, 3597 .base_baud = 115200, 3598 }, 3599 [pbn_fintek_F81512A] = { 3600 .num_ports = 12, 3601 .uart_offset = 8, 3602 .base_baud = 115200, 3603 }, 3604 [pbn_wch382_2] = { 3605 .flags = FL_BASE0, 3606 .num_ports = 2, 3607 .base_baud = 115200, 3608 .uart_offset = 8, 3609 .first_offset = 0xC0, 3610 }, 3611 [pbn_wch384_4] = { 3612 .flags = FL_BASE0, 3613 .num_ports = 4, 3614 .base_baud = 115200, 3615 .uart_offset = 8, 3616 .first_offset = 0xC0, 3617 }, 3618 [pbn_wch384_8] = { 3619 .flags = FL_BASE0, 3620 .num_ports = 8, 3621 .base_baud = 115200, 3622 .uart_offset = 8, 3623 .first_offset = 0x00, 3624 }, 3625 [pbn_sunix_pci_1s] = { 3626 .num_ports = 1, 3627 .base_baud = 921600, 3628 .uart_offset = 0x8, 3629 }, 3630 [pbn_sunix_pci_2s] = { 3631 .num_ports = 2, 3632 .base_baud = 921600, 3633 .uart_offset = 0x8, 3634 }, 3635 [pbn_sunix_pci_4s] = { 3636 .num_ports = 4, 3637 .base_baud = 921600, 3638 .uart_offset = 0x8, 3639 }, 3640 [pbn_sunix_pci_8s] = { 3641 .num_ports = 8, 3642 .base_baud = 921600, 3643 .uart_offset = 0x8, 3644 }, 3645 [pbn_sunix_pci_16s] = { 3646 .num_ports = 16, 3647 .base_baud = 921600, 3648 .uart_offset = 0x8, 3649 }, 3650 [pbn_titan_1_4000000] = { 3651 .flags = FL_BASE0, 3652 .num_ports = 1, 3653 .base_baud = 4000000, 3654 .uart_offset = 0x200, 3655 .first_offset = 0x1000, 3656 }, 3657 [pbn_titan_2_4000000] = { 3658 .flags = FL_BASE0, 3659 .num_ports = 2, 3660 .base_baud = 4000000, 3661 .uart_offset = 0x200, 3662 .first_offset = 0x1000, 3663 }, 3664 [pbn_titan_4_4000000] = { 3665 .flags = FL_BASE0, 3666 .num_ports = 4, 3667 .base_baud = 4000000, 3668 .uart_offset = 0x200, 3669 .first_offset = 0x1000, 3670 }, 3671 [pbn_titan_8_4000000] = { 3672 .flags = FL_BASE0, 3673 .num_ports = 8, 3674 .base_baud = 4000000, 3675 .uart_offset = 0x200, 3676 .first_offset = 0x1000, 3677 }, 3678 [pbn_moxa8250_2p] = { 3679 .flags = FL_BASE1, 3680 .num_ports = 2, 3681 .base_baud = 921600, 3682 .uart_offset = 0x200, 3683 }, 3684 [pbn_moxa8250_4p] = { 3685 .flags = FL_BASE1, 3686 .num_ports = 4, 3687 .base_baud = 921600, 3688 .uart_offset = 0x200, 3689 }, 3690 [pbn_moxa8250_8p] = { 3691 .flags = FL_BASE1, 3692 .num_ports = 8, 3693 .base_baud = 921600, 3694 .uart_offset = 0x200, 3695 }, 3696 }; 3697 3698 #define REPORT_CONFIG(option) \ 3699 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3700 #define REPORT_8250_CONFIG(option) \ 3701 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3702 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3703 3704 static const struct pci_device_id blacklist[] = { 3705 /* softmodems */ 3706 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3707 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3708 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3709 3710 /* multi-io cards handled by parport_serial */ 3711 /* WCH CH353 2S1P */ 3712 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3713 /* WCH CH353 1S1P */ 3714 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3715 /* WCH CH382 2S1P */ 3716 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3717 3718 /* Intel platforms with MID UART */ 3719 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3720 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3721 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3722 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3723 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3724 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3725 3726 /* Intel platforms with DesignWare UART */ 3727 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3728 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3729 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3730 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3731 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3732 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3733 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3734 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3735 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3736 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3737 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3738 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3739 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3740 3741 /* Exar devices */ 3742 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3743 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3744 3745 /* Pericom devices */ 3746 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3747 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3748 3749 /* End of the black list */ 3750 { } 3751 }; 3752 3753 static int serial_pci_is_class_communication(struct pci_dev *dev) 3754 { 3755 /* 3756 * If it is not a communications device or the programming 3757 * interface is greater than 6, give up. 3758 */ 3759 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3760 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3761 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3762 (dev->class & 0xff) > 6) 3763 return -ENODEV; 3764 3765 return 0; 3766 } 3767 3768 /* 3769 * Given a complete unknown PCI device, try to use some heuristics to 3770 * guess what the configuration might be, based on the pitiful PCI 3771 * serial specs. Returns 0 on success, -ENODEV on failure. 3772 */ 3773 static int 3774 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3775 { 3776 int num_iomem, num_port, first_port = -1, i; 3777 int rc; 3778 3779 rc = serial_pci_is_class_communication(dev); 3780 if (rc) 3781 return rc; 3782 3783 /* 3784 * Should we try to make guesses for multiport serial devices later? 3785 */ 3786 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3787 return -ENODEV; 3788 3789 num_iomem = num_port = 0; 3790 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3791 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3792 num_port++; 3793 if (first_port == -1) 3794 first_port = i; 3795 } 3796 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3797 num_iomem++; 3798 } 3799 3800 /* 3801 * If there is 1 or 0 iomem regions, and exactly one port, 3802 * use it. We guess the number of ports based on the IO 3803 * region size. 3804 */ 3805 if (num_iomem <= 1 && num_port == 1) { 3806 board->flags = first_port; 3807 board->num_ports = pci_resource_len(dev, first_port) / 8; 3808 return 0; 3809 } 3810 3811 /* 3812 * Now guess if we've got a board which indexes by BARs. 3813 * Each IO BAR should be 8 bytes, and they should follow 3814 * consecutively. 3815 */ 3816 first_port = -1; 3817 num_port = 0; 3818 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3819 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3820 pci_resource_len(dev, i) == 8 && 3821 (first_port == -1 || (first_port + num_port) == i)) { 3822 num_port++; 3823 if (first_port == -1) 3824 first_port = i; 3825 } 3826 } 3827 3828 if (num_port > 1) { 3829 board->flags = first_port | FL_BASE_BARS; 3830 board->num_ports = num_port; 3831 return 0; 3832 } 3833 3834 return -ENODEV; 3835 } 3836 3837 static inline int 3838 serial_pci_matches(const struct pciserial_board *board, 3839 const struct pciserial_board *guessed) 3840 { 3841 return 3842 board->num_ports == guessed->num_ports && 3843 board->base_baud == guessed->base_baud && 3844 board->uart_offset == guessed->uart_offset && 3845 board->reg_shift == guessed->reg_shift && 3846 board->first_offset == guessed->first_offset; 3847 } 3848 3849 struct serial_private * 3850 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3851 { 3852 struct uart_8250_port uart; 3853 struct serial_private *priv; 3854 struct pci_serial_quirk *quirk; 3855 int rc, nr_ports, i; 3856 3857 nr_ports = board->num_ports; 3858 3859 /* 3860 * Find an init and setup quirks. 3861 */ 3862 quirk = find_quirk(dev); 3863 3864 /* 3865 * Run the new-style initialization function. 3866 * The initialization function returns: 3867 * <0 - error 3868 * 0 - use board->num_ports 3869 * >0 - number of ports 3870 */ 3871 if (quirk->init) { 3872 rc = quirk->init(dev); 3873 if (rc < 0) { 3874 priv = ERR_PTR(rc); 3875 goto err_out; 3876 } 3877 if (rc) 3878 nr_ports = rc; 3879 } 3880 3881 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3882 if (!priv) { 3883 priv = ERR_PTR(-ENOMEM); 3884 goto err_deinit; 3885 } 3886 3887 priv->dev = dev; 3888 priv->quirk = quirk; 3889 3890 memset(&uart, 0, sizeof(uart)); 3891 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3892 uart.port.uartclk = board->base_baud * 16; 3893 3894 if (board->flags & FL_NOIRQ) { 3895 uart.port.irq = 0; 3896 } else { 3897 if (pci_match_id(pci_use_msi, dev)) { 3898 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3899 pci_set_master(dev); 3900 uart.port.flags &= ~UPF_SHARE_IRQ; 3901 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3902 } else { 3903 pci_dbg(dev, "Using legacy interrupts\n"); 3904 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3905 } 3906 if (rc < 0) { 3907 kfree(priv); 3908 priv = ERR_PTR(rc); 3909 goto err_deinit; 3910 } 3911 3912 uart.port.irq = pci_irq_vector(dev, 0); 3913 } 3914 3915 uart.port.dev = &dev->dev; 3916 3917 for (i = 0; i < nr_ports; i++) { 3918 if (quirk->setup(priv, board, &uart, i)) 3919 break; 3920 3921 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3922 uart.port.iobase, uart.port.irq, uart.port.iotype); 3923 3924 priv->line[i] = serial8250_register_8250_port(&uart); 3925 if (priv->line[i] < 0) { 3926 pci_err(dev, 3927 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3928 uart.port.iobase, uart.port.irq, 3929 uart.port.iotype, priv->line[i]); 3930 break; 3931 } 3932 } 3933 priv->nr = i; 3934 priv->board = board; 3935 return priv; 3936 3937 err_deinit: 3938 if (quirk->exit) 3939 quirk->exit(dev); 3940 err_out: 3941 return priv; 3942 } 3943 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3944 3945 static void pciserial_detach_ports(struct serial_private *priv) 3946 { 3947 struct pci_serial_quirk *quirk; 3948 int i; 3949 3950 for (i = 0; i < priv->nr; i++) 3951 serial8250_unregister_port(priv->line[i]); 3952 3953 /* 3954 * Find the exit quirks. 3955 */ 3956 quirk = find_quirk(priv->dev); 3957 if (quirk->exit) 3958 quirk->exit(priv->dev); 3959 } 3960 3961 void pciserial_remove_ports(struct serial_private *priv) 3962 { 3963 pciserial_detach_ports(priv); 3964 kfree(priv); 3965 } 3966 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3967 3968 void pciserial_suspend_ports(struct serial_private *priv) 3969 { 3970 int i; 3971 3972 for (i = 0; i < priv->nr; i++) 3973 if (priv->line[i] >= 0) 3974 serial8250_suspend_port(priv->line[i]); 3975 3976 /* 3977 * Ensure that every init quirk is properly torn down 3978 */ 3979 if (priv->quirk->exit) 3980 priv->quirk->exit(priv->dev); 3981 } 3982 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3983 3984 void pciserial_resume_ports(struct serial_private *priv) 3985 { 3986 int i; 3987 3988 /* 3989 * Ensure that the board is correctly configured. 3990 */ 3991 if (priv->quirk->init) 3992 priv->quirk->init(priv->dev); 3993 3994 for (i = 0; i < priv->nr; i++) 3995 if (priv->line[i] >= 0) 3996 serial8250_resume_port(priv->line[i]); 3997 } 3998 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3999 4000 /* 4001 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4002 * to the arrangement of serial ports on a PCI card. 4003 */ 4004 static int 4005 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4006 { 4007 struct pci_serial_quirk *quirk; 4008 struct serial_private *priv; 4009 const struct pciserial_board *board; 4010 const struct pci_device_id *exclude; 4011 struct pciserial_board tmp; 4012 int rc; 4013 4014 quirk = find_quirk(dev); 4015 if (quirk->probe) { 4016 rc = quirk->probe(dev); 4017 if (rc) 4018 return rc; 4019 } 4020 4021 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4022 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4023 return -EINVAL; 4024 } 4025 4026 board = &pci_boards[ent->driver_data]; 4027 4028 exclude = pci_match_id(blacklist, dev); 4029 if (exclude) { 4030 if (exclude->driver_data) 4031 pci_warn(dev, "ignoring port, enable %s to handle\n", 4032 (const char *)exclude->driver_data); 4033 return -ENODEV; 4034 } 4035 4036 rc = pcim_enable_device(dev); 4037 pci_save_state(dev); 4038 if (rc) 4039 return rc; 4040 4041 if (ent->driver_data == pbn_default) { 4042 /* 4043 * Use a copy of the pci_board entry for this; 4044 * avoid changing entries in the table. 4045 */ 4046 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4047 board = &tmp; 4048 4049 /* 4050 * We matched one of our class entries. Try to 4051 * determine the parameters of this board. 4052 */ 4053 rc = serial_pci_guess_board(dev, &tmp); 4054 if (rc) 4055 return rc; 4056 } else { 4057 /* 4058 * We matched an explicit entry. If we are able to 4059 * detect this boards settings with our heuristic, 4060 * then we no longer need this entry. 4061 */ 4062 memcpy(&tmp, &pci_boards[pbn_default], 4063 sizeof(struct pciserial_board)); 4064 rc = serial_pci_guess_board(dev, &tmp); 4065 if (rc == 0 && serial_pci_matches(board, &tmp)) 4066 moan_device("Redundant entry in serial pci_table.", 4067 dev); 4068 } 4069 4070 priv = pciserial_init_ports(dev, board); 4071 if (IS_ERR(priv)) 4072 return PTR_ERR(priv); 4073 4074 pci_set_drvdata(dev, priv); 4075 return 0; 4076 } 4077 4078 static void pciserial_remove_one(struct pci_dev *dev) 4079 { 4080 struct serial_private *priv = pci_get_drvdata(dev); 4081 4082 pciserial_remove_ports(priv); 4083 } 4084 4085 #ifdef CONFIG_PM_SLEEP 4086 static int pciserial_suspend_one(struct device *dev) 4087 { 4088 struct serial_private *priv = dev_get_drvdata(dev); 4089 4090 if (priv) 4091 pciserial_suspend_ports(priv); 4092 4093 return 0; 4094 } 4095 4096 static int pciserial_resume_one(struct device *dev) 4097 { 4098 struct pci_dev *pdev = to_pci_dev(dev); 4099 struct serial_private *priv = pci_get_drvdata(pdev); 4100 int err; 4101 4102 if (priv) { 4103 /* 4104 * The device may have been disabled. Re-enable it. 4105 */ 4106 err = pci_enable_device(pdev); 4107 /* FIXME: We cannot simply error out here */ 4108 if (err) 4109 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4110 pciserial_resume_ports(priv); 4111 } 4112 return 0; 4113 } 4114 #endif 4115 4116 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4117 pciserial_resume_one); 4118 4119 static const struct pci_device_id serial_pci_tbl[] = { 4120 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4121 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4122 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4123 pbn_b2_8_921600 }, 4124 /* Advantech also use 0x3618 and 0xf618 */ 4125 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4126 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4127 pbn_b0_4_921600 }, 4128 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4129 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4130 pbn_b0_4_921600 }, 4131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4132 PCI_SUBVENDOR_ID_CONNECT_TECH, 4133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4134 pbn_b1_8_1382400 }, 4135 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4136 PCI_SUBVENDOR_ID_CONNECT_TECH, 4137 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4138 pbn_b1_4_1382400 }, 4139 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4140 PCI_SUBVENDOR_ID_CONNECT_TECH, 4141 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4142 pbn_b1_2_1382400 }, 4143 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4144 PCI_SUBVENDOR_ID_CONNECT_TECH, 4145 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4146 pbn_b1_8_1382400 }, 4147 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4148 PCI_SUBVENDOR_ID_CONNECT_TECH, 4149 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4150 pbn_b1_4_1382400 }, 4151 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4152 PCI_SUBVENDOR_ID_CONNECT_TECH, 4153 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4154 pbn_b1_2_1382400 }, 4155 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4156 PCI_SUBVENDOR_ID_CONNECT_TECH, 4157 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4158 pbn_b1_8_921600 }, 4159 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4160 PCI_SUBVENDOR_ID_CONNECT_TECH, 4161 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4162 pbn_b1_8_921600 }, 4163 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4164 PCI_SUBVENDOR_ID_CONNECT_TECH, 4165 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4166 pbn_b1_4_921600 }, 4167 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4168 PCI_SUBVENDOR_ID_CONNECT_TECH, 4169 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4170 pbn_b1_4_921600 }, 4171 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4172 PCI_SUBVENDOR_ID_CONNECT_TECH, 4173 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4174 pbn_b1_2_921600 }, 4175 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4176 PCI_SUBVENDOR_ID_CONNECT_TECH, 4177 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4178 pbn_b1_8_921600 }, 4179 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4180 PCI_SUBVENDOR_ID_CONNECT_TECH, 4181 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4182 pbn_b1_8_921600 }, 4183 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4184 PCI_SUBVENDOR_ID_CONNECT_TECH, 4185 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4186 pbn_b1_4_921600 }, 4187 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4188 PCI_SUBVENDOR_ID_CONNECT_TECH, 4189 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4190 pbn_b1_2_1250000 }, 4191 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4192 PCI_SUBVENDOR_ID_CONNECT_TECH, 4193 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4194 pbn_b0_2_1843200 }, 4195 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4196 PCI_SUBVENDOR_ID_CONNECT_TECH, 4197 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4198 pbn_b0_4_1843200 }, 4199 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4200 PCI_VENDOR_ID_AFAVLAB, 4201 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4202 pbn_b0_4_1152000 }, 4203 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b2_bt_1_115200 }, 4206 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4208 pbn_b2_bt_2_115200 }, 4209 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4211 pbn_b2_bt_4_115200 }, 4212 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4214 pbn_b2_bt_2_115200 }, 4215 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4217 pbn_b2_bt_4_115200 }, 4218 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4220 pbn_b2_8_115200 }, 4221 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4223 pbn_b2_8_460800 }, 4224 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4226 pbn_b2_8_115200 }, 4227 4228 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_b2_bt_2_115200 }, 4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4233 pbn_b2_bt_2_921600 }, 4234 /* 4235 * VScom SPCOM800, from sl@s.pl 4236 */ 4237 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4239 pbn_b2_8_921600 }, 4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4242 pbn_b2_4_921600 }, 4243 /* Unknown card - subdevice 0x1584 */ 4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4245 PCI_VENDOR_ID_PLX, 4246 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4247 pbn_b2_4_115200 }, 4248 /* Unknown card - subdevice 0x1588 */ 4249 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4250 PCI_VENDOR_ID_PLX, 4251 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4252 pbn_b2_8_115200 }, 4253 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4254 PCI_SUBVENDOR_ID_KEYSPAN, 4255 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4256 pbn_panacom }, 4257 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4259 pbn_panacom4 }, 4260 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4262 pbn_panacom2 }, 4263 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4264 PCI_VENDOR_ID_ESDGMBH, 4265 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4266 pbn_b2_4_115200 }, 4267 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4268 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4269 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4270 pbn_b2_4_460800 }, 4271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4272 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4273 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4274 pbn_b2_8_460800 }, 4275 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4276 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4277 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4278 pbn_b2_16_460800 }, 4279 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4280 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4281 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4282 pbn_b2_16_460800 }, 4283 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4284 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4285 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4286 pbn_b2_4_460800 }, 4287 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4288 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4289 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4290 pbn_b2_8_460800 }, 4291 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4292 PCI_SUBVENDOR_ID_EXSYS, 4293 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4294 pbn_b2_4_115200 }, 4295 /* 4296 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4297 * (Exoray@isys.ca) 4298 */ 4299 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4300 0x10b5, 0x106a, 0, 0, 4301 pbn_plx_romulus }, 4302 /* 4303 * Quatech cards. These actually have configurable clocks but for 4304 * now we just use the default. 4305 * 4306 * 100 series are RS232, 200 series RS422, 4307 */ 4308 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_b1_4_115200 }, 4311 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_b1_2_115200 }, 4314 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_b2_2_115200 }, 4317 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_b1_2_115200 }, 4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_b2_2_115200 }, 4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_b1_4_115200 }, 4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_b1_8_115200 }, 4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_b1_8_115200 }, 4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_b1_4_115200 }, 4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_b1_2_115200 }, 4338 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4340 pbn_b1_4_115200 }, 4341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_b1_2_115200 }, 4344 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_b2_4_115200 }, 4347 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4349 pbn_b2_2_115200 }, 4350 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_b2_1_115200 }, 4353 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4355 pbn_b2_4_115200 }, 4356 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4358 pbn_b2_2_115200 }, 4359 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4361 pbn_b2_1_115200 }, 4362 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b0_8_115200 }, 4365 4366 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4367 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4368 0, 0, 4369 pbn_b0_4_921600 }, 4370 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4371 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4372 0, 0, 4373 pbn_b0_4_1152000 }, 4374 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b0_bt_2_921600 }, 4377 4378 /* 4379 * The below card is a little controversial since it is the 4380 * subject of a PCI vendor/device ID clash. (See 4381 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4382 * For now just used the hex ID 0x950a. 4383 */ 4384 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4385 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4386 0, 0, pbn_b0_2_115200 }, 4387 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4388 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4389 0, 0, pbn_b0_2_115200 }, 4390 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b0_2_1130000 }, 4393 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4394 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4395 pbn_b0_1_921600 }, 4396 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4398 pbn_b0_4_115200 }, 4399 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b0_bt_2_921600 }, 4402 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b2_8_1152000 }, 4405 4406 /* 4407 * Oxford Semiconductor Inc. Tornado PCI express device range. 4408 */ 4409 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_b0_1_15625000 }, 4412 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b0_1_15625000 }, 4415 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_oxsemi_1_15625000 }, 4418 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_oxsemi_1_15625000 }, 4421 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b0_1_15625000 }, 4424 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_b0_1_15625000 }, 4427 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_oxsemi_1_15625000 }, 4430 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_oxsemi_1_15625000 }, 4433 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_b0_1_15625000 }, 4436 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_b0_1_15625000 }, 4439 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_b0_1_15625000 }, 4442 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_b0_1_15625000 }, 4445 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_oxsemi_2_15625000 }, 4448 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_oxsemi_2_15625000 }, 4451 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_oxsemi_4_15625000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_oxsemi_4_15625000 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_oxsemi_8_15625000 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_oxsemi_8_15625000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_oxsemi_1_15625000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_1_15625000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_15625000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_1_15625000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_oxsemi_1_15625000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_15625000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_15625000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_15625000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_oxsemi_1_15625000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_oxsemi_1_15625000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_oxsemi_1_15625000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_1_15625000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_1_15625000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_1_15625000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_1_15625000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_1_15625000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_1_15625000 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_1_15625000 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_15625000 }, 4520 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_oxsemi_1_15625000 }, 4523 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_oxsemi_1_15625000 }, 4526 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_oxsemi_1_15625000 }, 4529 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_oxsemi_1_15625000 }, 4532 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4534 pbn_oxsemi_1_15625000 }, 4535 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4537 pbn_oxsemi_1_15625000 }, 4538 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4540 pbn_oxsemi_1_15625000 }, 4541 /* 4542 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4543 */ 4544 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4545 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4546 pbn_oxsemi_1_15625000 }, 4547 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4548 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4549 pbn_oxsemi_2_15625000 }, 4550 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4551 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4552 pbn_oxsemi_4_15625000 }, 4553 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4554 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4555 pbn_oxsemi_8_15625000 }, 4556 4557 /* 4558 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4559 */ 4560 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4561 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4562 pbn_oxsemi_2_15625000 }, 4563 /* 4564 * EndRun Technologies. PCI express device range. 4565 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4566 */ 4567 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4569 pbn_oxsemi_2_15625000 }, 4570 4571 /* 4572 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4573 * from skokodyn@yahoo.com 4574 */ 4575 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4576 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4577 pbn_sbsxrsio }, 4578 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4579 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4580 pbn_sbsxrsio }, 4581 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4582 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4583 pbn_sbsxrsio }, 4584 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4585 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4586 pbn_sbsxrsio }, 4587 4588 /* 4589 * Digitan DS560-558, from jimd@esoft.com 4590 */ 4591 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_b1_1_115200 }, 4594 4595 /* 4596 * Titan Electronic cards 4597 * The 400L and 800L have a custom setup quirk. 4598 */ 4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b0_1_921600 }, 4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b0_2_921600 }, 4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b0_4_921600 }, 4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b0_4_921600 }, 4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b1_1_921600 }, 4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b1_bt_2_921600 }, 4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b0_bt_4_921600 }, 4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_b0_bt_8_921600 }, 4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_b4_bt_2_921600 }, 4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_b4_bt_4_921600 }, 4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b4_bt_8_921600 }, 4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_b0_4_921600 }, 4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b0_4_921600 }, 4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_b0_4_921600 }, 4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_titan_1_4000000 }, 4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_titan_2_4000000 }, 4647 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_titan_4_4000000 }, 4650 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_titan_8_4000000 }, 4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_titan_2_4000000 }, 4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_titan_2_4000000 }, 4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_bt_2_921600 }, 4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_4_921600 }, 4665 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b0_4_921600 }, 4668 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b0_4_921600 }, 4671 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_4_921600 }, 4674 4675 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b2_1_460800 }, 4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b2_1_460800 }, 4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_b2_1_460800 }, 4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b2_bt_2_921600 }, 4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b2_bt_2_921600 }, 4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_b2_bt_2_921600 }, 4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b2_bt_4_921600 }, 4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b2_bt_4_921600 }, 4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b2_bt_4_921600 }, 4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b0_1_921600 }, 4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_1_921600 }, 4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_b0_1_921600 }, 4711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_bt_2_921600 }, 4714 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_b0_bt_2_921600 }, 4717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4719 pbn_b0_bt_2_921600 }, 4720 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_b0_bt_4_921600 }, 4723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_b0_bt_4_921600 }, 4726 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4728 pbn_b0_bt_4_921600 }, 4729 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4731 pbn_b0_bt_8_921600 }, 4732 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4734 pbn_b0_bt_8_921600 }, 4735 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4737 pbn_b0_bt_8_921600 }, 4738 4739 /* 4740 * Computone devices submitted by Doug McNash dmcnash@computone.com 4741 */ 4742 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4743 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4744 0, 0, pbn_computone_4 }, 4745 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4746 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4747 0, 0, pbn_computone_8 }, 4748 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4749 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4750 0, 0, pbn_computone_6 }, 4751 4752 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4754 pbn_oxsemi }, 4755 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4756 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4757 pbn_b0_bt_1_921600 }, 4758 4759 /* 4760 * Sunix PCI serial boards 4761 */ 4762 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4763 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4764 pbn_sunix_pci_1s }, 4765 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4766 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4767 pbn_sunix_pci_2s }, 4768 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4769 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4770 pbn_sunix_pci_4s }, 4771 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4772 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4773 pbn_sunix_pci_4s }, 4774 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4775 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4776 pbn_sunix_pci_8s }, 4777 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4778 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4779 pbn_sunix_pci_8s }, 4780 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4781 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4782 pbn_sunix_pci_16s }, 4783 4784 /* 4785 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4786 */ 4787 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_b0_bt_8_115200 }, 4790 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_b0_bt_8_115200 }, 4793 4794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_b0_bt_2_115200 }, 4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_b0_bt_2_115200 }, 4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4802 pbn_b0_bt_2_115200 }, 4803 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4805 pbn_b0_bt_2_115200 }, 4806 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4808 pbn_b0_bt_2_115200 }, 4809 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4811 pbn_b0_bt_4_460800 }, 4812 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4814 pbn_b0_bt_4_460800 }, 4815 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4817 pbn_b0_bt_2_460800 }, 4818 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4820 pbn_b0_bt_2_460800 }, 4821 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4823 pbn_b0_bt_2_460800 }, 4824 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4825 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4826 pbn_b0_bt_1_115200 }, 4827 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4829 pbn_b0_bt_1_460800 }, 4830 4831 /* 4832 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4833 * Cards are identified by their subsystem vendor IDs, which 4834 * (in hex) match the model number. 4835 * 4836 * Note that JC140x are RS422/485 cards which require ox950 4837 * ACR = 0x10, and as such are not currently fully supported. 4838 */ 4839 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4840 0x1204, 0x0004, 0, 0, 4841 pbn_b0_4_921600 }, 4842 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4843 0x1208, 0x0004, 0, 0, 4844 pbn_b0_4_921600 }, 4845 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4846 0x1402, 0x0002, 0, 0, 4847 pbn_b0_2_921600 }, */ 4848 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4849 0x1404, 0x0004, 0, 0, 4850 pbn_b0_4_921600 }, */ 4851 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4852 0x1208, 0x0004, 0, 0, 4853 pbn_b0_4_921600 }, 4854 4855 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4856 0x1204, 0x0004, 0, 0, 4857 pbn_b0_4_921600 }, 4858 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4859 0x1208, 0x0004, 0, 0, 4860 pbn_b0_4_921600 }, 4861 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4862 0x1208, 0x0004, 0, 0, 4863 pbn_b0_4_921600 }, 4864 /* 4865 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4866 */ 4867 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4868 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4869 pbn_b1_1_1382400 }, 4870 4871 /* 4872 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4873 */ 4874 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b1_1_1382400 }, 4877 4878 /* 4879 * RAStel 2 port modem, gerg@moreton.com.au 4880 */ 4881 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b2_bt_2_115200 }, 4884 4885 /* 4886 * EKF addition for i960 Boards form EKF with serial port 4887 */ 4888 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4889 0xE4BF, PCI_ANY_ID, 0, 0, 4890 pbn_intel_i960 }, 4891 4892 /* 4893 * Xircom Cardbus/Ethernet combos 4894 */ 4895 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4897 pbn_b0_1_115200 }, 4898 /* 4899 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4900 */ 4901 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4903 pbn_b0_1_115200 }, 4904 4905 /* 4906 * Untested PCI modems, sent in from various folks... 4907 */ 4908 4909 /* 4910 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4911 */ 4912 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4913 0x1048, 0x1500, 0, 0, 4914 pbn_b1_1_115200 }, 4915 4916 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4917 0xFF00, 0, 0, 0, 4918 pbn_sgi_ioc3 }, 4919 4920 /* 4921 * HP Diva card 4922 */ 4923 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4924 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4925 pbn_b1_1_115200 }, 4926 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4928 pbn_b0_5_115200 }, 4929 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4931 pbn_b2_1_115200 }, 4932 /* HPE PCI serial device */ 4933 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b1_1_115200 }, 4936 4937 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b3_2_115200 }, 4940 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b3_4_115200 }, 4943 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b3_8_115200 }, 4946 /* 4947 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4948 */ 4949 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4951 pbn_b0_1_115200 }, 4952 /* 4953 * ITE 4954 */ 4955 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4956 PCI_ANY_ID, PCI_ANY_ID, 4957 0, 0, 4958 pbn_b1_bt_1_115200 }, 4959 4960 /* 4961 * IntaShield IS-200 4962 */ 4963 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4965 pbn_b2_2_115200 }, 4966 /* 4967 * IntaShield IS-400 4968 */ 4969 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4971 pbn_b2_4_115200 }, 4972 /* Brainboxes Devices */ 4973 /* 4974 * Brainboxes UC-101 4975 */ 4976 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4977 PCI_ANY_ID, PCI_ANY_ID, 4978 0, 0, 4979 pbn_b2_2_115200 }, 4980 /* 4981 * Brainboxes UC-235/246 4982 */ 4983 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4984 PCI_ANY_ID, PCI_ANY_ID, 4985 0, 0, 4986 pbn_b2_1_115200 }, 4987 /* 4988 * Brainboxes UC-257 4989 */ 4990 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4991 PCI_ANY_ID, PCI_ANY_ID, 4992 0, 0, 4993 pbn_b2_2_115200 }, 4994 /* 4995 * Brainboxes UC-260/271/701/756 4996 */ 4997 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4998 PCI_ANY_ID, PCI_ANY_ID, 4999 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5000 pbn_b2_4_115200 }, 5001 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5002 PCI_ANY_ID, PCI_ANY_ID, 5003 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5004 pbn_b2_4_115200 }, 5005 /* 5006 * Brainboxes UC-268 5007 */ 5008 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 5009 PCI_ANY_ID, PCI_ANY_ID, 5010 0, 0, 5011 pbn_b2_4_115200 }, 5012 /* 5013 * Brainboxes UC-275/279 5014 */ 5015 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5016 PCI_ANY_ID, PCI_ANY_ID, 5017 0, 0, 5018 pbn_b2_8_115200 }, 5019 /* 5020 * Brainboxes UC-302 5021 */ 5022 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5023 PCI_ANY_ID, PCI_ANY_ID, 5024 0, 0, 5025 pbn_b2_2_115200 }, 5026 /* 5027 * Brainboxes UC-310 5028 */ 5029 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5030 PCI_ANY_ID, PCI_ANY_ID, 5031 0, 0, 5032 pbn_b2_2_115200 }, 5033 /* 5034 * Brainboxes UC-313 5035 */ 5036 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5037 PCI_ANY_ID, PCI_ANY_ID, 5038 0, 0, 5039 pbn_b2_2_115200 }, 5040 /* 5041 * Brainboxes UC-320/324 5042 */ 5043 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5044 PCI_ANY_ID, PCI_ANY_ID, 5045 0, 0, 5046 pbn_b2_1_115200 }, 5047 /* 5048 * Brainboxes UC-346 5049 */ 5050 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5051 PCI_ANY_ID, PCI_ANY_ID, 5052 0, 0, 5053 pbn_b2_4_115200 }, 5054 /* 5055 * Brainboxes UC-357 5056 */ 5057 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5058 PCI_ANY_ID, PCI_ANY_ID, 5059 0, 0, 5060 pbn_b2_2_115200 }, 5061 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5062 PCI_ANY_ID, PCI_ANY_ID, 5063 0, 0, 5064 pbn_b2_2_115200 }, 5065 /* 5066 * Brainboxes UC-368 5067 */ 5068 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5069 PCI_ANY_ID, PCI_ANY_ID, 5070 0, 0, 5071 pbn_b2_4_115200 }, 5072 /* 5073 * Brainboxes UC-420/431 5074 */ 5075 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5076 PCI_ANY_ID, PCI_ANY_ID, 5077 0, 0, 5078 pbn_b2_4_115200 }, 5079 /* 5080 * Perle PCI-RAS cards 5081 */ 5082 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5083 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5084 0, 0, pbn_b2_4_921600 }, 5085 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5086 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5087 0, 0, pbn_b2_8_921600 }, 5088 5089 /* 5090 * Mainpine series cards: Fairly standard layout but fools 5091 * parts of the autodetect in some cases and uses otherwise 5092 * unmatched communications subclasses in the PCI Express case 5093 */ 5094 5095 { /* RockForceDUO */ 5096 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5097 PCI_VENDOR_ID_MAINPINE, 0x0200, 5098 0, 0, pbn_b0_2_115200 }, 5099 { /* RockForceQUATRO */ 5100 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5101 PCI_VENDOR_ID_MAINPINE, 0x0300, 5102 0, 0, pbn_b0_4_115200 }, 5103 { /* RockForceDUO+ */ 5104 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5105 PCI_VENDOR_ID_MAINPINE, 0x0400, 5106 0, 0, pbn_b0_2_115200 }, 5107 { /* RockForceQUATRO+ */ 5108 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5109 PCI_VENDOR_ID_MAINPINE, 0x0500, 5110 0, 0, pbn_b0_4_115200 }, 5111 { /* RockForce+ */ 5112 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5113 PCI_VENDOR_ID_MAINPINE, 0x0600, 5114 0, 0, pbn_b0_2_115200 }, 5115 { /* RockForce+ */ 5116 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5117 PCI_VENDOR_ID_MAINPINE, 0x0700, 5118 0, 0, pbn_b0_4_115200 }, 5119 { /* RockForceOCTO+ */ 5120 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5121 PCI_VENDOR_ID_MAINPINE, 0x0800, 5122 0, 0, pbn_b0_8_115200 }, 5123 { /* RockForceDUO+ */ 5124 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5125 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5126 0, 0, pbn_b0_2_115200 }, 5127 { /* RockForceQUARTRO+ */ 5128 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5129 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5130 0, 0, pbn_b0_4_115200 }, 5131 { /* RockForceOCTO+ */ 5132 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5133 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5134 0, 0, pbn_b0_8_115200 }, 5135 { /* RockForceD1 */ 5136 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5137 PCI_VENDOR_ID_MAINPINE, 0x2000, 5138 0, 0, pbn_b0_1_115200 }, 5139 { /* RockForceF1 */ 5140 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5141 PCI_VENDOR_ID_MAINPINE, 0x2100, 5142 0, 0, pbn_b0_1_115200 }, 5143 { /* RockForceD2 */ 5144 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5145 PCI_VENDOR_ID_MAINPINE, 0x2200, 5146 0, 0, pbn_b0_2_115200 }, 5147 { /* RockForceF2 */ 5148 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5149 PCI_VENDOR_ID_MAINPINE, 0x2300, 5150 0, 0, pbn_b0_2_115200 }, 5151 { /* RockForceD4 */ 5152 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5153 PCI_VENDOR_ID_MAINPINE, 0x2400, 5154 0, 0, pbn_b0_4_115200 }, 5155 { /* RockForceF4 */ 5156 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5157 PCI_VENDOR_ID_MAINPINE, 0x2500, 5158 0, 0, pbn_b0_4_115200 }, 5159 { /* RockForceD8 */ 5160 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5161 PCI_VENDOR_ID_MAINPINE, 0x2600, 5162 0, 0, pbn_b0_8_115200 }, 5163 { /* RockForceF8 */ 5164 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5165 PCI_VENDOR_ID_MAINPINE, 0x2700, 5166 0, 0, pbn_b0_8_115200 }, 5167 { /* IQ Express D1 */ 5168 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5169 PCI_VENDOR_ID_MAINPINE, 0x3000, 5170 0, 0, pbn_b0_1_115200 }, 5171 { /* IQ Express F1 */ 5172 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5173 PCI_VENDOR_ID_MAINPINE, 0x3100, 5174 0, 0, pbn_b0_1_115200 }, 5175 { /* IQ Express D2 */ 5176 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5177 PCI_VENDOR_ID_MAINPINE, 0x3200, 5178 0, 0, pbn_b0_2_115200 }, 5179 { /* IQ Express F2 */ 5180 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5181 PCI_VENDOR_ID_MAINPINE, 0x3300, 5182 0, 0, pbn_b0_2_115200 }, 5183 { /* IQ Express D4 */ 5184 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5185 PCI_VENDOR_ID_MAINPINE, 0x3400, 5186 0, 0, pbn_b0_4_115200 }, 5187 { /* IQ Express F4 */ 5188 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5189 PCI_VENDOR_ID_MAINPINE, 0x3500, 5190 0, 0, pbn_b0_4_115200 }, 5191 { /* IQ Express D8 */ 5192 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5193 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5194 0, 0, pbn_b0_8_115200 }, 5195 { /* IQ Express F8 */ 5196 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5197 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5198 0, 0, pbn_b0_8_115200 }, 5199 5200 5201 /* 5202 * PA Semi PA6T-1682M on-chip UART 5203 */ 5204 { PCI_VENDOR_ID_PASEMI, 0xa004, 5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5206 pbn_pasemi_1682M }, 5207 5208 /* 5209 * National Instruments 5210 */ 5211 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5213 pbn_b1_16_115200 }, 5214 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5216 pbn_b1_8_115200 }, 5217 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5219 pbn_b1_bt_4_115200 }, 5220 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5222 pbn_b1_bt_2_115200 }, 5223 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5225 pbn_b1_bt_4_115200 }, 5226 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5228 pbn_b1_bt_2_115200 }, 5229 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5231 pbn_b1_16_115200 }, 5232 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5234 pbn_b1_8_115200 }, 5235 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5237 pbn_b1_bt_4_115200 }, 5238 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5240 pbn_b1_bt_2_115200 }, 5241 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5243 pbn_b1_bt_4_115200 }, 5244 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5246 pbn_b1_bt_2_115200 }, 5247 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5249 pbn_ni8430_2 }, 5250 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5252 pbn_ni8430_2 }, 5253 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5255 pbn_ni8430_4 }, 5256 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5258 pbn_ni8430_4 }, 5259 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5261 pbn_ni8430_8 }, 5262 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5264 pbn_ni8430_8 }, 5265 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5267 pbn_ni8430_16 }, 5268 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5270 pbn_ni8430_16 }, 5271 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5273 pbn_ni8430_2 }, 5274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5276 pbn_ni8430_2 }, 5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5279 pbn_ni8430_4 }, 5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5282 pbn_ni8430_4 }, 5283 5284 /* 5285 * MOXA 5286 */ 5287 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5289 pbn_moxa8250_2p }, 5290 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5292 pbn_moxa8250_2p }, 5293 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5295 pbn_moxa8250_4p }, 5296 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5298 pbn_moxa8250_4p }, 5299 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5301 pbn_moxa8250_8p }, 5302 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5304 pbn_moxa8250_8p }, 5305 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5307 pbn_moxa8250_8p }, 5308 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_moxa8250_8p }, 5311 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5313 pbn_moxa8250_2p }, 5314 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5316 pbn_moxa8250_4p }, 5317 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5319 pbn_moxa8250_8p }, 5320 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5322 pbn_moxa8250_8p }, 5323 5324 /* 5325 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5326 */ 5327 { PCI_VENDOR_ID_ADDIDATA, 5328 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5329 PCI_ANY_ID, 5330 PCI_ANY_ID, 5331 0, 5332 0, 5333 pbn_b0_4_115200 }, 5334 5335 { PCI_VENDOR_ID_ADDIDATA, 5336 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5337 PCI_ANY_ID, 5338 PCI_ANY_ID, 5339 0, 5340 0, 5341 pbn_b0_2_115200 }, 5342 5343 { PCI_VENDOR_ID_ADDIDATA, 5344 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5345 PCI_ANY_ID, 5346 PCI_ANY_ID, 5347 0, 5348 0, 5349 pbn_b0_1_115200 }, 5350 5351 { PCI_VENDOR_ID_AMCC, 5352 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5353 PCI_ANY_ID, 5354 PCI_ANY_ID, 5355 0, 5356 0, 5357 pbn_b1_8_115200 }, 5358 5359 { PCI_VENDOR_ID_ADDIDATA, 5360 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5361 PCI_ANY_ID, 5362 PCI_ANY_ID, 5363 0, 5364 0, 5365 pbn_b0_4_115200 }, 5366 5367 { PCI_VENDOR_ID_ADDIDATA, 5368 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5369 PCI_ANY_ID, 5370 PCI_ANY_ID, 5371 0, 5372 0, 5373 pbn_b0_2_115200 }, 5374 5375 { PCI_VENDOR_ID_ADDIDATA, 5376 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5377 PCI_ANY_ID, 5378 PCI_ANY_ID, 5379 0, 5380 0, 5381 pbn_b0_1_115200 }, 5382 5383 { PCI_VENDOR_ID_ADDIDATA, 5384 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5385 PCI_ANY_ID, 5386 PCI_ANY_ID, 5387 0, 5388 0, 5389 pbn_b0_4_115200 }, 5390 5391 { PCI_VENDOR_ID_ADDIDATA, 5392 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5393 PCI_ANY_ID, 5394 PCI_ANY_ID, 5395 0, 5396 0, 5397 pbn_b0_2_115200 }, 5398 5399 { PCI_VENDOR_ID_ADDIDATA, 5400 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5401 PCI_ANY_ID, 5402 PCI_ANY_ID, 5403 0, 5404 0, 5405 pbn_b0_1_115200 }, 5406 5407 { PCI_VENDOR_ID_ADDIDATA, 5408 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5409 PCI_ANY_ID, 5410 PCI_ANY_ID, 5411 0, 5412 0, 5413 pbn_b0_8_115200 }, 5414 5415 { PCI_VENDOR_ID_ADDIDATA, 5416 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5417 PCI_ANY_ID, 5418 PCI_ANY_ID, 5419 0, 5420 0, 5421 pbn_ADDIDATA_PCIe_4_3906250 }, 5422 5423 { PCI_VENDOR_ID_ADDIDATA, 5424 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5425 PCI_ANY_ID, 5426 PCI_ANY_ID, 5427 0, 5428 0, 5429 pbn_ADDIDATA_PCIe_2_3906250 }, 5430 5431 { PCI_VENDOR_ID_ADDIDATA, 5432 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5433 PCI_ANY_ID, 5434 PCI_ANY_ID, 5435 0, 5436 0, 5437 pbn_ADDIDATA_PCIe_1_3906250 }, 5438 5439 { PCI_VENDOR_ID_ADDIDATA, 5440 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5441 PCI_ANY_ID, 5442 PCI_ANY_ID, 5443 0, 5444 0, 5445 pbn_ADDIDATA_PCIe_8_3906250 }, 5446 5447 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5448 PCI_VENDOR_ID_IBM, 0x0299, 5449 0, 0, pbn_b0_bt_2_115200 }, 5450 5451 /* 5452 * other NetMos 9835 devices are most likely handled by the 5453 * parport_serial driver, check drivers/parport/parport_serial.c 5454 * before adding them here. 5455 */ 5456 5457 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5458 0xA000, 0x1000, 5459 0, 0, pbn_b0_1_115200 }, 5460 5461 /* the 9901 is a rebranded 9912 */ 5462 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5463 0xA000, 0x1000, 5464 0, 0, pbn_b0_1_115200 }, 5465 5466 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5467 0xA000, 0x1000, 5468 0, 0, pbn_b0_1_115200 }, 5469 5470 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5471 0xA000, 0x1000, 5472 0, 0, pbn_b0_1_115200 }, 5473 5474 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5475 0xA000, 0x1000, 5476 0, 0, pbn_b0_1_115200 }, 5477 5478 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5479 0xA000, 0x3002, 5480 0, 0, pbn_NETMOS9900_2s_115200 }, 5481 5482 /* 5483 * Best Connectivity and Rosewill PCI Multi I/O cards 5484 */ 5485 5486 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5487 0xA000, 0x1000, 5488 0, 0, pbn_b0_1_115200 }, 5489 5490 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5491 0xA000, 0x3002, 5492 0, 0, pbn_b0_bt_2_115200 }, 5493 5494 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5495 0xA000, 0x3004, 5496 0, 0, pbn_b0_bt_4_115200 }, 5497 /* Intel CE4100 */ 5498 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5500 pbn_ce4100_1_115200 }, 5501 5502 /* 5503 * Cronyx Omega PCI 5504 */ 5505 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5507 pbn_omegapci }, 5508 5509 /* 5510 * Broadcom TruManage 5511 */ 5512 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5514 pbn_brcm_trumanage }, 5515 5516 /* 5517 * AgeStar as-prs2-009 5518 */ 5519 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5520 PCI_ANY_ID, PCI_ANY_ID, 5521 0, 0, pbn_b0_bt_2_115200 }, 5522 5523 /* 5524 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5525 * so not listed here. 5526 */ 5527 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5528 PCI_ANY_ID, PCI_ANY_ID, 5529 0, 0, pbn_b0_bt_4_115200 }, 5530 5531 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5532 PCI_ANY_ID, PCI_ANY_ID, 5533 0, 0, pbn_b0_bt_2_115200 }, 5534 5535 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5536 PCI_ANY_ID, PCI_ANY_ID, 5537 0, 0, pbn_b0_bt_4_115200 }, 5538 5539 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5540 PCI_ANY_ID, PCI_ANY_ID, 5541 0, 0, pbn_wch382_2 }, 5542 5543 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5544 PCI_ANY_ID, PCI_ANY_ID, 5545 0, 0, pbn_wch384_4 }, 5546 5547 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5548 PCI_ANY_ID, PCI_ANY_ID, 5549 0, 0, pbn_wch384_8 }, 5550 /* 5551 * Realtek RealManage 5552 */ 5553 { PCI_VENDOR_ID_REALTEK, 0x816a, 5554 PCI_ANY_ID, PCI_ANY_ID, 5555 0, 0, pbn_b0_1_115200 }, 5556 5557 { PCI_VENDOR_ID_REALTEK, 0x816b, 5558 PCI_ANY_ID, PCI_ANY_ID, 5559 0, 0, pbn_b0_1_115200 }, 5560 5561 /* Fintek PCI serial cards */ 5562 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5563 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5564 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5565 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5566 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5567 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5568 5569 /* MKS Tenta SCOM-080x serial cards */ 5570 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5571 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5572 5573 /* Amazon PCI serial device */ 5574 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5575 5576 /* 5577 * These entries match devices with class COMMUNICATION_SERIAL, 5578 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5579 */ 5580 { PCI_ANY_ID, PCI_ANY_ID, 5581 PCI_ANY_ID, PCI_ANY_ID, 5582 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5583 0xffff00, pbn_default }, 5584 { PCI_ANY_ID, PCI_ANY_ID, 5585 PCI_ANY_ID, PCI_ANY_ID, 5586 PCI_CLASS_COMMUNICATION_MODEM << 8, 5587 0xffff00, pbn_default }, 5588 { PCI_ANY_ID, PCI_ANY_ID, 5589 PCI_ANY_ID, PCI_ANY_ID, 5590 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5591 0xffff00, pbn_default }, 5592 { 0, } 5593 }; 5594 5595 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5596 pci_channel_state_t state) 5597 { 5598 struct serial_private *priv = pci_get_drvdata(dev); 5599 5600 if (state == pci_channel_io_perm_failure) 5601 return PCI_ERS_RESULT_DISCONNECT; 5602 5603 if (priv) 5604 pciserial_detach_ports(priv); 5605 5606 pci_disable_device(dev); 5607 5608 return PCI_ERS_RESULT_NEED_RESET; 5609 } 5610 5611 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5612 { 5613 int rc; 5614 5615 rc = pci_enable_device(dev); 5616 5617 if (rc) 5618 return PCI_ERS_RESULT_DISCONNECT; 5619 5620 pci_restore_state(dev); 5621 pci_save_state(dev); 5622 5623 return PCI_ERS_RESULT_RECOVERED; 5624 } 5625 5626 static void serial8250_io_resume(struct pci_dev *dev) 5627 { 5628 struct serial_private *priv = pci_get_drvdata(dev); 5629 struct serial_private *new; 5630 5631 if (!priv) 5632 return; 5633 5634 new = pciserial_init_ports(dev, priv->board); 5635 if (!IS_ERR(new)) { 5636 pci_set_drvdata(dev, new); 5637 kfree(priv); 5638 } 5639 } 5640 5641 static const struct pci_error_handlers serial8250_err_handler = { 5642 .error_detected = serial8250_io_error_detected, 5643 .slot_reset = serial8250_io_slot_reset, 5644 .resume = serial8250_io_resume, 5645 }; 5646 5647 static struct pci_driver serial_pci_driver = { 5648 .name = "serial", 5649 .probe = pciserial_init_one, 5650 .remove = pciserial_remove_one, 5651 .driver = { 5652 .pm = &pciserial_pm_ops, 5653 }, 5654 .id_table = serial_pci_tbl, 5655 .err_handler = &serial8250_err_handler, 5656 }; 5657 5658 module_pci_driver(serial_pci_driver); 5659 5660 MODULE_LICENSE("GPL"); 5661 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5662 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5663