1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57 }; 58 59 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 60 61 static const struct pci_device_id pci_use_msi[] = { 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 69 PCI_ANY_ID, PCI_ANY_ID) }, 70 { } 71 }; 72 73 static int pci_default_setup(struct serial_private*, 74 const struct pciserial_board*, struct uart_8250_port *, int); 75 76 static void moan_device(const char *str, struct pci_dev *dev) 77 { 78 pci_err(dev, "%s\n" 79 "Please send the output of lspci -vv, this\n" 80 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 81 "manufacturer and name of serial board or\n" 82 "modem board to <linux-serial@vger.kernel.org>.\n", 83 str, dev->vendor, dev->device, 84 dev->subsystem_vendor, dev->subsystem_device); 85 } 86 87 static int 88 setup_port(struct serial_private *priv, struct uart_8250_port *port, 89 u8 bar, unsigned int offset, int regshift) 90 { 91 struct pci_dev *dev = priv->dev; 92 93 if (bar >= PCI_STD_NUM_BARS) 94 return -EINVAL; 95 96 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 97 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 98 return -ENOMEM; 99 100 port->port.iotype = UPIO_MEM; 101 port->port.iobase = 0; 102 port->port.mapbase = pci_resource_start(dev, bar) + offset; 103 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 104 port->port.regshift = regshift; 105 } else { 106 port->port.iotype = UPIO_PORT; 107 port->port.iobase = pci_resource_start(dev, bar) + offset; 108 port->port.mapbase = 0; 109 port->port.membase = NULL; 110 port->port.regshift = 0; 111 } 112 return 0; 113 } 114 115 /* 116 * ADDI-DATA GmbH communication cards <info@addi-data.com> 117 */ 118 static int addidata_apci7800_setup(struct serial_private *priv, 119 const struct pciserial_board *board, 120 struct uart_8250_port *port, int idx) 121 { 122 unsigned int bar = 0, offset = board->first_offset; 123 bar = FL_GET_BASE(board->flags); 124 125 if (idx < 2) { 126 offset += idx * board->uart_offset; 127 } else if ((idx >= 2) && (idx < 4)) { 128 bar += 1; 129 offset += ((idx - 2) * board->uart_offset); 130 } else if ((idx >= 4) && (idx < 6)) { 131 bar += 2; 132 offset += ((idx - 4) * board->uart_offset); 133 } else if (idx >= 6) { 134 bar += 3; 135 offset += ((idx - 6) * board->uart_offset); 136 } 137 138 return setup_port(priv, port, bar, offset, board->reg_shift); 139 } 140 141 /* 142 * AFAVLAB uses a different mixture of BARs and offsets 143 * Not that ugly ;) -- HW 144 */ 145 static int 146 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 147 struct uart_8250_port *port, int idx) 148 { 149 unsigned int bar, offset = board->first_offset; 150 151 bar = FL_GET_BASE(board->flags); 152 if (idx < 4) 153 bar += idx; 154 else { 155 bar = 4; 156 offset += (idx - 4) * board->uart_offset; 157 } 158 159 return setup_port(priv, port, bar, offset, board->reg_shift); 160 } 161 162 /* 163 * HP's Remote Management Console. The Diva chip came in several 164 * different versions. N-class, L2000 and A500 have two Diva chips, each 165 * with 3 UARTs (the third UART on the second chip is unused). Superdome 166 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 167 * one Diva chip, but it has been expanded to 5 UARTs. 168 */ 169 static int pci_hp_diva_init(struct pci_dev *dev) 170 { 171 int rc = 0; 172 173 switch (dev->subsystem_device) { 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 175 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 176 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 177 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 178 rc = 3; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 181 rc = 2; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 184 rc = 4; 185 break; 186 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 187 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 188 rc = 1; 189 break; 190 } 191 192 return rc; 193 } 194 195 /* 196 * HP's Diva chip puts the 4th/5th serial port further out, and 197 * some serial ports are supposed to be hidden on certain models. 198 */ 199 static int 200 pci_hp_diva_setup(struct serial_private *priv, 201 const struct pciserial_board *board, 202 struct uart_8250_port *port, int idx) 203 { 204 unsigned int offset = board->first_offset; 205 unsigned int bar = FL_GET_BASE(board->flags); 206 207 switch (priv->dev->subsystem_device) { 208 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 209 if (idx == 3) 210 idx++; 211 break; 212 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 213 if (idx > 0) 214 idx++; 215 if (idx > 2) 216 idx++; 217 break; 218 } 219 if (idx > 2) 220 offset = 0x18; 221 222 offset += idx * board->uart_offset; 223 224 return setup_port(priv, port, bar, offset, board->reg_shift); 225 } 226 227 /* 228 * Added for EKF Intel i960 serial boards 229 */ 230 static int pci_inteli960ni_init(struct pci_dev *dev) 231 { 232 u32 oldval; 233 234 if (!(dev->subsystem_device & 0x1000)) 235 return -ENODEV; 236 237 /* is firmware started? */ 238 pci_read_config_dword(dev, 0x44, &oldval); 239 if (oldval == 0x00001000L) { /* RESET value */ 240 pci_dbg(dev, "Local i960 firmware missing\n"); 241 return -ENODEV; 242 } 243 return 0; 244 } 245 246 /* 247 * Some PCI serial cards using the PLX 9050 PCI interface chip require 248 * that the card interrupt be explicitly enabled or disabled. This 249 * seems to be mainly needed on card using the PLX which also use I/O 250 * mapped memory. 251 */ 252 static int pci_plx9050_init(struct pci_dev *dev) 253 { 254 u8 irq_config; 255 void __iomem *p; 256 257 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 258 moan_device("no memory in bar 0", dev); 259 return 0; 260 } 261 262 irq_config = 0x41; 263 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 264 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 265 irq_config = 0x43; 266 267 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 268 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 269 /* 270 * As the megawolf cards have the int pins active 271 * high, and have 2 UART chips, both ints must be 272 * enabled on the 9050. Also, the UARTS are set in 273 * 16450 mode by default, so we have to enable the 274 * 16C950 'enhanced' mode so that we can use the 275 * deep FIFOs 276 */ 277 irq_config = 0x5b; 278 /* 279 * enable/disable interrupts 280 */ 281 p = ioremap(pci_resource_start(dev, 0), 0x80); 282 if (p == NULL) 283 return -ENOMEM; 284 writel(irq_config, p + 0x4c); 285 286 /* 287 * Read the register back to ensure that it took effect. 288 */ 289 readl(p + 0x4c); 290 iounmap(p); 291 292 return 0; 293 } 294 295 static void pci_plx9050_exit(struct pci_dev *dev) 296 { 297 u8 __iomem *p; 298 299 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 300 return; 301 302 /* 303 * disable interrupts 304 */ 305 p = ioremap(pci_resource_start(dev, 0), 0x80); 306 if (p != NULL) { 307 writel(0, p + 0x4c); 308 309 /* 310 * Read the register back to ensure that it took effect. 311 */ 312 readl(p + 0x4c); 313 iounmap(p); 314 } 315 } 316 317 #define NI8420_INT_ENABLE_REG 0x38 318 #define NI8420_INT_ENABLE_BIT 0x2000 319 320 static void pci_ni8420_exit(struct pci_dev *dev) 321 { 322 void __iomem *p; 323 unsigned int bar = 0; 324 325 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 326 moan_device("no memory in bar", dev); 327 return; 328 } 329 330 p = pci_ioremap_bar(dev, bar); 331 if (p == NULL) 332 return; 333 334 /* Disable the CPU Interrupt */ 335 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 336 p + NI8420_INT_ENABLE_REG); 337 iounmap(p); 338 } 339 340 341 /* MITE registers */ 342 #define MITE_IOWBSR1 0xc4 343 #define MITE_IOWCR1 0xf4 344 #define MITE_LCIMR1 0x08 345 #define MITE_LCIMR2 0x10 346 347 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 348 349 static void pci_ni8430_exit(struct pci_dev *dev) 350 { 351 void __iomem *p; 352 unsigned int bar = 0; 353 354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 355 moan_device("no memory in bar", dev); 356 return; 357 } 358 359 p = pci_ioremap_bar(dev, bar); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366 } 367 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369 static int 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372 { 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387 } 388 389 /* 390 * This does initialization for PMC OCTALPRO cards: 391 * maps the device memory, resets the UARTs (needed, bc 392 * if the module is removed and inserted again, the card 393 * is in the sleep mode) and enables global interrupt. 394 */ 395 396 /* global control register offset for SBS PMC-OctalPro */ 397 #define OCT_REG_CR_OFF 0x500 398 399 static int sbs_init(struct pci_dev *dev) 400 { 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417 } 418 419 /* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423 static void sbs_exit(struct pci_dev *dev) 424 { 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432 } 433 434 /* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464 static int pci_siig10x_init(struct pci_dev *dev) 465 { 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489 } 490 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494 static int pci_siig20x_init(struct pci_dev *dev) 495 { 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509 } 510 511 static int pci_siig_init(struct pci_dev *dev) 512 { 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522 } 523 524 static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527 { 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536 } 537 538 /* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543 static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545 }; 546 547 static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553 }; 554 555 static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560 }; 561 562 static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565 }; 566 567 static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570 } timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575 }; 576 577 /* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583 static int pci_timedia_probe(struct pci_dev *dev) 584 { 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 591 dev->subsystem_device); 592 return -ENODEV; 593 } 594 595 return 0; 596 } 597 598 static int pci_timedia_init(struct pci_dev *dev) 599 { 600 const unsigned short *ids; 601 int i, j; 602 603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 604 ids = timedia_data[i].ids; 605 for (j = 0; ids[j]; j++) 606 if (dev->subsystem_device == ids[j]) 607 return timedia_data[i].num; 608 } 609 return 0; 610 } 611 612 /* 613 * Timedia/SUNIX uses a mixture of BARs and offsets 614 * Ugh, this is ugly as all hell --- TYT 615 */ 616 static int 617 pci_timedia_setup(struct serial_private *priv, 618 const struct pciserial_board *board, 619 struct uart_8250_port *port, int idx) 620 { 621 unsigned int bar = 0, offset = board->first_offset; 622 623 switch (idx) { 624 case 0: 625 bar = 0; 626 break; 627 case 1: 628 offset = board->uart_offset; 629 bar = 0; 630 break; 631 case 2: 632 bar = 1; 633 break; 634 case 3: 635 offset = board->uart_offset; 636 fallthrough; 637 case 4: /* BAR 2 */ 638 case 5: /* BAR 3 */ 639 case 6: /* BAR 4 */ 640 case 7: /* BAR 5 */ 641 bar = idx - 2; 642 } 643 644 return setup_port(priv, port, bar, offset, board->reg_shift); 645 } 646 647 /* 648 * Some Titan cards are also a little weird 649 */ 650 static int 651 titan_400l_800l_setup(struct serial_private *priv, 652 const struct pciserial_board *board, 653 struct uart_8250_port *port, int idx) 654 { 655 unsigned int bar, offset = board->first_offset; 656 657 switch (idx) { 658 case 0: 659 bar = 1; 660 break; 661 case 1: 662 bar = 2; 663 break; 664 default: 665 bar = 4; 666 offset = (idx - 2) * board->uart_offset; 667 } 668 669 return setup_port(priv, port, bar, offset, board->reg_shift); 670 } 671 672 static int pci_xircom_init(struct pci_dev *dev) 673 { 674 msleep(100); 675 return 0; 676 } 677 678 static int pci_ni8420_init(struct pci_dev *dev) 679 { 680 void __iomem *p; 681 unsigned int bar = 0; 682 683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 684 moan_device("no memory in bar", dev); 685 return 0; 686 } 687 688 p = pci_ioremap_bar(dev, bar); 689 if (p == NULL) 690 return -ENOMEM; 691 692 /* Enable CPU Interrupt */ 693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 694 p + NI8420_INT_ENABLE_REG); 695 696 iounmap(p); 697 return 0; 698 } 699 700 #define MITE_IOWBSR1_WSIZE 0xa 701 #define MITE_IOWBSR1_WIN_OFFSET 0x800 702 #define MITE_IOWBSR1_WENAB (1 << 7) 703 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 706 707 static int pci_ni8430_init(struct pci_dev *dev) 708 { 709 void __iomem *p; 710 struct pci_bus_region region; 711 u32 device_window; 712 unsigned int bar = 0; 713 714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 715 moan_device("no memory in bar", dev); 716 return 0; 717 } 718 719 p = pci_ioremap_bar(dev, bar); 720 if (p == NULL) 721 return -ENOMEM; 722 723 /* 724 * Set device window address and size in BAR0, while acknowledging that 725 * the resource structure may contain a translated address that differs 726 * from the address the device responds to. 727 */ 728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 731 writel(device_window, p + MITE_IOWBSR1); 732 733 /* Set window access to go to RAMSEL IO address space */ 734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 735 p + MITE_IOWCR1); 736 737 /* Enable IO Bus Interrupt 0 */ 738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 739 740 /* Enable CPU Interrupt */ 741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 742 743 iounmap(p); 744 return 0; 745 } 746 747 /* UART Port Control Register */ 748 #define NI8430_PORTCON 0x0f 749 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 750 751 static int 752 pci_ni8430_setup(struct serial_private *priv, 753 const struct pciserial_board *board, 754 struct uart_8250_port *port, int idx) 755 { 756 struct pci_dev *dev = priv->dev; 757 void __iomem *p; 758 unsigned int bar, offset = board->first_offset; 759 760 if (idx >= board->num_ports) 761 return 1; 762 763 bar = FL_GET_BASE(board->flags); 764 offset += idx * board->uart_offset; 765 766 p = pci_ioremap_bar(dev, bar); 767 if (!p) 768 return -ENOMEM; 769 770 /* enable the transceiver */ 771 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 772 p + offset + NI8430_PORTCON); 773 774 iounmap(p); 775 776 return setup_port(priv, port, bar, offset, board->reg_shift); 777 } 778 779 static int pci_netmos_9900_setup(struct serial_private *priv, 780 const struct pciserial_board *board, 781 struct uart_8250_port *port, int idx) 782 { 783 unsigned int bar; 784 785 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 786 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 787 /* netmos apparently orders BARs by datasheet layout, so serial 788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 789 */ 790 bar = 3 * idx; 791 792 return setup_port(priv, port, bar, 0, board->reg_shift); 793 } 794 795 return pci_default_setup(priv, board, port, idx); 796 } 797 798 /* the 99xx series comes with a range of device IDs and a variety 799 * of capabilities: 800 * 801 * 9900 has varying capabilities and can cascade to sub-controllers 802 * (cascading should be purely internal) 803 * 9904 is hardwired with 4 serial ports 804 * 9912 and 9922 are hardwired with 2 serial ports 805 */ 806 static int pci_netmos_9900_numports(struct pci_dev *dev) 807 { 808 unsigned int c = dev->class; 809 unsigned int pi; 810 unsigned short sub_serports; 811 812 pi = c & 0xff; 813 814 if (pi == 2) 815 return 1; 816 817 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 818 /* two possibilities: 0x30ps encodes number of parallel and 819 * serial ports, or 0x1000 indicates *something*. This is not 820 * immediately obvious, since the 2s1p+4s configuration seems 821 * to offer all functionality on functions 0..2, while still 822 * advertising the same function 3 as the 4s+2s1p config. 823 */ 824 sub_serports = dev->subsystem_device & 0xf; 825 if (sub_serports > 0) 826 return sub_serports; 827 828 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 829 return 0; 830 } 831 832 moan_device("unknown NetMos/Mostech program interface", dev); 833 return 0; 834 } 835 836 static int pci_netmos_init(struct pci_dev *dev) 837 { 838 /* subdevice 0x00PS means <P> parallel, <S> serial */ 839 unsigned int num_serial = dev->subsystem_device & 0xf; 840 841 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 842 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 843 return 0; 844 845 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 846 dev->subsystem_device == 0x0299) 847 return 0; 848 849 switch (dev->device) { /* FALLTHROUGH on all */ 850 case PCI_DEVICE_ID_NETMOS_9904: 851 case PCI_DEVICE_ID_NETMOS_9912: 852 case PCI_DEVICE_ID_NETMOS_9922: 853 case PCI_DEVICE_ID_NETMOS_9900: 854 num_serial = pci_netmos_9900_numports(dev); 855 break; 856 857 default: 858 break; 859 } 860 861 if (num_serial == 0) { 862 moan_device("unknown NetMos/Mostech device", dev); 863 return -ENODEV; 864 } 865 866 return num_serial; 867 } 868 869 /* 870 * These chips are available with optionally one parallel port and up to 871 * two serial ports. Unfortunately they all have the same product id. 872 * 873 * Basic configuration is done over a region of 32 I/O ports. The base 874 * ioport is called INTA or INTC, depending on docs/other drivers. 875 * 876 * The region of the 32 I/O ports is configured in POSIO0R... 877 */ 878 879 /* registers */ 880 #define ITE_887x_MISCR 0x9c 881 #define ITE_887x_INTCBAR 0x78 882 #define ITE_887x_UARTBAR 0x7c 883 #define ITE_887x_PS0BAR 0x10 884 #define ITE_887x_POSIO0 0x60 885 886 /* I/O space size */ 887 #define ITE_887x_IOSIZE 32 888 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 889 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 890 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 891 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 892 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 893 #define ITE_887x_POSIO_SPEED (3 << 29) 894 /* enable IO_Space bit */ 895 #define ITE_887x_POSIO_ENABLE (1 << 31) 896 897 /* inta_addr are the configuration addresses of the ITE */ 898 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 899 static int pci_ite887x_init(struct pci_dev *dev) 900 { 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 907 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 908 "ite887x"); 909 if (iobase != NULL) { 910 /* write POSIO0R - speed | size | ioport */ 911 pci_write_config_dword(dev, ITE_887x_POSIO0, 912 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 913 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 914 /* write INTCBAR - ioport */ 915 pci_write_config_dword(dev, ITE_887x_INTCBAR, 916 inta_addr[i]); 917 ret = inb(inta_addr[i]); 918 if (ret != 0xff) { 919 /* ioport connected */ 920 break; 921 } 922 release_region(iobase->start, ITE_887x_IOSIZE); 923 } 924 } 925 926 if (i == ARRAY_SIZE(inta_addr)) { 927 pci_err(dev, "could not find iobase\n"); 928 return -ENODEV; 929 } 930 931 /* start of undocumented type checking (see parport_pc.c) */ 932 type = inb(iobase->start + 0x18) & 0x0f; 933 934 switch (type) { 935 case 0x2: /* ITE8871 (1P) */ 936 case 0xa: /* ITE8875 (1P) */ 937 ret = 0; 938 break; 939 case 0xe: /* ITE8872 (2S1P) */ 940 ret = 2; 941 break; 942 case 0x6: /* ITE8873 (1S) */ 943 ret = 1; 944 break; 945 case 0x8: /* ITE8874 (2S) */ 946 ret = 2; 947 break; 948 default: 949 moan_device("Unknown ITE887x", dev); 950 ret = -ENODEV; 951 } 952 953 /* configure all serial ports */ 954 for (i = 0; i < ret; i++) { 955 /* read the I/O port from the device */ 956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 957 &ioport); 958 ioport &= 0x0000FF00; /* the actual base address */ 959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 961 ITE_887x_POSIO_IOSIZE_8 | ioport); 962 963 /* write the ioport to the UARTBAR */ 964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 966 uartbar |= (ioport << (16 * i)); /* set the ioport */ 967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 968 969 /* get current config */ 970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 971 /* disable interrupts (UARTx_Routing[3:0]) */ 972 miscr &= ~(0xf << (12 - 4 * i)); 973 /* activate the UART (UARTx_En) */ 974 miscr |= 1 << (23 - i); 975 /* write new config with activated UART */ 976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 977 } 978 979 if (ret <= 0) { 980 /* the device has no UARTs if we get here */ 981 release_region(iobase->start, ITE_887x_IOSIZE); 982 } 983 984 return ret; 985 } 986 987 static void pci_ite887x_exit(struct pci_dev *dev) 988 { 989 u32 ioport; 990 /* the ioport is bit 0-15 in POSIO0R */ 991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 992 ioport &= 0xffff; 993 release_region(ioport, ITE_887x_IOSIZE); 994 } 995 996 /* 997 * EndRun Technologies. 998 * Determine the number of ports available on the device. 999 */ 1000 #define PCI_VENDOR_ID_ENDRUN 0x7401 1001 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1002 1003 static int pci_endrun_init(struct pci_dev *dev) 1004 { 1005 u8 __iomem *p; 1006 unsigned long deviceID; 1007 unsigned int number_uarts = 0; 1008 1009 /* EndRun device is all 0xexxx */ 1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1011 (dev->device & 0xf000) != 0xe000) 1012 return 0; 1013 1014 p = pci_iomap(dev, 0, 5); 1015 if (p == NULL) 1016 return -ENOMEM; 1017 1018 deviceID = ioread32(p); 1019 /* EndRun device */ 1020 if (deviceID == 0x07000200) { 1021 number_uarts = ioread8(p + 4); 1022 pci_dbg(dev, "%d ports detected on EndRun PCI Express device\n", number_uarts); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* 1029 * Oxford Semiconductor Inc. 1030 * Check that device is part of the Tornado range of devices, then determine 1031 * the number of ports available on the device. 1032 */ 1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1034 { 1035 u8 __iomem *p; 1036 unsigned long deviceID; 1037 unsigned int number_uarts = 0; 1038 1039 /* OxSemi Tornado devices are all 0xCxxx */ 1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1041 (dev->device & 0xF000) != 0xC000) 1042 return 0; 1043 1044 p = pci_iomap(dev, 0, 5); 1045 if (p == NULL) 1046 return -ENOMEM; 1047 1048 deviceID = ioread32(p); 1049 /* Tornado device */ 1050 if (deviceID == 0x07000200) { 1051 number_uarts = ioread8(p + 4); 1052 pci_dbg(dev, "%d ports detected on Oxford PCI Express device\n", number_uarts); 1053 } 1054 pci_iounmap(dev, p); 1055 return number_uarts; 1056 } 1057 1058 static int pci_asix_setup(struct serial_private *priv, 1059 const struct pciserial_board *board, 1060 struct uart_8250_port *port, int idx) 1061 { 1062 port->bugs |= UART_BUG_PARITY; 1063 return pci_default_setup(priv, board, port, idx); 1064 } 1065 1066 #define QPCR_TEST_FOR1 0x3F 1067 #define QPCR_TEST_GET1 0x00 1068 #define QPCR_TEST_FOR2 0x40 1069 #define QPCR_TEST_GET2 0x40 1070 #define QPCR_TEST_FOR3 0x80 1071 #define QPCR_TEST_GET3 0x40 1072 #define QPCR_TEST_FOR4 0xC0 1073 #define QPCR_TEST_GET4 0x80 1074 1075 #define QOPR_CLOCK_X1 0x0000 1076 #define QOPR_CLOCK_X2 0x0001 1077 #define QOPR_CLOCK_X4 0x0002 1078 #define QOPR_CLOCK_X8 0x0003 1079 #define QOPR_CLOCK_RATE_MASK 0x0003 1080 1081 /* Quatech devices have their own extra interface features */ 1082 static struct pci_device_id quatech_cards[] = { 1083 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1084 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1085 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1086 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1087 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1088 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1089 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1090 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1091 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1092 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1093 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1094 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1095 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1096 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1097 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1098 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1099 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1100 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1101 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1102 { 0, } 1103 }; 1104 1105 static int pci_quatech_rqopr(struct uart_8250_port *port) 1106 { 1107 unsigned long base = port->port.iobase; 1108 u8 LCR, val; 1109 1110 LCR = inb(base + UART_LCR); 1111 outb(0xBF, base + UART_LCR); 1112 val = inb(base + UART_SCR); 1113 outb(LCR, base + UART_LCR); 1114 return val; 1115 } 1116 1117 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1118 { 1119 unsigned long base = port->port.iobase; 1120 u8 LCR; 1121 1122 LCR = inb(base + UART_LCR); 1123 outb(0xBF, base + UART_LCR); 1124 inb(base + UART_SCR); 1125 outb(qopr, base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127 } 1128 1129 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1130 { 1131 unsigned long base = port->port.iobase; 1132 u8 LCR, val, qmcr; 1133 1134 LCR = inb(base + UART_LCR); 1135 outb(0xBF, base + UART_LCR); 1136 val = inb(base + UART_SCR); 1137 outb(val | 0x10, base + UART_SCR); 1138 qmcr = inb(base + UART_MCR); 1139 outb(val, base + UART_SCR); 1140 outb(LCR, base + UART_LCR); 1141 1142 return qmcr; 1143 } 1144 1145 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1146 { 1147 unsigned long base = port->port.iobase; 1148 u8 LCR, val; 1149 1150 LCR = inb(base + UART_LCR); 1151 outb(0xBF, base + UART_LCR); 1152 val = inb(base + UART_SCR); 1153 outb(val | 0x10, base + UART_SCR); 1154 outb(qmcr, base + UART_MCR); 1155 outb(val, base + UART_SCR); 1156 outb(LCR, base + UART_LCR); 1157 } 1158 1159 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1160 { 1161 unsigned long base = port->port.iobase; 1162 u8 LCR, val; 1163 1164 LCR = inb(base + UART_LCR); 1165 outb(0xBF, base + UART_LCR); 1166 val = inb(base + UART_SCR); 1167 if (val & 0x20) { 1168 outb(0x80, UART_LCR); 1169 if (!(inb(UART_SCR) & 0x20)) { 1170 outb(LCR, base + UART_LCR); 1171 return 1; 1172 } 1173 } 1174 return 0; 1175 } 1176 1177 static int pci_quatech_test(struct uart_8250_port *port) 1178 { 1179 u8 reg, qopr; 1180 1181 qopr = pci_quatech_rqopr(port); 1182 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1183 reg = pci_quatech_rqopr(port) & 0xC0; 1184 if (reg != QPCR_TEST_GET1) 1185 return -EINVAL; 1186 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1187 reg = pci_quatech_rqopr(port) & 0xC0; 1188 if (reg != QPCR_TEST_GET2) 1189 return -EINVAL; 1190 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1191 reg = pci_quatech_rqopr(port) & 0xC0; 1192 if (reg != QPCR_TEST_GET3) 1193 return -EINVAL; 1194 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1195 reg = pci_quatech_rqopr(port) & 0xC0; 1196 if (reg != QPCR_TEST_GET4) 1197 return -EINVAL; 1198 1199 pci_quatech_wqopr(port, qopr); 1200 return 0; 1201 } 1202 1203 static int pci_quatech_clock(struct uart_8250_port *port) 1204 { 1205 u8 qopr, reg, set; 1206 unsigned long clock; 1207 1208 if (pci_quatech_test(port) < 0) 1209 return 1843200; 1210 1211 qopr = pci_quatech_rqopr(port); 1212 1213 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (reg & QOPR_CLOCK_X8) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1220 reg = pci_quatech_rqopr(port); 1221 if (!(reg & QOPR_CLOCK_X8)) { 1222 clock = 1843200; 1223 goto out; 1224 } 1225 reg &= QOPR_CLOCK_X8; 1226 if (reg == QOPR_CLOCK_X2) { 1227 clock = 3685400; 1228 set = QOPR_CLOCK_X2; 1229 } else if (reg == QOPR_CLOCK_X4) { 1230 clock = 7372800; 1231 set = QOPR_CLOCK_X4; 1232 } else if (reg == QOPR_CLOCK_X8) { 1233 clock = 14745600; 1234 set = QOPR_CLOCK_X8; 1235 } else { 1236 clock = 1843200; 1237 set = QOPR_CLOCK_X1; 1238 } 1239 qopr &= ~QOPR_CLOCK_RATE_MASK; 1240 qopr |= set; 1241 1242 out: 1243 pci_quatech_wqopr(port, qopr); 1244 return clock; 1245 } 1246 1247 static int pci_quatech_rs422(struct uart_8250_port *port) 1248 { 1249 u8 qmcr; 1250 int rs422 = 0; 1251 1252 if (!pci_quatech_has_qmcr(port)) 1253 return 0; 1254 qmcr = pci_quatech_rqmcr(port); 1255 pci_quatech_wqmcr(port, 0xFF); 1256 if (pci_quatech_rqmcr(port)) 1257 rs422 = 1; 1258 pci_quatech_wqmcr(port, qmcr); 1259 return rs422; 1260 } 1261 1262 static int pci_quatech_init(struct pci_dev *dev) 1263 { 1264 const struct pci_device_id *match; 1265 bool amcc = false; 1266 1267 match = pci_match_id(quatech_cards, dev); 1268 if (match) 1269 amcc = match->driver_data; 1270 else 1271 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1272 1273 if (amcc) { 1274 unsigned long base = pci_resource_start(dev, 0); 1275 if (base) { 1276 u32 tmp; 1277 1278 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1279 tmp = inl(base + 0x3c); 1280 outl(tmp | 0x01000000, base + 0x3c); 1281 outl(tmp &= ~0x01000000, base + 0x3c); 1282 } 1283 } 1284 return 0; 1285 } 1286 1287 static int pci_quatech_setup(struct serial_private *priv, 1288 const struct pciserial_board *board, 1289 struct uart_8250_port *port, int idx) 1290 { 1291 /* Needed by pci_quatech calls below */ 1292 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1293 /* Set up the clocking */ 1294 port->port.uartclk = pci_quatech_clock(port); 1295 /* For now just warn about RS422 */ 1296 if (pci_quatech_rs422(port)) 1297 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1298 return pci_default_setup(priv, board, port, idx); 1299 } 1300 1301 static int pci_default_setup(struct serial_private *priv, 1302 const struct pciserial_board *board, 1303 struct uart_8250_port *port, int idx) 1304 { 1305 unsigned int bar, offset = board->first_offset, maxnr; 1306 1307 bar = FL_GET_BASE(board->flags); 1308 if (board->flags & FL_BASE_BARS) 1309 bar += idx; 1310 else 1311 offset += idx * board->uart_offset; 1312 1313 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1314 (board->reg_shift + 3); 1315 1316 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1317 return 1; 1318 1319 return setup_port(priv, port, bar, offset, board->reg_shift); 1320 } 1321 static void 1322 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1323 unsigned int quot, unsigned int quot_frac) 1324 { 1325 int scr; 1326 int lcr; 1327 1328 for (scr = 16; scr > 4; scr--) { 1329 unsigned int maxrate = port->uartclk / scr; 1330 unsigned int divisor = max(maxrate / baud, 1U); 1331 int delta = maxrate / divisor - baud; 1332 1333 if (baud > maxrate + baud / 50) 1334 continue; 1335 1336 if (delta > baud / 50) 1337 divisor++; 1338 1339 if (divisor > 0xffff) 1340 continue; 1341 1342 /* Update delta due to possible divisor change */ 1343 delta = maxrate / divisor - baud; 1344 if (abs(delta) < baud / 50) { 1345 lcr = serial_port_in(port, UART_LCR); 1346 serial_port_out(port, UART_LCR, lcr | 0x80); 1347 serial_port_out(port, UART_DLL, divisor & 0xff); 1348 serial_port_out(port, UART_DLM, divisor >> 8 & 0xff); 1349 serial_port_out(port, 2, 16 - scr); 1350 serial_port_out(port, UART_LCR, lcr); 1351 return; 1352 } 1353 } 1354 } 1355 static int pci_pericom_setup(struct serial_private *priv, 1356 const struct pciserial_board *board, 1357 struct uart_8250_port *port, int idx) 1358 { 1359 unsigned int bar, offset = board->first_offset, maxnr; 1360 1361 bar = FL_GET_BASE(board->flags); 1362 if (board->flags & FL_BASE_BARS) 1363 bar += idx; 1364 else 1365 offset += idx * board->uart_offset; 1366 1367 1368 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1369 (board->reg_shift + 3); 1370 1371 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1372 return 1; 1373 1374 port->port.set_divisor = pericom_do_set_divisor; 1375 1376 return setup_port(priv, port, bar, offset, board->reg_shift); 1377 } 1378 1379 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1380 const struct pciserial_board *board, 1381 struct uart_8250_port *port, int idx) 1382 { 1383 unsigned int bar, offset = board->first_offset, maxnr; 1384 1385 bar = FL_GET_BASE(board->flags); 1386 if (board->flags & FL_BASE_BARS) 1387 bar += idx; 1388 else 1389 offset += idx * board->uart_offset; 1390 1391 if (idx==3) 1392 offset = 0x38; 1393 1394 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1395 (board->reg_shift + 3); 1396 1397 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1398 return 1; 1399 1400 port->port.set_divisor = pericom_do_set_divisor; 1401 1402 return setup_port(priv, port, bar, offset, board->reg_shift); 1403 } 1404 1405 static int 1406 ce4100_serial_setup(struct serial_private *priv, 1407 const struct pciserial_board *board, 1408 struct uart_8250_port *port, int idx) 1409 { 1410 int ret; 1411 1412 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1413 port->port.iotype = UPIO_MEM32; 1414 port->port.type = PORT_XSCALE; 1415 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1416 port->port.regshift = 2; 1417 1418 return ret; 1419 } 1420 1421 static int 1422 pci_omegapci_setup(struct serial_private *priv, 1423 const struct pciserial_board *board, 1424 struct uart_8250_port *port, int idx) 1425 { 1426 return setup_port(priv, port, 2, idx * 8, 0); 1427 } 1428 1429 static int 1430 pci_brcm_trumanage_setup(struct serial_private *priv, 1431 const struct pciserial_board *board, 1432 struct uart_8250_port *port, int idx) 1433 { 1434 int ret = pci_default_setup(priv, board, port, idx); 1435 1436 port->port.type = PORT_BRCM_TRUMANAGE; 1437 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1438 return ret; 1439 } 1440 1441 /* RTS will control by MCR if this bit is 0 */ 1442 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1443 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1444 #define FINTEK_RTS_INVERT BIT(5) 1445 1446 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1447 static int pci_fintek_rs485_config(struct uart_port *port, 1448 struct serial_rs485 *rs485) 1449 { 1450 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1451 u8 setting; 1452 u8 *index = (u8 *) port->private_data; 1453 1454 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1455 1456 if (!rs485) 1457 rs485 = &port->rs485; 1458 else if (rs485->flags & SER_RS485_ENABLED) 1459 memset(rs485->padding, 0, sizeof(rs485->padding)); 1460 else 1461 memset(rs485, 0, sizeof(*rs485)); 1462 1463 /* F81504/508/512 not support RTS delay before or after send */ 1464 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1465 1466 if (rs485->flags & SER_RS485_ENABLED) { 1467 /* Enable RTS H/W control mode */ 1468 setting |= FINTEK_RTS_CONTROL_BY_HW; 1469 1470 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1471 /* RTS driving high on TX */ 1472 setting &= ~FINTEK_RTS_INVERT; 1473 } else { 1474 /* RTS driving low on TX */ 1475 setting |= FINTEK_RTS_INVERT; 1476 } 1477 1478 rs485->delay_rts_after_send = 0; 1479 rs485->delay_rts_before_send = 0; 1480 } else { 1481 /* Disable RTS H/W control mode */ 1482 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1483 } 1484 1485 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1486 1487 if (rs485 != &port->rs485) 1488 port->rs485 = *rs485; 1489 1490 return 0; 1491 } 1492 1493 static int pci_fintek_setup(struct serial_private *priv, 1494 const struct pciserial_board *board, 1495 struct uart_8250_port *port, int idx) 1496 { 1497 struct pci_dev *pdev = priv->dev; 1498 u8 *data; 1499 u8 config_base; 1500 u16 iobase; 1501 1502 config_base = 0x40 + 0x08 * idx; 1503 1504 /* Get the io address from configuration space */ 1505 pci_read_config_word(pdev, config_base + 4, &iobase); 1506 1507 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1508 1509 port->port.iotype = UPIO_PORT; 1510 port->port.iobase = iobase; 1511 port->port.rs485_config = pci_fintek_rs485_config; 1512 1513 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1514 if (!data) 1515 return -ENOMEM; 1516 1517 /* preserve index in PCI configuration space */ 1518 *data = idx; 1519 port->port.private_data = data; 1520 1521 return 0; 1522 } 1523 1524 static int pci_fintek_init(struct pci_dev *dev) 1525 { 1526 unsigned long iobase; 1527 u32 max_port, i; 1528 resource_size_t bar_data[3]; 1529 u8 config_base; 1530 struct serial_private *priv = pci_get_drvdata(dev); 1531 struct uart_8250_port *port; 1532 1533 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1534 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1535 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1536 return -ENODEV; 1537 1538 switch (dev->device) { 1539 case 0x1104: /* 4 ports */ 1540 case 0x1108: /* 8 ports */ 1541 max_port = dev->device & 0xff; 1542 break; 1543 case 0x1112: /* 12 ports */ 1544 max_port = 12; 1545 break; 1546 default: 1547 return -EINVAL; 1548 } 1549 1550 /* Get the io address dispatch from the BIOS */ 1551 bar_data[0] = pci_resource_start(dev, 5); 1552 bar_data[1] = pci_resource_start(dev, 4); 1553 bar_data[2] = pci_resource_start(dev, 3); 1554 1555 for (i = 0; i < max_port; ++i) { 1556 /* UART0 configuration offset start from 0x40 */ 1557 config_base = 0x40 + 0x08 * i; 1558 1559 /* Calculate Real IO Port */ 1560 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1561 1562 /* Enable UART I/O port */ 1563 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1564 1565 /* Select 128-byte FIFO and 8x FIFO threshold */ 1566 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1567 1568 /* LSB UART */ 1569 pci_write_config_byte(dev, config_base + 0x04, 1570 (u8)(iobase & 0xff)); 1571 1572 /* MSB UART */ 1573 pci_write_config_byte(dev, config_base + 0x05, 1574 (u8)((iobase & 0xff00) >> 8)); 1575 1576 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1577 1578 if (priv) { 1579 /* re-apply RS232/485 mode when 1580 * pciserial_resume_ports() 1581 */ 1582 port = serial8250_get_port(priv->line[i]); 1583 pci_fintek_rs485_config(&port->port, NULL); 1584 } else { 1585 /* First init without port data 1586 * force init to RS232 Mode 1587 */ 1588 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1589 } 1590 } 1591 1592 return max_port; 1593 } 1594 1595 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1596 { 1597 struct f815xxa_data *data = p->private_data; 1598 unsigned long flags; 1599 1600 spin_lock_irqsave(&data->lock, flags); 1601 writeb(value, p->membase + offset); 1602 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1603 spin_unlock_irqrestore(&data->lock, flags); 1604 } 1605 1606 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1607 const struct pciserial_board *board, 1608 struct uart_8250_port *port, int idx) 1609 { 1610 struct pci_dev *pdev = priv->dev; 1611 struct f815xxa_data *data; 1612 1613 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1614 if (!data) 1615 return -ENOMEM; 1616 1617 data->idx = idx; 1618 spin_lock_init(&data->lock); 1619 1620 port->port.private_data = data; 1621 port->port.iotype = UPIO_MEM; 1622 port->port.flags |= UPF_IOREMAP; 1623 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1624 port->port.serial_out = f815xxa_mem_serial_out; 1625 1626 return 0; 1627 } 1628 1629 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1630 { 1631 u32 max_port, i; 1632 int config_base; 1633 1634 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1635 return -ENODEV; 1636 1637 switch (dev->device) { 1638 case 0x1204: /* 4 ports */ 1639 case 0x1208: /* 8 ports */ 1640 max_port = dev->device & 0xff; 1641 break; 1642 case 0x1212: /* 12 ports */ 1643 max_port = 12; 1644 break; 1645 default: 1646 return -EINVAL; 1647 } 1648 1649 /* Set to mmio decode */ 1650 pci_write_config_byte(dev, 0x209, 0x40); 1651 1652 for (i = 0; i < max_port; ++i) { 1653 /* UART0 configuration offset start from 0x2A0 */ 1654 config_base = 0x2A0 + 0x08 * i; 1655 1656 /* Select 128-byte FIFO and 8x FIFO threshold */ 1657 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1658 1659 /* Enable UART I/O port */ 1660 pci_write_config_byte(dev, config_base + 0, 0x01); 1661 } 1662 1663 return max_port; 1664 } 1665 1666 static int skip_tx_en_setup(struct serial_private *priv, 1667 const struct pciserial_board *board, 1668 struct uart_8250_port *port, int idx) 1669 { 1670 port->port.quirks |= UPQ_NO_TXEN_TEST; 1671 pci_dbg(priv->dev, 1672 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1673 priv->dev->vendor, priv->dev->device, 1674 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1675 1676 return pci_default_setup(priv, board, port, idx); 1677 } 1678 1679 static void kt_handle_break(struct uart_port *p) 1680 { 1681 struct uart_8250_port *up = up_to_u8250p(p); 1682 /* 1683 * On receipt of a BI, serial device in Intel ME (Intel 1684 * management engine) needs to have its fifos cleared for sane 1685 * SOL (Serial Over Lan) output. 1686 */ 1687 serial8250_clear_and_reinit_fifos(up); 1688 } 1689 1690 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1691 { 1692 struct uart_8250_port *up = up_to_u8250p(p); 1693 unsigned int val; 1694 1695 /* 1696 * When the Intel ME (management engine) gets reset its serial 1697 * port registers could return 0 momentarily. Functions like 1698 * serial8250_console_write, read and save the IER, perform 1699 * some operation and then restore it. In order to avoid 1700 * setting IER register inadvertently to 0, if the value read 1701 * is 0, double check with ier value in uart_8250_port and use 1702 * that instead. up->ier should be the same value as what is 1703 * currently configured. 1704 */ 1705 val = inb(p->iobase + offset); 1706 if (offset == UART_IER) { 1707 if (val == 0) 1708 val = up->ier; 1709 } 1710 return val; 1711 } 1712 1713 static int kt_serial_setup(struct serial_private *priv, 1714 const struct pciserial_board *board, 1715 struct uart_8250_port *port, int idx) 1716 { 1717 port->port.flags |= UPF_BUG_THRE; 1718 port->port.serial_in = kt_serial_in; 1719 port->port.handle_break = kt_handle_break; 1720 return skip_tx_en_setup(priv, board, port, idx); 1721 } 1722 1723 static int pci_eg20t_init(struct pci_dev *dev) 1724 { 1725 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1726 return -ENODEV; 1727 #else 1728 return 0; 1729 #endif 1730 } 1731 1732 static int 1733 pci_wch_ch353_setup(struct serial_private *priv, 1734 const struct pciserial_board *board, 1735 struct uart_8250_port *port, int idx) 1736 { 1737 port->port.flags |= UPF_FIXED_TYPE; 1738 port->port.type = PORT_16550A; 1739 return pci_default_setup(priv, board, port, idx); 1740 } 1741 1742 static int 1743 pci_wch_ch355_setup(struct serial_private *priv, 1744 const struct pciserial_board *board, 1745 struct uart_8250_port *port, int idx) 1746 { 1747 port->port.flags |= UPF_FIXED_TYPE; 1748 port->port.type = PORT_16550A; 1749 return pci_default_setup(priv, board, port, idx); 1750 } 1751 1752 static int 1753 pci_wch_ch38x_setup(struct serial_private *priv, 1754 const struct pciserial_board *board, 1755 struct uart_8250_port *port, int idx) 1756 { 1757 port->port.flags |= UPF_FIXED_TYPE; 1758 port->port.type = PORT_16850; 1759 return pci_default_setup(priv, board, port, idx); 1760 } 1761 1762 1763 #define CH384_XINT_ENABLE_REG 0xEB 1764 #define CH384_XINT_ENABLE_BIT 0x02 1765 1766 static int pci_wch_ch38x_init(struct pci_dev *dev) 1767 { 1768 int max_port; 1769 unsigned long iobase; 1770 1771 1772 switch (dev->device) { 1773 case 0x3853: /* 8 ports */ 1774 max_port = 8; 1775 break; 1776 default: 1777 return -EINVAL; 1778 } 1779 1780 iobase = pci_resource_start(dev, 0); 1781 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1782 1783 return max_port; 1784 } 1785 1786 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1787 { 1788 unsigned long iobase; 1789 1790 iobase = pci_resource_start(dev, 0); 1791 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1792 } 1793 1794 1795 static int 1796 pci_sunix_setup(struct serial_private *priv, 1797 const struct pciserial_board *board, 1798 struct uart_8250_port *port, int idx) 1799 { 1800 int bar; 1801 int offset; 1802 1803 port->port.flags |= UPF_FIXED_TYPE; 1804 port->port.type = PORT_SUNIX; 1805 1806 if (idx < 4) { 1807 bar = 0; 1808 offset = idx * board->uart_offset; 1809 } else { 1810 bar = 1; 1811 idx -= 4; 1812 idx = div_s64_rem(idx, 4, &offset); 1813 offset = idx * 64 + offset * board->uart_offset; 1814 } 1815 1816 return setup_port(priv, port, bar, offset, 0); 1817 } 1818 1819 static int 1820 pci_moxa_setup(struct serial_private *priv, 1821 const struct pciserial_board *board, 1822 struct uart_8250_port *port, int idx) 1823 { 1824 unsigned int bar = FL_GET_BASE(board->flags); 1825 int offset; 1826 1827 if (board->num_ports == 4 && idx == 3) 1828 offset = 7 * board->uart_offset; 1829 else 1830 offset = idx * board->uart_offset; 1831 1832 return setup_port(priv, port, bar, offset, 0); 1833 } 1834 1835 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1836 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1837 #define PCI_DEVICE_ID_OCTPRO 0x0001 1838 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1839 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1840 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1841 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1842 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1843 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1844 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1845 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1846 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1847 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1848 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1849 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1850 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1851 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1852 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1853 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1854 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1855 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1856 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1857 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1858 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1859 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1860 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1861 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1862 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1863 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1864 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1865 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1866 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1867 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1868 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1869 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1870 #define PCI_VENDOR_ID_WCH 0x4348 1871 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1872 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1873 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1874 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1875 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1876 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1877 #define PCI_VENDOR_ID_AGESTAR 0x5372 1878 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1879 #define PCI_VENDOR_ID_ASIX 0x9710 1880 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1881 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1882 1883 #define PCIE_VENDOR_ID_WCH 0x1c00 1884 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1885 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1886 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1887 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1888 1889 #define PCI_VENDOR_ID_ACCESIO 0x494f 1890 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1891 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1892 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1893 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1894 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1895 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1896 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1897 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1898 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1899 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1900 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1901 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1902 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1903 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1904 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1905 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1906 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1908 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1910 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1912 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1914 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1916 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1918 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1919 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1920 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1921 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1922 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1923 1924 1925 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1926 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1927 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1928 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1929 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1930 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1931 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1932 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1933 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1934 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1935 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1936 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1937 1938 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1939 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1940 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1941 1942 /* 1943 * Master list of serial port init/setup/exit quirks. 1944 * This does not describe the general nature of the port. 1945 * (ie, baud base, number and location of ports, etc) 1946 * 1947 * This list is ordered alphabetically by vendor then device. 1948 * Specific entries must come before more generic entries. 1949 */ 1950 static struct pci_serial_quirk pci_serial_quirks[] = { 1951 /* 1952 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1953 */ 1954 { 1955 .vendor = PCI_VENDOR_ID_AMCC, 1956 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1957 .subvendor = PCI_ANY_ID, 1958 .subdevice = PCI_ANY_ID, 1959 .setup = addidata_apci7800_setup, 1960 }, 1961 /* 1962 * AFAVLAB cards - these may be called via parport_serial 1963 * It is not clear whether this applies to all products. 1964 */ 1965 { 1966 .vendor = PCI_VENDOR_ID_AFAVLAB, 1967 .device = PCI_ANY_ID, 1968 .subvendor = PCI_ANY_ID, 1969 .subdevice = PCI_ANY_ID, 1970 .setup = afavlab_setup, 1971 }, 1972 /* 1973 * HP Diva 1974 */ 1975 { 1976 .vendor = PCI_VENDOR_ID_HP, 1977 .device = PCI_DEVICE_ID_HP_DIVA, 1978 .subvendor = PCI_ANY_ID, 1979 .subdevice = PCI_ANY_ID, 1980 .init = pci_hp_diva_init, 1981 .setup = pci_hp_diva_setup, 1982 }, 1983 /* 1984 * HPE PCI serial device 1985 */ 1986 { 1987 .vendor = PCI_VENDOR_ID_HP_3PAR, 1988 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 1989 .subvendor = PCI_ANY_ID, 1990 .subdevice = PCI_ANY_ID, 1991 .setup = pci_hp_diva_setup, 1992 }, 1993 /* 1994 * Intel 1995 */ 1996 { 1997 .vendor = PCI_VENDOR_ID_INTEL, 1998 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1999 .subvendor = 0xe4bf, 2000 .subdevice = PCI_ANY_ID, 2001 .init = pci_inteli960ni_init, 2002 .setup = pci_default_setup, 2003 }, 2004 { 2005 .vendor = PCI_VENDOR_ID_INTEL, 2006 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2007 .subvendor = PCI_ANY_ID, 2008 .subdevice = PCI_ANY_ID, 2009 .setup = skip_tx_en_setup, 2010 }, 2011 { 2012 .vendor = PCI_VENDOR_ID_INTEL, 2013 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2014 .subvendor = PCI_ANY_ID, 2015 .subdevice = PCI_ANY_ID, 2016 .setup = skip_tx_en_setup, 2017 }, 2018 { 2019 .vendor = PCI_VENDOR_ID_INTEL, 2020 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2021 .subvendor = PCI_ANY_ID, 2022 .subdevice = PCI_ANY_ID, 2023 .setup = skip_tx_en_setup, 2024 }, 2025 { 2026 .vendor = PCI_VENDOR_ID_INTEL, 2027 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .setup = ce4100_serial_setup, 2031 }, 2032 { 2033 .vendor = PCI_VENDOR_ID_INTEL, 2034 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2035 .subvendor = PCI_ANY_ID, 2036 .subdevice = PCI_ANY_ID, 2037 .setup = kt_serial_setup, 2038 }, 2039 /* 2040 * ITE 2041 */ 2042 { 2043 .vendor = PCI_VENDOR_ID_ITE, 2044 .device = PCI_DEVICE_ID_ITE_8872, 2045 .subvendor = PCI_ANY_ID, 2046 .subdevice = PCI_ANY_ID, 2047 .init = pci_ite887x_init, 2048 .setup = pci_default_setup, 2049 .exit = pci_ite887x_exit, 2050 }, 2051 /* 2052 * National Instruments 2053 */ 2054 { 2055 .vendor = PCI_VENDOR_ID_NI, 2056 .device = PCI_DEVICE_ID_NI_PCI23216, 2057 .subvendor = PCI_ANY_ID, 2058 .subdevice = PCI_ANY_ID, 2059 .init = pci_ni8420_init, 2060 .setup = pci_default_setup, 2061 .exit = pci_ni8420_exit, 2062 }, 2063 { 2064 .vendor = PCI_VENDOR_ID_NI, 2065 .device = PCI_DEVICE_ID_NI_PCI2328, 2066 .subvendor = PCI_ANY_ID, 2067 .subdevice = PCI_ANY_ID, 2068 .init = pci_ni8420_init, 2069 .setup = pci_default_setup, 2070 .exit = pci_ni8420_exit, 2071 }, 2072 { 2073 .vendor = PCI_VENDOR_ID_NI, 2074 .device = PCI_DEVICE_ID_NI_PCI2324, 2075 .subvendor = PCI_ANY_ID, 2076 .subdevice = PCI_ANY_ID, 2077 .init = pci_ni8420_init, 2078 .setup = pci_default_setup, 2079 .exit = pci_ni8420_exit, 2080 }, 2081 { 2082 .vendor = PCI_VENDOR_ID_NI, 2083 .device = PCI_DEVICE_ID_NI_PCI2322, 2084 .subvendor = PCI_ANY_ID, 2085 .subdevice = PCI_ANY_ID, 2086 .init = pci_ni8420_init, 2087 .setup = pci_default_setup, 2088 .exit = pci_ni8420_exit, 2089 }, 2090 { 2091 .vendor = PCI_VENDOR_ID_NI, 2092 .device = PCI_DEVICE_ID_NI_PCI2324I, 2093 .subvendor = PCI_ANY_ID, 2094 .subdevice = PCI_ANY_ID, 2095 .init = pci_ni8420_init, 2096 .setup = pci_default_setup, 2097 .exit = pci_ni8420_exit, 2098 }, 2099 { 2100 .vendor = PCI_VENDOR_ID_NI, 2101 .device = PCI_DEVICE_ID_NI_PCI2322I, 2102 .subvendor = PCI_ANY_ID, 2103 .subdevice = PCI_ANY_ID, 2104 .init = pci_ni8420_init, 2105 .setup = pci_default_setup, 2106 .exit = pci_ni8420_exit, 2107 }, 2108 { 2109 .vendor = PCI_VENDOR_ID_NI, 2110 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2111 .subvendor = PCI_ANY_ID, 2112 .subdevice = PCI_ANY_ID, 2113 .init = pci_ni8420_init, 2114 .setup = pci_default_setup, 2115 .exit = pci_ni8420_exit, 2116 }, 2117 { 2118 .vendor = PCI_VENDOR_ID_NI, 2119 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2120 .subvendor = PCI_ANY_ID, 2121 .subdevice = PCI_ANY_ID, 2122 .init = pci_ni8420_init, 2123 .setup = pci_default_setup, 2124 .exit = pci_ni8420_exit, 2125 }, 2126 { 2127 .vendor = PCI_VENDOR_ID_NI, 2128 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2129 .subvendor = PCI_ANY_ID, 2130 .subdevice = PCI_ANY_ID, 2131 .init = pci_ni8420_init, 2132 .setup = pci_default_setup, 2133 .exit = pci_ni8420_exit, 2134 }, 2135 { 2136 .vendor = PCI_VENDOR_ID_NI, 2137 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2138 .subvendor = PCI_ANY_ID, 2139 .subdevice = PCI_ANY_ID, 2140 .init = pci_ni8420_init, 2141 .setup = pci_default_setup, 2142 .exit = pci_ni8420_exit, 2143 }, 2144 { 2145 .vendor = PCI_VENDOR_ID_NI, 2146 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2147 .subvendor = PCI_ANY_ID, 2148 .subdevice = PCI_ANY_ID, 2149 .init = pci_ni8420_init, 2150 .setup = pci_default_setup, 2151 .exit = pci_ni8420_exit, 2152 }, 2153 { 2154 .vendor = PCI_VENDOR_ID_NI, 2155 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2156 .subvendor = PCI_ANY_ID, 2157 .subdevice = PCI_ANY_ID, 2158 .init = pci_ni8420_init, 2159 .setup = pci_default_setup, 2160 .exit = pci_ni8420_exit, 2161 }, 2162 { 2163 .vendor = PCI_VENDOR_ID_NI, 2164 .device = PCI_ANY_ID, 2165 .subvendor = PCI_ANY_ID, 2166 .subdevice = PCI_ANY_ID, 2167 .init = pci_ni8430_init, 2168 .setup = pci_ni8430_setup, 2169 .exit = pci_ni8430_exit, 2170 }, 2171 /* Quatech */ 2172 { 2173 .vendor = PCI_VENDOR_ID_QUATECH, 2174 .device = PCI_ANY_ID, 2175 .subvendor = PCI_ANY_ID, 2176 .subdevice = PCI_ANY_ID, 2177 .init = pci_quatech_init, 2178 .setup = pci_quatech_setup, 2179 }, 2180 /* 2181 * Panacom 2182 */ 2183 { 2184 .vendor = PCI_VENDOR_ID_PANACOM, 2185 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2186 .subvendor = PCI_ANY_ID, 2187 .subdevice = PCI_ANY_ID, 2188 .init = pci_plx9050_init, 2189 .setup = pci_default_setup, 2190 .exit = pci_plx9050_exit, 2191 }, 2192 { 2193 .vendor = PCI_VENDOR_ID_PANACOM, 2194 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2195 .subvendor = PCI_ANY_ID, 2196 .subdevice = PCI_ANY_ID, 2197 .init = pci_plx9050_init, 2198 .setup = pci_default_setup, 2199 .exit = pci_plx9050_exit, 2200 }, 2201 /* 2202 * Pericom (Only 7954 - It have a offset jump for port 4) 2203 */ 2204 { 2205 .vendor = PCI_VENDOR_ID_PERICOM, 2206 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2207 .subvendor = PCI_ANY_ID, 2208 .subdevice = PCI_ANY_ID, 2209 .setup = pci_pericom_setup_four_at_eight, 2210 }, 2211 /* 2212 * PLX 2213 */ 2214 { 2215 .vendor = PCI_VENDOR_ID_PLX, 2216 .device = PCI_DEVICE_ID_PLX_9050, 2217 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2218 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2219 .init = pci_plx9050_init, 2220 .setup = pci_default_setup, 2221 .exit = pci_plx9050_exit, 2222 }, 2223 { 2224 .vendor = PCI_VENDOR_ID_PLX, 2225 .device = PCI_DEVICE_ID_PLX_9050, 2226 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2227 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2228 .init = pci_plx9050_init, 2229 .setup = pci_default_setup, 2230 .exit = pci_plx9050_exit, 2231 }, 2232 { 2233 .vendor = PCI_VENDOR_ID_PLX, 2234 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2235 .subvendor = PCI_VENDOR_ID_PLX, 2236 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2237 .init = pci_plx9050_init, 2238 .setup = pci_default_setup, 2239 .exit = pci_plx9050_exit, 2240 }, 2241 { 2242 .vendor = PCI_VENDOR_ID_ACCESIO, 2243 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2244 .subvendor = PCI_ANY_ID, 2245 .subdevice = PCI_ANY_ID, 2246 .setup = pci_pericom_setup_four_at_eight, 2247 }, 2248 { 2249 .vendor = PCI_VENDOR_ID_ACCESIO, 2250 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2251 .subvendor = PCI_ANY_ID, 2252 .subdevice = PCI_ANY_ID, 2253 .setup = pci_pericom_setup_four_at_eight, 2254 }, 2255 { 2256 .vendor = PCI_VENDOR_ID_ACCESIO, 2257 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2258 .subvendor = PCI_ANY_ID, 2259 .subdevice = PCI_ANY_ID, 2260 .setup = pci_pericom_setup_four_at_eight, 2261 }, 2262 { 2263 .vendor = PCI_VENDOR_ID_ACCESIO, 2264 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2265 .subvendor = PCI_ANY_ID, 2266 .subdevice = PCI_ANY_ID, 2267 .setup = pci_pericom_setup_four_at_eight, 2268 }, 2269 { 2270 .vendor = PCI_VENDOR_ID_ACCESIO, 2271 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2272 .subvendor = PCI_ANY_ID, 2273 .subdevice = PCI_ANY_ID, 2274 .setup = pci_pericom_setup_four_at_eight, 2275 }, 2276 { 2277 .vendor = PCI_VENDOR_ID_ACCESIO, 2278 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2279 .subvendor = PCI_ANY_ID, 2280 .subdevice = PCI_ANY_ID, 2281 .setup = pci_pericom_setup_four_at_eight, 2282 }, 2283 { 2284 .vendor = PCI_VENDOR_ID_ACCESIO, 2285 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2286 .subvendor = PCI_ANY_ID, 2287 .subdevice = PCI_ANY_ID, 2288 .setup = pci_pericom_setup_four_at_eight, 2289 }, 2290 { 2291 .vendor = PCI_VENDOR_ID_ACCESIO, 2292 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2293 .subvendor = PCI_ANY_ID, 2294 .subdevice = PCI_ANY_ID, 2295 .setup = pci_pericom_setup_four_at_eight, 2296 }, 2297 { 2298 .vendor = PCI_VENDOR_ID_ACCESIO, 2299 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2300 .subvendor = PCI_ANY_ID, 2301 .subdevice = PCI_ANY_ID, 2302 .setup = pci_pericom_setup_four_at_eight, 2303 }, 2304 { 2305 .vendor = PCI_VENDOR_ID_ACCESIO, 2306 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2307 .subvendor = PCI_ANY_ID, 2308 .subdevice = PCI_ANY_ID, 2309 .setup = pci_pericom_setup_four_at_eight, 2310 }, 2311 { 2312 .vendor = PCI_VENDOR_ID_ACCESIO, 2313 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2314 .subvendor = PCI_ANY_ID, 2315 .subdevice = PCI_ANY_ID, 2316 .setup = pci_pericom_setup_four_at_eight, 2317 }, 2318 { 2319 .vendor = PCI_VENDOR_ID_ACCESIO, 2320 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2321 .subvendor = PCI_ANY_ID, 2322 .subdevice = PCI_ANY_ID, 2323 .setup = pci_pericom_setup_four_at_eight, 2324 }, 2325 { 2326 .vendor = PCI_VENDOR_ID_ACCESIO, 2327 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2328 .subvendor = PCI_ANY_ID, 2329 .subdevice = PCI_ANY_ID, 2330 .setup = pci_pericom_setup_four_at_eight, 2331 }, 2332 { 2333 .vendor = PCI_VENDOR_ID_ACCESIO, 2334 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2335 .subvendor = PCI_ANY_ID, 2336 .subdevice = PCI_ANY_ID, 2337 .setup = pci_pericom_setup_four_at_eight, 2338 }, 2339 { 2340 .vendor = PCI_VENDOR_ID_ACCESIO, 2341 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2342 .subvendor = PCI_ANY_ID, 2343 .subdevice = PCI_ANY_ID, 2344 .setup = pci_pericom_setup_four_at_eight, 2345 }, 2346 { 2347 .vendor = PCI_VENDOR_ID_ACCESIO, 2348 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2349 .subvendor = PCI_ANY_ID, 2350 .subdevice = PCI_ANY_ID, 2351 .setup = pci_pericom_setup_four_at_eight, 2352 }, 2353 { 2354 .vendor = PCI_VENDOR_ID_ACCESIO, 2355 .device = PCI_ANY_ID, 2356 .subvendor = PCI_ANY_ID, 2357 .subdevice = PCI_ANY_ID, 2358 .setup = pci_pericom_setup, 2359 }, /* 2360 * SBS Technologies, Inc., PMC-OCTALPRO 232 2361 */ 2362 { 2363 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2364 .device = PCI_DEVICE_ID_OCTPRO, 2365 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2366 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2367 .init = sbs_init, 2368 .setup = sbs_setup, 2369 .exit = sbs_exit, 2370 }, 2371 /* 2372 * SBS Technologies, Inc., PMC-OCTALPRO 422 2373 */ 2374 { 2375 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2376 .device = PCI_DEVICE_ID_OCTPRO, 2377 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2378 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2379 .init = sbs_init, 2380 .setup = sbs_setup, 2381 .exit = sbs_exit, 2382 }, 2383 /* 2384 * SBS Technologies, Inc., P-Octal 232 2385 */ 2386 { 2387 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2388 .device = PCI_DEVICE_ID_OCTPRO, 2389 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2390 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2391 .init = sbs_init, 2392 .setup = sbs_setup, 2393 .exit = sbs_exit, 2394 }, 2395 /* 2396 * SBS Technologies, Inc., P-Octal 422 2397 */ 2398 { 2399 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2400 .device = PCI_DEVICE_ID_OCTPRO, 2401 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2402 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2403 .init = sbs_init, 2404 .setup = sbs_setup, 2405 .exit = sbs_exit, 2406 }, 2407 /* 2408 * SIIG cards - these may be called via parport_serial 2409 */ 2410 { 2411 .vendor = PCI_VENDOR_ID_SIIG, 2412 .device = PCI_ANY_ID, 2413 .subvendor = PCI_ANY_ID, 2414 .subdevice = PCI_ANY_ID, 2415 .init = pci_siig_init, 2416 .setup = pci_siig_setup, 2417 }, 2418 /* 2419 * Titan cards 2420 */ 2421 { 2422 .vendor = PCI_VENDOR_ID_TITAN, 2423 .device = PCI_DEVICE_ID_TITAN_400L, 2424 .subvendor = PCI_ANY_ID, 2425 .subdevice = PCI_ANY_ID, 2426 .setup = titan_400l_800l_setup, 2427 }, 2428 { 2429 .vendor = PCI_VENDOR_ID_TITAN, 2430 .device = PCI_DEVICE_ID_TITAN_800L, 2431 .subvendor = PCI_ANY_ID, 2432 .subdevice = PCI_ANY_ID, 2433 .setup = titan_400l_800l_setup, 2434 }, 2435 /* 2436 * Timedia cards 2437 */ 2438 { 2439 .vendor = PCI_VENDOR_ID_TIMEDIA, 2440 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2441 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2442 .subdevice = PCI_ANY_ID, 2443 .probe = pci_timedia_probe, 2444 .init = pci_timedia_init, 2445 .setup = pci_timedia_setup, 2446 }, 2447 { 2448 .vendor = PCI_VENDOR_ID_TIMEDIA, 2449 .device = PCI_ANY_ID, 2450 .subvendor = PCI_ANY_ID, 2451 .subdevice = PCI_ANY_ID, 2452 .setup = pci_timedia_setup, 2453 }, 2454 /* 2455 * Sunix PCI serial boards 2456 */ 2457 { 2458 .vendor = PCI_VENDOR_ID_SUNIX, 2459 .device = PCI_DEVICE_ID_SUNIX_1999, 2460 .subvendor = PCI_VENDOR_ID_SUNIX, 2461 .subdevice = PCI_ANY_ID, 2462 .setup = pci_sunix_setup, 2463 }, 2464 /* 2465 * Xircom cards 2466 */ 2467 { 2468 .vendor = PCI_VENDOR_ID_XIRCOM, 2469 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2470 .subvendor = PCI_ANY_ID, 2471 .subdevice = PCI_ANY_ID, 2472 .init = pci_xircom_init, 2473 .setup = pci_default_setup, 2474 }, 2475 /* 2476 * Netmos cards - these may be called via parport_serial 2477 */ 2478 { 2479 .vendor = PCI_VENDOR_ID_NETMOS, 2480 .device = PCI_ANY_ID, 2481 .subvendor = PCI_ANY_ID, 2482 .subdevice = PCI_ANY_ID, 2483 .init = pci_netmos_init, 2484 .setup = pci_netmos_9900_setup, 2485 }, 2486 /* 2487 * EndRun Technologies 2488 */ 2489 { 2490 .vendor = PCI_VENDOR_ID_ENDRUN, 2491 .device = PCI_ANY_ID, 2492 .subvendor = PCI_ANY_ID, 2493 .subdevice = PCI_ANY_ID, 2494 .init = pci_endrun_init, 2495 .setup = pci_default_setup, 2496 }, 2497 /* 2498 * For Oxford Semiconductor Tornado based devices 2499 */ 2500 { 2501 .vendor = PCI_VENDOR_ID_OXSEMI, 2502 .device = PCI_ANY_ID, 2503 .subvendor = PCI_ANY_ID, 2504 .subdevice = PCI_ANY_ID, 2505 .init = pci_oxsemi_tornado_init, 2506 .setup = pci_default_setup, 2507 }, 2508 { 2509 .vendor = PCI_VENDOR_ID_MAINPINE, 2510 .device = PCI_ANY_ID, 2511 .subvendor = PCI_ANY_ID, 2512 .subdevice = PCI_ANY_ID, 2513 .init = pci_oxsemi_tornado_init, 2514 .setup = pci_default_setup, 2515 }, 2516 { 2517 .vendor = PCI_VENDOR_ID_DIGI, 2518 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2519 .subvendor = PCI_SUBVENDOR_ID_IBM, 2520 .subdevice = PCI_ANY_ID, 2521 .init = pci_oxsemi_tornado_init, 2522 .setup = pci_default_setup, 2523 }, 2524 { 2525 .vendor = PCI_VENDOR_ID_INTEL, 2526 .device = 0x8811, 2527 .subvendor = PCI_ANY_ID, 2528 .subdevice = PCI_ANY_ID, 2529 .init = pci_eg20t_init, 2530 .setup = pci_default_setup, 2531 }, 2532 { 2533 .vendor = PCI_VENDOR_ID_INTEL, 2534 .device = 0x8812, 2535 .subvendor = PCI_ANY_ID, 2536 .subdevice = PCI_ANY_ID, 2537 .init = pci_eg20t_init, 2538 .setup = pci_default_setup, 2539 }, 2540 { 2541 .vendor = PCI_VENDOR_ID_INTEL, 2542 .device = 0x8813, 2543 .subvendor = PCI_ANY_ID, 2544 .subdevice = PCI_ANY_ID, 2545 .init = pci_eg20t_init, 2546 .setup = pci_default_setup, 2547 }, 2548 { 2549 .vendor = PCI_VENDOR_ID_INTEL, 2550 .device = 0x8814, 2551 .subvendor = PCI_ANY_ID, 2552 .subdevice = PCI_ANY_ID, 2553 .init = pci_eg20t_init, 2554 .setup = pci_default_setup, 2555 }, 2556 { 2557 .vendor = 0x10DB, 2558 .device = 0x8027, 2559 .subvendor = PCI_ANY_ID, 2560 .subdevice = PCI_ANY_ID, 2561 .init = pci_eg20t_init, 2562 .setup = pci_default_setup, 2563 }, 2564 { 2565 .vendor = 0x10DB, 2566 .device = 0x8028, 2567 .subvendor = PCI_ANY_ID, 2568 .subdevice = PCI_ANY_ID, 2569 .init = pci_eg20t_init, 2570 .setup = pci_default_setup, 2571 }, 2572 { 2573 .vendor = 0x10DB, 2574 .device = 0x8029, 2575 .subvendor = PCI_ANY_ID, 2576 .subdevice = PCI_ANY_ID, 2577 .init = pci_eg20t_init, 2578 .setup = pci_default_setup, 2579 }, 2580 { 2581 .vendor = 0x10DB, 2582 .device = 0x800C, 2583 .subvendor = PCI_ANY_ID, 2584 .subdevice = PCI_ANY_ID, 2585 .init = pci_eg20t_init, 2586 .setup = pci_default_setup, 2587 }, 2588 { 2589 .vendor = 0x10DB, 2590 .device = 0x800D, 2591 .subvendor = PCI_ANY_ID, 2592 .subdevice = PCI_ANY_ID, 2593 .init = pci_eg20t_init, 2594 .setup = pci_default_setup, 2595 }, 2596 /* 2597 * Cronyx Omega PCI (PLX-chip based) 2598 */ 2599 { 2600 .vendor = PCI_VENDOR_ID_PLX, 2601 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2602 .subvendor = PCI_ANY_ID, 2603 .subdevice = PCI_ANY_ID, 2604 .setup = pci_omegapci_setup, 2605 }, 2606 /* WCH CH353 1S1P card (16550 clone) */ 2607 { 2608 .vendor = PCI_VENDOR_ID_WCH, 2609 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2610 .subvendor = PCI_ANY_ID, 2611 .subdevice = PCI_ANY_ID, 2612 .setup = pci_wch_ch353_setup, 2613 }, 2614 /* WCH CH353 2S1P card (16550 clone) */ 2615 { 2616 .vendor = PCI_VENDOR_ID_WCH, 2617 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2618 .subvendor = PCI_ANY_ID, 2619 .subdevice = PCI_ANY_ID, 2620 .setup = pci_wch_ch353_setup, 2621 }, 2622 /* WCH CH353 4S card (16550 clone) */ 2623 { 2624 .vendor = PCI_VENDOR_ID_WCH, 2625 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2626 .subvendor = PCI_ANY_ID, 2627 .subdevice = PCI_ANY_ID, 2628 .setup = pci_wch_ch353_setup, 2629 }, 2630 /* WCH CH353 2S1PF card (16550 clone) */ 2631 { 2632 .vendor = PCI_VENDOR_ID_WCH, 2633 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2634 .subvendor = PCI_ANY_ID, 2635 .subdevice = PCI_ANY_ID, 2636 .setup = pci_wch_ch353_setup, 2637 }, 2638 /* WCH CH352 2S card (16550 clone) */ 2639 { 2640 .vendor = PCI_VENDOR_ID_WCH, 2641 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2642 .subvendor = PCI_ANY_ID, 2643 .subdevice = PCI_ANY_ID, 2644 .setup = pci_wch_ch353_setup, 2645 }, 2646 /* WCH CH355 4S card (16550 clone) */ 2647 { 2648 .vendor = PCI_VENDOR_ID_WCH, 2649 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2650 .subvendor = PCI_ANY_ID, 2651 .subdevice = PCI_ANY_ID, 2652 .setup = pci_wch_ch355_setup, 2653 }, 2654 /* WCH CH382 2S card (16850 clone) */ 2655 { 2656 .vendor = PCIE_VENDOR_ID_WCH, 2657 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2658 .subvendor = PCI_ANY_ID, 2659 .subdevice = PCI_ANY_ID, 2660 .setup = pci_wch_ch38x_setup, 2661 }, 2662 /* WCH CH382 2S1P card (16850 clone) */ 2663 { 2664 .vendor = PCIE_VENDOR_ID_WCH, 2665 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2666 .subvendor = PCI_ANY_ID, 2667 .subdevice = PCI_ANY_ID, 2668 .setup = pci_wch_ch38x_setup, 2669 }, 2670 /* WCH CH384 4S card (16850 clone) */ 2671 { 2672 .vendor = PCIE_VENDOR_ID_WCH, 2673 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2674 .subvendor = PCI_ANY_ID, 2675 .subdevice = PCI_ANY_ID, 2676 .setup = pci_wch_ch38x_setup, 2677 }, 2678 /* WCH CH384 8S card (16850 clone) */ 2679 { 2680 .vendor = PCIE_VENDOR_ID_WCH, 2681 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2682 .subvendor = PCI_ANY_ID, 2683 .subdevice = PCI_ANY_ID, 2684 .init = pci_wch_ch38x_init, 2685 .exit = pci_wch_ch38x_exit, 2686 .setup = pci_wch_ch38x_setup, 2687 }, 2688 /* 2689 * ASIX devices with FIFO bug 2690 */ 2691 { 2692 .vendor = PCI_VENDOR_ID_ASIX, 2693 .device = PCI_ANY_ID, 2694 .subvendor = PCI_ANY_ID, 2695 .subdevice = PCI_ANY_ID, 2696 .setup = pci_asix_setup, 2697 }, 2698 /* 2699 * Broadcom TruManage (NetXtreme) 2700 */ 2701 { 2702 .vendor = PCI_VENDOR_ID_BROADCOM, 2703 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2704 .subvendor = PCI_ANY_ID, 2705 .subdevice = PCI_ANY_ID, 2706 .setup = pci_brcm_trumanage_setup, 2707 }, 2708 { 2709 .vendor = 0x1c29, 2710 .device = 0x1104, 2711 .subvendor = PCI_ANY_ID, 2712 .subdevice = PCI_ANY_ID, 2713 .setup = pci_fintek_setup, 2714 .init = pci_fintek_init, 2715 }, 2716 { 2717 .vendor = 0x1c29, 2718 .device = 0x1108, 2719 .subvendor = PCI_ANY_ID, 2720 .subdevice = PCI_ANY_ID, 2721 .setup = pci_fintek_setup, 2722 .init = pci_fintek_init, 2723 }, 2724 { 2725 .vendor = 0x1c29, 2726 .device = 0x1112, 2727 .subvendor = PCI_ANY_ID, 2728 .subdevice = PCI_ANY_ID, 2729 .setup = pci_fintek_setup, 2730 .init = pci_fintek_init, 2731 }, 2732 /* 2733 * MOXA 2734 */ 2735 { 2736 .vendor = PCI_VENDOR_ID_MOXA, 2737 .device = PCI_ANY_ID, 2738 .subvendor = PCI_ANY_ID, 2739 .subdevice = PCI_ANY_ID, 2740 .setup = pci_moxa_setup, 2741 }, 2742 { 2743 .vendor = 0x1c29, 2744 .device = 0x1204, 2745 .subvendor = PCI_ANY_ID, 2746 .subdevice = PCI_ANY_ID, 2747 .setup = pci_fintek_f815xxa_setup, 2748 .init = pci_fintek_f815xxa_init, 2749 }, 2750 { 2751 .vendor = 0x1c29, 2752 .device = 0x1208, 2753 .subvendor = PCI_ANY_ID, 2754 .subdevice = PCI_ANY_ID, 2755 .setup = pci_fintek_f815xxa_setup, 2756 .init = pci_fintek_f815xxa_init, 2757 }, 2758 { 2759 .vendor = 0x1c29, 2760 .device = 0x1212, 2761 .subvendor = PCI_ANY_ID, 2762 .subdevice = PCI_ANY_ID, 2763 .setup = pci_fintek_f815xxa_setup, 2764 .init = pci_fintek_f815xxa_init, 2765 }, 2766 2767 /* 2768 * Default "match everything" terminator entry 2769 */ 2770 { 2771 .vendor = PCI_ANY_ID, 2772 .device = PCI_ANY_ID, 2773 .subvendor = PCI_ANY_ID, 2774 .subdevice = PCI_ANY_ID, 2775 .setup = pci_default_setup, 2776 } 2777 }; 2778 2779 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2780 { 2781 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2782 } 2783 2784 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2785 { 2786 struct pci_serial_quirk *quirk; 2787 2788 for (quirk = pci_serial_quirks; ; quirk++) 2789 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2790 quirk_id_matches(quirk->device, dev->device) && 2791 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2792 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2793 break; 2794 return quirk; 2795 } 2796 2797 /* 2798 * This is the configuration table for all of the PCI serial boards 2799 * which we support. It is directly indexed by the pci_board_num_t enum 2800 * value, which is encoded in the pci_device_id PCI probe table's 2801 * driver_data member. 2802 * 2803 * The makeup of these names are: 2804 * pbn_bn{_bt}_n_baud{_offsetinhex} 2805 * 2806 * bn = PCI BAR number 2807 * bt = Index using PCI BARs 2808 * n = number of serial ports 2809 * baud = baud rate 2810 * offsetinhex = offset for each sequential port (in hex) 2811 * 2812 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2813 * 2814 * Please note: in theory if n = 1, _bt infix should make no difference. 2815 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2816 */ 2817 enum pci_board_num_t { 2818 pbn_default = 0, 2819 2820 pbn_b0_1_115200, 2821 pbn_b0_2_115200, 2822 pbn_b0_4_115200, 2823 pbn_b0_5_115200, 2824 pbn_b0_8_115200, 2825 2826 pbn_b0_1_921600, 2827 pbn_b0_2_921600, 2828 pbn_b0_4_921600, 2829 2830 pbn_b0_2_1130000, 2831 2832 pbn_b0_4_1152000, 2833 2834 pbn_b0_4_1250000, 2835 2836 pbn_b0_2_1843200, 2837 pbn_b0_4_1843200, 2838 2839 pbn_b0_1_3906250, 2840 2841 pbn_b0_bt_1_115200, 2842 pbn_b0_bt_2_115200, 2843 pbn_b0_bt_4_115200, 2844 pbn_b0_bt_8_115200, 2845 2846 pbn_b0_bt_1_460800, 2847 pbn_b0_bt_2_460800, 2848 pbn_b0_bt_4_460800, 2849 2850 pbn_b0_bt_1_921600, 2851 pbn_b0_bt_2_921600, 2852 pbn_b0_bt_4_921600, 2853 pbn_b0_bt_8_921600, 2854 2855 pbn_b1_1_115200, 2856 pbn_b1_2_115200, 2857 pbn_b1_4_115200, 2858 pbn_b1_8_115200, 2859 pbn_b1_16_115200, 2860 2861 pbn_b1_1_921600, 2862 pbn_b1_2_921600, 2863 pbn_b1_4_921600, 2864 pbn_b1_8_921600, 2865 2866 pbn_b1_2_1250000, 2867 2868 pbn_b1_bt_1_115200, 2869 pbn_b1_bt_2_115200, 2870 pbn_b1_bt_4_115200, 2871 2872 pbn_b1_bt_2_921600, 2873 2874 pbn_b1_1_1382400, 2875 pbn_b1_2_1382400, 2876 pbn_b1_4_1382400, 2877 pbn_b1_8_1382400, 2878 2879 pbn_b2_1_115200, 2880 pbn_b2_2_115200, 2881 pbn_b2_4_115200, 2882 pbn_b2_8_115200, 2883 2884 pbn_b2_1_460800, 2885 pbn_b2_4_460800, 2886 pbn_b2_8_460800, 2887 pbn_b2_16_460800, 2888 2889 pbn_b2_1_921600, 2890 pbn_b2_4_921600, 2891 pbn_b2_8_921600, 2892 2893 pbn_b2_8_1152000, 2894 2895 pbn_b2_bt_1_115200, 2896 pbn_b2_bt_2_115200, 2897 pbn_b2_bt_4_115200, 2898 2899 pbn_b2_bt_2_921600, 2900 pbn_b2_bt_4_921600, 2901 2902 pbn_b3_2_115200, 2903 pbn_b3_4_115200, 2904 pbn_b3_8_115200, 2905 2906 pbn_b4_bt_2_921600, 2907 pbn_b4_bt_4_921600, 2908 pbn_b4_bt_8_921600, 2909 2910 /* 2911 * Board-specific versions. 2912 */ 2913 pbn_panacom, 2914 pbn_panacom2, 2915 pbn_panacom4, 2916 pbn_plx_romulus, 2917 pbn_endrun_2_4000000, 2918 pbn_oxsemi, 2919 pbn_oxsemi_1_3906250, 2920 pbn_oxsemi_2_3906250, 2921 pbn_oxsemi_4_3906250, 2922 pbn_oxsemi_8_3906250, 2923 pbn_intel_i960, 2924 pbn_sgi_ioc3, 2925 pbn_computone_4, 2926 pbn_computone_6, 2927 pbn_computone_8, 2928 pbn_sbsxrsio, 2929 pbn_pasemi_1682M, 2930 pbn_ni8430_2, 2931 pbn_ni8430_4, 2932 pbn_ni8430_8, 2933 pbn_ni8430_16, 2934 pbn_ADDIDATA_PCIe_1_3906250, 2935 pbn_ADDIDATA_PCIe_2_3906250, 2936 pbn_ADDIDATA_PCIe_4_3906250, 2937 pbn_ADDIDATA_PCIe_8_3906250, 2938 pbn_ce4100_1_115200, 2939 pbn_omegapci, 2940 pbn_NETMOS9900_2s_115200, 2941 pbn_brcm_trumanage, 2942 pbn_fintek_4, 2943 pbn_fintek_8, 2944 pbn_fintek_12, 2945 pbn_fintek_F81504A, 2946 pbn_fintek_F81508A, 2947 pbn_fintek_F81512A, 2948 pbn_wch382_2, 2949 pbn_wch384_4, 2950 pbn_wch384_8, 2951 pbn_pericom_PI7C9X7951, 2952 pbn_pericom_PI7C9X7952, 2953 pbn_pericom_PI7C9X7954, 2954 pbn_pericom_PI7C9X7958, 2955 pbn_sunix_pci_1s, 2956 pbn_sunix_pci_2s, 2957 pbn_sunix_pci_4s, 2958 pbn_sunix_pci_8s, 2959 pbn_sunix_pci_16s, 2960 pbn_titan_1_4000000, 2961 pbn_titan_2_4000000, 2962 pbn_titan_4_4000000, 2963 pbn_titan_8_4000000, 2964 pbn_moxa8250_2p, 2965 pbn_moxa8250_4p, 2966 pbn_moxa8250_8p, 2967 }; 2968 2969 /* 2970 * uart_offset - the space between channels 2971 * reg_shift - describes how the UART registers are mapped 2972 * to PCI memory by the card. 2973 * For example IER register on SBS, Inc. PMC-OctPro is located at 2974 * offset 0x10 from the UART base, while UART_IER is defined as 1 2975 * in include/linux/serial_reg.h, 2976 * see first lines of serial_in() and serial_out() in 8250.c 2977 */ 2978 2979 static struct pciserial_board pci_boards[] = { 2980 [pbn_default] = { 2981 .flags = FL_BASE0, 2982 .num_ports = 1, 2983 .base_baud = 115200, 2984 .uart_offset = 8, 2985 }, 2986 [pbn_b0_1_115200] = { 2987 .flags = FL_BASE0, 2988 .num_ports = 1, 2989 .base_baud = 115200, 2990 .uart_offset = 8, 2991 }, 2992 [pbn_b0_2_115200] = { 2993 .flags = FL_BASE0, 2994 .num_ports = 2, 2995 .base_baud = 115200, 2996 .uart_offset = 8, 2997 }, 2998 [pbn_b0_4_115200] = { 2999 .flags = FL_BASE0, 3000 .num_ports = 4, 3001 .base_baud = 115200, 3002 .uart_offset = 8, 3003 }, 3004 [pbn_b0_5_115200] = { 3005 .flags = FL_BASE0, 3006 .num_ports = 5, 3007 .base_baud = 115200, 3008 .uart_offset = 8, 3009 }, 3010 [pbn_b0_8_115200] = { 3011 .flags = FL_BASE0, 3012 .num_ports = 8, 3013 .base_baud = 115200, 3014 .uart_offset = 8, 3015 }, 3016 [pbn_b0_1_921600] = { 3017 .flags = FL_BASE0, 3018 .num_ports = 1, 3019 .base_baud = 921600, 3020 .uart_offset = 8, 3021 }, 3022 [pbn_b0_2_921600] = { 3023 .flags = FL_BASE0, 3024 .num_ports = 2, 3025 .base_baud = 921600, 3026 .uart_offset = 8, 3027 }, 3028 [pbn_b0_4_921600] = { 3029 .flags = FL_BASE0, 3030 .num_ports = 4, 3031 .base_baud = 921600, 3032 .uart_offset = 8, 3033 }, 3034 3035 [pbn_b0_2_1130000] = { 3036 .flags = FL_BASE0, 3037 .num_ports = 2, 3038 .base_baud = 1130000, 3039 .uart_offset = 8, 3040 }, 3041 3042 [pbn_b0_4_1152000] = { 3043 .flags = FL_BASE0, 3044 .num_ports = 4, 3045 .base_baud = 1152000, 3046 .uart_offset = 8, 3047 }, 3048 3049 [pbn_b0_4_1250000] = { 3050 .flags = FL_BASE0, 3051 .num_ports = 4, 3052 .base_baud = 1250000, 3053 .uart_offset = 8, 3054 }, 3055 3056 [pbn_b0_2_1843200] = { 3057 .flags = FL_BASE0, 3058 .num_ports = 2, 3059 .base_baud = 1843200, 3060 .uart_offset = 8, 3061 }, 3062 [pbn_b0_4_1843200] = { 3063 .flags = FL_BASE0, 3064 .num_ports = 4, 3065 .base_baud = 1843200, 3066 .uart_offset = 8, 3067 }, 3068 3069 [pbn_b0_1_3906250] = { 3070 .flags = FL_BASE0, 3071 .num_ports = 1, 3072 .base_baud = 3906250, 3073 .uart_offset = 8, 3074 }, 3075 3076 [pbn_b0_bt_1_115200] = { 3077 .flags = FL_BASE0|FL_BASE_BARS, 3078 .num_ports = 1, 3079 .base_baud = 115200, 3080 .uart_offset = 8, 3081 }, 3082 [pbn_b0_bt_2_115200] = { 3083 .flags = FL_BASE0|FL_BASE_BARS, 3084 .num_ports = 2, 3085 .base_baud = 115200, 3086 .uart_offset = 8, 3087 }, 3088 [pbn_b0_bt_4_115200] = { 3089 .flags = FL_BASE0|FL_BASE_BARS, 3090 .num_ports = 4, 3091 .base_baud = 115200, 3092 .uart_offset = 8, 3093 }, 3094 [pbn_b0_bt_8_115200] = { 3095 .flags = FL_BASE0|FL_BASE_BARS, 3096 .num_ports = 8, 3097 .base_baud = 115200, 3098 .uart_offset = 8, 3099 }, 3100 3101 [pbn_b0_bt_1_460800] = { 3102 .flags = FL_BASE0|FL_BASE_BARS, 3103 .num_ports = 1, 3104 .base_baud = 460800, 3105 .uart_offset = 8, 3106 }, 3107 [pbn_b0_bt_2_460800] = { 3108 .flags = FL_BASE0|FL_BASE_BARS, 3109 .num_ports = 2, 3110 .base_baud = 460800, 3111 .uart_offset = 8, 3112 }, 3113 [pbn_b0_bt_4_460800] = { 3114 .flags = FL_BASE0|FL_BASE_BARS, 3115 .num_ports = 4, 3116 .base_baud = 460800, 3117 .uart_offset = 8, 3118 }, 3119 3120 [pbn_b0_bt_1_921600] = { 3121 .flags = FL_BASE0|FL_BASE_BARS, 3122 .num_ports = 1, 3123 .base_baud = 921600, 3124 .uart_offset = 8, 3125 }, 3126 [pbn_b0_bt_2_921600] = { 3127 .flags = FL_BASE0|FL_BASE_BARS, 3128 .num_ports = 2, 3129 .base_baud = 921600, 3130 .uart_offset = 8, 3131 }, 3132 [pbn_b0_bt_4_921600] = { 3133 .flags = FL_BASE0|FL_BASE_BARS, 3134 .num_ports = 4, 3135 .base_baud = 921600, 3136 .uart_offset = 8, 3137 }, 3138 [pbn_b0_bt_8_921600] = { 3139 .flags = FL_BASE0|FL_BASE_BARS, 3140 .num_ports = 8, 3141 .base_baud = 921600, 3142 .uart_offset = 8, 3143 }, 3144 3145 [pbn_b1_1_115200] = { 3146 .flags = FL_BASE1, 3147 .num_ports = 1, 3148 .base_baud = 115200, 3149 .uart_offset = 8, 3150 }, 3151 [pbn_b1_2_115200] = { 3152 .flags = FL_BASE1, 3153 .num_ports = 2, 3154 .base_baud = 115200, 3155 .uart_offset = 8, 3156 }, 3157 [pbn_b1_4_115200] = { 3158 .flags = FL_BASE1, 3159 .num_ports = 4, 3160 .base_baud = 115200, 3161 .uart_offset = 8, 3162 }, 3163 [pbn_b1_8_115200] = { 3164 .flags = FL_BASE1, 3165 .num_ports = 8, 3166 .base_baud = 115200, 3167 .uart_offset = 8, 3168 }, 3169 [pbn_b1_16_115200] = { 3170 .flags = FL_BASE1, 3171 .num_ports = 16, 3172 .base_baud = 115200, 3173 .uart_offset = 8, 3174 }, 3175 3176 [pbn_b1_1_921600] = { 3177 .flags = FL_BASE1, 3178 .num_ports = 1, 3179 .base_baud = 921600, 3180 .uart_offset = 8, 3181 }, 3182 [pbn_b1_2_921600] = { 3183 .flags = FL_BASE1, 3184 .num_ports = 2, 3185 .base_baud = 921600, 3186 .uart_offset = 8, 3187 }, 3188 [pbn_b1_4_921600] = { 3189 .flags = FL_BASE1, 3190 .num_ports = 4, 3191 .base_baud = 921600, 3192 .uart_offset = 8, 3193 }, 3194 [pbn_b1_8_921600] = { 3195 .flags = FL_BASE1, 3196 .num_ports = 8, 3197 .base_baud = 921600, 3198 .uart_offset = 8, 3199 }, 3200 [pbn_b1_2_1250000] = { 3201 .flags = FL_BASE1, 3202 .num_ports = 2, 3203 .base_baud = 1250000, 3204 .uart_offset = 8, 3205 }, 3206 3207 [pbn_b1_bt_1_115200] = { 3208 .flags = FL_BASE1|FL_BASE_BARS, 3209 .num_ports = 1, 3210 .base_baud = 115200, 3211 .uart_offset = 8, 3212 }, 3213 [pbn_b1_bt_2_115200] = { 3214 .flags = FL_BASE1|FL_BASE_BARS, 3215 .num_ports = 2, 3216 .base_baud = 115200, 3217 .uart_offset = 8, 3218 }, 3219 [pbn_b1_bt_4_115200] = { 3220 .flags = FL_BASE1|FL_BASE_BARS, 3221 .num_ports = 4, 3222 .base_baud = 115200, 3223 .uart_offset = 8, 3224 }, 3225 3226 [pbn_b1_bt_2_921600] = { 3227 .flags = FL_BASE1|FL_BASE_BARS, 3228 .num_ports = 2, 3229 .base_baud = 921600, 3230 .uart_offset = 8, 3231 }, 3232 3233 [pbn_b1_1_1382400] = { 3234 .flags = FL_BASE1, 3235 .num_ports = 1, 3236 .base_baud = 1382400, 3237 .uart_offset = 8, 3238 }, 3239 [pbn_b1_2_1382400] = { 3240 .flags = FL_BASE1, 3241 .num_ports = 2, 3242 .base_baud = 1382400, 3243 .uart_offset = 8, 3244 }, 3245 [pbn_b1_4_1382400] = { 3246 .flags = FL_BASE1, 3247 .num_ports = 4, 3248 .base_baud = 1382400, 3249 .uart_offset = 8, 3250 }, 3251 [pbn_b1_8_1382400] = { 3252 .flags = FL_BASE1, 3253 .num_ports = 8, 3254 .base_baud = 1382400, 3255 .uart_offset = 8, 3256 }, 3257 3258 [pbn_b2_1_115200] = { 3259 .flags = FL_BASE2, 3260 .num_ports = 1, 3261 .base_baud = 115200, 3262 .uart_offset = 8, 3263 }, 3264 [pbn_b2_2_115200] = { 3265 .flags = FL_BASE2, 3266 .num_ports = 2, 3267 .base_baud = 115200, 3268 .uart_offset = 8, 3269 }, 3270 [pbn_b2_4_115200] = { 3271 .flags = FL_BASE2, 3272 .num_ports = 4, 3273 .base_baud = 115200, 3274 .uart_offset = 8, 3275 }, 3276 [pbn_b2_8_115200] = { 3277 .flags = FL_BASE2, 3278 .num_ports = 8, 3279 .base_baud = 115200, 3280 .uart_offset = 8, 3281 }, 3282 3283 [pbn_b2_1_460800] = { 3284 .flags = FL_BASE2, 3285 .num_ports = 1, 3286 .base_baud = 460800, 3287 .uart_offset = 8, 3288 }, 3289 [pbn_b2_4_460800] = { 3290 .flags = FL_BASE2, 3291 .num_ports = 4, 3292 .base_baud = 460800, 3293 .uart_offset = 8, 3294 }, 3295 [pbn_b2_8_460800] = { 3296 .flags = FL_BASE2, 3297 .num_ports = 8, 3298 .base_baud = 460800, 3299 .uart_offset = 8, 3300 }, 3301 [pbn_b2_16_460800] = { 3302 .flags = FL_BASE2, 3303 .num_ports = 16, 3304 .base_baud = 460800, 3305 .uart_offset = 8, 3306 }, 3307 3308 [pbn_b2_1_921600] = { 3309 .flags = FL_BASE2, 3310 .num_ports = 1, 3311 .base_baud = 921600, 3312 .uart_offset = 8, 3313 }, 3314 [pbn_b2_4_921600] = { 3315 .flags = FL_BASE2, 3316 .num_ports = 4, 3317 .base_baud = 921600, 3318 .uart_offset = 8, 3319 }, 3320 [pbn_b2_8_921600] = { 3321 .flags = FL_BASE2, 3322 .num_ports = 8, 3323 .base_baud = 921600, 3324 .uart_offset = 8, 3325 }, 3326 3327 [pbn_b2_8_1152000] = { 3328 .flags = FL_BASE2, 3329 .num_ports = 8, 3330 .base_baud = 1152000, 3331 .uart_offset = 8, 3332 }, 3333 3334 [pbn_b2_bt_1_115200] = { 3335 .flags = FL_BASE2|FL_BASE_BARS, 3336 .num_ports = 1, 3337 .base_baud = 115200, 3338 .uart_offset = 8, 3339 }, 3340 [pbn_b2_bt_2_115200] = { 3341 .flags = FL_BASE2|FL_BASE_BARS, 3342 .num_ports = 2, 3343 .base_baud = 115200, 3344 .uart_offset = 8, 3345 }, 3346 [pbn_b2_bt_4_115200] = { 3347 .flags = FL_BASE2|FL_BASE_BARS, 3348 .num_ports = 4, 3349 .base_baud = 115200, 3350 .uart_offset = 8, 3351 }, 3352 3353 [pbn_b2_bt_2_921600] = { 3354 .flags = FL_BASE2|FL_BASE_BARS, 3355 .num_ports = 2, 3356 .base_baud = 921600, 3357 .uart_offset = 8, 3358 }, 3359 [pbn_b2_bt_4_921600] = { 3360 .flags = FL_BASE2|FL_BASE_BARS, 3361 .num_ports = 4, 3362 .base_baud = 921600, 3363 .uart_offset = 8, 3364 }, 3365 3366 [pbn_b3_2_115200] = { 3367 .flags = FL_BASE3, 3368 .num_ports = 2, 3369 .base_baud = 115200, 3370 .uart_offset = 8, 3371 }, 3372 [pbn_b3_4_115200] = { 3373 .flags = FL_BASE3, 3374 .num_ports = 4, 3375 .base_baud = 115200, 3376 .uart_offset = 8, 3377 }, 3378 [pbn_b3_8_115200] = { 3379 .flags = FL_BASE3, 3380 .num_ports = 8, 3381 .base_baud = 115200, 3382 .uart_offset = 8, 3383 }, 3384 3385 [pbn_b4_bt_2_921600] = { 3386 .flags = FL_BASE4, 3387 .num_ports = 2, 3388 .base_baud = 921600, 3389 .uart_offset = 8, 3390 }, 3391 [pbn_b4_bt_4_921600] = { 3392 .flags = FL_BASE4, 3393 .num_ports = 4, 3394 .base_baud = 921600, 3395 .uart_offset = 8, 3396 }, 3397 [pbn_b4_bt_8_921600] = { 3398 .flags = FL_BASE4, 3399 .num_ports = 8, 3400 .base_baud = 921600, 3401 .uart_offset = 8, 3402 }, 3403 3404 /* 3405 * Entries following this are board-specific. 3406 */ 3407 3408 /* 3409 * Panacom - IOMEM 3410 */ 3411 [pbn_panacom] = { 3412 .flags = FL_BASE2, 3413 .num_ports = 2, 3414 .base_baud = 921600, 3415 .uart_offset = 0x400, 3416 .reg_shift = 7, 3417 }, 3418 [pbn_panacom2] = { 3419 .flags = FL_BASE2|FL_BASE_BARS, 3420 .num_ports = 2, 3421 .base_baud = 921600, 3422 .uart_offset = 0x400, 3423 .reg_shift = 7, 3424 }, 3425 [pbn_panacom4] = { 3426 .flags = FL_BASE2|FL_BASE_BARS, 3427 .num_ports = 4, 3428 .base_baud = 921600, 3429 .uart_offset = 0x400, 3430 .reg_shift = 7, 3431 }, 3432 3433 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3434 [pbn_plx_romulus] = { 3435 .flags = FL_BASE2, 3436 .num_ports = 4, 3437 .base_baud = 921600, 3438 .uart_offset = 8 << 2, 3439 .reg_shift = 2, 3440 .first_offset = 0x03, 3441 }, 3442 3443 /* 3444 * EndRun Technologies 3445 * Uses the size of PCI Base region 0 to 3446 * signal now many ports are available 3447 * 2 port 952 Uart support 3448 */ 3449 [pbn_endrun_2_4000000] = { 3450 .flags = FL_BASE0, 3451 .num_ports = 2, 3452 .base_baud = 4000000, 3453 .uart_offset = 0x200, 3454 .first_offset = 0x1000, 3455 }, 3456 3457 /* 3458 * This board uses the size of PCI Base region 0 to 3459 * signal now many ports are available 3460 */ 3461 [pbn_oxsemi] = { 3462 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3463 .num_ports = 32, 3464 .base_baud = 115200, 3465 .uart_offset = 8, 3466 }, 3467 [pbn_oxsemi_1_3906250] = { 3468 .flags = FL_BASE0, 3469 .num_ports = 1, 3470 .base_baud = 3906250, 3471 .uart_offset = 0x200, 3472 .first_offset = 0x1000, 3473 }, 3474 [pbn_oxsemi_2_3906250] = { 3475 .flags = FL_BASE0, 3476 .num_ports = 2, 3477 .base_baud = 3906250, 3478 .uart_offset = 0x200, 3479 .first_offset = 0x1000, 3480 }, 3481 [pbn_oxsemi_4_3906250] = { 3482 .flags = FL_BASE0, 3483 .num_ports = 4, 3484 .base_baud = 3906250, 3485 .uart_offset = 0x200, 3486 .first_offset = 0x1000, 3487 }, 3488 [pbn_oxsemi_8_3906250] = { 3489 .flags = FL_BASE0, 3490 .num_ports = 8, 3491 .base_baud = 3906250, 3492 .uart_offset = 0x200, 3493 .first_offset = 0x1000, 3494 }, 3495 3496 3497 /* 3498 * EKF addition for i960 Boards form EKF with serial port. 3499 * Max 256 ports. 3500 */ 3501 [pbn_intel_i960] = { 3502 .flags = FL_BASE0, 3503 .num_ports = 32, 3504 .base_baud = 921600, 3505 .uart_offset = 8 << 2, 3506 .reg_shift = 2, 3507 .first_offset = 0x10000, 3508 }, 3509 [pbn_sgi_ioc3] = { 3510 .flags = FL_BASE0|FL_NOIRQ, 3511 .num_ports = 1, 3512 .base_baud = 458333, 3513 .uart_offset = 8, 3514 .reg_shift = 0, 3515 .first_offset = 0x20178, 3516 }, 3517 3518 /* 3519 * Computone - uses IOMEM. 3520 */ 3521 [pbn_computone_4] = { 3522 .flags = FL_BASE0, 3523 .num_ports = 4, 3524 .base_baud = 921600, 3525 .uart_offset = 0x40, 3526 .reg_shift = 2, 3527 .first_offset = 0x200, 3528 }, 3529 [pbn_computone_6] = { 3530 .flags = FL_BASE0, 3531 .num_ports = 6, 3532 .base_baud = 921600, 3533 .uart_offset = 0x40, 3534 .reg_shift = 2, 3535 .first_offset = 0x200, 3536 }, 3537 [pbn_computone_8] = { 3538 .flags = FL_BASE0, 3539 .num_ports = 8, 3540 .base_baud = 921600, 3541 .uart_offset = 0x40, 3542 .reg_shift = 2, 3543 .first_offset = 0x200, 3544 }, 3545 [pbn_sbsxrsio] = { 3546 .flags = FL_BASE0, 3547 .num_ports = 8, 3548 .base_baud = 460800, 3549 .uart_offset = 256, 3550 .reg_shift = 4, 3551 }, 3552 /* 3553 * PA Semi PWRficient PA6T-1682M on-chip UART 3554 */ 3555 [pbn_pasemi_1682M] = { 3556 .flags = FL_BASE0, 3557 .num_ports = 1, 3558 .base_baud = 8333333, 3559 }, 3560 /* 3561 * National Instruments 843x 3562 */ 3563 [pbn_ni8430_16] = { 3564 .flags = FL_BASE0, 3565 .num_ports = 16, 3566 .base_baud = 3686400, 3567 .uart_offset = 0x10, 3568 .first_offset = 0x800, 3569 }, 3570 [pbn_ni8430_8] = { 3571 .flags = FL_BASE0, 3572 .num_ports = 8, 3573 .base_baud = 3686400, 3574 .uart_offset = 0x10, 3575 .first_offset = 0x800, 3576 }, 3577 [pbn_ni8430_4] = { 3578 .flags = FL_BASE0, 3579 .num_ports = 4, 3580 .base_baud = 3686400, 3581 .uart_offset = 0x10, 3582 .first_offset = 0x800, 3583 }, 3584 [pbn_ni8430_2] = { 3585 .flags = FL_BASE0, 3586 .num_ports = 2, 3587 .base_baud = 3686400, 3588 .uart_offset = 0x10, 3589 .first_offset = 0x800, 3590 }, 3591 /* 3592 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3593 */ 3594 [pbn_ADDIDATA_PCIe_1_3906250] = { 3595 .flags = FL_BASE0, 3596 .num_ports = 1, 3597 .base_baud = 3906250, 3598 .uart_offset = 0x200, 3599 .first_offset = 0x1000, 3600 }, 3601 [pbn_ADDIDATA_PCIe_2_3906250] = { 3602 .flags = FL_BASE0, 3603 .num_ports = 2, 3604 .base_baud = 3906250, 3605 .uart_offset = 0x200, 3606 .first_offset = 0x1000, 3607 }, 3608 [pbn_ADDIDATA_PCIe_4_3906250] = { 3609 .flags = FL_BASE0, 3610 .num_ports = 4, 3611 .base_baud = 3906250, 3612 .uart_offset = 0x200, 3613 .first_offset = 0x1000, 3614 }, 3615 [pbn_ADDIDATA_PCIe_8_3906250] = { 3616 .flags = FL_BASE0, 3617 .num_ports = 8, 3618 .base_baud = 3906250, 3619 .uart_offset = 0x200, 3620 .first_offset = 0x1000, 3621 }, 3622 [pbn_ce4100_1_115200] = { 3623 .flags = FL_BASE_BARS, 3624 .num_ports = 2, 3625 .base_baud = 921600, 3626 .reg_shift = 2, 3627 }, 3628 [pbn_omegapci] = { 3629 .flags = FL_BASE0, 3630 .num_ports = 8, 3631 .base_baud = 115200, 3632 .uart_offset = 0x200, 3633 }, 3634 [pbn_NETMOS9900_2s_115200] = { 3635 .flags = FL_BASE0, 3636 .num_ports = 2, 3637 .base_baud = 115200, 3638 }, 3639 [pbn_brcm_trumanage] = { 3640 .flags = FL_BASE0, 3641 .num_ports = 1, 3642 .reg_shift = 2, 3643 .base_baud = 115200, 3644 }, 3645 [pbn_fintek_4] = { 3646 .num_ports = 4, 3647 .uart_offset = 8, 3648 .base_baud = 115200, 3649 .first_offset = 0x40, 3650 }, 3651 [pbn_fintek_8] = { 3652 .num_ports = 8, 3653 .uart_offset = 8, 3654 .base_baud = 115200, 3655 .first_offset = 0x40, 3656 }, 3657 [pbn_fintek_12] = { 3658 .num_ports = 12, 3659 .uart_offset = 8, 3660 .base_baud = 115200, 3661 .first_offset = 0x40, 3662 }, 3663 [pbn_fintek_F81504A] = { 3664 .num_ports = 4, 3665 .uart_offset = 8, 3666 .base_baud = 115200, 3667 }, 3668 [pbn_fintek_F81508A] = { 3669 .num_ports = 8, 3670 .uart_offset = 8, 3671 .base_baud = 115200, 3672 }, 3673 [pbn_fintek_F81512A] = { 3674 .num_ports = 12, 3675 .uart_offset = 8, 3676 .base_baud = 115200, 3677 }, 3678 [pbn_wch382_2] = { 3679 .flags = FL_BASE0, 3680 .num_ports = 2, 3681 .base_baud = 115200, 3682 .uart_offset = 8, 3683 .first_offset = 0xC0, 3684 }, 3685 [pbn_wch384_4] = { 3686 .flags = FL_BASE0, 3687 .num_ports = 4, 3688 .base_baud = 115200, 3689 .uart_offset = 8, 3690 .first_offset = 0xC0, 3691 }, 3692 [pbn_wch384_8] = { 3693 .flags = FL_BASE0, 3694 .num_ports = 8, 3695 .base_baud = 115200, 3696 .uart_offset = 8, 3697 .first_offset = 0x00, 3698 }, 3699 /* 3700 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3701 */ 3702 [pbn_pericom_PI7C9X7951] = { 3703 .flags = FL_BASE0, 3704 .num_ports = 1, 3705 .base_baud = 921600, 3706 .uart_offset = 0x8, 3707 }, 3708 [pbn_pericom_PI7C9X7952] = { 3709 .flags = FL_BASE0, 3710 .num_ports = 2, 3711 .base_baud = 921600, 3712 .uart_offset = 0x8, 3713 }, 3714 [pbn_pericom_PI7C9X7954] = { 3715 .flags = FL_BASE0, 3716 .num_ports = 4, 3717 .base_baud = 921600, 3718 .uart_offset = 0x8, 3719 }, 3720 [pbn_pericom_PI7C9X7958] = { 3721 .flags = FL_BASE0, 3722 .num_ports = 8, 3723 .base_baud = 921600, 3724 .uart_offset = 0x8, 3725 }, 3726 [pbn_sunix_pci_1s] = { 3727 .num_ports = 1, 3728 .base_baud = 921600, 3729 .uart_offset = 0x8, 3730 }, 3731 [pbn_sunix_pci_2s] = { 3732 .num_ports = 2, 3733 .base_baud = 921600, 3734 .uart_offset = 0x8, 3735 }, 3736 [pbn_sunix_pci_4s] = { 3737 .num_ports = 4, 3738 .base_baud = 921600, 3739 .uart_offset = 0x8, 3740 }, 3741 [pbn_sunix_pci_8s] = { 3742 .num_ports = 8, 3743 .base_baud = 921600, 3744 .uart_offset = 0x8, 3745 }, 3746 [pbn_sunix_pci_16s] = { 3747 .num_ports = 16, 3748 .base_baud = 921600, 3749 .uart_offset = 0x8, 3750 }, 3751 [pbn_titan_1_4000000] = { 3752 .flags = FL_BASE0, 3753 .num_ports = 1, 3754 .base_baud = 4000000, 3755 .uart_offset = 0x200, 3756 .first_offset = 0x1000, 3757 }, 3758 [pbn_titan_2_4000000] = { 3759 .flags = FL_BASE0, 3760 .num_ports = 2, 3761 .base_baud = 4000000, 3762 .uart_offset = 0x200, 3763 .first_offset = 0x1000, 3764 }, 3765 [pbn_titan_4_4000000] = { 3766 .flags = FL_BASE0, 3767 .num_ports = 4, 3768 .base_baud = 4000000, 3769 .uart_offset = 0x200, 3770 .first_offset = 0x1000, 3771 }, 3772 [pbn_titan_8_4000000] = { 3773 .flags = FL_BASE0, 3774 .num_ports = 8, 3775 .base_baud = 4000000, 3776 .uart_offset = 0x200, 3777 .first_offset = 0x1000, 3778 }, 3779 [pbn_moxa8250_2p] = { 3780 .flags = FL_BASE1, 3781 .num_ports = 2, 3782 .base_baud = 921600, 3783 .uart_offset = 0x200, 3784 }, 3785 [pbn_moxa8250_4p] = { 3786 .flags = FL_BASE1, 3787 .num_ports = 4, 3788 .base_baud = 921600, 3789 .uart_offset = 0x200, 3790 }, 3791 [pbn_moxa8250_8p] = { 3792 .flags = FL_BASE1, 3793 .num_ports = 8, 3794 .base_baud = 921600, 3795 .uart_offset = 0x200, 3796 }, 3797 }; 3798 3799 static const struct pci_device_id blacklist[] = { 3800 /* softmodems */ 3801 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3802 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3803 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3804 3805 /* multi-io cards handled by parport_serial */ 3806 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3807 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3808 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3809 3810 /* Intel platforms with MID UART */ 3811 { PCI_VDEVICE(INTEL, 0x081b), }, 3812 { PCI_VDEVICE(INTEL, 0x081c), }, 3813 { PCI_VDEVICE(INTEL, 0x081d), }, 3814 { PCI_VDEVICE(INTEL, 0x1191), }, 3815 { PCI_VDEVICE(INTEL, 0x18d8), }, 3816 { PCI_VDEVICE(INTEL, 0x19d8), }, 3817 3818 /* Intel platforms with DesignWare UART */ 3819 { PCI_VDEVICE(INTEL, 0x0936), }, 3820 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3821 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3822 { PCI_VDEVICE(INTEL, 0x228a), }, 3823 { PCI_VDEVICE(INTEL, 0x228c), }, 3824 { PCI_VDEVICE(INTEL, 0x4b96), }, 3825 { PCI_VDEVICE(INTEL, 0x4b97), }, 3826 { PCI_VDEVICE(INTEL, 0x4b98), }, 3827 { PCI_VDEVICE(INTEL, 0x4b99), }, 3828 { PCI_VDEVICE(INTEL, 0x4b9a), }, 3829 { PCI_VDEVICE(INTEL, 0x4b9b), }, 3830 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3831 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3832 3833 /* Exar devices */ 3834 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3835 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3836 3837 /* End of the black list */ 3838 { } 3839 }; 3840 3841 static int serial_pci_is_class_communication(struct pci_dev *dev) 3842 { 3843 /* 3844 * If it is not a communications device or the programming 3845 * interface is greater than 6, give up. 3846 */ 3847 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3848 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3849 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3850 (dev->class & 0xff) > 6) 3851 return -ENODEV; 3852 3853 return 0; 3854 } 3855 3856 /* 3857 * Given a complete unknown PCI device, try to use some heuristics to 3858 * guess what the configuration might be, based on the pitiful PCI 3859 * serial specs. Returns 0 on success, -ENODEV on failure. 3860 */ 3861 static int 3862 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3863 { 3864 int num_iomem, num_port, first_port = -1, i; 3865 int rc; 3866 3867 rc = serial_pci_is_class_communication(dev); 3868 if (rc) 3869 return rc; 3870 3871 /* 3872 * Should we try to make guesses for multiport serial devices later? 3873 */ 3874 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3875 return -ENODEV; 3876 3877 num_iomem = num_port = 0; 3878 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3879 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3880 num_port++; 3881 if (first_port == -1) 3882 first_port = i; 3883 } 3884 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3885 num_iomem++; 3886 } 3887 3888 /* 3889 * If there is 1 or 0 iomem regions, and exactly one port, 3890 * use it. We guess the number of ports based on the IO 3891 * region size. 3892 */ 3893 if (num_iomem <= 1 && num_port == 1) { 3894 board->flags = first_port; 3895 board->num_ports = pci_resource_len(dev, first_port) / 8; 3896 return 0; 3897 } 3898 3899 /* 3900 * Now guess if we've got a board which indexes by BARs. 3901 * Each IO BAR should be 8 bytes, and they should follow 3902 * consecutively. 3903 */ 3904 first_port = -1; 3905 num_port = 0; 3906 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3907 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3908 pci_resource_len(dev, i) == 8 && 3909 (first_port == -1 || (first_port + num_port) == i)) { 3910 num_port++; 3911 if (first_port == -1) 3912 first_port = i; 3913 } 3914 } 3915 3916 if (num_port > 1) { 3917 board->flags = first_port | FL_BASE_BARS; 3918 board->num_ports = num_port; 3919 return 0; 3920 } 3921 3922 return -ENODEV; 3923 } 3924 3925 static inline int 3926 serial_pci_matches(const struct pciserial_board *board, 3927 const struct pciserial_board *guessed) 3928 { 3929 return 3930 board->num_ports == guessed->num_ports && 3931 board->base_baud == guessed->base_baud && 3932 board->uart_offset == guessed->uart_offset && 3933 board->reg_shift == guessed->reg_shift && 3934 board->first_offset == guessed->first_offset; 3935 } 3936 3937 struct serial_private * 3938 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3939 { 3940 struct uart_8250_port uart; 3941 struct serial_private *priv; 3942 struct pci_serial_quirk *quirk; 3943 int rc, nr_ports, i; 3944 3945 nr_ports = board->num_ports; 3946 3947 /* 3948 * Find an init and setup quirks. 3949 */ 3950 quirk = find_quirk(dev); 3951 3952 /* 3953 * Run the new-style initialization function. 3954 * The initialization function returns: 3955 * <0 - error 3956 * 0 - use board->num_ports 3957 * >0 - number of ports 3958 */ 3959 if (quirk->init) { 3960 rc = quirk->init(dev); 3961 if (rc < 0) { 3962 priv = ERR_PTR(rc); 3963 goto err_out; 3964 } 3965 if (rc) 3966 nr_ports = rc; 3967 } 3968 3969 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3970 if (!priv) { 3971 priv = ERR_PTR(-ENOMEM); 3972 goto err_deinit; 3973 } 3974 3975 priv->dev = dev; 3976 priv->quirk = quirk; 3977 3978 memset(&uart, 0, sizeof(uart)); 3979 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3980 uart.port.uartclk = board->base_baud * 16; 3981 3982 if (board->flags & FL_NOIRQ) { 3983 uart.port.irq = 0; 3984 } else { 3985 if (pci_match_id(pci_use_msi, dev)) { 3986 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3987 pci_set_master(dev); 3988 uart.port.flags &= ~UPF_SHARE_IRQ; 3989 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3990 } else { 3991 pci_dbg(dev, "Using legacy interrupts\n"); 3992 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3993 } 3994 if (rc < 0) { 3995 kfree(priv); 3996 priv = ERR_PTR(rc); 3997 goto err_deinit; 3998 } 3999 4000 uart.port.irq = pci_irq_vector(dev, 0); 4001 } 4002 4003 uart.port.dev = &dev->dev; 4004 4005 for (i = 0; i < nr_ports; i++) { 4006 if (quirk->setup(priv, board, &uart, i)) 4007 break; 4008 4009 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4010 uart.port.iobase, uart.port.irq, uart.port.iotype); 4011 4012 priv->line[i] = serial8250_register_8250_port(&uart); 4013 if (priv->line[i] < 0) { 4014 pci_err(dev, 4015 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4016 uart.port.iobase, uart.port.irq, 4017 uart.port.iotype, priv->line[i]); 4018 break; 4019 } 4020 } 4021 priv->nr = i; 4022 priv->board = board; 4023 return priv; 4024 4025 err_deinit: 4026 if (quirk->exit) 4027 quirk->exit(dev); 4028 err_out: 4029 return priv; 4030 } 4031 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4032 4033 static void pciserial_detach_ports(struct serial_private *priv) 4034 { 4035 struct pci_serial_quirk *quirk; 4036 int i; 4037 4038 for (i = 0; i < priv->nr; i++) 4039 serial8250_unregister_port(priv->line[i]); 4040 4041 /* 4042 * Find the exit quirks. 4043 */ 4044 quirk = find_quirk(priv->dev); 4045 if (quirk->exit) 4046 quirk->exit(priv->dev); 4047 } 4048 4049 void pciserial_remove_ports(struct serial_private *priv) 4050 { 4051 pciserial_detach_ports(priv); 4052 kfree(priv); 4053 } 4054 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4055 4056 void pciserial_suspend_ports(struct serial_private *priv) 4057 { 4058 int i; 4059 4060 for (i = 0; i < priv->nr; i++) 4061 if (priv->line[i] >= 0) 4062 serial8250_suspend_port(priv->line[i]); 4063 4064 /* 4065 * Ensure that every init quirk is properly torn down 4066 */ 4067 if (priv->quirk->exit) 4068 priv->quirk->exit(priv->dev); 4069 } 4070 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4071 4072 void pciserial_resume_ports(struct serial_private *priv) 4073 { 4074 int i; 4075 4076 /* 4077 * Ensure that the board is correctly configured. 4078 */ 4079 if (priv->quirk->init) 4080 priv->quirk->init(priv->dev); 4081 4082 for (i = 0; i < priv->nr; i++) 4083 if (priv->line[i] >= 0) 4084 serial8250_resume_port(priv->line[i]); 4085 } 4086 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4087 4088 /* 4089 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4090 * to the arrangement of serial ports on a PCI card. 4091 */ 4092 static int 4093 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4094 { 4095 struct pci_serial_quirk *quirk; 4096 struct serial_private *priv; 4097 const struct pciserial_board *board; 4098 const struct pci_device_id *exclude; 4099 struct pciserial_board tmp; 4100 int rc; 4101 4102 quirk = find_quirk(dev); 4103 if (quirk->probe) { 4104 rc = quirk->probe(dev); 4105 if (rc) 4106 return rc; 4107 } 4108 4109 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4110 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4111 return -EINVAL; 4112 } 4113 4114 board = &pci_boards[ent->driver_data]; 4115 4116 exclude = pci_match_id(blacklist, dev); 4117 if (exclude) 4118 return -ENODEV; 4119 4120 rc = pcim_enable_device(dev); 4121 pci_save_state(dev); 4122 if (rc) 4123 return rc; 4124 4125 if (ent->driver_data == pbn_default) { 4126 /* 4127 * Use a copy of the pci_board entry for this; 4128 * avoid changing entries in the table. 4129 */ 4130 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4131 board = &tmp; 4132 4133 /* 4134 * We matched one of our class entries. Try to 4135 * determine the parameters of this board. 4136 */ 4137 rc = serial_pci_guess_board(dev, &tmp); 4138 if (rc) 4139 return rc; 4140 } else { 4141 /* 4142 * We matched an explicit entry. If we are able to 4143 * detect this boards settings with our heuristic, 4144 * then we no longer need this entry. 4145 */ 4146 memcpy(&tmp, &pci_boards[pbn_default], 4147 sizeof(struct pciserial_board)); 4148 rc = serial_pci_guess_board(dev, &tmp); 4149 if (rc == 0 && serial_pci_matches(board, &tmp)) 4150 moan_device("Redundant entry in serial pci_table.", 4151 dev); 4152 } 4153 4154 priv = pciserial_init_ports(dev, board); 4155 if (IS_ERR(priv)) 4156 return PTR_ERR(priv); 4157 4158 pci_set_drvdata(dev, priv); 4159 return 0; 4160 } 4161 4162 static void pciserial_remove_one(struct pci_dev *dev) 4163 { 4164 struct serial_private *priv = pci_get_drvdata(dev); 4165 4166 pciserial_remove_ports(priv); 4167 } 4168 4169 #ifdef CONFIG_PM_SLEEP 4170 static int pciserial_suspend_one(struct device *dev) 4171 { 4172 struct serial_private *priv = dev_get_drvdata(dev); 4173 4174 if (priv) 4175 pciserial_suspend_ports(priv); 4176 4177 return 0; 4178 } 4179 4180 static int pciserial_resume_one(struct device *dev) 4181 { 4182 struct pci_dev *pdev = to_pci_dev(dev); 4183 struct serial_private *priv = pci_get_drvdata(pdev); 4184 int err; 4185 4186 if (priv) { 4187 /* 4188 * The device may have been disabled. Re-enable it. 4189 */ 4190 err = pci_enable_device(pdev); 4191 /* FIXME: We cannot simply error out here */ 4192 if (err) 4193 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4194 pciserial_resume_ports(priv); 4195 } 4196 return 0; 4197 } 4198 #endif 4199 4200 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4201 pciserial_resume_one); 4202 4203 static const struct pci_device_id serial_pci_tbl[] = { 4204 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4205 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4206 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4207 pbn_b2_8_921600 }, 4208 /* Advantech also use 0x3618 and 0xf618 */ 4209 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4210 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4211 pbn_b0_4_921600 }, 4212 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4213 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4214 pbn_b0_4_921600 }, 4215 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4216 PCI_SUBVENDOR_ID_CONNECT_TECH, 4217 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4218 pbn_b1_8_1382400 }, 4219 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4220 PCI_SUBVENDOR_ID_CONNECT_TECH, 4221 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4222 pbn_b1_4_1382400 }, 4223 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4224 PCI_SUBVENDOR_ID_CONNECT_TECH, 4225 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4226 pbn_b1_2_1382400 }, 4227 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4228 PCI_SUBVENDOR_ID_CONNECT_TECH, 4229 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4230 pbn_b1_8_1382400 }, 4231 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4232 PCI_SUBVENDOR_ID_CONNECT_TECH, 4233 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4234 pbn_b1_4_1382400 }, 4235 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4236 PCI_SUBVENDOR_ID_CONNECT_TECH, 4237 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4238 pbn_b1_2_1382400 }, 4239 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4240 PCI_SUBVENDOR_ID_CONNECT_TECH, 4241 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4242 pbn_b1_8_921600 }, 4243 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4244 PCI_SUBVENDOR_ID_CONNECT_TECH, 4245 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4246 pbn_b1_8_921600 }, 4247 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4248 PCI_SUBVENDOR_ID_CONNECT_TECH, 4249 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4250 pbn_b1_4_921600 }, 4251 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4252 PCI_SUBVENDOR_ID_CONNECT_TECH, 4253 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4254 pbn_b1_4_921600 }, 4255 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4256 PCI_SUBVENDOR_ID_CONNECT_TECH, 4257 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4258 pbn_b1_2_921600 }, 4259 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4260 PCI_SUBVENDOR_ID_CONNECT_TECH, 4261 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4262 pbn_b1_8_921600 }, 4263 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4264 PCI_SUBVENDOR_ID_CONNECT_TECH, 4265 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4266 pbn_b1_8_921600 }, 4267 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4268 PCI_SUBVENDOR_ID_CONNECT_TECH, 4269 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4270 pbn_b1_4_921600 }, 4271 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4272 PCI_SUBVENDOR_ID_CONNECT_TECH, 4273 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4274 pbn_b1_2_1250000 }, 4275 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4276 PCI_SUBVENDOR_ID_CONNECT_TECH, 4277 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4278 pbn_b0_2_1843200 }, 4279 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4280 PCI_SUBVENDOR_ID_CONNECT_TECH, 4281 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4282 pbn_b0_4_1843200 }, 4283 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4284 PCI_VENDOR_ID_AFAVLAB, 4285 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4286 pbn_b0_4_1152000 }, 4287 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_b2_bt_1_115200 }, 4290 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4292 pbn_b2_bt_2_115200 }, 4293 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4295 pbn_b2_bt_4_115200 }, 4296 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_b2_bt_2_115200 }, 4299 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_b2_bt_4_115200 }, 4302 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_b2_8_115200 }, 4305 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_b2_8_460800 }, 4308 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_b2_8_115200 }, 4311 4312 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4314 pbn_b2_bt_2_115200 }, 4315 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4317 pbn_b2_bt_2_921600 }, 4318 /* 4319 * VScom SPCOM800, from sl@s.pl 4320 */ 4321 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4323 pbn_b2_8_921600 }, 4324 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4326 pbn_b2_4_921600 }, 4327 /* Unknown card - subdevice 0x1584 */ 4328 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4329 PCI_VENDOR_ID_PLX, 4330 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4331 pbn_b2_4_115200 }, 4332 /* Unknown card - subdevice 0x1588 */ 4333 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4334 PCI_VENDOR_ID_PLX, 4335 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4336 pbn_b2_8_115200 }, 4337 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4338 PCI_SUBVENDOR_ID_KEYSPAN, 4339 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4340 pbn_panacom }, 4341 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_panacom4 }, 4344 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_panacom2 }, 4347 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4348 PCI_VENDOR_ID_ESDGMBH, 4349 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4350 pbn_b2_4_115200 }, 4351 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4352 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4353 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4354 pbn_b2_4_460800 }, 4355 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4356 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4357 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4358 pbn_b2_8_460800 }, 4359 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4360 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4361 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4362 pbn_b2_16_460800 }, 4363 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4364 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4365 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4366 pbn_b2_16_460800 }, 4367 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4368 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4369 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4370 pbn_b2_4_460800 }, 4371 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4372 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4373 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4374 pbn_b2_8_460800 }, 4375 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4376 PCI_SUBVENDOR_ID_EXSYS, 4377 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4378 pbn_b2_4_115200 }, 4379 /* 4380 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4381 * (Exoray@isys.ca) 4382 */ 4383 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4384 0x10b5, 0x106a, 0, 0, 4385 pbn_plx_romulus }, 4386 /* 4387 * EndRun Technologies. PCI express device range. 4388 * EndRun PTP/1588 has 2 Native UARTs. 4389 */ 4390 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_endrun_2_4000000 }, 4393 /* 4394 * Quatech cards. These actually have configurable clocks but for 4395 * now we just use the default. 4396 * 4397 * 100 series are RS232, 200 series RS422, 4398 */ 4399 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b1_4_115200 }, 4402 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b1_2_115200 }, 4405 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_b2_2_115200 }, 4408 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_b1_2_115200 }, 4411 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b2_2_115200 }, 4414 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b1_4_115200 }, 4417 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_b1_8_115200 }, 4420 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_b1_8_115200 }, 4423 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_b1_4_115200 }, 4426 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_b1_2_115200 }, 4429 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_b1_4_115200 }, 4432 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_b1_2_115200 }, 4435 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_b2_4_115200 }, 4438 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_b2_2_115200 }, 4441 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_b2_1_115200 }, 4444 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_b2_4_115200 }, 4447 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_b2_2_115200 }, 4450 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b2_1_115200 }, 4453 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_b0_8_115200 }, 4456 4457 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4458 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4459 0, 0, 4460 pbn_b0_4_921600 }, 4461 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4462 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4463 0, 0, 4464 pbn_b0_4_1152000 }, 4465 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_b0_bt_2_921600 }, 4468 4469 /* 4470 * The below card is a little controversial since it is the 4471 * subject of a PCI vendor/device ID clash. (See 4472 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4473 * For now just used the hex ID 0x950a. 4474 */ 4475 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4476 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4477 0, 0, pbn_b0_2_115200 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4479 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4480 0, 0, pbn_b0_2_115200 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_b0_2_1130000 }, 4484 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4485 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4486 pbn_b0_1_921600 }, 4487 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_b0_4_115200 }, 4490 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_b0_bt_2_921600 }, 4493 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_b2_8_1152000 }, 4496 4497 /* 4498 * Oxford Semiconductor Inc. Tornado PCI express device range. 4499 */ 4500 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_b0_1_3906250 }, 4503 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_b0_1_3906250 }, 4506 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_oxsemi_1_3906250 }, 4509 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_oxsemi_1_3906250 }, 4512 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_b0_1_3906250 }, 4515 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_b0_1_3906250 }, 4518 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_oxsemi_1_3906250 }, 4521 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_oxsemi_1_3906250 }, 4524 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4526 pbn_b0_1_3906250 }, 4527 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_b0_1_3906250 }, 4530 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4532 pbn_b0_1_3906250 }, 4533 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4535 pbn_b0_1_3906250 }, 4536 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4538 pbn_oxsemi_2_3906250 }, 4539 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4541 pbn_oxsemi_2_3906250 }, 4542 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4544 pbn_oxsemi_4_3906250 }, 4545 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4547 pbn_oxsemi_4_3906250 }, 4548 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4550 pbn_oxsemi_8_3906250 }, 4551 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4553 pbn_oxsemi_8_3906250 }, 4554 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4556 pbn_oxsemi_1_3906250 }, 4557 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_oxsemi_1_3906250 }, 4560 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4562 pbn_oxsemi_1_3906250 }, 4563 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_oxsemi_1_3906250 }, 4566 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_oxsemi_1_3906250 }, 4569 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_oxsemi_1_3906250 }, 4572 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_oxsemi_1_3906250 }, 4575 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_oxsemi_1_3906250 }, 4578 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4580 pbn_oxsemi_1_3906250 }, 4581 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_oxsemi_1_3906250 }, 4584 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_oxsemi_1_3906250 }, 4587 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_oxsemi_1_3906250 }, 4590 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_oxsemi_1_3906250 }, 4593 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_oxsemi_1_3906250 }, 4596 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_oxsemi_1_3906250 }, 4599 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_oxsemi_1_3906250 }, 4602 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_oxsemi_1_3906250 }, 4605 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_oxsemi_1_3906250 }, 4608 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_oxsemi_1_3906250 }, 4611 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_oxsemi_1_3906250 }, 4614 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_oxsemi_1_3906250 }, 4617 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_oxsemi_1_3906250 }, 4620 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_oxsemi_1_3906250 }, 4623 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_oxsemi_1_3906250 }, 4626 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_oxsemi_1_3906250 }, 4629 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_oxsemi_1_3906250 }, 4632 /* 4633 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4634 */ 4635 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4636 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4637 pbn_oxsemi_1_3906250 }, 4638 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4639 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4640 pbn_oxsemi_2_3906250 }, 4641 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4642 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4643 pbn_oxsemi_4_3906250 }, 4644 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4645 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4646 pbn_oxsemi_8_3906250 }, 4647 4648 /* 4649 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4650 */ 4651 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4652 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4653 pbn_oxsemi_2_3906250 }, 4654 4655 /* 4656 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4657 * from skokodyn@yahoo.com 4658 */ 4659 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4660 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4661 pbn_sbsxrsio }, 4662 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4663 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4664 pbn_sbsxrsio }, 4665 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4666 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4667 pbn_sbsxrsio }, 4668 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4669 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4670 pbn_sbsxrsio }, 4671 4672 /* 4673 * Digitan DS560-558, from jimd@esoft.com 4674 */ 4675 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b1_1_115200 }, 4678 4679 /* 4680 * Titan Electronic cards 4681 * The 400L and 800L have a custom setup quirk. 4682 */ 4683 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b0_1_921600 }, 4686 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b0_2_921600 }, 4689 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b0_4_921600 }, 4692 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b0_4_921600 }, 4695 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_b1_1_921600 }, 4698 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_b1_bt_2_921600 }, 4701 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_b0_bt_4_921600 }, 4704 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_b0_bt_8_921600 }, 4707 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_b4_bt_2_921600 }, 4710 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_b4_bt_4_921600 }, 4713 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_b4_bt_8_921600 }, 4716 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_b0_4_921600 }, 4719 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_b0_4_921600 }, 4722 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b0_4_921600 }, 4725 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_titan_1_4000000 }, 4728 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_titan_2_4000000 }, 4731 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_titan_4_4000000 }, 4734 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4736 pbn_titan_8_4000000 }, 4737 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4739 pbn_titan_2_4000000 }, 4740 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4742 pbn_titan_2_4000000 }, 4743 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4745 pbn_b0_bt_2_921600 }, 4746 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4748 pbn_b0_4_921600 }, 4749 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4751 pbn_b0_4_921600 }, 4752 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4754 pbn_b0_4_921600 }, 4755 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4757 pbn_b0_4_921600 }, 4758 4759 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_b2_1_460800 }, 4762 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b2_1_460800 }, 4765 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4767 pbn_b2_1_460800 }, 4768 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b2_bt_2_921600 }, 4771 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4773 pbn_b2_bt_2_921600 }, 4774 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4776 pbn_b2_bt_2_921600 }, 4777 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b2_bt_4_921600 }, 4780 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b2_bt_4_921600 }, 4783 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b2_bt_4_921600 }, 4786 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4788 pbn_b0_1_921600 }, 4789 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4791 pbn_b0_1_921600 }, 4792 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4794 pbn_b0_1_921600 }, 4795 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4797 pbn_b0_bt_2_921600 }, 4798 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4800 pbn_b0_bt_2_921600 }, 4801 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4803 pbn_b0_bt_2_921600 }, 4804 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4806 pbn_b0_bt_4_921600 }, 4807 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4808 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4809 pbn_b0_bt_4_921600 }, 4810 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4812 pbn_b0_bt_4_921600 }, 4813 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4814 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4815 pbn_b0_bt_8_921600 }, 4816 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4818 pbn_b0_bt_8_921600 }, 4819 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4820 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4821 pbn_b0_bt_8_921600 }, 4822 4823 /* 4824 * Computone devices submitted by Doug McNash dmcnash@computone.com 4825 */ 4826 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4827 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4828 0, 0, pbn_computone_4 }, 4829 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4830 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4831 0, 0, pbn_computone_8 }, 4832 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4833 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4834 0, 0, pbn_computone_6 }, 4835 4836 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4837 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4838 pbn_oxsemi }, 4839 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4840 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4841 pbn_b0_bt_1_921600 }, 4842 4843 /* 4844 * Sunix PCI serial boards 4845 */ 4846 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4847 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4848 pbn_sunix_pci_1s }, 4849 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4850 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4851 pbn_sunix_pci_2s }, 4852 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4853 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4854 pbn_sunix_pci_4s }, 4855 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4856 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4857 pbn_sunix_pci_4s }, 4858 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4859 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4860 pbn_sunix_pci_8s }, 4861 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4862 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4863 pbn_sunix_pci_8s }, 4864 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4865 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4866 pbn_sunix_pci_16s }, 4867 4868 /* 4869 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4870 */ 4871 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4873 pbn_b0_bt_8_115200 }, 4874 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b0_bt_8_115200 }, 4877 4878 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4880 pbn_b0_bt_2_115200 }, 4881 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4883 pbn_b0_bt_2_115200 }, 4884 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4886 pbn_b0_bt_2_115200 }, 4887 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4889 pbn_b0_bt_2_115200 }, 4890 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4892 pbn_b0_bt_2_115200 }, 4893 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4895 pbn_b0_bt_4_460800 }, 4896 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4898 pbn_b0_bt_4_460800 }, 4899 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_b0_bt_2_460800 }, 4902 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_b0_bt_2_460800 }, 4905 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_b0_bt_2_460800 }, 4908 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_b0_bt_1_115200 }, 4911 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4913 pbn_b0_bt_1_460800 }, 4914 4915 /* 4916 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4917 * Cards are identified by their subsystem vendor IDs, which 4918 * (in hex) match the model number. 4919 * 4920 * Note that JC140x are RS422/485 cards which require ox950 4921 * ACR = 0x10, and as such are not currently fully supported. 4922 */ 4923 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4924 0x1204, 0x0004, 0, 0, 4925 pbn_b0_4_921600 }, 4926 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4927 0x1208, 0x0004, 0, 0, 4928 pbn_b0_4_921600 }, 4929 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4930 0x1402, 0x0002, 0, 0, 4931 pbn_b0_2_921600 }, */ 4932 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4933 0x1404, 0x0004, 0, 0, 4934 pbn_b0_4_921600 }, */ 4935 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4936 0x1208, 0x0004, 0, 0, 4937 pbn_b0_4_921600 }, 4938 4939 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4940 0x1204, 0x0004, 0, 0, 4941 pbn_b0_4_921600 }, 4942 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4943 0x1208, 0x0004, 0, 0, 4944 pbn_b0_4_921600 }, 4945 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4946 0x1208, 0x0004, 0, 0, 4947 pbn_b0_4_921600 }, 4948 /* 4949 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4950 */ 4951 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4953 pbn_b1_1_1382400 }, 4954 4955 /* 4956 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4957 */ 4958 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4960 pbn_b1_1_1382400 }, 4961 4962 /* 4963 * RAStel 2 port modem, gerg@moreton.com.au 4964 */ 4965 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4967 pbn_b2_bt_2_115200 }, 4968 4969 /* 4970 * EKF addition for i960 Boards form EKF with serial port 4971 */ 4972 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4973 0xE4BF, PCI_ANY_ID, 0, 0, 4974 pbn_intel_i960 }, 4975 4976 /* 4977 * Xircom Cardbus/Ethernet combos 4978 */ 4979 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4981 pbn_b0_1_115200 }, 4982 /* 4983 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4984 */ 4985 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4987 pbn_b0_1_115200 }, 4988 4989 /* 4990 * Untested PCI modems, sent in from various folks... 4991 */ 4992 4993 /* 4994 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4995 */ 4996 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4997 0x1048, 0x1500, 0, 0, 4998 pbn_b1_1_115200 }, 4999 5000 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 5001 0xFF00, 0, 0, 0, 5002 pbn_sgi_ioc3 }, 5003 5004 /* 5005 * HP Diva card 5006 */ 5007 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5008 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 5009 pbn_b1_1_115200 }, 5010 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_b0_5_115200 }, 5013 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_b2_1_115200 }, 5016 /* HPE PCI serial device */ 5017 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5019 pbn_b1_1_115200 }, 5020 5021 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 5022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5023 pbn_b3_2_115200 }, 5024 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 5025 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5026 pbn_b3_4_115200 }, 5027 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 5028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5029 pbn_b3_8_115200 }, 5030 /* 5031 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 5032 */ 5033 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 5034 PCI_ANY_ID, PCI_ANY_ID, 5035 0, 5036 0, pbn_pericom_PI7C9X7951 }, 5037 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 5038 PCI_ANY_ID, PCI_ANY_ID, 5039 0, 5040 0, pbn_pericom_PI7C9X7952 }, 5041 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 5042 PCI_ANY_ID, PCI_ANY_ID, 5043 0, 5044 0, pbn_pericom_PI7C9X7954 }, 5045 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5046 PCI_ANY_ID, PCI_ANY_ID, 5047 0, 5048 0, pbn_pericom_PI7C9X7958 }, 5049 /* 5050 * ACCES I/O Products quad 5051 */ 5052 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_pericom_PI7C9X7952 }, 5055 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_pericom_PI7C9X7952 }, 5058 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_pericom_PI7C9X7954 }, 5061 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_pericom_PI7C9X7954 }, 5064 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_pericom_PI7C9X7952 }, 5067 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5069 pbn_pericom_PI7C9X7952 }, 5070 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5072 pbn_pericom_PI7C9X7954 }, 5073 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5075 pbn_pericom_PI7C9X7954 }, 5076 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5078 pbn_pericom_PI7C9X7952 }, 5079 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5081 pbn_pericom_PI7C9X7952 }, 5082 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5084 pbn_pericom_PI7C9X7954 }, 5085 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5087 pbn_pericom_PI7C9X7954 }, 5088 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5090 pbn_pericom_PI7C9X7951 }, 5091 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5093 pbn_pericom_PI7C9X7952 }, 5094 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5096 pbn_pericom_PI7C9X7952 }, 5097 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5099 pbn_pericom_PI7C9X7954 }, 5100 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5102 pbn_pericom_PI7C9X7954 }, 5103 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5105 pbn_pericom_PI7C9X7952 }, 5106 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5108 pbn_pericom_PI7C9X7954 }, 5109 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5111 pbn_pericom_PI7C9X7952 }, 5112 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5114 pbn_pericom_PI7C9X7952 }, 5115 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5117 pbn_pericom_PI7C9X7954 }, 5118 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5120 pbn_pericom_PI7C9X7954 }, 5121 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5123 pbn_pericom_PI7C9X7952 }, 5124 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5126 pbn_pericom_PI7C9X7954 }, 5127 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5129 pbn_pericom_PI7C9X7954 }, 5130 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5132 pbn_pericom_PI7C9X7958 }, 5133 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5135 pbn_pericom_PI7C9X7958 }, 5136 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5138 pbn_pericom_PI7C9X7954 }, 5139 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5141 pbn_pericom_PI7C9X7958 }, 5142 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5144 pbn_pericom_PI7C9X7954 }, 5145 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5147 pbn_pericom_PI7C9X7958 }, 5148 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5150 pbn_pericom_PI7C9X7954 }, 5151 /* 5152 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5153 */ 5154 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5156 pbn_b0_1_115200 }, 5157 /* 5158 * ITE 5159 */ 5160 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5161 PCI_ANY_ID, PCI_ANY_ID, 5162 0, 0, 5163 pbn_b1_bt_1_115200 }, 5164 5165 /* 5166 * IntaShield IS-200 5167 */ 5168 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5170 pbn_b2_2_115200 }, 5171 /* 5172 * IntaShield IS-400 5173 */ 5174 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5176 pbn_b2_4_115200 }, 5177 /* 5178 * BrainBoxes UC-260 5179 */ 5180 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5181 PCI_ANY_ID, PCI_ANY_ID, 5182 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5183 pbn_b2_4_115200 }, 5184 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5185 PCI_ANY_ID, PCI_ANY_ID, 5186 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5187 pbn_b2_4_115200 }, 5188 /* 5189 * Perle PCI-RAS cards 5190 */ 5191 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5192 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5193 0, 0, pbn_b2_4_921600 }, 5194 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5195 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5196 0, 0, pbn_b2_8_921600 }, 5197 5198 /* 5199 * Mainpine series cards: Fairly standard layout but fools 5200 * parts of the autodetect in some cases and uses otherwise 5201 * unmatched communications subclasses in the PCI Express case 5202 */ 5203 5204 { /* RockForceDUO */ 5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5206 PCI_VENDOR_ID_MAINPINE, 0x0200, 5207 0, 0, pbn_b0_2_115200 }, 5208 { /* RockForceQUATRO */ 5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5210 PCI_VENDOR_ID_MAINPINE, 0x0300, 5211 0, 0, pbn_b0_4_115200 }, 5212 { /* RockForceDUO+ */ 5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5214 PCI_VENDOR_ID_MAINPINE, 0x0400, 5215 0, 0, pbn_b0_2_115200 }, 5216 { /* RockForceQUATRO+ */ 5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5218 PCI_VENDOR_ID_MAINPINE, 0x0500, 5219 0, 0, pbn_b0_4_115200 }, 5220 { /* RockForce+ */ 5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5222 PCI_VENDOR_ID_MAINPINE, 0x0600, 5223 0, 0, pbn_b0_2_115200 }, 5224 { /* RockForce+ */ 5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5226 PCI_VENDOR_ID_MAINPINE, 0x0700, 5227 0, 0, pbn_b0_4_115200 }, 5228 { /* RockForceOCTO+ */ 5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5230 PCI_VENDOR_ID_MAINPINE, 0x0800, 5231 0, 0, pbn_b0_8_115200 }, 5232 { /* RockForceDUO+ */ 5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5234 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5235 0, 0, pbn_b0_2_115200 }, 5236 { /* RockForceQUARTRO+ */ 5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5238 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5239 0, 0, pbn_b0_4_115200 }, 5240 { /* RockForceOCTO+ */ 5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5242 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5243 0, 0, pbn_b0_8_115200 }, 5244 { /* RockForceD1 */ 5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5246 PCI_VENDOR_ID_MAINPINE, 0x2000, 5247 0, 0, pbn_b0_1_115200 }, 5248 { /* RockForceF1 */ 5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5250 PCI_VENDOR_ID_MAINPINE, 0x2100, 5251 0, 0, pbn_b0_1_115200 }, 5252 { /* RockForceD2 */ 5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5254 PCI_VENDOR_ID_MAINPINE, 0x2200, 5255 0, 0, pbn_b0_2_115200 }, 5256 { /* RockForceF2 */ 5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5258 PCI_VENDOR_ID_MAINPINE, 0x2300, 5259 0, 0, pbn_b0_2_115200 }, 5260 { /* RockForceD4 */ 5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5262 PCI_VENDOR_ID_MAINPINE, 0x2400, 5263 0, 0, pbn_b0_4_115200 }, 5264 { /* RockForceF4 */ 5265 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5266 PCI_VENDOR_ID_MAINPINE, 0x2500, 5267 0, 0, pbn_b0_4_115200 }, 5268 { /* RockForceD8 */ 5269 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5270 PCI_VENDOR_ID_MAINPINE, 0x2600, 5271 0, 0, pbn_b0_8_115200 }, 5272 { /* RockForceF8 */ 5273 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5274 PCI_VENDOR_ID_MAINPINE, 0x2700, 5275 0, 0, pbn_b0_8_115200 }, 5276 { /* IQ Express D1 */ 5277 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5278 PCI_VENDOR_ID_MAINPINE, 0x3000, 5279 0, 0, pbn_b0_1_115200 }, 5280 { /* IQ Express F1 */ 5281 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5282 PCI_VENDOR_ID_MAINPINE, 0x3100, 5283 0, 0, pbn_b0_1_115200 }, 5284 { /* IQ Express D2 */ 5285 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5286 PCI_VENDOR_ID_MAINPINE, 0x3200, 5287 0, 0, pbn_b0_2_115200 }, 5288 { /* IQ Express F2 */ 5289 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5290 PCI_VENDOR_ID_MAINPINE, 0x3300, 5291 0, 0, pbn_b0_2_115200 }, 5292 { /* IQ Express D4 */ 5293 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5294 PCI_VENDOR_ID_MAINPINE, 0x3400, 5295 0, 0, pbn_b0_4_115200 }, 5296 { /* IQ Express F4 */ 5297 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5298 PCI_VENDOR_ID_MAINPINE, 0x3500, 5299 0, 0, pbn_b0_4_115200 }, 5300 { /* IQ Express D8 */ 5301 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5302 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5303 0, 0, pbn_b0_8_115200 }, 5304 { /* IQ Express F8 */ 5305 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5306 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5307 0, 0, pbn_b0_8_115200 }, 5308 5309 5310 /* 5311 * PA Semi PA6T-1682M on-chip UART 5312 */ 5313 { PCI_VENDOR_ID_PASEMI, 0xa004, 5314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5315 pbn_pasemi_1682M }, 5316 5317 /* 5318 * National Instruments 5319 */ 5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5322 pbn_b1_16_115200 }, 5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5325 pbn_b1_8_115200 }, 5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5328 pbn_b1_bt_4_115200 }, 5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5331 pbn_b1_bt_2_115200 }, 5332 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5334 pbn_b1_bt_4_115200 }, 5335 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5337 pbn_b1_bt_2_115200 }, 5338 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5340 pbn_b1_16_115200 }, 5341 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5343 pbn_b1_8_115200 }, 5344 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5346 pbn_b1_bt_4_115200 }, 5347 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5349 pbn_b1_bt_2_115200 }, 5350 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5352 pbn_b1_bt_4_115200 }, 5353 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5355 pbn_b1_bt_2_115200 }, 5356 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5358 pbn_ni8430_2 }, 5359 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5361 pbn_ni8430_2 }, 5362 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5364 pbn_ni8430_4 }, 5365 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5367 pbn_ni8430_4 }, 5368 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5370 pbn_ni8430_8 }, 5371 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5373 pbn_ni8430_8 }, 5374 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5376 pbn_ni8430_16 }, 5377 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5379 pbn_ni8430_16 }, 5380 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5382 pbn_ni8430_2 }, 5383 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5385 pbn_ni8430_2 }, 5386 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5388 pbn_ni8430_4 }, 5389 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5391 pbn_ni8430_4 }, 5392 5393 /* 5394 * MOXA 5395 */ 5396 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5398 pbn_moxa8250_2p }, 5399 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5401 pbn_moxa8250_2p }, 5402 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5404 pbn_moxa8250_4p }, 5405 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5407 pbn_moxa8250_4p }, 5408 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5410 pbn_moxa8250_8p }, 5411 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5413 pbn_moxa8250_8p }, 5414 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5416 pbn_moxa8250_8p }, 5417 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5419 pbn_moxa8250_8p }, 5420 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5422 pbn_moxa8250_2p }, 5423 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5425 pbn_moxa8250_4p }, 5426 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5428 pbn_moxa8250_8p }, 5429 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5431 pbn_moxa8250_8p }, 5432 5433 /* 5434 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5435 */ 5436 { PCI_VENDOR_ID_ADDIDATA, 5437 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5438 PCI_ANY_ID, 5439 PCI_ANY_ID, 5440 0, 5441 0, 5442 pbn_b0_4_115200 }, 5443 5444 { PCI_VENDOR_ID_ADDIDATA, 5445 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5446 PCI_ANY_ID, 5447 PCI_ANY_ID, 5448 0, 5449 0, 5450 pbn_b0_2_115200 }, 5451 5452 { PCI_VENDOR_ID_ADDIDATA, 5453 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5454 PCI_ANY_ID, 5455 PCI_ANY_ID, 5456 0, 5457 0, 5458 pbn_b0_1_115200 }, 5459 5460 { PCI_VENDOR_ID_AMCC, 5461 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5462 PCI_ANY_ID, 5463 PCI_ANY_ID, 5464 0, 5465 0, 5466 pbn_b1_8_115200 }, 5467 5468 { PCI_VENDOR_ID_ADDIDATA, 5469 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5470 PCI_ANY_ID, 5471 PCI_ANY_ID, 5472 0, 5473 0, 5474 pbn_b0_4_115200 }, 5475 5476 { PCI_VENDOR_ID_ADDIDATA, 5477 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5478 PCI_ANY_ID, 5479 PCI_ANY_ID, 5480 0, 5481 0, 5482 pbn_b0_2_115200 }, 5483 5484 { PCI_VENDOR_ID_ADDIDATA, 5485 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5486 PCI_ANY_ID, 5487 PCI_ANY_ID, 5488 0, 5489 0, 5490 pbn_b0_1_115200 }, 5491 5492 { PCI_VENDOR_ID_ADDIDATA, 5493 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5494 PCI_ANY_ID, 5495 PCI_ANY_ID, 5496 0, 5497 0, 5498 pbn_b0_4_115200 }, 5499 5500 { PCI_VENDOR_ID_ADDIDATA, 5501 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5502 PCI_ANY_ID, 5503 PCI_ANY_ID, 5504 0, 5505 0, 5506 pbn_b0_2_115200 }, 5507 5508 { PCI_VENDOR_ID_ADDIDATA, 5509 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5510 PCI_ANY_ID, 5511 PCI_ANY_ID, 5512 0, 5513 0, 5514 pbn_b0_1_115200 }, 5515 5516 { PCI_VENDOR_ID_ADDIDATA, 5517 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5518 PCI_ANY_ID, 5519 PCI_ANY_ID, 5520 0, 5521 0, 5522 pbn_b0_8_115200 }, 5523 5524 { PCI_VENDOR_ID_ADDIDATA, 5525 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5526 PCI_ANY_ID, 5527 PCI_ANY_ID, 5528 0, 5529 0, 5530 pbn_ADDIDATA_PCIe_4_3906250 }, 5531 5532 { PCI_VENDOR_ID_ADDIDATA, 5533 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5534 PCI_ANY_ID, 5535 PCI_ANY_ID, 5536 0, 5537 0, 5538 pbn_ADDIDATA_PCIe_2_3906250 }, 5539 5540 { PCI_VENDOR_ID_ADDIDATA, 5541 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5542 PCI_ANY_ID, 5543 PCI_ANY_ID, 5544 0, 5545 0, 5546 pbn_ADDIDATA_PCIe_1_3906250 }, 5547 5548 { PCI_VENDOR_ID_ADDIDATA, 5549 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5550 PCI_ANY_ID, 5551 PCI_ANY_ID, 5552 0, 5553 0, 5554 pbn_ADDIDATA_PCIe_8_3906250 }, 5555 5556 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5557 PCI_VENDOR_ID_IBM, 0x0299, 5558 0, 0, pbn_b0_bt_2_115200 }, 5559 5560 /* 5561 * other NetMos 9835 devices are most likely handled by the 5562 * parport_serial driver, check drivers/parport/parport_serial.c 5563 * before adding them here. 5564 */ 5565 5566 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5567 0xA000, 0x1000, 5568 0, 0, pbn_b0_1_115200 }, 5569 5570 /* the 9901 is a rebranded 9912 */ 5571 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5572 0xA000, 0x1000, 5573 0, 0, pbn_b0_1_115200 }, 5574 5575 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5576 0xA000, 0x1000, 5577 0, 0, pbn_b0_1_115200 }, 5578 5579 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5580 0xA000, 0x1000, 5581 0, 0, pbn_b0_1_115200 }, 5582 5583 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5584 0xA000, 0x1000, 5585 0, 0, pbn_b0_1_115200 }, 5586 5587 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5588 0xA000, 0x3002, 5589 0, 0, pbn_NETMOS9900_2s_115200 }, 5590 5591 /* 5592 * Best Connectivity and Rosewill PCI Multi I/O cards 5593 */ 5594 5595 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5596 0xA000, 0x1000, 5597 0, 0, pbn_b0_1_115200 }, 5598 5599 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5600 0xA000, 0x3002, 5601 0, 0, pbn_b0_bt_2_115200 }, 5602 5603 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5604 0xA000, 0x3004, 5605 0, 0, pbn_b0_bt_4_115200 }, 5606 /* Intel CE4100 */ 5607 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5609 pbn_ce4100_1_115200 }, 5610 5611 /* 5612 * Cronyx Omega PCI 5613 */ 5614 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5616 pbn_omegapci }, 5617 5618 /* 5619 * Broadcom TruManage 5620 */ 5621 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5623 pbn_brcm_trumanage }, 5624 5625 /* 5626 * AgeStar as-prs2-009 5627 */ 5628 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5629 PCI_ANY_ID, PCI_ANY_ID, 5630 0, 0, pbn_b0_bt_2_115200 }, 5631 5632 /* 5633 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5634 * so not listed here. 5635 */ 5636 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5637 PCI_ANY_ID, PCI_ANY_ID, 5638 0, 0, pbn_b0_bt_4_115200 }, 5639 5640 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5641 PCI_ANY_ID, PCI_ANY_ID, 5642 0, 0, pbn_b0_bt_2_115200 }, 5643 5644 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5645 PCI_ANY_ID, PCI_ANY_ID, 5646 0, 0, pbn_b0_bt_4_115200 }, 5647 5648 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5649 PCI_ANY_ID, PCI_ANY_ID, 5650 0, 0, pbn_wch382_2 }, 5651 5652 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5653 PCI_ANY_ID, PCI_ANY_ID, 5654 0, 0, pbn_wch384_4 }, 5655 5656 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5657 PCI_ANY_ID, PCI_ANY_ID, 5658 0, 0, pbn_wch384_8 }, 5659 /* 5660 * Realtek RealManage 5661 */ 5662 { PCI_VENDOR_ID_REALTEK, 0x816a, 5663 PCI_ANY_ID, PCI_ANY_ID, 5664 0, 0, pbn_b0_1_115200 }, 5665 5666 { PCI_VENDOR_ID_REALTEK, 0x816b, 5667 PCI_ANY_ID, PCI_ANY_ID, 5668 0, 0, pbn_b0_1_115200 }, 5669 5670 /* Fintek PCI serial cards */ 5671 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5672 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5673 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5674 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5675 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5676 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5677 5678 /* MKS Tenta SCOM-080x serial cards */ 5679 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5680 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5681 5682 /* Amazon PCI serial device */ 5683 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5684 5685 /* 5686 * These entries match devices with class COMMUNICATION_SERIAL, 5687 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5688 */ 5689 { PCI_ANY_ID, PCI_ANY_ID, 5690 PCI_ANY_ID, PCI_ANY_ID, 5691 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5692 0xffff00, pbn_default }, 5693 { PCI_ANY_ID, PCI_ANY_ID, 5694 PCI_ANY_ID, PCI_ANY_ID, 5695 PCI_CLASS_COMMUNICATION_MODEM << 8, 5696 0xffff00, pbn_default }, 5697 { PCI_ANY_ID, PCI_ANY_ID, 5698 PCI_ANY_ID, PCI_ANY_ID, 5699 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5700 0xffff00, pbn_default }, 5701 { 0, } 5702 }; 5703 5704 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5705 pci_channel_state_t state) 5706 { 5707 struct serial_private *priv = pci_get_drvdata(dev); 5708 5709 if (state == pci_channel_io_perm_failure) 5710 return PCI_ERS_RESULT_DISCONNECT; 5711 5712 if (priv) 5713 pciserial_detach_ports(priv); 5714 5715 pci_disable_device(dev); 5716 5717 return PCI_ERS_RESULT_NEED_RESET; 5718 } 5719 5720 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5721 { 5722 int rc; 5723 5724 rc = pci_enable_device(dev); 5725 5726 if (rc) 5727 return PCI_ERS_RESULT_DISCONNECT; 5728 5729 pci_restore_state(dev); 5730 pci_save_state(dev); 5731 5732 return PCI_ERS_RESULT_RECOVERED; 5733 } 5734 5735 static void serial8250_io_resume(struct pci_dev *dev) 5736 { 5737 struct serial_private *priv = pci_get_drvdata(dev); 5738 struct serial_private *new; 5739 5740 if (!priv) 5741 return; 5742 5743 new = pciserial_init_ports(dev, priv->board); 5744 if (!IS_ERR(new)) { 5745 pci_set_drvdata(dev, new); 5746 kfree(priv); 5747 } 5748 } 5749 5750 static const struct pci_error_handlers serial8250_err_handler = { 5751 .error_detected = serial8250_io_error_detected, 5752 .slot_reset = serial8250_io_slot_reset, 5753 .resume = serial8250_io_resume, 5754 }; 5755 5756 static struct pci_driver serial_pci_driver = { 5757 .name = "serial", 5758 .probe = pciserial_init_one, 5759 .remove = pciserial_remove_one, 5760 .driver = { 5761 .pm = &pciserial_pm_ops, 5762 }, 5763 .id_table = serial_pci_tbl, 5764 .err_handler = &serial8250_err_handler, 5765 }; 5766 5767 module_pci_driver(serial_pci_driver); 5768 5769 MODULE_LICENSE("GPL"); 5770 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5771 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5772