1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 #define PCI_NUM_BAR_RESOURCES 6 47 48 struct serial_private { 49 struct pci_dev *dev; 50 unsigned int nr; 51 struct pci_serial_quirk *quirk; 52 const struct pciserial_board *board; 53 int line[0]; 54 }; 55 56 static int pci_default_setup(struct serial_private*, 57 const struct pciserial_board*, struct uart_8250_port *, int); 58 59 static void moan_device(const char *str, struct pci_dev *dev) 60 { 61 dev_err(&dev->dev, 62 "%s: %s\n" 63 "Please send the output of lspci -vv, this\n" 64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 65 "manufacturer and name of serial board or\n" 66 "modem board to <linux-serial@vger.kernel.org>.\n", 67 pci_name(dev), str, dev->vendor, dev->device, 68 dev->subsystem_vendor, dev->subsystem_device); 69 } 70 71 static int 72 setup_port(struct serial_private *priv, struct uart_8250_port *port, 73 int bar, int offset, int regshift) 74 { 75 struct pci_dev *dev = priv->dev; 76 77 if (bar >= PCI_NUM_BAR_RESOURCES) 78 return -EINVAL; 79 80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 82 return -ENOMEM; 83 84 port->port.iotype = UPIO_MEM; 85 port->port.iobase = 0; 86 port->port.mapbase = pci_resource_start(dev, bar) + offset; 87 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 88 port->port.regshift = regshift; 89 } else { 90 port->port.iotype = UPIO_PORT; 91 port->port.iobase = pci_resource_start(dev, bar) + offset; 92 port->port.mapbase = 0; 93 port->port.membase = NULL; 94 port->port.regshift = 0; 95 } 96 return 0; 97 } 98 99 /* 100 * ADDI-DATA GmbH communication cards <info@addi-data.com> 101 */ 102 static int addidata_apci7800_setup(struct serial_private *priv, 103 const struct pciserial_board *board, 104 struct uart_8250_port *port, int idx) 105 { 106 unsigned int bar = 0, offset = board->first_offset; 107 bar = FL_GET_BASE(board->flags); 108 109 if (idx < 2) { 110 offset += idx * board->uart_offset; 111 } else if ((idx >= 2) && (idx < 4)) { 112 bar += 1; 113 offset += ((idx - 2) * board->uart_offset); 114 } else if ((idx >= 4) && (idx < 6)) { 115 bar += 2; 116 offset += ((idx - 4) * board->uart_offset); 117 } else if (idx >= 6) { 118 bar += 3; 119 offset += ((idx - 6) * board->uart_offset); 120 } 121 122 return setup_port(priv, port, bar, offset, board->reg_shift); 123 } 124 125 /* 126 * AFAVLAB uses a different mixture of BARs and offsets 127 * Not that ugly ;) -- HW 128 */ 129 static int 130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 131 struct uart_8250_port *port, int idx) 132 { 133 unsigned int bar, offset = board->first_offset; 134 135 bar = FL_GET_BASE(board->flags); 136 if (idx < 4) 137 bar += idx; 138 else { 139 bar = 4; 140 offset += (idx - 4) * board->uart_offset; 141 } 142 143 return setup_port(priv, port, bar, offset, board->reg_shift); 144 } 145 146 /* 147 * HP's Remote Management Console. The Diva chip came in several 148 * different versions. N-class, L2000 and A500 have two Diva chips, each 149 * with 3 UARTs (the third UART on the second chip is unused). Superdome 150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 151 * one Diva chip, but it has been expanded to 5 UARTs. 152 */ 153 static int pci_hp_diva_init(struct pci_dev *dev) 154 { 155 int rc = 0; 156 157 switch (dev->subsystem_device) { 158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 161 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 162 rc = 3; 163 break; 164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 165 rc = 2; 166 break; 167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 168 rc = 4; 169 break; 170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 172 rc = 1; 173 break; 174 } 175 176 return rc; 177 } 178 179 /* 180 * HP's Diva chip puts the 4th/5th serial port further out, and 181 * some serial ports are supposed to be hidden on certain models. 182 */ 183 static int 184 pci_hp_diva_setup(struct serial_private *priv, 185 const struct pciserial_board *board, 186 struct uart_8250_port *port, int idx) 187 { 188 unsigned int offset = board->first_offset; 189 unsigned int bar = FL_GET_BASE(board->flags); 190 191 switch (priv->dev->subsystem_device) { 192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 193 if (idx == 3) 194 idx++; 195 break; 196 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 197 if (idx > 0) 198 idx++; 199 if (idx > 2) 200 idx++; 201 break; 202 } 203 if (idx > 2) 204 offset = 0x18; 205 206 offset += idx * board->uart_offset; 207 208 return setup_port(priv, port, bar, offset, board->reg_shift); 209 } 210 211 /* 212 * Added for EKF Intel i960 serial boards 213 */ 214 static int pci_inteli960ni_init(struct pci_dev *dev) 215 { 216 u32 oldval; 217 218 if (!(dev->subsystem_device & 0x1000)) 219 return -ENODEV; 220 221 /* is firmware started? */ 222 pci_read_config_dword(dev, 0x44, &oldval); 223 if (oldval == 0x00001000L) { /* RESET value */ 224 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 225 return -ENODEV; 226 } 227 return 0; 228 } 229 230 /* 231 * Some PCI serial cards using the PLX 9050 PCI interface chip require 232 * that the card interrupt be explicitly enabled or disabled. This 233 * seems to be mainly needed on card using the PLX which also use I/O 234 * mapped memory. 235 */ 236 static int pci_plx9050_init(struct pci_dev *dev) 237 { 238 u8 irq_config; 239 void __iomem *p; 240 241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 242 moan_device("no memory in bar 0", dev); 243 return 0; 244 } 245 246 irq_config = 0x41; 247 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 249 irq_config = 0x43; 250 251 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 253 /* 254 * As the megawolf cards have the int pins active 255 * high, and have 2 UART chips, both ints must be 256 * enabled on the 9050. Also, the UARTS are set in 257 * 16450 mode by default, so we have to enable the 258 * 16C950 'enhanced' mode so that we can use the 259 * deep FIFOs 260 */ 261 irq_config = 0x5b; 262 /* 263 * enable/disable interrupts 264 */ 265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 266 if (p == NULL) 267 return -ENOMEM; 268 writel(irq_config, p + 0x4c); 269 270 /* 271 * Read the register back to ensure that it took effect. 272 */ 273 readl(p + 0x4c); 274 iounmap(p); 275 276 return 0; 277 } 278 279 static void pci_plx9050_exit(struct pci_dev *dev) 280 { 281 u8 __iomem *p; 282 283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 284 return; 285 286 /* 287 * disable interrupts 288 */ 289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 290 if (p != NULL) { 291 writel(0, p + 0x4c); 292 293 /* 294 * Read the register back to ensure that it took effect. 295 */ 296 readl(p + 0x4c); 297 iounmap(p); 298 } 299 } 300 301 #define NI8420_INT_ENABLE_REG 0x38 302 #define NI8420_INT_ENABLE_BIT 0x2000 303 304 static void pci_ni8420_exit(struct pci_dev *dev) 305 { 306 void __iomem *p; 307 unsigned int bar = 0; 308 309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 310 moan_device("no memory in bar", dev); 311 return; 312 } 313 314 p = pci_ioremap_bar(dev, bar); 315 if (p == NULL) 316 return; 317 318 /* Disable the CPU Interrupt */ 319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 320 p + NI8420_INT_ENABLE_REG); 321 iounmap(p); 322 } 323 324 325 /* MITE registers */ 326 #define MITE_IOWBSR1 0xc4 327 #define MITE_IOWCR1 0xf4 328 #define MITE_LCIMR1 0x08 329 #define MITE_LCIMR2 0x10 330 331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 332 333 static void pci_ni8430_exit(struct pci_dev *dev) 334 { 335 void __iomem *p; 336 unsigned int bar = 0; 337 338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 339 moan_device("no memory in bar", dev); 340 return; 341 } 342 343 p = pci_ioremap_bar(dev, bar); 344 if (p == NULL) 345 return; 346 347 /* Disable the CPU Interrupt */ 348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 349 iounmap(p); 350 } 351 352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 353 static int 354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 355 struct uart_8250_port *port, int idx) 356 { 357 unsigned int bar, offset = board->first_offset; 358 359 bar = 0; 360 361 if (idx < 4) { 362 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 363 offset += idx * board->uart_offset; 364 } else if (idx < 8) { 365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 366 offset += idx * board->uart_offset + 0xC00; 367 } else /* we have only 8 ports on PMC-OCTALPRO */ 368 return 1; 369 370 return setup_port(priv, port, bar, offset, board->reg_shift); 371 } 372 373 /* 374 * This does initialization for PMC OCTALPRO cards: 375 * maps the device memory, resets the UARTs (needed, bc 376 * if the module is removed and inserted again, the card 377 * is in the sleep mode) and enables global interrupt. 378 */ 379 380 /* global control register offset for SBS PMC-OctalPro */ 381 #define OCT_REG_CR_OFF 0x500 382 383 static int sbs_init(struct pci_dev *dev) 384 { 385 u8 __iomem *p; 386 387 p = pci_ioremap_bar(dev, 0); 388 389 if (p == NULL) 390 return -ENOMEM; 391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 392 writeb(0x10, p + OCT_REG_CR_OFF); 393 udelay(50); 394 writeb(0x0, p + OCT_REG_CR_OFF); 395 396 /* Set bit-2 (INTENABLE) of Control Register */ 397 writeb(0x4, p + OCT_REG_CR_OFF); 398 iounmap(p); 399 400 return 0; 401 } 402 403 /* 404 * Disables the global interrupt of PMC-OctalPro 405 */ 406 407 static void sbs_exit(struct pci_dev *dev) 408 { 409 u8 __iomem *p; 410 411 p = pci_ioremap_bar(dev, 0); 412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 413 if (p != NULL) 414 writeb(0, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 } 417 418 /* 419 * SIIG serial cards have an PCI interface chip which also controls 420 * the UART clocking frequency. Each UART can be clocked independently 421 * (except cards equipped with 4 UARTs) and initial clocking settings 422 * are stored in the EEPROM chip. It can cause problems because this 423 * version of serial driver doesn't support differently clocked UART's 424 * on single PCI card. To prevent this, initialization functions set 425 * high frequency clocking for all UART's on given card. It is safe (I 426 * hope) because it doesn't touch EEPROM settings to prevent conflicts 427 * with other OSes (like M$ DOS). 428 * 429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 430 * 431 * There is two family of SIIG serial cards with different PCI 432 * interface chip and different configuration methods: 433 * - 10x cards have control registers in IO and/or memory space; 434 * - 20x cards have control registers in standard PCI configuration space. 435 * 436 * Note: all 10x cards have PCI device ids 0x10.. 437 * all 20x cards have PCI device ids 0x20.. 438 * 439 * There are also Quartet Serial cards which use Oxford Semiconductor 440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 441 * 442 * Note: some SIIG cards are probed by the parport_serial object. 443 */ 444 445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 447 448 static int pci_siig10x_init(struct pci_dev *dev) 449 { 450 u16 data; 451 void __iomem *p; 452 453 switch (dev->device & 0xfff8) { 454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 455 data = 0xffdf; 456 break; 457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 458 data = 0xf7ff; 459 break; 460 default: /* 1S1P, 4S */ 461 data = 0xfffb; 462 break; 463 } 464 465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 466 if (p == NULL) 467 return -ENOMEM; 468 469 writew(readw(p + 0x28) & data, p + 0x28); 470 readw(p + 0x28); 471 iounmap(p); 472 return 0; 473 } 474 475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 477 478 static int pci_siig20x_init(struct pci_dev *dev) 479 { 480 u8 data; 481 482 /* Change clock frequency for the first UART. */ 483 pci_read_config_byte(dev, 0x6f, &data); 484 pci_write_config_byte(dev, 0x6f, data & 0xef); 485 486 /* If this card has 2 UART, we have to do the same with second UART. */ 487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 489 pci_read_config_byte(dev, 0x73, &data); 490 pci_write_config_byte(dev, 0x73, data & 0xef); 491 } 492 return 0; 493 } 494 495 static int pci_siig_init(struct pci_dev *dev) 496 { 497 unsigned int type = dev->device & 0xff00; 498 499 if (type == 0x1000) 500 return pci_siig10x_init(dev); 501 else if (type == 0x2000) 502 return pci_siig20x_init(dev); 503 504 moan_device("Unknown SIIG card", dev); 505 return -ENODEV; 506 } 507 508 static int pci_siig_setup(struct serial_private *priv, 509 const struct pciserial_board *board, 510 struct uart_8250_port *port, int idx) 511 { 512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 513 514 if (idx > 3) { 515 bar = 4; 516 offset = (idx - 4) * 8; 517 } 518 519 return setup_port(priv, port, bar, offset, 0); 520 } 521 522 /* 523 * Timedia has an explosion of boards, and to avoid the PCI table from 524 * growing *huge*, we use this function to collapse some 70 entries 525 * in the PCI table into one, for sanity's and compactness's sake. 526 */ 527 static const unsigned short timedia_single_port[] = { 528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 529 }; 530 531 static const unsigned short timedia_dual_port[] = { 532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 536 0xD079, 0 537 }; 538 539 static const unsigned short timedia_quad_port[] = { 540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 543 0xB157, 0 544 }; 545 546 static const unsigned short timedia_eight_port[] = { 547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 549 }; 550 551 static const struct timedia_struct { 552 int num; 553 const unsigned short *ids; 554 } timedia_data[] = { 555 { 1, timedia_single_port }, 556 { 2, timedia_dual_port }, 557 { 4, timedia_quad_port }, 558 { 8, timedia_eight_port } 559 }; 560 561 /* 562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 563 * listing them individually, this driver merely grabs them all with 564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 565 * and should be left free to be claimed by parport_serial instead. 566 */ 567 static int pci_timedia_probe(struct pci_dev *dev) 568 { 569 /* 570 * Check the third digit of the subdevice ID 571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 572 */ 573 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 574 dev_info(&dev->dev, 575 "ignoring Timedia subdevice %04x for parport_serial\n", 576 dev->subsystem_device); 577 return -ENODEV; 578 } 579 580 return 0; 581 } 582 583 static int pci_timedia_init(struct pci_dev *dev) 584 { 585 const unsigned short *ids; 586 int i, j; 587 588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 589 ids = timedia_data[i].ids; 590 for (j = 0; ids[j]; j++) 591 if (dev->subsystem_device == ids[j]) 592 return timedia_data[i].num; 593 } 594 return 0; 595 } 596 597 /* 598 * Timedia/SUNIX uses a mixture of BARs and offsets 599 * Ugh, this is ugly as all hell --- TYT 600 */ 601 static int 602 pci_timedia_setup(struct serial_private *priv, 603 const struct pciserial_board *board, 604 struct uart_8250_port *port, int idx) 605 { 606 unsigned int bar = 0, offset = board->first_offset; 607 608 switch (idx) { 609 case 0: 610 bar = 0; 611 break; 612 case 1: 613 offset = board->uart_offset; 614 bar = 0; 615 break; 616 case 2: 617 bar = 1; 618 break; 619 case 3: 620 offset = board->uart_offset; 621 /* FALLTHROUGH */ 622 case 4: /* BAR 2 */ 623 case 5: /* BAR 3 */ 624 case 6: /* BAR 4 */ 625 case 7: /* BAR 5 */ 626 bar = idx - 2; 627 } 628 629 return setup_port(priv, port, bar, offset, board->reg_shift); 630 } 631 632 /* 633 * Some Titan cards are also a little weird 634 */ 635 static int 636 titan_400l_800l_setup(struct serial_private *priv, 637 const struct pciserial_board *board, 638 struct uart_8250_port *port, int idx) 639 { 640 unsigned int bar, offset = board->first_offset; 641 642 switch (idx) { 643 case 0: 644 bar = 1; 645 break; 646 case 1: 647 bar = 2; 648 break; 649 default: 650 bar = 4; 651 offset = (idx - 2) * board->uart_offset; 652 } 653 654 return setup_port(priv, port, bar, offset, board->reg_shift); 655 } 656 657 static int pci_xircom_init(struct pci_dev *dev) 658 { 659 msleep(100); 660 return 0; 661 } 662 663 static int pci_ni8420_init(struct pci_dev *dev) 664 { 665 void __iomem *p; 666 unsigned int bar = 0; 667 668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 669 moan_device("no memory in bar", dev); 670 return 0; 671 } 672 673 p = pci_ioremap_bar(dev, bar); 674 if (p == NULL) 675 return -ENOMEM; 676 677 /* Enable CPU Interrupt */ 678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 679 p + NI8420_INT_ENABLE_REG); 680 681 iounmap(p); 682 return 0; 683 } 684 685 #define MITE_IOWBSR1_WSIZE 0xa 686 #define MITE_IOWBSR1_WIN_OFFSET 0x800 687 #define MITE_IOWBSR1_WENAB (1 << 7) 688 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 691 692 static int pci_ni8430_init(struct pci_dev *dev) 693 { 694 void __iomem *p; 695 struct pci_bus_region region; 696 u32 device_window; 697 unsigned int bar = 0; 698 699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 700 moan_device("no memory in bar", dev); 701 return 0; 702 } 703 704 p = pci_ioremap_bar(dev, bar); 705 if (p == NULL) 706 return -ENOMEM; 707 708 /* 709 * Set device window address and size in BAR0, while acknowledging that 710 * the resource structure may contain a translated address that differs 711 * from the address the device responds to. 712 */ 713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 716 writel(device_window, p + MITE_IOWBSR1); 717 718 /* Set window access to go to RAMSEL IO address space */ 719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 720 p + MITE_IOWCR1); 721 722 /* Enable IO Bus Interrupt 0 */ 723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 724 725 /* Enable CPU Interrupt */ 726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 727 728 iounmap(p); 729 return 0; 730 } 731 732 /* UART Port Control Register */ 733 #define NI8430_PORTCON 0x0f 734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 735 736 static int 737 pci_ni8430_setup(struct serial_private *priv, 738 const struct pciserial_board *board, 739 struct uart_8250_port *port, int idx) 740 { 741 struct pci_dev *dev = priv->dev; 742 void __iomem *p; 743 unsigned int bar, offset = board->first_offset; 744 745 if (idx >= board->num_ports) 746 return 1; 747 748 bar = FL_GET_BASE(board->flags); 749 offset += idx * board->uart_offset; 750 751 p = pci_ioremap_bar(dev, bar); 752 if (!p) 753 return -ENOMEM; 754 755 /* enable the transceiver */ 756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 757 p + offset + NI8430_PORTCON); 758 759 iounmap(p); 760 761 return setup_port(priv, port, bar, offset, board->reg_shift); 762 } 763 764 static int pci_netmos_9900_setup(struct serial_private *priv, 765 const struct pciserial_board *board, 766 struct uart_8250_port *port, int idx) 767 { 768 unsigned int bar; 769 770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 771 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 772 /* netmos apparently orders BARs by datasheet layout, so serial 773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 774 */ 775 bar = 3 * idx; 776 777 return setup_port(priv, port, bar, 0, board->reg_shift); 778 } else { 779 return pci_default_setup(priv, board, port, idx); 780 } 781 } 782 783 /* the 99xx series comes with a range of device IDs and a variety 784 * of capabilities: 785 * 786 * 9900 has varying capabilities and can cascade to sub-controllers 787 * (cascading should be purely internal) 788 * 9904 is hardwired with 4 serial ports 789 * 9912 and 9922 are hardwired with 2 serial ports 790 */ 791 static int pci_netmos_9900_numports(struct pci_dev *dev) 792 { 793 unsigned int c = dev->class; 794 unsigned int pi; 795 unsigned short sub_serports; 796 797 pi = c & 0xff; 798 799 if (pi == 2) 800 return 1; 801 802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 803 /* two possibilities: 0x30ps encodes number of parallel and 804 * serial ports, or 0x1000 indicates *something*. This is not 805 * immediately obvious, since the 2s1p+4s configuration seems 806 * to offer all functionality on functions 0..2, while still 807 * advertising the same function 3 as the 4s+2s1p config. 808 */ 809 sub_serports = dev->subsystem_device & 0xf; 810 if (sub_serports > 0) 811 return sub_serports; 812 813 dev_err(&dev->dev, 814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 815 return 0; 816 } 817 818 moan_device("unknown NetMos/Mostech program interface", dev); 819 return 0; 820 } 821 822 static int pci_netmos_init(struct pci_dev *dev) 823 { 824 /* subdevice 0x00PS means <P> parallel, <S> serial */ 825 unsigned int num_serial = dev->subsystem_device & 0xf; 826 827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 828 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 829 return 0; 830 831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 832 dev->subsystem_device == 0x0299) 833 return 0; 834 835 switch (dev->device) { /* FALLTHROUGH on all */ 836 case PCI_DEVICE_ID_NETMOS_9904: 837 case PCI_DEVICE_ID_NETMOS_9912: 838 case PCI_DEVICE_ID_NETMOS_9922: 839 case PCI_DEVICE_ID_NETMOS_9900: 840 num_serial = pci_netmos_9900_numports(dev); 841 break; 842 843 default: 844 break; 845 } 846 847 if (num_serial == 0) { 848 moan_device("unknown NetMos/Mostech device", dev); 849 return -ENODEV; 850 } 851 852 return num_serial; 853 } 854 855 /* 856 * These chips are available with optionally one parallel port and up to 857 * two serial ports. Unfortunately they all have the same product id. 858 * 859 * Basic configuration is done over a region of 32 I/O ports. The base 860 * ioport is called INTA or INTC, depending on docs/other drivers. 861 * 862 * The region of the 32 I/O ports is configured in POSIO0R... 863 */ 864 865 /* registers */ 866 #define ITE_887x_MISCR 0x9c 867 #define ITE_887x_INTCBAR 0x78 868 #define ITE_887x_UARTBAR 0x7c 869 #define ITE_887x_PS0BAR 0x10 870 #define ITE_887x_POSIO0 0x60 871 872 /* I/O space size */ 873 #define ITE_887x_IOSIZE 32 874 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 876 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 879 #define ITE_887x_POSIO_SPEED (3 << 29) 880 /* enable IO_Space bit */ 881 #define ITE_887x_POSIO_ENABLE (1 << 31) 882 883 static int pci_ite887x_init(struct pci_dev *dev) 884 { 885 /* inta_addr are the configuration addresses of the ITE */ 886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 887 0x200, 0x280, 0 }; 888 int ret, i, type; 889 struct resource *iobase = NULL; 890 u32 miscr, uartbar, ioport; 891 892 /* search for the base-ioport */ 893 i = 0; 894 while (inta_addr[i] && iobase == NULL) { 895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 896 "ite887x"); 897 if (iobase != NULL) { 898 /* write POSIO0R - speed | size | ioport */ 899 pci_write_config_dword(dev, ITE_887x_POSIO0, 900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 902 /* write INTCBAR - ioport */ 903 pci_write_config_dword(dev, ITE_887x_INTCBAR, 904 inta_addr[i]); 905 ret = inb(inta_addr[i]); 906 if (ret != 0xff) { 907 /* ioport connected */ 908 break; 909 } 910 release_region(iobase->start, ITE_887x_IOSIZE); 911 iobase = NULL; 912 } 913 i++; 914 } 915 916 if (!inta_addr[i]) { 917 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 918 return -ENODEV; 919 } 920 921 /* start of undocumented type checking (see parport_pc.c) */ 922 type = inb(iobase->start + 0x18) & 0x0f; 923 924 switch (type) { 925 case 0x2: /* ITE8871 (1P) */ 926 case 0xa: /* ITE8875 (1P) */ 927 ret = 0; 928 break; 929 case 0xe: /* ITE8872 (2S1P) */ 930 ret = 2; 931 break; 932 case 0x6: /* ITE8873 (1S) */ 933 ret = 1; 934 break; 935 case 0x8: /* ITE8874 (2S) */ 936 ret = 2; 937 break; 938 default: 939 moan_device("Unknown ITE887x", dev); 940 ret = -ENODEV; 941 } 942 943 /* configure all serial ports */ 944 for (i = 0; i < ret; i++) { 945 /* read the I/O port from the device */ 946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 947 &ioport); 948 ioport &= 0x0000FF00; /* the actual base address */ 949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 951 ITE_887x_POSIO_IOSIZE_8 | ioport); 952 953 /* write the ioport to the UARTBAR */ 954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 956 uartbar |= (ioport << (16 * i)); /* set the ioport */ 957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 958 959 /* get current config */ 960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 961 /* disable interrupts (UARTx_Routing[3:0]) */ 962 miscr &= ~(0xf << (12 - 4 * i)); 963 /* activate the UART (UARTx_En) */ 964 miscr |= 1 << (23 - i); 965 /* write new config with activated UART */ 966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 967 } 968 969 if (ret <= 0) { 970 /* the device has no UARTs if we get here */ 971 release_region(iobase->start, ITE_887x_IOSIZE); 972 } 973 974 return ret; 975 } 976 977 static void pci_ite887x_exit(struct pci_dev *dev) 978 { 979 u32 ioport; 980 /* the ioport is bit 0-15 in POSIO0R */ 981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 982 ioport &= 0xffff; 983 release_region(ioport, ITE_887x_IOSIZE); 984 } 985 986 /* 987 * EndRun Technologies. 988 * Determine the number of ports available on the device. 989 */ 990 #define PCI_VENDOR_ID_ENDRUN 0x7401 991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 992 993 static int pci_endrun_init(struct pci_dev *dev) 994 { 995 u8 __iomem *p; 996 unsigned long deviceID; 997 unsigned int number_uarts = 0; 998 999 /* EndRun device is all 0xexxx */ 1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1001 (dev->device & 0xf000) != 0xe000) 1002 return 0; 1003 1004 p = pci_iomap(dev, 0, 5); 1005 if (p == NULL) 1006 return -ENOMEM; 1007 1008 deviceID = ioread32(p); 1009 /* EndRun device */ 1010 if (deviceID == 0x07000200) { 1011 number_uarts = ioread8(p + 4); 1012 dev_dbg(&dev->dev, 1013 "%d ports detected on EndRun PCI Express device\n", 1014 number_uarts); 1015 } 1016 pci_iounmap(dev, p); 1017 return number_uarts; 1018 } 1019 1020 /* 1021 * Oxford Semiconductor Inc. 1022 * Check that device is part of the Tornado range of devices, then determine 1023 * the number of ports available on the device. 1024 */ 1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1026 { 1027 u8 __iomem *p; 1028 unsigned long deviceID; 1029 unsigned int number_uarts = 0; 1030 1031 /* OxSemi Tornado devices are all 0xCxxx */ 1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1033 (dev->device & 0xF000) != 0xC000) 1034 return 0; 1035 1036 p = pci_iomap(dev, 0, 5); 1037 if (p == NULL) 1038 return -ENOMEM; 1039 1040 deviceID = ioread32(p); 1041 /* Tornado device */ 1042 if (deviceID == 0x07000200) { 1043 number_uarts = ioread8(p + 4); 1044 dev_dbg(&dev->dev, 1045 "%d ports detected on Oxford PCI Express device\n", 1046 number_uarts); 1047 } 1048 pci_iounmap(dev, p); 1049 return number_uarts; 1050 } 1051 1052 static int pci_asix_setup(struct serial_private *priv, 1053 const struct pciserial_board *board, 1054 struct uart_8250_port *port, int idx) 1055 { 1056 port->bugs |= UART_BUG_PARITY; 1057 return pci_default_setup(priv, board, port, idx); 1058 } 1059 1060 /* Quatech devices have their own extra interface features */ 1061 1062 struct quatech_feature { 1063 u16 devid; 1064 bool amcc; 1065 }; 1066 1067 #define QPCR_TEST_FOR1 0x3F 1068 #define QPCR_TEST_GET1 0x00 1069 #define QPCR_TEST_FOR2 0x40 1070 #define QPCR_TEST_GET2 0x40 1071 #define QPCR_TEST_FOR3 0x80 1072 #define QPCR_TEST_GET3 0x40 1073 #define QPCR_TEST_FOR4 0xC0 1074 #define QPCR_TEST_GET4 0x80 1075 1076 #define QOPR_CLOCK_X1 0x0000 1077 #define QOPR_CLOCK_X2 0x0001 1078 #define QOPR_CLOCK_X4 0x0002 1079 #define QOPR_CLOCK_X8 0x0003 1080 #define QOPR_CLOCK_RATE_MASK 0x0003 1081 1082 1083 static struct quatech_feature quatech_cards[] = { 1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1103 { 0, } 1104 }; 1105 1106 static int pci_quatech_amcc(u16 devid) 1107 { 1108 struct quatech_feature *qf = &quatech_cards[0]; 1109 while (qf->devid) { 1110 if (qf->devid == devid) 1111 return qf->amcc; 1112 qf++; 1113 } 1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1115 return 0; 1116 }; 1117 1118 static int pci_quatech_rqopr(struct uart_8250_port *port) 1119 { 1120 unsigned long base = port->port.iobase; 1121 u8 LCR, val; 1122 1123 LCR = inb(base + UART_LCR); 1124 outb(0xBF, base + UART_LCR); 1125 val = inb(base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127 return val; 1128 } 1129 1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1131 { 1132 unsigned long base = port->port.iobase; 1133 u8 LCR; 1134 1135 LCR = inb(base + UART_LCR); 1136 outb(0xBF, base + UART_LCR); 1137 inb(base + UART_SCR); 1138 outb(qopr, base + UART_SCR); 1139 outb(LCR, base + UART_LCR); 1140 } 1141 1142 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1143 { 1144 unsigned long base = port->port.iobase; 1145 u8 LCR, val, qmcr; 1146 1147 LCR = inb(base + UART_LCR); 1148 outb(0xBF, base + UART_LCR); 1149 val = inb(base + UART_SCR); 1150 outb(val | 0x10, base + UART_SCR); 1151 qmcr = inb(base + UART_MCR); 1152 outb(val, base + UART_SCR); 1153 outb(LCR, base + UART_LCR); 1154 1155 return qmcr; 1156 } 1157 1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1159 { 1160 unsigned long base = port->port.iobase; 1161 u8 LCR, val; 1162 1163 LCR = inb(base + UART_LCR); 1164 outb(0xBF, base + UART_LCR); 1165 val = inb(base + UART_SCR); 1166 outb(val | 0x10, base + UART_SCR); 1167 outb(qmcr, base + UART_MCR); 1168 outb(val, base + UART_SCR); 1169 outb(LCR, base + UART_LCR); 1170 } 1171 1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1173 { 1174 unsigned long base = port->port.iobase; 1175 u8 LCR, val; 1176 1177 LCR = inb(base + UART_LCR); 1178 outb(0xBF, base + UART_LCR); 1179 val = inb(base + UART_SCR); 1180 if (val & 0x20) { 1181 outb(0x80, UART_LCR); 1182 if (!(inb(UART_SCR) & 0x20)) { 1183 outb(LCR, base + UART_LCR); 1184 return 1; 1185 } 1186 } 1187 return 0; 1188 } 1189 1190 static int pci_quatech_test(struct uart_8250_port *port) 1191 { 1192 u8 reg, qopr; 1193 1194 qopr = pci_quatech_rqopr(port); 1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1196 reg = pci_quatech_rqopr(port) & 0xC0; 1197 if (reg != QPCR_TEST_GET1) 1198 return -EINVAL; 1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1200 reg = pci_quatech_rqopr(port) & 0xC0; 1201 if (reg != QPCR_TEST_GET2) 1202 return -EINVAL; 1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1204 reg = pci_quatech_rqopr(port) & 0xC0; 1205 if (reg != QPCR_TEST_GET3) 1206 return -EINVAL; 1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1208 reg = pci_quatech_rqopr(port) & 0xC0; 1209 if (reg != QPCR_TEST_GET4) 1210 return -EINVAL; 1211 1212 pci_quatech_wqopr(port, qopr); 1213 return 0; 1214 } 1215 1216 static int pci_quatech_clock(struct uart_8250_port *port) 1217 { 1218 u8 qopr, reg, set; 1219 unsigned long clock; 1220 1221 if (pci_quatech_test(port) < 0) 1222 return 1843200; 1223 1224 qopr = pci_quatech_rqopr(port); 1225 1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1227 reg = pci_quatech_rqopr(port); 1228 if (reg & QOPR_CLOCK_X8) { 1229 clock = 1843200; 1230 goto out; 1231 } 1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1233 reg = pci_quatech_rqopr(port); 1234 if (!(reg & QOPR_CLOCK_X8)) { 1235 clock = 1843200; 1236 goto out; 1237 } 1238 reg &= QOPR_CLOCK_X8; 1239 if (reg == QOPR_CLOCK_X2) { 1240 clock = 3685400; 1241 set = QOPR_CLOCK_X2; 1242 } else if (reg == QOPR_CLOCK_X4) { 1243 clock = 7372800; 1244 set = QOPR_CLOCK_X4; 1245 } else if (reg == QOPR_CLOCK_X8) { 1246 clock = 14745600; 1247 set = QOPR_CLOCK_X8; 1248 } else { 1249 clock = 1843200; 1250 set = QOPR_CLOCK_X1; 1251 } 1252 qopr &= ~QOPR_CLOCK_RATE_MASK; 1253 qopr |= set; 1254 1255 out: 1256 pci_quatech_wqopr(port, qopr); 1257 return clock; 1258 } 1259 1260 static int pci_quatech_rs422(struct uart_8250_port *port) 1261 { 1262 u8 qmcr; 1263 int rs422 = 0; 1264 1265 if (!pci_quatech_has_qmcr(port)) 1266 return 0; 1267 qmcr = pci_quatech_rqmcr(port); 1268 pci_quatech_wqmcr(port, 0xFF); 1269 if (pci_quatech_rqmcr(port)) 1270 rs422 = 1; 1271 pci_quatech_wqmcr(port, qmcr); 1272 return rs422; 1273 } 1274 1275 static int pci_quatech_init(struct pci_dev *dev) 1276 { 1277 if (pci_quatech_amcc(dev->device)) { 1278 unsigned long base = pci_resource_start(dev, 0); 1279 if (base) { 1280 u32 tmp; 1281 1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1283 tmp = inl(base + 0x3c); 1284 outl(tmp | 0x01000000, base + 0x3c); 1285 outl(tmp &= ~0x01000000, base + 0x3c); 1286 } 1287 } 1288 return 0; 1289 } 1290 1291 static int pci_quatech_setup(struct serial_private *priv, 1292 const struct pciserial_board *board, 1293 struct uart_8250_port *port, int idx) 1294 { 1295 /* Needed by pci_quatech calls below */ 1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1297 /* Set up the clocking */ 1298 port->port.uartclk = pci_quatech_clock(port); 1299 /* For now just warn about RS422 */ 1300 if (pci_quatech_rs422(port)) 1301 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1302 return pci_default_setup(priv, board, port, idx); 1303 } 1304 1305 static void pci_quatech_exit(struct pci_dev *dev) 1306 { 1307 } 1308 1309 static int pci_default_setup(struct serial_private *priv, 1310 const struct pciserial_board *board, 1311 struct uart_8250_port *port, int idx) 1312 { 1313 unsigned int bar, offset = board->first_offset, maxnr; 1314 1315 bar = FL_GET_BASE(board->flags); 1316 if (board->flags & FL_BASE_BARS) 1317 bar += idx; 1318 else 1319 offset += idx * board->uart_offset; 1320 1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1322 (board->reg_shift + 3); 1323 1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1325 return 1; 1326 1327 return setup_port(priv, port, bar, offset, board->reg_shift); 1328 } 1329 static void 1330 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1331 unsigned int quot, unsigned int quot_frac) 1332 { 1333 int scr; 1334 int lcr; 1335 int actual_baud; 1336 int tolerance; 1337 1338 for (scr = 5 ; scr <= 15 ; scr++) { 1339 actual_baud = 921600 * 16 / scr; 1340 tolerance = actual_baud / 50; 1341 1342 if ((baud < actual_baud + tolerance) && 1343 (baud > actual_baud - tolerance)) { 1344 1345 lcr = serial_port_in(port, UART_LCR); 1346 serial_port_out(port, UART_LCR, lcr | 0x80); 1347 1348 serial_port_out(port, UART_DLL, 1); 1349 serial_port_out(port, UART_DLM, 0); 1350 serial_port_out(port, 2, 16 - scr); 1351 serial_port_out(port, UART_LCR, lcr); 1352 return; 1353 } else if (baud > actual_baud) { 1354 break; 1355 } 1356 } 1357 serial8250_do_set_divisor(port, baud, quot, quot_frac); 1358 } 1359 static int pci_pericom_setup(struct serial_private *priv, 1360 const struct pciserial_board *board, 1361 struct uart_8250_port *port, int idx) 1362 { 1363 unsigned int bar, offset = board->first_offset, maxnr; 1364 1365 bar = FL_GET_BASE(board->flags); 1366 if (board->flags & FL_BASE_BARS) 1367 bar += idx; 1368 else 1369 offset += idx * board->uart_offset; 1370 1371 1372 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1373 (board->reg_shift + 3); 1374 1375 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1376 return 1; 1377 1378 port->port.set_divisor = pericom_do_set_divisor; 1379 1380 return setup_port(priv, port, bar, offset, board->reg_shift); 1381 } 1382 1383 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1384 const struct pciserial_board *board, 1385 struct uart_8250_port *port, int idx) 1386 { 1387 unsigned int bar, offset = board->first_offset, maxnr; 1388 1389 bar = FL_GET_BASE(board->flags); 1390 if (board->flags & FL_BASE_BARS) 1391 bar += idx; 1392 else 1393 offset += idx * board->uart_offset; 1394 1395 if (idx==3) 1396 offset = 0x38; 1397 1398 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1399 (board->reg_shift + 3); 1400 1401 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1402 return 1; 1403 1404 port->port.set_divisor = pericom_do_set_divisor; 1405 1406 return setup_port(priv, port, bar, offset, board->reg_shift); 1407 } 1408 1409 static int 1410 ce4100_serial_setup(struct serial_private *priv, 1411 const struct pciserial_board *board, 1412 struct uart_8250_port *port, int idx) 1413 { 1414 int ret; 1415 1416 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1417 port->port.iotype = UPIO_MEM32; 1418 port->port.type = PORT_XSCALE; 1419 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1420 port->port.regshift = 2; 1421 1422 return ret; 1423 } 1424 1425 static int 1426 pci_omegapci_setup(struct serial_private *priv, 1427 const struct pciserial_board *board, 1428 struct uart_8250_port *port, int idx) 1429 { 1430 return setup_port(priv, port, 2, idx * 8, 0); 1431 } 1432 1433 static int 1434 pci_brcm_trumanage_setup(struct serial_private *priv, 1435 const struct pciserial_board *board, 1436 struct uart_8250_port *port, int idx) 1437 { 1438 int ret = pci_default_setup(priv, board, port, idx); 1439 1440 port->port.type = PORT_BRCM_TRUMANAGE; 1441 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1442 return ret; 1443 } 1444 1445 /* RTS will control by MCR if this bit is 0 */ 1446 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1447 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1448 #define FINTEK_RTS_INVERT BIT(5) 1449 1450 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1451 static int pci_fintek_rs485_config(struct uart_port *port, 1452 struct serial_rs485 *rs485) 1453 { 1454 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1455 u8 setting; 1456 u8 *index = (u8 *) port->private_data; 1457 1458 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1459 1460 if (!rs485) 1461 rs485 = &port->rs485; 1462 else if (rs485->flags & SER_RS485_ENABLED) 1463 memset(rs485->padding, 0, sizeof(rs485->padding)); 1464 else 1465 memset(rs485, 0, sizeof(*rs485)); 1466 1467 /* F81504/508/512 not support RTS delay before or after send */ 1468 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1469 1470 if (rs485->flags & SER_RS485_ENABLED) { 1471 /* Enable RTS H/W control mode */ 1472 setting |= FINTEK_RTS_CONTROL_BY_HW; 1473 1474 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1475 /* RTS driving high on TX */ 1476 setting &= ~FINTEK_RTS_INVERT; 1477 } else { 1478 /* RTS driving low on TX */ 1479 setting |= FINTEK_RTS_INVERT; 1480 } 1481 1482 rs485->delay_rts_after_send = 0; 1483 rs485->delay_rts_before_send = 0; 1484 } else { 1485 /* Disable RTS H/W control mode */ 1486 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1487 } 1488 1489 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1490 1491 if (rs485 != &port->rs485) 1492 port->rs485 = *rs485; 1493 1494 return 0; 1495 } 1496 1497 static int pci_fintek_setup(struct serial_private *priv, 1498 const struct pciserial_board *board, 1499 struct uart_8250_port *port, int idx) 1500 { 1501 struct pci_dev *pdev = priv->dev; 1502 u8 *data; 1503 u8 config_base; 1504 u16 iobase; 1505 1506 config_base = 0x40 + 0x08 * idx; 1507 1508 /* Get the io address from configuration space */ 1509 pci_read_config_word(pdev, config_base + 4, &iobase); 1510 1511 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1512 1513 port->port.iotype = UPIO_PORT; 1514 port->port.iobase = iobase; 1515 port->port.rs485_config = pci_fintek_rs485_config; 1516 1517 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1518 if (!data) 1519 return -ENOMEM; 1520 1521 /* preserve index in PCI configuration space */ 1522 *data = idx; 1523 port->port.private_data = data; 1524 1525 return 0; 1526 } 1527 1528 static int pci_fintek_init(struct pci_dev *dev) 1529 { 1530 unsigned long iobase; 1531 u32 max_port, i; 1532 resource_size_t bar_data[3]; 1533 u8 config_base; 1534 struct serial_private *priv = pci_get_drvdata(dev); 1535 struct uart_8250_port *port; 1536 1537 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1538 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1539 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1540 return -ENODEV; 1541 1542 switch (dev->device) { 1543 case 0x1104: /* 4 ports */ 1544 case 0x1108: /* 8 ports */ 1545 max_port = dev->device & 0xff; 1546 break; 1547 case 0x1112: /* 12 ports */ 1548 max_port = 12; 1549 break; 1550 default: 1551 return -EINVAL; 1552 } 1553 1554 /* Get the io address dispatch from the BIOS */ 1555 bar_data[0] = pci_resource_start(dev, 5); 1556 bar_data[1] = pci_resource_start(dev, 4); 1557 bar_data[2] = pci_resource_start(dev, 3); 1558 1559 for (i = 0; i < max_port; ++i) { 1560 /* UART0 configuration offset start from 0x40 */ 1561 config_base = 0x40 + 0x08 * i; 1562 1563 /* Calculate Real IO Port */ 1564 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1565 1566 /* Enable UART I/O port */ 1567 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1568 1569 /* Select 128-byte FIFO and 8x FIFO threshold */ 1570 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1571 1572 /* LSB UART */ 1573 pci_write_config_byte(dev, config_base + 0x04, 1574 (u8)(iobase & 0xff)); 1575 1576 /* MSB UART */ 1577 pci_write_config_byte(dev, config_base + 0x05, 1578 (u8)((iobase & 0xff00) >> 8)); 1579 1580 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1581 1582 if (priv) { 1583 /* re-apply RS232/485 mode when 1584 * pciserial_resume_ports() 1585 */ 1586 port = serial8250_get_port(priv->line[i]); 1587 pci_fintek_rs485_config(&port->port, NULL); 1588 } else { 1589 /* First init without port data 1590 * force init to RS232 Mode 1591 */ 1592 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1593 } 1594 } 1595 1596 return max_port; 1597 } 1598 1599 static int skip_tx_en_setup(struct serial_private *priv, 1600 const struct pciserial_board *board, 1601 struct uart_8250_port *port, int idx) 1602 { 1603 port->port.quirks |= UPQ_NO_TXEN_TEST; 1604 dev_dbg(&priv->dev->dev, 1605 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1606 priv->dev->vendor, priv->dev->device, 1607 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1608 1609 return pci_default_setup(priv, board, port, idx); 1610 } 1611 1612 static void kt_handle_break(struct uart_port *p) 1613 { 1614 struct uart_8250_port *up = up_to_u8250p(p); 1615 /* 1616 * On receipt of a BI, serial device in Intel ME (Intel 1617 * management engine) needs to have its fifos cleared for sane 1618 * SOL (Serial Over Lan) output. 1619 */ 1620 serial8250_clear_and_reinit_fifos(up); 1621 } 1622 1623 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1624 { 1625 struct uart_8250_port *up = up_to_u8250p(p); 1626 unsigned int val; 1627 1628 /* 1629 * When the Intel ME (management engine) gets reset its serial 1630 * port registers could return 0 momentarily. Functions like 1631 * serial8250_console_write, read and save the IER, perform 1632 * some operation and then restore it. In order to avoid 1633 * setting IER register inadvertently to 0, if the value read 1634 * is 0, double check with ier value in uart_8250_port and use 1635 * that instead. up->ier should be the same value as what is 1636 * currently configured. 1637 */ 1638 val = inb(p->iobase + offset); 1639 if (offset == UART_IER) { 1640 if (val == 0) 1641 val = up->ier; 1642 } 1643 return val; 1644 } 1645 1646 static int kt_serial_setup(struct serial_private *priv, 1647 const struct pciserial_board *board, 1648 struct uart_8250_port *port, int idx) 1649 { 1650 port->port.flags |= UPF_BUG_THRE; 1651 port->port.serial_in = kt_serial_in; 1652 port->port.handle_break = kt_handle_break; 1653 return skip_tx_en_setup(priv, board, port, idx); 1654 } 1655 1656 static int pci_eg20t_init(struct pci_dev *dev) 1657 { 1658 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1659 return -ENODEV; 1660 #else 1661 return 0; 1662 #endif 1663 } 1664 1665 static int 1666 pci_wch_ch353_setup(struct serial_private *priv, 1667 const struct pciserial_board *board, 1668 struct uart_8250_port *port, int idx) 1669 { 1670 port->port.flags |= UPF_FIXED_TYPE; 1671 port->port.type = PORT_16550A; 1672 return pci_default_setup(priv, board, port, idx); 1673 } 1674 1675 static int 1676 pci_wch_ch355_setup(struct serial_private *priv, 1677 const struct pciserial_board *board, 1678 struct uart_8250_port *port, int idx) 1679 { 1680 port->port.flags |= UPF_FIXED_TYPE; 1681 port->port.type = PORT_16550A; 1682 return pci_default_setup(priv, board, port, idx); 1683 } 1684 1685 static int 1686 pci_wch_ch38x_setup(struct serial_private *priv, 1687 const struct pciserial_board *board, 1688 struct uart_8250_port *port, int idx) 1689 { 1690 port->port.flags |= UPF_FIXED_TYPE; 1691 port->port.type = PORT_16850; 1692 return pci_default_setup(priv, board, port, idx); 1693 } 1694 1695 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1696 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1697 #define PCI_DEVICE_ID_OCTPRO 0x0001 1698 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1699 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1700 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1701 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1702 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1703 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1704 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1705 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1706 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1707 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1708 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1709 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1710 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1711 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1712 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1713 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1714 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1715 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1716 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1717 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1718 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1719 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1720 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1721 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1722 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1723 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1724 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1725 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1726 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1727 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1728 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1729 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1730 #define PCI_VENDOR_ID_WCH 0x4348 1731 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1732 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1733 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1734 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1735 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1736 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1737 #define PCI_VENDOR_ID_AGESTAR 0x5372 1738 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1739 #define PCI_VENDOR_ID_ASIX 0x9710 1740 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1741 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1742 1743 #define PCIE_VENDOR_ID_WCH 0x1c00 1744 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1745 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1746 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1747 1748 #define PCI_VENDOR_ID_PERICOM 0x12D8 1749 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1750 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1751 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1752 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1753 1754 #define PCI_VENDOR_ID_ACCESIO 0x494f 1755 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1756 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1757 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1758 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1759 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1760 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1761 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1762 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1763 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1764 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1765 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1766 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1767 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1768 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1769 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1770 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1771 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1772 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1773 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1774 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1775 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1776 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1777 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1778 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1779 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1780 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1781 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1782 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1783 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1784 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1785 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1786 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1787 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1788 1789 1790 1791 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1792 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1793 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1794 1795 /* 1796 * Master list of serial port init/setup/exit quirks. 1797 * This does not describe the general nature of the port. 1798 * (ie, baud base, number and location of ports, etc) 1799 * 1800 * This list is ordered alphabetically by vendor then device. 1801 * Specific entries must come before more generic entries. 1802 */ 1803 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1804 /* 1805 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1806 */ 1807 { 1808 .vendor = PCI_VENDOR_ID_AMCC, 1809 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1810 .subvendor = PCI_ANY_ID, 1811 .subdevice = PCI_ANY_ID, 1812 .setup = addidata_apci7800_setup, 1813 }, 1814 /* 1815 * AFAVLAB cards - these may be called via parport_serial 1816 * It is not clear whether this applies to all products. 1817 */ 1818 { 1819 .vendor = PCI_VENDOR_ID_AFAVLAB, 1820 .device = PCI_ANY_ID, 1821 .subvendor = PCI_ANY_ID, 1822 .subdevice = PCI_ANY_ID, 1823 .setup = afavlab_setup, 1824 }, 1825 /* 1826 * HP Diva 1827 */ 1828 { 1829 .vendor = PCI_VENDOR_ID_HP, 1830 .device = PCI_DEVICE_ID_HP_DIVA, 1831 .subvendor = PCI_ANY_ID, 1832 .subdevice = PCI_ANY_ID, 1833 .init = pci_hp_diva_init, 1834 .setup = pci_hp_diva_setup, 1835 }, 1836 /* 1837 * Intel 1838 */ 1839 { 1840 .vendor = PCI_VENDOR_ID_INTEL, 1841 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1842 .subvendor = 0xe4bf, 1843 .subdevice = PCI_ANY_ID, 1844 .init = pci_inteli960ni_init, 1845 .setup = pci_default_setup, 1846 }, 1847 { 1848 .vendor = PCI_VENDOR_ID_INTEL, 1849 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1850 .subvendor = PCI_ANY_ID, 1851 .subdevice = PCI_ANY_ID, 1852 .setup = skip_tx_en_setup, 1853 }, 1854 { 1855 .vendor = PCI_VENDOR_ID_INTEL, 1856 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1857 .subvendor = PCI_ANY_ID, 1858 .subdevice = PCI_ANY_ID, 1859 .setup = skip_tx_en_setup, 1860 }, 1861 { 1862 .vendor = PCI_VENDOR_ID_INTEL, 1863 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1864 .subvendor = PCI_ANY_ID, 1865 .subdevice = PCI_ANY_ID, 1866 .setup = skip_tx_en_setup, 1867 }, 1868 { 1869 .vendor = PCI_VENDOR_ID_INTEL, 1870 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1871 .subvendor = PCI_ANY_ID, 1872 .subdevice = PCI_ANY_ID, 1873 .setup = ce4100_serial_setup, 1874 }, 1875 { 1876 .vendor = PCI_VENDOR_ID_INTEL, 1877 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1878 .subvendor = PCI_ANY_ID, 1879 .subdevice = PCI_ANY_ID, 1880 .setup = kt_serial_setup, 1881 }, 1882 /* 1883 * ITE 1884 */ 1885 { 1886 .vendor = PCI_VENDOR_ID_ITE, 1887 .device = PCI_DEVICE_ID_ITE_8872, 1888 .subvendor = PCI_ANY_ID, 1889 .subdevice = PCI_ANY_ID, 1890 .init = pci_ite887x_init, 1891 .setup = pci_default_setup, 1892 .exit = pci_ite887x_exit, 1893 }, 1894 /* 1895 * National Instruments 1896 */ 1897 { 1898 .vendor = PCI_VENDOR_ID_NI, 1899 .device = PCI_DEVICE_ID_NI_PCI23216, 1900 .subvendor = PCI_ANY_ID, 1901 .subdevice = PCI_ANY_ID, 1902 .init = pci_ni8420_init, 1903 .setup = pci_default_setup, 1904 .exit = pci_ni8420_exit, 1905 }, 1906 { 1907 .vendor = PCI_VENDOR_ID_NI, 1908 .device = PCI_DEVICE_ID_NI_PCI2328, 1909 .subvendor = PCI_ANY_ID, 1910 .subdevice = PCI_ANY_ID, 1911 .init = pci_ni8420_init, 1912 .setup = pci_default_setup, 1913 .exit = pci_ni8420_exit, 1914 }, 1915 { 1916 .vendor = PCI_VENDOR_ID_NI, 1917 .device = PCI_DEVICE_ID_NI_PCI2324, 1918 .subvendor = PCI_ANY_ID, 1919 .subdevice = PCI_ANY_ID, 1920 .init = pci_ni8420_init, 1921 .setup = pci_default_setup, 1922 .exit = pci_ni8420_exit, 1923 }, 1924 { 1925 .vendor = PCI_VENDOR_ID_NI, 1926 .device = PCI_DEVICE_ID_NI_PCI2322, 1927 .subvendor = PCI_ANY_ID, 1928 .subdevice = PCI_ANY_ID, 1929 .init = pci_ni8420_init, 1930 .setup = pci_default_setup, 1931 .exit = pci_ni8420_exit, 1932 }, 1933 { 1934 .vendor = PCI_VENDOR_ID_NI, 1935 .device = PCI_DEVICE_ID_NI_PCI2324I, 1936 .subvendor = PCI_ANY_ID, 1937 .subdevice = PCI_ANY_ID, 1938 .init = pci_ni8420_init, 1939 .setup = pci_default_setup, 1940 .exit = pci_ni8420_exit, 1941 }, 1942 { 1943 .vendor = PCI_VENDOR_ID_NI, 1944 .device = PCI_DEVICE_ID_NI_PCI2322I, 1945 .subvendor = PCI_ANY_ID, 1946 .subdevice = PCI_ANY_ID, 1947 .init = pci_ni8420_init, 1948 .setup = pci_default_setup, 1949 .exit = pci_ni8420_exit, 1950 }, 1951 { 1952 .vendor = PCI_VENDOR_ID_NI, 1953 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1954 .subvendor = PCI_ANY_ID, 1955 .subdevice = PCI_ANY_ID, 1956 .init = pci_ni8420_init, 1957 .setup = pci_default_setup, 1958 .exit = pci_ni8420_exit, 1959 }, 1960 { 1961 .vendor = PCI_VENDOR_ID_NI, 1962 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 1963 .subvendor = PCI_ANY_ID, 1964 .subdevice = PCI_ANY_ID, 1965 .init = pci_ni8420_init, 1966 .setup = pci_default_setup, 1967 .exit = pci_ni8420_exit, 1968 }, 1969 { 1970 .vendor = PCI_VENDOR_ID_NI, 1971 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 1972 .subvendor = PCI_ANY_ID, 1973 .subdevice = PCI_ANY_ID, 1974 .init = pci_ni8420_init, 1975 .setup = pci_default_setup, 1976 .exit = pci_ni8420_exit, 1977 }, 1978 { 1979 .vendor = PCI_VENDOR_ID_NI, 1980 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 1981 .subvendor = PCI_ANY_ID, 1982 .subdevice = PCI_ANY_ID, 1983 .init = pci_ni8420_init, 1984 .setup = pci_default_setup, 1985 .exit = pci_ni8420_exit, 1986 }, 1987 { 1988 .vendor = PCI_VENDOR_ID_NI, 1989 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 1990 .subvendor = PCI_ANY_ID, 1991 .subdevice = PCI_ANY_ID, 1992 .init = pci_ni8420_init, 1993 .setup = pci_default_setup, 1994 .exit = pci_ni8420_exit, 1995 }, 1996 { 1997 .vendor = PCI_VENDOR_ID_NI, 1998 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 1999 .subvendor = PCI_ANY_ID, 2000 .subdevice = PCI_ANY_ID, 2001 .init = pci_ni8420_init, 2002 .setup = pci_default_setup, 2003 .exit = pci_ni8420_exit, 2004 }, 2005 { 2006 .vendor = PCI_VENDOR_ID_NI, 2007 .device = PCI_ANY_ID, 2008 .subvendor = PCI_ANY_ID, 2009 .subdevice = PCI_ANY_ID, 2010 .init = pci_ni8430_init, 2011 .setup = pci_ni8430_setup, 2012 .exit = pci_ni8430_exit, 2013 }, 2014 /* Quatech */ 2015 { 2016 .vendor = PCI_VENDOR_ID_QUATECH, 2017 .device = PCI_ANY_ID, 2018 .subvendor = PCI_ANY_ID, 2019 .subdevice = PCI_ANY_ID, 2020 .init = pci_quatech_init, 2021 .setup = pci_quatech_setup, 2022 .exit = pci_quatech_exit, 2023 }, 2024 /* 2025 * Panacom 2026 */ 2027 { 2028 .vendor = PCI_VENDOR_ID_PANACOM, 2029 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2030 .subvendor = PCI_ANY_ID, 2031 .subdevice = PCI_ANY_ID, 2032 .init = pci_plx9050_init, 2033 .setup = pci_default_setup, 2034 .exit = pci_plx9050_exit, 2035 }, 2036 { 2037 .vendor = PCI_VENDOR_ID_PANACOM, 2038 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2039 .subvendor = PCI_ANY_ID, 2040 .subdevice = PCI_ANY_ID, 2041 .init = pci_plx9050_init, 2042 .setup = pci_default_setup, 2043 .exit = pci_plx9050_exit, 2044 }, 2045 /* 2046 * Pericom (Only 7954 - It have a offset jump for port 4) 2047 */ 2048 { 2049 .vendor = PCI_VENDOR_ID_PERICOM, 2050 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2051 .subvendor = PCI_ANY_ID, 2052 .subdevice = PCI_ANY_ID, 2053 .setup = pci_pericom_setup_four_at_eight, 2054 }, 2055 /* 2056 * PLX 2057 */ 2058 { 2059 .vendor = PCI_VENDOR_ID_PLX, 2060 .device = PCI_DEVICE_ID_PLX_9050, 2061 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2062 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2063 .init = pci_plx9050_init, 2064 .setup = pci_default_setup, 2065 .exit = pci_plx9050_exit, 2066 }, 2067 { 2068 .vendor = PCI_VENDOR_ID_PLX, 2069 .device = PCI_DEVICE_ID_PLX_9050, 2070 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2071 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2072 .init = pci_plx9050_init, 2073 .setup = pci_default_setup, 2074 .exit = pci_plx9050_exit, 2075 }, 2076 { 2077 .vendor = PCI_VENDOR_ID_PLX, 2078 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2079 .subvendor = PCI_VENDOR_ID_PLX, 2080 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2081 .init = pci_plx9050_init, 2082 .setup = pci_default_setup, 2083 .exit = pci_plx9050_exit, 2084 }, 2085 { 2086 .vendor = PCI_VENDOR_ID_ACCESIO, 2087 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2088 .subvendor = PCI_ANY_ID, 2089 .subdevice = PCI_ANY_ID, 2090 .setup = pci_pericom_setup_four_at_eight, 2091 }, 2092 { 2093 .vendor = PCI_VENDOR_ID_ACCESIO, 2094 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2095 .subvendor = PCI_ANY_ID, 2096 .subdevice = PCI_ANY_ID, 2097 .setup = pci_pericom_setup_four_at_eight, 2098 }, 2099 { 2100 .vendor = PCI_VENDOR_ID_ACCESIO, 2101 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2102 .subvendor = PCI_ANY_ID, 2103 .subdevice = PCI_ANY_ID, 2104 .setup = pci_pericom_setup_four_at_eight, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_ACCESIO, 2108 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .setup = pci_pericom_setup_four_at_eight, 2112 }, 2113 { 2114 .vendor = PCI_VENDOR_ID_ACCESIO, 2115 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2116 .subvendor = PCI_ANY_ID, 2117 .subdevice = PCI_ANY_ID, 2118 .setup = pci_pericom_setup_four_at_eight, 2119 }, 2120 { 2121 .vendor = PCI_VENDOR_ID_ACCESIO, 2122 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2123 .subvendor = PCI_ANY_ID, 2124 .subdevice = PCI_ANY_ID, 2125 .setup = pci_pericom_setup_four_at_eight, 2126 }, 2127 { 2128 .vendor = PCI_VENDOR_ID_ACCESIO, 2129 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2130 .subvendor = PCI_ANY_ID, 2131 .subdevice = PCI_ANY_ID, 2132 .setup = pci_pericom_setup_four_at_eight, 2133 }, 2134 { 2135 .vendor = PCI_VENDOR_ID_ACCESIO, 2136 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2137 .subvendor = PCI_ANY_ID, 2138 .subdevice = PCI_ANY_ID, 2139 .setup = pci_pericom_setup_four_at_eight, 2140 }, 2141 { 2142 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2143 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2144 .subvendor = PCI_ANY_ID, 2145 .subdevice = PCI_ANY_ID, 2146 .setup = pci_pericom_setup_four_at_eight, 2147 }, 2148 { 2149 .vendor = PCI_VENDOR_ID_ACCESIO, 2150 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2151 .subvendor = PCI_ANY_ID, 2152 .subdevice = PCI_ANY_ID, 2153 .setup = pci_pericom_setup_four_at_eight, 2154 }, 2155 { 2156 .vendor = PCI_VENDOR_ID_ACCESIO, 2157 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2158 .subvendor = PCI_ANY_ID, 2159 .subdevice = PCI_ANY_ID, 2160 .setup = pci_pericom_setup_four_at_eight, 2161 }, 2162 { 2163 .vendor = PCI_VENDOR_ID_ACCESIO, 2164 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2165 .subvendor = PCI_ANY_ID, 2166 .subdevice = PCI_ANY_ID, 2167 .setup = pci_pericom_setup_four_at_eight, 2168 }, 2169 { 2170 .vendor = PCI_VENDOR_ID_ACCESIO, 2171 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2172 .subvendor = PCI_ANY_ID, 2173 .subdevice = PCI_ANY_ID, 2174 .setup = pci_pericom_setup_four_at_eight, 2175 }, 2176 { 2177 .vendor = PCI_VENDOR_ID_ACCESIO, 2178 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2179 .subvendor = PCI_ANY_ID, 2180 .subdevice = PCI_ANY_ID, 2181 .setup = pci_pericom_setup_four_at_eight, 2182 }, 2183 { 2184 .vendor = PCI_VENDOR_ID_ACCESIO, 2185 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2186 .subvendor = PCI_ANY_ID, 2187 .subdevice = PCI_ANY_ID, 2188 .setup = pci_pericom_setup_four_at_eight, 2189 }, 2190 { 2191 .vendor = PCI_VENDOR_ID_ACCESIO, 2192 .device = PCI_ANY_ID, 2193 .subvendor = PCI_ANY_ID, 2194 .subdevice = PCI_ANY_ID, 2195 .setup = pci_pericom_setup, 2196 }, /* 2197 * SBS Technologies, Inc., PMC-OCTALPRO 232 2198 */ 2199 { 2200 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2201 .device = PCI_DEVICE_ID_OCTPRO, 2202 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2203 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2204 .init = sbs_init, 2205 .setup = sbs_setup, 2206 .exit = sbs_exit, 2207 }, 2208 /* 2209 * SBS Technologies, Inc., PMC-OCTALPRO 422 2210 */ 2211 { 2212 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2213 .device = PCI_DEVICE_ID_OCTPRO, 2214 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2215 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2216 .init = sbs_init, 2217 .setup = sbs_setup, 2218 .exit = sbs_exit, 2219 }, 2220 /* 2221 * SBS Technologies, Inc., P-Octal 232 2222 */ 2223 { 2224 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2225 .device = PCI_DEVICE_ID_OCTPRO, 2226 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2227 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2228 .init = sbs_init, 2229 .setup = sbs_setup, 2230 .exit = sbs_exit, 2231 }, 2232 /* 2233 * SBS Technologies, Inc., P-Octal 422 2234 */ 2235 { 2236 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2237 .device = PCI_DEVICE_ID_OCTPRO, 2238 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2239 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2240 .init = sbs_init, 2241 .setup = sbs_setup, 2242 .exit = sbs_exit, 2243 }, 2244 /* 2245 * SIIG cards - these may be called via parport_serial 2246 */ 2247 { 2248 .vendor = PCI_VENDOR_ID_SIIG, 2249 .device = PCI_ANY_ID, 2250 .subvendor = PCI_ANY_ID, 2251 .subdevice = PCI_ANY_ID, 2252 .init = pci_siig_init, 2253 .setup = pci_siig_setup, 2254 }, 2255 /* 2256 * Titan cards 2257 */ 2258 { 2259 .vendor = PCI_VENDOR_ID_TITAN, 2260 .device = PCI_DEVICE_ID_TITAN_400L, 2261 .subvendor = PCI_ANY_ID, 2262 .subdevice = PCI_ANY_ID, 2263 .setup = titan_400l_800l_setup, 2264 }, 2265 { 2266 .vendor = PCI_VENDOR_ID_TITAN, 2267 .device = PCI_DEVICE_ID_TITAN_800L, 2268 .subvendor = PCI_ANY_ID, 2269 .subdevice = PCI_ANY_ID, 2270 .setup = titan_400l_800l_setup, 2271 }, 2272 /* 2273 * Timedia cards 2274 */ 2275 { 2276 .vendor = PCI_VENDOR_ID_TIMEDIA, 2277 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2278 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2279 .subdevice = PCI_ANY_ID, 2280 .probe = pci_timedia_probe, 2281 .init = pci_timedia_init, 2282 .setup = pci_timedia_setup, 2283 }, 2284 { 2285 .vendor = PCI_VENDOR_ID_TIMEDIA, 2286 .device = PCI_ANY_ID, 2287 .subvendor = PCI_ANY_ID, 2288 .subdevice = PCI_ANY_ID, 2289 .setup = pci_timedia_setup, 2290 }, 2291 /* 2292 * SUNIX (Timedia) cards 2293 * Do not "probe" for these cards as there is at least one combination 2294 * card that should be handled by parport_pc that doesn't match the 2295 * rule in pci_timedia_probe. 2296 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2297 * There are some boards with part number SER5037AL that report 2298 * subdevice ID 0x0002. 2299 */ 2300 { 2301 .vendor = PCI_VENDOR_ID_SUNIX, 2302 .device = PCI_DEVICE_ID_SUNIX_1999, 2303 .subvendor = PCI_VENDOR_ID_SUNIX, 2304 .subdevice = PCI_ANY_ID, 2305 .init = pci_timedia_init, 2306 .setup = pci_timedia_setup, 2307 }, 2308 /* 2309 * Xircom cards 2310 */ 2311 { 2312 .vendor = PCI_VENDOR_ID_XIRCOM, 2313 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2314 .subvendor = PCI_ANY_ID, 2315 .subdevice = PCI_ANY_ID, 2316 .init = pci_xircom_init, 2317 .setup = pci_default_setup, 2318 }, 2319 /* 2320 * Netmos cards - these may be called via parport_serial 2321 */ 2322 { 2323 .vendor = PCI_VENDOR_ID_NETMOS, 2324 .device = PCI_ANY_ID, 2325 .subvendor = PCI_ANY_ID, 2326 .subdevice = PCI_ANY_ID, 2327 .init = pci_netmos_init, 2328 .setup = pci_netmos_9900_setup, 2329 }, 2330 /* 2331 * EndRun Technologies 2332 */ 2333 { 2334 .vendor = PCI_VENDOR_ID_ENDRUN, 2335 .device = PCI_ANY_ID, 2336 .subvendor = PCI_ANY_ID, 2337 .subdevice = PCI_ANY_ID, 2338 .init = pci_endrun_init, 2339 .setup = pci_default_setup, 2340 }, 2341 /* 2342 * For Oxford Semiconductor Tornado based devices 2343 */ 2344 { 2345 .vendor = PCI_VENDOR_ID_OXSEMI, 2346 .device = PCI_ANY_ID, 2347 .subvendor = PCI_ANY_ID, 2348 .subdevice = PCI_ANY_ID, 2349 .init = pci_oxsemi_tornado_init, 2350 .setup = pci_default_setup, 2351 }, 2352 { 2353 .vendor = PCI_VENDOR_ID_MAINPINE, 2354 .device = PCI_ANY_ID, 2355 .subvendor = PCI_ANY_ID, 2356 .subdevice = PCI_ANY_ID, 2357 .init = pci_oxsemi_tornado_init, 2358 .setup = pci_default_setup, 2359 }, 2360 { 2361 .vendor = PCI_VENDOR_ID_DIGI, 2362 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2363 .subvendor = PCI_SUBVENDOR_ID_IBM, 2364 .subdevice = PCI_ANY_ID, 2365 .init = pci_oxsemi_tornado_init, 2366 .setup = pci_default_setup, 2367 }, 2368 { 2369 .vendor = PCI_VENDOR_ID_INTEL, 2370 .device = 0x8811, 2371 .subvendor = PCI_ANY_ID, 2372 .subdevice = PCI_ANY_ID, 2373 .init = pci_eg20t_init, 2374 .setup = pci_default_setup, 2375 }, 2376 { 2377 .vendor = PCI_VENDOR_ID_INTEL, 2378 .device = 0x8812, 2379 .subvendor = PCI_ANY_ID, 2380 .subdevice = PCI_ANY_ID, 2381 .init = pci_eg20t_init, 2382 .setup = pci_default_setup, 2383 }, 2384 { 2385 .vendor = PCI_VENDOR_ID_INTEL, 2386 .device = 0x8813, 2387 .subvendor = PCI_ANY_ID, 2388 .subdevice = PCI_ANY_ID, 2389 .init = pci_eg20t_init, 2390 .setup = pci_default_setup, 2391 }, 2392 { 2393 .vendor = PCI_VENDOR_ID_INTEL, 2394 .device = 0x8814, 2395 .subvendor = PCI_ANY_ID, 2396 .subdevice = PCI_ANY_ID, 2397 .init = pci_eg20t_init, 2398 .setup = pci_default_setup, 2399 }, 2400 { 2401 .vendor = 0x10DB, 2402 .device = 0x8027, 2403 .subvendor = PCI_ANY_ID, 2404 .subdevice = PCI_ANY_ID, 2405 .init = pci_eg20t_init, 2406 .setup = pci_default_setup, 2407 }, 2408 { 2409 .vendor = 0x10DB, 2410 .device = 0x8028, 2411 .subvendor = PCI_ANY_ID, 2412 .subdevice = PCI_ANY_ID, 2413 .init = pci_eg20t_init, 2414 .setup = pci_default_setup, 2415 }, 2416 { 2417 .vendor = 0x10DB, 2418 .device = 0x8029, 2419 .subvendor = PCI_ANY_ID, 2420 .subdevice = PCI_ANY_ID, 2421 .init = pci_eg20t_init, 2422 .setup = pci_default_setup, 2423 }, 2424 { 2425 .vendor = 0x10DB, 2426 .device = 0x800C, 2427 .subvendor = PCI_ANY_ID, 2428 .subdevice = PCI_ANY_ID, 2429 .init = pci_eg20t_init, 2430 .setup = pci_default_setup, 2431 }, 2432 { 2433 .vendor = 0x10DB, 2434 .device = 0x800D, 2435 .subvendor = PCI_ANY_ID, 2436 .subdevice = PCI_ANY_ID, 2437 .init = pci_eg20t_init, 2438 .setup = pci_default_setup, 2439 }, 2440 /* 2441 * Cronyx Omega PCI (PLX-chip based) 2442 */ 2443 { 2444 .vendor = PCI_VENDOR_ID_PLX, 2445 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2446 .subvendor = PCI_ANY_ID, 2447 .subdevice = PCI_ANY_ID, 2448 .setup = pci_omegapci_setup, 2449 }, 2450 /* WCH CH353 1S1P card (16550 clone) */ 2451 { 2452 .vendor = PCI_VENDOR_ID_WCH, 2453 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2454 .subvendor = PCI_ANY_ID, 2455 .subdevice = PCI_ANY_ID, 2456 .setup = pci_wch_ch353_setup, 2457 }, 2458 /* WCH CH353 2S1P card (16550 clone) */ 2459 { 2460 .vendor = PCI_VENDOR_ID_WCH, 2461 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2462 .subvendor = PCI_ANY_ID, 2463 .subdevice = PCI_ANY_ID, 2464 .setup = pci_wch_ch353_setup, 2465 }, 2466 /* WCH CH353 4S card (16550 clone) */ 2467 { 2468 .vendor = PCI_VENDOR_ID_WCH, 2469 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2470 .subvendor = PCI_ANY_ID, 2471 .subdevice = PCI_ANY_ID, 2472 .setup = pci_wch_ch353_setup, 2473 }, 2474 /* WCH CH353 2S1PF card (16550 clone) */ 2475 { 2476 .vendor = PCI_VENDOR_ID_WCH, 2477 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2478 .subvendor = PCI_ANY_ID, 2479 .subdevice = PCI_ANY_ID, 2480 .setup = pci_wch_ch353_setup, 2481 }, 2482 /* WCH CH352 2S card (16550 clone) */ 2483 { 2484 .vendor = PCI_VENDOR_ID_WCH, 2485 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2486 .subvendor = PCI_ANY_ID, 2487 .subdevice = PCI_ANY_ID, 2488 .setup = pci_wch_ch353_setup, 2489 }, 2490 /* WCH CH355 4S card (16550 clone) */ 2491 { 2492 .vendor = PCI_VENDOR_ID_WCH, 2493 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2494 .subvendor = PCI_ANY_ID, 2495 .subdevice = PCI_ANY_ID, 2496 .setup = pci_wch_ch355_setup, 2497 }, 2498 /* WCH CH382 2S card (16850 clone) */ 2499 { 2500 .vendor = PCIE_VENDOR_ID_WCH, 2501 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2502 .subvendor = PCI_ANY_ID, 2503 .subdevice = PCI_ANY_ID, 2504 .setup = pci_wch_ch38x_setup, 2505 }, 2506 /* WCH CH382 2S1P card (16850 clone) */ 2507 { 2508 .vendor = PCIE_VENDOR_ID_WCH, 2509 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2510 .subvendor = PCI_ANY_ID, 2511 .subdevice = PCI_ANY_ID, 2512 .setup = pci_wch_ch38x_setup, 2513 }, 2514 /* WCH CH384 4S card (16850 clone) */ 2515 { 2516 .vendor = PCIE_VENDOR_ID_WCH, 2517 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2518 .subvendor = PCI_ANY_ID, 2519 .subdevice = PCI_ANY_ID, 2520 .setup = pci_wch_ch38x_setup, 2521 }, 2522 /* 2523 * ASIX devices with FIFO bug 2524 */ 2525 { 2526 .vendor = PCI_VENDOR_ID_ASIX, 2527 .device = PCI_ANY_ID, 2528 .subvendor = PCI_ANY_ID, 2529 .subdevice = PCI_ANY_ID, 2530 .setup = pci_asix_setup, 2531 }, 2532 /* 2533 * Broadcom TruManage (NetXtreme) 2534 */ 2535 { 2536 .vendor = PCI_VENDOR_ID_BROADCOM, 2537 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2538 .subvendor = PCI_ANY_ID, 2539 .subdevice = PCI_ANY_ID, 2540 .setup = pci_brcm_trumanage_setup, 2541 }, 2542 { 2543 .vendor = 0x1c29, 2544 .device = 0x1104, 2545 .subvendor = PCI_ANY_ID, 2546 .subdevice = PCI_ANY_ID, 2547 .setup = pci_fintek_setup, 2548 .init = pci_fintek_init, 2549 }, 2550 { 2551 .vendor = 0x1c29, 2552 .device = 0x1108, 2553 .subvendor = PCI_ANY_ID, 2554 .subdevice = PCI_ANY_ID, 2555 .setup = pci_fintek_setup, 2556 .init = pci_fintek_init, 2557 }, 2558 { 2559 .vendor = 0x1c29, 2560 .device = 0x1112, 2561 .subvendor = PCI_ANY_ID, 2562 .subdevice = PCI_ANY_ID, 2563 .setup = pci_fintek_setup, 2564 .init = pci_fintek_init, 2565 }, 2566 2567 /* 2568 * Default "match everything" terminator entry 2569 */ 2570 { 2571 .vendor = PCI_ANY_ID, 2572 .device = PCI_ANY_ID, 2573 .subvendor = PCI_ANY_ID, 2574 .subdevice = PCI_ANY_ID, 2575 .setup = pci_default_setup, 2576 } 2577 }; 2578 2579 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2580 { 2581 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2582 } 2583 2584 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2585 { 2586 struct pci_serial_quirk *quirk; 2587 2588 for (quirk = pci_serial_quirks; ; quirk++) 2589 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2590 quirk_id_matches(quirk->device, dev->device) && 2591 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2592 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2593 break; 2594 return quirk; 2595 } 2596 2597 static inline int get_pci_irq(struct pci_dev *dev, 2598 const struct pciserial_board *board) 2599 { 2600 if (board->flags & FL_NOIRQ) 2601 return 0; 2602 else 2603 return dev->irq; 2604 } 2605 2606 /* 2607 * This is the configuration table for all of the PCI serial boards 2608 * which we support. It is directly indexed by the pci_board_num_t enum 2609 * value, which is encoded in the pci_device_id PCI probe table's 2610 * driver_data member. 2611 * 2612 * The makeup of these names are: 2613 * pbn_bn{_bt}_n_baud{_offsetinhex} 2614 * 2615 * bn = PCI BAR number 2616 * bt = Index using PCI BARs 2617 * n = number of serial ports 2618 * baud = baud rate 2619 * offsetinhex = offset for each sequential port (in hex) 2620 * 2621 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2622 * 2623 * Please note: in theory if n = 1, _bt infix should make no difference. 2624 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2625 */ 2626 enum pci_board_num_t { 2627 pbn_default = 0, 2628 2629 pbn_b0_1_115200, 2630 pbn_b0_2_115200, 2631 pbn_b0_4_115200, 2632 pbn_b0_5_115200, 2633 pbn_b0_8_115200, 2634 2635 pbn_b0_1_921600, 2636 pbn_b0_2_921600, 2637 pbn_b0_4_921600, 2638 2639 pbn_b0_2_1130000, 2640 2641 pbn_b0_4_1152000, 2642 2643 pbn_b0_4_1250000, 2644 2645 pbn_b0_2_1843200, 2646 pbn_b0_4_1843200, 2647 2648 pbn_b0_1_4000000, 2649 2650 pbn_b0_bt_1_115200, 2651 pbn_b0_bt_2_115200, 2652 pbn_b0_bt_4_115200, 2653 pbn_b0_bt_8_115200, 2654 2655 pbn_b0_bt_1_460800, 2656 pbn_b0_bt_2_460800, 2657 pbn_b0_bt_4_460800, 2658 2659 pbn_b0_bt_1_921600, 2660 pbn_b0_bt_2_921600, 2661 pbn_b0_bt_4_921600, 2662 pbn_b0_bt_8_921600, 2663 2664 pbn_b1_1_115200, 2665 pbn_b1_2_115200, 2666 pbn_b1_4_115200, 2667 pbn_b1_8_115200, 2668 pbn_b1_16_115200, 2669 2670 pbn_b1_1_921600, 2671 pbn_b1_2_921600, 2672 pbn_b1_4_921600, 2673 pbn_b1_8_921600, 2674 2675 pbn_b1_2_1250000, 2676 2677 pbn_b1_bt_1_115200, 2678 pbn_b1_bt_2_115200, 2679 pbn_b1_bt_4_115200, 2680 2681 pbn_b1_bt_2_921600, 2682 2683 pbn_b1_1_1382400, 2684 pbn_b1_2_1382400, 2685 pbn_b1_4_1382400, 2686 pbn_b1_8_1382400, 2687 2688 pbn_b2_1_115200, 2689 pbn_b2_2_115200, 2690 pbn_b2_4_115200, 2691 pbn_b2_8_115200, 2692 2693 pbn_b2_1_460800, 2694 pbn_b2_4_460800, 2695 pbn_b2_8_460800, 2696 pbn_b2_16_460800, 2697 2698 pbn_b2_1_921600, 2699 pbn_b2_4_921600, 2700 pbn_b2_8_921600, 2701 2702 pbn_b2_8_1152000, 2703 2704 pbn_b2_bt_1_115200, 2705 pbn_b2_bt_2_115200, 2706 pbn_b2_bt_4_115200, 2707 2708 pbn_b2_bt_2_921600, 2709 pbn_b2_bt_4_921600, 2710 2711 pbn_b3_2_115200, 2712 pbn_b3_4_115200, 2713 pbn_b3_8_115200, 2714 2715 pbn_b4_bt_2_921600, 2716 pbn_b4_bt_4_921600, 2717 pbn_b4_bt_8_921600, 2718 2719 /* 2720 * Board-specific versions. 2721 */ 2722 pbn_panacom, 2723 pbn_panacom2, 2724 pbn_panacom4, 2725 pbn_plx_romulus, 2726 pbn_endrun_2_4000000, 2727 pbn_oxsemi, 2728 pbn_oxsemi_1_4000000, 2729 pbn_oxsemi_2_4000000, 2730 pbn_oxsemi_4_4000000, 2731 pbn_oxsemi_8_4000000, 2732 pbn_intel_i960, 2733 pbn_sgi_ioc3, 2734 pbn_computone_4, 2735 pbn_computone_6, 2736 pbn_computone_8, 2737 pbn_sbsxrsio, 2738 pbn_pasemi_1682M, 2739 pbn_ni8430_2, 2740 pbn_ni8430_4, 2741 pbn_ni8430_8, 2742 pbn_ni8430_16, 2743 pbn_ADDIDATA_PCIe_1_3906250, 2744 pbn_ADDIDATA_PCIe_2_3906250, 2745 pbn_ADDIDATA_PCIe_4_3906250, 2746 pbn_ADDIDATA_PCIe_8_3906250, 2747 pbn_ce4100_1_115200, 2748 pbn_omegapci, 2749 pbn_NETMOS9900_2s_115200, 2750 pbn_brcm_trumanage, 2751 pbn_fintek_4, 2752 pbn_fintek_8, 2753 pbn_fintek_12, 2754 pbn_wch382_2, 2755 pbn_wch384_4, 2756 pbn_pericom_PI7C9X7951, 2757 pbn_pericom_PI7C9X7952, 2758 pbn_pericom_PI7C9X7954, 2759 pbn_pericom_PI7C9X7958, 2760 }; 2761 2762 /* 2763 * uart_offset - the space between channels 2764 * reg_shift - describes how the UART registers are mapped 2765 * to PCI memory by the card. 2766 * For example IER register on SBS, Inc. PMC-OctPro is located at 2767 * offset 0x10 from the UART base, while UART_IER is defined as 1 2768 * in include/linux/serial_reg.h, 2769 * see first lines of serial_in() and serial_out() in 8250.c 2770 */ 2771 2772 static struct pciserial_board pci_boards[] = { 2773 [pbn_default] = { 2774 .flags = FL_BASE0, 2775 .num_ports = 1, 2776 .base_baud = 115200, 2777 .uart_offset = 8, 2778 }, 2779 [pbn_b0_1_115200] = { 2780 .flags = FL_BASE0, 2781 .num_ports = 1, 2782 .base_baud = 115200, 2783 .uart_offset = 8, 2784 }, 2785 [pbn_b0_2_115200] = { 2786 .flags = FL_BASE0, 2787 .num_ports = 2, 2788 .base_baud = 115200, 2789 .uart_offset = 8, 2790 }, 2791 [pbn_b0_4_115200] = { 2792 .flags = FL_BASE0, 2793 .num_ports = 4, 2794 .base_baud = 115200, 2795 .uart_offset = 8, 2796 }, 2797 [pbn_b0_5_115200] = { 2798 .flags = FL_BASE0, 2799 .num_ports = 5, 2800 .base_baud = 115200, 2801 .uart_offset = 8, 2802 }, 2803 [pbn_b0_8_115200] = { 2804 .flags = FL_BASE0, 2805 .num_ports = 8, 2806 .base_baud = 115200, 2807 .uart_offset = 8, 2808 }, 2809 [pbn_b0_1_921600] = { 2810 .flags = FL_BASE0, 2811 .num_ports = 1, 2812 .base_baud = 921600, 2813 .uart_offset = 8, 2814 }, 2815 [pbn_b0_2_921600] = { 2816 .flags = FL_BASE0, 2817 .num_ports = 2, 2818 .base_baud = 921600, 2819 .uart_offset = 8, 2820 }, 2821 [pbn_b0_4_921600] = { 2822 .flags = FL_BASE0, 2823 .num_ports = 4, 2824 .base_baud = 921600, 2825 .uart_offset = 8, 2826 }, 2827 2828 [pbn_b0_2_1130000] = { 2829 .flags = FL_BASE0, 2830 .num_ports = 2, 2831 .base_baud = 1130000, 2832 .uart_offset = 8, 2833 }, 2834 2835 [pbn_b0_4_1152000] = { 2836 .flags = FL_BASE0, 2837 .num_ports = 4, 2838 .base_baud = 1152000, 2839 .uart_offset = 8, 2840 }, 2841 2842 [pbn_b0_4_1250000] = { 2843 .flags = FL_BASE0, 2844 .num_ports = 4, 2845 .base_baud = 1250000, 2846 .uart_offset = 8, 2847 }, 2848 2849 [pbn_b0_2_1843200] = { 2850 .flags = FL_BASE0, 2851 .num_ports = 2, 2852 .base_baud = 1843200, 2853 .uart_offset = 8, 2854 }, 2855 [pbn_b0_4_1843200] = { 2856 .flags = FL_BASE0, 2857 .num_ports = 4, 2858 .base_baud = 1843200, 2859 .uart_offset = 8, 2860 }, 2861 2862 [pbn_b0_1_4000000] = { 2863 .flags = FL_BASE0, 2864 .num_ports = 1, 2865 .base_baud = 4000000, 2866 .uart_offset = 8, 2867 }, 2868 2869 [pbn_b0_bt_1_115200] = { 2870 .flags = FL_BASE0|FL_BASE_BARS, 2871 .num_ports = 1, 2872 .base_baud = 115200, 2873 .uart_offset = 8, 2874 }, 2875 [pbn_b0_bt_2_115200] = { 2876 .flags = FL_BASE0|FL_BASE_BARS, 2877 .num_ports = 2, 2878 .base_baud = 115200, 2879 .uart_offset = 8, 2880 }, 2881 [pbn_b0_bt_4_115200] = { 2882 .flags = FL_BASE0|FL_BASE_BARS, 2883 .num_ports = 4, 2884 .base_baud = 115200, 2885 .uart_offset = 8, 2886 }, 2887 [pbn_b0_bt_8_115200] = { 2888 .flags = FL_BASE0|FL_BASE_BARS, 2889 .num_ports = 8, 2890 .base_baud = 115200, 2891 .uart_offset = 8, 2892 }, 2893 2894 [pbn_b0_bt_1_460800] = { 2895 .flags = FL_BASE0|FL_BASE_BARS, 2896 .num_ports = 1, 2897 .base_baud = 460800, 2898 .uart_offset = 8, 2899 }, 2900 [pbn_b0_bt_2_460800] = { 2901 .flags = FL_BASE0|FL_BASE_BARS, 2902 .num_ports = 2, 2903 .base_baud = 460800, 2904 .uart_offset = 8, 2905 }, 2906 [pbn_b0_bt_4_460800] = { 2907 .flags = FL_BASE0|FL_BASE_BARS, 2908 .num_ports = 4, 2909 .base_baud = 460800, 2910 .uart_offset = 8, 2911 }, 2912 2913 [pbn_b0_bt_1_921600] = { 2914 .flags = FL_BASE0|FL_BASE_BARS, 2915 .num_ports = 1, 2916 .base_baud = 921600, 2917 .uart_offset = 8, 2918 }, 2919 [pbn_b0_bt_2_921600] = { 2920 .flags = FL_BASE0|FL_BASE_BARS, 2921 .num_ports = 2, 2922 .base_baud = 921600, 2923 .uart_offset = 8, 2924 }, 2925 [pbn_b0_bt_4_921600] = { 2926 .flags = FL_BASE0|FL_BASE_BARS, 2927 .num_ports = 4, 2928 .base_baud = 921600, 2929 .uart_offset = 8, 2930 }, 2931 [pbn_b0_bt_8_921600] = { 2932 .flags = FL_BASE0|FL_BASE_BARS, 2933 .num_ports = 8, 2934 .base_baud = 921600, 2935 .uart_offset = 8, 2936 }, 2937 2938 [pbn_b1_1_115200] = { 2939 .flags = FL_BASE1, 2940 .num_ports = 1, 2941 .base_baud = 115200, 2942 .uart_offset = 8, 2943 }, 2944 [pbn_b1_2_115200] = { 2945 .flags = FL_BASE1, 2946 .num_ports = 2, 2947 .base_baud = 115200, 2948 .uart_offset = 8, 2949 }, 2950 [pbn_b1_4_115200] = { 2951 .flags = FL_BASE1, 2952 .num_ports = 4, 2953 .base_baud = 115200, 2954 .uart_offset = 8, 2955 }, 2956 [pbn_b1_8_115200] = { 2957 .flags = FL_BASE1, 2958 .num_ports = 8, 2959 .base_baud = 115200, 2960 .uart_offset = 8, 2961 }, 2962 [pbn_b1_16_115200] = { 2963 .flags = FL_BASE1, 2964 .num_ports = 16, 2965 .base_baud = 115200, 2966 .uart_offset = 8, 2967 }, 2968 2969 [pbn_b1_1_921600] = { 2970 .flags = FL_BASE1, 2971 .num_ports = 1, 2972 .base_baud = 921600, 2973 .uart_offset = 8, 2974 }, 2975 [pbn_b1_2_921600] = { 2976 .flags = FL_BASE1, 2977 .num_ports = 2, 2978 .base_baud = 921600, 2979 .uart_offset = 8, 2980 }, 2981 [pbn_b1_4_921600] = { 2982 .flags = FL_BASE1, 2983 .num_ports = 4, 2984 .base_baud = 921600, 2985 .uart_offset = 8, 2986 }, 2987 [pbn_b1_8_921600] = { 2988 .flags = FL_BASE1, 2989 .num_ports = 8, 2990 .base_baud = 921600, 2991 .uart_offset = 8, 2992 }, 2993 [pbn_b1_2_1250000] = { 2994 .flags = FL_BASE1, 2995 .num_ports = 2, 2996 .base_baud = 1250000, 2997 .uart_offset = 8, 2998 }, 2999 3000 [pbn_b1_bt_1_115200] = { 3001 .flags = FL_BASE1|FL_BASE_BARS, 3002 .num_ports = 1, 3003 .base_baud = 115200, 3004 .uart_offset = 8, 3005 }, 3006 [pbn_b1_bt_2_115200] = { 3007 .flags = FL_BASE1|FL_BASE_BARS, 3008 .num_ports = 2, 3009 .base_baud = 115200, 3010 .uart_offset = 8, 3011 }, 3012 [pbn_b1_bt_4_115200] = { 3013 .flags = FL_BASE1|FL_BASE_BARS, 3014 .num_ports = 4, 3015 .base_baud = 115200, 3016 .uart_offset = 8, 3017 }, 3018 3019 [pbn_b1_bt_2_921600] = { 3020 .flags = FL_BASE1|FL_BASE_BARS, 3021 .num_ports = 2, 3022 .base_baud = 921600, 3023 .uart_offset = 8, 3024 }, 3025 3026 [pbn_b1_1_1382400] = { 3027 .flags = FL_BASE1, 3028 .num_ports = 1, 3029 .base_baud = 1382400, 3030 .uart_offset = 8, 3031 }, 3032 [pbn_b1_2_1382400] = { 3033 .flags = FL_BASE1, 3034 .num_ports = 2, 3035 .base_baud = 1382400, 3036 .uart_offset = 8, 3037 }, 3038 [pbn_b1_4_1382400] = { 3039 .flags = FL_BASE1, 3040 .num_ports = 4, 3041 .base_baud = 1382400, 3042 .uart_offset = 8, 3043 }, 3044 [pbn_b1_8_1382400] = { 3045 .flags = FL_BASE1, 3046 .num_ports = 8, 3047 .base_baud = 1382400, 3048 .uart_offset = 8, 3049 }, 3050 3051 [pbn_b2_1_115200] = { 3052 .flags = FL_BASE2, 3053 .num_ports = 1, 3054 .base_baud = 115200, 3055 .uart_offset = 8, 3056 }, 3057 [pbn_b2_2_115200] = { 3058 .flags = FL_BASE2, 3059 .num_ports = 2, 3060 .base_baud = 115200, 3061 .uart_offset = 8, 3062 }, 3063 [pbn_b2_4_115200] = { 3064 .flags = FL_BASE2, 3065 .num_ports = 4, 3066 .base_baud = 115200, 3067 .uart_offset = 8, 3068 }, 3069 [pbn_b2_8_115200] = { 3070 .flags = FL_BASE2, 3071 .num_ports = 8, 3072 .base_baud = 115200, 3073 .uart_offset = 8, 3074 }, 3075 3076 [pbn_b2_1_460800] = { 3077 .flags = FL_BASE2, 3078 .num_ports = 1, 3079 .base_baud = 460800, 3080 .uart_offset = 8, 3081 }, 3082 [pbn_b2_4_460800] = { 3083 .flags = FL_BASE2, 3084 .num_ports = 4, 3085 .base_baud = 460800, 3086 .uart_offset = 8, 3087 }, 3088 [pbn_b2_8_460800] = { 3089 .flags = FL_BASE2, 3090 .num_ports = 8, 3091 .base_baud = 460800, 3092 .uart_offset = 8, 3093 }, 3094 [pbn_b2_16_460800] = { 3095 .flags = FL_BASE2, 3096 .num_ports = 16, 3097 .base_baud = 460800, 3098 .uart_offset = 8, 3099 }, 3100 3101 [pbn_b2_1_921600] = { 3102 .flags = FL_BASE2, 3103 .num_ports = 1, 3104 .base_baud = 921600, 3105 .uart_offset = 8, 3106 }, 3107 [pbn_b2_4_921600] = { 3108 .flags = FL_BASE2, 3109 .num_ports = 4, 3110 .base_baud = 921600, 3111 .uart_offset = 8, 3112 }, 3113 [pbn_b2_8_921600] = { 3114 .flags = FL_BASE2, 3115 .num_ports = 8, 3116 .base_baud = 921600, 3117 .uart_offset = 8, 3118 }, 3119 3120 [pbn_b2_8_1152000] = { 3121 .flags = FL_BASE2, 3122 .num_ports = 8, 3123 .base_baud = 1152000, 3124 .uart_offset = 8, 3125 }, 3126 3127 [pbn_b2_bt_1_115200] = { 3128 .flags = FL_BASE2|FL_BASE_BARS, 3129 .num_ports = 1, 3130 .base_baud = 115200, 3131 .uart_offset = 8, 3132 }, 3133 [pbn_b2_bt_2_115200] = { 3134 .flags = FL_BASE2|FL_BASE_BARS, 3135 .num_ports = 2, 3136 .base_baud = 115200, 3137 .uart_offset = 8, 3138 }, 3139 [pbn_b2_bt_4_115200] = { 3140 .flags = FL_BASE2|FL_BASE_BARS, 3141 .num_ports = 4, 3142 .base_baud = 115200, 3143 .uart_offset = 8, 3144 }, 3145 3146 [pbn_b2_bt_2_921600] = { 3147 .flags = FL_BASE2|FL_BASE_BARS, 3148 .num_ports = 2, 3149 .base_baud = 921600, 3150 .uart_offset = 8, 3151 }, 3152 [pbn_b2_bt_4_921600] = { 3153 .flags = FL_BASE2|FL_BASE_BARS, 3154 .num_ports = 4, 3155 .base_baud = 921600, 3156 .uart_offset = 8, 3157 }, 3158 3159 [pbn_b3_2_115200] = { 3160 .flags = FL_BASE3, 3161 .num_ports = 2, 3162 .base_baud = 115200, 3163 .uart_offset = 8, 3164 }, 3165 [pbn_b3_4_115200] = { 3166 .flags = FL_BASE3, 3167 .num_ports = 4, 3168 .base_baud = 115200, 3169 .uart_offset = 8, 3170 }, 3171 [pbn_b3_8_115200] = { 3172 .flags = FL_BASE3, 3173 .num_ports = 8, 3174 .base_baud = 115200, 3175 .uart_offset = 8, 3176 }, 3177 3178 [pbn_b4_bt_2_921600] = { 3179 .flags = FL_BASE4, 3180 .num_ports = 2, 3181 .base_baud = 921600, 3182 .uart_offset = 8, 3183 }, 3184 [pbn_b4_bt_4_921600] = { 3185 .flags = FL_BASE4, 3186 .num_ports = 4, 3187 .base_baud = 921600, 3188 .uart_offset = 8, 3189 }, 3190 [pbn_b4_bt_8_921600] = { 3191 .flags = FL_BASE4, 3192 .num_ports = 8, 3193 .base_baud = 921600, 3194 .uart_offset = 8, 3195 }, 3196 3197 /* 3198 * Entries following this are board-specific. 3199 */ 3200 3201 /* 3202 * Panacom - IOMEM 3203 */ 3204 [pbn_panacom] = { 3205 .flags = FL_BASE2, 3206 .num_ports = 2, 3207 .base_baud = 921600, 3208 .uart_offset = 0x400, 3209 .reg_shift = 7, 3210 }, 3211 [pbn_panacom2] = { 3212 .flags = FL_BASE2|FL_BASE_BARS, 3213 .num_ports = 2, 3214 .base_baud = 921600, 3215 .uart_offset = 0x400, 3216 .reg_shift = 7, 3217 }, 3218 [pbn_panacom4] = { 3219 .flags = FL_BASE2|FL_BASE_BARS, 3220 .num_ports = 4, 3221 .base_baud = 921600, 3222 .uart_offset = 0x400, 3223 .reg_shift = 7, 3224 }, 3225 3226 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3227 [pbn_plx_romulus] = { 3228 .flags = FL_BASE2, 3229 .num_ports = 4, 3230 .base_baud = 921600, 3231 .uart_offset = 8 << 2, 3232 .reg_shift = 2, 3233 .first_offset = 0x03, 3234 }, 3235 3236 /* 3237 * EndRun Technologies 3238 * Uses the size of PCI Base region 0 to 3239 * signal now many ports are available 3240 * 2 port 952 Uart support 3241 */ 3242 [pbn_endrun_2_4000000] = { 3243 .flags = FL_BASE0, 3244 .num_ports = 2, 3245 .base_baud = 4000000, 3246 .uart_offset = 0x200, 3247 .first_offset = 0x1000, 3248 }, 3249 3250 /* 3251 * This board uses the size of PCI Base region 0 to 3252 * signal now many ports are available 3253 */ 3254 [pbn_oxsemi] = { 3255 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3256 .num_ports = 32, 3257 .base_baud = 115200, 3258 .uart_offset = 8, 3259 }, 3260 [pbn_oxsemi_1_4000000] = { 3261 .flags = FL_BASE0, 3262 .num_ports = 1, 3263 .base_baud = 4000000, 3264 .uart_offset = 0x200, 3265 .first_offset = 0x1000, 3266 }, 3267 [pbn_oxsemi_2_4000000] = { 3268 .flags = FL_BASE0, 3269 .num_ports = 2, 3270 .base_baud = 4000000, 3271 .uart_offset = 0x200, 3272 .first_offset = 0x1000, 3273 }, 3274 [pbn_oxsemi_4_4000000] = { 3275 .flags = FL_BASE0, 3276 .num_ports = 4, 3277 .base_baud = 4000000, 3278 .uart_offset = 0x200, 3279 .first_offset = 0x1000, 3280 }, 3281 [pbn_oxsemi_8_4000000] = { 3282 .flags = FL_BASE0, 3283 .num_ports = 8, 3284 .base_baud = 4000000, 3285 .uart_offset = 0x200, 3286 .first_offset = 0x1000, 3287 }, 3288 3289 3290 /* 3291 * EKF addition for i960 Boards form EKF with serial port. 3292 * Max 256 ports. 3293 */ 3294 [pbn_intel_i960] = { 3295 .flags = FL_BASE0, 3296 .num_ports = 32, 3297 .base_baud = 921600, 3298 .uart_offset = 8 << 2, 3299 .reg_shift = 2, 3300 .first_offset = 0x10000, 3301 }, 3302 [pbn_sgi_ioc3] = { 3303 .flags = FL_BASE0|FL_NOIRQ, 3304 .num_ports = 1, 3305 .base_baud = 458333, 3306 .uart_offset = 8, 3307 .reg_shift = 0, 3308 .first_offset = 0x20178, 3309 }, 3310 3311 /* 3312 * Computone - uses IOMEM. 3313 */ 3314 [pbn_computone_4] = { 3315 .flags = FL_BASE0, 3316 .num_ports = 4, 3317 .base_baud = 921600, 3318 .uart_offset = 0x40, 3319 .reg_shift = 2, 3320 .first_offset = 0x200, 3321 }, 3322 [pbn_computone_6] = { 3323 .flags = FL_BASE0, 3324 .num_ports = 6, 3325 .base_baud = 921600, 3326 .uart_offset = 0x40, 3327 .reg_shift = 2, 3328 .first_offset = 0x200, 3329 }, 3330 [pbn_computone_8] = { 3331 .flags = FL_BASE0, 3332 .num_ports = 8, 3333 .base_baud = 921600, 3334 .uart_offset = 0x40, 3335 .reg_shift = 2, 3336 .first_offset = 0x200, 3337 }, 3338 [pbn_sbsxrsio] = { 3339 .flags = FL_BASE0, 3340 .num_ports = 8, 3341 .base_baud = 460800, 3342 .uart_offset = 256, 3343 .reg_shift = 4, 3344 }, 3345 /* 3346 * PA Semi PWRficient PA6T-1682M on-chip UART 3347 */ 3348 [pbn_pasemi_1682M] = { 3349 .flags = FL_BASE0, 3350 .num_ports = 1, 3351 .base_baud = 8333333, 3352 }, 3353 /* 3354 * National Instruments 843x 3355 */ 3356 [pbn_ni8430_16] = { 3357 .flags = FL_BASE0, 3358 .num_ports = 16, 3359 .base_baud = 3686400, 3360 .uart_offset = 0x10, 3361 .first_offset = 0x800, 3362 }, 3363 [pbn_ni8430_8] = { 3364 .flags = FL_BASE0, 3365 .num_ports = 8, 3366 .base_baud = 3686400, 3367 .uart_offset = 0x10, 3368 .first_offset = 0x800, 3369 }, 3370 [pbn_ni8430_4] = { 3371 .flags = FL_BASE0, 3372 .num_ports = 4, 3373 .base_baud = 3686400, 3374 .uart_offset = 0x10, 3375 .first_offset = 0x800, 3376 }, 3377 [pbn_ni8430_2] = { 3378 .flags = FL_BASE0, 3379 .num_ports = 2, 3380 .base_baud = 3686400, 3381 .uart_offset = 0x10, 3382 .first_offset = 0x800, 3383 }, 3384 /* 3385 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3386 */ 3387 [pbn_ADDIDATA_PCIe_1_3906250] = { 3388 .flags = FL_BASE0, 3389 .num_ports = 1, 3390 .base_baud = 3906250, 3391 .uart_offset = 0x200, 3392 .first_offset = 0x1000, 3393 }, 3394 [pbn_ADDIDATA_PCIe_2_3906250] = { 3395 .flags = FL_BASE0, 3396 .num_ports = 2, 3397 .base_baud = 3906250, 3398 .uart_offset = 0x200, 3399 .first_offset = 0x1000, 3400 }, 3401 [pbn_ADDIDATA_PCIe_4_3906250] = { 3402 .flags = FL_BASE0, 3403 .num_ports = 4, 3404 .base_baud = 3906250, 3405 .uart_offset = 0x200, 3406 .first_offset = 0x1000, 3407 }, 3408 [pbn_ADDIDATA_PCIe_8_3906250] = { 3409 .flags = FL_BASE0, 3410 .num_ports = 8, 3411 .base_baud = 3906250, 3412 .uart_offset = 0x200, 3413 .first_offset = 0x1000, 3414 }, 3415 [pbn_ce4100_1_115200] = { 3416 .flags = FL_BASE_BARS, 3417 .num_ports = 2, 3418 .base_baud = 921600, 3419 .reg_shift = 2, 3420 }, 3421 [pbn_omegapci] = { 3422 .flags = FL_BASE0, 3423 .num_ports = 8, 3424 .base_baud = 115200, 3425 .uart_offset = 0x200, 3426 }, 3427 [pbn_NETMOS9900_2s_115200] = { 3428 .flags = FL_BASE0, 3429 .num_ports = 2, 3430 .base_baud = 115200, 3431 }, 3432 [pbn_brcm_trumanage] = { 3433 .flags = FL_BASE0, 3434 .num_ports = 1, 3435 .reg_shift = 2, 3436 .base_baud = 115200, 3437 }, 3438 [pbn_fintek_4] = { 3439 .num_ports = 4, 3440 .uart_offset = 8, 3441 .base_baud = 115200, 3442 .first_offset = 0x40, 3443 }, 3444 [pbn_fintek_8] = { 3445 .num_ports = 8, 3446 .uart_offset = 8, 3447 .base_baud = 115200, 3448 .first_offset = 0x40, 3449 }, 3450 [pbn_fintek_12] = { 3451 .num_ports = 12, 3452 .uart_offset = 8, 3453 .base_baud = 115200, 3454 .first_offset = 0x40, 3455 }, 3456 [pbn_wch382_2] = { 3457 .flags = FL_BASE0, 3458 .num_ports = 2, 3459 .base_baud = 115200, 3460 .uart_offset = 8, 3461 .first_offset = 0xC0, 3462 }, 3463 [pbn_wch384_4] = { 3464 .flags = FL_BASE0, 3465 .num_ports = 4, 3466 .base_baud = 115200, 3467 .uart_offset = 8, 3468 .first_offset = 0xC0, 3469 }, 3470 /* 3471 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3472 */ 3473 [pbn_pericom_PI7C9X7951] = { 3474 .flags = FL_BASE0, 3475 .num_ports = 1, 3476 .base_baud = 921600, 3477 .uart_offset = 0x8, 3478 }, 3479 [pbn_pericom_PI7C9X7952] = { 3480 .flags = FL_BASE0, 3481 .num_ports = 2, 3482 .base_baud = 921600, 3483 .uart_offset = 0x8, 3484 }, 3485 [pbn_pericom_PI7C9X7954] = { 3486 .flags = FL_BASE0, 3487 .num_ports = 4, 3488 .base_baud = 921600, 3489 .uart_offset = 0x8, 3490 }, 3491 [pbn_pericom_PI7C9X7958] = { 3492 .flags = FL_BASE0, 3493 .num_ports = 8, 3494 .base_baud = 921600, 3495 .uart_offset = 0x8, 3496 }, 3497 }; 3498 3499 static const struct pci_device_id blacklist[] = { 3500 /* softmodems */ 3501 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3502 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3503 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3504 3505 /* multi-io cards handled by parport_serial */ 3506 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3507 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3508 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3509 3510 /* Moxa Smartio MUE boards handled by 8250_moxa */ 3511 { PCI_VDEVICE(MOXA, 0x1024), }, 3512 { PCI_VDEVICE(MOXA, 0x1025), }, 3513 { PCI_VDEVICE(MOXA, 0x1045), }, 3514 { PCI_VDEVICE(MOXA, 0x1144), }, 3515 { PCI_VDEVICE(MOXA, 0x1160), }, 3516 { PCI_VDEVICE(MOXA, 0x1161), }, 3517 { PCI_VDEVICE(MOXA, 0x1182), }, 3518 { PCI_VDEVICE(MOXA, 0x1183), }, 3519 { PCI_VDEVICE(MOXA, 0x1322), }, 3520 { PCI_VDEVICE(MOXA, 0x1342), }, 3521 { PCI_VDEVICE(MOXA, 0x1381), }, 3522 { PCI_VDEVICE(MOXA, 0x1683), }, 3523 3524 /* Intel platforms with MID UART */ 3525 { PCI_VDEVICE(INTEL, 0x081b), }, 3526 { PCI_VDEVICE(INTEL, 0x081c), }, 3527 { PCI_VDEVICE(INTEL, 0x081d), }, 3528 { PCI_VDEVICE(INTEL, 0x1191), }, 3529 { PCI_VDEVICE(INTEL, 0x18d8), }, 3530 { PCI_VDEVICE(INTEL, 0x19d8), }, 3531 3532 /* Intel platforms with DesignWare UART */ 3533 { PCI_VDEVICE(INTEL, 0x0936), }, 3534 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3535 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3536 { PCI_VDEVICE(INTEL, 0x228a), }, 3537 { PCI_VDEVICE(INTEL, 0x228c), }, 3538 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3539 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3540 3541 /* Exar devices */ 3542 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3543 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3544 3545 /* End of the black list */ 3546 { } 3547 }; 3548 3549 static int serial_pci_is_class_communication(struct pci_dev *dev) 3550 { 3551 /* 3552 * If it is not a communications device or the programming 3553 * interface is greater than 6, give up. 3554 */ 3555 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3556 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3557 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3558 (dev->class & 0xff) > 6) 3559 return -ENODEV; 3560 3561 return 0; 3562 } 3563 3564 /* 3565 * Given a complete unknown PCI device, try to use some heuristics to 3566 * guess what the configuration might be, based on the pitiful PCI 3567 * serial specs. Returns 0 on success, -ENODEV on failure. 3568 */ 3569 static int 3570 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3571 { 3572 int num_iomem, num_port, first_port = -1, i; 3573 int rc; 3574 3575 rc = serial_pci_is_class_communication(dev); 3576 if (rc) 3577 return rc; 3578 3579 /* 3580 * Should we try to make guesses for multiport serial devices later? 3581 */ 3582 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3583 return -ENODEV; 3584 3585 num_iomem = num_port = 0; 3586 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3587 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3588 num_port++; 3589 if (first_port == -1) 3590 first_port = i; 3591 } 3592 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3593 num_iomem++; 3594 } 3595 3596 /* 3597 * If there is 1 or 0 iomem regions, and exactly one port, 3598 * use it. We guess the number of ports based on the IO 3599 * region size. 3600 */ 3601 if (num_iomem <= 1 && num_port == 1) { 3602 board->flags = first_port; 3603 board->num_ports = pci_resource_len(dev, first_port) / 8; 3604 return 0; 3605 } 3606 3607 /* 3608 * Now guess if we've got a board which indexes by BARs. 3609 * Each IO BAR should be 8 bytes, and they should follow 3610 * consecutively. 3611 */ 3612 first_port = -1; 3613 num_port = 0; 3614 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3615 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3616 pci_resource_len(dev, i) == 8 && 3617 (first_port == -1 || (first_port + num_port) == i)) { 3618 num_port++; 3619 if (first_port == -1) 3620 first_port = i; 3621 } 3622 } 3623 3624 if (num_port > 1) { 3625 board->flags = first_port | FL_BASE_BARS; 3626 board->num_ports = num_port; 3627 return 0; 3628 } 3629 3630 return -ENODEV; 3631 } 3632 3633 static inline int 3634 serial_pci_matches(const struct pciserial_board *board, 3635 const struct pciserial_board *guessed) 3636 { 3637 return 3638 board->num_ports == guessed->num_ports && 3639 board->base_baud == guessed->base_baud && 3640 board->uart_offset == guessed->uart_offset && 3641 board->reg_shift == guessed->reg_shift && 3642 board->first_offset == guessed->first_offset; 3643 } 3644 3645 struct serial_private * 3646 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3647 { 3648 struct uart_8250_port uart; 3649 struct serial_private *priv; 3650 struct pci_serial_quirk *quirk; 3651 int rc, nr_ports, i; 3652 3653 nr_ports = board->num_ports; 3654 3655 /* 3656 * Find an init and setup quirks. 3657 */ 3658 quirk = find_quirk(dev); 3659 3660 /* 3661 * Run the new-style initialization function. 3662 * The initialization function returns: 3663 * <0 - error 3664 * 0 - use board->num_ports 3665 * >0 - number of ports 3666 */ 3667 if (quirk->init) { 3668 rc = quirk->init(dev); 3669 if (rc < 0) { 3670 priv = ERR_PTR(rc); 3671 goto err_out; 3672 } 3673 if (rc) 3674 nr_ports = rc; 3675 } 3676 3677 priv = kzalloc(sizeof(struct serial_private) + 3678 sizeof(unsigned int) * nr_ports, 3679 GFP_KERNEL); 3680 if (!priv) { 3681 priv = ERR_PTR(-ENOMEM); 3682 goto err_deinit; 3683 } 3684 3685 priv->dev = dev; 3686 priv->quirk = quirk; 3687 3688 memset(&uart, 0, sizeof(uart)); 3689 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3690 uart.port.uartclk = board->base_baud * 16; 3691 uart.port.irq = get_pci_irq(dev, board); 3692 uart.port.dev = &dev->dev; 3693 3694 for (i = 0; i < nr_ports; i++) { 3695 if (quirk->setup(priv, board, &uart, i)) 3696 break; 3697 3698 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3699 uart.port.iobase, uart.port.irq, uart.port.iotype); 3700 3701 priv->line[i] = serial8250_register_8250_port(&uart); 3702 if (priv->line[i] < 0) { 3703 dev_err(&dev->dev, 3704 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3705 uart.port.iobase, uart.port.irq, 3706 uart.port.iotype, priv->line[i]); 3707 break; 3708 } 3709 } 3710 priv->nr = i; 3711 priv->board = board; 3712 return priv; 3713 3714 err_deinit: 3715 if (quirk->exit) 3716 quirk->exit(dev); 3717 err_out: 3718 return priv; 3719 } 3720 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3721 3722 static void pciserial_detach_ports(struct serial_private *priv) 3723 { 3724 struct pci_serial_quirk *quirk; 3725 int i; 3726 3727 for (i = 0; i < priv->nr; i++) 3728 serial8250_unregister_port(priv->line[i]); 3729 3730 /* 3731 * Find the exit quirks. 3732 */ 3733 quirk = find_quirk(priv->dev); 3734 if (quirk->exit) 3735 quirk->exit(priv->dev); 3736 } 3737 3738 void pciserial_remove_ports(struct serial_private *priv) 3739 { 3740 pciserial_detach_ports(priv); 3741 kfree(priv); 3742 } 3743 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3744 3745 void pciserial_suspend_ports(struct serial_private *priv) 3746 { 3747 int i; 3748 3749 for (i = 0; i < priv->nr; i++) 3750 if (priv->line[i] >= 0) 3751 serial8250_suspend_port(priv->line[i]); 3752 3753 /* 3754 * Ensure that every init quirk is properly torn down 3755 */ 3756 if (priv->quirk->exit) 3757 priv->quirk->exit(priv->dev); 3758 } 3759 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3760 3761 void pciserial_resume_ports(struct serial_private *priv) 3762 { 3763 int i; 3764 3765 /* 3766 * Ensure that the board is correctly configured. 3767 */ 3768 if (priv->quirk->init) 3769 priv->quirk->init(priv->dev); 3770 3771 for (i = 0; i < priv->nr; i++) 3772 if (priv->line[i] >= 0) 3773 serial8250_resume_port(priv->line[i]); 3774 } 3775 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3776 3777 /* 3778 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3779 * to the arrangement of serial ports on a PCI card. 3780 */ 3781 static int 3782 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3783 { 3784 struct pci_serial_quirk *quirk; 3785 struct serial_private *priv; 3786 const struct pciserial_board *board; 3787 const struct pci_device_id *exclude; 3788 struct pciserial_board tmp; 3789 int rc; 3790 3791 quirk = find_quirk(dev); 3792 if (quirk->probe) { 3793 rc = quirk->probe(dev); 3794 if (rc) 3795 return rc; 3796 } 3797 3798 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3799 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3800 ent->driver_data); 3801 return -EINVAL; 3802 } 3803 3804 board = &pci_boards[ent->driver_data]; 3805 3806 exclude = pci_match_id(blacklist, dev); 3807 if (exclude) 3808 return -ENODEV; 3809 3810 rc = pcim_enable_device(dev); 3811 pci_save_state(dev); 3812 if (rc) 3813 return rc; 3814 3815 if (ent->driver_data == pbn_default) { 3816 /* 3817 * Use a copy of the pci_board entry for this; 3818 * avoid changing entries in the table. 3819 */ 3820 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3821 board = &tmp; 3822 3823 /* 3824 * We matched one of our class entries. Try to 3825 * determine the parameters of this board. 3826 */ 3827 rc = serial_pci_guess_board(dev, &tmp); 3828 if (rc) 3829 return rc; 3830 } else { 3831 /* 3832 * We matched an explicit entry. If we are able to 3833 * detect this boards settings with our heuristic, 3834 * then we no longer need this entry. 3835 */ 3836 memcpy(&tmp, &pci_boards[pbn_default], 3837 sizeof(struct pciserial_board)); 3838 rc = serial_pci_guess_board(dev, &tmp); 3839 if (rc == 0 && serial_pci_matches(board, &tmp)) 3840 moan_device("Redundant entry in serial pci_table.", 3841 dev); 3842 } 3843 3844 priv = pciserial_init_ports(dev, board); 3845 if (IS_ERR(priv)) 3846 return PTR_ERR(priv); 3847 3848 pci_set_drvdata(dev, priv); 3849 return 0; 3850 } 3851 3852 static void pciserial_remove_one(struct pci_dev *dev) 3853 { 3854 struct serial_private *priv = pci_get_drvdata(dev); 3855 3856 pciserial_remove_ports(priv); 3857 } 3858 3859 #ifdef CONFIG_PM_SLEEP 3860 static int pciserial_suspend_one(struct device *dev) 3861 { 3862 struct pci_dev *pdev = to_pci_dev(dev); 3863 struct serial_private *priv = pci_get_drvdata(pdev); 3864 3865 if (priv) 3866 pciserial_suspend_ports(priv); 3867 3868 return 0; 3869 } 3870 3871 static int pciserial_resume_one(struct device *dev) 3872 { 3873 struct pci_dev *pdev = to_pci_dev(dev); 3874 struct serial_private *priv = pci_get_drvdata(pdev); 3875 int err; 3876 3877 if (priv) { 3878 /* 3879 * The device may have been disabled. Re-enable it. 3880 */ 3881 err = pci_enable_device(pdev); 3882 /* FIXME: We cannot simply error out here */ 3883 if (err) 3884 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 3885 pciserial_resume_ports(priv); 3886 } 3887 return 0; 3888 } 3889 #endif 3890 3891 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 3892 pciserial_resume_one); 3893 3894 static const struct pci_device_id serial_pci_tbl[] = { 3895 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3896 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3897 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3898 pbn_b2_8_921600 }, 3899 /* Advantech also use 0x3618 and 0xf618 */ 3900 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 3901 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3902 pbn_b0_4_921600 }, 3903 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 3904 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3905 pbn_b0_4_921600 }, 3906 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3907 PCI_SUBVENDOR_ID_CONNECT_TECH, 3908 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3909 pbn_b1_8_1382400 }, 3910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3911 PCI_SUBVENDOR_ID_CONNECT_TECH, 3912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3913 pbn_b1_4_1382400 }, 3914 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3915 PCI_SUBVENDOR_ID_CONNECT_TECH, 3916 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3917 pbn_b1_2_1382400 }, 3918 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3919 PCI_SUBVENDOR_ID_CONNECT_TECH, 3920 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3921 pbn_b1_8_1382400 }, 3922 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3923 PCI_SUBVENDOR_ID_CONNECT_TECH, 3924 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3925 pbn_b1_4_1382400 }, 3926 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3927 PCI_SUBVENDOR_ID_CONNECT_TECH, 3928 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3929 pbn_b1_2_1382400 }, 3930 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3931 PCI_SUBVENDOR_ID_CONNECT_TECH, 3932 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3933 pbn_b1_8_921600 }, 3934 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3935 PCI_SUBVENDOR_ID_CONNECT_TECH, 3936 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3937 pbn_b1_8_921600 }, 3938 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3939 PCI_SUBVENDOR_ID_CONNECT_TECH, 3940 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3941 pbn_b1_4_921600 }, 3942 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3943 PCI_SUBVENDOR_ID_CONNECT_TECH, 3944 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3945 pbn_b1_4_921600 }, 3946 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3947 PCI_SUBVENDOR_ID_CONNECT_TECH, 3948 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3949 pbn_b1_2_921600 }, 3950 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3951 PCI_SUBVENDOR_ID_CONNECT_TECH, 3952 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3953 pbn_b1_8_921600 }, 3954 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3955 PCI_SUBVENDOR_ID_CONNECT_TECH, 3956 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3957 pbn_b1_8_921600 }, 3958 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3959 PCI_SUBVENDOR_ID_CONNECT_TECH, 3960 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3961 pbn_b1_4_921600 }, 3962 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3963 PCI_SUBVENDOR_ID_CONNECT_TECH, 3964 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 3965 pbn_b1_2_1250000 }, 3966 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3967 PCI_SUBVENDOR_ID_CONNECT_TECH, 3968 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 3969 pbn_b0_2_1843200 }, 3970 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3971 PCI_SUBVENDOR_ID_CONNECT_TECH, 3972 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 3973 pbn_b0_4_1843200 }, 3974 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3975 PCI_VENDOR_ID_AFAVLAB, 3976 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 3977 pbn_b0_4_1152000 }, 3978 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3980 pbn_b2_bt_1_115200 }, 3981 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3983 pbn_b2_bt_2_115200 }, 3984 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3986 pbn_b2_bt_4_115200 }, 3987 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3989 pbn_b2_bt_2_115200 }, 3990 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3992 pbn_b2_bt_4_115200 }, 3993 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 3994 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3995 pbn_b2_8_115200 }, 3996 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 3997 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3998 pbn_b2_8_460800 }, 3999 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4000 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4001 pbn_b2_8_115200 }, 4002 4003 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4005 pbn_b2_bt_2_115200 }, 4006 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4007 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4008 pbn_b2_bt_2_921600 }, 4009 /* 4010 * VScom SPCOM800, from sl@s.pl 4011 */ 4012 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4013 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4014 pbn_b2_8_921600 }, 4015 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4017 pbn_b2_4_921600 }, 4018 /* Unknown card - subdevice 0x1584 */ 4019 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4020 PCI_VENDOR_ID_PLX, 4021 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4022 pbn_b2_4_115200 }, 4023 /* Unknown card - subdevice 0x1588 */ 4024 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4025 PCI_VENDOR_ID_PLX, 4026 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4027 pbn_b2_8_115200 }, 4028 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4029 PCI_SUBVENDOR_ID_KEYSPAN, 4030 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4031 pbn_panacom }, 4032 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4034 pbn_panacom4 }, 4035 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4037 pbn_panacom2 }, 4038 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4039 PCI_VENDOR_ID_ESDGMBH, 4040 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4041 pbn_b2_4_115200 }, 4042 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4043 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4044 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4045 pbn_b2_4_460800 }, 4046 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4047 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4048 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4049 pbn_b2_8_460800 }, 4050 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4051 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4052 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4053 pbn_b2_16_460800 }, 4054 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4055 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4056 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4057 pbn_b2_16_460800 }, 4058 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4059 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4060 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4061 pbn_b2_4_460800 }, 4062 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4063 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4064 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4065 pbn_b2_8_460800 }, 4066 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4067 PCI_SUBVENDOR_ID_EXSYS, 4068 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4069 pbn_b2_4_115200 }, 4070 /* 4071 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4072 * (Exoray@isys.ca) 4073 */ 4074 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4075 0x10b5, 0x106a, 0, 0, 4076 pbn_plx_romulus }, 4077 /* 4078 * EndRun Technologies. PCI express device range. 4079 * EndRun PTP/1588 has 2 Native UARTs. 4080 */ 4081 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4083 pbn_endrun_2_4000000 }, 4084 /* 4085 * Quatech cards. These actually have configurable clocks but for 4086 * now we just use the default. 4087 * 4088 * 100 series are RS232, 200 series RS422, 4089 */ 4090 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4091 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4092 pbn_b1_4_115200 }, 4093 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4094 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4095 pbn_b1_2_115200 }, 4096 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4097 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4098 pbn_b2_2_115200 }, 4099 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4101 pbn_b1_2_115200 }, 4102 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4104 pbn_b2_2_115200 }, 4105 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4107 pbn_b1_4_115200 }, 4108 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4110 pbn_b1_8_115200 }, 4111 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4113 pbn_b1_8_115200 }, 4114 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4116 pbn_b1_4_115200 }, 4117 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4119 pbn_b1_2_115200 }, 4120 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4122 pbn_b1_4_115200 }, 4123 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4125 pbn_b1_2_115200 }, 4126 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4128 pbn_b2_4_115200 }, 4129 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4131 pbn_b2_2_115200 }, 4132 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4134 pbn_b2_1_115200 }, 4135 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4137 pbn_b2_4_115200 }, 4138 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4140 pbn_b2_2_115200 }, 4141 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4143 pbn_b2_1_115200 }, 4144 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4146 pbn_b0_8_115200 }, 4147 4148 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4149 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4150 0, 0, 4151 pbn_b0_4_921600 }, 4152 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4153 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4154 0, 0, 4155 pbn_b0_4_1152000 }, 4156 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4158 pbn_b0_bt_2_921600 }, 4159 4160 /* 4161 * The below card is a little controversial since it is the 4162 * subject of a PCI vendor/device ID clash. (See 4163 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4164 * For now just used the hex ID 0x950a. 4165 */ 4166 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4167 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4168 0, 0, pbn_b0_2_115200 }, 4169 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4170 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4171 0, 0, pbn_b0_2_115200 }, 4172 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4174 pbn_b0_2_1130000 }, 4175 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4176 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4177 pbn_b0_1_921600 }, 4178 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4180 pbn_b0_4_115200 }, 4181 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4183 pbn_b0_bt_2_921600 }, 4184 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4186 pbn_b2_8_1152000 }, 4187 4188 /* 4189 * Oxford Semiconductor Inc. Tornado PCI express device range. 4190 */ 4191 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4193 pbn_b0_1_4000000 }, 4194 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b0_1_4000000 }, 4197 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4199 pbn_oxsemi_1_4000000 }, 4200 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4202 pbn_oxsemi_1_4000000 }, 4203 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b0_1_4000000 }, 4206 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4208 pbn_b0_1_4000000 }, 4209 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4211 pbn_oxsemi_1_4000000 }, 4212 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4214 pbn_oxsemi_1_4000000 }, 4215 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4217 pbn_b0_1_4000000 }, 4218 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4220 pbn_b0_1_4000000 }, 4221 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4223 pbn_b0_1_4000000 }, 4224 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4226 pbn_b0_1_4000000 }, 4227 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4229 pbn_oxsemi_2_4000000 }, 4230 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4232 pbn_oxsemi_2_4000000 }, 4233 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4235 pbn_oxsemi_4_4000000 }, 4236 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4238 pbn_oxsemi_4_4000000 }, 4239 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4241 pbn_oxsemi_8_4000000 }, 4242 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4244 pbn_oxsemi_8_4000000 }, 4245 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4247 pbn_oxsemi_1_4000000 }, 4248 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4250 pbn_oxsemi_1_4000000 }, 4251 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4253 pbn_oxsemi_1_4000000 }, 4254 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4256 pbn_oxsemi_1_4000000 }, 4257 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4259 pbn_oxsemi_1_4000000 }, 4260 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4262 pbn_oxsemi_1_4000000 }, 4263 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4265 pbn_oxsemi_1_4000000 }, 4266 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4268 pbn_oxsemi_1_4000000 }, 4269 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4271 pbn_oxsemi_1_4000000 }, 4272 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4274 pbn_oxsemi_1_4000000 }, 4275 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4277 pbn_oxsemi_1_4000000 }, 4278 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4280 pbn_oxsemi_1_4000000 }, 4281 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4283 pbn_oxsemi_1_4000000 }, 4284 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4286 pbn_oxsemi_1_4000000 }, 4287 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_oxsemi_1_4000000 }, 4290 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4292 pbn_oxsemi_1_4000000 }, 4293 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4295 pbn_oxsemi_1_4000000 }, 4296 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_oxsemi_1_4000000 }, 4299 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_oxsemi_1_4000000 }, 4302 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_oxsemi_1_4000000 }, 4305 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_oxsemi_1_4000000 }, 4308 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_oxsemi_1_4000000 }, 4311 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_oxsemi_1_4000000 }, 4314 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_oxsemi_1_4000000 }, 4317 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_oxsemi_1_4000000 }, 4320 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_oxsemi_1_4000000 }, 4323 /* 4324 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4325 */ 4326 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4327 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4328 pbn_oxsemi_1_4000000 }, 4329 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4330 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4331 pbn_oxsemi_2_4000000 }, 4332 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4333 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4334 pbn_oxsemi_4_4000000 }, 4335 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4336 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4337 pbn_oxsemi_8_4000000 }, 4338 4339 /* 4340 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4341 */ 4342 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4343 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4344 pbn_oxsemi_2_4000000 }, 4345 4346 /* 4347 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4348 * from skokodyn@yahoo.com 4349 */ 4350 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4351 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4352 pbn_sbsxrsio }, 4353 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4354 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4355 pbn_sbsxrsio }, 4356 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4357 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4358 pbn_sbsxrsio }, 4359 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4360 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4361 pbn_sbsxrsio }, 4362 4363 /* 4364 * Digitan DS560-558, from jimd@esoft.com 4365 */ 4366 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4368 pbn_b1_1_115200 }, 4369 4370 /* 4371 * Titan Electronic cards 4372 * The 400L and 800L have a custom setup quirk. 4373 */ 4374 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b0_1_921600 }, 4377 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b0_2_921600 }, 4380 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b0_4_921600 }, 4383 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4385 pbn_b0_4_921600 }, 4386 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_b1_1_921600 }, 4389 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b1_bt_2_921600 }, 4392 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b0_bt_4_921600 }, 4395 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4397 pbn_b0_bt_8_921600 }, 4398 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4400 pbn_b4_bt_2_921600 }, 4401 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b4_bt_4_921600 }, 4404 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b4_bt_8_921600 }, 4407 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b0_4_921600 }, 4410 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b0_4_921600 }, 4413 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b0_4_921600 }, 4416 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_oxsemi_1_4000000 }, 4419 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_oxsemi_2_4000000 }, 4422 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_oxsemi_4_4000000 }, 4425 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_oxsemi_8_4000000 }, 4428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_oxsemi_2_4000000 }, 4431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_oxsemi_2_4000000 }, 4434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b0_bt_2_921600 }, 4437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_b0_4_921600 }, 4440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_b0_4_921600 }, 4443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_b0_4_921600 }, 4446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_b0_4_921600 }, 4449 4450 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b2_1_460800 }, 4453 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_b2_1_460800 }, 4456 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_b2_1_460800 }, 4459 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_b2_bt_2_921600 }, 4462 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_b2_bt_2_921600 }, 4465 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_b2_bt_2_921600 }, 4468 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_b2_bt_4_921600 }, 4471 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_b2_bt_4_921600 }, 4474 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4476 pbn_b2_bt_4_921600 }, 4477 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4479 pbn_b0_1_921600 }, 4480 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4482 pbn_b0_1_921600 }, 4483 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_b0_1_921600 }, 4486 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_b0_bt_2_921600 }, 4489 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_b0_bt_2_921600 }, 4492 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_b0_bt_2_921600 }, 4495 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_b0_bt_4_921600 }, 4498 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_b0_bt_4_921600 }, 4501 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_b0_bt_4_921600 }, 4504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_b0_bt_8_921600 }, 4507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_b0_bt_8_921600 }, 4510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_b0_bt_8_921600 }, 4513 4514 /* 4515 * Computone devices submitted by Doug McNash dmcnash@computone.com 4516 */ 4517 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4518 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4519 0, 0, pbn_computone_4 }, 4520 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4521 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4522 0, 0, pbn_computone_8 }, 4523 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4524 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4525 0, 0, pbn_computone_6 }, 4526 4527 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_oxsemi }, 4530 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4531 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4532 pbn_b0_bt_1_921600 }, 4533 4534 /* 4535 * SUNIX (TIMEDIA) 4536 */ 4537 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4538 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4539 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4540 pbn_b0_bt_1_921600 }, 4541 4542 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4543 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4544 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4545 pbn_b0_bt_1_921600 }, 4546 4547 /* 4548 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4549 */ 4550 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4552 pbn_b0_bt_8_115200 }, 4553 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4555 pbn_b0_bt_8_115200 }, 4556 4557 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_b0_bt_2_115200 }, 4560 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4562 pbn_b0_bt_2_115200 }, 4563 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_b0_bt_2_115200 }, 4566 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_b0_bt_2_115200 }, 4569 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_b0_bt_2_115200 }, 4572 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_b0_bt_4_460800 }, 4575 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_b0_bt_4_460800 }, 4578 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4580 pbn_b0_bt_2_460800 }, 4581 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_b0_bt_2_460800 }, 4584 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_b0_bt_2_460800 }, 4587 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_b0_bt_1_115200 }, 4590 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_b0_bt_1_460800 }, 4593 4594 /* 4595 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4596 * Cards are identified by their subsystem vendor IDs, which 4597 * (in hex) match the model number. 4598 * 4599 * Note that JC140x are RS422/485 cards which require ox950 4600 * ACR = 0x10, and as such are not currently fully supported. 4601 */ 4602 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4603 0x1204, 0x0004, 0, 0, 4604 pbn_b0_4_921600 }, 4605 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4606 0x1208, 0x0004, 0, 0, 4607 pbn_b0_4_921600 }, 4608 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4609 0x1402, 0x0002, 0, 0, 4610 pbn_b0_2_921600 }, */ 4611 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4612 0x1404, 0x0004, 0, 0, 4613 pbn_b0_4_921600 }, */ 4614 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4615 0x1208, 0x0004, 0, 0, 4616 pbn_b0_4_921600 }, 4617 4618 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4619 0x1204, 0x0004, 0, 0, 4620 pbn_b0_4_921600 }, 4621 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4622 0x1208, 0x0004, 0, 0, 4623 pbn_b0_4_921600 }, 4624 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4625 0x1208, 0x0004, 0, 0, 4626 pbn_b0_4_921600 }, 4627 /* 4628 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4629 */ 4630 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4632 pbn_b1_1_1382400 }, 4633 4634 /* 4635 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4636 */ 4637 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_b1_1_1382400 }, 4640 4641 /* 4642 * RAStel 2 port modem, gerg@moreton.com.au 4643 */ 4644 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_b2_bt_2_115200 }, 4647 4648 /* 4649 * EKF addition for i960 Boards form EKF with serial port 4650 */ 4651 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4652 0xE4BF, PCI_ANY_ID, 0, 0, 4653 pbn_intel_i960 }, 4654 4655 /* 4656 * Xircom Cardbus/Ethernet combos 4657 */ 4658 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_b0_1_115200 }, 4661 /* 4662 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4663 */ 4664 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b0_1_115200 }, 4667 4668 /* 4669 * Untested PCI modems, sent in from various folks... 4670 */ 4671 4672 /* 4673 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4674 */ 4675 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4676 0x1048, 0x1500, 0, 0, 4677 pbn_b1_1_115200 }, 4678 4679 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4680 0xFF00, 0, 0, 0, 4681 pbn_sgi_ioc3 }, 4682 4683 /* 4684 * HP Diva card 4685 */ 4686 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4687 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4688 pbn_b1_1_115200 }, 4689 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b0_5_115200 }, 4692 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b2_1_115200 }, 4695 4696 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b3_2_115200 }, 4699 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b3_4_115200 }, 4702 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b3_8_115200 }, 4705 /* 4706 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4707 */ 4708 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4709 PCI_ANY_ID, PCI_ANY_ID, 4710 0, 4711 0, pbn_pericom_PI7C9X7951 }, 4712 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4713 PCI_ANY_ID, PCI_ANY_ID, 4714 0, 4715 0, pbn_pericom_PI7C9X7952 }, 4716 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4717 PCI_ANY_ID, PCI_ANY_ID, 4718 0, 4719 0, pbn_pericom_PI7C9X7954 }, 4720 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 4721 PCI_ANY_ID, PCI_ANY_ID, 4722 0, 4723 0, pbn_pericom_PI7C9X7958 }, 4724 /* 4725 * ACCES I/O Products quad 4726 */ 4727 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4729 pbn_pericom_PI7C9X7952 }, 4730 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4732 pbn_pericom_PI7C9X7952 }, 4733 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4735 pbn_pericom_PI7C9X7954 }, 4736 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4738 pbn_pericom_PI7C9X7954 }, 4739 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4741 pbn_pericom_PI7C9X7952 }, 4742 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_pericom_PI7C9X7952 }, 4745 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4747 pbn_pericom_PI7C9X7954 }, 4748 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_pericom_PI7C9X7954 }, 4751 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_pericom_PI7C9X7952 }, 4754 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_pericom_PI7C9X7952 }, 4757 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_pericom_PI7C9X7954 }, 4760 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_pericom_PI7C9X7954 }, 4763 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_pericom_PI7C9X7951 }, 4766 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_pericom_PI7C9X7952 }, 4769 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_pericom_PI7C9X7952 }, 4772 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_pericom_PI7C9X7954 }, 4775 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_pericom_PI7C9X7954 }, 4778 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_pericom_PI7C9X7952 }, 4781 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_pericom_PI7C9X7954 }, 4784 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_pericom_PI7C9X7952 }, 4787 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_pericom_PI7C9X7952 }, 4790 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_pericom_PI7C9X7954 }, 4793 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_pericom_PI7C9X7954 }, 4796 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_pericom_PI7C9X7952 }, 4799 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_pericom_PI7C9X7954 }, 4802 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_pericom_PI7C9X7954 }, 4805 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_pericom_PI7C9X7958 }, 4808 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4810 pbn_pericom_PI7C9X7958 }, 4811 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4813 pbn_pericom_PI7C9X7954 }, 4814 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4816 pbn_pericom_PI7C9X7958 }, 4817 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4819 pbn_pericom_PI7C9X7954 }, 4820 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 4821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4822 pbn_pericom_PI7C9X7958 }, 4823 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 4824 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4825 pbn_pericom_PI7C9X7954 }, 4826 /* 4827 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4828 */ 4829 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4830 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4831 pbn_b0_1_115200 }, 4832 /* 4833 * ITE 4834 */ 4835 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4836 PCI_ANY_ID, PCI_ANY_ID, 4837 0, 0, 4838 pbn_b1_bt_1_115200 }, 4839 4840 /* 4841 * IntaShield IS-200 4842 */ 4843 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4844 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4845 pbn_b2_2_115200 }, 4846 /* 4847 * IntaShield IS-400 4848 */ 4849 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4851 pbn_b2_4_115200 }, 4852 /* 4853 * BrainBoxes UC-260 4854 */ 4855 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4856 PCI_ANY_ID, PCI_ANY_ID, 4857 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4858 pbn_b2_4_115200 }, 4859 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4860 PCI_ANY_ID, PCI_ANY_ID, 4861 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4862 pbn_b2_4_115200 }, 4863 /* 4864 * Perle PCI-RAS cards 4865 */ 4866 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4867 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4868 0, 0, pbn_b2_4_921600 }, 4869 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4870 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4871 0, 0, pbn_b2_8_921600 }, 4872 4873 /* 4874 * Mainpine series cards: Fairly standard layout but fools 4875 * parts of the autodetect in some cases and uses otherwise 4876 * unmatched communications subclasses in the PCI Express case 4877 */ 4878 4879 { /* RockForceDUO */ 4880 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4881 PCI_VENDOR_ID_MAINPINE, 0x0200, 4882 0, 0, pbn_b0_2_115200 }, 4883 { /* RockForceQUATRO */ 4884 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4885 PCI_VENDOR_ID_MAINPINE, 0x0300, 4886 0, 0, pbn_b0_4_115200 }, 4887 { /* RockForceDUO+ */ 4888 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4889 PCI_VENDOR_ID_MAINPINE, 0x0400, 4890 0, 0, pbn_b0_2_115200 }, 4891 { /* RockForceQUATRO+ */ 4892 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4893 PCI_VENDOR_ID_MAINPINE, 0x0500, 4894 0, 0, pbn_b0_4_115200 }, 4895 { /* RockForce+ */ 4896 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4897 PCI_VENDOR_ID_MAINPINE, 0x0600, 4898 0, 0, pbn_b0_2_115200 }, 4899 { /* RockForce+ */ 4900 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4901 PCI_VENDOR_ID_MAINPINE, 0x0700, 4902 0, 0, pbn_b0_4_115200 }, 4903 { /* RockForceOCTO+ */ 4904 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4905 PCI_VENDOR_ID_MAINPINE, 0x0800, 4906 0, 0, pbn_b0_8_115200 }, 4907 { /* RockForceDUO+ */ 4908 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4909 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4910 0, 0, pbn_b0_2_115200 }, 4911 { /* RockForceQUARTRO+ */ 4912 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4913 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4914 0, 0, pbn_b0_4_115200 }, 4915 { /* RockForceOCTO+ */ 4916 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4917 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4918 0, 0, pbn_b0_8_115200 }, 4919 { /* RockForceD1 */ 4920 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4921 PCI_VENDOR_ID_MAINPINE, 0x2000, 4922 0, 0, pbn_b0_1_115200 }, 4923 { /* RockForceF1 */ 4924 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4925 PCI_VENDOR_ID_MAINPINE, 0x2100, 4926 0, 0, pbn_b0_1_115200 }, 4927 { /* RockForceD2 */ 4928 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4929 PCI_VENDOR_ID_MAINPINE, 0x2200, 4930 0, 0, pbn_b0_2_115200 }, 4931 { /* RockForceF2 */ 4932 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4933 PCI_VENDOR_ID_MAINPINE, 0x2300, 4934 0, 0, pbn_b0_2_115200 }, 4935 { /* RockForceD4 */ 4936 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4937 PCI_VENDOR_ID_MAINPINE, 0x2400, 4938 0, 0, pbn_b0_4_115200 }, 4939 { /* RockForceF4 */ 4940 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4941 PCI_VENDOR_ID_MAINPINE, 0x2500, 4942 0, 0, pbn_b0_4_115200 }, 4943 { /* RockForceD8 */ 4944 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4945 PCI_VENDOR_ID_MAINPINE, 0x2600, 4946 0, 0, pbn_b0_8_115200 }, 4947 { /* RockForceF8 */ 4948 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4949 PCI_VENDOR_ID_MAINPINE, 0x2700, 4950 0, 0, pbn_b0_8_115200 }, 4951 { /* IQ Express D1 */ 4952 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4953 PCI_VENDOR_ID_MAINPINE, 0x3000, 4954 0, 0, pbn_b0_1_115200 }, 4955 { /* IQ Express F1 */ 4956 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4957 PCI_VENDOR_ID_MAINPINE, 0x3100, 4958 0, 0, pbn_b0_1_115200 }, 4959 { /* IQ Express D2 */ 4960 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4961 PCI_VENDOR_ID_MAINPINE, 0x3200, 4962 0, 0, pbn_b0_2_115200 }, 4963 { /* IQ Express F2 */ 4964 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4965 PCI_VENDOR_ID_MAINPINE, 0x3300, 4966 0, 0, pbn_b0_2_115200 }, 4967 { /* IQ Express D4 */ 4968 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4969 PCI_VENDOR_ID_MAINPINE, 0x3400, 4970 0, 0, pbn_b0_4_115200 }, 4971 { /* IQ Express F4 */ 4972 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4973 PCI_VENDOR_ID_MAINPINE, 0x3500, 4974 0, 0, pbn_b0_4_115200 }, 4975 { /* IQ Express D8 */ 4976 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4977 PCI_VENDOR_ID_MAINPINE, 0x3C00, 4978 0, 0, pbn_b0_8_115200 }, 4979 { /* IQ Express F8 */ 4980 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4981 PCI_VENDOR_ID_MAINPINE, 0x3D00, 4982 0, 0, pbn_b0_8_115200 }, 4983 4984 4985 /* 4986 * PA Semi PA6T-1682M on-chip UART 4987 */ 4988 { PCI_VENDOR_ID_PASEMI, 0xa004, 4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4990 pbn_pasemi_1682M }, 4991 4992 /* 4993 * National Instruments 4994 */ 4995 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4997 pbn_b1_16_115200 }, 4998 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5000 pbn_b1_8_115200 }, 5001 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5003 pbn_b1_bt_4_115200 }, 5004 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5005 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5006 pbn_b1_bt_2_115200 }, 5007 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5009 pbn_b1_bt_4_115200 }, 5010 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5012 pbn_b1_bt_2_115200 }, 5013 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5015 pbn_b1_16_115200 }, 5016 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5018 pbn_b1_8_115200 }, 5019 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5021 pbn_b1_bt_4_115200 }, 5022 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5024 pbn_b1_bt_2_115200 }, 5025 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5027 pbn_b1_bt_4_115200 }, 5028 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5030 pbn_b1_bt_2_115200 }, 5031 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5032 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5033 pbn_ni8430_2 }, 5034 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5035 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5036 pbn_ni8430_2 }, 5037 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5038 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5039 pbn_ni8430_4 }, 5040 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5042 pbn_ni8430_4 }, 5043 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5045 pbn_ni8430_8 }, 5046 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5048 pbn_ni8430_8 }, 5049 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5051 pbn_ni8430_16 }, 5052 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5054 pbn_ni8430_16 }, 5055 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5057 pbn_ni8430_2 }, 5058 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5060 pbn_ni8430_2 }, 5061 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5063 pbn_ni8430_4 }, 5064 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5066 pbn_ni8430_4 }, 5067 5068 /* 5069 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5070 */ 5071 { PCI_VENDOR_ID_ADDIDATA, 5072 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5073 PCI_ANY_ID, 5074 PCI_ANY_ID, 5075 0, 5076 0, 5077 pbn_b0_4_115200 }, 5078 5079 { PCI_VENDOR_ID_ADDIDATA, 5080 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5081 PCI_ANY_ID, 5082 PCI_ANY_ID, 5083 0, 5084 0, 5085 pbn_b0_2_115200 }, 5086 5087 { PCI_VENDOR_ID_ADDIDATA, 5088 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5089 PCI_ANY_ID, 5090 PCI_ANY_ID, 5091 0, 5092 0, 5093 pbn_b0_1_115200 }, 5094 5095 { PCI_VENDOR_ID_AMCC, 5096 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5097 PCI_ANY_ID, 5098 PCI_ANY_ID, 5099 0, 5100 0, 5101 pbn_b1_8_115200 }, 5102 5103 { PCI_VENDOR_ID_ADDIDATA, 5104 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5105 PCI_ANY_ID, 5106 PCI_ANY_ID, 5107 0, 5108 0, 5109 pbn_b0_4_115200 }, 5110 5111 { PCI_VENDOR_ID_ADDIDATA, 5112 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5113 PCI_ANY_ID, 5114 PCI_ANY_ID, 5115 0, 5116 0, 5117 pbn_b0_2_115200 }, 5118 5119 { PCI_VENDOR_ID_ADDIDATA, 5120 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5121 PCI_ANY_ID, 5122 PCI_ANY_ID, 5123 0, 5124 0, 5125 pbn_b0_1_115200 }, 5126 5127 { PCI_VENDOR_ID_ADDIDATA, 5128 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5129 PCI_ANY_ID, 5130 PCI_ANY_ID, 5131 0, 5132 0, 5133 pbn_b0_4_115200 }, 5134 5135 { PCI_VENDOR_ID_ADDIDATA, 5136 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5137 PCI_ANY_ID, 5138 PCI_ANY_ID, 5139 0, 5140 0, 5141 pbn_b0_2_115200 }, 5142 5143 { PCI_VENDOR_ID_ADDIDATA, 5144 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5145 PCI_ANY_ID, 5146 PCI_ANY_ID, 5147 0, 5148 0, 5149 pbn_b0_1_115200 }, 5150 5151 { PCI_VENDOR_ID_ADDIDATA, 5152 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5153 PCI_ANY_ID, 5154 PCI_ANY_ID, 5155 0, 5156 0, 5157 pbn_b0_8_115200 }, 5158 5159 { PCI_VENDOR_ID_ADDIDATA, 5160 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5161 PCI_ANY_ID, 5162 PCI_ANY_ID, 5163 0, 5164 0, 5165 pbn_ADDIDATA_PCIe_4_3906250 }, 5166 5167 { PCI_VENDOR_ID_ADDIDATA, 5168 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5169 PCI_ANY_ID, 5170 PCI_ANY_ID, 5171 0, 5172 0, 5173 pbn_ADDIDATA_PCIe_2_3906250 }, 5174 5175 { PCI_VENDOR_ID_ADDIDATA, 5176 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5177 PCI_ANY_ID, 5178 PCI_ANY_ID, 5179 0, 5180 0, 5181 pbn_ADDIDATA_PCIe_1_3906250 }, 5182 5183 { PCI_VENDOR_ID_ADDIDATA, 5184 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5185 PCI_ANY_ID, 5186 PCI_ANY_ID, 5187 0, 5188 0, 5189 pbn_ADDIDATA_PCIe_8_3906250 }, 5190 5191 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5192 PCI_VENDOR_ID_IBM, 0x0299, 5193 0, 0, pbn_b0_bt_2_115200 }, 5194 5195 /* 5196 * other NetMos 9835 devices are most likely handled by the 5197 * parport_serial driver, check drivers/parport/parport_serial.c 5198 * before adding them here. 5199 */ 5200 5201 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5202 0xA000, 0x1000, 5203 0, 0, pbn_b0_1_115200 }, 5204 5205 /* the 9901 is a rebranded 9912 */ 5206 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5207 0xA000, 0x1000, 5208 0, 0, pbn_b0_1_115200 }, 5209 5210 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5211 0xA000, 0x1000, 5212 0, 0, pbn_b0_1_115200 }, 5213 5214 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5215 0xA000, 0x1000, 5216 0, 0, pbn_b0_1_115200 }, 5217 5218 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5219 0xA000, 0x1000, 5220 0, 0, pbn_b0_1_115200 }, 5221 5222 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5223 0xA000, 0x3002, 5224 0, 0, pbn_NETMOS9900_2s_115200 }, 5225 5226 /* 5227 * Best Connectivity and Rosewill PCI Multi I/O cards 5228 */ 5229 5230 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5231 0xA000, 0x1000, 5232 0, 0, pbn_b0_1_115200 }, 5233 5234 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5235 0xA000, 0x3002, 5236 0, 0, pbn_b0_bt_2_115200 }, 5237 5238 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5239 0xA000, 0x3004, 5240 0, 0, pbn_b0_bt_4_115200 }, 5241 /* Intel CE4100 */ 5242 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5244 pbn_ce4100_1_115200 }, 5245 5246 /* 5247 * Cronyx Omega PCI 5248 */ 5249 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5251 pbn_omegapci }, 5252 5253 /* 5254 * Broadcom TruManage 5255 */ 5256 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5258 pbn_brcm_trumanage }, 5259 5260 /* 5261 * AgeStar as-prs2-009 5262 */ 5263 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5264 PCI_ANY_ID, PCI_ANY_ID, 5265 0, 0, pbn_b0_bt_2_115200 }, 5266 5267 /* 5268 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5269 * so not listed here. 5270 */ 5271 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5272 PCI_ANY_ID, PCI_ANY_ID, 5273 0, 0, pbn_b0_bt_4_115200 }, 5274 5275 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5276 PCI_ANY_ID, PCI_ANY_ID, 5277 0, 0, pbn_b0_bt_2_115200 }, 5278 5279 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5280 PCI_ANY_ID, PCI_ANY_ID, 5281 0, 0, pbn_b0_bt_4_115200 }, 5282 5283 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5284 PCI_ANY_ID, PCI_ANY_ID, 5285 0, 0, pbn_wch382_2 }, 5286 5287 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5288 PCI_ANY_ID, PCI_ANY_ID, 5289 0, 0, pbn_wch384_4 }, 5290 5291 /* Fintek PCI serial cards */ 5292 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5293 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5294 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5295 5296 /* MKS Tenta SCOM-080x serial cards */ 5297 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5298 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5299 5300 /* Amazon PCI serial device */ 5301 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5302 5303 /* 5304 * These entries match devices with class COMMUNICATION_SERIAL, 5305 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5306 */ 5307 { PCI_ANY_ID, PCI_ANY_ID, 5308 PCI_ANY_ID, PCI_ANY_ID, 5309 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5310 0xffff00, pbn_default }, 5311 { PCI_ANY_ID, PCI_ANY_ID, 5312 PCI_ANY_ID, PCI_ANY_ID, 5313 PCI_CLASS_COMMUNICATION_MODEM << 8, 5314 0xffff00, pbn_default }, 5315 { PCI_ANY_ID, PCI_ANY_ID, 5316 PCI_ANY_ID, PCI_ANY_ID, 5317 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5318 0xffff00, pbn_default }, 5319 { 0, } 5320 }; 5321 5322 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5323 pci_channel_state_t state) 5324 { 5325 struct serial_private *priv = pci_get_drvdata(dev); 5326 5327 if (state == pci_channel_io_perm_failure) 5328 return PCI_ERS_RESULT_DISCONNECT; 5329 5330 if (priv) 5331 pciserial_detach_ports(priv); 5332 5333 pci_disable_device(dev); 5334 5335 return PCI_ERS_RESULT_NEED_RESET; 5336 } 5337 5338 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5339 { 5340 int rc; 5341 5342 rc = pci_enable_device(dev); 5343 5344 if (rc) 5345 return PCI_ERS_RESULT_DISCONNECT; 5346 5347 pci_restore_state(dev); 5348 pci_save_state(dev); 5349 5350 return PCI_ERS_RESULT_RECOVERED; 5351 } 5352 5353 static void serial8250_io_resume(struct pci_dev *dev) 5354 { 5355 struct serial_private *priv = pci_get_drvdata(dev); 5356 struct serial_private *new; 5357 5358 if (!priv) 5359 return; 5360 5361 new = pciserial_init_ports(dev, priv->board); 5362 if (!IS_ERR(new)) { 5363 pci_set_drvdata(dev, new); 5364 kfree(priv); 5365 } 5366 } 5367 5368 static const struct pci_error_handlers serial8250_err_handler = { 5369 .error_detected = serial8250_io_error_detected, 5370 .slot_reset = serial8250_io_slot_reset, 5371 .resume = serial8250_io_resume, 5372 }; 5373 5374 static struct pci_driver serial_pci_driver = { 5375 .name = "serial", 5376 .probe = pciserial_init_one, 5377 .remove = pciserial_remove_one, 5378 .driver = { 5379 .pm = &pciserial_pm_ops, 5380 }, 5381 .id_table = serial_pci_tbl, 5382 .err_handler = &serial8250_err_handler, 5383 }; 5384 5385 module_pci_driver(serial_pci_driver); 5386 5387 MODULE_LICENSE("GPL"); 5388 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5389 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5390