1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include "8250.h" 29 30 #undef SERIAL_DEBUG_PCI 31 32 /* 33 * init function returns: 34 * > 0 - number of ports 35 * = 0 - use board->num_ports 36 * < 0 - error 37 */ 38 struct pci_serial_quirk { 39 u32 vendor; 40 u32 device; 41 u32 subvendor; 42 u32 subdevice; 43 int (*probe)(struct pci_dev *dev); 44 int (*init)(struct pci_dev *dev); 45 int (*setup)(struct serial_private *, 46 const struct pciserial_board *, 47 struct uart_8250_port *, int); 48 void (*exit)(struct pci_dev *dev); 49 }; 50 51 #define PCI_NUM_BAR_RESOURCES 6 52 53 struct serial_private { 54 struct pci_dev *dev; 55 unsigned int nr; 56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 57 struct pci_serial_quirk *quirk; 58 int line[0]; 59 }; 60 61 static int pci_default_setup(struct serial_private*, 62 const struct pciserial_board*, struct uart_8250_port *, int); 63 64 static void moan_device(const char *str, struct pci_dev *dev) 65 { 66 printk(KERN_WARNING 67 "%s: %s\n" 68 "Please send the output of lspci -vv, this\n" 69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 70 "manufacturer and name of serial board or\n" 71 "modem board to rmk+serial@arm.linux.org.uk.\n", 72 pci_name(dev), str, dev->vendor, dev->device, 73 dev->subsystem_vendor, dev->subsystem_device); 74 } 75 76 static int 77 setup_port(struct serial_private *priv, struct uart_8250_port *port, 78 int bar, int offset, int regshift) 79 { 80 struct pci_dev *dev = priv->dev; 81 unsigned long base, len; 82 83 if (bar >= PCI_NUM_BAR_RESOURCES) 84 return -EINVAL; 85 86 base = pci_resource_start(dev, bar); 87 88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 89 len = pci_resource_len(dev, bar); 90 91 if (!priv->remapped_bar[bar]) 92 priv->remapped_bar[bar] = ioremap_nocache(base, len); 93 if (!priv->remapped_bar[bar]) 94 return -ENOMEM; 95 96 port->port.iotype = UPIO_MEM; 97 port->port.iobase = 0; 98 port->port.mapbase = base + offset; 99 port->port.membase = priv->remapped_bar[bar] + offset; 100 port->port.regshift = regshift; 101 } else { 102 port->port.iotype = UPIO_PORT; 103 port->port.iobase = base + offset; 104 port->port.mapbase = 0; 105 port->port.membase = NULL; 106 port->port.regshift = 0; 107 } 108 return 0; 109 } 110 111 /* 112 * ADDI-DATA GmbH communication cards <info@addi-data.com> 113 */ 114 static int addidata_apci7800_setup(struct serial_private *priv, 115 const struct pciserial_board *board, 116 struct uart_8250_port *port, int idx) 117 { 118 unsigned int bar = 0, offset = board->first_offset; 119 bar = FL_GET_BASE(board->flags); 120 121 if (idx < 2) { 122 offset += idx * board->uart_offset; 123 } else if ((idx >= 2) && (idx < 4)) { 124 bar += 1; 125 offset += ((idx - 2) * board->uart_offset); 126 } else if ((idx >= 4) && (idx < 6)) { 127 bar += 2; 128 offset += ((idx - 4) * board->uart_offset); 129 } else if (idx >= 6) { 130 bar += 3; 131 offset += ((idx - 6) * board->uart_offset); 132 } 133 134 return setup_port(priv, port, bar, offset, board->reg_shift); 135 } 136 137 /* 138 * AFAVLAB uses a different mixture of BARs and offsets 139 * Not that ugly ;) -- HW 140 */ 141 static int 142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 143 struct uart_8250_port *port, int idx) 144 { 145 unsigned int bar, offset = board->first_offset; 146 147 bar = FL_GET_BASE(board->flags); 148 if (idx < 4) 149 bar += idx; 150 else { 151 bar = 4; 152 offset += (idx - 4) * board->uart_offset; 153 } 154 155 return setup_port(priv, port, bar, offset, board->reg_shift); 156 } 157 158 /* 159 * HP's Remote Management Console. The Diva chip came in several 160 * different versions. N-class, L2000 and A500 have two Diva chips, each 161 * with 3 UARTs (the third UART on the second chip is unused). Superdome 162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 163 * one Diva chip, but it has been expanded to 5 UARTs. 164 */ 165 static int pci_hp_diva_init(struct pci_dev *dev) 166 { 167 int rc = 0; 168 169 switch (dev->subsystem_device) { 170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 173 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 174 rc = 3; 175 break; 176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 177 rc = 2; 178 break; 179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 180 rc = 4; 181 break; 182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 184 rc = 1; 185 break; 186 } 187 188 return rc; 189 } 190 191 /* 192 * HP's Diva chip puts the 4th/5th serial port further out, and 193 * some serial ports are supposed to be hidden on certain models. 194 */ 195 static int 196 pci_hp_diva_setup(struct serial_private *priv, 197 const struct pciserial_board *board, 198 struct uart_8250_port *port, int idx) 199 { 200 unsigned int offset = board->first_offset; 201 unsigned int bar = FL_GET_BASE(board->flags); 202 203 switch (priv->dev->subsystem_device) { 204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 205 if (idx == 3) 206 idx++; 207 break; 208 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 209 if (idx > 0) 210 idx++; 211 if (idx > 2) 212 idx++; 213 break; 214 } 215 if (idx > 2) 216 offset = 0x18; 217 218 offset += idx * board->uart_offset; 219 220 return setup_port(priv, port, bar, offset, board->reg_shift); 221 } 222 223 /* 224 * Added for EKF Intel i960 serial boards 225 */ 226 static int pci_inteli960ni_init(struct pci_dev *dev) 227 { 228 unsigned long oldval; 229 230 if (!(dev->subsystem_device & 0x1000)) 231 return -ENODEV; 232 233 /* is firmware started? */ 234 pci_read_config_dword(dev, 0x44, (void *)&oldval); 235 if (oldval == 0x00001000L) { /* RESET value */ 236 printk(KERN_DEBUG "Local i960 firmware missing"); 237 return -ENODEV; 238 } 239 return 0; 240 } 241 242 /* 243 * Some PCI serial cards using the PLX 9050 PCI interface chip require 244 * that the card interrupt be explicitly enabled or disabled. This 245 * seems to be mainly needed on card using the PLX which also use I/O 246 * mapped memory. 247 */ 248 static int pci_plx9050_init(struct pci_dev *dev) 249 { 250 u8 irq_config; 251 void __iomem *p; 252 253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 254 moan_device("no memory in bar 0", dev); 255 return 0; 256 } 257 258 irq_config = 0x41; 259 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 261 irq_config = 0x43; 262 263 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 265 /* 266 * As the megawolf cards have the int pins active 267 * high, and have 2 UART chips, both ints must be 268 * enabled on the 9050. Also, the UARTS are set in 269 * 16450 mode by default, so we have to enable the 270 * 16C950 'enhanced' mode so that we can use the 271 * deep FIFOs 272 */ 273 irq_config = 0x5b; 274 /* 275 * enable/disable interrupts 276 */ 277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 278 if (p == NULL) 279 return -ENOMEM; 280 writel(irq_config, p + 0x4c); 281 282 /* 283 * Read the register back to ensure that it took effect. 284 */ 285 readl(p + 0x4c); 286 iounmap(p); 287 288 return 0; 289 } 290 291 static void pci_plx9050_exit(struct pci_dev *dev) 292 { 293 u8 __iomem *p; 294 295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 296 return; 297 298 /* 299 * disable interrupts 300 */ 301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 302 if (p != NULL) { 303 writel(0, p + 0x4c); 304 305 /* 306 * Read the register back to ensure that it took effect. 307 */ 308 readl(p + 0x4c); 309 iounmap(p); 310 } 311 } 312 313 #define NI8420_INT_ENABLE_REG 0x38 314 #define NI8420_INT_ENABLE_BIT 0x2000 315 316 static void pci_ni8420_exit(struct pci_dev *dev) 317 { 318 void __iomem *p; 319 unsigned long base, len; 320 unsigned int bar = 0; 321 322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 323 moan_device("no memory in bar", dev); 324 return; 325 } 326 327 base = pci_resource_start(dev, bar); 328 len = pci_resource_len(dev, bar); 329 p = ioremap_nocache(base, len); 330 if (p == NULL) 331 return; 332 333 /* Disable the CPU Interrupt */ 334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 335 p + NI8420_INT_ENABLE_REG); 336 iounmap(p); 337 } 338 339 340 /* MITE registers */ 341 #define MITE_IOWBSR1 0xc4 342 #define MITE_IOWCR1 0xf4 343 #define MITE_LCIMR1 0x08 344 #define MITE_LCIMR2 0x10 345 346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 347 348 static void pci_ni8430_exit(struct pci_dev *dev) 349 { 350 void __iomem *p; 351 unsigned long base, len; 352 unsigned int bar = 0; 353 354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 355 moan_device("no memory in bar", dev); 356 return; 357 } 358 359 base = pci_resource_start(dev, bar); 360 len = pci_resource_len(dev, bar); 361 p = ioremap_nocache(base, len); 362 if (p == NULL) 363 return; 364 365 /* Disable the CPU Interrupt */ 366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 367 iounmap(p); 368 } 369 370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 371 static int 372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 373 struct uart_8250_port *port, int idx) 374 { 375 unsigned int bar, offset = board->first_offset; 376 377 bar = 0; 378 379 if (idx < 4) { 380 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 381 offset += idx * board->uart_offset; 382 } else if (idx < 8) { 383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 384 offset += idx * board->uart_offset + 0xC00; 385 } else /* we have only 8 ports on PMC-OCTALPRO */ 386 return 1; 387 388 return setup_port(priv, port, bar, offset, board->reg_shift); 389 } 390 391 /* 392 * This does initialization for PMC OCTALPRO cards: 393 * maps the device memory, resets the UARTs (needed, bc 394 * if the module is removed and inserted again, the card 395 * is in the sleep mode) and enables global interrupt. 396 */ 397 398 /* global control register offset for SBS PMC-OctalPro */ 399 #define OCT_REG_CR_OFF 0x500 400 401 static int sbs_init(struct pci_dev *dev) 402 { 403 u8 __iomem *p; 404 405 p = pci_ioremap_bar(dev, 0); 406 407 if (p == NULL) 408 return -ENOMEM; 409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 410 writeb(0x10, p + OCT_REG_CR_OFF); 411 udelay(50); 412 writeb(0x0, p + OCT_REG_CR_OFF); 413 414 /* Set bit-2 (INTENABLE) of Control Register */ 415 writeb(0x4, p + OCT_REG_CR_OFF); 416 iounmap(p); 417 418 return 0; 419 } 420 421 /* 422 * Disables the global interrupt of PMC-OctalPro 423 */ 424 425 static void sbs_exit(struct pci_dev *dev) 426 { 427 u8 __iomem *p; 428 429 p = pci_ioremap_bar(dev, 0); 430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 431 if (p != NULL) 432 writeb(0, p + OCT_REG_CR_OFF); 433 iounmap(p); 434 } 435 436 /* 437 * SIIG serial cards have an PCI interface chip which also controls 438 * the UART clocking frequency. Each UART can be clocked independently 439 * (except cards equipped with 4 UARTs) and initial clocking settings 440 * are stored in the EEPROM chip. It can cause problems because this 441 * version of serial driver doesn't support differently clocked UART's 442 * on single PCI card. To prevent this, initialization functions set 443 * high frequency clocking for all UART's on given card. It is safe (I 444 * hope) because it doesn't touch EEPROM settings to prevent conflicts 445 * with other OSes (like M$ DOS). 446 * 447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 448 * 449 * There is two family of SIIG serial cards with different PCI 450 * interface chip and different configuration methods: 451 * - 10x cards have control registers in IO and/or memory space; 452 * - 20x cards have control registers in standard PCI configuration space. 453 * 454 * Note: all 10x cards have PCI device ids 0x10.. 455 * all 20x cards have PCI device ids 0x20.. 456 * 457 * There are also Quartet Serial cards which use Oxford Semiconductor 458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 459 * 460 * Note: some SIIG cards are probed by the parport_serial object. 461 */ 462 463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 465 466 static int pci_siig10x_init(struct pci_dev *dev) 467 { 468 u16 data; 469 void __iomem *p; 470 471 switch (dev->device & 0xfff8) { 472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 473 data = 0xffdf; 474 break; 475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 476 data = 0xf7ff; 477 break; 478 default: /* 1S1P, 4S */ 479 data = 0xfffb; 480 break; 481 } 482 483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 484 if (p == NULL) 485 return -ENOMEM; 486 487 writew(readw(p + 0x28) & data, p + 0x28); 488 readw(p + 0x28); 489 iounmap(p); 490 return 0; 491 } 492 493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 495 496 static int pci_siig20x_init(struct pci_dev *dev) 497 { 498 u8 data; 499 500 /* Change clock frequency for the first UART. */ 501 pci_read_config_byte(dev, 0x6f, &data); 502 pci_write_config_byte(dev, 0x6f, data & 0xef); 503 504 /* If this card has 2 UART, we have to do the same with second UART. */ 505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 507 pci_read_config_byte(dev, 0x73, &data); 508 pci_write_config_byte(dev, 0x73, data & 0xef); 509 } 510 return 0; 511 } 512 513 static int pci_siig_init(struct pci_dev *dev) 514 { 515 unsigned int type = dev->device & 0xff00; 516 517 if (type == 0x1000) 518 return pci_siig10x_init(dev); 519 else if (type == 0x2000) 520 return pci_siig20x_init(dev); 521 522 moan_device("Unknown SIIG card", dev); 523 return -ENODEV; 524 } 525 526 static int pci_siig_setup(struct serial_private *priv, 527 const struct pciserial_board *board, 528 struct uart_8250_port *port, int idx) 529 { 530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 531 532 if (idx > 3) { 533 bar = 4; 534 offset = (idx - 4) * 8; 535 } 536 537 return setup_port(priv, port, bar, offset, 0); 538 } 539 540 /* 541 * Timedia has an explosion of boards, and to avoid the PCI table from 542 * growing *huge*, we use this function to collapse some 70 entries 543 * in the PCI table into one, for sanity's and compactness's sake. 544 */ 545 static const unsigned short timedia_single_port[] = { 546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 547 }; 548 549 static const unsigned short timedia_dual_port[] = { 550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 554 0xD079, 0 555 }; 556 557 static const unsigned short timedia_quad_port[] = { 558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 561 0xB157, 0 562 }; 563 564 static const unsigned short timedia_eight_port[] = { 565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 567 }; 568 569 static const struct timedia_struct { 570 int num; 571 const unsigned short *ids; 572 } timedia_data[] = { 573 { 1, timedia_single_port }, 574 { 2, timedia_dual_port }, 575 { 4, timedia_quad_port }, 576 { 8, timedia_eight_port } 577 }; 578 579 /* 580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 581 * listing them individually, this driver merely grabs them all with 582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 583 * and should be left free to be claimed by parport_serial instead. 584 */ 585 static int pci_timedia_probe(struct pci_dev *dev) 586 { 587 /* 588 * Check the third digit of the subdevice ID 589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 590 */ 591 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 592 dev_info(&dev->dev, 593 "ignoring Timedia subdevice %04x for parport_serial\n", 594 dev->subsystem_device); 595 return -ENODEV; 596 } 597 598 return 0; 599 } 600 601 static int pci_timedia_init(struct pci_dev *dev) 602 { 603 const unsigned short *ids; 604 int i, j; 605 606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 607 ids = timedia_data[i].ids; 608 for (j = 0; ids[j]; j++) 609 if (dev->subsystem_device == ids[j]) 610 return timedia_data[i].num; 611 } 612 return 0; 613 } 614 615 /* 616 * Timedia/SUNIX uses a mixture of BARs and offsets 617 * Ugh, this is ugly as all hell --- TYT 618 */ 619 static int 620 pci_timedia_setup(struct serial_private *priv, 621 const struct pciserial_board *board, 622 struct uart_8250_port *port, int idx) 623 { 624 unsigned int bar = 0, offset = board->first_offset; 625 626 switch (idx) { 627 case 0: 628 bar = 0; 629 break; 630 case 1: 631 offset = board->uart_offset; 632 bar = 0; 633 break; 634 case 2: 635 bar = 1; 636 break; 637 case 3: 638 offset = board->uart_offset; 639 /* FALLTHROUGH */ 640 case 4: /* BAR 2 */ 641 case 5: /* BAR 3 */ 642 case 6: /* BAR 4 */ 643 case 7: /* BAR 5 */ 644 bar = idx - 2; 645 } 646 647 return setup_port(priv, port, bar, offset, board->reg_shift); 648 } 649 650 /* 651 * Some Titan cards are also a little weird 652 */ 653 static int 654 titan_400l_800l_setup(struct serial_private *priv, 655 const struct pciserial_board *board, 656 struct uart_8250_port *port, int idx) 657 { 658 unsigned int bar, offset = board->first_offset; 659 660 switch (idx) { 661 case 0: 662 bar = 1; 663 break; 664 case 1: 665 bar = 2; 666 break; 667 default: 668 bar = 4; 669 offset = (idx - 2) * board->uart_offset; 670 } 671 672 return setup_port(priv, port, bar, offset, board->reg_shift); 673 } 674 675 static int pci_xircom_init(struct pci_dev *dev) 676 { 677 msleep(100); 678 return 0; 679 } 680 681 static int pci_ni8420_init(struct pci_dev *dev) 682 { 683 void __iomem *p; 684 unsigned long base, len; 685 unsigned int bar = 0; 686 687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 688 moan_device("no memory in bar", dev); 689 return 0; 690 } 691 692 base = pci_resource_start(dev, bar); 693 len = pci_resource_len(dev, bar); 694 p = ioremap_nocache(base, len); 695 if (p == NULL) 696 return -ENOMEM; 697 698 /* Enable CPU Interrupt */ 699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 700 p + NI8420_INT_ENABLE_REG); 701 702 iounmap(p); 703 return 0; 704 } 705 706 #define MITE_IOWBSR1_WSIZE 0xa 707 #define MITE_IOWBSR1_WIN_OFFSET 0x800 708 #define MITE_IOWBSR1_WENAB (1 << 7) 709 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 712 713 static int pci_ni8430_init(struct pci_dev *dev) 714 { 715 void __iomem *p; 716 unsigned long base, len; 717 u32 device_window; 718 unsigned int bar = 0; 719 720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 721 moan_device("no memory in bar", dev); 722 return 0; 723 } 724 725 base = pci_resource_start(dev, bar); 726 len = pci_resource_len(dev, bar); 727 p = ioremap_nocache(base, len); 728 if (p == NULL) 729 return -ENOMEM; 730 731 /* Set device window address and size in BAR0 */ 732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 734 writel(device_window, p + MITE_IOWBSR1); 735 736 /* Set window access to go to RAMSEL IO address space */ 737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 738 p + MITE_IOWCR1); 739 740 /* Enable IO Bus Interrupt 0 */ 741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 742 743 /* Enable CPU Interrupt */ 744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 745 746 iounmap(p); 747 return 0; 748 } 749 750 /* UART Port Control Register */ 751 #define NI8430_PORTCON 0x0f 752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 753 754 static int 755 pci_ni8430_setup(struct serial_private *priv, 756 const struct pciserial_board *board, 757 struct uart_8250_port *port, int idx) 758 { 759 void __iomem *p; 760 unsigned long base, len; 761 unsigned int bar, offset = board->first_offset; 762 763 if (idx >= board->num_ports) 764 return 1; 765 766 bar = FL_GET_BASE(board->flags); 767 offset += idx * board->uart_offset; 768 769 base = pci_resource_start(priv->dev, bar); 770 len = pci_resource_len(priv->dev, bar); 771 p = ioremap_nocache(base, len); 772 773 /* enable the transceiver */ 774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 775 p + offset + NI8430_PORTCON); 776 777 iounmap(p); 778 779 return setup_port(priv, port, bar, offset, board->reg_shift); 780 } 781 782 static int pci_netmos_9900_setup(struct serial_private *priv, 783 const struct pciserial_board *board, 784 struct uart_8250_port *port, int idx) 785 { 786 unsigned int bar; 787 788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) { 789 /* netmos apparently orders BARs by datasheet layout, so serial 790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 791 */ 792 bar = 3 * idx; 793 794 return setup_port(priv, port, bar, 0, board->reg_shift); 795 } else { 796 return pci_default_setup(priv, board, port, idx); 797 } 798 } 799 800 /* the 99xx series comes with a range of device IDs and a variety 801 * of capabilities: 802 * 803 * 9900 has varying capabilities and can cascade to sub-controllers 804 * (cascading should be purely internal) 805 * 9904 is hardwired with 4 serial ports 806 * 9912 and 9922 are hardwired with 2 serial ports 807 */ 808 static int pci_netmos_9900_numports(struct pci_dev *dev) 809 { 810 unsigned int c = dev->class; 811 unsigned int pi; 812 unsigned short sub_serports; 813 814 pi = (c & 0xff); 815 816 if (pi == 2) { 817 return 1; 818 } else if ((pi == 0) && 819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 820 /* two possibilities: 0x30ps encodes number of parallel and 821 * serial ports, or 0x1000 indicates *something*. This is not 822 * immediately obvious, since the 2s1p+4s configuration seems 823 * to offer all functionality on functions 0..2, while still 824 * advertising the same function 3 as the 4s+2s1p config. 825 */ 826 sub_serports = dev->subsystem_device & 0xf; 827 if (sub_serports > 0) { 828 return sub_serports; 829 } else { 830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 831 return 0; 832 } 833 } 834 835 moan_device("unknown NetMos/Mostech program interface", dev); 836 return 0; 837 } 838 839 static int pci_netmos_init(struct pci_dev *dev) 840 { 841 /* subdevice 0x00PS means <P> parallel, <S> serial */ 842 unsigned int num_serial = dev->subsystem_device & 0xf; 843 844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 845 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 846 return 0; 847 848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 849 dev->subsystem_device == 0x0299) 850 return 0; 851 852 switch (dev->device) { /* FALLTHROUGH on all */ 853 case PCI_DEVICE_ID_NETMOS_9904: 854 case PCI_DEVICE_ID_NETMOS_9912: 855 case PCI_DEVICE_ID_NETMOS_9922: 856 case PCI_DEVICE_ID_NETMOS_9900: 857 num_serial = pci_netmos_9900_numports(dev); 858 break; 859 860 default: 861 if (num_serial == 0 ) { 862 moan_device("unknown NetMos/Mostech device", dev); 863 } 864 } 865 866 if (num_serial == 0) 867 return -ENODEV; 868 869 return num_serial; 870 } 871 872 /* 873 * These chips are available with optionally one parallel port and up to 874 * two serial ports. Unfortunately they all have the same product id. 875 * 876 * Basic configuration is done over a region of 32 I/O ports. The base 877 * ioport is called INTA or INTC, depending on docs/other drivers. 878 * 879 * The region of the 32 I/O ports is configured in POSIO0R... 880 */ 881 882 /* registers */ 883 #define ITE_887x_MISCR 0x9c 884 #define ITE_887x_INTCBAR 0x78 885 #define ITE_887x_UARTBAR 0x7c 886 #define ITE_887x_PS0BAR 0x10 887 #define ITE_887x_POSIO0 0x60 888 889 /* I/O space size */ 890 #define ITE_887x_IOSIZE 32 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 896 #define ITE_887x_POSIO_SPEED (3 << 29) 897 /* enable IO_Space bit */ 898 #define ITE_887x_POSIO_ENABLE (1 << 31) 899 900 static int pci_ite887x_init(struct pci_dev *dev) 901 { 902 /* inta_addr are the configuration addresses of the ITE */ 903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 904 0x200, 0x280, 0 }; 905 int ret, i, type; 906 struct resource *iobase = NULL; 907 u32 miscr, uartbar, ioport; 908 909 /* search for the base-ioport */ 910 i = 0; 911 while (inta_addr[i] && iobase == NULL) { 912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 913 "ite887x"); 914 if (iobase != NULL) { 915 /* write POSIO0R - speed | size | ioport */ 916 pci_write_config_dword(dev, ITE_887x_POSIO0, 917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 919 /* write INTCBAR - ioport */ 920 pci_write_config_dword(dev, ITE_887x_INTCBAR, 921 inta_addr[i]); 922 ret = inb(inta_addr[i]); 923 if (ret != 0xff) { 924 /* ioport connected */ 925 break; 926 } 927 release_region(iobase->start, ITE_887x_IOSIZE); 928 iobase = NULL; 929 } 930 i++; 931 } 932 933 if (!inta_addr[i]) { 934 printk(KERN_ERR "ite887x: could not find iobase\n"); 935 return -ENODEV; 936 } 937 938 /* start of undocumented type checking (see parport_pc.c) */ 939 type = inb(iobase->start + 0x18) & 0x0f; 940 941 switch (type) { 942 case 0x2: /* ITE8871 (1P) */ 943 case 0xa: /* ITE8875 (1P) */ 944 ret = 0; 945 break; 946 case 0xe: /* ITE8872 (2S1P) */ 947 ret = 2; 948 break; 949 case 0x6: /* ITE8873 (1S) */ 950 ret = 1; 951 break; 952 case 0x8: /* ITE8874 (2S) */ 953 ret = 2; 954 break; 955 default: 956 moan_device("Unknown ITE887x", dev); 957 ret = -ENODEV; 958 } 959 960 /* configure all serial ports */ 961 for (i = 0; i < ret; i++) { 962 /* read the I/O port from the device */ 963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 964 &ioport); 965 ioport &= 0x0000FF00; /* the actual base address */ 966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 968 ITE_887x_POSIO_IOSIZE_8 | ioport); 969 970 /* write the ioport to the UARTBAR */ 971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 973 uartbar |= (ioport << (16 * i)); /* set the ioport */ 974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 975 976 /* get current config */ 977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 978 /* disable interrupts (UARTx_Routing[3:0]) */ 979 miscr &= ~(0xf << (12 - 4 * i)); 980 /* activate the UART (UARTx_En) */ 981 miscr |= 1 << (23 - i); 982 /* write new config with activated UART */ 983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 984 } 985 986 if (ret <= 0) { 987 /* the device has no UARTs if we get here */ 988 release_region(iobase->start, ITE_887x_IOSIZE); 989 } 990 991 return ret; 992 } 993 994 static void pci_ite887x_exit(struct pci_dev *dev) 995 { 996 u32 ioport; 997 /* the ioport is bit 0-15 in POSIO0R */ 998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 999 ioport &= 0xffff; 1000 release_region(ioport, ITE_887x_IOSIZE); 1001 } 1002 1003 /* 1004 * Oxford Semiconductor Inc. 1005 * Check that device is part of the Tornado range of devices, then determine 1006 * the number of ports available on the device. 1007 */ 1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1009 { 1010 u8 __iomem *p; 1011 unsigned long deviceID; 1012 unsigned int number_uarts = 0; 1013 1014 /* OxSemi Tornado devices are all 0xCxxx */ 1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1016 (dev->device & 0xF000) != 0xC000) 1017 return 0; 1018 1019 p = pci_iomap(dev, 0, 5); 1020 if (p == NULL) 1021 return -ENOMEM; 1022 1023 deviceID = ioread32(p); 1024 /* Tornado device */ 1025 if (deviceID == 0x07000200) { 1026 number_uarts = ioread8(p + 4); 1027 printk(KERN_DEBUG 1028 "%d ports detected on Oxford PCI Express device\n", 1029 number_uarts); 1030 } 1031 pci_iounmap(dev, p); 1032 return number_uarts; 1033 } 1034 1035 static int pci_asix_setup(struct serial_private *priv, 1036 const struct pciserial_board *board, 1037 struct uart_8250_port *port, int idx) 1038 { 1039 port->bugs |= UART_BUG_PARITY; 1040 return pci_default_setup(priv, board, port, idx); 1041 } 1042 1043 static int pci_default_setup(struct serial_private *priv, 1044 const struct pciserial_board *board, 1045 struct uart_8250_port *port, int idx) 1046 { 1047 unsigned int bar, offset = board->first_offset, maxnr; 1048 1049 bar = FL_GET_BASE(board->flags); 1050 if (board->flags & FL_BASE_BARS) 1051 bar += idx; 1052 else 1053 offset += idx * board->uart_offset; 1054 1055 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1056 (board->reg_shift + 3); 1057 1058 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1059 return 1; 1060 1061 return setup_port(priv, port, bar, offset, board->reg_shift); 1062 } 1063 1064 static int 1065 ce4100_serial_setup(struct serial_private *priv, 1066 const struct pciserial_board *board, 1067 struct uart_8250_port *port, int idx) 1068 { 1069 int ret; 1070 1071 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1072 port->port.iotype = UPIO_MEM32; 1073 port->port.type = PORT_XSCALE; 1074 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1075 port->port.regshift = 2; 1076 1077 return ret; 1078 } 1079 1080 static int 1081 pci_omegapci_setup(struct serial_private *priv, 1082 const struct pciserial_board *board, 1083 struct uart_8250_port *port, int idx) 1084 { 1085 return setup_port(priv, port, 2, idx * 8, 0); 1086 } 1087 1088 static int 1089 pci_brcm_trumanage_setup(struct serial_private *priv, 1090 const struct pciserial_board *board, 1091 struct uart_8250_port *port, int idx) 1092 { 1093 int ret = pci_default_setup(priv, board, port, idx); 1094 1095 port->port.type = PORT_BRCM_TRUMANAGE; 1096 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1097 return ret; 1098 } 1099 1100 static int skip_tx_en_setup(struct serial_private *priv, 1101 const struct pciserial_board *board, 1102 struct uart_8250_port *port, int idx) 1103 { 1104 port->port.flags |= UPF_NO_TXEN_TEST; 1105 printk(KERN_DEBUG "serial8250: skipping TxEn test for device " 1106 "[%04x:%04x] subsystem [%04x:%04x]\n", 1107 priv->dev->vendor, 1108 priv->dev->device, 1109 priv->dev->subsystem_vendor, 1110 priv->dev->subsystem_device); 1111 1112 return pci_default_setup(priv, board, port, idx); 1113 } 1114 1115 static void kt_handle_break(struct uart_port *p) 1116 { 1117 struct uart_8250_port *up = 1118 container_of(p, struct uart_8250_port, port); 1119 /* 1120 * On receipt of a BI, serial device in Intel ME (Intel 1121 * management engine) needs to have its fifos cleared for sane 1122 * SOL (Serial Over Lan) output. 1123 */ 1124 serial8250_clear_and_reinit_fifos(up); 1125 } 1126 1127 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1128 { 1129 struct uart_8250_port *up = 1130 container_of(p, struct uart_8250_port, port); 1131 unsigned int val; 1132 1133 /* 1134 * When the Intel ME (management engine) gets reset its serial 1135 * port registers could return 0 momentarily. Functions like 1136 * serial8250_console_write, read and save the IER, perform 1137 * some operation and then restore it. In order to avoid 1138 * setting IER register inadvertently to 0, if the value read 1139 * is 0, double check with ier value in uart_8250_port and use 1140 * that instead. up->ier should be the same value as what is 1141 * currently configured. 1142 */ 1143 val = inb(p->iobase + offset); 1144 if (offset == UART_IER) { 1145 if (val == 0) 1146 val = up->ier; 1147 } 1148 return val; 1149 } 1150 1151 static int kt_serial_setup(struct serial_private *priv, 1152 const struct pciserial_board *board, 1153 struct uart_8250_port *port, int idx) 1154 { 1155 port->port.flags |= UPF_BUG_THRE; 1156 port->port.serial_in = kt_serial_in; 1157 port->port.handle_break = kt_handle_break; 1158 return skip_tx_en_setup(priv, board, port, idx); 1159 } 1160 1161 static int pci_eg20t_init(struct pci_dev *dev) 1162 { 1163 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1164 return -ENODEV; 1165 #else 1166 return 0; 1167 #endif 1168 } 1169 1170 static int 1171 pci_xr17c154_setup(struct serial_private *priv, 1172 const struct pciserial_board *board, 1173 struct uart_8250_port *port, int idx) 1174 { 1175 port->port.flags |= UPF_EXAR_EFR; 1176 return pci_default_setup(priv, board, port, idx); 1177 } 1178 1179 static int 1180 pci_xr17v35x_setup(struct serial_private *priv, 1181 const struct pciserial_board *board, 1182 struct uart_8250_port *port, int idx) 1183 { 1184 u8 __iomem *p; 1185 1186 p = pci_ioremap_bar(priv->dev, 0); 1187 if (p == NULL) 1188 return -ENOMEM; 1189 1190 port->port.flags |= UPF_EXAR_EFR; 1191 1192 /* 1193 * Setup Multipurpose Input/Output pins. 1194 */ 1195 if (idx == 0) { 1196 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1197 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1198 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1199 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1200 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1201 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1202 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1203 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1204 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1205 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1206 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1207 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1208 } 1209 writeb(0x00, p + UART_EXAR_8XMODE); 1210 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1211 writeb(128, p + UART_EXAR_TXTRG); 1212 writeb(128, p + UART_EXAR_RXTRG); 1213 iounmap(p); 1214 1215 return pci_default_setup(priv, board, port, idx); 1216 } 1217 1218 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1219 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1220 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1221 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1222 1223 static int 1224 pci_fastcom335_setup(struct serial_private *priv, 1225 const struct pciserial_board *board, 1226 struct uart_8250_port *port, int idx) 1227 { 1228 u8 __iomem *p; 1229 1230 p = pci_ioremap_bar(priv->dev, 0); 1231 if (p == NULL) 1232 return -ENOMEM; 1233 1234 port->port.flags |= UPF_EXAR_EFR; 1235 1236 /* 1237 * Setup Multipurpose Input/Output pins. 1238 */ 1239 if (idx == 0) { 1240 switch (priv->dev->device) { 1241 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1242 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1243 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1244 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1245 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1246 break; 1247 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1248 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1249 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1250 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1251 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1252 break; 1253 } 1254 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1255 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1256 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1257 } 1258 writeb(0x00, p + UART_EXAR_8XMODE); 1259 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1260 writeb(32, p + UART_EXAR_TXTRG); 1261 writeb(32, p + UART_EXAR_RXTRG); 1262 iounmap(p); 1263 1264 return pci_default_setup(priv, board, port, idx); 1265 } 1266 1267 static int 1268 pci_wch_ch353_setup(struct serial_private *priv, 1269 const struct pciserial_board *board, 1270 struct uart_8250_port *port, int idx) 1271 { 1272 port->port.flags |= UPF_FIXED_TYPE; 1273 port->port.type = PORT_16550A; 1274 return pci_default_setup(priv, board, port, idx); 1275 } 1276 1277 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1278 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1279 #define PCI_DEVICE_ID_OCTPRO 0x0001 1280 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1281 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1282 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1283 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1284 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1285 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1286 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1287 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1288 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1289 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1290 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1291 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1292 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1293 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1294 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1295 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1296 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1297 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1298 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1299 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1300 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1301 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1302 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1303 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1304 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1305 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1306 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1307 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1308 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1309 #define PCI_VENDOR_ID_WCH 0x4348 1310 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1311 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1312 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1313 #define PCI_VENDOR_ID_AGESTAR 0x5372 1314 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1315 #define PCI_VENDOR_ID_ASIX 0x9710 1316 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1317 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1318 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1319 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1320 1321 1322 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1323 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1324 1325 /* 1326 * Master list of serial port init/setup/exit quirks. 1327 * This does not describe the general nature of the port. 1328 * (ie, baud base, number and location of ports, etc) 1329 * 1330 * This list is ordered alphabetically by vendor then device. 1331 * Specific entries must come before more generic entries. 1332 */ 1333 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1334 /* 1335 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1336 */ 1337 { 1338 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD, 1339 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800, 1340 .subvendor = PCI_ANY_ID, 1341 .subdevice = PCI_ANY_ID, 1342 .setup = addidata_apci7800_setup, 1343 }, 1344 /* 1345 * AFAVLAB cards - these may be called via parport_serial 1346 * It is not clear whether this applies to all products. 1347 */ 1348 { 1349 .vendor = PCI_VENDOR_ID_AFAVLAB, 1350 .device = PCI_ANY_ID, 1351 .subvendor = PCI_ANY_ID, 1352 .subdevice = PCI_ANY_ID, 1353 .setup = afavlab_setup, 1354 }, 1355 /* 1356 * HP Diva 1357 */ 1358 { 1359 .vendor = PCI_VENDOR_ID_HP, 1360 .device = PCI_DEVICE_ID_HP_DIVA, 1361 .subvendor = PCI_ANY_ID, 1362 .subdevice = PCI_ANY_ID, 1363 .init = pci_hp_diva_init, 1364 .setup = pci_hp_diva_setup, 1365 }, 1366 /* 1367 * Intel 1368 */ 1369 { 1370 .vendor = PCI_VENDOR_ID_INTEL, 1371 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1372 .subvendor = 0xe4bf, 1373 .subdevice = PCI_ANY_ID, 1374 .init = pci_inteli960ni_init, 1375 .setup = pci_default_setup, 1376 }, 1377 { 1378 .vendor = PCI_VENDOR_ID_INTEL, 1379 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1380 .subvendor = PCI_ANY_ID, 1381 .subdevice = PCI_ANY_ID, 1382 .setup = skip_tx_en_setup, 1383 }, 1384 { 1385 .vendor = PCI_VENDOR_ID_INTEL, 1386 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1387 .subvendor = PCI_ANY_ID, 1388 .subdevice = PCI_ANY_ID, 1389 .setup = skip_tx_en_setup, 1390 }, 1391 { 1392 .vendor = PCI_VENDOR_ID_INTEL, 1393 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1394 .subvendor = PCI_ANY_ID, 1395 .subdevice = PCI_ANY_ID, 1396 .setup = skip_tx_en_setup, 1397 }, 1398 { 1399 .vendor = PCI_VENDOR_ID_INTEL, 1400 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1401 .subvendor = PCI_ANY_ID, 1402 .subdevice = PCI_ANY_ID, 1403 .setup = ce4100_serial_setup, 1404 }, 1405 { 1406 .vendor = PCI_VENDOR_ID_INTEL, 1407 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1408 .subvendor = PCI_ANY_ID, 1409 .subdevice = PCI_ANY_ID, 1410 .setup = kt_serial_setup, 1411 }, 1412 /* 1413 * ITE 1414 */ 1415 { 1416 .vendor = PCI_VENDOR_ID_ITE, 1417 .device = PCI_DEVICE_ID_ITE_8872, 1418 .subvendor = PCI_ANY_ID, 1419 .subdevice = PCI_ANY_ID, 1420 .init = pci_ite887x_init, 1421 .setup = pci_default_setup, 1422 .exit = pci_ite887x_exit, 1423 }, 1424 /* 1425 * National Instruments 1426 */ 1427 { 1428 .vendor = PCI_VENDOR_ID_NI, 1429 .device = PCI_DEVICE_ID_NI_PCI23216, 1430 .subvendor = PCI_ANY_ID, 1431 .subdevice = PCI_ANY_ID, 1432 .init = pci_ni8420_init, 1433 .setup = pci_default_setup, 1434 .exit = pci_ni8420_exit, 1435 }, 1436 { 1437 .vendor = PCI_VENDOR_ID_NI, 1438 .device = PCI_DEVICE_ID_NI_PCI2328, 1439 .subvendor = PCI_ANY_ID, 1440 .subdevice = PCI_ANY_ID, 1441 .init = pci_ni8420_init, 1442 .setup = pci_default_setup, 1443 .exit = pci_ni8420_exit, 1444 }, 1445 { 1446 .vendor = PCI_VENDOR_ID_NI, 1447 .device = PCI_DEVICE_ID_NI_PCI2324, 1448 .subvendor = PCI_ANY_ID, 1449 .subdevice = PCI_ANY_ID, 1450 .init = pci_ni8420_init, 1451 .setup = pci_default_setup, 1452 .exit = pci_ni8420_exit, 1453 }, 1454 { 1455 .vendor = PCI_VENDOR_ID_NI, 1456 .device = PCI_DEVICE_ID_NI_PCI2322, 1457 .subvendor = PCI_ANY_ID, 1458 .subdevice = PCI_ANY_ID, 1459 .init = pci_ni8420_init, 1460 .setup = pci_default_setup, 1461 .exit = pci_ni8420_exit, 1462 }, 1463 { 1464 .vendor = PCI_VENDOR_ID_NI, 1465 .device = PCI_DEVICE_ID_NI_PCI2324I, 1466 .subvendor = PCI_ANY_ID, 1467 .subdevice = PCI_ANY_ID, 1468 .init = pci_ni8420_init, 1469 .setup = pci_default_setup, 1470 .exit = pci_ni8420_exit, 1471 }, 1472 { 1473 .vendor = PCI_VENDOR_ID_NI, 1474 .device = PCI_DEVICE_ID_NI_PCI2322I, 1475 .subvendor = PCI_ANY_ID, 1476 .subdevice = PCI_ANY_ID, 1477 .init = pci_ni8420_init, 1478 .setup = pci_default_setup, 1479 .exit = pci_ni8420_exit, 1480 }, 1481 { 1482 .vendor = PCI_VENDOR_ID_NI, 1483 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1484 .subvendor = PCI_ANY_ID, 1485 .subdevice = PCI_ANY_ID, 1486 .init = pci_ni8420_init, 1487 .setup = pci_default_setup, 1488 .exit = pci_ni8420_exit, 1489 }, 1490 { 1491 .vendor = PCI_VENDOR_ID_NI, 1492 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 1493 .subvendor = PCI_ANY_ID, 1494 .subdevice = PCI_ANY_ID, 1495 .init = pci_ni8420_init, 1496 .setup = pci_default_setup, 1497 .exit = pci_ni8420_exit, 1498 }, 1499 { 1500 .vendor = PCI_VENDOR_ID_NI, 1501 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 1502 .subvendor = PCI_ANY_ID, 1503 .subdevice = PCI_ANY_ID, 1504 .init = pci_ni8420_init, 1505 .setup = pci_default_setup, 1506 .exit = pci_ni8420_exit, 1507 }, 1508 { 1509 .vendor = PCI_VENDOR_ID_NI, 1510 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 1511 .subvendor = PCI_ANY_ID, 1512 .subdevice = PCI_ANY_ID, 1513 .init = pci_ni8420_init, 1514 .setup = pci_default_setup, 1515 .exit = pci_ni8420_exit, 1516 }, 1517 { 1518 .vendor = PCI_VENDOR_ID_NI, 1519 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 1520 .subvendor = PCI_ANY_ID, 1521 .subdevice = PCI_ANY_ID, 1522 .init = pci_ni8420_init, 1523 .setup = pci_default_setup, 1524 .exit = pci_ni8420_exit, 1525 }, 1526 { 1527 .vendor = PCI_VENDOR_ID_NI, 1528 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 1529 .subvendor = PCI_ANY_ID, 1530 .subdevice = PCI_ANY_ID, 1531 .init = pci_ni8420_init, 1532 .setup = pci_default_setup, 1533 .exit = pci_ni8420_exit, 1534 }, 1535 { 1536 .vendor = PCI_VENDOR_ID_NI, 1537 .device = PCI_ANY_ID, 1538 .subvendor = PCI_ANY_ID, 1539 .subdevice = PCI_ANY_ID, 1540 .init = pci_ni8430_init, 1541 .setup = pci_ni8430_setup, 1542 .exit = pci_ni8430_exit, 1543 }, 1544 /* 1545 * Panacom 1546 */ 1547 { 1548 .vendor = PCI_VENDOR_ID_PANACOM, 1549 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 1550 .subvendor = PCI_ANY_ID, 1551 .subdevice = PCI_ANY_ID, 1552 .init = pci_plx9050_init, 1553 .setup = pci_default_setup, 1554 .exit = pci_plx9050_exit, 1555 }, 1556 { 1557 .vendor = PCI_VENDOR_ID_PANACOM, 1558 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 1559 .subvendor = PCI_ANY_ID, 1560 .subdevice = PCI_ANY_ID, 1561 .init = pci_plx9050_init, 1562 .setup = pci_default_setup, 1563 .exit = pci_plx9050_exit, 1564 }, 1565 /* 1566 * PLX 1567 */ 1568 { 1569 .vendor = PCI_VENDOR_ID_PLX, 1570 .device = PCI_DEVICE_ID_PLX_9030, 1571 .subvendor = PCI_SUBVENDOR_ID_PERLE, 1572 .subdevice = PCI_ANY_ID, 1573 .setup = pci_default_setup, 1574 }, 1575 { 1576 .vendor = PCI_VENDOR_ID_PLX, 1577 .device = PCI_DEVICE_ID_PLX_9050, 1578 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 1579 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 1580 .init = pci_plx9050_init, 1581 .setup = pci_default_setup, 1582 .exit = pci_plx9050_exit, 1583 }, 1584 { 1585 .vendor = PCI_VENDOR_ID_PLX, 1586 .device = PCI_DEVICE_ID_PLX_9050, 1587 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 1588 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 1589 .init = pci_plx9050_init, 1590 .setup = pci_default_setup, 1591 .exit = pci_plx9050_exit, 1592 }, 1593 { 1594 .vendor = PCI_VENDOR_ID_PLX, 1595 .device = PCI_DEVICE_ID_PLX_9050, 1596 .subvendor = PCI_VENDOR_ID_PLX, 1597 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 1598 .init = pci_plx9050_init, 1599 .setup = pci_default_setup, 1600 .exit = pci_plx9050_exit, 1601 }, 1602 { 1603 .vendor = PCI_VENDOR_ID_PLX, 1604 .device = PCI_DEVICE_ID_PLX_ROMULUS, 1605 .subvendor = PCI_VENDOR_ID_PLX, 1606 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 1607 .init = pci_plx9050_init, 1608 .setup = pci_default_setup, 1609 .exit = pci_plx9050_exit, 1610 }, 1611 /* 1612 * SBS Technologies, Inc., PMC-OCTALPRO 232 1613 */ 1614 { 1615 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 1616 .device = PCI_DEVICE_ID_OCTPRO, 1617 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 1618 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 1619 .init = sbs_init, 1620 .setup = sbs_setup, 1621 .exit = sbs_exit, 1622 }, 1623 /* 1624 * SBS Technologies, Inc., PMC-OCTALPRO 422 1625 */ 1626 { 1627 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 1628 .device = PCI_DEVICE_ID_OCTPRO, 1629 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 1630 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 1631 .init = sbs_init, 1632 .setup = sbs_setup, 1633 .exit = sbs_exit, 1634 }, 1635 /* 1636 * SBS Technologies, Inc., P-Octal 232 1637 */ 1638 { 1639 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 1640 .device = PCI_DEVICE_ID_OCTPRO, 1641 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 1642 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 1643 .init = sbs_init, 1644 .setup = sbs_setup, 1645 .exit = sbs_exit, 1646 }, 1647 /* 1648 * SBS Technologies, Inc., P-Octal 422 1649 */ 1650 { 1651 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 1652 .device = PCI_DEVICE_ID_OCTPRO, 1653 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 1654 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 1655 .init = sbs_init, 1656 .setup = sbs_setup, 1657 .exit = sbs_exit, 1658 }, 1659 /* 1660 * SIIG cards - these may be called via parport_serial 1661 */ 1662 { 1663 .vendor = PCI_VENDOR_ID_SIIG, 1664 .device = PCI_ANY_ID, 1665 .subvendor = PCI_ANY_ID, 1666 .subdevice = PCI_ANY_ID, 1667 .init = pci_siig_init, 1668 .setup = pci_siig_setup, 1669 }, 1670 /* 1671 * Titan cards 1672 */ 1673 { 1674 .vendor = PCI_VENDOR_ID_TITAN, 1675 .device = PCI_DEVICE_ID_TITAN_400L, 1676 .subvendor = PCI_ANY_ID, 1677 .subdevice = PCI_ANY_ID, 1678 .setup = titan_400l_800l_setup, 1679 }, 1680 { 1681 .vendor = PCI_VENDOR_ID_TITAN, 1682 .device = PCI_DEVICE_ID_TITAN_800L, 1683 .subvendor = PCI_ANY_ID, 1684 .subdevice = PCI_ANY_ID, 1685 .setup = titan_400l_800l_setup, 1686 }, 1687 /* 1688 * Timedia cards 1689 */ 1690 { 1691 .vendor = PCI_VENDOR_ID_TIMEDIA, 1692 .device = PCI_DEVICE_ID_TIMEDIA_1889, 1693 .subvendor = PCI_VENDOR_ID_TIMEDIA, 1694 .subdevice = PCI_ANY_ID, 1695 .probe = pci_timedia_probe, 1696 .init = pci_timedia_init, 1697 .setup = pci_timedia_setup, 1698 }, 1699 { 1700 .vendor = PCI_VENDOR_ID_TIMEDIA, 1701 .device = PCI_ANY_ID, 1702 .subvendor = PCI_ANY_ID, 1703 .subdevice = PCI_ANY_ID, 1704 .setup = pci_timedia_setup, 1705 }, 1706 /* 1707 * Exar cards 1708 */ 1709 { 1710 .vendor = PCI_VENDOR_ID_EXAR, 1711 .device = PCI_DEVICE_ID_EXAR_XR17C152, 1712 .subvendor = PCI_ANY_ID, 1713 .subdevice = PCI_ANY_ID, 1714 .setup = pci_xr17c154_setup, 1715 }, 1716 { 1717 .vendor = PCI_VENDOR_ID_EXAR, 1718 .device = PCI_DEVICE_ID_EXAR_XR17C154, 1719 .subvendor = PCI_ANY_ID, 1720 .subdevice = PCI_ANY_ID, 1721 .setup = pci_xr17c154_setup, 1722 }, 1723 { 1724 .vendor = PCI_VENDOR_ID_EXAR, 1725 .device = PCI_DEVICE_ID_EXAR_XR17C158, 1726 .subvendor = PCI_ANY_ID, 1727 .subdevice = PCI_ANY_ID, 1728 .setup = pci_xr17c154_setup, 1729 }, 1730 { 1731 .vendor = PCI_VENDOR_ID_EXAR, 1732 .device = PCI_DEVICE_ID_EXAR_XR17V352, 1733 .subvendor = PCI_ANY_ID, 1734 .subdevice = PCI_ANY_ID, 1735 .setup = pci_xr17v35x_setup, 1736 }, 1737 { 1738 .vendor = PCI_VENDOR_ID_EXAR, 1739 .device = PCI_DEVICE_ID_EXAR_XR17V354, 1740 .subvendor = PCI_ANY_ID, 1741 .subdevice = PCI_ANY_ID, 1742 .setup = pci_xr17v35x_setup, 1743 }, 1744 { 1745 .vendor = PCI_VENDOR_ID_EXAR, 1746 .device = PCI_DEVICE_ID_EXAR_XR17V358, 1747 .subvendor = PCI_ANY_ID, 1748 .subdevice = PCI_ANY_ID, 1749 .setup = pci_xr17v35x_setup, 1750 }, 1751 /* 1752 * Xircom cards 1753 */ 1754 { 1755 .vendor = PCI_VENDOR_ID_XIRCOM, 1756 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 1757 .subvendor = PCI_ANY_ID, 1758 .subdevice = PCI_ANY_ID, 1759 .init = pci_xircom_init, 1760 .setup = pci_default_setup, 1761 }, 1762 /* 1763 * Netmos cards - these may be called via parport_serial 1764 */ 1765 { 1766 .vendor = PCI_VENDOR_ID_NETMOS, 1767 .device = PCI_ANY_ID, 1768 .subvendor = PCI_ANY_ID, 1769 .subdevice = PCI_ANY_ID, 1770 .init = pci_netmos_init, 1771 .setup = pci_netmos_9900_setup, 1772 }, 1773 /* 1774 * For Oxford Semiconductor Tornado based devices 1775 */ 1776 { 1777 .vendor = PCI_VENDOR_ID_OXSEMI, 1778 .device = PCI_ANY_ID, 1779 .subvendor = PCI_ANY_ID, 1780 .subdevice = PCI_ANY_ID, 1781 .init = pci_oxsemi_tornado_init, 1782 .setup = pci_default_setup, 1783 }, 1784 { 1785 .vendor = PCI_VENDOR_ID_MAINPINE, 1786 .device = PCI_ANY_ID, 1787 .subvendor = PCI_ANY_ID, 1788 .subdevice = PCI_ANY_ID, 1789 .init = pci_oxsemi_tornado_init, 1790 .setup = pci_default_setup, 1791 }, 1792 { 1793 .vendor = PCI_VENDOR_ID_DIGI, 1794 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 1795 .subvendor = PCI_SUBVENDOR_ID_IBM, 1796 .subdevice = PCI_ANY_ID, 1797 .init = pci_oxsemi_tornado_init, 1798 .setup = pci_default_setup, 1799 }, 1800 { 1801 .vendor = PCI_VENDOR_ID_INTEL, 1802 .device = 0x8811, 1803 .subvendor = PCI_ANY_ID, 1804 .subdevice = PCI_ANY_ID, 1805 .init = pci_eg20t_init, 1806 .setup = pci_default_setup, 1807 }, 1808 { 1809 .vendor = PCI_VENDOR_ID_INTEL, 1810 .device = 0x8812, 1811 .subvendor = PCI_ANY_ID, 1812 .subdevice = PCI_ANY_ID, 1813 .init = pci_eg20t_init, 1814 .setup = pci_default_setup, 1815 }, 1816 { 1817 .vendor = PCI_VENDOR_ID_INTEL, 1818 .device = 0x8813, 1819 .subvendor = PCI_ANY_ID, 1820 .subdevice = PCI_ANY_ID, 1821 .init = pci_eg20t_init, 1822 .setup = pci_default_setup, 1823 }, 1824 { 1825 .vendor = PCI_VENDOR_ID_INTEL, 1826 .device = 0x8814, 1827 .subvendor = PCI_ANY_ID, 1828 .subdevice = PCI_ANY_ID, 1829 .init = pci_eg20t_init, 1830 .setup = pci_default_setup, 1831 }, 1832 { 1833 .vendor = 0x10DB, 1834 .device = 0x8027, 1835 .subvendor = PCI_ANY_ID, 1836 .subdevice = PCI_ANY_ID, 1837 .init = pci_eg20t_init, 1838 .setup = pci_default_setup, 1839 }, 1840 { 1841 .vendor = 0x10DB, 1842 .device = 0x8028, 1843 .subvendor = PCI_ANY_ID, 1844 .subdevice = PCI_ANY_ID, 1845 .init = pci_eg20t_init, 1846 .setup = pci_default_setup, 1847 }, 1848 { 1849 .vendor = 0x10DB, 1850 .device = 0x8029, 1851 .subvendor = PCI_ANY_ID, 1852 .subdevice = PCI_ANY_ID, 1853 .init = pci_eg20t_init, 1854 .setup = pci_default_setup, 1855 }, 1856 { 1857 .vendor = 0x10DB, 1858 .device = 0x800C, 1859 .subvendor = PCI_ANY_ID, 1860 .subdevice = PCI_ANY_ID, 1861 .init = pci_eg20t_init, 1862 .setup = pci_default_setup, 1863 }, 1864 { 1865 .vendor = 0x10DB, 1866 .device = 0x800D, 1867 .subvendor = PCI_ANY_ID, 1868 .subdevice = PCI_ANY_ID, 1869 .init = pci_eg20t_init, 1870 .setup = pci_default_setup, 1871 }, 1872 /* 1873 * Cronyx Omega PCI (PLX-chip based) 1874 */ 1875 { 1876 .vendor = PCI_VENDOR_ID_PLX, 1877 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 1878 .subvendor = PCI_ANY_ID, 1879 .subdevice = PCI_ANY_ID, 1880 .setup = pci_omegapci_setup, 1881 }, 1882 /* WCH CH353 2S1P card (16550 clone) */ 1883 { 1884 .vendor = PCI_VENDOR_ID_WCH, 1885 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 1886 .subvendor = PCI_ANY_ID, 1887 .subdevice = PCI_ANY_ID, 1888 .setup = pci_wch_ch353_setup, 1889 }, 1890 /* WCH CH353 4S card (16550 clone) */ 1891 { 1892 .vendor = PCI_VENDOR_ID_WCH, 1893 .device = PCI_DEVICE_ID_WCH_CH353_4S, 1894 .subvendor = PCI_ANY_ID, 1895 .subdevice = PCI_ANY_ID, 1896 .setup = pci_wch_ch353_setup, 1897 }, 1898 /* WCH CH353 2S1PF card (16550 clone) */ 1899 { 1900 .vendor = PCI_VENDOR_ID_WCH, 1901 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 1902 .subvendor = PCI_ANY_ID, 1903 .subdevice = PCI_ANY_ID, 1904 .setup = pci_wch_ch353_setup, 1905 }, 1906 /* 1907 * ASIX devices with FIFO bug 1908 */ 1909 { 1910 .vendor = PCI_VENDOR_ID_ASIX, 1911 .device = PCI_ANY_ID, 1912 .subvendor = PCI_ANY_ID, 1913 .subdevice = PCI_ANY_ID, 1914 .setup = pci_asix_setup, 1915 }, 1916 /* 1917 * Commtech, Inc. Fastcom adapters 1918 * 1919 */ 1920 { 1921 .vendor = PCI_VENDOR_ID_COMMTECH, 1922 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 1923 .subvendor = PCI_ANY_ID, 1924 .subdevice = PCI_ANY_ID, 1925 .setup = pci_fastcom335_setup, 1926 }, 1927 { 1928 .vendor = PCI_VENDOR_ID_COMMTECH, 1929 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 1930 .subvendor = PCI_ANY_ID, 1931 .subdevice = PCI_ANY_ID, 1932 .setup = pci_fastcom335_setup, 1933 }, 1934 { 1935 .vendor = PCI_VENDOR_ID_COMMTECH, 1936 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 1937 .subvendor = PCI_ANY_ID, 1938 .subdevice = PCI_ANY_ID, 1939 .setup = pci_fastcom335_setup, 1940 }, 1941 { 1942 .vendor = PCI_VENDOR_ID_COMMTECH, 1943 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 1944 .subvendor = PCI_ANY_ID, 1945 .subdevice = PCI_ANY_ID, 1946 .setup = pci_fastcom335_setup, 1947 }, 1948 { 1949 .vendor = PCI_VENDOR_ID_COMMTECH, 1950 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 1951 .subvendor = PCI_ANY_ID, 1952 .subdevice = PCI_ANY_ID, 1953 .setup = pci_xr17v35x_setup, 1954 }, 1955 { 1956 .vendor = PCI_VENDOR_ID_COMMTECH, 1957 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 1958 .subvendor = PCI_ANY_ID, 1959 .subdevice = PCI_ANY_ID, 1960 .setup = pci_xr17v35x_setup, 1961 }, 1962 { 1963 .vendor = PCI_VENDOR_ID_COMMTECH, 1964 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 1965 .subvendor = PCI_ANY_ID, 1966 .subdevice = PCI_ANY_ID, 1967 .setup = pci_xr17v35x_setup, 1968 }, 1969 /* 1970 * Broadcom TruManage (NetXtreme) 1971 */ 1972 { 1973 .vendor = PCI_VENDOR_ID_BROADCOM, 1974 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 1975 .subvendor = PCI_ANY_ID, 1976 .subdevice = PCI_ANY_ID, 1977 .setup = pci_brcm_trumanage_setup, 1978 }, 1979 1980 /* 1981 * Default "match everything" terminator entry 1982 */ 1983 { 1984 .vendor = PCI_ANY_ID, 1985 .device = PCI_ANY_ID, 1986 .subvendor = PCI_ANY_ID, 1987 .subdevice = PCI_ANY_ID, 1988 .setup = pci_default_setup, 1989 } 1990 }; 1991 1992 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 1993 { 1994 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 1995 } 1996 1997 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 1998 { 1999 struct pci_serial_quirk *quirk; 2000 2001 for (quirk = pci_serial_quirks; ; quirk++) 2002 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2003 quirk_id_matches(quirk->device, dev->device) && 2004 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2005 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2006 break; 2007 return quirk; 2008 } 2009 2010 static inline int get_pci_irq(struct pci_dev *dev, 2011 const struct pciserial_board *board) 2012 { 2013 if (board->flags & FL_NOIRQ) 2014 return 0; 2015 else 2016 return dev->irq; 2017 } 2018 2019 /* 2020 * This is the configuration table for all of the PCI serial boards 2021 * which we support. It is directly indexed by the pci_board_num_t enum 2022 * value, which is encoded in the pci_device_id PCI probe table's 2023 * driver_data member. 2024 * 2025 * The makeup of these names are: 2026 * pbn_bn{_bt}_n_baud{_offsetinhex} 2027 * 2028 * bn = PCI BAR number 2029 * bt = Index using PCI BARs 2030 * n = number of serial ports 2031 * baud = baud rate 2032 * offsetinhex = offset for each sequential port (in hex) 2033 * 2034 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2035 * 2036 * Please note: in theory if n = 1, _bt infix should make no difference. 2037 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2038 */ 2039 enum pci_board_num_t { 2040 pbn_default = 0, 2041 2042 pbn_b0_1_115200, 2043 pbn_b0_2_115200, 2044 pbn_b0_4_115200, 2045 pbn_b0_5_115200, 2046 pbn_b0_8_115200, 2047 2048 pbn_b0_1_921600, 2049 pbn_b0_2_921600, 2050 pbn_b0_4_921600, 2051 2052 pbn_b0_2_1130000, 2053 2054 pbn_b0_4_1152000, 2055 2056 pbn_b0_2_1152000_200, 2057 pbn_b0_4_1152000_200, 2058 pbn_b0_8_1152000_200, 2059 2060 pbn_b0_2_1843200, 2061 pbn_b0_4_1843200, 2062 2063 pbn_b0_2_1843200_200, 2064 pbn_b0_4_1843200_200, 2065 pbn_b0_8_1843200_200, 2066 2067 pbn_b0_1_4000000, 2068 2069 pbn_b0_bt_1_115200, 2070 pbn_b0_bt_2_115200, 2071 pbn_b0_bt_4_115200, 2072 pbn_b0_bt_8_115200, 2073 2074 pbn_b0_bt_1_460800, 2075 pbn_b0_bt_2_460800, 2076 pbn_b0_bt_4_460800, 2077 2078 pbn_b0_bt_1_921600, 2079 pbn_b0_bt_2_921600, 2080 pbn_b0_bt_4_921600, 2081 pbn_b0_bt_8_921600, 2082 2083 pbn_b1_1_115200, 2084 pbn_b1_2_115200, 2085 pbn_b1_4_115200, 2086 pbn_b1_8_115200, 2087 pbn_b1_16_115200, 2088 2089 pbn_b1_1_921600, 2090 pbn_b1_2_921600, 2091 pbn_b1_4_921600, 2092 pbn_b1_8_921600, 2093 2094 pbn_b1_2_1250000, 2095 2096 pbn_b1_bt_1_115200, 2097 pbn_b1_bt_2_115200, 2098 pbn_b1_bt_4_115200, 2099 2100 pbn_b1_bt_2_921600, 2101 2102 pbn_b1_1_1382400, 2103 pbn_b1_2_1382400, 2104 pbn_b1_4_1382400, 2105 pbn_b1_8_1382400, 2106 2107 pbn_b2_1_115200, 2108 pbn_b2_2_115200, 2109 pbn_b2_4_115200, 2110 pbn_b2_8_115200, 2111 2112 pbn_b2_1_460800, 2113 pbn_b2_4_460800, 2114 pbn_b2_8_460800, 2115 pbn_b2_16_460800, 2116 2117 pbn_b2_1_921600, 2118 pbn_b2_4_921600, 2119 pbn_b2_8_921600, 2120 2121 pbn_b2_8_1152000, 2122 2123 pbn_b2_bt_1_115200, 2124 pbn_b2_bt_2_115200, 2125 pbn_b2_bt_4_115200, 2126 2127 pbn_b2_bt_2_921600, 2128 pbn_b2_bt_4_921600, 2129 2130 pbn_b3_2_115200, 2131 pbn_b3_4_115200, 2132 pbn_b3_8_115200, 2133 2134 pbn_b4_bt_2_921600, 2135 pbn_b4_bt_4_921600, 2136 pbn_b4_bt_8_921600, 2137 2138 /* 2139 * Board-specific versions. 2140 */ 2141 pbn_panacom, 2142 pbn_panacom2, 2143 pbn_panacom4, 2144 pbn_plx_romulus, 2145 pbn_oxsemi, 2146 pbn_oxsemi_1_4000000, 2147 pbn_oxsemi_2_4000000, 2148 pbn_oxsemi_4_4000000, 2149 pbn_oxsemi_8_4000000, 2150 pbn_intel_i960, 2151 pbn_sgi_ioc3, 2152 pbn_computone_4, 2153 pbn_computone_6, 2154 pbn_computone_8, 2155 pbn_sbsxrsio, 2156 pbn_exar_XR17C152, 2157 pbn_exar_XR17C154, 2158 pbn_exar_XR17C158, 2159 pbn_exar_XR17V352, 2160 pbn_exar_XR17V354, 2161 pbn_exar_XR17V358, 2162 pbn_exar_ibm_saturn, 2163 pbn_pasemi_1682M, 2164 pbn_ni8430_2, 2165 pbn_ni8430_4, 2166 pbn_ni8430_8, 2167 pbn_ni8430_16, 2168 pbn_ADDIDATA_PCIe_1_3906250, 2169 pbn_ADDIDATA_PCIe_2_3906250, 2170 pbn_ADDIDATA_PCIe_4_3906250, 2171 pbn_ADDIDATA_PCIe_8_3906250, 2172 pbn_ce4100_1_115200, 2173 pbn_omegapci, 2174 pbn_NETMOS9900_2s_115200, 2175 pbn_brcm_trumanage, 2176 }; 2177 2178 /* 2179 * uart_offset - the space between channels 2180 * reg_shift - describes how the UART registers are mapped 2181 * to PCI memory by the card. 2182 * For example IER register on SBS, Inc. PMC-OctPro is located at 2183 * offset 0x10 from the UART base, while UART_IER is defined as 1 2184 * in include/linux/serial_reg.h, 2185 * see first lines of serial_in() and serial_out() in 8250.c 2186 */ 2187 2188 static struct pciserial_board pci_boards[] = { 2189 [pbn_default] = { 2190 .flags = FL_BASE0, 2191 .num_ports = 1, 2192 .base_baud = 115200, 2193 .uart_offset = 8, 2194 }, 2195 [pbn_b0_1_115200] = { 2196 .flags = FL_BASE0, 2197 .num_ports = 1, 2198 .base_baud = 115200, 2199 .uart_offset = 8, 2200 }, 2201 [pbn_b0_2_115200] = { 2202 .flags = FL_BASE0, 2203 .num_ports = 2, 2204 .base_baud = 115200, 2205 .uart_offset = 8, 2206 }, 2207 [pbn_b0_4_115200] = { 2208 .flags = FL_BASE0, 2209 .num_ports = 4, 2210 .base_baud = 115200, 2211 .uart_offset = 8, 2212 }, 2213 [pbn_b0_5_115200] = { 2214 .flags = FL_BASE0, 2215 .num_ports = 5, 2216 .base_baud = 115200, 2217 .uart_offset = 8, 2218 }, 2219 [pbn_b0_8_115200] = { 2220 .flags = FL_BASE0, 2221 .num_ports = 8, 2222 .base_baud = 115200, 2223 .uart_offset = 8, 2224 }, 2225 [pbn_b0_1_921600] = { 2226 .flags = FL_BASE0, 2227 .num_ports = 1, 2228 .base_baud = 921600, 2229 .uart_offset = 8, 2230 }, 2231 [pbn_b0_2_921600] = { 2232 .flags = FL_BASE0, 2233 .num_ports = 2, 2234 .base_baud = 921600, 2235 .uart_offset = 8, 2236 }, 2237 [pbn_b0_4_921600] = { 2238 .flags = FL_BASE0, 2239 .num_ports = 4, 2240 .base_baud = 921600, 2241 .uart_offset = 8, 2242 }, 2243 2244 [pbn_b0_2_1130000] = { 2245 .flags = FL_BASE0, 2246 .num_ports = 2, 2247 .base_baud = 1130000, 2248 .uart_offset = 8, 2249 }, 2250 2251 [pbn_b0_4_1152000] = { 2252 .flags = FL_BASE0, 2253 .num_ports = 4, 2254 .base_baud = 1152000, 2255 .uart_offset = 8, 2256 }, 2257 2258 [pbn_b0_2_1152000_200] = { 2259 .flags = FL_BASE0, 2260 .num_ports = 2, 2261 .base_baud = 1152000, 2262 .uart_offset = 0x200, 2263 }, 2264 2265 [pbn_b0_4_1152000_200] = { 2266 .flags = FL_BASE0, 2267 .num_ports = 4, 2268 .base_baud = 1152000, 2269 .uart_offset = 0x200, 2270 }, 2271 2272 [pbn_b0_8_1152000_200] = { 2273 .flags = FL_BASE0, 2274 .num_ports = 8, 2275 .base_baud = 1152000, 2276 .uart_offset = 0x200, 2277 }, 2278 2279 [pbn_b0_2_1843200] = { 2280 .flags = FL_BASE0, 2281 .num_ports = 2, 2282 .base_baud = 1843200, 2283 .uart_offset = 8, 2284 }, 2285 [pbn_b0_4_1843200] = { 2286 .flags = FL_BASE0, 2287 .num_ports = 4, 2288 .base_baud = 1843200, 2289 .uart_offset = 8, 2290 }, 2291 2292 [pbn_b0_2_1843200_200] = { 2293 .flags = FL_BASE0, 2294 .num_ports = 2, 2295 .base_baud = 1843200, 2296 .uart_offset = 0x200, 2297 }, 2298 [pbn_b0_4_1843200_200] = { 2299 .flags = FL_BASE0, 2300 .num_ports = 4, 2301 .base_baud = 1843200, 2302 .uart_offset = 0x200, 2303 }, 2304 [pbn_b0_8_1843200_200] = { 2305 .flags = FL_BASE0, 2306 .num_ports = 8, 2307 .base_baud = 1843200, 2308 .uart_offset = 0x200, 2309 }, 2310 [pbn_b0_1_4000000] = { 2311 .flags = FL_BASE0, 2312 .num_ports = 1, 2313 .base_baud = 4000000, 2314 .uart_offset = 8, 2315 }, 2316 2317 [pbn_b0_bt_1_115200] = { 2318 .flags = FL_BASE0|FL_BASE_BARS, 2319 .num_ports = 1, 2320 .base_baud = 115200, 2321 .uart_offset = 8, 2322 }, 2323 [pbn_b0_bt_2_115200] = { 2324 .flags = FL_BASE0|FL_BASE_BARS, 2325 .num_ports = 2, 2326 .base_baud = 115200, 2327 .uart_offset = 8, 2328 }, 2329 [pbn_b0_bt_4_115200] = { 2330 .flags = FL_BASE0|FL_BASE_BARS, 2331 .num_ports = 4, 2332 .base_baud = 115200, 2333 .uart_offset = 8, 2334 }, 2335 [pbn_b0_bt_8_115200] = { 2336 .flags = FL_BASE0|FL_BASE_BARS, 2337 .num_ports = 8, 2338 .base_baud = 115200, 2339 .uart_offset = 8, 2340 }, 2341 2342 [pbn_b0_bt_1_460800] = { 2343 .flags = FL_BASE0|FL_BASE_BARS, 2344 .num_ports = 1, 2345 .base_baud = 460800, 2346 .uart_offset = 8, 2347 }, 2348 [pbn_b0_bt_2_460800] = { 2349 .flags = FL_BASE0|FL_BASE_BARS, 2350 .num_ports = 2, 2351 .base_baud = 460800, 2352 .uart_offset = 8, 2353 }, 2354 [pbn_b0_bt_4_460800] = { 2355 .flags = FL_BASE0|FL_BASE_BARS, 2356 .num_ports = 4, 2357 .base_baud = 460800, 2358 .uart_offset = 8, 2359 }, 2360 2361 [pbn_b0_bt_1_921600] = { 2362 .flags = FL_BASE0|FL_BASE_BARS, 2363 .num_ports = 1, 2364 .base_baud = 921600, 2365 .uart_offset = 8, 2366 }, 2367 [pbn_b0_bt_2_921600] = { 2368 .flags = FL_BASE0|FL_BASE_BARS, 2369 .num_ports = 2, 2370 .base_baud = 921600, 2371 .uart_offset = 8, 2372 }, 2373 [pbn_b0_bt_4_921600] = { 2374 .flags = FL_BASE0|FL_BASE_BARS, 2375 .num_ports = 4, 2376 .base_baud = 921600, 2377 .uart_offset = 8, 2378 }, 2379 [pbn_b0_bt_8_921600] = { 2380 .flags = FL_BASE0|FL_BASE_BARS, 2381 .num_ports = 8, 2382 .base_baud = 921600, 2383 .uart_offset = 8, 2384 }, 2385 2386 [pbn_b1_1_115200] = { 2387 .flags = FL_BASE1, 2388 .num_ports = 1, 2389 .base_baud = 115200, 2390 .uart_offset = 8, 2391 }, 2392 [pbn_b1_2_115200] = { 2393 .flags = FL_BASE1, 2394 .num_ports = 2, 2395 .base_baud = 115200, 2396 .uart_offset = 8, 2397 }, 2398 [pbn_b1_4_115200] = { 2399 .flags = FL_BASE1, 2400 .num_ports = 4, 2401 .base_baud = 115200, 2402 .uart_offset = 8, 2403 }, 2404 [pbn_b1_8_115200] = { 2405 .flags = FL_BASE1, 2406 .num_ports = 8, 2407 .base_baud = 115200, 2408 .uart_offset = 8, 2409 }, 2410 [pbn_b1_16_115200] = { 2411 .flags = FL_BASE1, 2412 .num_ports = 16, 2413 .base_baud = 115200, 2414 .uart_offset = 8, 2415 }, 2416 2417 [pbn_b1_1_921600] = { 2418 .flags = FL_BASE1, 2419 .num_ports = 1, 2420 .base_baud = 921600, 2421 .uart_offset = 8, 2422 }, 2423 [pbn_b1_2_921600] = { 2424 .flags = FL_BASE1, 2425 .num_ports = 2, 2426 .base_baud = 921600, 2427 .uart_offset = 8, 2428 }, 2429 [pbn_b1_4_921600] = { 2430 .flags = FL_BASE1, 2431 .num_ports = 4, 2432 .base_baud = 921600, 2433 .uart_offset = 8, 2434 }, 2435 [pbn_b1_8_921600] = { 2436 .flags = FL_BASE1, 2437 .num_ports = 8, 2438 .base_baud = 921600, 2439 .uart_offset = 8, 2440 }, 2441 [pbn_b1_2_1250000] = { 2442 .flags = FL_BASE1, 2443 .num_ports = 2, 2444 .base_baud = 1250000, 2445 .uart_offset = 8, 2446 }, 2447 2448 [pbn_b1_bt_1_115200] = { 2449 .flags = FL_BASE1|FL_BASE_BARS, 2450 .num_ports = 1, 2451 .base_baud = 115200, 2452 .uart_offset = 8, 2453 }, 2454 [pbn_b1_bt_2_115200] = { 2455 .flags = FL_BASE1|FL_BASE_BARS, 2456 .num_ports = 2, 2457 .base_baud = 115200, 2458 .uart_offset = 8, 2459 }, 2460 [pbn_b1_bt_4_115200] = { 2461 .flags = FL_BASE1|FL_BASE_BARS, 2462 .num_ports = 4, 2463 .base_baud = 115200, 2464 .uart_offset = 8, 2465 }, 2466 2467 [pbn_b1_bt_2_921600] = { 2468 .flags = FL_BASE1|FL_BASE_BARS, 2469 .num_ports = 2, 2470 .base_baud = 921600, 2471 .uart_offset = 8, 2472 }, 2473 2474 [pbn_b1_1_1382400] = { 2475 .flags = FL_BASE1, 2476 .num_ports = 1, 2477 .base_baud = 1382400, 2478 .uart_offset = 8, 2479 }, 2480 [pbn_b1_2_1382400] = { 2481 .flags = FL_BASE1, 2482 .num_ports = 2, 2483 .base_baud = 1382400, 2484 .uart_offset = 8, 2485 }, 2486 [pbn_b1_4_1382400] = { 2487 .flags = FL_BASE1, 2488 .num_ports = 4, 2489 .base_baud = 1382400, 2490 .uart_offset = 8, 2491 }, 2492 [pbn_b1_8_1382400] = { 2493 .flags = FL_BASE1, 2494 .num_ports = 8, 2495 .base_baud = 1382400, 2496 .uart_offset = 8, 2497 }, 2498 2499 [pbn_b2_1_115200] = { 2500 .flags = FL_BASE2, 2501 .num_ports = 1, 2502 .base_baud = 115200, 2503 .uart_offset = 8, 2504 }, 2505 [pbn_b2_2_115200] = { 2506 .flags = FL_BASE2, 2507 .num_ports = 2, 2508 .base_baud = 115200, 2509 .uart_offset = 8, 2510 }, 2511 [pbn_b2_4_115200] = { 2512 .flags = FL_BASE2, 2513 .num_ports = 4, 2514 .base_baud = 115200, 2515 .uart_offset = 8, 2516 }, 2517 [pbn_b2_8_115200] = { 2518 .flags = FL_BASE2, 2519 .num_ports = 8, 2520 .base_baud = 115200, 2521 .uart_offset = 8, 2522 }, 2523 2524 [pbn_b2_1_460800] = { 2525 .flags = FL_BASE2, 2526 .num_ports = 1, 2527 .base_baud = 460800, 2528 .uart_offset = 8, 2529 }, 2530 [pbn_b2_4_460800] = { 2531 .flags = FL_BASE2, 2532 .num_ports = 4, 2533 .base_baud = 460800, 2534 .uart_offset = 8, 2535 }, 2536 [pbn_b2_8_460800] = { 2537 .flags = FL_BASE2, 2538 .num_ports = 8, 2539 .base_baud = 460800, 2540 .uart_offset = 8, 2541 }, 2542 [pbn_b2_16_460800] = { 2543 .flags = FL_BASE2, 2544 .num_ports = 16, 2545 .base_baud = 460800, 2546 .uart_offset = 8, 2547 }, 2548 2549 [pbn_b2_1_921600] = { 2550 .flags = FL_BASE2, 2551 .num_ports = 1, 2552 .base_baud = 921600, 2553 .uart_offset = 8, 2554 }, 2555 [pbn_b2_4_921600] = { 2556 .flags = FL_BASE2, 2557 .num_ports = 4, 2558 .base_baud = 921600, 2559 .uart_offset = 8, 2560 }, 2561 [pbn_b2_8_921600] = { 2562 .flags = FL_BASE2, 2563 .num_ports = 8, 2564 .base_baud = 921600, 2565 .uart_offset = 8, 2566 }, 2567 2568 [pbn_b2_8_1152000] = { 2569 .flags = FL_BASE2, 2570 .num_ports = 8, 2571 .base_baud = 1152000, 2572 .uart_offset = 8, 2573 }, 2574 2575 [pbn_b2_bt_1_115200] = { 2576 .flags = FL_BASE2|FL_BASE_BARS, 2577 .num_ports = 1, 2578 .base_baud = 115200, 2579 .uart_offset = 8, 2580 }, 2581 [pbn_b2_bt_2_115200] = { 2582 .flags = FL_BASE2|FL_BASE_BARS, 2583 .num_ports = 2, 2584 .base_baud = 115200, 2585 .uart_offset = 8, 2586 }, 2587 [pbn_b2_bt_4_115200] = { 2588 .flags = FL_BASE2|FL_BASE_BARS, 2589 .num_ports = 4, 2590 .base_baud = 115200, 2591 .uart_offset = 8, 2592 }, 2593 2594 [pbn_b2_bt_2_921600] = { 2595 .flags = FL_BASE2|FL_BASE_BARS, 2596 .num_ports = 2, 2597 .base_baud = 921600, 2598 .uart_offset = 8, 2599 }, 2600 [pbn_b2_bt_4_921600] = { 2601 .flags = FL_BASE2|FL_BASE_BARS, 2602 .num_ports = 4, 2603 .base_baud = 921600, 2604 .uart_offset = 8, 2605 }, 2606 2607 [pbn_b3_2_115200] = { 2608 .flags = FL_BASE3, 2609 .num_ports = 2, 2610 .base_baud = 115200, 2611 .uart_offset = 8, 2612 }, 2613 [pbn_b3_4_115200] = { 2614 .flags = FL_BASE3, 2615 .num_ports = 4, 2616 .base_baud = 115200, 2617 .uart_offset = 8, 2618 }, 2619 [pbn_b3_8_115200] = { 2620 .flags = FL_BASE3, 2621 .num_ports = 8, 2622 .base_baud = 115200, 2623 .uart_offset = 8, 2624 }, 2625 2626 [pbn_b4_bt_2_921600] = { 2627 .flags = FL_BASE4, 2628 .num_ports = 2, 2629 .base_baud = 921600, 2630 .uart_offset = 8, 2631 }, 2632 [pbn_b4_bt_4_921600] = { 2633 .flags = FL_BASE4, 2634 .num_ports = 4, 2635 .base_baud = 921600, 2636 .uart_offset = 8, 2637 }, 2638 [pbn_b4_bt_8_921600] = { 2639 .flags = FL_BASE4, 2640 .num_ports = 8, 2641 .base_baud = 921600, 2642 .uart_offset = 8, 2643 }, 2644 2645 /* 2646 * Entries following this are board-specific. 2647 */ 2648 2649 /* 2650 * Panacom - IOMEM 2651 */ 2652 [pbn_panacom] = { 2653 .flags = FL_BASE2, 2654 .num_ports = 2, 2655 .base_baud = 921600, 2656 .uart_offset = 0x400, 2657 .reg_shift = 7, 2658 }, 2659 [pbn_panacom2] = { 2660 .flags = FL_BASE2|FL_BASE_BARS, 2661 .num_ports = 2, 2662 .base_baud = 921600, 2663 .uart_offset = 0x400, 2664 .reg_shift = 7, 2665 }, 2666 [pbn_panacom4] = { 2667 .flags = FL_BASE2|FL_BASE_BARS, 2668 .num_ports = 4, 2669 .base_baud = 921600, 2670 .uart_offset = 0x400, 2671 .reg_shift = 7, 2672 }, 2673 2674 /* I think this entry is broken - the first_offset looks wrong --rmk */ 2675 [pbn_plx_romulus] = { 2676 .flags = FL_BASE2, 2677 .num_ports = 4, 2678 .base_baud = 921600, 2679 .uart_offset = 8 << 2, 2680 .reg_shift = 2, 2681 .first_offset = 0x03, 2682 }, 2683 2684 /* 2685 * This board uses the size of PCI Base region 0 to 2686 * signal now many ports are available 2687 */ 2688 [pbn_oxsemi] = { 2689 .flags = FL_BASE0|FL_REGION_SZ_CAP, 2690 .num_ports = 32, 2691 .base_baud = 115200, 2692 .uart_offset = 8, 2693 }, 2694 [pbn_oxsemi_1_4000000] = { 2695 .flags = FL_BASE0, 2696 .num_ports = 1, 2697 .base_baud = 4000000, 2698 .uart_offset = 0x200, 2699 .first_offset = 0x1000, 2700 }, 2701 [pbn_oxsemi_2_4000000] = { 2702 .flags = FL_BASE0, 2703 .num_ports = 2, 2704 .base_baud = 4000000, 2705 .uart_offset = 0x200, 2706 .first_offset = 0x1000, 2707 }, 2708 [pbn_oxsemi_4_4000000] = { 2709 .flags = FL_BASE0, 2710 .num_ports = 4, 2711 .base_baud = 4000000, 2712 .uart_offset = 0x200, 2713 .first_offset = 0x1000, 2714 }, 2715 [pbn_oxsemi_8_4000000] = { 2716 .flags = FL_BASE0, 2717 .num_ports = 8, 2718 .base_baud = 4000000, 2719 .uart_offset = 0x200, 2720 .first_offset = 0x1000, 2721 }, 2722 2723 2724 /* 2725 * EKF addition for i960 Boards form EKF with serial port. 2726 * Max 256 ports. 2727 */ 2728 [pbn_intel_i960] = { 2729 .flags = FL_BASE0, 2730 .num_ports = 32, 2731 .base_baud = 921600, 2732 .uart_offset = 8 << 2, 2733 .reg_shift = 2, 2734 .first_offset = 0x10000, 2735 }, 2736 [pbn_sgi_ioc3] = { 2737 .flags = FL_BASE0|FL_NOIRQ, 2738 .num_ports = 1, 2739 .base_baud = 458333, 2740 .uart_offset = 8, 2741 .reg_shift = 0, 2742 .first_offset = 0x20178, 2743 }, 2744 2745 /* 2746 * Computone - uses IOMEM. 2747 */ 2748 [pbn_computone_4] = { 2749 .flags = FL_BASE0, 2750 .num_ports = 4, 2751 .base_baud = 921600, 2752 .uart_offset = 0x40, 2753 .reg_shift = 2, 2754 .first_offset = 0x200, 2755 }, 2756 [pbn_computone_6] = { 2757 .flags = FL_BASE0, 2758 .num_ports = 6, 2759 .base_baud = 921600, 2760 .uart_offset = 0x40, 2761 .reg_shift = 2, 2762 .first_offset = 0x200, 2763 }, 2764 [pbn_computone_8] = { 2765 .flags = FL_BASE0, 2766 .num_ports = 8, 2767 .base_baud = 921600, 2768 .uart_offset = 0x40, 2769 .reg_shift = 2, 2770 .first_offset = 0x200, 2771 }, 2772 [pbn_sbsxrsio] = { 2773 .flags = FL_BASE0, 2774 .num_ports = 8, 2775 .base_baud = 460800, 2776 .uart_offset = 256, 2777 .reg_shift = 4, 2778 }, 2779 /* 2780 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 2781 * Only basic 16550A support. 2782 * XR17C15[24] are not tested, but they should work. 2783 */ 2784 [pbn_exar_XR17C152] = { 2785 .flags = FL_BASE0, 2786 .num_ports = 2, 2787 .base_baud = 921600, 2788 .uart_offset = 0x200, 2789 }, 2790 [pbn_exar_XR17C154] = { 2791 .flags = FL_BASE0, 2792 .num_ports = 4, 2793 .base_baud = 921600, 2794 .uart_offset = 0x200, 2795 }, 2796 [pbn_exar_XR17C158] = { 2797 .flags = FL_BASE0, 2798 .num_ports = 8, 2799 .base_baud = 921600, 2800 .uart_offset = 0x200, 2801 }, 2802 [pbn_exar_XR17V352] = { 2803 .flags = FL_BASE0, 2804 .num_ports = 2, 2805 .base_baud = 7812500, 2806 .uart_offset = 0x400, 2807 .reg_shift = 0, 2808 .first_offset = 0, 2809 }, 2810 [pbn_exar_XR17V354] = { 2811 .flags = FL_BASE0, 2812 .num_ports = 4, 2813 .base_baud = 7812500, 2814 .uart_offset = 0x400, 2815 .reg_shift = 0, 2816 .first_offset = 0, 2817 }, 2818 [pbn_exar_XR17V358] = { 2819 .flags = FL_BASE0, 2820 .num_ports = 8, 2821 .base_baud = 7812500, 2822 .uart_offset = 0x400, 2823 .reg_shift = 0, 2824 .first_offset = 0, 2825 }, 2826 [pbn_exar_ibm_saturn] = { 2827 .flags = FL_BASE0, 2828 .num_ports = 1, 2829 .base_baud = 921600, 2830 .uart_offset = 0x200, 2831 }, 2832 2833 /* 2834 * PA Semi PWRficient PA6T-1682M on-chip UART 2835 */ 2836 [pbn_pasemi_1682M] = { 2837 .flags = FL_BASE0, 2838 .num_ports = 1, 2839 .base_baud = 8333333, 2840 }, 2841 /* 2842 * National Instruments 843x 2843 */ 2844 [pbn_ni8430_16] = { 2845 .flags = FL_BASE0, 2846 .num_ports = 16, 2847 .base_baud = 3686400, 2848 .uart_offset = 0x10, 2849 .first_offset = 0x800, 2850 }, 2851 [pbn_ni8430_8] = { 2852 .flags = FL_BASE0, 2853 .num_ports = 8, 2854 .base_baud = 3686400, 2855 .uart_offset = 0x10, 2856 .first_offset = 0x800, 2857 }, 2858 [pbn_ni8430_4] = { 2859 .flags = FL_BASE0, 2860 .num_ports = 4, 2861 .base_baud = 3686400, 2862 .uart_offset = 0x10, 2863 .first_offset = 0x800, 2864 }, 2865 [pbn_ni8430_2] = { 2866 .flags = FL_BASE0, 2867 .num_ports = 2, 2868 .base_baud = 3686400, 2869 .uart_offset = 0x10, 2870 .first_offset = 0x800, 2871 }, 2872 /* 2873 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 2874 */ 2875 [pbn_ADDIDATA_PCIe_1_3906250] = { 2876 .flags = FL_BASE0, 2877 .num_ports = 1, 2878 .base_baud = 3906250, 2879 .uart_offset = 0x200, 2880 .first_offset = 0x1000, 2881 }, 2882 [pbn_ADDIDATA_PCIe_2_3906250] = { 2883 .flags = FL_BASE0, 2884 .num_ports = 2, 2885 .base_baud = 3906250, 2886 .uart_offset = 0x200, 2887 .first_offset = 0x1000, 2888 }, 2889 [pbn_ADDIDATA_PCIe_4_3906250] = { 2890 .flags = FL_BASE0, 2891 .num_ports = 4, 2892 .base_baud = 3906250, 2893 .uart_offset = 0x200, 2894 .first_offset = 0x1000, 2895 }, 2896 [pbn_ADDIDATA_PCIe_8_3906250] = { 2897 .flags = FL_BASE0, 2898 .num_ports = 8, 2899 .base_baud = 3906250, 2900 .uart_offset = 0x200, 2901 .first_offset = 0x1000, 2902 }, 2903 [pbn_ce4100_1_115200] = { 2904 .flags = FL_BASE_BARS, 2905 .num_ports = 2, 2906 .base_baud = 921600, 2907 .reg_shift = 2, 2908 }, 2909 [pbn_omegapci] = { 2910 .flags = FL_BASE0, 2911 .num_ports = 8, 2912 .base_baud = 115200, 2913 .uart_offset = 0x200, 2914 }, 2915 [pbn_NETMOS9900_2s_115200] = { 2916 .flags = FL_BASE0, 2917 .num_ports = 2, 2918 .base_baud = 115200, 2919 }, 2920 [pbn_brcm_trumanage] = { 2921 .flags = FL_BASE0, 2922 .num_ports = 1, 2923 .reg_shift = 2, 2924 .base_baud = 115200, 2925 }, 2926 }; 2927 2928 static const struct pci_device_id blacklist[] = { 2929 /* softmodems */ 2930 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 2931 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 2932 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 2933 2934 /* multi-io cards handled by parport_serial */ 2935 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 2936 }; 2937 2938 /* 2939 * Given a complete unknown PCI device, try to use some heuristics to 2940 * guess what the configuration might be, based on the pitiful PCI 2941 * serial specs. Returns 0 on success, 1 on failure. 2942 */ 2943 static int 2944 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 2945 { 2946 const struct pci_device_id *bldev; 2947 int num_iomem, num_port, first_port = -1, i; 2948 2949 /* 2950 * If it is not a communications device or the programming 2951 * interface is greater than 6, give up. 2952 * 2953 * (Should we try to make guesses for multiport serial devices 2954 * later?) 2955 */ 2956 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 2957 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 2958 (dev->class & 0xff) > 6) 2959 return -ENODEV; 2960 2961 /* 2962 * Do not access blacklisted devices that are known not to 2963 * feature serial ports or are handled by other modules. 2964 */ 2965 for (bldev = blacklist; 2966 bldev < blacklist + ARRAY_SIZE(blacklist); 2967 bldev++) { 2968 if (dev->vendor == bldev->vendor && 2969 dev->device == bldev->device) 2970 return -ENODEV; 2971 } 2972 2973 num_iomem = num_port = 0; 2974 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 2975 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 2976 num_port++; 2977 if (first_port == -1) 2978 first_port = i; 2979 } 2980 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 2981 num_iomem++; 2982 } 2983 2984 /* 2985 * If there is 1 or 0 iomem regions, and exactly one port, 2986 * use it. We guess the number of ports based on the IO 2987 * region size. 2988 */ 2989 if (num_iomem <= 1 && num_port == 1) { 2990 board->flags = first_port; 2991 board->num_ports = pci_resource_len(dev, first_port) / 8; 2992 return 0; 2993 } 2994 2995 /* 2996 * Now guess if we've got a board which indexes by BARs. 2997 * Each IO BAR should be 8 bytes, and they should follow 2998 * consecutively. 2999 */ 3000 first_port = -1; 3001 num_port = 0; 3002 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3003 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3004 pci_resource_len(dev, i) == 8 && 3005 (first_port == -1 || (first_port + num_port) == i)) { 3006 num_port++; 3007 if (first_port == -1) 3008 first_port = i; 3009 } 3010 } 3011 3012 if (num_port > 1) { 3013 board->flags = first_port | FL_BASE_BARS; 3014 board->num_ports = num_port; 3015 return 0; 3016 } 3017 3018 return -ENODEV; 3019 } 3020 3021 static inline int 3022 serial_pci_matches(const struct pciserial_board *board, 3023 const struct pciserial_board *guessed) 3024 { 3025 return 3026 board->num_ports == guessed->num_ports && 3027 board->base_baud == guessed->base_baud && 3028 board->uart_offset == guessed->uart_offset && 3029 board->reg_shift == guessed->reg_shift && 3030 board->first_offset == guessed->first_offset; 3031 } 3032 3033 struct serial_private * 3034 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3035 { 3036 struct uart_8250_port uart; 3037 struct serial_private *priv; 3038 struct pci_serial_quirk *quirk; 3039 int rc, nr_ports, i; 3040 3041 nr_ports = board->num_ports; 3042 3043 /* 3044 * Find an init and setup quirks. 3045 */ 3046 quirk = find_quirk(dev); 3047 3048 /* 3049 * Run the new-style initialization function. 3050 * The initialization function returns: 3051 * <0 - error 3052 * 0 - use board->num_ports 3053 * >0 - number of ports 3054 */ 3055 if (quirk->init) { 3056 rc = quirk->init(dev); 3057 if (rc < 0) { 3058 priv = ERR_PTR(rc); 3059 goto err_out; 3060 } 3061 if (rc) 3062 nr_ports = rc; 3063 } 3064 3065 priv = kzalloc(sizeof(struct serial_private) + 3066 sizeof(unsigned int) * nr_ports, 3067 GFP_KERNEL); 3068 if (!priv) { 3069 priv = ERR_PTR(-ENOMEM); 3070 goto err_deinit; 3071 } 3072 3073 priv->dev = dev; 3074 priv->quirk = quirk; 3075 3076 memset(&uart, 0, sizeof(uart)); 3077 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3078 uart.port.uartclk = board->base_baud * 16; 3079 uart.port.irq = get_pci_irq(dev, board); 3080 uart.port.dev = &dev->dev; 3081 3082 for (i = 0; i < nr_ports; i++) { 3083 if (quirk->setup(priv, board, &uart, i)) 3084 break; 3085 3086 #ifdef SERIAL_DEBUG_PCI 3087 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n", 3088 uart.port.iobase, uart.port.irq, uart.port.iotype); 3089 #endif 3090 3091 priv->line[i] = serial8250_register_8250_port(&uart); 3092 if (priv->line[i] < 0) { 3093 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]); 3094 break; 3095 } 3096 } 3097 priv->nr = i; 3098 return priv; 3099 3100 err_deinit: 3101 if (quirk->exit) 3102 quirk->exit(dev); 3103 err_out: 3104 return priv; 3105 } 3106 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3107 3108 void pciserial_remove_ports(struct serial_private *priv) 3109 { 3110 struct pci_serial_quirk *quirk; 3111 int i; 3112 3113 for (i = 0; i < priv->nr; i++) 3114 serial8250_unregister_port(priv->line[i]); 3115 3116 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3117 if (priv->remapped_bar[i]) 3118 iounmap(priv->remapped_bar[i]); 3119 priv->remapped_bar[i] = NULL; 3120 } 3121 3122 /* 3123 * Find the exit quirks. 3124 */ 3125 quirk = find_quirk(priv->dev); 3126 if (quirk->exit) 3127 quirk->exit(priv->dev); 3128 3129 kfree(priv); 3130 } 3131 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3132 3133 void pciserial_suspend_ports(struct serial_private *priv) 3134 { 3135 int i; 3136 3137 for (i = 0; i < priv->nr; i++) 3138 if (priv->line[i] >= 0) 3139 serial8250_suspend_port(priv->line[i]); 3140 3141 /* 3142 * Ensure that every init quirk is properly torn down 3143 */ 3144 if (priv->quirk->exit) 3145 priv->quirk->exit(priv->dev); 3146 } 3147 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3148 3149 void pciserial_resume_ports(struct serial_private *priv) 3150 { 3151 int i; 3152 3153 /* 3154 * Ensure that the board is correctly configured. 3155 */ 3156 if (priv->quirk->init) 3157 priv->quirk->init(priv->dev); 3158 3159 for (i = 0; i < priv->nr; i++) 3160 if (priv->line[i] >= 0) 3161 serial8250_resume_port(priv->line[i]); 3162 } 3163 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3164 3165 /* 3166 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3167 * to the arrangement of serial ports on a PCI card. 3168 */ 3169 static int 3170 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3171 { 3172 struct pci_serial_quirk *quirk; 3173 struct serial_private *priv; 3174 const struct pciserial_board *board; 3175 struct pciserial_board tmp; 3176 int rc; 3177 3178 quirk = find_quirk(dev); 3179 if (quirk->probe) { 3180 rc = quirk->probe(dev); 3181 if (rc) 3182 return rc; 3183 } 3184 3185 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3186 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n", 3187 ent->driver_data); 3188 return -EINVAL; 3189 } 3190 3191 board = &pci_boards[ent->driver_data]; 3192 3193 rc = pci_enable_device(dev); 3194 pci_save_state(dev); 3195 if (rc) 3196 return rc; 3197 3198 if (ent->driver_data == pbn_default) { 3199 /* 3200 * Use a copy of the pci_board entry for this; 3201 * avoid changing entries in the table. 3202 */ 3203 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3204 board = &tmp; 3205 3206 /* 3207 * We matched one of our class entries. Try to 3208 * determine the parameters of this board. 3209 */ 3210 rc = serial_pci_guess_board(dev, &tmp); 3211 if (rc) 3212 goto disable; 3213 } else { 3214 /* 3215 * We matched an explicit entry. If we are able to 3216 * detect this boards settings with our heuristic, 3217 * then we no longer need this entry. 3218 */ 3219 memcpy(&tmp, &pci_boards[pbn_default], 3220 sizeof(struct pciserial_board)); 3221 rc = serial_pci_guess_board(dev, &tmp); 3222 if (rc == 0 && serial_pci_matches(board, &tmp)) 3223 moan_device("Redundant entry in serial pci_table.", 3224 dev); 3225 } 3226 3227 priv = pciserial_init_ports(dev, board); 3228 if (!IS_ERR(priv)) { 3229 pci_set_drvdata(dev, priv); 3230 return 0; 3231 } 3232 3233 rc = PTR_ERR(priv); 3234 3235 disable: 3236 pci_disable_device(dev); 3237 return rc; 3238 } 3239 3240 static void pciserial_remove_one(struct pci_dev *dev) 3241 { 3242 struct serial_private *priv = pci_get_drvdata(dev); 3243 3244 pci_set_drvdata(dev, NULL); 3245 3246 pciserial_remove_ports(priv); 3247 3248 pci_disable_device(dev); 3249 } 3250 3251 #ifdef CONFIG_PM 3252 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) 3253 { 3254 struct serial_private *priv = pci_get_drvdata(dev); 3255 3256 if (priv) 3257 pciserial_suspend_ports(priv); 3258 3259 pci_save_state(dev); 3260 pci_set_power_state(dev, pci_choose_state(dev, state)); 3261 return 0; 3262 } 3263 3264 static int pciserial_resume_one(struct pci_dev *dev) 3265 { 3266 int err; 3267 struct serial_private *priv = pci_get_drvdata(dev); 3268 3269 pci_set_power_state(dev, PCI_D0); 3270 pci_restore_state(dev); 3271 3272 if (priv) { 3273 /* 3274 * The device may have been disabled. Re-enable it. 3275 */ 3276 err = pci_enable_device(dev); 3277 /* FIXME: We cannot simply error out here */ 3278 if (err) 3279 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n"); 3280 pciserial_resume_ports(priv); 3281 } 3282 return 0; 3283 } 3284 #endif 3285 3286 static struct pci_device_id serial_pci_tbl[] = { 3287 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3288 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3289 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3290 pbn_b2_8_921600 }, 3291 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3292 PCI_SUBVENDOR_ID_CONNECT_TECH, 3293 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3294 pbn_b1_8_1382400 }, 3295 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3296 PCI_SUBVENDOR_ID_CONNECT_TECH, 3297 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3298 pbn_b1_4_1382400 }, 3299 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3300 PCI_SUBVENDOR_ID_CONNECT_TECH, 3301 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3302 pbn_b1_2_1382400 }, 3303 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3304 PCI_SUBVENDOR_ID_CONNECT_TECH, 3305 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3306 pbn_b1_8_1382400 }, 3307 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3308 PCI_SUBVENDOR_ID_CONNECT_TECH, 3309 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3310 pbn_b1_4_1382400 }, 3311 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3312 PCI_SUBVENDOR_ID_CONNECT_TECH, 3313 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3314 pbn_b1_2_1382400 }, 3315 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3316 PCI_SUBVENDOR_ID_CONNECT_TECH, 3317 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3318 pbn_b1_8_921600 }, 3319 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3320 PCI_SUBVENDOR_ID_CONNECT_TECH, 3321 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3322 pbn_b1_8_921600 }, 3323 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3324 PCI_SUBVENDOR_ID_CONNECT_TECH, 3325 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3326 pbn_b1_4_921600 }, 3327 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3328 PCI_SUBVENDOR_ID_CONNECT_TECH, 3329 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3330 pbn_b1_4_921600 }, 3331 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3332 PCI_SUBVENDOR_ID_CONNECT_TECH, 3333 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3334 pbn_b1_2_921600 }, 3335 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3336 PCI_SUBVENDOR_ID_CONNECT_TECH, 3337 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3338 pbn_b1_8_921600 }, 3339 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3340 PCI_SUBVENDOR_ID_CONNECT_TECH, 3341 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3342 pbn_b1_8_921600 }, 3343 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3344 PCI_SUBVENDOR_ID_CONNECT_TECH, 3345 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3346 pbn_b1_4_921600 }, 3347 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3348 PCI_SUBVENDOR_ID_CONNECT_TECH, 3349 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 3350 pbn_b1_2_1250000 }, 3351 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3352 PCI_SUBVENDOR_ID_CONNECT_TECH, 3353 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 3354 pbn_b0_2_1843200 }, 3355 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3356 PCI_SUBVENDOR_ID_CONNECT_TECH, 3357 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 3358 pbn_b0_4_1843200 }, 3359 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3360 PCI_VENDOR_ID_AFAVLAB, 3361 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 3362 pbn_b0_4_1152000 }, 3363 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3364 PCI_SUBVENDOR_ID_CONNECT_TECH, 3365 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 3366 pbn_b0_2_1843200_200 }, 3367 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3368 PCI_SUBVENDOR_ID_CONNECT_TECH, 3369 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 3370 pbn_b0_4_1843200_200 }, 3371 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3372 PCI_SUBVENDOR_ID_CONNECT_TECH, 3373 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 3374 pbn_b0_8_1843200_200 }, 3375 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3376 PCI_SUBVENDOR_ID_CONNECT_TECH, 3377 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 3378 pbn_b0_2_1843200_200 }, 3379 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3380 PCI_SUBVENDOR_ID_CONNECT_TECH, 3381 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 3382 pbn_b0_4_1843200_200 }, 3383 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3384 PCI_SUBVENDOR_ID_CONNECT_TECH, 3385 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 3386 pbn_b0_8_1843200_200 }, 3387 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3388 PCI_SUBVENDOR_ID_CONNECT_TECH, 3389 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 3390 pbn_b0_2_1843200_200 }, 3391 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3392 PCI_SUBVENDOR_ID_CONNECT_TECH, 3393 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 3394 pbn_b0_4_1843200_200 }, 3395 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3396 PCI_SUBVENDOR_ID_CONNECT_TECH, 3397 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 3398 pbn_b0_8_1843200_200 }, 3399 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3400 PCI_SUBVENDOR_ID_CONNECT_TECH, 3401 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 3402 pbn_b0_2_1843200_200 }, 3403 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3404 PCI_SUBVENDOR_ID_CONNECT_TECH, 3405 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 3406 pbn_b0_4_1843200_200 }, 3407 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3408 PCI_SUBVENDOR_ID_CONNECT_TECH, 3409 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 3410 pbn_b0_8_1843200_200 }, 3411 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3412 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 3413 0, 0, pbn_exar_ibm_saturn }, 3414 3415 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3417 pbn_b2_bt_1_115200 }, 3418 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3420 pbn_b2_bt_2_115200 }, 3421 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3423 pbn_b2_bt_4_115200 }, 3424 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3426 pbn_b2_bt_2_115200 }, 3427 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3429 pbn_b2_bt_4_115200 }, 3430 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3432 pbn_b2_8_115200 }, 3433 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3435 pbn_b2_8_460800 }, 3436 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3438 pbn_b2_8_115200 }, 3439 3440 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3442 pbn_b2_bt_2_115200 }, 3443 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3445 pbn_b2_bt_2_921600 }, 3446 /* 3447 * VScom SPCOM800, from sl@s.pl 3448 */ 3449 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3451 pbn_b2_8_921600 }, 3452 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 3453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3454 pbn_b2_4_921600 }, 3455 /* Unknown card - subdevice 0x1584 */ 3456 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3457 PCI_VENDOR_ID_PLX, 3458 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 3459 pbn_b0_4_115200 }, 3460 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3461 PCI_SUBVENDOR_ID_KEYSPAN, 3462 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 3463 pbn_panacom }, 3464 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3466 pbn_panacom4 }, 3467 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3469 pbn_panacom2 }, 3470 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 3471 PCI_VENDOR_ID_ESDGMBH, 3472 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 3473 pbn_b2_4_115200 }, 3474 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3475 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3476 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 3477 pbn_b2_4_460800 }, 3478 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3479 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3480 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 3481 pbn_b2_8_460800 }, 3482 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3483 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3484 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 3485 pbn_b2_16_460800 }, 3486 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3487 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3488 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 3489 pbn_b2_16_460800 }, 3490 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3491 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 3492 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 3493 pbn_b2_4_460800 }, 3494 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3495 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 3496 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 3497 pbn_b2_8_460800 }, 3498 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3499 PCI_SUBVENDOR_ID_EXSYS, 3500 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 3501 pbn_b2_4_115200 }, 3502 /* 3503 * Megawolf Romulus PCI Serial Card, from Mike Hudson 3504 * (Exoray@isys.ca) 3505 */ 3506 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 3507 0x10b5, 0x106a, 0, 0, 3508 pbn_plx_romulus }, 3509 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 3510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3511 pbn_b1_4_115200 }, 3512 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 3513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3514 pbn_b1_2_115200 }, 3515 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 3516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3517 pbn_b1_8_115200 }, 3518 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 3519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3520 pbn_b1_8_115200 }, 3521 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 3522 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 3523 0, 0, 3524 pbn_b0_4_921600 }, 3525 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3526 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 3527 0, 0, 3528 pbn_b0_4_1152000 }, 3529 { PCI_VENDOR_ID_OXSEMI, 0x9505, 3530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3531 pbn_b0_bt_2_921600 }, 3532 3533 /* 3534 * The below card is a little controversial since it is the 3535 * subject of a PCI vendor/device ID clash. (See 3536 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 3537 * For now just used the hex ID 0x950a. 3538 */ 3539 { PCI_VENDOR_ID_OXSEMI, 0x950a, 3540 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 3541 0, 0, pbn_b0_2_115200 }, 3542 { PCI_VENDOR_ID_OXSEMI, 0x950a, 3543 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 3544 0, 0, pbn_b0_2_115200 }, 3545 { PCI_VENDOR_ID_OXSEMI, 0x950a, 3546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3547 pbn_b0_2_1130000 }, 3548 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 3549 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 3550 pbn_b0_1_921600 }, 3551 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3552 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3553 pbn_b0_4_115200 }, 3554 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 3555 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3556 pbn_b0_bt_2_921600 }, 3557 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 3558 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 3559 pbn_b2_8_1152000 }, 3560 3561 /* 3562 * Oxford Semiconductor Inc. Tornado PCI express device range. 3563 */ 3564 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 3565 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3566 pbn_b0_1_4000000 }, 3567 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 3568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3569 pbn_b0_1_4000000 }, 3570 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 3571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3572 pbn_oxsemi_1_4000000 }, 3573 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 3574 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3575 pbn_oxsemi_1_4000000 }, 3576 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 3577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3578 pbn_b0_1_4000000 }, 3579 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 3580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3581 pbn_b0_1_4000000 }, 3582 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 3583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3584 pbn_oxsemi_1_4000000 }, 3585 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 3586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3587 pbn_oxsemi_1_4000000 }, 3588 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 3589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3590 pbn_b0_1_4000000 }, 3591 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 3592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3593 pbn_b0_1_4000000 }, 3594 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3596 pbn_b0_1_4000000 }, 3597 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 3598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3599 pbn_b0_1_4000000 }, 3600 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 3601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3602 pbn_oxsemi_2_4000000 }, 3603 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 3604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3605 pbn_oxsemi_2_4000000 }, 3606 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 3607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3608 pbn_oxsemi_4_4000000 }, 3609 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3611 pbn_oxsemi_4_4000000 }, 3612 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 3613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3614 pbn_oxsemi_8_4000000 }, 3615 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3617 pbn_oxsemi_8_4000000 }, 3618 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 3619 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3620 pbn_oxsemi_1_4000000 }, 3621 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 3622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3623 pbn_oxsemi_1_4000000 }, 3624 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 3625 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3626 pbn_oxsemi_1_4000000 }, 3627 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 3628 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3629 pbn_oxsemi_1_4000000 }, 3630 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3632 pbn_oxsemi_1_4000000 }, 3633 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 3634 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3635 pbn_oxsemi_1_4000000 }, 3636 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 3637 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3638 pbn_oxsemi_1_4000000 }, 3639 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 3640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3641 pbn_oxsemi_1_4000000 }, 3642 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 3643 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3644 pbn_oxsemi_1_4000000 }, 3645 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 3646 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3647 pbn_oxsemi_1_4000000 }, 3648 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 3649 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3650 pbn_oxsemi_1_4000000 }, 3651 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 3652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3653 pbn_oxsemi_1_4000000 }, 3654 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 3655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3656 pbn_oxsemi_1_4000000 }, 3657 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 3658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3659 pbn_oxsemi_1_4000000 }, 3660 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 3661 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3662 pbn_oxsemi_1_4000000 }, 3663 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 3664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3665 pbn_oxsemi_1_4000000 }, 3666 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 3667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3668 pbn_oxsemi_1_4000000 }, 3669 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 3670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3671 pbn_oxsemi_1_4000000 }, 3672 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 3673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3674 pbn_oxsemi_1_4000000 }, 3675 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 3676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3677 pbn_oxsemi_1_4000000 }, 3678 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 3679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3680 pbn_oxsemi_1_4000000 }, 3681 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 3682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3683 pbn_oxsemi_1_4000000 }, 3684 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 3685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3686 pbn_oxsemi_1_4000000 }, 3687 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 3688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3689 pbn_oxsemi_1_4000000 }, 3690 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 3691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3692 pbn_oxsemi_1_4000000 }, 3693 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 3694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3695 pbn_oxsemi_1_4000000 }, 3696 /* 3697 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 3698 */ 3699 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 3700 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 3701 pbn_oxsemi_1_4000000 }, 3702 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 3703 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 3704 pbn_oxsemi_2_4000000 }, 3705 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 3706 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 3707 pbn_oxsemi_4_4000000 }, 3708 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 3709 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 3710 pbn_oxsemi_8_4000000 }, 3711 3712 /* 3713 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 3714 */ 3715 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 3716 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 3717 pbn_oxsemi_2_4000000 }, 3718 3719 /* 3720 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 3721 * from skokodyn@yahoo.com 3722 */ 3723 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 3724 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 3725 pbn_sbsxrsio }, 3726 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 3727 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 3728 pbn_sbsxrsio }, 3729 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 3730 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 3731 pbn_sbsxrsio }, 3732 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 3733 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 3734 pbn_sbsxrsio }, 3735 3736 /* 3737 * Digitan DS560-558, from jimd@esoft.com 3738 */ 3739 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 3740 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3741 pbn_b1_1_115200 }, 3742 3743 /* 3744 * Titan Electronic cards 3745 * The 400L and 800L have a custom setup quirk. 3746 */ 3747 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 3748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3749 pbn_b0_1_921600 }, 3750 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3752 pbn_b0_2_921600 }, 3753 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 3754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3755 pbn_b0_4_921600 }, 3756 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 3757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3758 pbn_b0_4_921600 }, 3759 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 3760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3761 pbn_b1_1_921600 }, 3762 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 3763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3764 pbn_b1_bt_2_921600 }, 3765 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 3766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3767 pbn_b0_bt_4_921600 }, 3768 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 3769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3770 pbn_b0_bt_8_921600 }, 3771 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 3772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3773 pbn_b4_bt_2_921600 }, 3774 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 3775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3776 pbn_b4_bt_4_921600 }, 3777 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 3778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3779 pbn_b4_bt_8_921600 }, 3780 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 3781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3782 pbn_b0_4_921600 }, 3783 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 3784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3785 pbn_b0_4_921600 }, 3786 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 3787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3788 pbn_b0_4_921600 }, 3789 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 3790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3791 pbn_oxsemi_1_4000000 }, 3792 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 3793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3794 pbn_oxsemi_2_4000000 }, 3795 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 3796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3797 pbn_oxsemi_4_4000000 }, 3798 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3800 pbn_oxsemi_8_4000000 }, 3801 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 3802 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3803 pbn_oxsemi_2_4000000 }, 3804 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 3805 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3806 pbn_oxsemi_2_4000000 }, 3807 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 3808 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3809 pbn_b0_4_921600 }, 3810 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 3811 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3812 pbn_b0_4_921600 }, 3813 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 3814 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3815 pbn_b0_4_921600 }, 3816 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 3817 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3818 pbn_b0_4_921600 }, 3819 3820 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 3821 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3822 pbn_b2_1_460800 }, 3823 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3825 pbn_b2_1_460800 }, 3826 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3828 pbn_b2_1_460800 }, 3829 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3831 pbn_b2_bt_2_921600 }, 3832 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3834 pbn_b2_bt_2_921600 }, 3835 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3837 pbn_b2_bt_2_921600 }, 3838 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3840 pbn_b2_bt_4_921600 }, 3841 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3843 pbn_b2_bt_4_921600 }, 3844 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3846 pbn_b2_bt_4_921600 }, 3847 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3849 pbn_b0_1_921600 }, 3850 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 3851 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3852 pbn_b0_1_921600 }, 3853 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3855 pbn_b0_1_921600 }, 3856 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 3857 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3858 pbn_b0_bt_2_921600 }, 3859 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 3860 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3861 pbn_b0_bt_2_921600 }, 3862 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 3863 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3864 pbn_b0_bt_2_921600 }, 3865 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 3866 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3867 pbn_b0_bt_4_921600 }, 3868 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 3869 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3870 pbn_b0_bt_4_921600 }, 3871 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 3872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3873 pbn_b0_bt_4_921600 }, 3874 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 3875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3876 pbn_b0_bt_8_921600 }, 3877 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 3878 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3879 pbn_b0_bt_8_921600 }, 3880 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3882 pbn_b0_bt_8_921600 }, 3883 3884 /* 3885 * Computone devices submitted by Doug McNash dmcnash@computone.com 3886 */ 3887 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 3888 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 3889 0, 0, pbn_computone_4 }, 3890 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 3891 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 3892 0, 0, pbn_computone_8 }, 3893 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 3894 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 3895 0, 0, pbn_computone_6 }, 3896 3897 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 3898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3899 pbn_oxsemi }, 3900 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 3901 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 3902 pbn_b0_bt_1_921600 }, 3903 3904 /* 3905 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 3906 */ 3907 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 3908 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3909 pbn_b0_bt_8_115200 }, 3910 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 3911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3912 pbn_b0_bt_8_115200 }, 3913 3914 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3916 pbn_b0_bt_2_115200 }, 3917 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3919 pbn_b0_bt_2_115200 }, 3920 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3922 pbn_b0_bt_2_115200 }, 3923 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3925 pbn_b0_bt_2_115200 }, 3926 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3928 pbn_b0_bt_2_115200 }, 3929 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3931 pbn_b0_bt_4_460800 }, 3932 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3934 pbn_b0_bt_4_460800 }, 3935 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3937 pbn_b0_bt_2_460800 }, 3938 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3940 pbn_b0_bt_2_460800 }, 3941 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3943 pbn_b0_bt_2_460800 }, 3944 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3946 pbn_b0_bt_1_115200 }, 3947 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3949 pbn_b0_bt_1_460800 }, 3950 3951 /* 3952 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 3953 * Cards are identified by their subsystem vendor IDs, which 3954 * (in hex) match the model number. 3955 * 3956 * Note that JC140x are RS422/485 cards which require ox950 3957 * ACR = 0x10, and as such are not currently fully supported. 3958 */ 3959 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 3960 0x1204, 0x0004, 0, 0, 3961 pbn_b0_4_921600 }, 3962 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 3963 0x1208, 0x0004, 0, 0, 3964 pbn_b0_4_921600 }, 3965 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 3966 0x1402, 0x0002, 0, 0, 3967 pbn_b0_2_921600 }, */ 3968 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 3969 0x1404, 0x0004, 0, 0, 3970 pbn_b0_4_921600 }, */ 3971 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 3972 0x1208, 0x0004, 0, 0, 3973 pbn_b0_4_921600 }, 3974 3975 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 3976 0x1204, 0x0004, 0, 0, 3977 pbn_b0_4_921600 }, 3978 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 3979 0x1208, 0x0004, 0, 0, 3980 pbn_b0_4_921600 }, 3981 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 3982 0x1208, 0x0004, 0, 0, 3983 pbn_b0_4_921600 }, 3984 /* 3985 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 3986 */ 3987 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3989 pbn_b1_1_1382400 }, 3990 3991 /* 3992 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 3993 */ 3994 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 3995 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3996 pbn_b1_1_1382400 }, 3997 3998 /* 3999 * RAStel 2 port modem, gerg@moreton.com.au 4000 */ 4001 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4002 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4003 pbn_b2_bt_2_115200 }, 4004 4005 /* 4006 * EKF addition for i960 Boards form EKF with serial port 4007 */ 4008 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4009 0xE4BF, PCI_ANY_ID, 0, 0, 4010 pbn_intel_i960 }, 4011 4012 /* 4013 * Xircom Cardbus/Ethernet combos 4014 */ 4015 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4017 pbn_b0_1_115200 }, 4018 /* 4019 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4020 */ 4021 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4022 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4023 pbn_b0_1_115200 }, 4024 4025 /* 4026 * Untested PCI modems, sent in from various folks... 4027 */ 4028 4029 /* 4030 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4031 */ 4032 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4033 0x1048, 0x1500, 0, 0, 4034 pbn_b1_1_115200 }, 4035 4036 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4037 0xFF00, 0, 0, 0, 4038 pbn_sgi_ioc3 }, 4039 4040 /* 4041 * HP Diva card 4042 */ 4043 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4044 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4045 pbn_b1_1_115200 }, 4046 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4047 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4048 pbn_b0_5_115200 }, 4049 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4051 pbn_b2_1_115200 }, 4052 4053 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4055 pbn_b3_2_115200 }, 4056 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4058 pbn_b3_4_115200 }, 4059 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4061 pbn_b3_8_115200 }, 4062 4063 /* 4064 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4065 */ 4066 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4067 PCI_ANY_ID, PCI_ANY_ID, 4068 0, 4069 0, pbn_exar_XR17C152 }, 4070 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4071 PCI_ANY_ID, PCI_ANY_ID, 4072 0, 4073 0, pbn_exar_XR17C154 }, 4074 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4075 PCI_ANY_ID, PCI_ANY_ID, 4076 0, 4077 0, pbn_exar_XR17C158 }, 4078 /* 4079 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs 4080 */ 4081 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4082 PCI_ANY_ID, PCI_ANY_ID, 4083 0, 4084 0, pbn_exar_XR17V352 }, 4085 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4086 PCI_ANY_ID, PCI_ANY_ID, 4087 0, 4088 0, pbn_exar_XR17V354 }, 4089 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4090 PCI_ANY_ID, PCI_ANY_ID, 4091 0, 4092 0, pbn_exar_XR17V358 }, 4093 4094 /* 4095 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4096 */ 4097 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4099 pbn_b0_1_115200 }, 4100 /* 4101 * ITE 4102 */ 4103 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4104 PCI_ANY_ID, PCI_ANY_ID, 4105 0, 0, 4106 pbn_b1_bt_1_115200 }, 4107 4108 /* 4109 * IntaShield IS-200 4110 */ 4111 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4113 pbn_b2_2_115200 }, 4114 /* 4115 * IntaShield IS-400 4116 */ 4117 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4119 pbn_b2_4_115200 }, 4120 /* 4121 * Perle PCI-RAS cards 4122 */ 4123 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4124 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4125 0, 0, pbn_b2_4_921600 }, 4126 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4127 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4128 0, 0, pbn_b2_8_921600 }, 4129 4130 /* 4131 * Mainpine series cards: Fairly standard layout but fools 4132 * parts of the autodetect in some cases and uses otherwise 4133 * unmatched communications subclasses in the PCI Express case 4134 */ 4135 4136 { /* RockForceDUO */ 4137 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4138 PCI_VENDOR_ID_MAINPINE, 0x0200, 4139 0, 0, pbn_b0_2_115200 }, 4140 { /* RockForceQUATRO */ 4141 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4142 PCI_VENDOR_ID_MAINPINE, 0x0300, 4143 0, 0, pbn_b0_4_115200 }, 4144 { /* RockForceDUO+ */ 4145 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4146 PCI_VENDOR_ID_MAINPINE, 0x0400, 4147 0, 0, pbn_b0_2_115200 }, 4148 { /* RockForceQUATRO+ */ 4149 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4150 PCI_VENDOR_ID_MAINPINE, 0x0500, 4151 0, 0, pbn_b0_4_115200 }, 4152 { /* RockForce+ */ 4153 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4154 PCI_VENDOR_ID_MAINPINE, 0x0600, 4155 0, 0, pbn_b0_2_115200 }, 4156 { /* RockForce+ */ 4157 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4158 PCI_VENDOR_ID_MAINPINE, 0x0700, 4159 0, 0, pbn_b0_4_115200 }, 4160 { /* RockForceOCTO+ */ 4161 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4162 PCI_VENDOR_ID_MAINPINE, 0x0800, 4163 0, 0, pbn_b0_8_115200 }, 4164 { /* RockForceDUO+ */ 4165 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4166 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4167 0, 0, pbn_b0_2_115200 }, 4168 { /* RockForceQUARTRO+ */ 4169 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4170 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4171 0, 0, pbn_b0_4_115200 }, 4172 { /* RockForceOCTO+ */ 4173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4174 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4175 0, 0, pbn_b0_8_115200 }, 4176 { /* RockForceD1 */ 4177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4178 PCI_VENDOR_ID_MAINPINE, 0x2000, 4179 0, 0, pbn_b0_1_115200 }, 4180 { /* RockForceF1 */ 4181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4182 PCI_VENDOR_ID_MAINPINE, 0x2100, 4183 0, 0, pbn_b0_1_115200 }, 4184 { /* RockForceD2 */ 4185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4186 PCI_VENDOR_ID_MAINPINE, 0x2200, 4187 0, 0, pbn_b0_2_115200 }, 4188 { /* RockForceF2 */ 4189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4190 PCI_VENDOR_ID_MAINPINE, 0x2300, 4191 0, 0, pbn_b0_2_115200 }, 4192 { /* RockForceD4 */ 4193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4194 PCI_VENDOR_ID_MAINPINE, 0x2400, 4195 0, 0, pbn_b0_4_115200 }, 4196 { /* RockForceF4 */ 4197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4198 PCI_VENDOR_ID_MAINPINE, 0x2500, 4199 0, 0, pbn_b0_4_115200 }, 4200 { /* RockForceD8 */ 4201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4202 PCI_VENDOR_ID_MAINPINE, 0x2600, 4203 0, 0, pbn_b0_8_115200 }, 4204 { /* RockForceF8 */ 4205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4206 PCI_VENDOR_ID_MAINPINE, 0x2700, 4207 0, 0, pbn_b0_8_115200 }, 4208 { /* IQ Express D1 */ 4209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4210 PCI_VENDOR_ID_MAINPINE, 0x3000, 4211 0, 0, pbn_b0_1_115200 }, 4212 { /* IQ Express F1 */ 4213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4214 PCI_VENDOR_ID_MAINPINE, 0x3100, 4215 0, 0, pbn_b0_1_115200 }, 4216 { /* IQ Express D2 */ 4217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4218 PCI_VENDOR_ID_MAINPINE, 0x3200, 4219 0, 0, pbn_b0_2_115200 }, 4220 { /* IQ Express F2 */ 4221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4222 PCI_VENDOR_ID_MAINPINE, 0x3300, 4223 0, 0, pbn_b0_2_115200 }, 4224 { /* IQ Express D4 */ 4225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4226 PCI_VENDOR_ID_MAINPINE, 0x3400, 4227 0, 0, pbn_b0_4_115200 }, 4228 { /* IQ Express F4 */ 4229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4230 PCI_VENDOR_ID_MAINPINE, 0x3500, 4231 0, 0, pbn_b0_4_115200 }, 4232 { /* IQ Express D8 */ 4233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4234 PCI_VENDOR_ID_MAINPINE, 0x3C00, 4235 0, 0, pbn_b0_8_115200 }, 4236 { /* IQ Express F8 */ 4237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4238 PCI_VENDOR_ID_MAINPINE, 0x3D00, 4239 0, 0, pbn_b0_8_115200 }, 4240 4241 4242 /* 4243 * PA Semi PA6T-1682M on-chip UART 4244 */ 4245 { PCI_VENDOR_ID_PASEMI, 0xa004, 4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4247 pbn_pasemi_1682M }, 4248 4249 /* 4250 * National Instruments 4251 */ 4252 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4254 pbn_b1_16_115200 }, 4255 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4257 pbn_b1_8_115200 }, 4258 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4260 pbn_b1_bt_4_115200 }, 4261 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4263 pbn_b1_bt_2_115200 }, 4264 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4266 pbn_b1_bt_4_115200 }, 4267 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4269 pbn_b1_bt_2_115200 }, 4270 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4272 pbn_b1_16_115200 }, 4273 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4275 pbn_b1_8_115200 }, 4276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4278 pbn_b1_bt_4_115200 }, 4279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4281 pbn_b1_bt_2_115200 }, 4282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4284 pbn_b1_bt_4_115200 }, 4285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4287 pbn_b1_bt_2_115200 }, 4288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4290 pbn_ni8430_2 }, 4291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_ni8430_2 }, 4294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_ni8430_4 }, 4297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4299 pbn_ni8430_4 }, 4300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4302 pbn_ni8430_8 }, 4303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4305 pbn_ni8430_8 }, 4306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4308 pbn_ni8430_16 }, 4309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4311 pbn_ni8430_16 }, 4312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4314 pbn_ni8430_2 }, 4315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4317 pbn_ni8430_2 }, 4318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4320 pbn_ni8430_4 }, 4321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4323 pbn_ni8430_4 }, 4324 4325 /* 4326 * ADDI-DATA GmbH communication cards <info@addi-data.com> 4327 */ 4328 { PCI_VENDOR_ID_ADDIDATA, 4329 PCI_DEVICE_ID_ADDIDATA_APCI7500, 4330 PCI_ANY_ID, 4331 PCI_ANY_ID, 4332 0, 4333 0, 4334 pbn_b0_4_115200 }, 4335 4336 { PCI_VENDOR_ID_ADDIDATA, 4337 PCI_DEVICE_ID_ADDIDATA_APCI7420, 4338 PCI_ANY_ID, 4339 PCI_ANY_ID, 4340 0, 4341 0, 4342 pbn_b0_2_115200 }, 4343 4344 { PCI_VENDOR_ID_ADDIDATA, 4345 PCI_DEVICE_ID_ADDIDATA_APCI7300, 4346 PCI_ANY_ID, 4347 PCI_ANY_ID, 4348 0, 4349 0, 4350 pbn_b0_1_115200 }, 4351 4352 { PCI_VENDOR_ID_ADDIDATA_OLD, 4353 PCI_DEVICE_ID_ADDIDATA_APCI7800, 4354 PCI_ANY_ID, 4355 PCI_ANY_ID, 4356 0, 4357 0, 4358 pbn_b1_8_115200 }, 4359 4360 { PCI_VENDOR_ID_ADDIDATA, 4361 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 4362 PCI_ANY_ID, 4363 PCI_ANY_ID, 4364 0, 4365 0, 4366 pbn_b0_4_115200 }, 4367 4368 { PCI_VENDOR_ID_ADDIDATA, 4369 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 4370 PCI_ANY_ID, 4371 PCI_ANY_ID, 4372 0, 4373 0, 4374 pbn_b0_2_115200 }, 4375 4376 { PCI_VENDOR_ID_ADDIDATA, 4377 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 4378 PCI_ANY_ID, 4379 PCI_ANY_ID, 4380 0, 4381 0, 4382 pbn_b0_1_115200 }, 4383 4384 { PCI_VENDOR_ID_ADDIDATA, 4385 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 4386 PCI_ANY_ID, 4387 PCI_ANY_ID, 4388 0, 4389 0, 4390 pbn_b0_4_115200 }, 4391 4392 { PCI_VENDOR_ID_ADDIDATA, 4393 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 4394 PCI_ANY_ID, 4395 PCI_ANY_ID, 4396 0, 4397 0, 4398 pbn_b0_2_115200 }, 4399 4400 { PCI_VENDOR_ID_ADDIDATA, 4401 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 4402 PCI_ANY_ID, 4403 PCI_ANY_ID, 4404 0, 4405 0, 4406 pbn_b0_1_115200 }, 4407 4408 { PCI_VENDOR_ID_ADDIDATA, 4409 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 4410 PCI_ANY_ID, 4411 PCI_ANY_ID, 4412 0, 4413 0, 4414 pbn_b0_8_115200 }, 4415 4416 { PCI_VENDOR_ID_ADDIDATA, 4417 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 4418 PCI_ANY_ID, 4419 PCI_ANY_ID, 4420 0, 4421 0, 4422 pbn_ADDIDATA_PCIe_4_3906250 }, 4423 4424 { PCI_VENDOR_ID_ADDIDATA, 4425 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 4426 PCI_ANY_ID, 4427 PCI_ANY_ID, 4428 0, 4429 0, 4430 pbn_ADDIDATA_PCIe_2_3906250 }, 4431 4432 { PCI_VENDOR_ID_ADDIDATA, 4433 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 4434 PCI_ANY_ID, 4435 PCI_ANY_ID, 4436 0, 4437 0, 4438 pbn_ADDIDATA_PCIe_1_3906250 }, 4439 4440 { PCI_VENDOR_ID_ADDIDATA, 4441 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 4442 PCI_ANY_ID, 4443 PCI_ANY_ID, 4444 0, 4445 0, 4446 pbn_ADDIDATA_PCIe_8_3906250 }, 4447 4448 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 4449 PCI_VENDOR_ID_IBM, 0x0299, 4450 0, 0, pbn_b0_bt_2_115200 }, 4451 4452 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 4453 0xA000, 0x1000, 4454 0, 0, pbn_b0_1_115200 }, 4455 4456 /* the 9901 is a rebranded 9912 */ 4457 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 4458 0xA000, 0x1000, 4459 0, 0, pbn_b0_1_115200 }, 4460 4461 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 4462 0xA000, 0x1000, 4463 0, 0, pbn_b0_1_115200 }, 4464 4465 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 4466 0xA000, 0x1000, 4467 0, 0, pbn_b0_1_115200 }, 4468 4469 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 4470 0xA000, 0x1000, 4471 0, 0, pbn_b0_1_115200 }, 4472 4473 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 4474 0xA000, 0x3002, 4475 0, 0, pbn_NETMOS9900_2s_115200 }, 4476 4477 /* 4478 * Best Connectivity and Rosewill PCI Multi I/O cards 4479 */ 4480 4481 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 4482 0xA000, 0x1000, 4483 0, 0, pbn_b0_1_115200 }, 4484 4485 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 4486 0xA000, 0x3002, 4487 0, 0, pbn_b0_bt_2_115200 }, 4488 4489 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 4490 0xA000, 0x3004, 4491 0, 0, pbn_b0_bt_4_115200 }, 4492 /* Intel CE4100 */ 4493 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_ce4100_1_115200 }, 4496 4497 /* 4498 * Cronyx Omega PCI 4499 */ 4500 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_omegapci }, 4503 4504 /* 4505 * Broadcom TruManage 4506 */ 4507 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_brcm_trumanage }, 4510 4511 /* 4512 * AgeStar as-prs2-009 4513 */ 4514 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 4515 PCI_ANY_ID, PCI_ANY_ID, 4516 0, 0, pbn_b0_bt_2_115200 }, 4517 4518 /* 4519 * WCH CH353 series devices: The 2S1P is handled by parport_serial 4520 * so not listed here. 4521 */ 4522 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 4523 PCI_ANY_ID, PCI_ANY_ID, 4524 0, 0, pbn_b0_bt_4_115200 }, 4525 4526 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 4527 PCI_ANY_ID, PCI_ANY_ID, 4528 0, 0, pbn_b0_bt_2_115200 }, 4529 4530 /* 4531 * Commtech, Inc. Fastcom adapters 4532 */ 4533 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 4534 PCI_ANY_ID, PCI_ANY_ID, 4535 0, 4536 0, pbn_b0_2_1152000_200 }, 4537 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 4538 PCI_ANY_ID, PCI_ANY_ID, 4539 0, 4540 0, pbn_b0_4_1152000_200 }, 4541 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 4542 PCI_ANY_ID, PCI_ANY_ID, 4543 0, 4544 0, pbn_b0_4_1152000_200 }, 4545 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 4546 PCI_ANY_ID, PCI_ANY_ID, 4547 0, 4548 0, pbn_b0_8_1152000_200 }, 4549 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 4550 PCI_ANY_ID, PCI_ANY_ID, 4551 0, 4552 0, pbn_exar_XR17V352 }, 4553 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 4554 PCI_ANY_ID, PCI_ANY_ID, 4555 0, 4556 0, pbn_exar_XR17V354 }, 4557 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 4558 PCI_ANY_ID, PCI_ANY_ID, 4559 0, 4560 0, pbn_exar_XR17V358 }, 4561 4562 /* 4563 * These entries match devices with class COMMUNICATION_SERIAL, 4564 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 4565 */ 4566 { PCI_ANY_ID, PCI_ANY_ID, 4567 PCI_ANY_ID, PCI_ANY_ID, 4568 PCI_CLASS_COMMUNICATION_SERIAL << 8, 4569 0xffff00, pbn_default }, 4570 { PCI_ANY_ID, PCI_ANY_ID, 4571 PCI_ANY_ID, PCI_ANY_ID, 4572 PCI_CLASS_COMMUNICATION_MODEM << 8, 4573 0xffff00, pbn_default }, 4574 { PCI_ANY_ID, PCI_ANY_ID, 4575 PCI_ANY_ID, PCI_ANY_ID, 4576 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 4577 0xffff00, pbn_default }, 4578 { 0, } 4579 }; 4580 4581 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 4582 pci_channel_state_t state) 4583 { 4584 struct serial_private *priv = pci_get_drvdata(dev); 4585 4586 if (state == pci_channel_io_perm_failure) 4587 return PCI_ERS_RESULT_DISCONNECT; 4588 4589 if (priv) 4590 pciserial_suspend_ports(priv); 4591 4592 pci_disable_device(dev); 4593 4594 return PCI_ERS_RESULT_NEED_RESET; 4595 } 4596 4597 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 4598 { 4599 int rc; 4600 4601 rc = pci_enable_device(dev); 4602 4603 if (rc) 4604 return PCI_ERS_RESULT_DISCONNECT; 4605 4606 pci_restore_state(dev); 4607 pci_save_state(dev); 4608 4609 return PCI_ERS_RESULT_RECOVERED; 4610 } 4611 4612 static void serial8250_io_resume(struct pci_dev *dev) 4613 { 4614 struct serial_private *priv = pci_get_drvdata(dev); 4615 4616 if (priv) 4617 pciserial_resume_ports(priv); 4618 } 4619 4620 static const struct pci_error_handlers serial8250_err_handler = { 4621 .error_detected = serial8250_io_error_detected, 4622 .slot_reset = serial8250_io_slot_reset, 4623 .resume = serial8250_io_resume, 4624 }; 4625 4626 static struct pci_driver serial_pci_driver = { 4627 .name = "serial", 4628 .probe = pciserial_init_one, 4629 .remove = pciserial_remove_one, 4630 #ifdef CONFIG_PM 4631 .suspend = pciserial_suspend_one, 4632 .resume = pciserial_resume_one, 4633 #endif 4634 .id_table = serial_pci_tbl, 4635 .err_handler = &serial8250_err_handler, 4636 }; 4637 4638 module_pci_driver(serial_pci_driver); 4639 4640 MODULE_LICENSE("GPL"); 4641 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 4642 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 4643