1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include "8250.h" 29 30 /* 31 * init function returns: 32 * > 0 - number of ports 33 * = 0 - use board->num_ports 34 * < 0 - error 35 */ 36 struct pci_serial_quirk { 37 u32 vendor; 38 u32 device; 39 u32 subvendor; 40 u32 subdevice; 41 int (*probe)(struct pci_dev *dev); 42 int (*init)(struct pci_dev *dev); 43 int (*setup)(struct serial_private *, 44 const struct pciserial_board *, 45 struct uart_8250_port *, int); 46 void (*exit)(struct pci_dev *dev); 47 }; 48 49 #define PCI_NUM_BAR_RESOURCES 6 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 55 struct pci_serial_quirk *quirk; 56 int line[0]; 57 }; 58 59 static int pci_default_setup(struct serial_private*, 60 const struct pciserial_board*, struct uart_8250_port *, int); 61 62 static void moan_device(const char *str, struct pci_dev *dev) 63 { 64 dev_err(&dev->dev, 65 "%s: %s\n" 66 "Please send the output of lspci -vv, this\n" 67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 68 "manufacturer and name of serial board or\n" 69 "modem board to rmk+serial@arm.linux.org.uk.\n", 70 pci_name(dev), str, dev->vendor, dev->device, 71 dev->subsystem_vendor, dev->subsystem_device); 72 } 73 74 static int 75 setup_port(struct serial_private *priv, struct uart_8250_port *port, 76 int bar, int offset, int regshift) 77 { 78 struct pci_dev *dev = priv->dev; 79 unsigned long base, len; 80 81 if (bar >= PCI_NUM_BAR_RESOURCES) 82 return -EINVAL; 83 84 base = pci_resource_start(dev, bar); 85 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 87 len = pci_resource_len(dev, bar); 88 89 if (!priv->remapped_bar[bar]) 90 priv->remapped_bar[bar] = ioremap_nocache(base, len); 91 if (!priv->remapped_bar[bar]) 92 return -ENOMEM; 93 94 port->port.iotype = UPIO_MEM; 95 port->port.iobase = 0; 96 port->port.mapbase = base + offset; 97 port->port.membase = priv->remapped_bar[bar] + offset; 98 port->port.regshift = regshift; 99 } else { 100 port->port.iotype = UPIO_PORT; 101 port->port.iobase = base + offset; 102 port->port.mapbase = 0; 103 port->port.membase = NULL; 104 port->port.regshift = 0; 105 } 106 return 0; 107 } 108 109 /* 110 * ADDI-DATA GmbH communication cards <info@addi-data.com> 111 */ 112 static int addidata_apci7800_setup(struct serial_private *priv, 113 const struct pciserial_board *board, 114 struct uart_8250_port *port, int idx) 115 { 116 unsigned int bar = 0, offset = board->first_offset; 117 bar = FL_GET_BASE(board->flags); 118 119 if (idx < 2) { 120 offset += idx * board->uart_offset; 121 } else if ((idx >= 2) && (idx < 4)) { 122 bar += 1; 123 offset += ((idx - 2) * board->uart_offset); 124 } else if ((idx >= 4) && (idx < 6)) { 125 bar += 2; 126 offset += ((idx - 4) * board->uart_offset); 127 } else if (idx >= 6) { 128 bar += 3; 129 offset += ((idx - 6) * board->uart_offset); 130 } 131 132 return setup_port(priv, port, bar, offset, board->reg_shift); 133 } 134 135 /* 136 * AFAVLAB uses a different mixture of BARs and offsets 137 * Not that ugly ;) -- HW 138 */ 139 static int 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 141 struct uart_8250_port *port, int idx) 142 { 143 unsigned int bar, offset = board->first_offset; 144 145 bar = FL_GET_BASE(board->flags); 146 if (idx < 4) 147 bar += idx; 148 else { 149 bar = 4; 150 offset += (idx - 4) * board->uart_offset; 151 } 152 153 return setup_port(priv, port, bar, offset, board->reg_shift); 154 } 155 156 /* 157 * HP's Remote Management Console. The Diva chip came in several 158 * different versions. N-class, L2000 and A500 have two Diva chips, each 159 * with 3 UARTs (the third UART on the second chip is unused). Superdome 160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 161 * one Diva chip, but it has been expanded to 5 UARTs. 162 */ 163 static int pci_hp_diva_init(struct pci_dev *dev) 164 { 165 int rc = 0; 166 167 switch (dev->subsystem_device) { 168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 171 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 172 rc = 3; 173 break; 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 175 rc = 2; 176 break; 177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 178 rc = 4; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 182 rc = 1; 183 break; 184 } 185 186 return rc; 187 } 188 189 /* 190 * HP's Diva chip puts the 4th/5th serial port further out, and 191 * some serial ports are supposed to be hidden on certain models. 192 */ 193 static int 194 pci_hp_diva_setup(struct serial_private *priv, 195 const struct pciserial_board *board, 196 struct uart_8250_port *port, int idx) 197 { 198 unsigned int offset = board->first_offset; 199 unsigned int bar = FL_GET_BASE(board->flags); 200 201 switch (priv->dev->subsystem_device) { 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 203 if (idx == 3) 204 idx++; 205 break; 206 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 207 if (idx > 0) 208 idx++; 209 if (idx > 2) 210 idx++; 211 break; 212 } 213 if (idx > 2) 214 offset = 0x18; 215 216 offset += idx * board->uart_offset; 217 218 return setup_port(priv, port, bar, offset, board->reg_shift); 219 } 220 221 /* 222 * Added for EKF Intel i960 serial boards 223 */ 224 static int pci_inteli960ni_init(struct pci_dev *dev) 225 { 226 unsigned long oldval; 227 228 if (!(dev->subsystem_device & 0x1000)) 229 return -ENODEV; 230 231 /* is firmware started? */ 232 pci_read_config_dword(dev, 0x44, (void *)&oldval); 233 if (oldval == 0x00001000L) { /* RESET value */ 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 235 return -ENODEV; 236 } 237 return 0; 238 } 239 240 /* 241 * Some PCI serial cards using the PLX 9050 PCI interface chip require 242 * that the card interrupt be explicitly enabled or disabled. This 243 * seems to be mainly needed on card using the PLX which also use I/O 244 * mapped memory. 245 */ 246 static int pci_plx9050_init(struct pci_dev *dev) 247 { 248 u8 irq_config; 249 void __iomem *p; 250 251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 252 moan_device("no memory in bar 0", dev); 253 return 0; 254 } 255 256 irq_config = 0x41; 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 259 irq_config = 0x43; 260 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 263 /* 264 * As the megawolf cards have the int pins active 265 * high, and have 2 UART chips, both ints must be 266 * enabled on the 9050. Also, the UARTS are set in 267 * 16450 mode by default, so we have to enable the 268 * 16C950 'enhanced' mode so that we can use the 269 * deep FIFOs 270 */ 271 irq_config = 0x5b; 272 /* 273 * enable/disable interrupts 274 */ 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 276 if (p == NULL) 277 return -ENOMEM; 278 writel(irq_config, p + 0x4c); 279 280 /* 281 * Read the register back to ensure that it took effect. 282 */ 283 readl(p + 0x4c); 284 iounmap(p); 285 286 return 0; 287 } 288 289 static void pci_plx9050_exit(struct pci_dev *dev) 290 { 291 u8 __iomem *p; 292 293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 294 return; 295 296 /* 297 * disable interrupts 298 */ 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 300 if (p != NULL) { 301 writel(0, p + 0x4c); 302 303 /* 304 * Read the register back to ensure that it took effect. 305 */ 306 readl(p + 0x4c); 307 iounmap(p); 308 } 309 } 310 311 #define NI8420_INT_ENABLE_REG 0x38 312 #define NI8420_INT_ENABLE_BIT 0x2000 313 314 static void pci_ni8420_exit(struct pci_dev *dev) 315 { 316 void __iomem *p; 317 unsigned long base, len; 318 unsigned int bar = 0; 319 320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 321 moan_device("no memory in bar", dev); 322 return; 323 } 324 325 base = pci_resource_start(dev, bar); 326 len = pci_resource_len(dev, bar); 327 p = ioremap_nocache(base, len); 328 if (p == NULL) 329 return; 330 331 /* Disable the CPU Interrupt */ 332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 333 p + NI8420_INT_ENABLE_REG); 334 iounmap(p); 335 } 336 337 338 /* MITE registers */ 339 #define MITE_IOWBSR1 0xc4 340 #define MITE_IOWCR1 0xf4 341 #define MITE_LCIMR1 0x08 342 #define MITE_LCIMR2 0x10 343 344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 345 346 static void pci_ni8430_exit(struct pci_dev *dev) 347 { 348 void __iomem *p; 349 unsigned long base, len; 350 unsigned int bar = 0; 351 352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 353 moan_device("no memory in bar", dev); 354 return; 355 } 356 357 base = pci_resource_start(dev, bar); 358 len = pci_resource_len(dev, bar); 359 p = ioremap_nocache(base, len); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366 } 367 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369 static int 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372 { 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387 } 388 389 /* 390 * This does initialization for PMC OCTALPRO cards: 391 * maps the device memory, resets the UARTs (needed, bc 392 * if the module is removed and inserted again, the card 393 * is in the sleep mode) and enables global interrupt. 394 */ 395 396 /* global control register offset for SBS PMC-OctalPro */ 397 #define OCT_REG_CR_OFF 0x500 398 399 static int sbs_init(struct pci_dev *dev) 400 { 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417 } 418 419 /* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423 static void sbs_exit(struct pci_dev *dev) 424 { 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432 } 433 434 /* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464 static int pci_siig10x_init(struct pci_dev *dev) 465 { 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489 } 490 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494 static int pci_siig20x_init(struct pci_dev *dev) 495 { 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509 } 510 511 static int pci_siig_init(struct pci_dev *dev) 512 { 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 else if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522 } 523 524 static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527 { 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536 } 537 538 /* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543 static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545 }; 546 547 static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553 }; 554 555 static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560 }; 561 562 static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565 }; 566 567 static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570 } timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575 }; 576 577 /* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583 static int pci_timedia_probe(struct pci_dev *dev) 584 { 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 dev_info(&dev->dev, 591 "ignoring Timedia subdevice %04x for parport_serial\n", 592 dev->subsystem_device); 593 return -ENODEV; 594 } 595 596 return 0; 597 } 598 599 static int pci_timedia_init(struct pci_dev *dev) 600 { 601 const unsigned short *ids; 602 int i, j; 603 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 605 ids = timedia_data[i].ids; 606 for (j = 0; ids[j]; j++) 607 if (dev->subsystem_device == ids[j]) 608 return timedia_data[i].num; 609 } 610 return 0; 611 } 612 613 /* 614 * Timedia/SUNIX uses a mixture of BARs and offsets 615 * Ugh, this is ugly as all hell --- TYT 616 */ 617 static int 618 pci_timedia_setup(struct serial_private *priv, 619 const struct pciserial_board *board, 620 struct uart_8250_port *port, int idx) 621 { 622 unsigned int bar = 0, offset = board->first_offset; 623 624 switch (idx) { 625 case 0: 626 bar = 0; 627 break; 628 case 1: 629 offset = board->uart_offset; 630 bar = 0; 631 break; 632 case 2: 633 bar = 1; 634 break; 635 case 3: 636 offset = board->uart_offset; 637 /* FALLTHROUGH */ 638 case 4: /* BAR 2 */ 639 case 5: /* BAR 3 */ 640 case 6: /* BAR 4 */ 641 case 7: /* BAR 5 */ 642 bar = idx - 2; 643 } 644 645 return setup_port(priv, port, bar, offset, board->reg_shift); 646 } 647 648 /* 649 * Some Titan cards are also a little weird 650 */ 651 static int 652 titan_400l_800l_setup(struct serial_private *priv, 653 const struct pciserial_board *board, 654 struct uart_8250_port *port, int idx) 655 { 656 unsigned int bar, offset = board->first_offset; 657 658 switch (idx) { 659 case 0: 660 bar = 1; 661 break; 662 case 1: 663 bar = 2; 664 break; 665 default: 666 bar = 4; 667 offset = (idx - 2) * board->uart_offset; 668 } 669 670 return setup_port(priv, port, bar, offset, board->reg_shift); 671 } 672 673 static int pci_xircom_init(struct pci_dev *dev) 674 { 675 msleep(100); 676 return 0; 677 } 678 679 static int pci_ni8420_init(struct pci_dev *dev) 680 { 681 void __iomem *p; 682 unsigned long base, len; 683 unsigned int bar = 0; 684 685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 686 moan_device("no memory in bar", dev); 687 return 0; 688 } 689 690 base = pci_resource_start(dev, bar); 691 len = pci_resource_len(dev, bar); 692 p = ioremap_nocache(base, len); 693 if (p == NULL) 694 return -ENOMEM; 695 696 /* Enable CPU Interrupt */ 697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 698 p + NI8420_INT_ENABLE_REG); 699 700 iounmap(p); 701 return 0; 702 } 703 704 #define MITE_IOWBSR1_WSIZE 0xa 705 #define MITE_IOWBSR1_WIN_OFFSET 0x800 706 #define MITE_IOWBSR1_WENAB (1 << 7) 707 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 708 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 709 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 710 711 static int pci_ni8430_init(struct pci_dev *dev) 712 { 713 void __iomem *p; 714 unsigned long base, len; 715 u32 device_window; 716 unsigned int bar = 0; 717 718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 719 moan_device("no memory in bar", dev); 720 return 0; 721 } 722 723 base = pci_resource_start(dev, bar); 724 len = pci_resource_len(dev, bar); 725 p = ioremap_nocache(base, len); 726 if (p == NULL) 727 return -ENOMEM; 728 729 /* Set device window address and size in BAR0 */ 730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 732 writel(device_window, p + MITE_IOWBSR1); 733 734 /* Set window access to go to RAMSEL IO address space */ 735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 736 p + MITE_IOWCR1); 737 738 /* Enable IO Bus Interrupt 0 */ 739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 740 741 /* Enable CPU Interrupt */ 742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 743 744 iounmap(p); 745 return 0; 746 } 747 748 /* UART Port Control Register */ 749 #define NI8430_PORTCON 0x0f 750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 751 752 static int 753 pci_ni8430_setup(struct serial_private *priv, 754 const struct pciserial_board *board, 755 struct uart_8250_port *port, int idx) 756 { 757 void __iomem *p; 758 unsigned long base, len; 759 unsigned int bar, offset = board->first_offset; 760 761 if (idx >= board->num_ports) 762 return 1; 763 764 bar = FL_GET_BASE(board->flags); 765 offset += idx * board->uart_offset; 766 767 base = pci_resource_start(priv->dev, bar); 768 len = pci_resource_len(priv->dev, bar); 769 p = ioremap_nocache(base, len); 770 771 /* enable the transceiver */ 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 773 p + offset + NI8430_PORTCON); 774 775 iounmap(p); 776 777 return setup_port(priv, port, bar, offset, board->reg_shift); 778 } 779 780 static int pci_netmos_9900_setup(struct serial_private *priv, 781 const struct pciserial_board *board, 782 struct uart_8250_port *port, int idx) 783 { 784 unsigned int bar; 785 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 788 /* netmos apparently orders BARs by datasheet layout, so serial 789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 790 */ 791 bar = 3 * idx; 792 793 return setup_port(priv, port, bar, 0, board->reg_shift); 794 } else { 795 return pci_default_setup(priv, board, port, idx); 796 } 797 } 798 799 /* the 99xx series comes with a range of device IDs and a variety 800 * of capabilities: 801 * 802 * 9900 has varying capabilities and can cascade to sub-controllers 803 * (cascading should be purely internal) 804 * 9904 is hardwired with 4 serial ports 805 * 9912 and 9922 are hardwired with 2 serial ports 806 */ 807 static int pci_netmos_9900_numports(struct pci_dev *dev) 808 { 809 unsigned int c = dev->class; 810 unsigned int pi; 811 unsigned short sub_serports; 812 813 pi = (c & 0xff); 814 815 if (pi == 2) { 816 return 1; 817 } else if ((pi == 0) && 818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 819 /* two possibilities: 0x30ps encodes number of parallel and 820 * serial ports, or 0x1000 indicates *something*. This is not 821 * immediately obvious, since the 2s1p+4s configuration seems 822 * to offer all functionality on functions 0..2, while still 823 * advertising the same function 3 as the 4s+2s1p config. 824 */ 825 sub_serports = dev->subsystem_device & 0xf; 826 if (sub_serports > 0) { 827 return sub_serports; 828 } else { 829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 830 return 0; 831 } 832 } 833 834 moan_device("unknown NetMos/Mostech program interface", dev); 835 return 0; 836 } 837 838 static int pci_netmos_init(struct pci_dev *dev) 839 { 840 /* subdevice 0x00PS means <P> parallel, <S> serial */ 841 unsigned int num_serial = dev->subsystem_device & 0xf; 842 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 844 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 845 return 0; 846 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 848 dev->subsystem_device == 0x0299) 849 return 0; 850 851 switch (dev->device) { /* FALLTHROUGH on all */ 852 case PCI_DEVICE_ID_NETMOS_9904: 853 case PCI_DEVICE_ID_NETMOS_9912: 854 case PCI_DEVICE_ID_NETMOS_9922: 855 case PCI_DEVICE_ID_NETMOS_9900: 856 num_serial = pci_netmos_9900_numports(dev); 857 break; 858 859 default: 860 if (num_serial == 0 ) { 861 moan_device("unknown NetMos/Mostech device", dev); 862 } 863 } 864 865 if (num_serial == 0) 866 return -ENODEV; 867 868 return num_serial; 869 } 870 871 /* 872 * These chips are available with optionally one parallel port and up to 873 * two serial ports. Unfortunately they all have the same product id. 874 * 875 * Basic configuration is done over a region of 32 I/O ports. The base 876 * ioport is called INTA or INTC, depending on docs/other drivers. 877 * 878 * The region of the 32 I/O ports is configured in POSIO0R... 879 */ 880 881 /* registers */ 882 #define ITE_887x_MISCR 0x9c 883 #define ITE_887x_INTCBAR 0x78 884 #define ITE_887x_UARTBAR 0x7c 885 #define ITE_887x_PS0BAR 0x10 886 #define ITE_887x_POSIO0 0x60 887 888 /* I/O space size */ 889 #define ITE_887x_IOSIZE 32 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 895 #define ITE_887x_POSIO_SPEED (3 << 29) 896 /* enable IO_Space bit */ 897 #define ITE_887x_POSIO_ENABLE (1 << 31) 898 899 static int pci_ite887x_init(struct pci_dev *dev) 900 { 901 /* inta_addr are the configuration addresses of the ITE */ 902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 903 0x200, 0x280, 0 }; 904 int ret, i, type; 905 struct resource *iobase = NULL; 906 u32 miscr, uartbar, ioport; 907 908 /* search for the base-ioport */ 909 i = 0; 910 while (inta_addr[i] && iobase == NULL) { 911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 912 "ite887x"); 913 if (iobase != NULL) { 914 /* write POSIO0R - speed | size | ioport */ 915 pci_write_config_dword(dev, ITE_887x_POSIO0, 916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 918 /* write INTCBAR - ioport */ 919 pci_write_config_dword(dev, ITE_887x_INTCBAR, 920 inta_addr[i]); 921 ret = inb(inta_addr[i]); 922 if (ret != 0xff) { 923 /* ioport connected */ 924 break; 925 } 926 release_region(iobase->start, ITE_887x_IOSIZE); 927 iobase = NULL; 928 } 929 i++; 930 } 931 932 if (!inta_addr[i]) { 933 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 934 return -ENODEV; 935 } 936 937 /* start of undocumented type checking (see parport_pc.c) */ 938 type = inb(iobase->start + 0x18) & 0x0f; 939 940 switch (type) { 941 case 0x2: /* ITE8871 (1P) */ 942 case 0xa: /* ITE8875 (1P) */ 943 ret = 0; 944 break; 945 case 0xe: /* ITE8872 (2S1P) */ 946 ret = 2; 947 break; 948 case 0x6: /* ITE8873 (1S) */ 949 ret = 1; 950 break; 951 case 0x8: /* ITE8874 (2S) */ 952 ret = 2; 953 break; 954 default: 955 moan_device("Unknown ITE887x", dev); 956 ret = -ENODEV; 957 } 958 959 /* configure all serial ports */ 960 for (i = 0; i < ret; i++) { 961 /* read the I/O port from the device */ 962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 963 &ioport); 964 ioport &= 0x0000FF00; /* the actual base address */ 965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 967 ITE_887x_POSIO_IOSIZE_8 | ioport); 968 969 /* write the ioport to the UARTBAR */ 970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 972 uartbar |= (ioport << (16 * i)); /* set the ioport */ 973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 974 975 /* get current config */ 976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 977 /* disable interrupts (UARTx_Routing[3:0]) */ 978 miscr &= ~(0xf << (12 - 4 * i)); 979 /* activate the UART (UARTx_En) */ 980 miscr |= 1 << (23 - i); 981 /* write new config with activated UART */ 982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 983 } 984 985 if (ret <= 0) { 986 /* the device has no UARTs if we get here */ 987 release_region(iobase->start, ITE_887x_IOSIZE); 988 } 989 990 return ret; 991 } 992 993 static void pci_ite887x_exit(struct pci_dev *dev) 994 { 995 u32 ioport; 996 /* the ioport is bit 0-15 in POSIO0R */ 997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 998 ioport &= 0xffff; 999 release_region(ioport, ITE_887x_IOSIZE); 1000 } 1001 1002 /* 1003 * Oxford Semiconductor Inc. 1004 * Check that device is part of the Tornado range of devices, then determine 1005 * the number of ports available on the device. 1006 */ 1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1008 { 1009 u8 __iomem *p; 1010 unsigned long deviceID; 1011 unsigned int number_uarts = 0; 1012 1013 /* OxSemi Tornado devices are all 0xCxxx */ 1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1015 (dev->device & 0xF000) != 0xC000) 1016 return 0; 1017 1018 p = pci_iomap(dev, 0, 5); 1019 if (p == NULL) 1020 return -ENOMEM; 1021 1022 deviceID = ioread32(p); 1023 /* Tornado device */ 1024 if (deviceID == 0x07000200) { 1025 number_uarts = ioread8(p + 4); 1026 dev_dbg(&dev->dev, 1027 "%d ports detected on Oxford PCI Express device\n", 1028 number_uarts); 1029 } 1030 pci_iounmap(dev, p); 1031 return number_uarts; 1032 } 1033 1034 static int pci_asix_setup(struct serial_private *priv, 1035 const struct pciserial_board *board, 1036 struct uart_8250_port *port, int idx) 1037 { 1038 port->bugs |= UART_BUG_PARITY; 1039 return pci_default_setup(priv, board, port, idx); 1040 } 1041 1042 /* Quatech devices have their own extra interface features */ 1043 1044 struct quatech_feature { 1045 u16 devid; 1046 bool amcc; 1047 }; 1048 1049 #define QPCR_TEST_FOR1 0x3F 1050 #define QPCR_TEST_GET1 0x00 1051 #define QPCR_TEST_FOR2 0x40 1052 #define QPCR_TEST_GET2 0x40 1053 #define QPCR_TEST_FOR3 0x80 1054 #define QPCR_TEST_GET3 0x40 1055 #define QPCR_TEST_FOR4 0xC0 1056 #define QPCR_TEST_GET4 0x80 1057 1058 #define QOPR_CLOCK_X1 0x0000 1059 #define QOPR_CLOCK_X2 0x0001 1060 #define QOPR_CLOCK_X4 0x0002 1061 #define QOPR_CLOCK_X8 0x0003 1062 #define QOPR_CLOCK_RATE_MASK 0x0003 1063 1064 1065 static struct quatech_feature quatech_cards[] = { 1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1085 { 0, } 1086 }; 1087 1088 static int pci_quatech_amcc(u16 devid) 1089 { 1090 struct quatech_feature *qf = &quatech_cards[0]; 1091 while (qf->devid) { 1092 if (qf->devid == devid) 1093 return qf->amcc; 1094 qf++; 1095 } 1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1097 return 0; 1098 }; 1099 1100 static int pci_quatech_rqopr(struct uart_8250_port *port) 1101 { 1102 unsigned long base = port->port.iobase; 1103 u8 LCR, val; 1104 1105 LCR = inb(base + UART_LCR); 1106 outb(0xBF, base + UART_LCR); 1107 val = inb(base + UART_SCR); 1108 outb(LCR, base + UART_LCR); 1109 return val; 1110 } 1111 1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1113 { 1114 unsigned long base = port->port.iobase; 1115 u8 LCR, val; 1116 1117 LCR = inb(base + UART_LCR); 1118 outb(0xBF, base + UART_LCR); 1119 val = inb(base + UART_SCR); 1120 outb(qopr, base + UART_SCR); 1121 outb(LCR, base + UART_LCR); 1122 } 1123 1124 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1125 { 1126 unsigned long base = port->port.iobase; 1127 u8 LCR, val, qmcr; 1128 1129 LCR = inb(base + UART_LCR); 1130 outb(0xBF, base + UART_LCR); 1131 val = inb(base + UART_SCR); 1132 outb(val | 0x10, base + UART_SCR); 1133 qmcr = inb(base + UART_MCR); 1134 outb(val, base + UART_SCR); 1135 outb(LCR, base + UART_LCR); 1136 1137 return qmcr; 1138 } 1139 1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1141 { 1142 unsigned long base = port->port.iobase; 1143 u8 LCR, val; 1144 1145 LCR = inb(base + UART_LCR); 1146 outb(0xBF, base + UART_LCR); 1147 val = inb(base + UART_SCR); 1148 outb(val | 0x10, base + UART_SCR); 1149 outb(qmcr, base + UART_MCR); 1150 outb(val, base + UART_SCR); 1151 outb(LCR, base + UART_LCR); 1152 } 1153 1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1155 { 1156 unsigned long base = port->port.iobase; 1157 u8 LCR, val; 1158 1159 LCR = inb(base + UART_LCR); 1160 outb(0xBF, base + UART_LCR); 1161 val = inb(base + UART_SCR); 1162 if (val & 0x20) { 1163 outb(0x80, UART_LCR); 1164 if (!(inb(UART_SCR) & 0x20)) { 1165 outb(LCR, base + UART_LCR); 1166 return 1; 1167 } 1168 } 1169 return 0; 1170 } 1171 1172 static int pci_quatech_test(struct uart_8250_port *port) 1173 { 1174 u8 reg; 1175 u8 qopr = pci_quatech_rqopr(port); 1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1177 reg = pci_quatech_rqopr(port) & 0xC0; 1178 if (reg != QPCR_TEST_GET1) 1179 return -EINVAL; 1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1181 reg = pci_quatech_rqopr(port) & 0xC0; 1182 if (reg != QPCR_TEST_GET2) 1183 return -EINVAL; 1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1185 reg = pci_quatech_rqopr(port) & 0xC0; 1186 if (reg != QPCR_TEST_GET3) 1187 return -EINVAL; 1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1189 reg = pci_quatech_rqopr(port) & 0xC0; 1190 if (reg != QPCR_TEST_GET4) 1191 return -EINVAL; 1192 1193 pci_quatech_wqopr(port, qopr); 1194 return 0; 1195 } 1196 1197 static int pci_quatech_clock(struct uart_8250_port *port) 1198 { 1199 u8 qopr, reg, set; 1200 unsigned long clock; 1201 1202 if (pci_quatech_test(port) < 0) 1203 return 1843200; 1204 1205 qopr = pci_quatech_rqopr(port); 1206 1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1208 reg = pci_quatech_rqopr(port); 1209 if (reg & QOPR_CLOCK_X8) { 1210 clock = 1843200; 1211 goto out; 1212 } 1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (!(reg & QOPR_CLOCK_X8)) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 reg &= QOPR_CLOCK_X8; 1220 if (reg == QOPR_CLOCK_X2) { 1221 clock = 3685400; 1222 set = QOPR_CLOCK_X2; 1223 } else if (reg == QOPR_CLOCK_X4) { 1224 clock = 7372800; 1225 set = QOPR_CLOCK_X4; 1226 } else if (reg == QOPR_CLOCK_X8) { 1227 clock = 14745600; 1228 set = QOPR_CLOCK_X8; 1229 } else { 1230 clock = 1843200; 1231 set = QOPR_CLOCK_X1; 1232 } 1233 qopr &= ~QOPR_CLOCK_RATE_MASK; 1234 qopr |= set; 1235 1236 out: 1237 pci_quatech_wqopr(port, qopr); 1238 return clock; 1239 } 1240 1241 static int pci_quatech_rs422(struct uart_8250_port *port) 1242 { 1243 u8 qmcr; 1244 int rs422 = 0; 1245 1246 if (!pci_quatech_has_qmcr(port)) 1247 return 0; 1248 qmcr = pci_quatech_rqmcr(port); 1249 pci_quatech_wqmcr(port, 0xFF); 1250 if (pci_quatech_rqmcr(port)) 1251 rs422 = 1; 1252 pci_quatech_wqmcr(port, qmcr); 1253 return rs422; 1254 } 1255 1256 static int pci_quatech_init(struct pci_dev *dev) 1257 { 1258 if (pci_quatech_amcc(dev->device)) { 1259 unsigned long base = pci_resource_start(dev, 0); 1260 if (base) { 1261 u32 tmp; 1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1263 tmp = inl(base + 0x3c); 1264 outl(tmp | 0x01000000, base + 0x3c); 1265 outl(tmp &= ~0x01000000, base + 0x3c); 1266 } 1267 } 1268 return 0; 1269 } 1270 1271 static int pci_quatech_setup(struct serial_private *priv, 1272 const struct pciserial_board *board, 1273 struct uart_8250_port *port, int idx) 1274 { 1275 /* Needed by pci_quatech calls below */ 1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1277 /* Set up the clocking */ 1278 port->port.uartclk = pci_quatech_clock(port); 1279 /* For now just warn about RS422 */ 1280 if (pci_quatech_rs422(port)) 1281 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1282 return pci_default_setup(priv, board, port, idx); 1283 } 1284 1285 static void pci_quatech_exit(struct pci_dev *dev) 1286 { 1287 } 1288 1289 static int pci_default_setup(struct serial_private *priv, 1290 const struct pciserial_board *board, 1291 struct uart_8250_port *port, int idx) 1292 { 1293 unsigned int bar, offset = board->first_offset, maxnr; 1294 1295 bar = FL_GET_BASE(board->flags); 1296 if (board->flags & FL_BASE_BARS) 1297 bar += idx; 1298 else 1299 offset += idx * board->uart_offset; 1300 1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1302 (board->reg_shift + 3); 1303 1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1305 return 1; 1306 1307 return setup_port(priv, port, bar, offset, board->reg_shift); 1308 } 1309 1310 static int pci_pericom_setup(struct serial_private *priv, 1311 const struct pciserial_board *board, 1312 struct uart_8250_port *port, int idx) 1313 { 1314 unsigned int bar, offset = board->first_offset, maxnr; 1315 1316 bar = FL_GET_BASE(board->flags); 1317 if (board->flags & FL_BASE_BARS) 1318 bar += idx; 1319 else 1320 offset += idx * board->uart_offset; 1321 1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1323 (board->reg_shift + 3); 1324 1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1326 return 1; 1327 1328 port->port.uartclk = 14745600; 1329 1330 return setup_port(priv, port, bar, offset, board->reg_shift); 1331 } 1332 1333 static int 1334 ce4100_serial_setup(struct serial_private *priv, 1335 const struct pciserial_board *board, 1336 struct uart_8250_port *port, int idx) 1337 { 1338 int ret; 1339 1340 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1341 port->port.iotype = UPIO_MEM32; 1342 port->port.type = PORT_XSCALE; 1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1344 port->port.regshift = 2; 1345 1346 return ret; 1347 } 1348 1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1351 1352 #define BYT_PRV_CLK 0x800 1353 #define BYT_PRV_CLK_EN (1 << 0) 1354 #define BYT_PRV_CLK_M_VAL_SHIFT 1 1355 #define BYT_PRV_CLK_N_VAL_SHIFT 16 1356 #define BYT_PRV_CLK_UPDATE (1 << 31) 1357 1358 #define BYT_GENERAL_REG 0x808 1359 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3) 1360 1361 #define BYT_TX_OVF_INT 0x820 1362 #define BYT_TX_OVF_INT_MASK (1 << 1) 1363 1364 static void 1365 byt_set_termios(struct uart_port *p, struct ktermios *termios, 1366 struct ktermios *old) 1367 { 1368 unsigned int baud = tty_termios_baud_rate(termios); 1369 unsigned int m, n; 1370 u32 reg; 1371 1372 /* 1373 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1374 * dividers must be adjusted. 1375 * 1376 * uartclk = (m / n) * 100 MHz, where m <= n 1377 */ 1378 switch (baud) { 1379 case 500000: 1380 case 1000000: 1381 case 2000000: 1382 case 4000000: 1383 m = 64; 1384 n = 100; 1385 p->uartclk = 64000000; 1386 break; 1387 case 3500000: 1388 m = 56; 1389 n = 100; 1390 p->uartclk = 56000000; 1391 break; 1392 case 1500000: 1393 case 3000000: 1394 m = 48; 1395 n = 100; 1396 p->uartclk = 48000000; 1397 break; 1398 case 2500000: 1399 m = 40; 1400 n = 100; 1401 p->uartclk = 40000000; 1402 break; 1403 default: 1404 m = 2304; 1405 n = 3125; 1406 p->uartclk = 73728000; 1407 } 1408 1409 /* Reset the clock */ 1410 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1411 writel(reg, p->membase + BYT_PRV_CLK); 1412 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1413 writel(reg, p->membase + BYT_PRV_CLK); 1414 1415 /* 1416 * If auto-handshake mechanism is not enabled, 1417 * disable rts_n override 1418 */ 1419 reg = readl(p->membase + BYT_GENERAL_REG); 1420 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE; 1421 if (termios->c_cflag & CRTSCTS) 1422 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE; 1423 writel(reg, p->membase + BYT_GENERAL_REG); 1424 1425 serial8250_do_set_termios(p, termios, old); 1426 } 1427 1428 static bool byt_dma_filter(struct dma_chan *chan, void *param) 1429 { 1430 return chan->chan_id == *(int *)param; 1431 } 1432 1433 static int 1434 byt_serial_setup(struct serial_private *priv, 1435 const struct pciserial_board *board, 1436 struct uart_8250_port *port, int idx) 1437 { 1438 struct uart_8250_dma *dma; 1439 int ret; 1440 1441 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL); 1442 if (!dma) 1443 return -ENOMEM; 1444 1445 switch (priv->dev->device) { 1446 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1447 dma->rx_chan_id = 3; 1448 dma->tx_chan_id = 2; 1449 break; 1450 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1451 dma->rx_chan_id = 5; 1452 dma->tx_chan_id = 4; 1453 break; 1454 default: 1455 return -EINVAL; 1456 } 1457 1458 dma->rxconf.slave_id = dma->rx_chan_id; 1459 dma->rxconf.src_maxburst = 16; 1460 1461 dma->txconf.slave_id = dma->tx_chan_id; 1462 dma->txconf.dst_maxburst = 16; 1463 1464 dma->fn = byt_dma_filter; 1465 dma->rx_param = &dma->rx_chan_id; 1466 dma->tx_param = &dma->tx_chan_id; 1467 1468 ret = pci_default_setup(priv, board, port, idx); 1469 port->port.iotype = UPIO_MEM; 1470 port->port.type = PORT_16550A; 1471 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1472 port->port.set_termios = byt_set_termios; 1473 port->port.fifosize = 64; 1474 port->tx_loadsz = 64; 1475 port->dma = dma; 1476 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1477 1478 /* Disable Tx counter interrupts */ 1479 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1480 1481 return ret; 1482 } 1483 1484 static int 1485 pci_omegapci_setup(struct serial_private *priv, 1486 const struct pciserial_board *board, 1487 struct uart_8250_port *port, int idx) 1488 { 1489 return setup_port(priv, port, 2, idx * 8, 0); 1490 } 1491 1492 static int 1493 pci_brcm_trumanage_setup(struct serial_private *priv, 1494 const struct pciserial_board *board, 1495 struct uart_8250_port *port, int idx) 1496 { 1497 int ret = pci_default_setup(priv, board, port, idx); 1498 1499 port->port.type = PORT_BRCM_TRUMANAGE; 1500 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1501 return ret; 1502 } 1503 1504 static int pci_fintek_setup(struct serial_private *priv, 1505 const struct pciserial_board *board, 1506 struct uart_8250_port *port, int idx) 1507 { 1508 struct pci_dev *pdev = priv->dev; 1509 unsigned long base; 1510 unsigned long iobase; 1511 unsigned long ciobase = 0; 1512 u8 config_base; 1513 1514 /* 1515 * We are supposed to be able to read these from the PCI config space, 1516 * but the values there don't seem to match what we need to use, so 1517 * just use these hard-coded values for now, as they are correct. 1518 */ 1519 switch (idx) { 1520 case 0: iobase = 0xe000; config_base = 0x40; break; 1521 case 1: iobase = 0xe008; config_base = 0x48; break; 1522 case 2: iobase = 0xe010; config_base = 0x50; break; 1523 case 3: iobase = 0xe018; config_base = 0x58; break; 1524 case 4: iobase = 0xe020; config_base = 0x60; break; 1525 case 5: iobase = 0xe028; config_base = 0x68; break; 1526 case 6: iobase = 0xe030; config_base = 0x70; break; 1527 case 7: iobase = 0xe038; config_base = 0x78; break; 1528 case 8: iobase = 0xe040; config_base = 0x80; break; 1529 case 9: iobase = 0xe048; config_base = 0x88; break; 1530 case 10: iobase = 0xe050; config_base = 0x90; break; 1531 case 11: iobase = 0xe058; config_base = 0x98; break; 1532 default: 1533 /* Unknown number of ports, get out of here */ 1534 return -EINVAL; 1535 } 1536 1537 if (idx < 4) { 1538 base = pci_resource_start(priv->dev, 3); 1539 ciobase = (int)(base + (0x8 * idx)); 1540 } 1541 1542 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n", 1543 __func__, idx, iobase, ciobase, config_base); 1544 1545 /* Enable UART I/O port */ 1546 pci_write_config_byte(pdev, config_base + 0x00, 0x01); 1547 1548 /* Select 128-byte FIFO and 8x FIFO threshold */ 1549 pci_write_config_byte(pdev, config_base + 0x01, 0x33); 1550 1551 /* LSB UART */ 1552 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff)); 1553 1554 /* MSB UART */ 1555 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8)); 1556 1557 /* irq number, this usually fails, but the spec says to do it anyway. */ 1558 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq); 1559 1560 port->port.iotype = UPIO_PORT; 1561 port->port.iobase = iobase; 1562 port->port.mapbase = 0; 1563 port->port.membase = NULL; 1564 port->port.regshift = 0; 1565 1566 return 0; 1567 } 1568 1569 static int skip_tx_en_setup(struct serial_private *priv, 1570 const struct pciserial_board *board, 1571 struct uart_8250_port *port, int idx) 1572 { 1573 port->port.flags |= UPF_NO_TXEN_TEST; 1574 dev_dbg(&priv->dev->dev, 1575 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1576 priv->dev->vendor, priv->dev->device, 1577 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1578 1579 return pci_default_setup(priv, board, port, idx); 1580 } 1581 1582 static void kt_handle_break(struct uart_port *p) 1583 { 1584 struct uart_8250_port *up = 1585 container_of(p, struct uart_8250_port, port); 1586 /* 1587 * On receipt of a BI, serial device in Intel ME (Intel 1588 * management engine) needs to have its fifos cleared for sane 1589 * SOL (Serial Over Lan) output. 1590 */ 1591 serial8250_clear_and_reinit_fifos(up); 1592 } 1593 1594 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1595 { 1596 struct uart_8250_port *up = 1597 container_of(p, struct uart_8250_port, port); 1598 unsigned int val; 1599 1600 /* 1601 * When the Intel ME (management engine) gets reset its serial 1602 * port registers could return 0 momentarily. Functions like 1603 * serial8250_console_write, read and save the IER, perform 1604 * some operation and then restore it. In order to avoid 1605 * setting IER register inadvertently to 0, if the value read 1606 * is 0, double check with ier value in uart_8250_port and use 1607 * that instead. up->ier should be the same value as what is 1608 * currently configured. 1609 */ 1610 val = inb(p->iobase + offset); 1611 if (offset == UART_IER) { 1612 if (val == 0) 1613 val = up->ier; 1614 } 1615 return val; 1616 } 1617 1618 static int kt_serial_setup(struct serial_private *priv, 1619 const struct pciserial_board *board, 1620 struct uart_8250_port *port, int idx) 1621 { 1622 port->port.flags |= UPF_BUG_THRE; 1623 port->port.serial_in = kt_serial_in; 1624 port->port.handle_break = kt_handle_break; 1625 return skip_tx_en_setup(priv, board, port, idx); 1626 } 1627 1628 static int pci_eg20t_init(struct pci_dev *dev) 1629 { 1630 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1631 return -ENODEV; 1632 #else 1633 return 0; 1634 #endif 1635 } 1636 1637 static int 1638 pci_xr17c154_setup(struct serial_private *priv, 1639 const struct pciserial_board *board, 1640 struct uart_8250_port *port, int idx) 1641 { 1642 port->port.flags |= UPF_EXAR_EFR; 1643 return pci_default_setup(priv, board, port, idx); 1644 } 1645 1646 static int 1647 pci_xr17v35x_setup(struct serial_private *priv, 1648 const struct pciserial_board *board, 1649 struct uart_8250_port *port, int idx) 1650 { 1651 u8 __iomem *p; 1652 1653 p = pci_ioremap_bar(priv->dev, 0); 1654 if (p == NULL) 1655 return -ENOMEM; 1656 1657 port->port.flags |= UPF_EXAR_EFR; 1658 1659 /* 1660 * Setup Multipurpose Input/Output pins. 1661 */ 1662 if (idx == 0) { 1663 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1664 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1665 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1666 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1667 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1668 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1669 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1670 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1671 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1672 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1673 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1674 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1675 } 1676 writeb(0x00, p + UART_EXAR_8XMODE); 1677 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1678 writeb(128, p + UART_EXAR_TXTRG); 1679 writeb(128, p + UART_EXAR_RXTRG); 1680 iounmap(p); 1681 1682 return pci_default_setup(priv, board, port, idx); 1683 } 1684 1685 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1686 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1687 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1688 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1689 1690 static int 1691 pci_fastcom335_setup(struct serial_private *priv, 1692 const struct pciserial_board *board, 1693 struct uart_8250_port *port, int idx) 1694 { 1695 u8 __iomem *p; 1696 1697 p = pci_ioremap_bar(priv->dev, 0); 1698 if (p == NULL) 1699 return -ENOMEM; 1700 1701 port->port.flags |= UPF_EXAR_EFR; 1702 1703 /* 1704 * Setup Multipurpose Input/Output pins. 1705 */ 1706 if (idx == 0) { 1707 switch (priv->dev->device) { 1708 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1709 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1710 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1711 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1712 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1713 break; 1714 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1715 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1716 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1717 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1718 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1719 break; 1720 } 1721 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1722 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1723 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1724 } 1725 writeb(0x00, p + UART_EXAR_8XMODE); 1726 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1727 writeb(32, p + UART_EXAR_TXTRG); 1728 writeb(32, p + UART_EXAR_RXTRG); 1729 iounmap(p); 1730 1731 return pci_default_setup(priv, board, port, idx); 1732 } 1733 1734 static int 1735 pci_wch_ch353_setup(struct serial_private *priv, 1736 const struct pciserial_board *board, 1737 struct uart_8250_port *port, int idx) 1738 { 1739 port->port.flags |= UPF_FIXED_TYPE; 1740 port->port.type = PORT_16550A; 1741 return pci_default_setup(priv, board, port, idx); 1742 } 1743 1744 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1745 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1746 #define PCI_DEVICE_ID_OCTPRO 0x0001 1747 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1748 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1749 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1750 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1751 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1752 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1753 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1754 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1755 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1756 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1757 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1758 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1759 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1760 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1761 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1762 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1763 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1764 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1765 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1766 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1767 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1768 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1769 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1770 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1771 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1772 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1773 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1774 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1775 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1776 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1777 #define PCI_VENDOR_ID_WCH 0x4348 1778 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1779 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1780 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1781 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1782 #define PCI_VENDOR_ID_AGESTAR 0x5372 1783 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1784 #define PCI_VENDOR_ID_ASIX 0x9710 1785 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1786 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1787 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1788 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1789 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1790 1791 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1792 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1793 1794 1795 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1796 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1797 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1798 1799 /* 1800 * Master list of serial port init/setup/exit quirks. 1801 * This does not describe the general nature of the port. 1802 * (ie, baud base, number and location of ports, etc) 1803 * 1804 * This list is ordered alphabetically by vendor then device. 1805 * Specific entries must come before more generic entries. 1806 */ 1807 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1808 /* 1809 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1810 */ 1811 { 1812 .vendor = PCI_VENDOR_ID_AMCC, 1813 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1814 .subvendor = PCI_ANY_ID, 1815 .subdevice = PCI_ANY_ID, 1816 .setup = addidata_apci7800_setup, 1817 }, 1818 /* 1819 * AFAVLAB cards - these may be called via parport_serial 1820 * It is not clear whether this applies to all products. 1821 */ 1822 { 1823 .vendor = PCI_VENDOR_ID_AFAVLAB, 1824 .device = PCI_ANY_ID, 1825 .subvendor = PCI_ANY_ID, 1826 .subdevice = PCI_ANY_ID, 1827 .setup = afavlab_setup, 1828 }, 1829 /* 1830 * HP Diva 1831 */ 1832 { 1833 .vendor = PCI_VENDOR_ID_HP, 1834 .device = PCI_DEVICE_ID_HP_DIVA, 1835 .subvendor = PCI_ANY_ID, 1836 .subdevice = PCI_ANY_ID, 1837 .init = pci_hp_diva_init, 1838 .setup = pci_hp_diva_setup, 1839 }, 1840 /* 1841 * Intel 1842 */ 1843 { 1844 .vendor = PCI_VENDOR_ID_INTEL, 1845 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1846 .subvendor = 0xe4bf, 1847 .subdevice = PCI_ANY_ID, 1848 .init = pci_inteli960ni_init, 1849 .setup = pci_default_setup, 1850 }, 1851 { 1852 .vendor = PCI_VENDOR_ID_INTEL, 1853 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1854 .subvendor = PCI_ANY_ID, 1855 .subdevice = PCI_ANY_ID, 1856 .setup = skip_tx_en_setup, 1857 }, 1858 { 1859 .vendor = PCI_VENDOR_ID_INTEL, 1860 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1861 .subvendor = PCI_ANY_ID, 1862 .subdevice = PCI_ANY_ID, 1863 .setup = skip_tx_en_setup, 1864 }, 1865 { 1866 .vendor = PCI_VENDOR_ID_INTEL, 1867 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1868 .subvendor = PCI_ANY_ID, 1869 .subdevice = PCI_ANY_ID, 1870 .setup = skip_tx_en_setup, 1871 }, 1872 { 1873 .vendor = PCI_VENDOR_ID_INTEL, 1874 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1875 .subvendor = PCI_ANY_ID, 1876 .subdevice = PCI_ANY_ID, 1877 .setup = ce4100_serial_setup, 1878 }, 1879 { 1880 .vendor = PCI_VENDOR_ID_INTEL, 1881 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1882 .subvendor = PCI_ANY_ID, 1883 .subdevice = PCI_ANY_ID, 1884 .setup = kt_serial_setup, 1885 }, 1886 { 1887 .vendor = PCI_VENDOR_ID_INTEL, 1888 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 1889 .subvendor = PCI_ANY_ID, 1890 .subdevice = PCI_ANY_ID, 1891 .setup = byt_serial_setup, 1892 }, 1893 { 1894 .vendor = PCI_VENDOR_ID_INTEL, 1895 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 1896 .subvendor = PCI_ANY_ID, 1897 .subdevice = PCI_ANY_ID, 1898 .setup = byt_serial_setup, 1899 }, 1900 /* 1901 * ITE 1902 */ 1903 { 1904 .vendor = PCI_VENDOR_ID_ITE, 1905 .device = PCI_DEVICE_ID_ITE_8872, 1906 .subvendor = PCI_ANY_ID, 1907 .subdevice = PCI_ANY_ID, 1908 .init = pci_ite887x_init, 1909 .setup = pci_default_setup, 1910 .exit = pci_ite887x_exit, 1911 }, 1912 /* 1913 * National Instruments 1914 */ 1915 { 1916 .vendor = PCI_VENDOR_ID_NI, 1917 .device = PCI_DEVICE_ID_NI_PCI23216, 1918 .subvendor = PCI_ANY_ID, 1919 .subdevice = PCI_ANY_ID, 1920 .init = pci_ni8420_init, 1921 .setup = pci_default_setup, 1922 .exit = pci_ni8420_exit, 1923 }, 1924 { 1925 .vendor = PCI_VENDOR_ID_NI, 1926 .device = PCI_DEVICE_ID_NI_PCI2328, 1927 .subvendor = PCI_ANY_ID, 1928 .subdevice = PCI_ANY_ID, 1929 .init = pci_ni8420_init, 1930 .setup = pci_default_setup, 1931 .exit = pci_ni8420_exit, 1932 }, 1933 { 1934 .vendor = PCI_VENDOR_ID_NI, 1935 .device = PCI_DEVICE_ID_NI_PCI2324, 1936 .subvendor = PCI_ANY_ID, 1937 .subdevice = PCI_ANY_ID, 1938 .init = pci_ni8420_init, 1939 .setup = pci_default_setup, 1940 .exit = pci_ni8420_exit, 1941 }, 1942 { 1943 .vendor = PCI_VENDOR_ID_NI, 1944 .device = PCI_DEVICE_ID_NI_PCI2322, 1945 .subvendor = PCI_ANY_ID, 1946 .subdevice = PCI_ANY_ID, 1947 .init = pci_ni8420_init, 1948 .setup = pci_default_setup, 1949 .exit = pci_ni8420_exit, 1950 }, 1951 { 1952 .vendor = PCI_VENDOR_ID_NI, 1953 .device = PCI_DEVICE_ID_NI_PCI2324I, 1954 .subvendor = PCI_ANY_ID, 1955 .subdevice = PCI_ANY_ID, 1956 .init = pci_ni8420_init, 1957 .setup = pci_default_setup, 1958 .exit = pci_ni8420_exit, 1959 }, 1960 { 1961 .vendor = PCI_VENDOR_ID_NI, 1962 .device = PCI_DEVICE_ID_NI_PCI2322I, 1963 .subvendor = PCI_ANY_ID, 1964 .subdevice = PCI_ANY_ID, 1965 .init = pci_ni8420_init, 1966 .setup = pci_default_setup, 1967 .exit = pci_ni8420_exit, 1968 }, 1969 { 1970 .vendor = PCI_VENDOR_ID_NI, 1971 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1972 .subvendor = PCI_ANY_ID, 1973 .subdevice = PCI_ANY_ID, 1974 .init = pci_ni8420_init, 1975 .setup = pci_default_setup, 1976 .exit = pci_ni8420_exit, 1977 }, 1978 { 1979 .vendor = PCI_VENDOR_ID_NI, 1980 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 1981 .subvendor = PCI_ANY_ID, 1982 .subdevice = PCI_ANY_ID, 1983 .init = pci_ni8420_init, 1984 .setup = pci_default_setup, 1985 .exit = pci_ni8420_exit, 1986 }, 1987 { 1988 .vendor = PCI_VENDOR_ID_NI, 1989 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 1990 .subvendor = PCI_ANY_ID, 1991 .subdevice = PCI_ANY_ID, 1992 .init = pci_ni8420_init, 1993 .setup = pci_default_setup, 1994 .exit = pci_ni8420_exit, 1995 }, 1996 { 1997 .vendor = PCI_VENDOR_ID_NI, 1998 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 1999 .subvendor = PCI_ANY_ID, 2000 .subdevice = PCI_ANY_ID, 2001 .init = pci_ni8420_init, 2002 .setup = pci_default_setup, 2003 .exit = pci_ni8420_exit, 2004 }, 2005 { 2006 .vendor = PCI_VENDOR_ID_NI, 2007 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2008 .subvendor = PCI_ANY_ID, 2009 .subdevice = PCI_ANY_ID, 2010 .init = pci_ni8420_init, 2011 .setup = pci_default_setup, 2012 .exit = pci_ni8420_exit, 2013 }, 2014 { 2015 .vendor = PCI_VENDOR_ID_NI, 2016 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2017 .subvendor = PCI_ANY_ID, 2018 .subdevice = PCI_ANY_ID, 2019 .init = pci_ni8420_init, 2020 .setup = pci_default_setup, 2021 .exit = pci_ni8420_exit, 2022 }, 2023 { 2024 .vendor = PCI_VENDOR_ID_NI, 2025 .device = PCI_ANY_ID, 2026 .subvendor = PCI_ANY_ID, 2027 .subdevice = PCI_ANY_ID, 2028 .init = pci_ni8430_init, 2029 .setup = pci_ni8430_setup, 2030 .exit = pci_ni8430_exit, 2031 }, 2032 /* Quatech */ 2033 { 2034 .vendor = PCI_VENDOR_ID_QUATECH, 2035 .device = PCI_ANY_ID, 2036 .subvendor = PCI_ANY_ID, 2037 .subdevice = PCI_ANY_ID, 2038 .init = pci_quatech_init, 2039 .setup = pci_quatech_setup, 2040 .exit = pci_quatech_exit, 2041 }, 2042 /* 2043 * Panacom 2044 */ 2045 { 2046 .vendor = PCI_VENDOR_ID_PANACOM, 2047 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2048 .subvendor = PCI_ANY_ID, 2049 .subdevice = PCI_ANY_ID, 2050 .init = pci_plx9050_init, 2051 .setup = pci_default_setup, 2052 .exit = pci_plx9050_exit, 2053 }, 2054 { 2055 .vendor = PCI_VENDOR_ID_PANACOM, 2056 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2057 .subvendor = PCI_ANY_ID, 2058 .subdevice = PCI_ANY_ID, 2059 .init = pci_plx9050_init, 2060 .setup = pci_default_setup, 2061 .exit = pci_plx9050_exit, 2062 }, 2063 /* 2064 * Pericom 2065 */ 2066 { 2067 .vendor = 0x12d8, 2068 .device = 0x7952, 2069 .subvendor = PCI_ANY_ID, 2070 .subdevice = PCI_ANY_ID, 2071 .setup = pci_pericom_setup, 2072 }, 2073 { 2074 .vendor = 0x12d8, 2075 .device = 0x7954, 2076 .subvendor = PCI_ANY_ID, 2077 .subdevice = PCI_ANY_ID, 2078 .setup = pci_pericom_setup, 2079 }, 2080 { 2081 .vendor = 0x12d8, 2082 .device = 0x7958, 2083 .subvendor = PCI_ANY_ID, 2084 .subdevice = PCI_ANY_ID, 2085 .setup = pci_pericom_setup, 2086 }, 2087 2088 /* 2089 * PLX 2090 */ 2091 { 2092 .vendor = PCI_VENDOR_ID_PLX, 2093 .device = PCI_DEVICE_ID_PLX_9030, 2094 .subvendor = PCI_SUBVENDOR_ID_PERLE, 2095 .subdevice = PCI_ANY_ID, 2096 .setup = pci_default_setup, 2097 }, 2098 { 2099 .vendor = PCI_VENDOR_ID_PLX, 2100 .device = PCI_DEVICE_ID_PLX_9050, 2101 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2102 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2103 .init = pci_plx9050_init, 2104 .setup = pci_default_setup, 2105 .exit = pci_plx9050_exit, 2106 }, 2107 { 2108 .vendor = PCI_VENDOR_ID_PLX, 2109 .device = PCI_DEVICE_ID_PLX_9050, 2110 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2111 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2112 .init = pci_plx9050_init, 2113 .setup = pci_default_setup, 2114 .exit = pci_plx9050_exit, 2115 }, 2116 { 2117 .vendor = PCI_VENDOR_ID_PLX, 2118 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2119 .subvendor = PCI_VENDOR_ID_PLX, 2120 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2121 .init = pci_plx9050_init, 2122 .setup = pci_default_setup, 2123 .exit = pci_plx9050_exit, 2124 }, 2125 /* 2126 * SBS Technologies, Inc., PMC-OCTALPRO 232 2127 */ 2128 { 2129 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2130 .device = PCI_DEVICE_ID_OCTPRO, 2131 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2132 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2133 .init = sbs_init, 2134 .setup = sbs_setup, 2135 .exit = sbs_exit, 2136 }, 2137 /* 2138 * SBS Technologies, Inc., PMC-OCTALPRO 422 2139 */ 2140 { 2141 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2142 .device = PCI_DEVICE_ID_OCTPRO, 2143 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2144 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2145 .init = sbs_init, 2146 .setup = sbs_setup, 2147 .exit = sbs_exit, 2148 }, 2149 /* 2150 * SBS Technologies, Inc., P-Octal 232 2151 */ 2152 { 2153 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2154 .device = PCI_DEVICE_ID_OCTPRO, 2155 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2156 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2157 .init = sbs_init, 2158 .setup = sbs_setup, 2159 .exit = sbs_exit, 2160 }, 2161 /* 2162 * SBS Technologies, Inc., P-Octal 422 2163 */ 2164 { 2165 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2166 .device = PCI_DEVICE_ID_OCTPRO, 2167 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2168 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2169 .init = sbs_init, 2170 .setup = sbs_setup, 2171 .exit = sbs_exit, 2172 }, 2173 /* 2174 * SIIG cards - these may be called via parport_serial 2175 */ 2176 { 2177 .vendor = PCI_VENDOR_ID_SIIG, 2178 .device = PCI_ANY_ID, 2179 .subvendor = PCI_ANY_ID, 2180 .subdevice = PCI_ANY_ID, 2181 .init = pci_siig_init, 2182 .setup = pci_siig_setup, 2183 }, 2184 /* 2185 * Titan cards 2186 */ 2187 { 2188 .vendor = PCI_VENDOR_ID_TITAN, 2189 .device = PCI_DEVICE_ID_TITAN_400L, 2190 .subvendor = PCI_ANY_ID, 2191 .subdevice = PCI_ANY_ID, 2192 .setup = titan_400l_800l_setup, 2193 }, 2194 { 2195 .vendor = PCI_VENDOR_ID_TITAN, 2196 .device = PCI_DEVICE_ID_TITAN_800L, 2197 .subvendor = PCI_ANY_ID, 2198 .subdevice = PCI_ANY_ID, 2199 .setup = titan_400l_800l_setup, 2200 }, 2201 /* 2202 * Timedia cards 2203 */ 2204 { 2205 .vendor = PCI_VENDOR_ID_TIMEDIA, 2206 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2207 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2208 .subdevice = PCI_ANY_ID, 2209 .probe = pci_timedia_probe, 2210 .init = pci_timedia_init, 2211 .setup = pci_timedia_setup, 2212 }, 2213 { 2214 .vendor = PCI_VENDOR_ID_TIMEDIA, 2215 .device = PCI_ANY_ID, 2216 .subvendor = PCI_ANY_ID, 2217 .subdevice = PCI_ANY_ID, 2218 .setup = pci_timedia_setup, 2219 }, 2220 /* 2221 * SUNIX (Timedia) cards 2222 * Do not "probe" for these cards as there is at least one combination 2223 * card that should be handled by parport_pc that doesn't match the 2224 * rule in pci_timedia_probe. 2225 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2226 * There are some boards with part number SER5037AL that report 2227 * subdevice ID 0x0002. 2228 */ 2229 { 2230 .vendor = PCI_VENDOR_ID_SUNIX, 2231 .device = PCI_DEVICE_ID_SUNIX_1999, 2232 .subvendor = PCI_VENDOR_ID_SUNIX, 2233 .subdevice = PCI_ANY_ID, 2234 .init = pci_timedia_init, 2235 .setup = pci_timedia_setup, 2236 }, 2237 /* 2238 * Exar cards 2239 */ 2240 { 2241 .vendor = PCI_VENDOR_ID_EXAR, 2242 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2243 .subvendor = PCI_ANY_ID, 2244 .subdevice = PCI_ANY_ID, 2245 .setup = pci_xr17c154_setup, 2246 }, 2247 { 2248 .vendor = PCI_VENDOR_ID_EXAR, 2249 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2250 .subvendor = PCI_ANY_ID, 2251 .subdevice = PCI_ANY_ID, 2252 .setup = pci_xr17c154_setup, 2253 }, 2254 { 2255 .vendor = PCI_VENDOR_ID_EXAR, 2256 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2257 .subvendor = PCI_ANY_ID, 2258 .subdevice = PCI_ANY_ID, 2259 .setup = pci_xr17c154_setup, 2260 }, 2261 { 2262 .vendor = PCI_VENDOR_ID_EXAR, 2263 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2264 .subvendor = PCI_ANY_ID, 2265 .subdevice = PCI_ANY_ID, 2266 .setup = pci_xr17v35x_setup, 2267 }, 2268 { 2269 .vendor = PCI_VENDOR_ID_EXAR, 2270 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2271 .subvendor = PCI_ANY_ID, 2272 .subdevice = PCI_ANY_ID, 2273 .setup = pci_xr17v35x_setup, 2274 }, 2275 { 2276 .vendor = PCI_VENDOR_ID_EXAR, 2277 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2278 .subvendor = PCI_ANY_ID, 2279 .subdevice = PCI_ANY_ID, 2280 .setup = pci_xr17v35x_setup, 2281 }, 2282 /* 2283 * Xircom cards 2284 */ 2285 { 2286 .vendor = PCI_VENDOR_ID_XIRCOM, 2287 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2288 .subvendor = PCI_ANY_ID, 2289 .subdevice = PCI_ANY_ID, 2290 .init = pci_xircom_init, 2291 .setup = pci_default_setup, 2292 }, 2293 /* 2294 * Netmos cards - these may be called via parport_serial 2295 */ 2296 { 2297 .vendor = PCI_VENDOR_ID_NETMOS, 2298 .device = PCI_ANY_ID, 2299 .subvendor = PCI_ANY_ID, 2300 .subdevice = PCI_ANY_ID, 2301 .init = pci_netmos_init, 2302 .setup = pci_netmos_9900_setup, 2303 }, 2304 /* 2305 * For Oxford Semiconductor Tornado based devices 2306 */ 2307 { 2308 .vendor = PCI_VENDOR_ID_OXSEMI, 2309 .device = PCI_ANY_ID, 2310 .subvendor = PCI_ANY_ID, 2311 .subdevice = PCI_ANY_ID, 2312 .init = pci_oxsemi_tornado_init, 2313 .setup = pci_default_setup, 2314 }, 2315 { 2316 .vendor = PCI_VENDOR_ID_MAINPINE, 2317 .device = PCI_ANY_ID, 2318 .subvendor = PCI_ANY_ID, 2319 .subdevice = PCI_ANY_ID, 2320 .init = pci_oxsemi_tornado_init, 2321 .setup = pci_default_setup, 2322 }, 2323 { 2324 .vendor = PCI_VENDOR_ID_DIGI, 2325 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2326 .subvendor = PCI_SUBVENDOR_ID_IBM, 2327 .subdevice = PCI_ANY_ID, 2328 .init = pci_oxsemi_tornado_init, 2329 .setup = pci_default_setup, 2330 }, 2331 { 2332 .vendor = PCI_VENDOR_ID_INTEL, 2333 .device = 0x8811, 2334 .subvendor = PCI_ANY_ID, 2335 .subdevice = PCI_ANY_ID, 2336 .init = pci_eg20t_init, 2337 .setup = pci_default_setup, 2338 }, 2339 { 2340 .vendor = PCI_VENDOR_ID_INTEL, 2341 .device = 0x8812, 2342 .subvendor = PCI_ANY_ID, 2343 .subdevice = PCI_ANY_ID, 2344 .init = pci_eg20t_init, 2345 .setup = pci_default_setup, 2346 }, 2347 { 2348 .vendor = PCI_VENDOR_ID_INTEL, 2349 .device = 0x8813, 2350 .subvendor = PCI_ANY_ID, 2351 .subdevice = PCI_ANY_ID, 2352 .init = pci_eg20t_init, 2353 .setup = pci_default_setup, 2354 }, 2355 { 2356 .vendor = PCI_VENDOR_ID_INTEL, 2357 .device = 0x8814, 2358 .subvendor = PCI_ANY_ID, 2359 .subdevice = PCI_ANY_ID, 2360 .init = pci_eg20t_init, 2361 .setup = pci_default_setup, 2362 }, 2363 { 2364 .vendor = 0x10DB, 2365 .device = 0x8027, 2366 .subvendor = PCI_ANY_ID, 2367 .subdevice = PCI_ANY_ID, 2368 .init = pci_eg20t_init, 2369 .setup = pci_default_setup, 2370 }, 2371 { 2372 .vendor = 0x10DB, 2373 .device = 0x8028, 2374 .subvendor = PCI_ANY_ID, 2375 .subdevice = PCI_ANY_ID, 2376 .init = pci_eg20t_init, 2377 .setup = pci_default_setup, 2378 }, 2379 { 2380 .vendor = 0x10DB, 2381 .device = 0x8029, 2382 .subvendor = PCI_ANY_ID, 2383 .subdevice = PCI_ANY_ID, 2384 .init = pci_eg20t_init, 2385 .setup = pci_default_setup, 2386 }, 2387 { 2388 .vendor = 0x10DB, 2389 .device = 0x800C, 2390 .subvendor = PCI_ANY_ID, 2391 .subdevice = PCI_ANY_ID, 2392 .init = pci_eg20t_init, 2393 .setup = pci_default_setup, 2394 }, 2395 { 2396 .vendor = 0x10DB, 2397 .device = 0x800D, 2398 .subvendor = PCI_ANY_ID, 2399 .subdevice = PCI_ANY_ID, 2400 .init = pci_eg20t_init, 2401 .setup = pci_default_setup, 2402 }, 2403 /* 2404 * Cronyx Omega PCI (PLX-chip based) 2405 */ 2406 { 2407 .vendor = PCI_VENDOR_ID_PLX, 2408 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2409 .subvendor = PCI_ANY_ID, 2410 .subdevice = PCI_ANY_ID, 2411 .setup = pci_omegapci_setup, 2412 }, 2413 /* WCH CH353 2S1P card (16550 clone) */ 2414 { 2415 .vendor = PCI_VENDOR_ID_WCH, 2416 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2417 .subvendor = PCI_ANY_ID, 2418 .subdevice = PCI_ANY_ID, 2419 .setup = pci_wch_ch353_setup, 2420 }, 2421 /* WCH CH353 4S card (16550 clone) */ 2422 { 2423 .vendor = PCI_VENDOR_ID_WCH, 2424 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2425 .subvendor = PCI_ANY_ID, 2426 .subdevice = PCI_ANY_ID, 2427 .setup = pci_wch_ch353_setup, 2428 }, 2429 /* WCH CH353 2S1PF card (16550 clone) */ 2430 { 2431 .vendor = PCI_VENDOR_ID_WCH, 2432 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2433 .subvendor = PCI_ANY_ID, 2434 .subdevice = PCI_ANY_ID, 2435 .setup = pci_wch_ch353_setup, 2436 }, 2437 /* WCH CH352 2S card (16550 clone) */ 2438 { 2439 .vendor = PCI_VENDOR_ID_WCH, 2440 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2441 .subvendor = PCI_ANY_ID, 2442 .subdevice = PCI_ANY_ID, 2443 .setup = pci_wch_ch353_setup, 2444 }, 2445 /* 2446 * ASIX devices with FIFO bug 2447 */ 2448 { 2449 .vendor = PCI_VENDOR_ID_ASIX, 2450 .device = PCI_ANY_ID, 2451 .subvendor = PCI_ANY_ID, 2452 .subdevice = PCI_ANY_ID, 2453 .setup = pci_asix_setup, 2454 }, 2455 /* 2456 * Commtech, Inc. Fastcom adapters 2457 * 2458 */ 2459 { 2460 .vendor = PCI_VENDOR_ID_COMMTECH, 2461 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2462 .subvendor = PCI_ANY_ID, 2463 .subdevice = PCI_ANY_ID, 2464 .setup = pci_fastcom335_setup, 2465 }, 2466 { 2467 .vendor = PCI_VENDOR_ID_COMMTECH, 2468 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2469 .subvendor = PCI_ANY_ID, 2470 .subdevice = PCI_ANY_ID, 2471 .setup = pci_fastcom335_setup, 2472 }, 2473 { 2474 .vendor = PCI_VENDOR_ID_COMMTECH, 2475 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2476 .subvendor = PCI_ANY_ID, 2477 .subdevice = PCI_ANY_ID, 2478 .setup = pci_fastcom335_setup, 2479 }, 2480 { 2481 .vendor = PCI_VENDOR_ID_COMMTECH, 2482 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2483 .subvendor = PCI_ANY_ID, 2484 .subdevice = PCI_ANY_ID, 2485 .setup = pci_fastcom335_setup, 2486 }, 2487 { 2488 .vendor = PCI_VENDOR_ID_COMMTECH, 2489 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2490 .subvendor = PCI_ANY_ID, 2491 .subdevice = PCI_ANY_ID, 2492 .setup = pci_xr17v35x_setup, 2493 }, 2494 { 2495 .vendor = PCI_VENDOR_ID_COMMTECH, 2496 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2497 .subvendor = PCI_ANY_ID, 2498 .subdevice = PCI_ANY_ID, 2499 .setup = pci_xr17v35x_setup, 2500 }, 2501 { 2502 .vendor = PCI_VENDOR_ID_COMMTECH, 2503 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2504 .subvendor = PCI_ANY_ID, 2505 .subdevice = PCI_ANY_ID, 2506 .setup = pci_xr17v35x_setup, 2507 }, 2508 /* 2509 * Broadcom TruManage (NetXtreme) 2510 */ 2511 { 2512 .vendor = PCI_VENDOR_ID_BROADCOM, 2513 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2514 .subvendor = PCI_ANY_ID, 2515 .subdevice = PCI_ANY_ID, 2516 .setup = pci_brcm_trumanage_setup, 2517 }, 2518 { 2519 .vendor = 0x1c29, 2520 .device = 0x1104, 2521 .subvendor = PCI_ANY_ID, 2522 .subdevice = PCI_ANY_ID, 2523 .setup = pci_fintek_setup, 2524 }, 2525 { 2526 .vendor = 0x1c29, 2527 .device = 0x1108, 2528 .subvendor = PCI_ANY_ID, 2529 .subdevice = PCI_ANY_ID, 2530 .setup = pci_fintek_setup, 2531 }, 2532 { 2533 .vendor = 0x1c29, 2534 .device = 0x1112, 2535 .subvendor = PCI_ANY_ID, 2536 .subdevice = PCI_ANY_ID, 2537 .setup = pci_fintek_setup, 2538 }, 2539 2540 /* 2541 * Default "match everything" terminator entry 2542 */ 2543 { 2544 .vendor = PCI_ANY_ID, 2545 .device = PCI_ANY_ID, 2546 .subvendor = PCI_ANY_ID, 2547 .subdevice = PCI_ANY_ID, 2548 .setup = pci_default_setup, 2549 } 2550 }; 2551 2552 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2553 { 2554 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2555 } 2556 2557 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2558 { 2559 struct pci_serial_quirk *quirk; 2560 2561 for (quirk = pci_serial_quirks; ; quirk++) 2562 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2563 quirk_id_matches(quirk->device, dev->device) && 2564 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2565 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2566 break; 2567 return quirk; 2568 } 2569 2570 static inline int get_pci_irq(struct pci_dev *dev, 2571 const struct pciserial_board *board) 2572 { 2573 if (board->flags & FL_NOIRQ) 2574 return 0; 2575 else 2576 return dev->irq; 2577 } 2578 2579 /* 2580 * This is the configuration table for all of the PCI serial boards 2581 * which we support. It is directly indexed by the pci_board_num_t enum 2582 * value, which is encoded in the pci_device_id PCI probe table's 2583 * driver_data member. 2584 * 2585 * The makeup of these names are: 2586 * pbn_bn{_bt}_n_baud{_offsetinhex} 2587 * 2588 * bn = PCI BAR number 2589 * bt = Index using PCI BARs 2590 * n = number of serial ports 2591 * baud = baud rate 2592 * offsetinhex = offset for each sequential port (in hex) 2593 * 2594 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2595 * 2596 * Please note: in theory if n = 1, _bt infix should make no difference. 2597 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2598 */ 2599 enum pci_board_num_t { 2600 pbn_default = 0, 2601 2602 pbn_b0_1_115200, 2603 pbn_b0_2_115200, 2604 pbn_b0_4_115200, 2605 pbn_b0_5_115200, 2606 pbn_b0_8_115200, 2607 2608 pbn_b0_1_921600, 2609 pbn_b0_2_921600, 2610 pbn_b0_4_921600, 2611 2612 pbn_b0_2_1130000, 2613 2614 pbn_b0_4_1152000, 2615 2616 pbn_b0_2_1152000_200, 2617 pbn_b0_4_1152000_200, 2618 pbn_b0_8_1152000_200, 2619 2620 pbn_b0_2_1843200, 2621 pbn_b0_4_1843200, 2622 2623 pbn_b0_2_1843200_200, 2624 pbn_b0_4_1843200_200, 2625 pbn_b0_8_1843200_200, 2626 2627 pbn_b0_1_4000000, 2628 2629 pbn_b0_bt_1_115200, 2630 pbn_b0_bt_2_115200, 2631 pbn_b0_bt_4_115200, 2632 pbn_b0_bt_8_115200, 2633 2634 pbn_b0_bt_1_460800, 2635 pbn_b0_bt_2_460800, 2636 pbn_b0_bt_4_460800, 2637 2638 pbn_b0_bt_1_921600, 2639 pbn_b0_bt_2_921600, 2640 pbn_b0_bt_4_921600, 2641 pbn_b0_bt_8_921600, 2642 2643 pbn_b1_1_115200, 2644 pbn_b1_2_115200, 2645 pbn_b1_4_115200, 2646 pbn_b1_8_115200, 2647 pbn_b1_16_115200, 2648 2649 pbn_b1_1_921600, 2650 pbn_b1_2_921600, 2651 pbn_b1_4_921600, 2652 pbn_b1_8_921600, 2653 2654 pbn_b1_2_1250000, 2655 2656 pbn_b1_bt_1_115200, 2657 pbn_b1_bt_2_115200, 2658 pbn_b1_bt_4_115200, 2659 2660 pbn_b1_bt_2_921600, 2661 2662 pbn_b1_1_1382400, 2663 pbn_b1_2_1382400, 2664 pbn_b1_4_1382400, 2665 pbn_b1_8_1382400, 2666 2667 pbn_b2_1_115200, 2668 pbn_b2_2_115200, 2669 pbn_b2_4_115200, 2670 pbn_b2_8_115200, 2671 2672 pbn_b2_1_460800, 2673 pbn_b2_4_460800, 2674 pbn_b2_8_460800, 2675 pbn_b2_16_460800, 2676 2677 pbn_b2_1_921600, 2678 pbn_b2_4_921600, 2679 pbn_b2_8_921600, 2680 2681 pbn_b2_8_1152000, 2682 2683 pbn_b2_bt_1_115200, 2684 pbn_b2_bt_2_115200, 2685 pbn_b2_bt_4_115200, 2686 2687 pbn_b2_bt_2_921600, 2688 pbn_b2_bt_4_921600, 2689 2690 pbn_b3_2_115200, 2691 pbn_b3_4_115200, 2692 pbn_b3_8_115200, 2693 2694 pbn_b4_bt_2_921600, 2695 pbn_b4_bt_4_921600, 2696 pbn_b4_bt_8_921600, 2697 2698 /* 2699 * Board-specific versions. 2700 */ 2701 pbn_panacom, 2702 pbn_panacom2, 2703 pbn_panacom4, 2704 pbn_plx_romulus, 2705 pbn_oxsemi, 2706 pbn_oxsemi_1_4000000, 2707 pbn_oxsemi_2_4000000, 2708 pbn_oxsemi_4_4000000, 2709 pbn_oxsemi_8_4000000, 2710 pbn_intel_i960, 2711 pbn_sgi_ioc3, 2712 pbn_computone_4, 2713 pbn_computone_6, 2714 pbn_computone_8, 2715 pbn_sbsxrsio, 2716 pbn_exar_XR17C152, 2717 pbn_exar_XR17C154, 2718 pbn_exar_XR17C158, 2719 pbn_exar_XR17V352, 2720 pbn_exar_XR17V354, 2721 pbn_exar_XR17V358, 2722 pbn_exar_ibm_saturn, 2723 pbn_pasemi_1682M, 2724 pbn_ni8430_2, 2725 pbn_ni8430_4, 2726 pbn_ni8430_8, 2727 pbn_ni8430_16, 2728 pbn_ADDIDATA_PCIe_1_3906250, 2729 pbn_ADDIDATA_PCIe_2_3906250, 2730 pbn_ADDIDATA_PCIe_4_3906250, 2731 pbn_ADDIDATA_PCIe_8_3906250, 2732 pbn_ce4100_1_115200, 2733 pbn_byt, 2734 pbn_omegapci, 2735 pbn_NETMOS9900_2s_115200, 2736 pbn_brcm_trumanage, 2737 pbn_fintek_4, 2738 pbn_fintek_8, 2739 pbn_fintek_12, 2740 }; 2741 2742 /* 2743 * uart_offset - the space between channels 2744 * reg_shift - describes how the UART registers are mapped 2745 * to PCI memory by the card. 2746 * For example IER register on SBS, Inc. PMC-OctPro is located at 2747 * offset 0x10 from the UART base, while UART_IER is defined as 1 2748 * in include/linux/serial_reg.h, 2749 * see first lines of serial_in() and serial_out() in 8250.c 2750 */ 2751 2752 static struct pciserial_board pci_boards[] = { 2753 [pbn_default] = { 2754 .flags = FL_BASE0, 2755 .num_ports = 1, 2756 .base_baud = 115200, 2757 .uart_offset = 8, 2758 }, 2759 [pbn_b0_1_115200] = { 2760 .flags = FL_BASE0, 2761 .num_ports = 1, 2762 .base_baud = 115200, 2763 .uart_offset = 8, 2764 }, 2765 [pbn_b0_2_115200] = { 2766 .flags = FL_BASE0, 2767 .num_ports = 2, 2768 .base_baud = 115200, 2769 .uart_offset = 8, 2770 }, 2771 [pbn_b0_4_115200] = { 2772 .flags = FL_BASE0, 2773 .num_ports = 4, 2774 .base_baud = 115200, 2775 .uart_offset = 8, 2776 }, 2777 [pbn_b0_5_115200] = { 2778 .flags = FL_BASE0, 2779 .num_ports = 5, 2780 .base_baud = 115200, 2781 .uart_offset = 8, 2782 }, 2783 [pbn_b0_8_115200] = { 2784 .flags = FL_BASE0, 2785 .num_ports = 8, 2786 .base_baud = 115200, 2787 .uart_offset = 8, 2788 }, 2789 [pbn_b0_1_921600] = { 2790 .flags = FL_BASE0, 2791 .num_ports = 1, 2792 .base_baud = 921600, 2793 .uart_offset = 8, 2794 }, 2795 [pbn_b0_2_921600] = { 2796 .flags = FL_BASE0, 2797 .num_ports = 2, 2798 .base_baud = 921600, 2799 .uart_offset = 8, 2800 }, 2801 [pbn_b0_4_921600] = { 2802 .flags = FL_BASE0, 2803 .num_ports = 4, 2804 .base_baud = 921600, 2805 .uart_offset = 8, 2806 }, 2807 2808 [pbn_b0_2_1130000] = { 2809 .flags = FL_BASE0, 2810 .num_ports = 2, 2811 .base_baud = 1130000, 2812 .uart_offset = 8, 2813 }, 2814 2815 [pbn_b0_4_1152000] = { 2816 .flags = FL_BASE0, 2817 .num_ports = 4, 2818 .base_baud = 1152000, 2819 .uart_offset = 8, 2820 }, 2821 2822 [pbn_b0_2_1152000_200] = { 2823 .flags = FL_BASE0, 2824 .num_ports = 2, 2825 .base_baud = 1152000, 2826 .uart_offset = 0x200, 2827 }, 2828 2829 [pbn_b0_4_1152000_200] = { 2830 .flags = FL_BASE0, 2831 .num_ports = 4, 2832 .base_baud = 1152000, 2833 .uart_offset = 0x200, 2834 }, 2835 2836 [pbn_b0_8_1152000_200] = { 2837 .flags = FL_BASE0, 2838 .num_ports = 8, 2839 .base_baud = 1152000, 2840 .uart_offset = 0x200, 2841 }, 2842 2843 [pbn_b0_2_1843200] = { 2844 .flags = FL_BASE0, 2845 .num_ports = 2, 2846 .base_baud = 1843200, 2847 .uart_offset = 8, 2848 }, 2849 [pbn_b0_4_1843200] = { 2850 .flags = FL_BASE0, 2851 .num_ports = 4, 2852 .base_baud = 1843200, 2853 .uart_offset = 8, 2854 }, 2855 2856 [pbn_b0_2_1843200_200] = { 2857 .flags = FL_BASE0, 2858 .num_ports = 2, 2859 .base_baud = 1843200, 2860 .uart_offset = 0x200, 2861 }, 2862 [pbn_b0_4_1843200_200] = { 2863 .flags = FL_BASE0, 2864 .num_ports = 4, 2865 .base_baud = 1843200, 2866 .uart_offset = 0x200, 2867 }, 2868 [pbn_b0_8_1843200_200] = { 2869 .flags = FL_BASE0, 2870 .num_ports = 8, 2871 .base_baud = 1843200, 2872 .uart_offset = 0x200, 2873 }, 2874 [pbn_b0_1_4000000] = { 2875 .flags = FL_BASE0, 2876 .num_ports = 1, 2877 .base_baud = 4000000, 2878 .uart_offset = 8, 2879 }, 2880 2881 [pbn_b0_bt_1_115200] = { 2882 .flags = FL_BASE0|FL_BASE_BARS, 2883 .num_ports = 1, 2884 .base_baud = 115200, 2885 .uart_offset = 8, 2886 }, 2887 [pbn_b0_bt_2_115200] = { 2888 .flags = FL_BASE0|FL_BASE_BARS, 2889 .num_ports = 2, 2890 .base_baud = 115200, 2891 .uart_offset = 8, 2892 }, 2893 [pbn_b0_bt_4_115200] = { 2894 .flags = FL_BASE0|FL_BASE_BARS, 2895 .num_ports = 4, 2896 .base_baud = 115200, 2897 .uart_offset = 8, 2898 }, 2899 [pbn_b0_bt_8_115200] = { 2900 .flags = FL_BASE0|FL_BASE_BARS, 2901 .num_ports = 8, 2902 .base_baud = 115200, 2903 .uart_offset = 8, 2904 }, 2905 2906 [pbn_b0_bt_1_460800] = { 2907 .flags = FL_BASE0|FL_BASE_BARS, 2908 .num_ports = 1, 2909 .base_baud = 460800, 2910 .uart_offset = 8, 2911 }, 2912 [pbn_b0_bt_2_460800] = { 2913 .flags = FL_BASE0|FL_BASE_BARS, 2914 .num_ports = 2, 2915 .base_baud = 460800, 2916 .uart_offset = 8, 2917 }, 2918 [pbn_b0_bt_4_460800] = { 2919 .flags = FL_BASE0|FL_BASE_BARS, 2920 .num_ports = 4, 2921 .base_baud = 460800, 2922 .uart_offset = 8, 2923 }, 2924 2925 [pbn_b0_bt_1_921600] = { 2926 .flags = FL_BASE0|FL_BASE_BARS, 2927 .num_ports = 1, 2928 .base_baud = 921600, 2929 .uart_offset = 8, 2930 }, 2931 [pbn_b0_bt_2_921600] = { 2932 .flags = FL_BASE0|FL_BASE_BARS, 2933 .num_ports = 2, 2934 .base_baud = 921600, 2935 .uart_offset = 8, 2936 }, 2937 [pbn_b0_bt_4_921600] = { 2938 .flags = FL_BASE0|FL_BASE_BARS, 2939 .num_ports = 4, 2940 .base_baud = 921600, 2941 .uart_offset = 8, 2942 }, 2943 [pbn_b0_bt_8_921600] = { 2944 .flags = FL_BASE0|FL_BASE_BARS, 2945 .num_ports = 8, 2946 .base_baud = 921600, 2947 .uart_offset = 8, 2948 }, 2949 2950 [pbn_b1_1_115200] = { 2951 .flags = FL_BASE1, 2952 .num_ports = 1, 2953 .base_baud = 115200, 2954 .uart_offset = 8, 2955 }, 2956 [pbn_b1_2_115200] = { 2957 .flags = FL_BASE1, 2958 .num_ports = 2, 2959 .base_baud = 115200, 2960 .uart_offset = 8, 2961 }, 2962 [pbn_b1_4_115200] = { 2963 .flags = FL_BASE1, 2964 .num_ports = 4, 2965 .base_baud = 115200, 2966 .uart_offset = 8, 2967 }, 2968 [pbn_b1_8_115200] = { 2969 .flags = FL_BASE1, 2970 .num_ports = 8, 2971 .base_baud = 115200, 2972 .uart_offset = 8, 2973 }, 2974 [pbn_b1_16_115200] = { 2975 .flags = FL_BASE1, 2976 .num_ports = 16, 2977 .base_baud = 115200, 2978 .uart_offset = 8, 2979 }, 2980 2981 [pbn_b1_1_921600] = { 2982 .flags = FL_BASE1, 2983 .num_ports = 1, 2984 .base_baud = 921600, 2985 .uart_offset = 8, 2986 }, 2987 [pbn_b1_2_921600] = { 2988 .flags = FL_BASE1, 2989 .num_ports = 2, 2990 .base_baud = 921600, 2991 .uart_offset = 8, 2992 }, 2993 [pbn_b1_4_921600] = { 2994 .flags = FL_BASE1, 2995 .num_ports = 4, 2996 .base_baud = 921600, 2997 .uart_offset = 8, 2998 }, 2999 [pbn_b1_8_921600] = { 3000 .flags = FL_BASE1, 3001 .num_ports = 8, 3002 .base_baud = 921600, 3003 .uart_offset = 8, 3004 }, 3005 [pbn_b1_2_1250000] = { 3006 .flags = FL_BASE1, 3007 .num_ports = 2, 3008 .base_baud = 1250000, 3009 .uart_offset = 8, 3010 }, 3011 3012 [pbn_b1_bt_1_115200] = { 3013 .flags = FL_BASE1|FL_BASE_BARS, 3014 .num_ports = 1, 3015 .base_baud = 115200, 3016 .uart_offset = 8, 3017 }, 3018 [pbn_b1_bt_2_115200] = { 3019 .flags = FL_BASE1|FL_BASE_BARS, 3020 .num_ports = 2, 3021 .base_baud = 115200, 3022 .uart_offset = 8, 3023 }, 3024 [pbn_b1_bt_4_115200] = { 3025 .flags = FL_BASE1|FL_BASE_BARS, 3026 .num_ports = 4, 3027 .base_baud = 115200, 3028 .uart_offset = 8, 3029 }, 3030 3031 [pbn_b1_bt_2_921600] = { 3032 .flags = FL_BASE1|FL_BASE_BARS, 3033 .num_ports = 2, 3034 .base_baud = 921600, 3035 .uart_offset = 8, 3036 }, 3037 3038 [pbn_b1_1_1382400] = { 3039 .flags = FL_BASE1, 3040 .num_ports = 1, 3041 .base_baud = 1382400, 3042 .uart_offset = 8, 3043 }, 3044 [pbn_b1_2_1382400] = { 3045 .flags = FL_BASE1, 3046 .num_ports = 2, 3047 .base_baud = 1382400, 3048 .uart_offset = 8, 3049 }, 3050 [pbn_b1_4_1382400] = { 3051 .flags = FL_BASE1, 3052 .num_ports = 4, 3053 .base_baud = 1382400, 3054 .uart_offset = 8, 3055 }, 3056 [pbn_b1_8_1382400] = { 3057 .flags = FL_BASE1, 3058 .num_ports = 8, 3059 .base_baud = 1382400, 3060 .uart_offset = 8, 3061 }, 3062 3063 [pbn_b2_1_115200] = { 3064 .flags = FL_BASE2, 3065 .num_ports = 1, 3066 .base_baud = 115200, 3067 .uart_offset = 8, 3068 }, 3069 [pbn_b2_2_115200] = { 3070 .flags = FL_BASE2, 3071 .num_ports = 2, 3072 .base_baud = 115200, 3073 .uart_offset = 8, 3074 }, 3075 [pbn_b2_4_115200] = { 3076 .flags = FL_BASE2, 3077 .num_ports = 4, 3078 .base_baud = 115200, 3079 .uart_offset = 8, 3080 }, 3081 [pbn_b2_8_115200] = { 3082 .flags = FL_BASE2, 3083 .num_ports = 8, 3084 .base_baud = 115200, 3085 .uart_offset = 8, 3086 }, 3087 3088 [pbn_b2_1_460800] = { 3089 .flags = FL_BASE2, 3090 .num_ports = 1, 3091 .base_baud = 460800, 3092 .uart_offset = 8, 3093 }, 3094 [pbn_b2_4_460800] = { 3095 .flags = FL_BASE2, 3096 .num_ports = 4, 3097 .base_baud = 460800, 3098 .uart_offset = 8, 3099 }, 3100 [pbn_b2_8_460800] = { 3101 .flags = FL_BASE2, 3102 .num_ports = 8, 3103 .base_baud = 460800, 3104 .uart_offset = 8, 3105 }, 3106 [pbn_b2_16_460800] = { 3107 .flags = FL_BASE2, 3108 .num_ports = 16, 3109 .base_baud = 460800, 3110 .uart_offset = 8, 3111 }, 3112 3113 [pbn_b2_1_921600] = { 3114 .flags = FL_BASE2, 3115 .num_ports = 1, 3116 .base_baud = 921600, 3117 .uart_offset = 8, 3118 }, 3119 [pbn_b2_4_921600] = { 3120 .flags = FL_BASE2, 3121 .num_ports = 4, 3122 .base_baud = 921600, 3123 .uart_offset = 8, 3124 }, 3125 [pbn_b2_8_921600] = { 3126 .flags = FL_BASE2, 3127 .num_ports = 8, 3128 .base_baud = 921600, 3129 .uart_offset = 8, 3130 }, 3131 3132 [pbn_b2_8_1152000] = { 3133 .flags = FL_BASE2, 3134 .num_ports = 8, 3135 .base_baud = 1152000, 3136 .uart_offset = 8, 3137 }, 3138 3139 [pbn_b2_bt_1_115200] = { 3140 .flags = FL_BASE2|FL_BASE_BARS, 3141 .num_ports = 1, 3142 .base_baud = 115200, 3143 .uart_offset = 8, 3144 }, 3145 [pbn_b2_bt_2_115200] = { 3146 .flags = FL_BASE2|FL_BASE_BARS, 3147 .num_ports = 2, 3148 .base_baud = 115200, 3149 .uart_offset = 8, 3150 }, 3151 [pbn_b2_bt_4_115200] = { 3152 .flags = FL_BASE2|FL_BASE_BARS, 3153 .num_ports = 4, 3154 .base_baud = 115200, 3155 .uart_offset = 8, 3156 }, 3157 3158 [pbn_b2_bt_2_921600] = { 3159 .flags = FL_BASE2|FL_BASE_BARS, 3160 .num_ports = 2, 3161 .base_baud = 921600, 3162 .uart_offset = 8, 3163 }, 3164 [pbn_b2_bt_4_921600] = { 3165 .flags = FL_BASE2|FL_BASE_BARS, 3166 .num_ports = 4, 3167 .base_baud = 921600, 3168 .uart_offset = 8, 3169 }, 3170 3171 [pbn_b3_2_115200] = { 3172 .flags = FL_BASE3, 3173 .num_ports = 2, 3174 .base_baud = 115200, 3175 .uart_offset = 8, 3176 }, 3177 [pbn_b3_4_115200] = { 3178 .flags = FL_BASE3, 3179 .num_ports = 4, 3180 .base_baud = 115200, 3181 .uart_offset = 8, 3182 }, 3183 [pbn_b3_8_115200] = { 3184 .flags = FL_BASE3, 3185 .num_ports = 8, 3186 .base_baud = 115200, 3187 .uart_offset = 8, 3188 }, 3189 3190 [pbn_b4_bt_2_921600] = { 3191 .flags = FL_BASE4, 3192 .num_ports = 2, 3193 .base_baud = 921600, 3194 .uart_offset = 8, 3195 }, 3196 [pbn_b4_bt_4_921600] = { 3197 .flags = FL_BASE4, 3198 .num_ports = 4, 3199 .base_baud = 921600, 3200 .uart_offset = 8, 3201 }, 3202 [pbn_b4_bt_8_921600] = { 3203 .flags = FL_BASE4, 3204 .num_ports = 8, 3205 .base_baud = 921600, 3206 .uart_offset = 8, 3207 }, 3208 3209 /* 3210 * Entries following this are board-specific. 3211 */ 3212 3213 /* 3214 * Panacom - IOMEM 3215 */ 3216 [pbn_panacom] = { 3217 .flags = FL_BASE2, 3218 .num_ports = 2, 3219 .base_baud = 921600, 3220 .uart_offset = 0x400, 3221 .reg_shift = 7, 3222 }, 3223 [pbn_panacom2] = { 3224 .flags = FL_BASE2|FL_BASE_BARS, 3225 .num_ports = 2, 3226 .base_baud = 921600, 3227 .uart_offset = 0x400, 3228 .reg_shift = 7, 3229 }, 3230 [pbn_panacom4] = { 3231 .flags = FL_BASE2|FL_BASE_BARS, 3232 .num_ports = 4, 3233 .base_baud = 921600, 3234 .uart_offset = 0x400, 3235 .reg_shift = 7, 3236 }, 3237 3238 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3239 [pbn_plx_romulus] = { 3240 .flags = FL_BASE2, 3241 .num_ports = 4, 3242 .base_baud = 921600, 3243 .uart_offset = 8 << 2, 3244 .reg_shift = 2, 3245 .first_offset = 0x03, 3246 }, 3247 3248 /* 3249 * This board uses the size of PCI Base region 0 to 3250 * signal now many ports are available 3251 */ 3252 [pbn_oxsemi] = { 3253 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3254 .num_ports = 32, 3255 .base_baud = 115200, 3256 .uart_offset = 8, 3257 }, 3258 [pbn_oxsemi_1_4000000] = { 3259 .flags = FL_BASE0, 3260 .num_ports = 1, 3261 .base_baud = 4000000, 3262 .uart_offset = 0x200, 3263 .first_offset = 0x1000, 3264 }, 3265 [pbn_oxsemi_2_4000000] = { 3266 .flags = FL_BASE0, 3267 .num_ports = 2, 3268 .base_baud = 4000000, 3269 .uart_offset = 0x200, 3270 .first_offset = 0x1000, 3271 }, 3272 [pbn_oxsemi_4_4000000] = { 3273 .flags = FL_BASE0, 3274 .num_ports = 4, 3275 .base_baud = 4000000, 3276 .uart_offset = 0x200, 3277 .first_offset = 0x1000, 3278 }, 3279 [pbn_oxsemi_8_4000000] = { 3280 .flags = FL_BASE0, 3281 .num_ports = 8, 3282 .base_baud = 4000000, 3283 .uart_offset = 0x200, 3284 .first_offset = 0x1000, 3285 }, 3286 3287 3288 /* 3289 * EKF addition for i960 Boards form EKF with serial port. 3290 * Max 256 ports. 3291 */ 3292 [pbn_intel_i960] = { 3293 .flags = FL_BASE0, 3294 .num_ports = 32, 3295 .base_baud = 921600, 3296 .uart_offset = 8 << 2, 3297 .reg_shift = 2, 3298 .first_offset = 0x10000, 3299 }, 3300 [pbn_sgi_ioc3] = { 3301 .flags = FL_BASE0|FL_NOIRQ, 3302 .num_ports = 1, 3303 .base_baud = 458333, 3304 .uart_offset = 8, 3305 .reg_shift = 0, 3306 .first_offset = 0x20178, 3307 }, 3308 3309 /* 3310 * Computone - uses IOMEM. 3311 */ 3312 [pbn_computone_4] = { 3313 .flags = FL_BASE0, 3314 .num_ports = 4, 3315 .base_baud = 921600, 3316 .uart_offset = 0x40, 3317 .reg_shift = 2, 3318 .first_offset = 0x200, 3319 }, 3320 [pbn_computone_6] = { 3321 .flags = FL_BASE0, 3322 .num_ports = 6, 3323 .base_baud = 921600, 3324 .uart_offset = 0x40, 3325 .reg_shift = 2, 3326 .first_offset = 0x200, 3327 }, 3328 [pbn_computone_8] = { 3329 .flags = FL_BASE0, 3330 .num_ports = 8, 3331 .base_baud = 921600, 3332 .uart_offset = 0x40, 3333 .reg_shift = 2, 3334 .first_offset = 0x200, 3335 }, 3336 [pbn_sbsxrsio] = { 3337 .flags = FL_BASE0, 3338 .num_ports = 8, 3339 .base_baud = 460800, 3340 .uart_offset = 256, 3341 .reg_shift = 4, 3342 }, 3343 /* 3344 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3345 * Only basic 16550A support. 3346 * XR17C15[24] are not tested, but they should work. 3347 */ 3348 [pbn_exar_XR17C152] = { 3349 .flags = FL_BASE0, 3350 .num_ports = 2, 3351 .base_baud = 921600, 3352 .uart_offset = 0x200, 3353 }, 3354 [pbn_exar_XR17C154] = { 3355 .flags = FL_BASE0, 3356 .num_ports = 4, 3357 .base_baud = 921600, 3358 .uart_offset = 0x200, 3359 }, 3360 [pbn_exar_XR17C158] = { 3361 .flags = FL_BASE0, 3362 .num_ports = 8, 3363 .base_baud = 921600, 3364 .uart_offset = 0x200, 3365 }, 3366 [pbn_exar_XR17V352] = { 3367 .flags = FL_BASE0, 3368 .num_ports = 2, 3369 .base_baud = 7812500, 3370 .uart_offset = 0x400, 3371 .reg_shift = 0, 3372 .first_offset = 0, 3373 }, 3374 [pbn_exar_XR17V354] = { 3375 .flags = FL_BASE0, 3376 .num_ports = 4, 3377 .base_baud = 7812500, 3378 .uart_offset = 0x400, 3379 .reg_shift = 0, 3380 .first_offset = 0, 3381 }, 3382 [pbn_exar_XR17V358] = { 3383 .flags = FL_BASE0, 3384 .num_ports = 8, 3385 .base_baud = 7812500, 3386 .uart_offset = 0x400, 3387 .reg_shift = 0, 3388 .first_offset = 0, 3389 }, 3390 [pbn_exar_ibm_saturn] = { 3391 .flags = FL_BASE0, 3392 .num_ports = 1, 3393 .base_baud = 921600, 3394 .uart_offset = 0x200, 3395 }, 3396 3397 /* 3398 * PA Semi PWRficient PA6T-1682M on-chip UART 3399 */ 3400 [pbn_pasemi_1682M] = { 3401 .flags = FL_BASE0, 3402 .num_ports = 1, 3403 .base_baud = 8333333, 3404 }, 3405 /* 3406 * National Instruments 843x 3407 */ 3408 [pbn_ni8430_16] = { 3409 .flags = FL_BASE0, 3410 .num_ports = 16, 3411 .base_baud = 3686400, 3412 .uart_offset = 0x10, 3413 .first_offset = 0x800, 3414 }, 3415 [pbn_ni8430_8] = { 3416 .flags = FL_BASE0, 3417 .num_ports = 8, 3418 .base_baud = 3686400, 3419 .uart_offset = 0x10, 3420 .first_offset = 0x800, 3421 }, 3422 [pbn_ni8430_4] = { 3423 .flags = FL_BASE0, 3424 .num_ports = 4, 3425 .base_baud = 3686400, 3426 .uart_offset = 0x10, 3427 .first_offset = 0x800, 3428 }, 3429 [pbn_ni8430_2] = { 3430 .flags = FL_BASE0, 3431 .num_ports = 2, 3432 .base_baud = 3686400, 3433 .uart_offset = 0x10, 3434 .first_offset = 0x800, 3435 }, 3436 /* 3437 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3438 */ 3439 [pbn_ADDIDATA_PCIe_1_3906250] = { 3440 .flags = FL_BASE0, 3441 .num_ports = 1, 3442 .base_baud = 3906250, 3443 .uart_offset = 0x200, 3444 .first_offset = 0x1000, 3445 }, 3446 [pbn_ADDIDATA_PCIe_2_3906250] = { 3447 .flags = FL_BASE0, 3448 .num_ports = 2, 3449 .base_baud = 3906250, 3450 .uart_offset = 0x200, 3451 .first_offset = 0x1000, 3452 }, 3453 [pbn_ADDIDATA_PCIe_4_3906250] = { 3454 .flags = FL_BASE0, 3455 .num_ports = 4, 3456 .base_baud = 3906250, 3457 .uart_offset = 0x200, 3458 .first_offset = 0x1000, 3459 }, 3460 [pbn_ADDIDATA_PCIe_8_3906250] = { 3461 .flags = FL_BASE0, 3462 .num_ports = 8, 3463 .base_baud = 3906250, 3464 .uart_offset = 0x200, 3465 .first_offset = 0x1000, 3466 }, 3467 [pbn_ce4100_1_115200] = { 3468 .flags = FL_BASE_BARS, 3469 .num_ports = 2, 3470 .base_baud = 921600, 3471 .reg_shift = 2, 3472 }, 3473 /* 3474 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3475 * but is overridden by byt_set_termios. 3476 */ 3477 [pbn_byt] = { 3478 .flags = FL_BASE0, 3479 .num_ports = 1, 3480 .base_baud = 2764800, 3481 .uart_offset = 0x80, 3482 .reg_shift = 2, 3483 }, 3484 [pbn_omegapci] = { 3485 .flags = FL_BASE0, 3486 .num_ports = 8, 3487 .base_baud = 115200, 3488 .uart_offset = 0x200, 3489 }, 3490 [pbn_NETMOS9900_2s_115200] = { 3491 .flags = FL_BASE0, 3492 .num_ports = 2, 3493 .base_baud = 115200, 3494 }, 3495 [pbn_brcm_trumanage] = { 3496 .flags = FL_BASE0, 3497 .num_ports = 1, 3498 .reg_shift = 2, 3499 .base_baud = 115200, 3500 }, 3501 [pbn_fintek_4] = { 3502 .num_ports = 4, 3503 .uart_offset = 8, 3504 .base_baud = 115200, 3505 .first_offset = 0x40, 3506 }, 3507 [pbn_fintek_8] = { 3508 .num_ports = 8, 3509 .uart_offset = 8, 3510 .base_baud = 115200, 3511 .first_offset = 0x40, 3512 }, 3513 [pbn_fintek_12] = { 3514 .num_ports = 12, 3515 .uart_offset = 8, 3516 .base_baud = 115200, 3517 .first_offset = 0x40, 3518 }, 3519 }; 3520 3521 static const struct pci_device_id blacklist[] = { 3522 /* softmodems */ 3523 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3524 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3525 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3526 3527 /* multi-io cards handled by parport_serial */ 3528 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3529 }; 3530 3531 /* 3532 * Given a complete unknown PCI device, try to use some heuristics to 3533 * guess what the configuration might be, based on the pitiful PCI 3534 * serial specs. Returns 0 on success, 1 on failure. 3535 */ 3536 static int 3537 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3538 { 3539 const struct pci_device_id *bldev; 3540 int num_iomem, num_port, first_port = -1, i; 3541 3542 /* 3543 * If it is not a communications device or the programming 3544 * interface is greater than 6, give up. 3545 * 3546 * (Should we try to make guesses for multiport serial devices 3547 * later?) 3548 */ 3549 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3550 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3551 (dev->class & 0xff) > 6) 3552 return -ENODEV; 3553 3554 /* 3555 * Do not access blacklisted devices that are known not to 3556 * feature serial ports or are handled by other modules. 3557 */ 3558 for (bldev = blacklist; 3559 bldev < blacklist + ARRAY_SIZE(blacklist); 3560 bldev++) { 3561 if (dev->vendor == bldev->vendor && 3562 dev->device == bldev->device) 3563 return -ENODEV; 3564 } 3565 3566 num_iomem = num_port = 0; 3567 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3568 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3569 num_port++; 3570 if (first_port == -1) 3571 first_port = i; 3572 } 3573 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3574 num_iomem++; 3575 } 3576 3577 /* 3578 * If there is 1 or 0 iomem regions, and exactly one port, 3579 * use it. We guess the number of ports based on the IO 3580 * region size. 3581 */ 3582 if (num_iomem <= 1 && num_port == 1) { 3583 board->flags = first_port; 3584 board->num_ports = pci_resource_len(dev, first_port) / 8; 3585 return 0; 3586 } 3587 3588 /* 3589 * Now guess if we've got a board which indexes by BARs. 3590 * Each IO BAR should be 8 bytes, and they should follow 3591 * consecutively. 3592 */ 3593 first_port = -1; 3594 num_port = 0; 3595 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3596 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3597 pci_resource_len(dev, i) == 8 && 3598 (first_port == -1 || (first_port + num_port) == i)) { 3599 num_port++; 3600 if (first_port == -1) 3601 first_port = i; 3602 } 3603 } 3604 3605 if (num_port > 1) { 3606 board->flags = first_port | FL_BASE_BARS; 3607 board->num_ports = num_port; 3608 return 0; 3609 } 3610 3611 return -ENODEV; 3612 } 3613 3614 static inline int 3615 serial_pci_matches(const struct pciserial_board *board, 3616 const struct pciserial_board *guessed) 3617 { 3618 return 3619 board->num_ports == guessed->num_ports && 3620 board->base_baud == guessed->base_baud && 3621 board->uart_offset == guessed->uart_offset && 3622 board->reg_shift == guessed->reg_shift && 3623 board->first_offset == guessed->first_offset; 3624 } 3625 3626 struct serial_private * 3627 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3628 { 3629 struct uart_8250_port uart; 3630 struct serial_private *priv; 3631 struct pci_serial_quirk *quirk; 3632 int rc, nr_ports, i; 3633 3634 nr_ports = board->num_ports; 3635 3636 /* 3637 * Find an init and setup quirks. 3638 */ 3639 quirk = find_quirk(dev); 3640 3641 /* 3642 * Run the new-style initialization function. 3643 * The initialization function returns: 3644 * <0 - error 3645 * 0 - use board->num_ports 3646 * >0 - number of ports 3647 */ 3648 if (quirk->init) { 3649 rc = quirk->init(dev); 3650 if (rc < 0) { 3651 priv = ERR_PTR(rc); 3652 goto err_out; 3653 } 3654 if (rc) 3655 nr_ports = rc; 3656 } 3657 3658 priv = kzalloc(sizeof(struct serial_private) + 3659 sizeof(unsigned int) * nr_ports, 3660 GFP_KERNEL); 3661 if (!priv) { 3662 priv = ERR_PTR(-ENOMEM); 3663 goto err_deinit; 3664 } 3665 3666 priv->dev = dev; 3667 priv->quirk = quirk; 3668 3669 memset(&uart, 0, sizeof(uart)); 3670 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3671 uart.port.uartclk = board->base_baud * 16; 3672 uart.port.irq = get_pci_irq(dev, board); 3673 uart.port.dev = &dev->dev; 3674 3675 for (i = 0; i < nr_ports; i++) { 3676 if (quirk->setup(priv, board, &uart, i)) 3677 break; 3678 3679 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3680 uart.port.iobase, uart.port.irq, uart.port.iotype); 3681 3682 priv->line[i] = serial8250_register_8250_port(&uart); 3683 if (priv->line[i] < 0) { 3684 dev_err(&dev->dev, 3685 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3686 uart.port.iobase, uart.port.irq, 3687 uart.port.iotype, priv->line[i]); 3688 break; 3689 } 3690 } 3691 priv->nr = i; 3692 return priv; 3693 3694 err_deinit: 3695 if (quirk->exit) 3696 quirk->exit(dev); 3697 err_out: 3698 return priv; 3699 } 3700 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3701 3702 void pciserial_remove_ports(struct serial_private *priv) 3703 { 3704 struct pci_serial_quirk *quirk; 3705 int i; 3706 3707 for (i = 0; i < priv->nr; i++) 3708 serial8250_unregister_port(priv->line[i]); 3709 3710 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3711 if (priv->remapped_bar[i]) 3712 iounmap(priv->remapped_bar[i]); 3713 priv->remapped_bar[i] = NULL; 3714 } 3715 3716 /* 3717 * Find the exit quirks. 3718 */ 3719 quirk = find_quirk(priv->dev); 3720 if (quirk->exit) 3721 quirk->exit(priv->dev); 3722 3723 kfree(priv); 3724 } 3725 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3726 3727 void pciserial_suspend_ports(struct serial_private *priv) 3728 { 3729 int i; 3730 3731 for (i = 0; i < priv->nr; i++) 3732 if (priv->line[i] >= 0) 3733 serial8250_suspend_port(priv->line[i]); 3734 3735 /* 3736 * Ensure that every init quirk is properly torn down 3737 */ 3738 if (priv->quirk->exit) 3739 priv->quirk->exit(priv->dev); 3740 } 3741 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3742 3743 void pciserial_resume_ports(struct serial_private *priv) 3744 { 3745 int i; 3746 3747 /* 3748 * Ensure that the board is correctly configured. 3749 */ 3750 if (priv->quirk->init) 3751 priv->quirk->init(priv->dev); 3752 3753 for (i = 0; i < priv->nr; i++) 3754 if (priv->line[i] >= 0) 3755 serial8250_resume_port(priv->line[i]); 3756 } 3757 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3758 3759 /* 3760 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3761 * to the arrangement of serial ports on a PCI card. 3762 */ 3763 static int 3764 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3765 { 3766 struct pci_serial_quirk *quirk; 3767 struct serial_private *priv; 3768 const struct pciserial_board *board; 3769 struct pciserial_board tmp; 3770 int rc; 3771 3772 quirk = find_quirk(dev); 3773 if (quirk->probe) { 3774 rc = quirk->probe(dev); 3775 if (rc) 3776 return rc; 3777 } 3778 3779 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3780 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3781 ent->driver_data); 3782 return -EINVAL; 3783 } 3784 3785 board = &pci_boards[ent->driver_data]; 3786 3787 rc = pci_enable_device(dev); 3788 pci_save_state(dev); 3789 if (rc) 3790 return rc; 3791 3792 if (ent->driver_data == pbn_default) { 3793 /* 3794 * Use a copy of the pci_board entry for this; 3795 * avoid changing entries in the table. 3796 */ 3797 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3798 board = &tmp; 3799 3800 /* 3801 * We matched one of our class entries. Try to 3802 * determine the parameters of this board. 3803 */ 3804 rc = serial_pci_guess_board(dev, &tmp); 3805 if (rc) 3806 goto disable; 3807 } else { 3808 /* 3809 * We matched an explicit entry. If we are able to 3810 * detect this boards settings with our heuristic, 3811 * then we no longer need this entry. 3812 */ 3813 memcpy(&tmp, &pci_boards[pbn_default], 3814 sizeof(struct pciserial_board)); 3815 rc = serial_pci_guess_board(dev, &tmp); 3816 if (rc == 0 && serial_pci_matches(board, &tmp)) 3817 moan_device("Redundant entry in serial pci_table.", 3818 dev); 3819 } 3820 3821 priv = pciserial_init_ports(dev, board); 3822 if (!IS_ERR(priv)) { 3823 pci_set_drvdata(dev, priv); 3824 return 0; 3825 } 3826 3827 rc = PTR_ERR(priv); 3828 3829 disable: 3830 pci_disable_device(dev); 3831 return rc; 3832 } 3833 3834 static void pciserial_remove_one(struct pci_dev *dev) 3835 { 3836 struct serial_private *priv = pci_get_drvdata(dev); 3837 3838 pciserial_remove_ports(priv); 3839 3840 pci_disable_device(dev); 3841 } 3842 3843 #ifdef CONFIG_PM 3844 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) 3845 { 3846 struct serial_private *priv = pci_get_drvdata(dev); 3847 3848 if (priv) 3849 pciserial_suspend_ports(priv); 3850 3851 pci_save_state(dev); 3852 pci_set_power_state(dev, pci_choose_state(dev, state)); 3853 return 0; 3854 } 3855 3856 static int pciserial_resume_one(struct pci_dev *dev) 3857 { 3858 int err; 3859 struct serial_private *priv = pci_get_drvdata(dev); 3860 3861 pci_set_power_state(dev, PCI_D0); 3862 pci_restore_state(dev); 3863 3864 if (priv) { 3865 /* 3866 * The device may have been disabled. Re-enable it. 3867 */ 3868 err = pci_enable_device(dev); 3869 /* FIXME: We cannot simply error out here */ 3870 if (err) 3871 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n"); 3872 pciserial_resume_ports(priv); 3873 } 3874 return 0; 3875 } 3876 #endif 3877 3878 static struct pci_device_id serial_pci_tbl[] = { 3879 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3880 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3881 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3882 pbn_b2_8_921600 }, 3883 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3884 PCI_SUBVENDOR_ID_CONNECT_TECH, 3885 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3886 pbn_b1_8_1382400 }, 3887 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3888 PCI_SUBVENDOR_ID_CONNECT_TECH, 3889 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3890 pbn_b1_4_1382400 }, 3891 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3892 PCI_SUBVENDOR_ID_CONNECT_TECH, 3893 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3894 pbn_b1_2_1382400 }, 3895 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3896 PCI_SUBVENDOR_ID_CONNECT_TECH, 3897 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3898 pbn_b1_8_1382400 }, 3899 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3900 PCI_SUBVENDOR_ID_CONNECT_TECH, 3901 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3902 pbn_b1_4_1382400 }, 3903 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3904 PCI_SUBVENDOR_ID_CONNECT_TECH, 3905 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3906 pbn_b1_2_1382400 }, 3907 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3908 PCI_SUBVENDOR_ID_CONNECT_TECH, 3909 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3910 pbn_b1_8_921600 }, 3911 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3912 PCI_SUBVENDOR_ID_CONNECT_TECH, 3913 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3914 pbn_b1_8_921600 }, 3915 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3916 PCI_SUBVENDOR_ID_CONNECT_TECH, 3917 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3918 pbn_b1_4_921600 }, 3919 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3920 PCI_SUBVENDOR_ID_CONNECT_TECH, 3921 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3922 pbn_b1_4_921600 }, 3923 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3924 PCI_SUBVENDOR_ID_CONNECT_TECH, 3925 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3926 pbn_b1_2_921600 }, 3927 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3928 PCI_SUBVENDOR_ID_CONNECT_TECH, 3929 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3930 pbn_b1_8_921600 }, 3931 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3932 PCI_SUBVENDOR_ID_CONNECT_TECH, 3933 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3934 pbn_b1_8_921600 }, 3935 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3936 PCI_SUBVENDOR_ID_CONNECT_TECH, 3937 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3938 pbn_b1_4_921600 }, 3939 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3940 PCI_SUBVENDOR_ID_CONNECT_TECH, 3941 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 3942 pbn_b1_2_1250000 }, 3943 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3944 PCI_SUBVENDOR_ID_CONNECT_TECH, 3945 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 3946 pbn_b0_2_1843200 }, 3947 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3948 PCI_SUBVENDOR_ID_CONNECT_TECH, 3949 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 3950 pbn_b0_4_1843200 }, 3951 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3952 PCI_VENDOR_ID_AFAVLAB, 3953 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 3954 pbn_b0_4_1152000 }, 3955 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3956 PCI_SUBVENDOR_ID_CONNECT_TECH, 3957 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 3958 pbn_b0_2_1843200_200 }, 3959 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3960 PCI_SUBVENDOR_ID_CONNECT_TECH, 3961 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 3962 pbn_b0_4_1843200_200 }, 3963 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3964 PCI_SUBVENDOR_ID_CONNECT_TECH, 3965 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 3966 pbn_b0_8_1843200_200 }, 3967 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3968 PCI_SUBVENDOR_ID_CONNECT_TECH, 3969 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 3970 pbn_b0_2_1843200_200 }, 3971 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3972 PCI_SUBVENDOR_ID_CONNECT_TECH, 3973 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 3974 pbn_b0_4_1843200_200 }, 3975 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3976 PCI_SUBVENDOR_ID_CONNECT_TECH, 3977 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 3978 pbn_b0_8_1843200_200 }, 3979 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3980 PCI_SUBVENDOR_ID_CONNECT_TECH, 3981 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 3982 pbn_b0_2_1843200_200 }, 3983 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3984 PCI_SUBVENDOR_ID_CONNECT_TECH, 3985 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 3986 pbn_b0_4_1843200_200 }, 3987 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3988 PCI_SUBVENDOR_ID_CONNECT_TECH, 3989 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 3990 pbn_b0_8_1843200_200 }, 3991 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3992 PCI_SUBVENDOR_ID_CONNECT_TECH, 3993 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 3994 pbn_b0_2_1843200_200 }, 3995 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3996 PCI_SUBVENDOR_ID_CONNECT_TECH, 3997 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 3998 pbn_b0_4_1843200_200 }, 3999 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4000 PCI_SUBVENDOR_ID_CONNECT_TECH, 4001 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4002 pbn_b0_8_1843200_200 }, 4003 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4004 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4005 0, 0, pbn_exar_ibm_saturn }, 4006 4007 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4008 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4009 pbn_b2_bt_1_115200 }, 4010 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4011 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4012 pbn_b2_bt_2_115200 }, 4013 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4014 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4015 pbn_b2_bt_4_115200 }, 4016 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4017 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4018 pbn_b2_bt_2_115200 }, 4019 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4020 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4021 pbn_b2_bt_4_115200 }, 4022 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4023 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4024 pbn_b2_8_115200 }, 4025 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4026 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4027 pbn_b2_8_460800 }, 4028 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4029 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4030 pbn_b2_8_115200 }, 4031 4032 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4034 pbn_b2_bt_2_115200 }, 4035 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4037 pbn_b2_bt_2_921600 }, 4038 /* 4039 * VScom SPCOM800, from sl@s.pl 4040 */ 4041 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4043 pbn_b2_8_921600 }, 4044 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4046 pbn_b2_4_921600 }, 4047 /* Unknown card - subdevice 0x1584 */ 4048 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4049 PCI_VENDOR_ID_PLX, 4050 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4051 pbn_b2_4_115200 }, 4052 /* Unknown card - subdevice 0x1588 */ 4053 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4054 PCI_VENDOR_ID_PLX, 4055 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4056 pbn_b2_8_115200 }, 4057 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4058 PCI_SUBVENDOR_ID_KEYSPAN, 4059 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4060 pbn_panacom }, 4061 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4063 pbn_panacom4 }, 4064 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4065 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4066 pbn_panacom2 }, 4067 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4068 PCI_VENDOR_ID_ESDGMBH, 4069 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4070 pbn_b2_4_115200 }, 4071 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4072 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4073 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4074 pbn_b2_4_460800 }, 4075 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4076 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4077 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4078 pbn_b2_8_460800 }, 4079 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4080 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4081 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4082 pbn_b2_16_460800 }, 4083 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4084 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4085 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4086 pbn_b2_16_460800 }, 4087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4088 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4089 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4090 pbn_b2_4_460800 }, 4091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4092 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4093 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4094 pbn_b2_8_460800 }, 4095 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4096 PCI_SUBVENDOR_ID_EXSYS, 4097 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4098 pbn_b2_4_115200 }, 4099 /* 4100 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4101 * (Exoray@isys.ca) 4102 */ 4103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4104 0x10b5, 0x106a, 0, 0, 4105 pbn_plx_romulus }, 4106 /* 4107 * Quatech cards. These actually have configurable clocks but for 4108 * now we just use the default. 4109 * 4110 * 100 series are RS232, 200 series RS422, 4111 */ 4112 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4114 pbn_b1_4_115200 }, 4115 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4117 pbn_b1_2_115200 }, 4118 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4120 pbn_b2_2_115200 }, 4121 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4123 pbn_b1_2_115200 }, 4124 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4126 pbn_b2_2_115200 }, 4127 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4129 pbn_b1_4_115200 }, 4130 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4132 pbn_b1_8_115200 }, 4133 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4135 pbn_b1_8_115200 }, 4136 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4138 pbn_b1_4_115200 }, 4139 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4141 pbn_b1_2_115200 }, 4142 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4144 pbn_b1_4_115200 }, 4145 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4147 pbn_b1_2_115200 }, 4148 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4150 pbn_b2_4_115200 }, 4151 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4153 pbn_b2_2_115200 }, 4154 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4156 pbn_b2_1_115200 }, 4157 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4159 pbn_b2_4_115200 }, 4160 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4162 pbn_b2_2_115200 }, 4163 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4165 pbn_b2_1_115200 }, 4166 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4168 pbn_b0_8_115200 }, 4169 4170 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4171 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4172 0, 0, 4173 pbn_b0_4_921600 }, 4174 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4175 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4176 0, 0, 4177 pbn_b0_4_1152000 }, 4178 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4180 pbn_b0_bt_2_921600 }, 4181 4182 /* 4183 * The below card is a little controversial since it is the 4184 * subject of a PCI vendor/device ID clash. (See 4185 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4186 * For now just used the hex ID 0x950a. 4187 */ 4188 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4189 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4190 0, 0, pbn_b0_2_115200 }, 4191 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4192 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4193 0, 0, pbn_b0_2_115200 }, 4194 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b0_2_1130000 }, 4197 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4198 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4199 pbn_b0_1_921600 }, 4200 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4202 pbn_b0_4_115200 }, 4203 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b0_bt_2_921600 }, 4206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4207 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4208 pbn_b2_8_1152000 }, 4209 4210 /* 4211 * Oxford Semiconductor Inc. Tornado PCI express device range. 4212 */ 4213 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4215 pbn_b0_1_4000000 }, 4216 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4218 pbn_b0_1_4000000 }, 4219 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4221 pbn_oxsemi_1_4000000 }, 4222 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4224 pbn_oxsemi_1_4000000 }, 4225 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4227 pbn_b0_1_4000000 }, 4228 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_b0_1_4000000 }, 4231 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4233 pbn_oxsemi_1_4000000 }, 4234 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4236 pbn_oxsemi_1_4000000 }, 4237 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4239 pbn_b0_1_4000000 }, 4240 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4242 pbn_b0_1_4000000 }, 4243 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4245 pbn_b0_1_4000000 }, 4246 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4248 pbn_b0_1_4000000 }, 4249 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4251 pbn_oxsemi_2_4000000 }, 4252 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4254 pbn_oxsemi_2_4000000 }, 4255 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4257 pbn_oxsemi_4_4000000 }, 4258 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4260 pbn_oxsemi_4_4000000 }, 4261 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4263 pbn_oxsemi_8_4000000 }, 4264 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4266 pbn_oxsemi_8_4000000 }, 4267 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4269 pbn_oxsemi_1_4000000 }, 4270 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4272 pbn_oxsemi_1_4000000 }, 4273 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4275 pbn_oxsemi_1_4000000 }, 4276 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4278 pbn_oxsemi_1_4000000 }, 4279 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4281 pbn_oxsemi_1_4000000 }, 4282 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4284 pbn_oxsemi_1_4000000 }, 4285 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4287 pbn_oxsemi_1_4000000 }, 4288 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4290 pbn_oxsemi_1_4000000 }, 4291 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_oxsemi_1_4000000 }, 4294 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_oxsemi_1_4000000 }, 4297 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4299 pbn_oxsemi_1_4000000 }, 4300 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4302 pbn_oxsemi_1_4000000 }, 4303 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4305 pbn_oxsemi_1_4000000 }, 4306 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4308 pbn_oxsemi_1_4000000 }, 4309 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4311 pbn_oxsemi_1_4000000 }, 4312 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4314 pbn_oxsemi_1_4000000 }, 4315 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4317 pbn_oxsemi_1_4000000 }, 4318 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4320 pbn_oxsemi_1_4000000 }, 4321 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4323 pbn_oxsemi_1_4000000 }, 4324 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4326 pbn_oxsemi_1_4000000 }, 4327 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4329 pbn_oxsemi_1_4000000 }, 4330 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4332 pbn_oxsemi_1_4000000 }, 4333 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4335 pbn_oxsemi_1_4000000 }, 4336 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4338 pbn_oxsemi_1_4000000 }, 4339 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4341 pbn_oxsemi_1_4000000 }, 4342 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4344 pbn_oxsemi_1_4000000 }, 4345 /* 4346 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4347 */ 4348 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4349 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4350 pbn_oxsemi_1_4000000 }, 4351 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4352 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4353 pbn_oxsemi_2_4000000 }, 4354 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4355 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4356 pbn_oxsemi_4_4000000 }, 4357 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4358 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4359 pbn_oxsemi_8_4000000 }, 4360 4361 /* 4362 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4363 */ 4364 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4365 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4366 pbn_oxsemi_2_4000000 }, 4367 4368 /* 4369 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4370 * from skokodyn@yahoo.com 4371 */ 4372 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4373 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4374 pbn_sbsxrsio }, 4375 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4376 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4377 pbn_sbsxrsio }, 4378 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4379 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4380 pbn_sbsxrsio }, 4381 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4382 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4383 pbn_sbsxrsio }, 4384 4385 /* 4386 * Digitan DS560-558, from jimd@esoft.com 4387 */ 4388 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_b1_1_115200 }, 4391 4392 /* 4393 * Titan Electronic cards 4394 * The 400L and 800L have a custom setup quirk. 4395 */ 4396 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4398 pbn_b0_1_921600 }, 4399 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b0_2_921600 }, 4402 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b0_4_921600 }, 4405 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_b0_4_921600 }, 4408 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_b1_1_921600 }, 4411 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b1_bt_2_921600 }, 4414 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b0_bt_4_921600 }, 4417 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_b0_bt_8_921600 }, 4420 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_b4_bt_2_921600 }, 4423 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_b4_bt_4_921600 }, 4426 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_b4_bt_8_921600 }, 4429 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_b0_4_921600 }, 4432 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_b0_4_921600 }, 4435 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_b0_4_921600 }, 4438 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_oxsemi_1_4000000 }, 4441 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_oxsemi_2_4000000 }, 4444 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_oxsemi_4_4000000 }, 4447 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_oxsemi_8_4000000 }, 4450 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_oxsemi_2_4000000 }, 4453 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_oxsemi_2_4000000 }, 4456 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_b0_bt_2_921600 }, 4459 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_b0_4_921600 }, 4462 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_b0_4_921600 }, 4465 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_b0_4_921600 }, 4468 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_b0_4_921600 }, 4471 4472 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_b2_1_460800 }, 4475 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_b2_1_460800 }, 4478 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_b2_1_460800 }, 4481 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_b2_bt_2_921600 }, 4484 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_b2_bt_2_921600 }, 4487 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_b2_bt_2_921600 }, 4490 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_b2_bt_4_921600 }, 4493 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_b2_bt_4_921600 }, 4496 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_b2_bt_4_921600 }, 4499 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_b0_1_921600 }, 4502 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_b0_1_921600 }, 4505 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_b0_1_921600 }, 4508 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_b0_bt_2_921600 }, 4511 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_b0_bt_2_921600 }, 4514 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_b0_bt_2_921600 }, 4517 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_b0_bt_4_921600 }, 4520 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_b0_bt_4_921600 }, 4523 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_b0_bt_4_921600 }, 4526 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_b0_bt_8_921600 }, 4529 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_b0_bt_8_921600 }, 4532 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4534 pbn_b0_bt_8_921600 }, 4535 4536 /* 4537 * Computone devices submitted by Doug McNash dmcnash@computone.com 4538 */ 4539 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4540 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4541 0, 0, pbn_computone_4 }, 4542 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4543 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4544 0, 0, pbn_computone_8 }, 4545 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4546 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4547 0, 0, pbn_computone_6 }, 4548 4549 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_oxsemi }, 4552 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4553 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4554 pbn_b0_bt_1_921600 }, 4555 4556 /* 4557 * SUNIX (TIMEDIA) 4558 */ 4559 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4560 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4561 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4562 pbn_b0_bt_1_921600 }, 4563 4564 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4565 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4566 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4567 pbn_b0_bt_1_921600 }, 4568 4569 /* 4570 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4571 */ 4572 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_b0_bt_8_115200 }, 4575 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_b0_bt_8_115200 }, 4578 4579 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_b0_bt_2_115200 }, 4582 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_b0_bt_2_115200 }, 4585 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4587 pbn_b0_bt_2_115200 }, 4588 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4590 pbn_b0_bt_2_115200 }, 4591 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_b0_bt_2_115200 }, 4594 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4596 pbn_b0_bt_4_460800 }, 4597 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b0_bt_4_460800 }, 4600 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b0_bt_2_460800 }, 4603 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4605 pbn_b0_bt_2_460800 }, 4606 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_b0_bt_2_460800 }, 4609 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_b0_bt_1_115200 }, 4612 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_b0_bt_1_460800 }, 4615 4616 /* 4617 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4618 * Cards are identified by their subsystem vendor IDs, which 4619 * (in hex) match the model number. 4620 * 4621 * Note that JC140x are RS422/485 cards which require ox950 4622 * ACR = 0x10, and as such are not currently fully supported. 4623 */ 4624 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4625 0x1204, 0x0004, 0, 0, 4626 pbn_b0_4_921600 }, 4627 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4628 0x1208, 0x0004, 0, 0, 4629 pbn_b0_4_921600 }, 4630 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4631 0x1402, 0x0002, 0, 0, 4632 pbn_b0_2_921600 }, */ 4633 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4634 0x1404, 0x0004, 0, 0, 4635 pbn_b0_4_921600 }, */ 4636 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4637 0x1208, 0x0004, 0, 0, 4638 pbn_b0_4_921600 }, 4639 4640 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4641 0x1204, 0x0004, 0, 0, 4642 pbn_b0_4_921600 }, 4643 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4644 0x1208, 0x0004, 0, 0, 4645 pbn_b0_4_921600 }, 4646 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4647 0x1208, 0x0004, 0, 0, 4648 pbn_b0_4_921600 }, 4649 /* 4650 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4651 */ 4652 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b1_1_1382400 }, 4655 4656 /* 4657 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4658 */ 4659 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b1_1_1382400 }, 4662 4663 /* 4664 * RAStel 2 port modem, gerg@moreton.com.au 4665 */ 4666 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_b2_bt_2_115200 }, 4669 4670 /* 4671 * EKF addition for i960 Boards form EKF with serial port 4672 */ 4673 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4674 0xE4BF, PCI_ANY_ID, 0, 0, 4675 pbn_intel_i960 }, 4676 4677 /* 4678 * Xircom Cardbus/Ethernet combos 4679 */ 4680 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b0_1_115200 }, 4683 /* 4684 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4685 */ 4686 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b0_1_115200 }, 4689 4690 /* 4691 * Untested PCI modems, sent in from various folks... 4692 */ 4693 4694 /* 4695 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4696 */ 4697 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4698 0x1048, 0x1500, 0, 0, 4699 pbn_b1_1_115200 }, 4700 4701 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4702 0xFF00, 0, 0, 0, 4703 pbn_sgi_ioc3 }, 4704 4705 /* 4706 * HP Diva card 4707 */ 4708 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4709 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4710 pbn_b1_1_115200 }, 4711 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_5_115200 }, 4714 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_b2_1_115200 }, 4717 4718 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4720 pbn_b3_2_115200 }, 4721 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4723 pbn_b3_4_115200 }, 4724 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_b3_8_115200 }, 4727 4728 /* 4729 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4730 */ 4731 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4732 PCI_ANY_ID, PCI_ANY_ID, 4733 0, 4734 0, pbn_exar_XR17C152 }, 4735 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4736 PCI_ANY_ID, PCI_ANY_ID, 4737 0, 4738 0, pbn_exar_XR17C154 }, 4739 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4740 PCI_ANY_ID, PCI_ANY_ID, 4741 0, 4742 0, pbn_exar_XR17C158 }, 4743 /* 4744 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs 4745 */ 4746 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4747 PCI_ANY_ID, PCI_ANY_ID, 4748 0, 4749 0, pbn_exar_XR17V352 }, 4750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4751 PCI_ANY_ID, PCI_ANY_ID, 4752 0, 4753 0, pbn_exar_XR17V354 }, 4754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4755 PCI_ANY_ID, PCI_ANY_ID, 4756 0, 4757 0, pbn_exar_XR17V358 }, 4758 4759 /* 4760 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4761 */ 4762 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b0_1_115200 }, 4765 /* 4766 * ITE 4767 */ 4768 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4769 PCI_ANY_ID, PCI_ANY_ID, 4770 0, 0, 4771 pbn_b1_bt_1_115200 }, 4772 4773 /* 4774 * IntaShield IS-200 4775 */ 4776 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4778 pbn_b2_2_115200 }, 4779 /* 4780 * IntaShield IS-400 4781 */ 4782 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4784 pbn_b2_4_115200 }, 4785 /* 4786 * Perle PCI-RAS cards 4787 */ 4788 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4789 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4790 0, 0, pbn_b2_4_921600 }, 4791 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4792 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4793 0, 0, pbn_b2_8_921600 }, 4794 4795 /* 4796 * Mainpine series cards: Fairly standard layout but fools 4797 * parts of the autodetect in some cases and uses otherwise 4798 * unmatched communications subclasses in the PCI Express case 4799 */ 4800 4801 { /* RockForceDUO */ 4802 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4803 PCI_VENDOR_ID_MAINPINE, 0x0200, 4804 0, 0, pbn_b0_2_115200 }, 4805 { /* RockForceQUATRO */ 4806 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4807 PCI_VENDOR_ID_MAINPINE, 0x0300, 4808 0, 0, pbn_b0_4_115200 }, 4809 { /* RockForceDUO+ */ 4810 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4811 PCI_VENDOR_ID_MAINPINE, 0x0400, 4812 0, 0, pbn_b0_2_115200 }, 4813 { /* RockForceQUATRO+ */ 4814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4815 PCI_VENDOR_ID_MAINPINE, 0x0500, 4816 0, 0, pbn_b0_4_115200 }, 4817 { /* RockForce+ */ 4818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4819 PCI_VENDOR_ID_MAINPINE, 0x0600, 4820 0, 0, pbn_b0_2_115200 }, 4821 { /* RockForce+ */ 4822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4823 PCI_VENDOR_ID_MAINPINE, 0x0700, 4824 0, 0, pbn_b0_4_115200 }, 4825 { /* RockForceOCTO+ */ 4826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4827 PCI_VENDOR_ID_MAINPINE, 0x0800, 4828 0, 0, pbn_b0_8_115200 }, 4829 { /* RockForceDUO+ */ 4830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4831 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4832 0, 0, pbn_b0_2_115200 }, 4833 { /* RockForceQUARTRO+ */ 4834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4835 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4836 0, 0, pbn_b0_4_115200 }, 4837 { /* RockForceOCTO+ */ 4838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4839 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4840 0, 0, pbn_b0_8_115200 }, 4841 { /* RockForceD1 */ 4842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4843 PCI_VENDOR_ID_MAINPINE, 0x2000, 4844 0, 0, pbn_b0_1_115200 }, 4845 { /* RockForceF1 */ 4846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4847 PCI_VENDOR_ID_MAINPINE, 0x2100, 4848 0, 0, pbn_b0_1_115200 }, 4849 { /* RockForceD2 */ 4850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4851 PCI_VENDOR_ID_MAINPINE, 0x2200, 4852 0, 0, pbn_b0_2_115200 }, 4853 { /* RockForceF2 */ 4854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4855 PCI_VENDOR_ID_MAINPINE, 0x2300, 4856 0, 0, pbn_b0_2_115200 }, 4857 { /* RockForceD4 */ 4858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4859 PCI_VENDOR_ID_MAINPINE, 0x2400, 4860 0, 0, pbn_b0_4_115200 }, 4861 { /* RockForceF4 */ 4862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4863 PCI_VENDOR_ID_MAINPINE, 0x2500, 4864 0, 0, pbn_b0_4_115200 }, 4865 { /* RockForceD8 */ 4866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4867 PCI_VENDOR_ID_MAINPINE, 0x2600, 4868 0, 0, pbn_b0_8_115200 }, 4869 { /* RockForceF8 */ 4870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4871 PCI_VENDOR_ID_MAINPINE, 0x2700, 4872 0, 0, pbn_b0_8_115200 }, 4873 { /* IQ Express D1 */ 4874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4875 PCI_VENDOR_ID_MAINPINE, 0x3000, 4876 0, 0, pbn_b0_1_115200 }, 4877 { /* IQ Express F1 */ 4878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4879 PCI_VENDOR_ID_MAINPINE, 0x3100, 4880 0, 0, pbn_b0_1_115200 }, 4881 { /* IQ Express D2 */ 4882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4883 PCI_VENDOR_ID_MAINPINE, 0x3200, 4884 0, 0, pbn_b0_2_115200 }, 4885 { /* IQ Express F2 */ 4886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4887 PCI_VENDOR_ID_MAINPINE, 0x3300, 4888 0, 0, pbn_b0_2_115200 }, 4889 { /* IQ Express D4 */ 4890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4891 PCI_VENDOR_ID_MAINPINE, 0x3400, 4892 0, 0, pbn_b0_4_115200 }, 4893 { /* IQ Express F4 */ 4894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4895 PCI_VENDOR_ID_MAINPINE, 0x3500, 4896 0, 0, pbn_b0_4_115200 }, 4897 { /* IQ Express D8 */ 4898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4899 PCI_VENDOR_ID_MAINPINE, 0x3C00, 4900 0, 0, pbn_b0_8_115200 }, 4901 { /* IQ Express F8 */ 4902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4903 PCI_VENDOR_ID_MAINPINE, 0x3D00, 4904 0, 0, pbn_b0_8_115200 }, 4905 4906 4907 /* 4908 * PA Semi PA6T-1682M on-chip UART 4909 */ 4910 { PCI_VENDOR_ID_PASEMI, 0xa004, 4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4912 pbn_pasemi_1682M }, 4913 4914 /* 4915 * National Instruments 4916 */ 4917 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4919 pbn_b1_16_115200 }, 4920 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4922 pbn_b1_8_115200 }, 4923 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4925 pbn_b1_bt_4_115200 }, 4926 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4928 pbn_b1_bt_2_115200 }, 4929 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4931 pbn_b1_bt_4_115200 }, 4932 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4934 pbn_b1_bt_2_115200 }, 4935 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4937 pbn_b1_16_115200 }, 4938 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4940 pbn_b1_8_115200 }, 4941 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4943 pbn_b1_bt_4_115200 }, 4944 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4946 pbn_b1_bt_2_115200 }, 4947 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4949 pbn_b1_bt_4_115200 }, 4950 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4952 pbn_b1_bt_2_115200 }, 4953 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4955 pbn_ni8430_2 }, 4956 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4958 pbn_ni8430_2 }, 4959 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4961 pbn_ni8430_4 }, 4962 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4964 pbn_ni8430_4 }, 4965 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4967 pbn_ni8430_8 }, 4968 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4970 pbn_ni8430_8 }, 4971 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4973 pbn_ni8430_16 }, 4974 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4976 pbn_ni8430_16 }, 4977 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4979 pbn_ni8430_2 }, 4980 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_ni8430_2 }, 4983 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_ni8430_4 }, 4986 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4988 pbn_ni8430_4 }, 4989 4990 /* 4991 * ADDI-DATA GmbH communication cards <info@addi-data.com> 4992 */ 4993 { PCI_VENDOR_ID_ADDIDATA, 4994 PCI_DEVICE_ID_ADDIDATA_APCI7500, 4995 PCI_ANY_ID, 4996 PCI_ANY_ID, 4997 0, 4998 0, 4999 pbn_b0_4_115200 }, 5000 5001 { PCI_VENDOR_ID_ADDIDATA, 5002 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5003 PCI_ANY_ID, 5004 PCI_ANY_ID, 5005 0, 5006 0, 5007 pbn_b0_2_115200 }, 5008 5009 { PCI_VENDOR_ID_ADDIDATA, 5010 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5011 PCI_ANY_ID, 5012 PCI_ANY_ID, 5013 0, 5014 0, 5015 pbn_b0_1_115200 }, 5016 5017 { PCI_VENDOR_ID_AMCC, 5018 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5019 PCI_ANY_ID, 5020 PCI_ANY_ID, 5021 0, 5022 0, 5023 pbn_b1_8_115200 }, 5024 5025 { PCI_VENDOR_ID_ADDIDATA, 5026 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5027 PCI_ANY_ID, 5028 PCI_ANY_ID, 5029 0, 5030 0, 5031 pbn_b0_4_115200 }, 5032 5033 { PCI_VENDOR_ID_ADDIDATA, 5034 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5035 PCI_ANY_ID, 5036 PCI_ANY_ID, 5037 0, 5038 0, 5039 pbn_b0_2_115200 }, 5040 5041 { PCI_VENDOR_ID_ADDIDATA, 5042 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5043 PCI_ANY_ID, 5044 PCI_ANY_ID, 5045 0, 5046 0, 5047 pbn_b0_1_115200 }, 5048 5049 { PCI_VENDOR_ID_ADDIDATA, 5050 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5051 PCI_ANY_ID, 5052 PCI_ANY_ID, 5053 0, 5054 0, 5055 pbn_b0_4_115200 }, 5056 5057 { PCI_VENDOR_ID_ADDIDATA, 5058 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5059 PCI_ANY_ID, 5060 PCI_ANY_ID, 5061 0, 5062 0, 5063 pbn_b0_2_115200 }, 5064 5065 { PCI_VENDOR_ID_ADDIDATA, 5066 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5067 PCI_ANY_ID, 5068 PCI_ANY_ID, 5069 0, 5070 0, 5071 pbn_b0_1_115200 }, 5072 5073 { PCI_VENDOR_ID_ADDIDATA, 5074 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5075 PCI_ANY_ID, 5076 PCI_ANY_ID, 5077 0, 5078 0, 5079 pbn_b0_8_115200 }, 5080 5081 { PCI_VENDOR_ID_ADDIDATA, 5082 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5083 PCI_ANY_ID, 5084 PCI_ANY_ID, 5085 0, 5086 0, 5087 pbn_ADDIDATA_PCIe_4_3906250 }, 5088 5089 { PCI_VENDOR_ID_ADDIDATA, 5090 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5091 PCI_ANY_ID, 5092 PCI_ANY_ID, 5093 0, 5094 0, 5095 pbn_ADDIDATA_PCIe_2_3906250 }, 5096 5097 { PCI_VENDOR_ID_ADDIDATA, 5098 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5099 PCI_ANY_ID, 5100 PCI_ANY_ID, 5101 0, 5102 0, 5103 pbn_ADDIDATA_PCIe_1_3906250 }, 5104 5105 { PCI_VENDOR_ID_ADDIDATA, 5106 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5107 PCI_ANY_ID, 5108 PCI_ANY_ID, 5109 0, 5110 0, 5111 pbn_ADDIDATA_PCIe_8_3906250 }, 5112 5113 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5114 PCI_VENDOR_ID_IBM, 0x0299, 5115 0, 0, pbn_b0_bt_2_115200 }, 5116 5117 /* 5118 * other NetMos 9835 devices are most likely handled by the 5119 * parport_serial driver, check drivers/parport/parport_serial.c 5120 * before adding them here. 5121 */ 5122 5123 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5124 0xA000, 0x1000, 5125 0, 0, pbn_b0_1_115200 }, 5126 5127 /* the 9901 is a rebranded 9912 */ 5128 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5129 0xA000, 0x1000, 5130 0, 0, pbn_b0_1_115200 }, 5131 5132 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5133 0xA000, 0x1000, 5134 0, 0, pbn_b0_1_115200 }, 5135 5136 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5137 0xA000, 0x1000, 5138 0, 0, pbn_b0_1_115200 }, 5139 5140 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5141 0xA000, 0x1000, 5142 0, 0, pbn_b0_1_115200 }, 5143 5144 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5145 0xA000, 0x3002, 5146 0, 0, pbn_NETMOS9900_2s_115200 }, 5147 5148 /* 5149 * Best Connectivity and Rosewill PCI Multi I/O cards 5150 */ 5151 5152 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5153 0xA000, 0x1000, 5154 0, 0, pbn_b0_1_115200 }, 5155 5156 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5157 0xA000, 0x3002, 5158 0, 0, pbn_b0_bt_2_115200 }, 5159 5160 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5161 0xA000, 0x3004, 5162 0, 0, pbn_b0_bt_4_115200 }, 5163 /* Intel CE4100 */ 5164 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5165 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5166 pbn_ce4100_1_115200 }, 5167 /* Intel BayTrail */ 5168 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5169 PCI_ANY_ID, PCI_ANY_ID, 5170 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5171 pbn_byt }, 5172 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5173 PCI_ANY_ID, PCI_ANY_ID, 5174 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5175 pbn_byt }, 5176 5177 /* 5178 * Cronyx Omega PCI 5179 */ 5180 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5182 pbn_omegapci }, 5183 5184 /* 5185 * Broadcom TruManage 5186 */ 5187 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5189 pbn_brcm_trumanage }, 5190 5191 /* 5192 * AgeStar as-prs2-009 5193 */ 5194 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5195 PCI_ANY_ID, PCI_ANY_ID, 5196 0, 0, pbn_b0_bt_2_115200 }, 5197 5198 /* 5199 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5200 * so not listed here. 5201 */ 5202 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5203 PCI_ANY_ID, PCI_ANY_ID, 5204 0, 0, pbn_b0_bt_4_115200 }, 5205 5206 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5207 PCI_ANY_ID, PCI_ANY_ID, 5208 0, 0, pbn_b0_bt_2_115200 }, 5209 5210 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S, 5211 PCI_ANY_ID, PCI_ANY_ID, 5212 0, 0, pbn_b0_bt_2_115200 }, 5213 5214 /* 5215 * Commtech, Inc. Fastcom adapters 5216 */ 5217 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5218 PCI_ANY_ID, PCI_ANY_ID, 5219 0, 5220 0, pbn_b0_2_1152000_200 }, 5221 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5222 PCI_ANY_ID, PCI_ANY_ID, 5223 0, 5224 0, pbn_b0_4_1152000_200 }, 5225 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5226 PCI_ANY_ID, PCI_ANY_ID, 5227 0, 5228 0, pbn_b0_4_1152000_200 }, 5229 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5230 PCI_ANY_ID, PCI_ANY_ID, 5231 0, 5232 0, pbn_b0_8_1152000_200 }, 5233 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5234 PCI_ANY_ID, PCI_ANY_ID, 5235 0, 5236 0, pbn_exar_XR17V352 }, 5237 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5238 PCI_ANY_ID, PCI_ANY_ID, 5239 0, 5240 0, pbn_exar_XR17V354 }, 5241 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5242 PCI_ANY_ID, PCI_ANY_ID, 5243 0, 5244 0, pbn_exar_XR17V358 }, 5245 5246 /* Fintek PCI serial cards */ 5247 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5248 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5249 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5250 5251 /* 5252 * These entries match devices with class COMMUNICATION_SERIAL, 5253 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5254 */ 5255 { PCI_ANY_ID, PCI_ANY_ID, 5256 PCI_ANY_ID, PCI_ANY_ID, 5257 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5258 0xffff00, pbn_default }, 5259 { PCI_ANY_ID, PCI_ANY_ID, 5260 PCI_ANY_ID, PCI_ANY_ID, 5261 PCI_CLASS_COMMUNICATION_MODEM << 8, 5262 0xffff00, pbn_default }, 5263 { PCI_ANY_ID, PCI_ANY_ID, 5264 PCI_ANY_ID, PCI_ANY_ID, 5265 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5266 0xffff00, pbn_default }, 5267 { 0, } 5268 }; 5269 5270 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5271 pci_channel_state_t state) 5272 { 5273 struct serial_private *priv = pci_get_drvdata(dev); 5274 5275 if (state == pci_channel_io_perm_failure) 5276 return PCI_ERS_RESULT_DISCONNECT; 5277 5278 if (priv) 5279 pciserial_suspend_ports(priv); 5280 5281 pci_disable_device(dev); 5282 5283 return PCI_ERS_RESULT_NEED_RESET; 5284 } 5285 5286 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5287 { 5288 int rc; 5289 5290 rc = pci_enable_device(dev); 5291 5292 if (rc) 5293 return PCI_ERS_RESULT_DISCONNECT; 5294 5295 pci_restore_state(dev); 5296 pci_save_state(dev); 5297 5298 return PCI_ERS_RESULT_RECOVERED; 5299 } 5300 5301 static void serial8250_io_resume(struct pci_dev *dev) 5302 { 5303 struct serial_private *priv = pci_get_drvdata(dev); 5304 5305 if (priv) 5306 pciserial_resume_ports(priv); 5307 } 5308 5309 static const struct pci_error_handlers serial8250_err_handler = { 5310 .error_detected = serial8250_io_error_detected, 5311 .slot_reset = serial8250_io_slot_reset, 5312 .resume = serial8250_io_resume, 5313 }; 5314 5315 static struct pci_driver serial_pci_driver = { 5316 .name = "serial", 5317 .probe = pciserial_init_one, 5318 .remove = pciserial_remove_one, 5319 #ifdef CONFIG_PM 5320 .suspend = pciserial_suspend_one, 5321 .resume = pciserial_resume_one, 5322 #endif 5323 .id_table = serial_pci_tbl, 5324 .err_handler = &serial8250_err_handler, 5325 }; 5326 5327 module_pci_driver(serial_pci_driver); 5328 5329 MODULE_LICENSE("GPL"); 5330 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5331 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5332