1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 #define PCI_NUM_BAR_RESOURCES 6 47 48 struct serial_private { 49 struct pci_dev *dev; 50 unsigned int nr; 51 struct pci_serial_quirk *quirk; 52 const struct pciserial_board *board; 53 int line[0]; 54 }; 55 56 static int pci_default_setup(struct serial_private*, 57 const struct pciserial_board*, struct uart_8250_port *, int); 58 59 static void moan_device(const char *str, struct pci_dev *dev) 60 { 61 dev_err(&dev->dev, 62 "%s: %s\n" 63 "Please send the output of lspci -vv, this\n" 64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 65 "manufacturer and name of serial board or\n" 66 "modem board to <linux-serial@vger.kernel.org>.\n", 67 pci_name(dev), str, dev->vendor, dev->device, 68 dev->subsystem_vendor, dev->subsystem_device); 69 } 70 71 static int 72 setup_port(struct serial_private *priv, struct uart_8250_port *port, 73 int bar, int offset, int regshift) 74 { 75 struct pci_dev *dev = priv->dev; 76 77 if (bar >= PCI_NUM_BAR_RESOURCES) 78 return -EINVAL; 79 80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 82 return -ENOMEM; 83 84 port->port.iotype = UPIO_MEM; 85 port->port.iobase = 0; 86 port->port.mapbase = pci_resource_start(dev, bar) + offset; 87 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 88 port->port.regshift = regshift; 89 } else { 90 port->port.iotype = UPIO_PORT; 91 port->port.iobase = pci_resource_start(dev, bar) + offset; 92 port->port.mapbase = 0; 93 port->port.membase = NULL; 94 port->port.regshift = 0; 95 } 96 return 0; 97 } 98 99 /* 100 * ADDI-DATA GmbH communication cards <info@addi-data.com> 101 */ 102 static int addidata_apci7800_setup(struct serial_private *priv, 103 const struct pciserial_board *board, 104 struct uart_8250_port *port, int idx) 105 { 106 unsigned int bar = 0, offset = board->first_offset; 107 bar = FL_GET_BASE(board->flags); 108 109 if (idx < 2) { 110 offset += idx * board->uart_offset; 111 } else if ((idx >= 2) && (idx < 4)) { 112 bar += 1; 113 offset += ((idx - 2) * board->uart_offset); 114 } else if ((idx >= 4) && (idx < 6)) { 115 bar += 2; 116 offset += ((idx - 4) * board->uart_offset); 117 } else if (idx >= 6) { 118 bar += 3; 119 offset += ((idx - 6) * board->uart_offset); 120 } 121 122 return setup_port(priv, port, bar, offset, board->reg_shift); 123 } 124 125 /* 126 * AFAVLAB uses a different mixture of BARs and offsets 127 * Not that ugly ;) -- HW 128 */ 129 static int 130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 131 struct uart_8250_port *port, int idx) 132 { 133 unsigned int bar, offset = board->first_offset; 134 135 bar = FL_GET_BASE(board->flags); 136 if (idx < 4) 137 bar += idx; 138 else { 139 bar = 4; 140 offset += (idx - 4) * board->uart_offset; 141 } 142 143 return setup_port(priv, port, bar, offset, board->reg_shift); 144 } 145 146 /* 147 * HP's Remote Management Console. The Diva chip came in several 148 * different versions. N-class, L2000 and A500 have two Diva chips, each 149 * with 3 UARTs (the third UART on the second chip is unused). Superdome 150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 151 * one Diva chip, but it has been expanded to 5 UARTs. 152 */ 153 static int pci_hp_diva_init(struct pci_dev *dev) 154 { 155 int rc = 0; 156 157 switch (dev->subsystem_device) { 158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 161 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 162 rc = 3; 163 break; 164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 165 rc = 2; 166 break; 167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 168 rc = 4; 169 break; 170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 172 rc = 1; 173 break; 174 } 175 176 return rc; 177 } 178 179 /* 180 * HP's Diva chip puts the 4th/5th serial port further out, and 181 * some serial ports are supposed to be hidden on certain models. 182 */ 183 static int 184 pci_hp_diva_setup(struct serial_private *priv, 185 const struct pciserial_board *board, 186 struct uart_8250_port *port, int idx) 187 { 188 unsigned int offset = board->first_offset; 189 unsigned int bar = FL_GET_BASE(board->flags); 190 191 switch (priv->dev->subsystem_device) { 192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 193 if (idx == 3) 194 idx++; 195 break; 196 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 197 if (idx > 0) 198 idx++; 199 if (idx > 2) 200 idx++; 201 break; 202 } 203 if (idx > 2) 204 offset = 0x18; 205 206 offset += idx * board->uart_offset; 207 208 return setup_port(priv, port, bar, offset, board->reg_shift); 209 } 210 211 /* 212 * Added for EKF Intel i960 serial boards 213 */ 214 static int pci_inteli960ni_init(struct pci_dev *dev) 215 { 216 u32 oldval; 217 218 if (!(dev->subsystem_device & 0x1000)) 219 return -ENODEV; 220 221 /* is firmware started? */ 222 pci_read_config_dword(dev, 0x44, &oldval); 223 if (oldval == 0x00001000L) { /* RESET value */ 224 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 225 return -ENODEV; 226 } 227 return 0; 228 } 229 230 /* 231 * Some PCI serial cards using the PLX 9050 PCI interface chip require 232 * that the card interrupt be explicitly enabled or disabled. This 233 * seems to be mainly needed on card using the PLX which also use I/O 234 * mapped memory. 235 */ 236 static int pci_plx9050_init(struct pci_dev *dev) 237 { 238 u8 irq_config; 239 void __iomem *p; 240 241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 242 moan_device("no memory in bar 0", dev); 243 return 0; 244 } 245 246 irq_config = 0x41; 247 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 249 irq_config = 0x43; 250 251 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 253 /* 254 * As the megawolf cards have the int pins active 255 * high, and have 2 UART chips, both ints must be 256 * enabled on the 9050. Also, the UARTS are set in 257 * 16450 mode by default, so we have to enable the 258 * 16C950 'enhanced' mode so that we can use the 259 * deep FIFOs 260 */ 261 irq_config = 0x5b; 262 /* 263 * enable/disable interrupts 264 */ 265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 266 if (p == NULL) 267 return -ENOMEM; 268 writel(irq_config, p + 0x4c); 269 270 /* 271 * Read the register back to ensure that it took effect. 272 */ 273 readl(p + 0x4c); 274 iounmap(p); 275 276 return 0; 277 } 278 279 static void pci_plx9050_exit(struct pci_dev *dev) 280 { 281 u8 __iomem *p; 282 283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 284 return; 285 286 /* 287 * disable interrupts 288 */ 289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 290 if (p != NULL) { 291 writel(0, p + 0x4c); 292 293 /* 294 * Read the register back to ensure that it took effect. 295 */ 296 readl(p + 0x4c); 297 iounmap(p); 298 } 299 } 300 301 #define NI8420_INT_ENABLE_REG 0x38 302 #define NI8420_INT_ENABLE_BIT 0x2000 303 304 static void pci_ni8420_exit(struct pci_dev *dev) 305 { 306 void __iomem *p; 307 unsigned int bar = 0; 308 309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 310 moan_device("no memory in bar", dev); 311 return; 312 } 313 314 p = pci_ioremap_bar(dev, bar); 315 if (p == NULL) 316 return; 317 318 /* Disable the CPU Interrupt */ 319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 320 p + NI8420_INT_ENABLE_REG); 321 iounmap(p); 322 } 323 324 325 /* MITE registers */ 326 #define MITE_IOWBSR1 0xc4 327 #define MITE_IOWCR1 0xf4 328 #define MITE_LCIMR1 0x08 329 #define MITE_LCIMR2 0x10 330 331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 332 333 static void pci_ni8430_exit(struct pci_dev *dev) 334 { 335 void __iomem *p; 336 unsigned int bar = 0; 337 338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 339 moan_device("no memory in bar", dev); 340 return; 341 } 342 343 p = pci_ioremap_bar(dev, bar); 344 if (p == NULL) 345 return; 346 347 /* Disable the CPU Interrupt */ 348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 349 iounmap(p); 350 } 351 352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 353 static int 354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 355 struct uart_8250_port *port, int idx) 356 { 357 unsigned int bar, offset = board->first_offset; 358 359 bar = 0; 360 361 if (idx < 4) { 362 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 363 offset += idx * board->uart_offset; 364 } else if (idx < 8) { 365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 366 offset += idx * board->uart_offset + 0xC00; 367 } else /* we have only 8 ports on PMC-OCTALPRO */ 368 return 1; 369 370 return setup_port(priv, port, bar, offset, board->reg_shift); 371 } 372 373 /* 374 * This does initialization for PMC OCTALPRO cards: 375 * maps the device memory, resets the UARTs (needed, bc 376 * if the module is removed and inserted again, the card 377 * is in the sleep mode) and enables global interrupt. 378 */ 379 380 /* global control register offset for SBS PMC-OctalPro */ 381 #define OCT_REG_CR_OFF 0x500 382 383 static int sbs_init(struct pci_dev *dev) 384 { 385 u8 __iomem *p; 386 387 p = pci_ioremap_bar(dev, 0); 388 389 if (p == NULL) 390 return -ENOMEM; 391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 392 writeb(0x10, p + OCT_REG_CR_OFF); 393 udelay(50); 394 writeb(0x0, p + OCT_REG_CR_OFF); 395 396 /* Set bit-2 (INTENABLE) of Control Register */ 397 writeb(0x4, p + OCT_REG_CR_OFF); 398 iounmap(p); 399 400 return 0; 401 } 402 403 /* 404 * Disables the global interrupt of PMC-OctalPro 405 */ 406 407 static void sbs_exit(struct pci_dev *dev) 408 { 409 u8 __iomem *p; 410 411 p = pci_ioremap_bar(dev, 0); 412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 413 if (p != NULL) 414 writeb(0, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 } 417 418 /* 419 * SIIG serial cards have an PCI interface chip which also controls 420 * the UART clocking frequency. Each UART can be clocked independently 421 * (except cards equipped with 4 UARTs) and initial clocking settings 422 * are stored in the EEPROM chip. It can cause problems because this 423 * version of serial driver doesn't support differently clocked UART's 424 * on single PCI card. To prevent this, initialization functions set 425 * high frequency clocking for all UART's on given card. It is safe (I 426 * hope) because it doesn't touch EEPROM settings to prevent conflicts 427 * with other OSes (like M$ DOS). 428 * 429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 430 * 431 * There is two family of SIIG serial cards with different PCI 432 * interface chip and different configuration methods: 433 * - 10x cards have control registers in IO and/or memory space; 434 * - 20x cards have control registers in standard PCI configuration space. 435 * 436 * Note: all 10x cards have PCI device ids 0x10.. 437 * all 20x cards have PCI device ids 0x20.. 438 * 439 * There are also Quartet Serial cards which use Oxford Semiconductor 440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 441 * 442 * Note: some SIIG cards are probed by the parport_serial object. 443 */ 444 445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 447 448 static int pci_siig10x_init(struct pci_dev *dev) 449 { 450 u16 data; 451 void __iomem *p; 452 453 switch (dev->device & 0xfff8) { 454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 455 data = 0xffdf; 456 break; 457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 458 data = 0xf7ff; 459 break; 460 default: /* 1S1P, 4S */ 461 data = 0xfffb; 462 break; 463 } 464 465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 466 if (p == NULL) 467 return -ENOMEM; 468 469 writew(readw(p + 0x28) & data, p + 0x28); 470 readw(p + 0x28); 471 iounmap(p); 472 return 0; 473 } 474 475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 477 478 static int pci_siig20x_init(struct pci_dev *dev) 479 { 480 u8 data; 481 482 /* Change clock frequency for the first UART. */ 483 pci_read_config_byte(dev, 0x6f, &data); 484 pci_write_config_byte(dev, 0x6f, data & 0xef); 485 486 /* If this card has 2 UART, we have to do the same with second UART. */ 487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 489 pci_read_config_byte(dev, 0x73, &data); 490 pci_write_config_byte(dev, 0x73, data & 0xef); 491 } 492 return 0; 493 } 494 495 static int pci_siig_init(struct pci_dev *dev) 496 { 497 unsigned int type = dev->device & 0xff00; 498 499 if (type == 0x1000) 500 return pci_siig10x_init(dev); 501 else if (type == 0x2000) 502 return pci_siig20x_init(dev); 503 504 moan_device("Unknown SIIG card", dev); 505 return -ENODEV; 506 } 507 508 static int pci_siig_setup(struct serial_private *priv, 509 const struct pciserial_board *board, 510 struct uart_8250_port *port, int idx) 511 { 512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 513 514 if (idx > 3) { 515 bar = 4; 516 offset = (idx - 4) * 8; 517 } 518 519 return setup_port(priv, port, bar, offset, 0); 520 } 521 522 /* 523 * Timedia has an explosion of boards, and to avoid the PCI table from 524 * growing *huge*, we use this function to collapse some 70 entries 525 * in the PCI table into one, for sanity's and compactness's sake. 526 */ 527 static const unsigned short timedia_single_port[] = { 528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 529 }; 530 531 static const unsigned short timedia_dual_port[] = { 532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 536 0xD079, 0 537 }; 538 539 static const unsigned short timedia_quad_port[] = { 540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 543 0xB157, 0 544 }; 545 546 static const unsigned short timedia_eight_port[] = { 547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 549 }; 550 551 static const struct timedia_struct { 552 int num; 553 const unsigned short *ids; 554 } timedia_data[] = { 555 { 1, timedia_single_port }, 556 { 2, timedia_dual_port }, 557 { 4, timedia_quad_port }, 558 { 8, timedia_eight_port } 559 }; 560 561 /* 562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 563 * listing them individually, this driver merely grabs them all with 564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 565 * and should be left free to be claimed by parport_serial instead. 566 */ 567 static int pci_timedia_probe(struct pci_dev *dev) 568 { 569 /* 570 * Check the third digit of the subdevice ID 571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 572 */ 573 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 574 dev_info(&dev->dev, 575 "ignoring Timedia subdevice %04x for parport_serial\n", 576 dev->subsystem_device); 577 return -ENODEV; 578 } 579 580 return 0; 581 } 582 583 static int pci_timedia_init(struct pci_dev *dev) 584 { 585 const unsigned short *ids; 586 int i, j; 587 588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 589 ids = timedia_data[i].ids; 590 for (j = 0; ids[j]; j++) 591 if (dev->subsystem_device == ids[j]) 592 return timedia_data[i].num; 593 } 594 return 0; 595 } 596 597 /* 598 * Timedia/SUNIX uses a mixture of BARs and offsets 599 * Ugh, this is ugly as all hell --- TYT 600 */ 601 static int 602 pci_timedia_setup(struct serial_private *priv, 603 const struct pciserial_board *board, 604 struct uart_8250_port *port, int idx) 605 { 606 unsigned int bar = 0, offset = board->first_offset; 607 608 switch (idx) { 609 case 0: 610 bar = 0; 611 break; 612 case 1: 613 offset = board->uart_offset; 614 bar = 0; 615 break; 616 case 2: 617 bar = 1; 618 break; 619 case 3: 620 offset = board->uart_offset; 621 /* FALLTHROUGH */ 622 case 4: /* BAR 2 */ 623 case 5: /* BAR 3 */ 624 case 6: /* BAR 4 */ 625 case 7: /* BAR 5 */ 626 bar = idx - 2; 627 } 628 629 return setup_port(priv, port, bar, offset, board->reg_shift); 630 } 631 632 /* 633 * Some Titan cards are also a little weird 634 */ 635 static int 636 titan_400l_800l_setup(struct serial_private *priv, 637 const struct pciserial_board *board, 638 struct uart_8250_port *port, int idx) 639 { 640 unsigned int bar, offset = board->first_offset; 641 642 switch (idx) { 643 case 0: 644 bar = 1; 645 break; 646 case 1: 647 bar = 2; 648 break; 649 default: 650 bar = 4; 651 offset = (idx - 2) * board->uart_offset; 652 } 653 654 return setup_port(priv, port, bar, offset, board->reg_shift); 655 } 656 657 static int pci_xircom_init(struct pci_dev *dev) 658 { 659 msleep(100); 660 return 0; 661 } 662 663 static int pci_ni8420_init(struct pci_dev *dev) 664 { 665 void __iomem *p; 666 unsigned int bar = 0; 667 668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 669 moan_device("no memory in bar", dev); 670 return 0; 671 } 672 673 p = pci_ioremap_bar(dev, bar); 674 if (p == NULL) 675 return -ENOMEM; 676 677 /* Enable CPU Interrupt */ 678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 679 p + NI8420_INT_ENABLE_REG); 680 681 iounmap(p); 682 return 0; 683 } 684 685 #define MITE_IOWBSR1_WSIZE 0xa 686 #define MITE_IOWBSR1_WIN_OFFSET 0x800 687 #define MITE_IOWBSR1_WENAB (1 << 7) 688 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 691 692 static int pci_ni8430_init(struct pci_dev *dev) 693 { 694 void __iomem *p; 695 struct pci_bus_region region; 696 u32 device_window; 697 unsigned int bar = 0; 698 699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 700 moan_device("no memory in bar", dev); 701 return 0; 702 } 703 704 p = pci_ioremap_bar(dev, bar); 705 if (p == NULL) 706 return -ENOMEM; 707 708 /* 709 * Set device window address and size in BAR0, while acknowledging that 710 * the resource structure may contain a translated address that differs 711 * from the address the device responds to. 712 */ 713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 716 writel(device_window, p + MITE_IOWBSR1); 717 718 /* Set window access to go to RAMSEL IO address space */ 719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 720 p + MITE_IOWCR1); 721 722 /* Enable IO Bus Interrupt 0 */ 723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 724 725 /* Enable CPU Interrupt */ 726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 727 728 iounmap(p); 729 return 0; 730 } 731 732 /* UART Port Control Register */ 733 #define NI8430_PORTCON 0x0f 734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 735 736 static int 737 pci_ni8430_setup(struct serial_private *priv, 738 const struct pciserial_board *board, 739 struct uart_8250_port *port, int idx) 740 { 741 struct pci_dev *dev = priv->dev; 742 void __iomem *p; 743 unsigned int bar, offset = board->first_offset; 744 745 if (idx >= board->num_ports) 746 return 1; 747 748 bar = FL_GET_BASE(board->flags); 749 offset += idx * board->uart_offset; 750 751 p = pci_ioremap_bar(dev, bar); 752 if (!p) 753 return -ENOMEM; 754 755 /* enable the transceiver */ 756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 757 p + offset + NI8430_PORTCON); 758 759 iounmap(p); 760 761 return setup_port(priv, port, bar, offset, board->reg_shift); 762 } 763 764 static int pci_netmos_9900_setup(struct serial_private *priv, 765 const struct pciserial_board *board, 766 struct uart_8250_port *port, int idx) 767 { 768 unsigned int bar; 769 770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 771 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 772 /* netmos apparently orders BARs by datasheet layout, so serial 773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 774 */ 775 bar = 3 * idx; 776 777 return setup_port(priv, port, bar, 0, board->reg_shift); 778 } else { 779 return pci_default_setup(priv, board, port, idx); 780 } 781 } 782 783 /* the 99xx series comes with a range of device IDs and a variety 784 * of capabilities: 785 * 786 * 9900 has varying capabilities and can cascade to sub-controllers 787 * (cascading should be purely internal) 788 * 9904 is hardwired with 4 serial ports 789 * 9912 and 9922 are hardwired with 2 serial ports 790 */ 791 static int pci_netmos_9900_numports(struct pci_dev *dev) 792 { 793 unsigned int c = dev->class; 794 unsigned int pi; 795 unsigned short sub_serports; 796 797 pi = c & 0xff; 798 799 if (pi == 2) 800 return 1; 801 802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 803 /* two possibilities: 0x30ps encodes number of parallel and 804 * serial ports, or 0x1000 indicates *something*. This is not 805 * immediately obvious, since the 2s1p+4s configuration seems 806 * to offer all functionality on functions 0..2, while still 807 * advertising the same function 3 as the 4s+2s1p config. 808 */ 809 sub_serports = dev->subsystem_device & 0xf; 810 if (sub_serports > 0) 811 return sub_serports; 812 813 dev_err(&dev->dev, 814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 815 return 0; 816 } 817 818 moan_device("unknown NetMos/Mostech program interface", dev); 819 return 0; 820 } 821 822 static int pci_netmos_init(struct pci_dev *dev) 823 { 824 /* subdevice 0x00PS means <P> parallel, <S> serial */ 825 unsigned int num_serial = dev->subsystem_device & 0xf; 826 827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 828 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 829 return 0; 830 831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 832 dev->subsystem_device == 0x0299) 833 return 0; 834 835 switch (dev->device) { /* FALLTHROUGH on all */ 836 case PCI_DEVICE_ID_NETMOS_9904: 837 case PCI_DEVICE_ID_NETMOS_9912: 838 case PCI_DEVICE_ID_NETMOS_9922: 839 case PCI_DEVICE_ID_NETMOS_9900: 840 num_serial = pci_netmos_9900_numports(dev); 841 break; 842 843 default: 844 break; 845 } 846 847 if (num_serial == 0) { 848 moan_device("unknown NetMos/Mostech device", dev); 849 return -ENODEV; 850 } 851 852 return num_serial; 853 } 854 855 /* 856 * These chips are available with optionally one parallel port and up to 857 * two serial ports. Unfortunately they all have the same product id. 858 * 859 * Basic configuration is done over a region of 32 I/O ports. The base 860 * ioport is called INTA or INTC, depending on docs/other drivers. 861 * 862 * The region of the 32 I/O ports is configured in POSIO0R... 863 */ 864 865 /* registers */ 866 #define ITE_887x_MISCR 0x9c 867 #define ITE_887x_INTCBAR 0x78 868 #define ITE_887x_UARTBAR 0x7c 869 #define ITE_887x_PS0BAR 0x10 870 #define ITE_887x_POSIO0 0x60 871 872 /* I/O space size */ 873 #define ITE_887x_IOSIZE 32 874 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 876 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 879 #define ITE_887x_POSIO_SPEED (3 << 29) 880 /* enable IO_Space bit */ 881 #define ITE_887x_POSIO_ENABLE (1 << 31) 882 883 static int pci_ite887x_init(struct pci_dev *dev) 884 { 885 /* inta_addr are the configuration addresses of the ITE */ 886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 887 0x200, 0x280, 0 }; 888 int ret, i, type; 889 struct resource *iobase = NULL; 890 u32 miscr, uartbar, ioport; 891 892 /* search for the base-ioport */ 893 i = 0; 894 while (inta_addr[i] && iobase == NULL) { 895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 896 "ite887x"); 897 if (iobase != NULL) { 898 /* write POSIO0R - speed | size | ioport */ 899 pci_write_config_dword(dev, ITE_887x_POSIO0, 900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 902 /* write INTCBAR - ioport */ 903 pci_write_config_dword(dev, ITE_887x_INTCBAR, 904 inta_addr[i]); 905 ret = inb(inta_addr[i]); 906 if (ret != 0xff) { 907 /* ioport connected */ 908 break; 909 } 910 release_region(iobase->start, ITE_887x_IOSIZE); 911 iobase = NULL; 912 } 913 i++; 914 } 915 916 if (!inta_addr[i]) { 917 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 918 return -ENODEV; 919 } 920 921 /* start of undocumented type checking (see parport_pc.c) */ 922 type = inb(iobase->start + 0x18) & 0x0f; 923 924 switch (type) { 925 case 0x2: /* ITE8871 (1P) */ 926 case 0xa: /* ITE8875 (1P) */ 927 ret = 0; 928 break; 929 case 0xe: /* ITE8872 (2S1P) */ 930 ret = 2; 931 break; 932 case 0x6: /* ITE8873 (1S) */ 933 ret = 1; 934 break; 935 case 0x8: /* ITE8874 (2S) */ 936 ret = 2; 937 break; 938 default: 939 moan_device("Unknown ITE887x", dev); 940 ret = -ENODEV; 941 } 942 943 /* configure all serial ports */ 944 for (i = 0; i < ret; i++) { 945 /* read the I/O port from the device */ 946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 947 &ioport); 948 ioport &= 0x0000FF00; /* the actual base address */ 949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 951 ITE_887x_POSIO_IOSIZE_8 | ioport); 952 953 /* write the ioport to the UARTBAR */ 954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 956 uartbar |= (ioport << (16 * i)); /* set the ioport */ 957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 958 959 /* get current config */ 960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 961 /* disable interrupts (UARTx_Routing[3:0]) */ 962 miscr &= ~(0xf << (12 - 4 * i)); 963 /* activate the UART (UARTx_En) */ 964 miscr |= 1 << (23 - i); 965 /* write new config with activated UART */ 966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 967 } 968 969 if (ret <= 0) { 970 /* the device has no UARTs if we get here */ 971 release_region(iobase->start, ITE_887x_IOSIZE); 972 } 973 974 return ret; 975 } 976 977 static void pci_ite887x_exit(struct pci_dev *dev) 978 { 979 u32 ioport; 980 /* the ioport is bit 0-15 in POSIO0R */ 981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 982 ioport &= 0xffff; 983 release_region(ioport, ITE_887x_IOSIZE); 984 } 985 986 /* 987 * EndRun Technologies. 988 * Determine the number of ports available on the device. 989 */ 990 #define PCI_VENDOR_ID_ENDRUN 0x7401 991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 992 993 static int pci_endrun_init(struct pci_dev *dev) 994 { 995 u8 __iomem *p; 996 unsigned long deviceID; 997 unsigned int number_uarts = 0; 998 999 /* EndRun device is all 0xexxx */ 1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1001 (dev->device & 0xf000) != 0xe000) 1002 return 0; 1003 1004 p = pci_iomap(dev, 0, 5); 1005 if (p == NULL) 1006 return -ENOMEM; 1007 1008 deviceID = ioread32(p); 1009 /* EndRun device */ 1010 if (deviceID == 0x07000200) { 1011 number_uarts = ioread8(p + 4); 1012 dev_dbg(&dev->dev, 1013 "%d ports detected on EndRun PCI Express device\n", 1014 number_uarts); 1015 } 1016 pci_iounmap(dev, p); 1017 return number_uarts; 1018 } 1019 1020 /* 1021 * Oxford Semiconductor Inc. 1022 * Check that device is part of the Tornado range of devices, then determine 1023 * the number of ports available on the device. 1024 */ 1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1026 { 1027 u8 __iomem *p; 1028 unsigned long deviceID; 1029 unsigned int number_uarts = 0; 1030 1031 /* OxSemi Tornado devices are all 0xCxxx */ 1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1033 (dev->device & 0xF000) != 0xC000) 1034 return 0; 1035 1036 p = pci_iomap(dev, 0, 5); 1037 if (p == NULL) 1038 return -ENOMEM; 1039 1040 deviceID = ioread32(p); 1041 /* Tornado device */ 1042 if (deviceID == 0x07000200) { 1043 number_uarts = ioread8(p + 4); 1044 dev_dbg(&dev->dev, 1045 "%d ports detected on Oxford PCI Express device\n", 1046 number_uarts); 1047 } 1048 pci_iounmap(dev, p); 1049 return number_uarts; 1050 } 1051 1052 static int pci_asix_setup(struct serial_private *priv, 1053 const struct pciserial_board *board, 1054 struct uart_8250_port *port, int idx) 1055 { 1056 port->bugs |= UART_BUG_PARITY; 1057 return pci_default_setup(priv, board, port, idx); 1058 } 1059 1060 /* Quatech devices have their own extra interface features */ 1061 1062 struct quatech_feature { 1063 u16 devid; 1064 bool amcc; 1065 }; 1066 1067 #define QPCR_TEST_FOR1 0x3F 1068 #define QPCR_TEST_GET1 0x00 1069 #define QPCR_TEST_FOR2 0x40 1070 #define QPCR_TEST_GET2 0x40 1071 #define QPCR_TEST_FOR3 0x80 1072 #define QPCR_TEST_GET3 0x40 1073 #define QPCR_TEST_FOR4 0xC0 1074 #define QPCR_TEST_GET4 0x80 1075 1076 #define QOPR_CLOCK_X1 0x0000 1077 #define QOPR_CLOCK_X2 0x0001 1078 #define QOPR_CLOCK_X4 0x0002 1079 #define QOPR_CLOCK_X8 0x0003 1080 #define QOPR_CLOCK_RATE_MASK 0x0003 1081 1082 1083 static struct quatech_feature quatech_cards[] = { 1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1103 { 0, } 1104 }; 1105 1106 static int pci_quatech_amcc(u16 devid) 1107 { 1108 struct quatech_feature *qf = &quatech_cards[0]; 1109 while (qf->devid) { 1110 if (qf->devid == devid) 1111 return qf->amcc; 1112 qf++; 1113 } 1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1115 return 0; 1116 }; 1117 1118 static int pci_quatech_rqopr(struct uart_8250_port *port) 1119 { 1120 unsigned long base = port->port.iobase; 1121 u8 LCR, val; 1122 1123 LCR = inb(base + UART_LCR); 1124 outb(0xBF, base + UART_LCR); 1125 val = inb(base + UART_SCR); 1126 outb(LCR, base + UART_LCR); 1127 return val; 1128 } 1129 1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1131 { 1132 unsigned long base = port->port.iobase; 1133 u8 LCR; 1134 1135 LCR = inb(base + UART_LCR); 1136 outb(0xBF, base + UART_LCR); 1137 inb(base + UART_SCR); 1138 outb(qopr, base + UART_SCR); 1139 outb(LCR, base + UART_LCR); 1140 } 1141 1142 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1143 { 1144 unsigned long base = port->port.iobase; 1145 u8 LCR, val, qmcr; 1146 1147 LCR = inb(base + UART_LCR); 1148 outb(0xBF, base + UART_LCR); 1149 val = inb(base + UART_SCR); 1150 outb(val | 0x10, base + UART_SCR); 1151 qmcr = inb(base + UART_MCR); 1152 outb(val, base + UART_SCR); 1153 outb(LCR, base + UART_LCR); 1154 1155 return qmcr; 1156 } 1157 1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1159 { 1160 unsigned long base = port->port.iobase; 1161 u8 LCR, val; 1162 1163 LCR = inb(base + UART_LCR); 1164 outb(0xBF, base + UART_LCR); 1165 val = inb(base + UART_SCR); 1166 outb(val | 0x10, base + UART_SCR); 1167 outb(qmcr, base + UART_MCR); 1168 outb(val, base + UART_SCR); 1169 outb(LCR, base + UART_LCR); 1170 } 1171 1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1173 { 1174 unsigned long base = port->port.iobase; 1175 u8 LCR, val; 1176 1177 LCR = inb(base + UART_LCR); 1178 outb(0xBF, base + UART_LCR); 1179 val = inb(base + UART_SCR); 1180 if (val & 0x20) { 1181 outb(0x80, UART_LCR); 1182 if (!(inb(UART_SCR) & 0x20)) { 1183 outb(LCR, base + UART_LCR); 1184 return 1; 1185 } 1186 } 1187 return 0; 1188 } 1189 1190 static int pci_quatech_test(struct uart_8250_port *port) 1191 { 1192 u8 reg, qopr; 1193 1194 qopr = pci_quatech_rqopr(port); 1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1196 reg = pci_quatech_rqopr(port) & 0xC0; 1197 if (reg != QPCR_TEST_GET1) 1198 return -EINVAL; 1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1200 reg = pci_quatech_rqopr(port) & 0xC0; 1201 if (reg != QPCR_TEST_GET2) 1202 return -EINVAL; 1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1204 reg = pci_quatech_rqopr(port) & 0xC0; 1205 if (reg != QPCR_TEST_GET3) 1206 return -EINVAL; 1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1208 reg = pci_quatech_rqopr(port) & 0xC0; 1209 if (reg != QPCR_TEST_GET4) 1210 return -EINVAL; 1211 1212 pci_quatech_wqopr(port, qopr); 1213 return 0; 1214 } 1215 1216 static int pci_quatech_clock(struct uart_8250_port *port) 1217 { 1218 u8 qopr, reg, set; 1219 unsigned long clock; 1220 1221 if (pci_quatech_test(port) < 0) 1222 return 1843200; 1223 1224 qopr = pci_quatech_rqopr(port); 1225 1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1227 reg = pci_quatech_rqopr(port); 1228 if (reg & QOPR_CLOCK_X8) { 1229 clock = 1843200; 1230 goto out; 1231 } 1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1233 reg = pci_quatech_rqopr(port); 1234 if (!(reg & QOPR_CLOCK_X8)) { 1235 clock = 1843200; 1236 goto out; 1237 } 1238 reg &= QOPR_CLOCK_X8; 1239 if (reg == QOPR_CLOCK_X2) { 1240 clock = 3685400; 1241 set = QOPR_CLOCK_X2; 1242 } else if (reg == QOPR_CLOCK_X4) { 1243 clock = 7372800; 1244 set = QOPR_CLOCK_X4; 1245 } else if (reg == QOPR_CLOCK_X8) { 1246 clock = 14745600; 1247 set = QOPR_CLOCK_X8; 1248 } else { 1249 clock = 1843200; 1250 set = QOPR_CLOCK_X1; 1251 } 1252 qopr &= ~QOPR_CLOCK_RATE_MASK; 1253 qopr |= set; 1254 1255 out: 1256 pci_quatech_wqopr(port, qopr); 1257 return clock; 1258 } 1259 1260 static int pci_quatech_rs422(struct uart_8250_port *port) 1261 { 1262 u8 qmcr; 1263 int rs422 = 0; 1264 1265 if (!pci_quatech_has_qmcr(port)) 1266 return 0; 1267 qmcr = pci_quatech_rqmcr(port); 1268 pci_quatech_wqmcr(port, 0xFF); 1269 if (pci_quatech_rqmcr(port)) 1270 rs422 = 1; 1271 pci_quatech_wqmcr(port, qmcr); 1272 return rs422; 1273 } 1274 1275 static int pci_quatech_init(struct pci_dev *dev) 1276 { 1277 if (pci_quatech_amcc(dev->device)) { 1278 unsigned long base = pci_resource_start(dev, 0); 1279 if (base) { 1280 u32 tmp; 1281 1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1283 tmp = inl(base + 0x3c); 1284 outl(tmp | 0x01000000, base + 0x3c); 1285 outl(tmp &= ~0x01000000, base + 0x3c); 1286 } 1287 } 1288 return 0; 1289 } 1290 1291 static int pci_quatech_setup(struct serial_private *priv, 1292 const struct pciserial_board *board, 1293 struct uart_8250_port *port, int idx) 1294 { 1295 /* Needed by pci_quatech calls below */ 1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1297 /* Set up the clocking */ 1298 port->port.uartclk = pci_quatech_clock(port); 1299 /* For now just warn about RS422 */ 1300 if (pci_quatech_rs422(port)) 1301 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1302 return pci_default_setup(priv, board, port, idx); 1303 } 1304 1305 static void pci_quatech_exit(struct pci_dev *dev) 1306 { 1307 } 1308 1309 static int pci_default_setup(struct serial_private *priv, 1310 const struct pciserial_board *board, 1311 struct uart_8250_port *port, int idx) 1312 { 1313 unsigned int bar, offset = board->first_offset, maxnr; 1314 1315 bar = FL_GET_BASE(board->flags); 1316 if (board->flags & FL_BASE_BARS) 1317 bar += idx; 1318 else 1319 offset += idx * board->uart_offset; 1320 1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1322 (board->reg_shift + 3); 1323 1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1325 return 1; 1326 1327 return setup_port(priv, port, bar, offset, board->reg_shift); 1328 } 1329 1330 static int pci_pericom_setup(struct serial_private *priv, 1331 const struct pciserial_board *board, 1332 struct uart_8250_port *port, int idx) 1333 { 1334 unsigned int bar, offset = board->first_offset, maxnr; 1335 1336 bar = FL_GET_BASE(board->flags); 1337 if (board->flags & FL_BASE_BARS) 1338 bar += idx; 1339 else 1340 offset += idx * board->uart_offset; 1341 1342 if (idx==3) 1343 offset = 0x38; 1344 1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1346 (board->reg_shift + 3); 1347 1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1349 return 1; 1350 1351 return setup_port(priv, port, bar, offset, board->reg_shift); 1352 } 1353 1354 static int 1355 ce4100_serial_setup(struct serial_private *priv, 1356 const struct pciserial_board *board, 1357 struct uart_8250_port *port, int idx) 1358 { 1359 int ret; 1360 1361 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1362 port->port.iotype = UPIO_MEM32; 1363 port->port.type = PORT_XSCALE; 1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1365 port->port.regshift = 2; 1366 1367 return ret; 1368 } 1369 1370 static int 1371 pci_omegapci_setup(struct serial_private *priv, 1372 const struct pciserial_board *board, 1373 struct uart_8250_port *port, int idx) 1374 { 1375 return setup_port(priv, port, 2, idx * 8, 0); 1376 } 1377 1378 static int 1379 pci_brcm_trumanage_setup(struct serial_private *priv, 1380 const struct pciserial_board *board, 1381 struct uart_8250_port *port, int idx) 1382 { 1383 int ret = pci_default_setup(priv, board, port, idx); 1384 1385 port->port.type = PORT_BRCM_TRUMANAGE; 1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1387 return ret; 1388 } 1389 1390 /* RTS will control by MCR if this bit is 0 */ 1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1393 #define FINTEK_RTS_INVERT BIT(5) 1394 1395 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1396 static int pci_fintek_rs485_config(struct uart_port *port, 1397 struct serial_rs485 *rs485) 1398 { 1399 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1400 u8 setting; 1401 u8 *index = (u8 *) port->private_data; 1402 1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1404 1405 if (!rs485) 1406 rs485 = &port->rs485; 1407 else if (rs485->flags & SER_RS485_ENABLED) 1408 memset(rs485->padding, 0, sizeof(rs485->padding)); 1409 else 1410 memset(rs485, 0, sizeof(*rs485)); 1411 1412 /* F81504/508/512 not support RTS delay before or after send */ 1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1414 1415 if (rs485->flags & SER_RS485_ENABLED) { 1416 /* Enable RTS H/W control mode */ 1417 setting |= FINTEK_RTS_CONTROL_BY_HW; 1418 1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1420 /* RTS driving high on TX */ 1421 setting &= ~FINTEK_RTS_INVERT; 1422 } else { 1423 /* RTS driving low on TX */ 1424 setting |= FINTEK_RTS_INVERT; 1425 } 1426 1427 rs485->delay_rts_after_send = 0; 1428 rs485->delay_rts_before_send = 0; 1429 } else { 1430 /* Disable RTS H/W control mode */ 1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1432 } 1433 1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1435 1436 if (rs485 != &port->rs485) 1437 port->rs485 = *rs485; 1438 1439 return 0; 1440 } 1441 1442 static int pci_fintek_setup(struct serial_private *priv, 1443 const struct pciserial_board *board, 1444 struct uart_8250_port *port, int idx) 1445 { 1446 struct pci_dev *pdev = priv->dev; 1447 u8 *data; 1448 u8 config_base; 1449 u16 iobase; 1450 1451 config_base = 0x40 + 0x08 * idx; 1452 1453 /* Get the io address from configuration space */ 1454 pci_read_config_word(pdev, config_base + 4, &iobase); 1455 1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1457 1458 port->port.iotype = UPIO_PORT; 1459 port->port.iobase = iobase; 1460 port->port.rs485_config = pci_fintek_rs485_config; 1461 1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1463 if (!data) 1464 return -ENOMEM; 1465 1466 /* preserve index in PCI configuration space */ 1467 *data = idx; 1468 port->port.private_data = data; 1469 1470 return 0; 1471 } 1472 1473 static int pci_fintek_init(struct pci_dev *dev) 1474 { 1475 unsigned long iobase; 1476 u32 max_port, i; 1477 resource_size_t bar_data[3]; 1478 u8 config_base; 1479 struct serial_private *priv = pci_get_drvdata(dev); 1480 struct uart_8250_port *port; 1481 1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1485 return -ENODEV; 1486 1487 switch (dev->device) { 1488 case 0x1104: /* 4 ports */ 1489 case 0x1108: /* 8 ports */ 1490 max_port = dev->device & 0xff; 1491 break; 1492 case 0x1112: /* 12 ports */ 1493 max_port = 12; 1494 break; 1495 default: 1496 return -EINVAL; 1497 } 1498 1499 /* Get the io address dispatch from the BIOS */ 1500 bar_data[0] = pci_resource_start(dev, 5); 1501 bar_data[1] = pci_resource_start(dev, 4); 1502 bar_data[2] = pci_resource_start(dev, 3); 1503 1504 for (i = 0; i < max_port; ++i) { 1505 /* UART0 configuration offset start from 0x40 */ 1506 config_base = 0x40 + 0x08 * i; 1507 1508 /* Calculate Real IO Port */ 1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1510 1511 /* Enable UART I/O port */ 1512 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1513 1514 /* Select 128-byte FIFO and 8x FIFO threshold */ 1515 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1516 1517 /* LSB UART */ 1518 pci_write_config_byte(dev, config_base + 0x04, 1519 (u8)(iobase & 0xff)); 1520 1521 /* MSB UART */ 1522 pci_write_config_byte(dev, config_base + 0x05, 1523 (u8)((iobase & 0xff00) >> 8)); 1524 1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1526 1527 if (priv) { 1528 /* re-apply RS232/485 mode when 1529 * pciserial_resume_ports() 1530 */ 1531 port = serial8250_get_port(priv->line[i]); 1532 pci_fintek_rs485_config(&port->port, NULL); 1533 } else { 1534 /* First init without port data 1535 * force init to RS232 Mode 1536 */ 1537 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1538 } 1539 } 1540 1541 return max_port; 1542 } 1543 1544 static int skip_tx_en_setup(struct serial_private *priv, 1545 const struct pciserial_board *board, 1546 struct uart_8250_port *port, int idx) 1547 { 1548 port->port.quirks |= UPQ_NO_TXEN_TEST; 1549 dev_dbg(&priv->dev->dev, 1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1551 priv->dev->vendor, priv->dev->device, 1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1553 1554 return pci_default_setup(priv, board, port, idx); 1555 } 1556 1557 static void kt_handle_break(struct uart_port *p) 1558 { 1559 struct uart_8250_port *up = up_to_u8250p(p); 1560 /* 1561 * On receipt of a BI, serial device in Intel ME (Intel 1562 * management engine) needs to have its fifos cleared for sane 1563 * SOL (Serial Over Lan) output. 1564 */ 1565 serial8250_clear_and_reinit_fifos(up); 1566 } 1567 1568 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1569 { 1570 struct uart_8250_port *up = up_to_u8250p(p); 1571 unsigned int val; 1572 1573 /* 1574 * When the Intel ME (management engine) gets reset its serial 1575 * port registers could return 0 momentarily. Functions like 1576 * serial8250_console_write, read and save the IER, perform 1577 * some operation and then restore it. In order to avoid 1578 * setting IER register inadvertently to 0, if the value read 1579 * is 0, double check with ier value in uart_8250_port and use 1580 * that instead. up->ier should be the same value as what is 1581 * currently configured. 1582 */ 1583 val = inb(p->iobase + offset); 1584 if (offset == UART_IER) { 1585 if (val == 0) 1586 val = up->ier; 1587 } 1588 return val; 1589 } 1590 1591 static int kt_serial_setup(struct serial_private *priv, 1592 const struct pciserial_board *board, 1593 struct uart_8250_port *port, int idx) 1594 { 1595 port->port.flags |= UPF_BUG_THRE; 1596 port->port.serial_in = kt_serial_in; 1597 port->port.handle_break = kt_handle_break; 1598 return skip_tx_en_setup(priv, board, port, idx); 1599 } 1600 1601 static int pci_eg20t_init(struct pci_dev *dev) 1602 { 1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1604 return -ENODEV; 1605 #else 1606 return 0; 1607 #endif 1608 } 1609 1610 static int 1611 pci_wch_ch353_setup(struct serial_private *priv, 1612 const struct pciserial_board *board, 1613 struct uart_8250_port *port, int idx) 1614 { 1615 port->port.flags |= UPF_FIXED_TYPE; 1616 port->port.type = PORT_16550A; 1617 return pci_default_setup(priv, board, port, idx); 1618 } 1619 1620 static int 1621 pci_wch_ch355_setup(struct serial_private *priv, 1622 const struct pciserial_board *board, 1623 struct uart_8250_port *port, int idx) 1624 { 1625 port->port.flags |= UPF_FIXED_TYPE; 1626 port->port.type = PORT_16550A; 1627 return pci_default_setup(priv, board, port, idx); 1628 } 1629 1630 static int 1631 pci_wch_ch38x_setup(struct serial_private *priv, 1632 const struct pciserial_board *board, 1633 struct uart_8250_port *port, int idx) 1634 { 1635 port->port.flags |= UPF_FIXED_TYPE; 1636 port->port.type = PORT_16850; 1637 return pci_default_setup(priv, board, port, idx); 1638 } 1639 1640 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1641 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1642 #define PCI_DEVICE_ID_OCTPRO 0x0001 1643 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1644 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1645 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1646 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1647 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1648 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1649 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1650 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1651 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1652 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1653 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1654 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1655 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1656 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1657 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1658 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1659 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1660 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1661 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1662 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1663 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1664 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1665 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1666 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1667 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1668 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1669 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1670 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1671 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1672 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1673 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1674 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1675 #define PCI_VENDOR_ID_WCH 0x4348 1676 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1677 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1678 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1679 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1680 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1681 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1682 #define PCI_VENDOR_ID_AGESTAR 0x5372 1683 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1684 #define PCI_VENDOR_ID_ASIX 0x9710 1685 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1686 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1687 1688 #define PCIE_VENDOR_ID_WCH 0x1c00 1689 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1690 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1691 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1692 1693 #define PCI_VENDOR_ID_PERICOM 0x12D8 1694 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 1695 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 1696 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 1697 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 1698 1699 #define PCI_VENDOR_ID_ACCESIO 0x494f 1700 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1701 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1702 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1703 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1704 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1705 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1706 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1708 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1710 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1712 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1716 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1717 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1718 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1719 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1720 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1721 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1722 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1728 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1733 1734 1735 1736 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1737 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1738 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1739 1740 /* 1741 * Master list of serial port init/setup/exit quirks. 1742 * This does not describe the general nature of the port. 1743 * (ie, baud base, number and location of ports, etc) 1744 * 1745 * This list is ordered alphabetically by vendor then device. 1746 * Specific entries must come before more generic entries. 1747 */ 1748 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1749 /* 1750 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1751 */ 1752 { 1753 .vendor = PCI_VENDOR_ID_AMCC, 1754 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1755 .subvendor = PCI_ANY_ID, 1756 .subdevice = PCI_ANY_ID, 1757 .setup = addidata_apci7800_setup, 1758 }, 1759 /* 1760 * AFAVLAB cards - these may be called via parport_serial 1761 * It is not clear whether this applies to all products. 1762 */ 1763 { 1764 .vendor = PCI_VENDOR_ID_AFAVLAB, 1765 .device = PCI_ANY_ID, 1766 .subvendor = PCI_ANY_ID, 1767 .subdevice = PCI_ANY_ID, 1768 .setup = afavlab_setup, 1769 }, 1770 /* 1771 * HP Diva 1772 */ 1773 { 1774 .vendor = PCI_VENDOR_ID_HP, 1775 .device = PCI_DEVICE_ID_HP_DIVA, 1776 .subvendor = PCI_ANY_ID, 1777 .subdevice = PCI_ANY_ID, 1778 .init = pci_hp_diva_init, 1779 .setup = pci_hp_diva_setup, 1780 }, 1781 /* 1782 * Intel 1783 */ 1784 { 1785 .vendor = PCI_VENDOR_ID_INTEL, 1786 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1787 .subvendor = 0xe4bf, 1788 .subdevice = PCI_ANY_ID, 1789 .init = pci_inteli960ni_init, 1790 .setup = pci_default_setup, 1791 }, 1792 { 1793 .vendor = PCI_VENDOR_ID_INTEL, 1794 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1795 .subvendor = PCI_ANY_ID, 1796 .subdevice = PCI_ANY_ID, 1797 .setup = skip_tx_en_setup, 1798 }, 1799 { 1800 .vendor = PCI_VENDOR_ID_INTEL, 1801 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1802 .subvendor = PCI_ANY_ID, 1803 .subdevice = PCI_ANY_ID, 1804 .setup = skip_tx_en_setup, 1805 }, 1806 { 1807 .vendor = PCI_VENDOR_ID_INTEL, 1808 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1809 .subvendor = PCI_ANY_ID, 1810 .subdevice = PCI_ANY_ID, 1811 .setup = skip_tx_en_setup, 1812 }, 1813 { 1814 .vendor = PCI_VENDOR_ID_INTEL, 1815 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1816 .subvendor = PCI_ANY_ID, 1817 .subdevice = PCI_ANY_ID, 1818 .setup = ce4100_serial_setup, 1819 }, 1820 { 1821 .vendor = PCI_VENDOR_ID_INTEL, 1822 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1823 .subvendor = PCI_ANY_ID, 1824 .subdevice = PCI_ANY_ID, 1825 .setup = kt_serial_setup, 1826 }, 1827 /* 1828 * ITE 1829 */ 1830 { 1831 .vendor = PCI_VENDOR_ID_ITE, 1832 .device = PCI_DEVICE_ID_ITE_8872, 1833 .subvendor = PCI_ANY_ID, 1834 .subdevice = PCI_ANY_ID, 1835 .init = pci_ite887x_init, 1836 .setup = pci_default_setup, 1837 .exit = pci_ite887x_exit, 1838 }, 1839 /* 1840 * National Instruments 1841 */ 1842 { 1843 .vendor = PCI_VENDOR_ID_NI, 1844 .device = PCI_DEVICE_ID_NI_PCI23216, 1845 .subvendor = PCI_ANY_ID, 1846 .subdevice = PCI_ANY_ID, 1847 .init = pci_ni8420_init, 1848 .setup = pci_default_setup, 1849 .exit = pci_ni8420_exit, 1850 }, 1851 { 1852 .vendor = PCI_VENDOR_ID_NI, 1853 .device = PCI_DEVICE_ID_NI_PCI2328, 1854 .subvendor = PCI_ANY_ID, 1855 .subdevice = PCI_ANY_ID, 1856 .init = pci_ni8420_init, 1857 .setup = pci_default_setup, 1858 .exit = pci_ni8420_exit, 1859 }, 1860 { 1861 .vendor = PCI_VENDOR_ID_NI, 1862 .device = PCI_DEVICE_ID_NI_PCI2324, 1863 .subvendor = PCI_ANY_ID, 1864 .subdevice = PCI_ANY_ID, 1865 .init = pci_ni8420_init, 1866 .setup = pci_default_setup, 1867 .exit = pci_ni8420_exit, 1868 }, 1869 { 1870 .vendor = PCI_VENDOR_ID_NI, 1871 .device = PCI_DEVICE_ID_NI_PCI2322, 1872 .subvendor = PCI_ANY_ID, 1873 .subdevice = PCI_ANY_ID, 1874 .init = pci_ni8420_init, 1875 .setup = pci_default_setup, 1876 .exit = pci_ni8420_exit, 1877 }, 1878 { 1879 .vendor = PCI_VENDOR_ID_NI, 1880 .device = PCI_DEVICE_ID_NI_PCI2324I, 1881 .subvendor = PCI_ANY_ID, 1882 .subdevice = PCI_ANY_ID, 1883 .init = pci_ni8420_init, 1884 .setup = pci_default_setup, 1885 .exit = pci_ni8420_exit, 1886 }, 1887 { 1888 .vendor = PCI_VENDOR_ID_NI, 1889 .device = PCI_DEVICE_ID_NI_PCI2322I, 1890 .subvendor = PCI_ANY_ID, 1891 .subdevice = PCI_ANY_ID, 1892 .init = pci_ni8420_init, 1893 .setup = pci_default_setup, 1894 .exit = pci_ni8420_exit, 1895 }, 1896 { 1897 .vendor = PCI_VENDOR_ID_NI, 1898 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1899 .subvendor = PCI_ANY_ID, 1900 .subdevice = PCI_ANY_ID, 1901 .init = pci_ni8420_init, 1902 .setup = pci_default_setup, 1903 .exit = pci_ni8420_exit, 1904 }, 1905 { 1906 .vendor = PCI_VENDOR_ID_NI, 1907 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 1908 .subvendor = PCI_ANY_ID, 1909 .subdevice = PCI_ANY_ID, 1910 .init = pci_ni8420_init, 1911 .setup = pci_default_setup, 1912 .exit = pci_ni8420_exit, 1913 }, 1914 { 1915 .vendor = PCI_VENDOR_ID_NI, 1916 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 1917 .subvendor = PCI_ANY_ID, 1918 .subdevice = PCI_ANY_ID, 1919 .init = pci_ni8420_init, 1920 .setup = pci_default_setup, 1921 .exit = pci_ni8420_exit, 1922 }, 1923 { 1924 .vendor = PCI_VENDOR_ID_NI, 1925 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 1926 .subvendor = PCI_ANY_ID, 1927 .subdevice = PCI_ANY_ID, 1928 .init = pci_ni8420_init, 1929 .setup = pci_default_setup, 1930 .exit = pci_ni8420_exit, 1931 }, 1932 { 1933 .vendor = PCI_VENDOR_ID_NI, 1934 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 1935 .subvendor = PCI_ANY_ID, 1936 .subdevice = PCI_ANY_ID, 1937 .init = pci_ni8420_init, 1938 .setup = pci_default_setup, 1939 .exit = pci_ni8420_exit, 1940 }, 1941 { 1942 .vendor = PCI_VENDOR_ID_NI, 1943 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 1944 .subvendor = PCI_ANY_ID, 1945 .subdevice = PCI_ANY_ID, 1946 .init = pci_ni8420_init, 1947 .setup = pci_default_setup, 1948 .exit = pci_ni8420_exit, 1949 }, 1950 { 1951 .vendor = PCI_VENDOR_ID_NI, 1952 .device = PCI_ANY_ID, 1953 .subvendor = PCI_ANY_ID, 1954 .subdevice = PCI_ANY_ID, 1955 .init = pci_ni8430_init, 1956 .setup = pci_ni8430_setup, 1957 .exit = pci_ni8430_exit, 1958 }, 1959 /* Quatech */ 1960 { 1961 .vendor = PCI_VENDOR_ID_QUATECH, 1962 .device = PCI_ANY_ID, 1963 .subvendor = PCI_ANY_ID, 1964 .subdevice = PCI_ANY_ID, 1965 .init = pci_quatech_init, 1966 .setup = pci_quatech_setup, 1967 .exit = pci_quatech_exit, 1968 }, 1969 /* 1970 * Panacom 1971 */ 1972 { 1973 .vendor = PCI_VENDOR_ID_PANACOM, 1974 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 1975 .subvendor = PCI_ANY_ID, 1976 .subdevice = PCI_ANY_ID, 1977 .init = pci_plx9050_init, 1978 .setup = pci_default_setup, 1979 .exit = pci_plx9050_exit, 1980 }, 1981 { 1982 .vendor = PCI_VENDOR_ID_PANACOM, 1983 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 1984 .subvendor = PCI_ANY_ID, 1985 .subdevice = PCI_ANY_ID, 1986 .init = pci_plx9050_init, 1987 .setup = pci_default_setup, 1988 .exit = pci_plx9050_exit, 1989 }, 1990 /* 1991 * Pericom (Only 7954 - It have a offset jump for port 4) 1992 */ 1993 { 1994 .vendor = PCI_VENDOR_ID_PERICOM, 1995 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 1996 .subvendor = PCI_ANY_ID, 1997 .subdevice = PCI_ANY_ID, 1998 .setup = pci_pericom_setup, 1999 }, 2000 /* 2001 * PLX 2002 */ 2003 { 2004 .vendor = PCI_VENDOR_ID_PLX, 2005 .device = PCI_DEVICE_ID_PLX_9050, 2006 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2007 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2008 .init = pci_plx9050_init, 2009 .setup = pci_default_setup, 2010 .exit = pci_plx9050_exit, 2011 }, 2012 { 2013 .vendor = PCI_VENDOR_ID_PLX, 2014 .device = PCI_DEVICE_ID_PLX_9050, 2015 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2016 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2017 .init = pci_plx9050_init, 2018 .setup = pci_default_setup, 2019 .exit = pci_plx9050_exit, 2020 }, 2021 { 2022 .vendor = PCI_VENDOR_ID_PLX, 2023 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2024 .subvendor = PCI_VENDOR_ID_PLX, 2025 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2026 .init = pci_plx9050_init, 2027 .setup = pci_default_setup, 2028 .exit = pci_plx9050_exit, 2029 }, 2030 { 2031 .vendor = PCI_VENDOR_ID_ACCESIO, 2032 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2033 .subvendor = PCI_ANY_ID, 2034 .subdevice = PCI_ANY_ID, 2035 .setup = pci_pericom_setup, 2036 }, 2037 { 2038 .vendor = PCI_VENDOR_ID_ACCESIO, 2039 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2040 .subvendor = PCI_ANY_ID, 2041 .subdevice = PCI_ANY_ID, 2042 .setup = pci_pericom_setup, 2043 }, 2044 { 2045 .vendor = PCI_VENDOR_ID_ACCESIO, 2046 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2047 .subvendor = PCI_ANY_ID, 2048 .subdevice = PCI_ANY_ID, 2049 .setup = pci_pericom_setup, 2050 }, 2051 { 2052 .vendor = PCI_VENDOR_ID_ACCESIO, 2053 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2054 .subvendor = PCI_ANY_ID, 2055 .subdevice = PCI_ANY_ID, 2056 .setup = pci_pericom_setup, 2057 }, 2058 { 2059 .vendor = PCI_VENDOR_ID_ACCESIO, 2060 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2061 .subvendor = PCI_ANY_ID, 2062 .subdevice = PCI_ANY_ID, 2063 .setup = pci_pericom_setup, 2064 }, 2065 { 2066 .vendor = PCI_VENDOR_ID_ACCESIO, 2067 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2068 .subvendor = PCI_ANY_ID, 2069 .subdevice = PCI_ANY_ID, 2070 .setup = pci_pericom_setup, 2071 }, 2072 { 2073 .vendor = PCI_VENDOR_ID_ACCESIO, 2074 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2075 .subvendor = PCI_ANY_ID, 2076 .subdevice = PCI_ANY_ID, 2077 .setup = pci_pericom_setup, 2078 }, 2079 { 2080 .vendor = PCI_VENDOR_ID_ACCESIO, 2081 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2082 .subvendor = PCI_ANY_ID, 2083 .subdevice = PCI_ANY_ID, 2084 .setup = pci_pericom_setup, 2085 }, 2086 { 2087 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2088 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2089 .subvendor = PCI_ANY_ID, 2090 .subdevice = PCI_ANY_ID, 2091 .setup = pci_pericom_setup, 2092 }, 2093 { 2094 .vendor = PCI_VENDOR_ID_ACCESIO, 2095 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2096 .subvendor = PCI_ANY_ID, 2097 .subdevice = PCI_ANY_ID, 2098 .setup = pci_pericom_setup, 2099 }, 2100 { 2101 .vendor = PCI_VENDOR_ID_ACCESIO, 2102 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2103 .subvendor = PCI_ANY_ID, 2104 .subdevice = PCI_ANY_ID, 2105 .setup = pci_pericom_setup, 2106 }, 2107 { 2108 .vendor = PCI_VENDOR_ID_ACCESIO, 2109 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2110 .subvendor = PCI_ANY_ID, 2111 .subdevice = PCI_ANY_ID, 2112 .setup = pci_pericom_setup, 2113 }, 2114 { 2115 .vendor = PCI_VENDOR_ID_ACCESIO, 2116 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2117 .subvendor = PCI_ANY_ID, 2118 .subdevice = PCI_ANY_ID, 2119 .setup = pci_pericom_setup, 2120 }, 2121 { 2122 .vendor = PCI_VENDOR_ID_ACCESIO, 2123 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2124 .subvendor = PCI_ANY_ID, 2125 .subdevice = PCI_ANY_ID, 2126 .setup = pci_pericom_setup, 2127 }, 2128 { 2129 .vendor = PCI_VENDOR_ID_ACCESIO, 2130 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2131 .subvendor = PCI_ANY_ID, 2132 .subdevice = PCI_ANY_ID, 2133 .setup = pci_pericom_setup, 2134 }, 2135 /* 2136 * SBS Technologies, Inc., PMC-OCTALPRO 232 2137 */ 2138 { 2139 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2140 .device = PCI_DEVICE_ID_OCTPRO, 2141 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2142 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2143 .init = sbs_init, 2144 .setup = sbs_setup, 2145 .exit = sbs_exit, 2146 }, 2147 /* 2148 * SBS Technologies, Inc., PMC-OCTALPRO 422 2149 */ 2150 { 2151 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2152 .device = PCI_DEVICE_ID_OCTPRO, 2153 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2154 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2155 .init = sbs_init, 2156 .setup = sbs_setup, 2157 .exit = sbs_exit, 2158 }, 2159 /* 2160 * SBS Technologies, Inc., P-Octal 232 2161 */ 2162 { 2163 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2164 .device = PCI_DEVICE_ID_OCTPRO, 2165 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2166 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2167 .init = sbs_init, 2168 .setup = sbs_setup, 2169 .exit = sbs_exit, 2170 }, 2171 /* 2172 * SBS Technologies, Inc., P-Octal 422 2173 */ 2174 { 2175 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2176 .device = PCI_DEVICE_ID_OCTPRO, 2177 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2178 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2179 .init = sbs_init, 2180 .setup = sbs_setup, 2181 .exit = sbs_exit, 2182 }, 2183 /* 2184 * SIIG cards - these may be called via parport_serial 2185 */ 2186 { 2187 .vendor = PCI_VENDOR_ID_SIIG, 2188 .device = PCI_ANY_ID, 2189 .subvendor = PCI_ANY_ID, 2190 .subdevice = PCI_ANY_ID, 2191 .init = pci_siig_init, 2192 .setup = pci_siig_setup, 2193 }, 2194 /* 2195 * Titan cards 2196 */ 2197 { 2198 .vendor = PCI_VENDOR_ID_TITAN, 2199 .device = PCI_DEVICE_ID_TITAN_400L, 2200 .subvendor = PCI_ANY_ID, 2201 .subdevice = PCI_ANY_ID, 2202 .setup = titan_400l_800l_setup, 2203 }, 2204 { 2205 .vendor = PCI_VENDOR_ID_TITAN, 2206 .device = PCI_DEVICE_ID_TITAN_800L, 2207 .subvendor = PCI_ANY_ID, 2208 .subdevice = PCI_ANY_ID, 2209 .setup = titan_400l_800l_setup, 2210 }, 2211 /* 2212 * Timedia cards 2213 */ 2214 { 2215 .vendor = PCI_VENDOR_ID_TIMEDIA, 2216 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2217 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2218 .subdevice = PCI_ANY_ID, 2219 .probe = pci_timedia_probe, 2220 .init = pci_timedia_init, 2221 .setup = pci_timedia_setup, 2222 }, 2223 { 2224 .vendor = PCI_VENDOR_ID_TIMEDIA, 2225 .device = PCI_ANY_ID, 2226 .subvendor = PCI_ANY_ID, 2227 .subdevice = PCI_ANY_ID, 2228 .setup = pci_timedia_setup, 2229 }, 2230 /* 2231 * SUNIX (Timedia) cards 2232 * Do not "probe" for these cards as there is at least one combination 2233 * card that should be handled by parport_pc that doesn't match the 2234 * rule in pci_timedia_probe. 2235 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2236 * There are some boards with part number SER5037AL that report 2237 * subdevice ID 0x0002. 2238 */ 2239 { 2240 .vendor = PCI_VENDOR_ID_SUNIX, 2241 .device = PCI_DEVICE_ID_SUNIX_1999, 2242 .subvendor = PCI_VENDOR_ID_SUNIX, 2243 .subdevice = PCI_ANY_ID, 2244 .init = pci_timedia_init, 2245 .setup = pci_timedia_setup, 2246 }, 2247 /* 2248 * Xircom cards 2249 */ 2250 { 2251 .vendor = PCI_VENDOR_ID_XIRCOM, 2252 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2253 .subvendor = PCI_ANY_ID, 2254 .subdevice = PCI_ANY_ID, 2255 .init = pci_xircom_init, 2256 .setup = pci_default_setup, 2257 }, 2258 /* 2259 * Netmos cards - these may be called via parport_serial 2260 */ 2261 { 2262 .vendor = PCI_VENDOR_ID_NETMOS, 2263 .device = PCI_ANY_ID, 2264 .subvendor = PCI_ANY_ID, 2265 .subdevice = PCI_ANY_ID, 2266 .init = pci_netmos_init, 2267 .setup = pci_netmos_9900_setup, 2268 }, 2269 /* 2270 * EndRun Technologies 2271 */ 2272 { 2273 .vendor = PCI_VENDOR_ID_ENDRUN, 2274 .device = PCI_ANY_ID, 2275 .subvendor = PCI_ANY_ID, 2276 .subdevice = PCI_ANY_ID, 2277 .init = pci_endrun_init, 2278 .setup = pci_default_setup, 2279 }, 2280 /* 2281 * For Oxford Semiconductor Tornado based devices 2282 */ 2283 { 2284 .vendor = PCI_VENDOR_ID_OXSEMI, 2285 .device = PCI_ANY_ID, 2286 .subvendor = PCI_ANY_ID, 2287 .subdevice = PCI_ANY_ID, 2288 .init = pci_oxsemi_tornado_init, 2289 .setup = pci_default_setup, 2290 }, 2291 { 2292 .vendor = PCI_VENDOR_ID_MAINPINE, 2293 .device = PCI_ANY_ID, 2294 .subvendor = PCI_ANY_ID, 2295 .subdevice = PCI_ANY_ID, 2296 .init = pci_oxsemi_tornado_init, 2297 .setup = pci_default_setup, 2298 }, 2299 { 2300 .vendor = PCI_VENDOR_ID_DIGI, 2301 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2302 .subvendor = PCI_SUBVENDOR_ID_IBM, 2303 .subdevice = PCI_ANY_ID, 2304 .init = pci_oxsemi_tornado_init, 2305 .setup = pci_default_setup, 2306 }, 2307 { 2308 .vendor = PCI_VENDOR_ID_INTEL, 2309 .device = 0x8811, 2310 .subvendor = PCI_ANY_ID, 2311 .subdevice = PCI_ANY_ID, 2312 .init = pci_eg20t_init, 2313 .setup = pci_default_setup, 2314 }, 2315 { 2316 .vendor = PCI_VENDOR_ID_INTEL, 2317 .device = 0x8812, 2318 .subvendor = PCI_ANY_ID, 2319 .subdevice = PCI_ANY_ID, 2320 .init = pci_eg20t_init, 2321 .setup = pci_default_setup, 2322 }, 2323 { 2324 .vendor = PCI_VENDOR_ID_INTEL, 2325 .device = 0x8813, 2326 .subvendor = PCI_ANY_ID, 2327 .subdevice = PCI_ANY_ID, 2328 .init = pci_eg20t_init, 2329 .setup = pci_default_setup, 2330 }, 2331 { 2332 .vendor = PCI_VENDOR_ID_INTEL, 2333 .device = 0x8814, 2334 .subvendor = PCI_ANY_ID, 2335 .subdevice = PCI_ANY_ID, 2336 .init = pci_eg20t_init, 2337 .setup = pci_default_setup, 2338 }, 2339 { 2340 .vendor = 0x10DB, 2341 .device = 0x8027, 2342 .subvendor = PCI_ANY_ID, 2343 .subdevice = PCI_ANY_ID, 2344 .init = pci_eg20t_init, 2345 .setup = pci_default_setup, 2346 }, 2347 { 2348 .vendor = 0x10DB, 2349 .device = 0x8028, 2350 .subvendor = PCI_ANY_ID, 2351 .subdevice = PCI_ANY_ID, 2352 .init = pci_eg20t_init, 2353 .setup = pci_default_setup, 2354 }, 2355 { 2356 .vendor = 0x10DB, 2357 .device = 0x8029, 2358 .subvendor = PCI_ANY_ID, 2359 .subdevice = PCI_ANY_ID, 2360 .init = pci_eg20t_init, 2361 .setup = pci_default_setup, 2362 }, 2363 { 2364 .vendor = 0x10DB, 2365 .device = 0x800C, 2366 .subvendor = PCI_ANY_ID, 2367 .subdevice = PCI_ANY_ID, 2368 .init = pci_eg20t_init, 2369 .setup = pci_default_setup, 2370 }, 2371 { 2372 .vendor = 0x10DB, 2373 .device = 0x800D, 2374 .subvendor = PCI_ANY_ID, 2375 .subdevice = PCI_ANY_ID, 2376 .init = pci_eg20t_init, 2377 .setup = pci_default_setup, 2378 }, 2379 /* 2380 * Cronyx Omega PCI (PLX-chip based) 2381 */ 2382 { 2383 .vendor = PCI_VENDOR_ID_PLX, 2384 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2385 .subvendor = PCI_ANY_ID, 2386 .subdevice = PCI_ANY_ID, 2387 .setup = pci_omegapci_setup, 2388 }, 2389 /* WCH CH353 1S1P card (16550 clone) */ 2390 { 2391 .vendor = PCI_VENDOR_ID_WCH, 2392 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2393 .subvendor = PCI_ANY_ID, 2394 .subdevice = PCI_ANY_ID, 2395 .setup = pci_wch_ch353_setup, 2396 }, 2397 /* WCH CH353 2S1P card (16550 clone) */ 2398 { 2399 .vendor = PCI_VENDOR_ID_WCH, 2400 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2401 .subvendor = PCI_ANY_ID, 2402 .subdevice = PCI_ANY_ID, 2403 .setup = pci_wch_ch353_setup, 2404 }, 2405 /* WCH CH353 4S card (16550 clone) */ 2406 { 2407 .vendor = PCI_VENDOR_ID_WCH, 2408 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2409 .subvendor = PCI_ANY_ID, 2410 .subdevice = PCI_ANY_ID, 2411 .setup = pci_wch_ch353_setup, 2412 }, 2413 /* WCH CH353 2S1PF card (16550 clone) */ 2414 { 2415 .vendor = PCI_VENDOR_ID_WCH, 2416 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2417 .subvendor = PCI_ANY_ID, 2418 .subdevice = PCI_ANY_ID, 2419 .setup = pci_wch_ch353_setup, 2420 }, 2421 /* WCH CH352 2S card (16550 clone) */ 2422 { 2423 .vendor = PCI_VENDOR_ID_WCH, 2424 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2425 .subvendor = PCI_ANY_ID, 2426 .subdevice = PCI_ANY_ID, 2427 .setup = pci_wch_ch353_setup, 2428 }, 2429 /* WCH CH355 4S card (16550 clone) */ 2430 { 2431 .vendor = PCI_VENDOR_ID_WCH, 2432 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2433 .subvendor = PCI_ANY_ID, 2434 .subdevice = PCI_ANY_ID, 2435 .setup = pci_wch_ch355_setup, 2436 }, 2437 /* WCH CH382 2S card (16850 clone) */ 2438 { 2439 .vendor = PCIE_VENDOR_ID_WCH, 2440 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2441 .subvendor = PCI_ANY_ID, 2442 .subdevice = PCI_ANY_ID, 2443 .setup = pci_wch_ch38x_setup, 2444 }, 2445 /* WCH CH382 2S1P card (16850 clone) */ 2446 { 2447 .vendor = PCIE_VENDOR_ID_WCH, 2448 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2449 .subvendor = PCI_ANY_ID, 2450 .subdevice = PCI_ANY_ID, 2451 .setup = pci_wch_ch38x_setup, 2452 }, 2453 /* WCH CH384 4S card (16850 clone) */ 2454 { 2455 .vendor = PCIE_VENDOR_ID_WCH, 2456 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2457 .subvendor = PCI_ANY_ID, 2458 .subdevice = PCI_ANY_ID, 2459 .setup = pci_wch_ch38x_setup, 2460 }, 2461 /* 2462 * ASIX devices with FIFO bug 2463 */ 2464 { 2465 .vendor = PCI_VENDOR_ID_ASIX, 2466 .device = PCI_ANY_ID, 2467 .subvendor = PCI_ANY_ID, 2468 .subdevice = PCI_ANY_ID, 2469 .setup = pci_asix_setup, 2470 }, 2471 /* 2472 * Broadcom TruManage (NetXtreme) 2473 */ 2474 { 2475 .vendor = PCI_VENDOR_ID_BROADCOM, 2476 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2477 .subvendor = PCI_ANY_ID, 2478 .subdevice = PCI_ANY_ID, 2479 .setup = pci_brcm_trumanage_setup, 2480 }, 2481 { 2482 .vendor = 0x1c29, 2483 .device = 0x1104, 2484 .subvendor = PCI_ANY_ID, 2485 .subdevice = PCI_ANY_ID, 2486 .setup = pci_fintek_setup, 2487 .init = pci_fintek_init, 2488 }, 2489 { 2490 .vendor = 0x1c29, 2491 .device = 0x1108, 2492 .subvendor = PCI_ANY_ID, 2493 .subdevice = PCI_ANY_ID, 2494 .setup = pci_fintek_setup, 2495 .init = pci_fintek_init, 2496 }, 2497 { 2498 .vendor = 0x1c29, 2499 .device = 0x1112, 2500 .subvendor = PCI_ANY_ID, 2501 .subdevice = PCI_ANY_ID, 2502 .setup = pci_fintek_setup, 2503 .init = pci_fintek_init, 2504 }, 2505 2506 /* 2507 * Default "match everything" terminator entry 2508 */ 2509 { 2510 .vendor = PCI_ANY_ID, 2511 .device = PCI_ANY_ID, 2512 .subvendor = PCI_ANY_ID, 2513 .subdevice = PCI_ANY_ID, 2514 .setup = pci_default_setup, 2515 } 2516 }; 2517 2518 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2519 { 2520 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2521 } 2522 2523 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2524 { 2525 struct pci_serial_quirk *quirk; 2526 2527 for (quirk = pci_serial_quirks; ; quirk++) 2528 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2529 quirk_id_matches(quirk->device, dev->device) && 2530 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2531 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2532 break; 2533 return quirk; 2534 } 2535 2536 static inline int get_pci_irq(struct pci_dev *dev, 2537 const struct pciserial_board *board) 2538 { 2539 if (board->flags & FL_NOIRQ) 2540 return 0; 2541 else 2542 return dev->irq; 2543 } 2544 2545 /* 2546 * This is the configuration table for all of the PCI serial boards 2547 * which we support. It is directly indexed by the pci_board_num_t enum 2548 * value, which is encoded in the pci_device_id PCI probe table's 2549 * driver_data member. 2550 * 2551 * The makeup of these names are: 2552 * pbn_bn{_bt}_n_baud{_offsetinhex} 2553 * 2554 * bn = PCI BAR number 2555 * bt = Index using PCI BARs 2556 * n = number of serial ports 2557 * baud = baud rate 2558 * offsetinhex = offset for each sequential port (in hex) 2559 * 2560 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2561 * 2562 * Please note: in theory if n = 1, _bt infix should make no difference. 2563 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2564 */ 2565 enum pci_board_num_t { 2566 pbn_default = 0, 2567 2568 pbn_b0_1_115200, 2569 pbn_b0_2_115200, 2570 pbn_b0_4_115200, 2571 pbn_b0_5_115200, 2572 pbn_b0_8_115200, 2573 2574 pbn_b0_1_921600, 2575 pbn_b0_2_921600, 2576 pbn_b0_4_921600, 2577 2578 pbn_b0_2_1130000, 2579 2580 pbn_b0_4_1152000, 2581 2582 pbn_b0_4_1250000, 2583 2584 pbn_b0_2_1843200, 2585 pbn_b0_4_1843200, 2586 2587 pbn_b0_1_4000000, 2588 2589 pbn_b0_bt_1_115200, 2590 pbn_b0_bt_2_115200, 2591 pbn_b0_bt_4_115200, 2592 pbn_b0_bt_8_115200, 2593 2594 pbn_b0_bt_1_460800, 2595 pbn_b0_bt_2_460800, 2596 pbn_b0_bt_4_460800, 2597 2598 pbn_b0_bt_1_921600, 2599 pbn_b0_bt_2_921600, 2600 pbn_b0_bt_4_921600, 2601 pbn_b0_bt_8_921600, 2602 2603 pbn_b1_1_115200, 2604 pbn_b1_2_115200, 2605 pbn_b1_4_115200, 2606 pbn_b1_8_115200, 2607 pbn_b1_16_115200, 2608 2609 pbn_b1_1_921600, 2610 pbn_b1_2_921600, 2611 pbn_b1_4_921600, 2612 pbn_b1_8_921600, 2613 2614 pbn_b1_2_1250000, 2615 2616 pbn_b1_bt_1_115200, 2617 pbn_b1_bt_2_115200, 2618 pbn_b1_bt_4_115200, 2619 2620 pbn_b1_bt_2_921600, 2621 2622 pbn_b1_1_1382400, 2623 pbn_b1_2_1382400, 2624 pbn_b1_4_1382400, 2625 pbn_b1_8_1382400, 2626 2627 pbn_b2_1_115200, 2628 pbn_b2_2_115200, 2629 pbn_b2_4_115200, 2630 pbn_b2_8_115200, 2631 2632 pbn_b2_1_460800, 2633 pbn_b2_4_460800, 2634 pbn_b2_8_460800, 2635 pbn_b2_16_460800, 2636 2637 pbn_b2_1_921600, 2638 pbn_b2_4_921600, 2639 pbn_b2_8_921600, 2640 2641 pbn_b2_8_1152000, 2642 2643 pbn_b2_bt_1_115200, 2644 pbn_b2_bt_2_115200, 2645 pbn_b2_bt_4_115200, 2646 2647 pbn_b2_bt_2_921600, 2648 pbn_b2_bt_4_921600, 2649 2650 pbn_b3_2_115200, 2651 pbn_b3_4_115200, 2652 pbn_b3_8_115200, 2653 2654 pbn_b4_bt_2_921600, 2655 pbn_b4_bt_4_921600, 2656 pbn_b4_bt_8_921600, 2657 2658 /* 2659 * Board-specific versions. 2660 */ 2661 pbn_panacom, 2662 pbn_panacom2, 2663 pbn_panacom4, 2664 pbn_plx_romulus, 2665 pbn_endrun_2_4000000, 2666 pbn_oxsemi, 2667 pbn_oxsemi_1_4000000, 2668 pbn_oxsemi_2_4000000, 2669 pbn_oxsemi_4_4000000, 2670 pbn_oxsemi_8_4000000, 2671 pbn_intel_i960, 2672 pbn_sgi_ioc3, 2673 pbn_computone_4, 2674 pbn_computone_6, 2675 pbn_computone_8, 2676 pbn_sbsxrsio, 2677 pbn_pasemi_1682M, 2678 pbn_ni8430_2, 2679 pbn_ni8430_4, 2680 pbn_ni8430_8, 2681 pbn_ni8430_16, 2682 pbn_ADDIDATA_PCIe_1_3906250, 2683 pbn_ADDIDATA_PCIe_2_3906250, 2684 pbn_ADDIDATA_PCIe_4_3906250, 2685 pbn_ADDIDATA_PCIe_8_3906250, 2686 pbn_ce4100_1_115200, 2687 pbn_omegapci, 2688 pbn_NETMOS9900_2s_115200, 2689 pbn_brcm_trumanage, 2690 pbn_fintek_4, 2691 pbn_fintek_8, 2692 pbn_fintek_12, 2693 pbn_wch382_2, 2694 pbn_wch384_4, 2695 pbn_pericom_PI7C9X7951, 2696 pbn_pericom_PI7C9X7952, 2697 pbn_pericom_PI7C9X7954, 2698 pbn_pericom_PI7C9X7958, 2699 }; 2700 2701 /* 2702 * uart_offset - the space between channels 2703 * reg_shift - describes how the UART registers are mapped 2704 * to PCI memory by the card. 2705 * For example IER register on SBS, Inc. PMC-OctPro is located at 2706 * offset 0x10 from the UART base, while UART_IER is defined as 1 2707 * in include/linux/serial_reg.h, 2708 * see first lines of serial_in() and serial_out() in 8250.c 2709 */ 2710 2711 static struct pciserial_board pci_boards[] = { 2712 [pbn_default] = { 2713 .flags = FL_BASE0, 2714 .num_ports = 1, 2715 .base_baud = 115200, 2716 .uart_offset = 8, 2717 }, 2718 [pbn_b0_1_115200] = { 2719 .flags = FL_BASE0, 2720 .num_ports = 1, 2721 .base_baud = 115200, 2722 .uart_offset = 8, 2723 }, 2724 [pbn_b0_2_115200] = { 2725 .flags = FL_BASE0, 2726 .num_ports = 2, 2727 .base_baud = 115200, 2728 .uart_offset = 8, 2729 }, 2730 [pbn_b0_4_115200] = { 2731 .flags = FL_BASE0, 2732 .num_ports = 4, 2733 .base_baud = 115200, 2734 .uart_offset = 8, 2735 }, 2736 [pbn_b0_5_115200] = { 2737 .flags = FL_BASE0, 2738 .num_ports = 5, 2739 .base_baud = 115200, 2740 .uart_offset = 8, 2741 }, 2742 [pbn_b0_8_115200] = { 2743 .flags = FL_BASE0, 2744 .num_ports = 8, 2745 .base_baud = 115200, 2746 .uart_offset = 8, 2747 }, 2748 [pbn_b0_1_921600] = { 2749 .flags = FL_BASE0, 2750 .num_ports = 1, 2751 .base_baud = 921600, 2752 .uart_offset = 8, 2753 }, 2754 [pbn_b0_2_921600] = { 2755 .flags = FL_BASE0, 2756 .num_ports = 2, 2757 .base_baud = 921600, 2758 .uart_offset = 8, 2759 }, 2760 [pbn_b0_4_921600] = { 2761 .flags = FL_BASE0, 2762 .num_ports = 4, 2763 .base_baud = 921600, 2764 .uart_offset = 8, 2765 }, 2766 2767 [pbn_b0_2_1130000] = { 2768 .flags = FL_BASE0, 2769 .num_ports = 2, 2770 .base_baud = 1130000, 2771 .uart_offset = 8, 2772 }, 2773 2774 [pbn_b0_4_1152000] = { 2775 .flags = FL_BASE0, 2776 .num_ports = 4, 2777 .base_baud = 1152000, 2778 .uart_offset = 8, 2779 }, 2780 2781 [pbn_b0_4_1250000] = { 2782 .flags = FL_BASE0, 2783 .num_ports = 4, 2784 .base_baud = 1250000, 2785 .uart_offset = 8, 2786 }, 2787 2788 [pbn_b0_2_1843200] = { 2789 .flags = FL_BASE0, 2790 .num_ports = 2, 2791 .base_baud = 1843200, 2792 .uart_offset = 8, 2793 }, 2794 [pbn_b0_4_1843200] = { 2795 .flags = FL_BASE0, 2796 .num_ports = 4, 2797 .base_baud = 1843200, 2798 .uart_offset = 8, 2799 }, 2800 2801 [pbn_b0_1_4000000] = { 2802 .flags = FL_BASE0, 2803 .num_ports = 1, 2804 .base_baud = 4000000, 2805 .uart_offset = 8, 2806 }, 2807 2808 [pbn_b0_bt_1_115200] = { 2809 .flags = FL_BASE0|FL_BASE_BARS, 2810 .num_ports = 1, 2811 .base_baud = 115200, 2812 .uart_offset = 8, 2813 }, 2814 [pbn_b0_bt_2_115200] = { 2815 .flags = FL_BASE0|FL_BASE_BARS, 2816 .num_ports = 2, 2817 .base_baud = 115200, 2818 .uart_offset = 8, 2819 }, 2820 [pbn_b0_bt_4_115200] = { 2821 .flags = FL_BASE0|FL_BASE_BARS, 2822 .num_ports = 4, 2823 .base_baud = 115200, 2824 .uart_offset = 8, 2825 }, 2826 [pbn_b0_bt_8_115200] = { 2827 .flags = FL_BASE0|FL_BASE_BARS, 2828 .num_ports = 8, 2829 .base_baud = 115200, 2830 .uart_offset = 8, 2831 }, 2832 2833 [pbn_b0_bt_1_460800] = { 2834 .flags = FL_BASE0|FL_BASE_BARS, 2835 .num_ports = 1, 2836 .base_baud = 460800, 2837 .uart_offset = 8, 2838 }, 2839 [pbn_b0_bt_2_460800] = { 2840 .flags = FL_BASE0|FL_BASE_BARS, 2841 .num_ports = 2, 2842 .base_baud = 460800, 2843 .uart_offset = 8, 2844 }, 2845 [pbn_b0_bt_4_460800] = { 2846 .flags = FL_BASE0|FL_BASE_BARS, 2847 .num_ports = 4, 2848 .base_baud = 460800, 2849 .uart_offset = 8, 2850 }, 2851 2852 [pbn_b0_bt_1_921600] = { 2853 .flags = FL_BASE0|FL_BASE_BARS, 2854 .num_ports = 1, 2855 .base_baud = 921600, 2856 .uart_offset = 8, 2857 }, 2858 [pbn_b0_bt_2_921600] = { 2859 .flags = FL_BASE0|FL_BASE_BARS, 2860 .num_ports = 2, 2861 .base_baud = 921600, 2862 .uart_offset = 8, 2863 }, 2864 [pbn_b0_bt_4_921600] = { 2865 .flags = FL_BASE0|FL_BASE_BARS, 2866 .num_ports = 4, 2867 .base_baud = 921600, 2868 .uart_offset = 8, 2869 }, 2870 [pbn_b0_bt_8_921600] = { 2871 .flags = FL_BASE0|FL_BASE_BARS, 2872 .num_ports = 8, 2873 .base_baud = 921600, 2874 .uart_offset = 8, 2875 }, 2876 2877 [pbn_b1_1_115200] = { 2878 .flags = FL_BASE1, 2879 .num_ports = 1, 2880 .base_baud = 115200, 2881 .uart_offset = 8, 2882 }, 2883 [pbn_b1_2_115200] = { 2884 .flags = FL_BASE1, 2885 .num_ports = 2, 2886 .base_baud = 115200, 2887 .uart_offset = 8, 2888 }, 2889 [pbn_b1_4_115200] = { 2890 .flags = FL_BASE1, 2891 .num_ports = 4, 2892 .base_baud = 115200, 2893 .uart_offset = 8, 2894 }, 2895 [pbn_b1_8_115200] = { 2896 .flags = FL_BASE1, 2897 .num_ports = 8, 2898 .base_baud = 115200, 2899 .uart_offset = 8, 2900 }, 2901 [pbn_b1_16_115200] = { 2902 .flags = FL_BASE1, 2903 .num_ports = 16, 2904 .base_baud = 115200, 2905 .uart_offset = 8, 2906 }, 2907 2908 [pbn_b1_1_921600] = { 2909 .flags = FL_BASE1, 2910 .num_ports = 1, 2911 .base_baud = 921600, 2912 .uart_offset = 8, 2913 }, 2914 [pbn_b1_2_921600] = { 2915 .flags = FL_BASE1, 2916 .num_ports = 2, 2917 .base_baud = 921600, 2918 .uart_offset = 8, 2919 }, 2920 [pbn_b1_4_921600] = { 2921 .flags = FL_BASE1, 2922 .num_ports = 4, 2923 .base_baud = 921600, 2924 .uart_offset = 8, 2925 }, 2926 [pbn_b1_8_921600] = { 2927 .flags = FL_BASE1, 2928 .num_ports = 8, 2929 .base_baud = 921600, 2930 .uart_offset = 8, 2931 }, 2932 [pbn_b1_2_1250000] = { 2933 .flags = FL_BASE1, 2934 .num_ports = 2, 2935 .base_baud = 1250000, 2936 .uart_offset = 8, 2937 }, 2938 2939 [pbn_b1_bt_1_115200] = { 2940 .flags = FL_BASE1|FL_BASE_BARS, 2941 .num_ports = 1, 2942 .base_baud = 115200, 2943 .uart_offset = 8, 2944 }, 2945 [pbn_b1_bt_2_115200] = { 2946 .flags = FL_BASE1|FL_BASE_BARS, 2947 .num_ports = 2, 2948 .base_baud = 115200, 2949 .uart_offset = 8, 2950 }, 2951 [pbn_b1_bt_4_115200] = { 2952 .flags = FL_BASE1|FL_BASE_BARS, 2953 .num_ports = 4, 2954 .base_baud = 115200, 2955 .uart_offset = 8, 2956 }, 2957 2958 [pbn_b1_bt_2_921600] = { 2959 .flags = FL_BASE1|FL_BASE_BARS, 2960 .num_ports = 2, 2961 .base_baud = 921600, 2962 .uart_offset = 8, 2963 }, 2964 2965 [pbn_b1_1_1382400] = { 2966 .flags = FL_BASE1, 2967 .num_ports = 1, 2968 .base_baud = 1382400, 2969 .uart_offset = 8, 2970 }, 2971 [pbn_b1_2_1382400] = { 2972 .flags = FL_BASE1, 2973 .num_ports = 2, 2974 .base_baud = 1382400, 2975 .uart_offset = 8, 2976 }, 2977 [pbn_b1_4_1382400] = { 2978 .flags = FL_BASE1, 2979 .num_ports = 4, 2980 .base_baud = 1382400, 2981 .uart_offset = 8, 2982 }, 2983 [pbn_b1_8_1382400] = { 2984 .flags = FL_BASE1, 2985 .num_ports = 8, 2986 .base_baud = 1382400, 2987 .uart_offset = 8, 2988 }, 2989 2990 [pbn_b2_1_115200] = { 2991 .flags = FL_BASE2, 2992 .num_ports = 1, 2993 .base_baud = 115200, 2994 .uart_offset = 8, 2995 }, 2996 [pbn_b2_2_115200] = { 2997 .flags = FL_BASE2, 2998 .num_ports = 2, 2999 .base_baud = 115200, 3000 .uart_offset = 8, 3001 }, 3002 [pbn_b2_4_115200] = { 3003 .flags = FL_BASE2, 3004 .num_ports = 4, 3005 .base_baud = 115200, 3006 .uart_offset = 8, 3007 }, 3008 [pbn_b2_8_115200] = { 3009 .flags = FL_BASE2, 3010 .num_ports = 8, 3011 .base_baud = 115200, 3012 .uart_offset = 8, 3013 }, 3014 3015 [pbn_b2_1_460800] = { 3016 .flags = FL_BASE2, 3017 .num_ports = 1, 3018 .base_baud = 460800, 3019 .uart_offset = 8, 3020 }, 3021 [pbn_b2_4_460800] = { 3022 .flags = FL_BASE2, 3023 .num_ports = 4, 3024 .base_baud = 460800, 3025 .uart_offset = 8, 3026 }, 3027 [pbn_b2_8_460800] = { 3028 .flags = FL_BASE2, 3029 .num_ports = 8, 3030 .base_baud = 460800, 3031 .uart_offset = 8, 3032 }, 3033 [pbn_b2_16_460800] = { 3034 .flags = FL_BASE2, 3035 .num_ports = 16, 3036 .base_baud = 460800, 3037 .uart_offset = 8, 3038 }, 3039 3040 [pbn_b2_1_921600] = { 3041 .flags = FL_BASE2, 3042 .num_ports = 1, 3043 .base_baud = 921600, 3044 .uart_offset = 8, 3045 }, 3046 [pbn_b2_4_921600] = { 3047 .flags = FL_BASE2, 3048 .num_ports = 4, 3049 .base_baud = 921600, 3050 .uart_offset = 8, 3051 }, 3052 [pbn_b2_8_921600] = { 3053 .flags = FL_BASE2, 3054 .num_ports = 8, 3055 .base_baud = 921600, 3056 .uart_offset = 8, 3057 }, 3058 3059 [pbn_b2_8_1152000] = { 3060 .flags = FL_BASE2, 3061 .num_ports = 8, 3062 .base_baud = 1152000, 3063 .uart_offset = 8, 3064 }, 3065 3066 [pbn_b2_bt_1_115200] = { 3067 .flags = FL_BASE2|FL_BASE_BARS, 3068 .num_ports = 1, 3069 .base_baud = 115200, 3070 .uart_offset = 8, 3071 }, 3072 [pbn_b2_bt_2_115200] = { 3073 .flags = FL_BASE2|FL_BASE_BARS, 3074 .num_ports = 2, 3075 .base_baud = 115200, 3076 .uart_offset = 8, 3077 }, 3078 [pbn_b2_bt_4_115200] = { 3079 .flags = FL_BASE2|FL_BASE_BARS, 3080 .num_ports = 4, 3081 .base_baud = 115200, 3082 .uart_offset = 8, 3083 }, 3084 3085 [pbn_b2_bt_2_921600] = { 3086 .flags = FL_BASE2|FL_BASE_BARS, 3087 .num_ports = 2, 3088 .base_baud = 921600, 3089 .uart_offset = 8, 3090 }, 3091 [pbn_b2_bt_4_921600] = { 3092 .flags = FL_BASE2|FL_BASE_BARS, 3093 .num_ports = 4, 3094 .base_baud = 921600, 3095 .uart_offset = 8, 3096 }, 3097 3098 [pbn_b3_2_115200] = { 3099 .flags = FL_BASE3, 3100 .num_ports = 2, 3101 .base_baud = 115200, 3102 .uart_offset = 8, 3103 }, 3104 [pbn_b3_4_115200] = { 3105 .flags = FL_BASE3, 3106 .num_ports = 4, 3107 .base_baud = 115200, 3108 .uart_offset = 8, 3109 }, 3110 [pbn_b3_8_115200] = { 3111 .flags = FL_BASE3, 3112 .num_ports = 8, 3113 .base_baud = 115200, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b4_bt_2_921600] = { 3118 .flags = FL_BASE4, 3119 .num_ports = 2, 3120 .base_baud = 921600, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b4_bt_4_921600] = { 3124 .flags = FL_BASE4, 3125 .num_ports = 4, 3126 .base_baud = 921600, 3127 .uart_offset = 8, 3128 }, 3129 [pbn_b4_bt_8_921600] = { 3130 .flags = FL_BASE4, 3131 .num_ports = 8, 3132 .base_baud = 921600, 3133 .uart_offset = 8, 3134 }, 3135 3136 /* 3137 * Entries following this are board-specific. 3138 */ 3139 3140 /* 3141 * Panacom - IOMEM 3142 */ 3143 [pbn_panacom] = { 3144 .flags = FL_BASE2, 3145 .num_ports = 2, 3146 .base_baud = 921600, 3147 .uart_offset = 0x400, 3148 .reg_shift = 7, 3149 }, 3150 [pbn_panacom2] = { 3151 .flags = FL_BASE2|FL_BASE_BARS, 3152 .num_ports = 2, 3153 .base_baud = 921600, 3154 .uart_offset = 0x400, 3155 .reg_shift = 7, 3156 }, 3157 [pbn_panacom4] = { 3158 .flags = FL_BASE2|FL_BASE_BARS, 3159 .num_ports = 4, 3160 .base_baud = 921600, 3161 .uart_offset = 0x400, 3162 .reg_shift = 7, 3163 }, 3164 3165 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3166 [pbn_plx_romulus] = { 3167 .flags = FL_BASE2, 3168 .num_ports = 4, 3169 .base_baud = 921600, 3170 .uart_offset = 8 << 2, 3171 .reg_shift = 2, 3172 .first_offset = 0x03, 3173 }, 3174 3175 /* 3176 * EndRun Technologies 3177 * Uses the size of PCI Base region 0 to 3178 * signal now many ports are available 3179 * 2 port 952 Uart support 3180 */ 3181 [pbn_endrun_2_4000000] = { 3182 .flags = FL_BASE0, 3183 .num_ports = 2, 3184 .base_baud = 4000000, 3185 .uart_offset = 0x200, 3186 .first_offset = 0x1000, 3187 }, 3188 3189 /* 3190 * This board uses the size of PCI Base region 0 to 3191 * signal now many ports are available 3192 */ 3193 [pbn_oxsemi] = { 3194 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3195 .num_ports = 32, 3196 .base_baud = 115200, 3197 .uart_offset = 8, 3198 }, 3199 [pbn_oxsemi_1_4000000] = { 3200 .flags = FL_BASE0, 3201 .num_ports = 1, 3202 .base_baud = 4000000, 3203 .uart_offset = 0x200, 3204 .first_offset = 0x1000, 3205 }, 3206 [pbn_oxsemi_2_4000000] = { 3207 .flags = FL_BASE0, 3208 .num_ports = 2, 3209 .base_baud = 4000000, 3210 .uart_offset = 0x200, 3211 .first_offset = 0x1000, 3212 }, 3213 [pbn_oxsemi_4_4000000] = { 3214 .flags = FL_BASE0, 3215 .num_ports = 4, 3216 .base_baud = 4000000, 3217 .uart_offset = 0x200, 3218 .first_offset = 0x1000, 3219 }, 3220 [pbn_oxsemi_8_4000000] = { 3221 .flags = FL_BASE0, 3222 .num_ports = 8, 3223 .base_baud = 4000000, 3224 .uart_offset = 0x200, 3225 .first_offset = 0x1000, 3226 }, 3227 3228 3229 /* 3230 * EKF addition for i960 Boards form EKF with serial port. 3231 * Max 256 ports. 3232 */ 3233 [pbn_intel_i960] = { 3234 .flags = FL_BASE0, 3235 .num_ports = 32, 3236 .base_baud = 921600, 3237 .uart_offset = 8 << 2, 3238 .reg_shift = 2, 3239 .first_offset = 0x10000, 3240 }, 3241 [pbn_sgi_ioc3] = { 3242 .flags = FL_BASE0|FL_NOIRQ, 3243 .num_ports = 1, 3244 .base_baud = 458333, 3245 .uart_offset = 8, 3246 .reg_shift = 0, 3247 .first_offset = 0x20178, 3248 }, 3249 3250 /* 3251 * Computone - uses IOMEM. 3252 */ 3253 [pbn_computone_4] = { 3254 .flags = FL_BASE0, 3255 .num_ports = 4, 3256 .base_baud = 921600, 3257 .uart_offset = 0x40, 3258 .reg_shift = 2, 3259 .first_offset = 0x200, 3260 }, 3261 [pbn_computone_6] = { 3262 .flags = FL_BASE0, 3263 .num_ports = 6, 3264 .base_baud = 921600, 3265 .uart_offset = 0x40, 3266 .reg_shift = 2, 3267 .first_offset = 0x200, 3268 }, 3269 [pbn_computone_8] = { 3270 .flags = FL_BASE0, 3271 .num_ports = 8, 3272 .base_baud = 921600, 3273 .uart_offset = 0x40, 3274 .reg_shift = 2, 3275 .first_offset = 0x200, 3276 }, 3277 [pbn_sbsxrsio] = { 3278 .flags = FL_BASE0, 3279 .num_ports = 8, 3280 .base_baud = 460800, 3281 .uart_offset = 256, 3282 .reg_shift = 4, 3283 }, 3284 /* 3285 * PA Semi PWRficient PA6T-1682M on-chip UART 3286 */ 3287 [pbn_pasemi_1682M] = { 3288 .flags = FL_BASE0, 3289 .num_ports = 1, 3290 .base_baud = 8333333, 3291 }, 3292 /* 3293 * National Instruments 843x 3294 */ 3295 [pbn_ni8430_16] = { 3296 .flags = FL_BASE0, 3297 .num_ports = 16, 3298 .base_baud = 3686400, 3299 .uart_offset = 0x10, 3300 .first_offset = 0x800, 3301 }, 3302 [pbn_ni8430_8] = { 3303 .flags = FL_BASE0, 3304 .num_ports = 8, 3305 .base_baud = 3686400, 3306 .uart_offset = 0x10, 3307 .first_offset = 0x800, 3308 }, 3309 [pbn_ni8430_4] = { 3310 .flags = FL_BASE0, 3311 .num_ports = 4, 3312 .base_baud = 3686400, 3313 .uart_offset = 0x10, 3314 .first_offset = 0x800, 3315 }, 3316 [pbn_ni8430_2] = { 3317 .flags = FL_BASE0, 3318 .num_ports = 2, 3319 .base_baud = 3686400, 3320 .uart_offset = 0x10, 3321 .first_offset = 0x800, 3322 }, 3323 /* 3324 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3325 */ 3326 [pbn_ADDIDATA_PCIe_1_3906250] = { 3327 .flags = FL_BASE0, 3328 .num_ports = 1, 3329 .base_baud = 3906250, 3330 .uart_offset = 0x200, 3331 .first_offset = 0x1000, 3332 }, 3333 [pbn_ADDIDATA_PCIe_2_3906250] = { 3334 .flags = FL_BASE0, 3335 .num_ports = 2, 3336 .base_baud = 3906250, 3337 .uart_offset = 0x200, 3338 .first_offset = 0x1000, 3339 }, 3340 [pbn_ADDIDATA_PCIe_4_3906250] = { 3341 .flags = FL_BASE0, 3342 .num_ports = 4, 3343 .base_baud = 3906250, 3344 .uart_offset = 0x200, 3345 .first_offset = 0x1000, 3346 }, 3347 [pbn_ADDIDATA_PCIe_8_3906250] = { 3348 .flags = FL_BASE0, 3349 .num_ports = 8, 3350 .base_baud = 3906250, 3351 .uart_offset = 0x200, 3352 .first_offset = 0x1000, 3353 }, 3354 [pbn_ce4100_1_115200] = { 3355 .flags = FL_BASE_BARS, 3356 .num_ports = 2, 3357 .base_baud = 921600, 3358 .reg_shift = 2, 3359 }, 3360 [pbn_omegapci] = { 3361 .flags = FL_BASE0, 3362 .num_ports = 8, 3363 .base_baud = 115200, 3364 .uart_offset = 0x200, 3365 }, 3366 [pbn_NETMOS9900_2s_115200] = { 3367 .flags = FL_BASE0, 3368 .num_ports = 2, 3369 .base_baud = 115200, 3370 }, 3371 [pbn_brcm_trumanage] = { 3372 .flags = FL_BASE0, 3373 .num_ports = 1, 3374 .reg_shift = 2, 3375 .base_baud = 115200, 3376 }, 3377 [pbn_fintek_4] = { 3378 .num_ports = 4, 3379 .uart_offset = 8, 3380 .base_baud = 115200, 3381 .first_offset = 0x40, 3382 }, 3383 [pbn_fintek_8] = { 3384 .num_ports = 8, 3385 .uart_offset = 8, 3386 .base_baud = 115200, 3387 .first_offset = 0x40, 3388 }, 3389 [pbn_fintek_12] = { 3390 .num_ports = 12, 3391 .uart_offset = 8, 3392 .base_baud = 115200, 3393 .first_offset = 0x40, 3394 }, 3395 [pbn_wch382_2] = { 3396 .flags = FL_BASE0, 3397 .num_ports = 2, 3398 .base_baud = 115200, 3399 .uart_offset = 8, 3400 .first_offset = 0xC0, 3401 }, 3402 [pbn_wch384_4] = { 3403 .flags = FL_BASE0, 3404 .num_ports = 4, 3405 .base_baud = 115200, 3406 .uart_offset = 8, 3407 .first_offset = 0xC0, 3408 }, 3409 /* 3410 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3411 */ 3412 [pbn_pericom_PI7C9X7951] = { 3413 .flags = FL_BASE0, 3414 .num_ports = 1, 3415 .base_baud = 921600, 3416 .uart_offset = 0x8, 3417 }, 3418 [pbn_pericom_PI7C9X7952] = { 3419 .flags = FL_BASE0, 3420 .num_ports = 2, 3421 .base_baud = 921600, 3422 .uart_offset = 0x8, 3423 }, 3424 [pbn_pericom_PI7C9X7954] = { 3425 .flags = FL_BASE0, 3426 .num_ports = 4, 3427 .base_baud = 921600, 3428 .uart_offset = 0x8, 3429 }, 3430 [pbn_pericom_PI7C9X7958] = { 3431 .flags = FL_BASE0, 3432 .num_ports = 8, 3433 .base_baud = 921600, 3434 .uart_offset = 0x8, 3435 }, 3436 }; 3437 3438 static const struct pci_device_id blacklist[] = { 3439 /* softmodems */ 3440 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3441 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3442 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3443 3444 /* multi-io cards handled by parport_serial */ 3445 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3446 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3447 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3448 3449 /* Moxa Smartio MUE boards handled by 8250_moxa */ 3450 { PCI_VDEVICE(MOXA, 0x1024), }, 3451 { PCI_VDEVICE(MOXA, 0x1025), }, 3452 { PCI_VDEVICE(MOXA, 0x1045), }, 3453 { PCI_VDEVICE(MOXA, 0x1144), }, 3454 { PCI_VDEVICE(MOXA, 0x1160), }, 3455 { PCI_VDEVICE(MOXA, 0x1161), }, 3456 { PCI_VDEVICE(MOXA, 0x1182), }, 3457 { PCI_VDEVICE(MOXA, 0x1183), }, 3458 { PCI_VDEVICE(MOXA, 0x1322), }, 3459 { PCI_VDEVICE(MOXA, 0x1342), }, 3460 { PCI_VDEVICE(MOXA, 0x1381), }, 3461 { PCI_VDEVICE(MOXA, 0x1683), }, 3462 3463 /* Intel platforms with MID UART */ 3464 { PCI_VDEVICE(INTEL, 0x081b), }, 3465 { PCI_VDEVICE(INTEL, 0x081c), }, 3466 { PCI_VDEVICE(INTEL, 0x081d), }, 3467 { PCI_VDEVICE(INTEL, 0x1191), }, 3468 { PCI_VDEVICE(INTEL, 0x18d8), }, 3469 { PCI_VDEVICE(INTEL, 0x19d8), }, 3470 3471 /* Intel platforms with DesignWare UART */ 3472 { PCI_VDEVICE(INTEL, 0x0936), }, 3473 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3474 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3475 { PCI_VDEVICE(INTEL, 0x228a), }, 3476 { PCI_VDEVICE(INTEL, 0x228c), }, 3477 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3478 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3479 3480 /* Exar devices */ 3481 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3482 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3483 3484 /* End of the black list */ 3485 { } 3486 }; 3487 3488 static int serial_pci_is_class_communication(struct pci_dev *dev) 3489 { 3490 /* 3491 * If it is not a communications device or the programming 3492 * interface is greater than 6, give up. 3493 */ 3494 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3495 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3496 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3497 (dev->class & 0xff) > 6) 3498 return -ENODEV; 3499 3500 return 0; 3501 } 3502 3503 /* 3504 * Given a complete unknown PCI device, try to use some heuristics to 3505 * guess what the configuration might be, based on the pitiful PCI 3506 * serial specs. Returns 0 on success, -ENODEV on failure. 3507 */ 3508 static int 3509 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3510 { 3511 int num_iomem, num_port, first_port = -1, i; 3512 int rc; 3513 3514 rc = serial_pci_is_class_communication(dev); 3515 if (rc) 3516 return rc; 3517 3518 /* 3519 * Should we try to make guesses for multiport serial devices later? 3520 */ 3521 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3522 return -ENODEV; 3523 3524 num_iomem = num_port = 0; 3525 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3526 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3527 num_port++; 3528 if (first_port == -1) 3529 first_port = i; 3530 } 3531 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3532 num_iomem++; 3533 } 3534 3535 /* 3536 * If there is 1 or 0 iomem regions, and exactly one port, 3537 * use it. We guess the number of ports based on the IO 3538 * region size. 3539 */ 3540 if (num_iomem <= 1 && num_port == 1) { 3541 board->flags = first_port; 3542 board->num_ports = pci_resource_len(dev, first_port) / 8; 3543 return 0; 3544 } 3545 3546 /* 3547 * Now guess if we've got a board which indexes by BARs. 3548 * Each IO BAR should be 8 bytes, and they should follow 3549 * consecutively. 3550 */ 3551 first_port = -1; 3552 num_port = 0; 3553 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3554 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3555 pci_resource_len(dev, i) == 8 && 3556 (first_port == -1 || (first_port + num_port) == i)) { 3557 num_port++; 3558 if (first_port == -1) 3559 first_port = i; 3560 } 3561 } 3562 3563 if (num_port > 1) { 3564 board->flags = first_port | FL_BASE_BARS; 3565 board->num_ports = num_port; 3566 return 0; 3567 } 3568 3569 return -ENODEV; 3570 } 3571 3572 static inline int 3573 serial_pci_matches(const struct pciserial_board *board, 3574 const struct pciserial_board *guessed) 3575 { 3576 return 3577 board->num_ports == guessed->num_ports && 3578 board->base_baud == guessed->base_baud && 3579 board->uart_offset == guessed->uart_offset && 3580 board->reg_shift == guessed->reg_shift && 3581 board->first_offset == guessed->first_offset; 3582 } 3583 3584 struct serial_private * 3585 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3586 { 3587 struct uart_8250_port uart; 3588 struct serial_private *priv; 3589 struct pci_serial_quirk *quirk; 3590 int rc, nr_ports, i; 3591 3592 nr_ports = board->num_ports; 3593 3594 /* 3595 * Find an init and setup quirks. 3596 */ 3597 quirk = find_quirk(dev); 3598 3599 /* 3600 * Run the new-style initialization function. 3601 * The initialization function returns: 3602 * <0 - error 3603 * 0 - use board->num_ports 3604 * >0 - number of ports 3605 */ 3606 if (quirk->init) { 3607 rc = quirk->init(dev); 3608 if (rc < 0) { 3609 priv = ERR_PTR(rc); 3610 goto err_out; 3611 } 3612 if (rc) 3613 nr_ports = rc; 3614 } 3615 3616 priv = kzalloc(sizeof(struct serial_private) + 3617 sizeof(unsigned int) * nr_ports, 3618 GFP_KERNEL); 3619 if (!priv) { 3620 priv = ERR_PTR(-ENOMEM); 3621 goto err_deinit; 3622 } 3623 3624 priv->dev = dev; 3625 priv->quirk = quirk; 3626 3627 memset(&uart, 0, sizeof(uart)); 3628 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3629 uart.port.uartclk = board->base_baud * 16; 3630 uart.port.irq = get_pci_irq(dev, board); 3631 uart.port.dev = &dev->dev; 3632 3633 for (i = 0; i < nr_ports; i++) { 3634 if (quirk->setup(priv, board, &uart, i)) 3635 break; 3636 3637 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3638 uart.port.iobase, uart.port.irq, uart.port.iotype); 3639 3640 priv->line[i] = serial8250_register_8250_port(&uart); 3641 if (priv->line[i] < 0) { 3642 dev_err(&dev->dev, 3643 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3644 uart.port.iobase, uart.port.irq, 3645 uart.port.iotype, priv->line[i]); 3646 break; 3647 } 3648 } 3649 priv->nr = i; 3650 priv->board = board; 3651 return priv; 3652 3653 err_deinit: 3654 if (quirk->exit) 3655 quirk->exit(dev); 3656 err_out: 3657 return priv; 3658 } 3659 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3660 3661 static void pciserial_detach_ports(struct serial_private *priv) 3662 { 3663 struct pci_serial_quirk *quirk; 3664 int i; 3665 3666 for (i = 0; i < priv->nr; i++) 3667 serial8250_unregister_port(priv->line[i]); 3668 3669 /* 3670 * Find the exit quirks. 3671 */ 3672 quirk = find_quirk(priv->dev); 3673 if (quirk->exit) 3674 quirk->exit(priv->dev); 3675 } 3676 3677 void pciserial_remove_ports(struct serial_private *priv) 3678 { 3679 pciserial_detach_ports(priv); 3680 kfree(priv); 3681 } 3682 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3683 3684 void pciserial_suspend_ports(struct serial_private *priv) 3685 { 3686 int i; 3687 3688 for (i = 0; i < priv->nr; i++) 3689 if (priv->line[i] >= 0) 3690 serial8250_suspend_port(priv->line[i]); 3691 3692 /* 3693 * Ensure that every init quirk is properly torn down 3694 */ 3695 if (priv->quirk->exit) 3696 priv->quirk->exit(priv->dev); 3697 } 3698 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3699 3700 void pciserial_resume_ports(struct serial_private *priv) 3701 { 3702 int i; 3703 3704 /* 3705 * Ensure that the board is correctly configured. 3706 */ 3707 if (priv->quirk->init) 3708 priv->quirk->init(priv->dev); 3709 3710 for (i = 0; i < priv->nr; i++) 3711 if (priv->line[i] >= 0) 3712 serial8250_resume_port(priv->line[i]); 3713 } 3714 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3715 3716 /* 3717 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3718 * to the arrangement of serial ports on a PCI card. 3719 */ 3720 static int 3721 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3722 { 3723 struct pci_serial_quirk *quirk; 3724 struct serial_private *priv; 3725 const struct pciserial_board *board; 3726 const struct pci_device_id *exclude; 3727 struct pciserial_board tmp; 3728 int rc; 3729 3730 quirk = find_quirk(dev); 3731 if (quirk->probe) { 3732 rc = quirk->probe(dev); 3733 if (rc) 3734 return rc; 3735 } 3736 3737 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3738 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3739 ent->driver_data); 3740 return -EINVAL; 3741 } 3742 3743 board = &pci_boards[ent->driver_data]; 3744 3745 exclude = pci_match_id(blacklist, dev); 3746 if (exclude) 3747 return -ENODEV; 3748 3749 rc = pcim_enable_device(dev); 3750 pci_save_state(dev); 3751 if (rc) 3752 return rc; 3753 3754 if (ent->driver_data == pbn_default) { 3755 /* 3756 * Use a copy of the pci_board entry for this; 3757 * avoid changing entries in the table. 3758 */ 3759 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3760 board = &tmp; 3761 3762 /* 3763 * We matched one of our class entries. Try to 3764 * determine the parameters of this board. 3765 */ 3766 rc = serial_pci_guess_board(dev, &tmp); 3767 if (rc) 3768 return rc; 3769 } else { 3770 /* 3771 * We matched an explicit entry. If we are able to 3772 * detect this boards settings with our heuristic, 3773 * then we no longer need this entry. 3774 */ 3775 memcpy(&tmp, &pci_boards[pbn_default], 3776 sizeof(struct pciserial_board)); 3777 rc = serial_pci_guess_board(dev, &tmp); 3778 if (rc == 0 && serial_pci_matches(board, &tmp)) 3779 moan_device("Redundant entry in serial pci_table.", 3780 dev); 3781 } 3782 3783 priv = pciserial_init_ports(dev, board); 3784 if (IS_ERR(priv)) 3785 return PTR_ERR(priv); 3786 3787 pci_set_drvdata(dev, priv); 3788 return 0; 3789 } 3790 3791 static void pciserial_remove_one(struct pci_dev *dev) 3792 { 3793 struct serial_private *priv = pci_get_drvdata(dev); 3794 3795 pciserial_remove_ports(priv); 3796 } 3797 3798 #ifdef CONFIG_PM_SLEEP 3799 static int pciserial_suspend_one(struct device *dev) 3800 { 3801 struct pci_dev *pdev = to_pci_dev(dev); 3802 struct serial_private *priv = pci_get_drvdata(pdev); 3803 3804 if (priv) 3805 pciserial_suspend_ports(priv); 3806 3807 return 0; 3808 } 3809 3810 static int pciserial_resume_one(struct device *dev) 3811 { 3812 struct pci_dev *pdev = to_pci_dev(dev); 3813 struct serial_private *priv = pci_get_drvdata(pdev); 3814 int err; 3815 3816 if (priv) { 3817 /* 3818 * The device may have been disabled. Re-enable it. 3819 */ 3820 err = pci_enable_device(pdev); 3821 /* FIXME: We cannot simply error out here */ 3822 if (err) 3823 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 3824 pciserial_resume_ports(priv); 3825 } 3826 return 0; 3827 } 3828 #endif 3829 3830 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 3831 pciserial_resume_one); 3832 3833 static const struct pci_device_id serial_pci_tbl[] = { 3834 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3835 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3836 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3837 pbn_b2_8_921600 }, 3838 /* Advantech also use 0x3618 and 0xf618 */ 3839 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 3840 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3841 pbn_b0_4_921600 }, 3842 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 3843 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3844 pbn_b0_4_921600 }, 3845 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3846 PCI_SUBVENDOR_ID_CONNECT_TECH, 3847 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3848 pbn_b1_8_1382400 }, 3849 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3850 PCI_SUBVENDOR_ID_CONNECT_TECH, 3851 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3852 pbn_b1_4_1382400 }, 3853 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3854 PCI_SUBVENDOR_ID_CONNECT_TECH, 3855 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3856 pbn_b1_2_1382400 }, 3857 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3858 PCI_SUBVENDOR_ID_CONNECT_TECH, 3859 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3860 pbn_b1_8_1382400 }, 3861 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3862 PCI_SUBVENDOR_ID_CONNECT_TECH, 3863 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3864 pbn_b1_4_1382400 }, 3865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3866 PCI_SUBVENDOR_ID_CONNECT_TECH, 3867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3868 pbn_b1_2_1382400 }, 3869 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3870 PCI_SUBVENDOR_ID_CONNECT_TECH, 3871 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3872 pbn_b1_8_921600 }, 3873 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3874 PCI_SUBVENDOR_ID_CONNECT_TECH, 3875 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3876 pbn_b1_8_921600 }, 3877 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3878 PCI_SUBVENDOR_ID_CONNECT_TECH, 3879 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3880 pbn_b1_4_921600 }, 3881 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3882 PCI_SUBVENDOR_ID_CONNECT_TECH, 3883 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3884 pbn_b1_4_921600 }, 3885 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3886 PCI_SUBVENDOR_ID_CONNECT_TECH, 3887 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3888 pbn_b1_2_921600 }, 3889 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3890 PCI_SUBVENDOR_ID_CONNECT_TECH, 3891 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3892 pbn_b1_8_921600 }, 3893 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3894 PCI_SUBVENDOR_ID_CONNECT_TECH, 3895 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3896 pbn_b1_8_921600 }, 3897 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3898 PCI_SUBVENDOR_ID_CONNECT_TECH, 3899 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3900 pbn_b1_4_921600 }, 3901 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3902 PCI_SUBVENDOR_ID_CONNECT_TECH, 3903 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 3904 pbn_b1_2_1250000 }, 3905 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3906 PCI_SUBVENDOR_ID_CONNECT_TECH, 3907 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 3908 pbn_b0_2_1843200 }, 3909 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3910 PCI_SUBVENDOR_ID_CONNECT_TECH, 3911 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 3912 pbn_b0_4_1843200 }, 3913 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3914 PCI_VENDOR_ID_AFAVLAB, 3915 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 3916 pbn_b0_4_1152000 }, 3917 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3919 pbn_b2_bt_1_115200 }, 3920 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3922 pbn_b2_bt_2_115200 }, 3923 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3925 pbn_b2_bt_4_115200 }, 3926 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3928 pbn_b2_bt_2_115200 }, 3929 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3931 pbn_b2_bt_4_115200 }, 3932 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3934 pbn_b2_8_115200 }, 3935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3937 pbn_b2_8_460800 }, 3938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3940 pbn_b2_8_115200 }, 3941 3942 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3944 pbn_b2_bt_2_115200 }, 3945 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3947 pbn_b2_bt_2_921600 }, 3948 /* 3949 * VScom SPCOM800, from sl@s.pl 3950 */ 3951 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3953 pbn_b2_8_921600 }, 3954 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3956 pbn_b2_4_921600 }, 3957 /* Unknown card - subdevice 0x1584 */ 3958 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3959 PCI_VENDOR_ID_PLX, 3960 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 3961 pbn_b2_4_115200 }, 3962 /* Unknown card - subdevice 0x1588 */ 3963 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3964 PCI_VENDOR_ID_PLX, 3965 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 3966 pbn_b2_8_115200 }, 3967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3968 PCI_SUBVENDOR_ID_KEYSPAN, 3969 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 3970 pbn_panacom }, 3971 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3973 pbn_panacom4 }, 3974 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3976 pbn_panacom2 }, 3977 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 3978 PCI_VENDOR_ID_ESDGMBH, 3979 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 3980 pbn_b2_4_115200 }, 3981 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3982 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3983 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 3984 pbn_b2_4_460800 }, 3985 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3986 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3987 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 3988 pbn_b2_8_460800 }, 3989 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3990 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3991 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 3992 pbn_b2_16_460800 }, 3993 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3994 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 3995 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 3996 pbn_b2_16_460800 }, 3997 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 3998 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 3999 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4000 pbn_b2_4_460800 }, 4001 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4002 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4003 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4004 pbn_b2_8_460800 }, 4005 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4006 PCI_SUBVENDOR_ID_EXSYS, 4007 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4008 pbn_b2_4_115200 }, 4009 /* 4010 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4011 * (Exoray@isys.ca) 4012 */ 4013 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4014 0x10b5, 0x106a, 0, 0, 4015 pbn_plx_romulus }, 4016 /* 4017 * EndRun Technologies. PCI express device range. 4018 * EndRun PTP/1588 has 2 Native UARTs. 4019 */ 4020 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4022 pbn_endrun_2_4000000 }, 4023 /* 4024 * Quatech cards. These actually have configurable clocks but for 4025 * now we just use the default. 4026 * 4027 * 100 series are RS232, 200 series RS422, 4028 */ 4029 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4031 pbn_b1_4_115200 }, 4032 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4034 pbn_b1_2_115200 }, 4035 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4037 pbn_b2_2_115200 }, 4038 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4040 pbn_b1_2_115200 }, 4041 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4043 pbn_b2_2_115200 }, 4044 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4046 pbn_b1_4_115200 }, 4047 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4049 pbn_b1_8_115200 }, 4050 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4052 pbn_b1_8_115200 }, 4053 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4055 pbn_b1_4_115200 }, 4056 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4058 pbn_b1_2_115200 }, 4059 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4061 pbn_b1_4_115200 }, 4062 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4064 pbn_b1_2_115200 }, 4065 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4067 pbn_b2_4_115200 }, 4068 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4070 pbn_b2_2_115200 }, 4071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4073 pbn_b2_1_115200 }, 4074 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4076 pbn_b2_4_115200 }, 4077 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4079 pbn_b2_2_115200 }, 4080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4082 pbn_b2_1_115200 }, 4083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4085 pbn_b0_8_115200 }, 4086 4087 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4088 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4089 0, 0, 4090 pbn_b0_4_921600 }, 4091 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4092 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4093 0, 0, 4094 pbn_b0_4_1152000 }, 4095 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4097 pbn_b0_bt_2_921600 }, 4098 4099 /* 4100 * The below card is a little controversial since it is the 4101 * subject of a PCI vendor/device ID clash. (See 4102 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4103 * For now just used the hex ID 0x950a. 4104 */ 4105 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4106 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4107 0, 0, pbn_b0_2_115200 }, 4108 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4109 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4110 0, 0, pbn_b0_2_115200 }, 4111 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4113 pbn_b0_2_1130000 }, 4114 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4115 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4116 pbn_b0_1_921600 }, 4117 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4119 pbn_b0_4_115200 }, 4120 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4122 pbn_b0_bt_2_921600 }, 4123 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4125 pbn_b2_8_1152000 }, 4126 4127 /* 4128 * Oxford Semiconductor Inc. Tornado PCI express device range. 4129 */ 4130 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4132 pbn_b0_1_4000000 }, 4133 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4135 pbn_b0_1_4000000 }, 4136 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4138 pbn_oxsemi_1_4000000 }, 4139 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4141 pbn_oxsemi_1_4000000 }, 4142 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4144 pbn_b0_1_4000000 }, 4145 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4147 pbn_b0_1_4000000 }, 4148 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4150 pbn_oxsemi_1_4000000 }, 4151 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4153 pbn_oxsemi_1_4000000 }, 4154 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4156 pbn_b0_1_4000000 }, 4157 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4159 pbn_b0_1_4000000 }, 4160 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4162 pbn_b0_1_4000000 }, 4163 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4165 pbn_b0_1_4000000 }, 4166 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4168 pbn_oxsemi_2_4000000 }, 4169 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4171 pbn_oxsemi_2_4000000 }, 4172 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4174 pbn_oxsemi_4_4000000 }, 4175 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4177 pbn_oxsemi_4_4000000 }, 4178 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4180 pbn_oxsemi_8_4000000 }, 4181 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4183 pbn_oxsemi_8_4000000 }, 4184 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4186 pbn_oxsemi_1_4000000 }, 4187 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4189 pbn_oxsemi_1_4000000 }, 4190 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4192 pbn_oxsemi_1_4000000 }, 4193 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4195 pbn_oxsemi_1_4000000 }, 4196 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4198 pbn_oxsemi_1_4000000 }, 4199 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4201 pbn_oxsemi_1_4000000 }, 4202 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4204 pbn_oxsemi_1_4000000 }, 4205 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4207 pbn_oxsemi_1_4000000 }, 4208 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4210 pbn_oxsemi_1_4000000 }, 4211 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_oxsemi_1_4000000 }, 4214 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4216 pbn_oxsemi_1_4000000 }, 4217 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4219 pbn_oxsemi_1_4000000 }, 4220 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4222 pbn_oxsemi_1_4000000 }, 4223 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4225 pbn_oxsemi_1_4000000 }, 4226 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4228 pbn_oxsemi_1_4000000 }, 4229 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4231 pbn_oxsemi_1_4000000 }, 4232 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4234 pbn_oxsemi_1_4000000 }, 4235 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4237 pbn_oxsemi_1_4000000 }, 4238 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4240 pbn_oxsemi_1_4000000 }, 4241 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4243 pbn_oxsemi_1_4000000 }, 4244 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4246 pbn_oxsemi_1_4000000 }, 4247 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4249 pbn_oxsemi_1_4000000 }, 4250 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4252 pbn_oxsemi_1_4000000 }, 4253 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4255 pbn_oxsemi_1_4000000 }, 4256 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4258 pbn_oxsemi_1_4000000 }, 4259 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4261 pbn_oxsemi_1_4000000 }, 4262 /* 4263 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4264 */ 4265 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4266 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4267 pbn_oxsemi_1_4000000 }, 4268 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4269 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4270 pbn_oxsemi_2_4000000 }, 4271 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4272 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4273 pbn_oxsemi_4_4000000 }, 4274 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4275 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4276 pbn_oxsemi_8_4000000 }, 4277 4278 /* 4279 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4280 */ 4281 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4282 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4283 pbn_oxsemi_2_4000000 }, 4284 4285 /* 4286 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4287 * from skokodyn@yahoo.com 4288 */ 4289 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4290 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4291 pbn_sbsxrsio }, 4292 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4293 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4294 pbn_sbsxrsio }, 4295 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4296 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4297 pbn_sbsxrsio }, 4298 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4299 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4300 pbn_sbsxrsio }, 4301 4302 /* 4303 * Digitan DS560-558, from jimd@esoft.com 4304 */ 4305 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_b1_1_115200 }, 4308 4309 /* 4310 * Titan Electronic cards 4311 * The 400L and 800L have a custom setup quirk. 4312 */ 4313 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_b0_1_921600 }, 4316 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4318 pbn_b0_2_921600 }, 4319 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4321 pbn_b0_4_921600 }, 4322 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4324 pbn_b0_4_921600 }, 4325 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4327 pbn_b1_1_921600 }, 4328 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_b1_bt_2_921600 }, 4331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4333 pbn_b0_bt_4_921600 }, 4334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4336 pbn_b0_bt_8_921600 }, 4337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_b4_bt_2_921600 }, 4340 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_b4_bt_4_921600 }, 4343 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4345 pbn_b4_bt_8_921600 }, 4346 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4348 pbn_b0_4_921600 }, 4349 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4351 pbn_b0_4_921600 }, 4352 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_b0_4_921600 }, 4355 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4357 pbn_oxsemi_1_4000000 }, 4358 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4360 pbn_oxsemi_2_4000000 }, 4361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4363 pbn_oxsemi_4_4000000 }, 4364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4366 pbn_oxsemi_8_4000000 }, 4367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4369 pbn_oxsemi_2_4000000 }, 4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4372 pbn_oxsemi_2_4000000 }, 4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4375 pbn_b0_bt_2_921600 }, 4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4378 pbn_b0_4_921600 }, 4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4381 pbn_b0_4_921600 }, 4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4384 pbn_b0_4_921600 }, 4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4387 pbn_b0_4_921600 }, 4388 4389 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b2_1_460800 }, 4392 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b2_1_460800 }, 4395 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4397 pbn_b2_1_460800 }, 4398 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4400 pbn_b2_bt_2_921600 }, 4401 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b2_bt_2_921600 }, 4404 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b2_bt_2_921600 }, 4407 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b2_bt_4_921600 }, 4410 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b2_bt_4_921600 }, 4413 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b2_bt_4_921600 }, 4416 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_b0_1_921600 }, 4419 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_b0_1_921600 }, 4422 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_b0_1_921600 }, 4425 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_b0_bt_2_921600 }, 4428 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_b0_bt_2_921600 }, 4431 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_b0_bt_2_921600 }, 4434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b0_bt_4_921600 }, 4437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_b0_bt_4_921600 }, 4440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_b0_bt_4_921600 }, 4443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_b0_bt_8_921600 }, 4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_b0_bt_8_921600 }, 4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_b0_bt_8_921600 }, 4452 4453 /* 4454 * Computone devices submitted by Doug McNash dmcnash@computone.com 4455 */ 4456 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4457 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4458 0, 0, pbn_computone_4 }, 4459 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4460 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4461 0, 0, pbn_computone_8 }, 4462 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4463 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4464 0, 0, pbn_computone_6 }, 4465 4466 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi }, 4469 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4470 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4471 pbn_b0_bt_1_921600 }, 4472 4473 /* 4474 * SUNIX (TIMEDIA) 4475 */ 4476 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4477 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4478 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4479 pbn_b0_bt_1_921600 }, 4480 4481 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4482 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4483 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4484 pbn_b0_bt_1_921600 }, 4485 4486 /* 4487 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4488 */ 4489 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_b0_bt_8_115200 }, 4492 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_b0_bt_8_115200 }, 4495 4496 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_b0_bt_2_115200 }, 4499 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_b0_bt_2_115200 }, 4502 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_b0_bt_2_115200 }, 4505 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_b0_bt_2_115200 }, 4508 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_b0_bt_2_115200 }, 4511 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_b0_bt_4_460800 }, 4514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_b0_bt_4_460800 }, 4517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_b0_bt_2_460800 }, 4520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_b0_bt_2_460800 }, 4523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_b0_bt_2_460800 }, 4526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_b0_bt_1_115200 }, 4529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_b0_bt_1_460800 }, 4532 4533 /* 4534 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4535 * Cards are identified by their subsystem vendor IDs, which 4536 * (in hex) match the model number. 4537 * 4538 * Note that JC140x are RS422/485 cards which require ox950 4539 * ACR = 0x10, and as such are not currently fully supported. 4540 */ 4541 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4542 0x1204, 0x0004, 0, 0, 4543 pbn_b0_4_921600 }, 4544 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4545 0x1208, 0x0004, 0, 0, 4546 pbn_b0_4_921600 }, 4547 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4548 0x1402, 0x0002, 0, 0, 4549 pbn_b0_2_921600 }, */ 4550 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4551 0x1404, 0x0004, 0, 0, 4552 pbn_b0_4_921600 }, */ 4553 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4554 0x1208, 0x0004, 0, 0, 4555 pbn_b0_4_921600 }, 4556 4557 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4558 0x1204, 0x0004, 0, 0, 4559 pbn_b0_4_921600 }, 4560 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4561 0x1208, 0x0004, 0, 0, 4562 pbn_b0_4_921600 }, 4563 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4564 0x1208, 0x0004, 0, 0, 4565 pbn_b0_4_921600 }, 4566 /* 4567 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4568 */ 4569 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4571 pbn_b1_1_1382400 }, 4572 4573 /* 4574 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4575 */ 4576 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4578 pbn_b1_1_1382400 }, 4579 4580 /* 4581 * RAStel 2 port modem, gerg@moreton.com.au 4582 */ 4583 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_b2_bt_2_115200 }, 4586 4587 /* 4588 * EKF addition for i960 Boards form EKF with serial port 4589 */ 4590 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4591 0xE4BF, PCI_ANY_ID, 0, 0, 4592 pbn_intel_i960 }, 4593 4594 /* 4595 * Xircom Cardbus/Ethernet combos 4596 */ 4597 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b0_1_115200 }, 4600 /* 4601 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4602 */ 4603 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4605 pbn_b0_1_115200 }, 4606 4607 /* 4608 * Untested PCI modems, sent in from various folks... 4609 */ 4610 4611 /* 4612 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4613 */ 4614 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4615 0x1048, 0x1500, 0, 0, 4616 pbn_b1_1_115200 }, 4617 4618 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4619 0xFF00, 0, 0, 0, 4620 pbn_sgi_ioc3 }, 4621 4622 /* 4623 * HP Diva card 4624 */ 4625 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4626 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4627 pbn_b1_1_115200 }, 4628 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_b0_5_115200 }, 4631 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_b2_1_115200 }, 4634 4635 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b3_2_115200 }, 4638 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_b3_4_115200 }, 4641 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_b3_8_115200 }, 4644 /* 4645 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4646 */ 4647 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4648 PCI_ANY_ID, PCI_ANY_ID, 4649 0, 4650 0, pbn_pericom_PI7C9X7951 }, 4651 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4652 PCI_ANY_ID, PCI_ANY_ID, 4653 0, 4654 0, pbn_pericom_PI7C9X7952 }, 4655 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4656 PCI_ANY_ID, PCI_ANY_ID, 4657 0, 4658 0, pbn_pericom_PI7C9X7954 }, 4659 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 4660 PCI_ANY_ID, PCI_ANY_ID, 4661 0, 4662 0, pbn_pericom_PI7C9X7958 }, 4663 /* 4664 * ACCES I/O Products quad 4665 */ 4666 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_pericom_PI7C9X7952 }, 4669 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_pericom_PI7C9X7952 }, 4672 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_pericom_PI7C9X7954 }, 4675 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_pericom_PI7C9X7954 }, 4678 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_pericom_PI7C9X7952 }, 4681 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_pericom_PI7C9X7952 }, 4684 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_pericom_PI7C9X7954 }, 4687 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_pericom_PI7C9X7954 }, 4690 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_pericom_PI7C9X7952 }, 4693 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_pericom_PI7C9X7952 }, 4696 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_pericom_PI7C9X7954 }, 4699 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_pericom_PI7C9X7954 }, 4702 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_pericom_PI7C9X7951 }, 4705 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_pericom_PI7C9X7952 }, 4708 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_pericom_PI7C9X7952 }, 4711 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_pericom_PI7C9X7954 }, 4714 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_pericom_PI7C9X7954 }, 4717 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4719 pbn_pericom_PI7C9X7952 }, 4720 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_pericom_PI7C9X7954 }, 4723 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_pericom_PI7C9X7952 }, 4726 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4728 pbn_pericom_PI7C9X7952 }, 4729 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4731 pbn_pericom_PI7C9X7954 }, 4732 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4734 pbn_pericom_PI7C9X7954 }, 4735 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4737 pbn_pericom_PI7C9X7952 }, 4738 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4740 pbn_pericom_PI7C9X7954 }, 4741 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_pericom_PI7C9X7954 }, 4744 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_pericom_PI7C9X7958 }, 4747 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4749 pbn_pericom_PI7C9X7958 }, 4750 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4752 pbn_pericom_PI7C9X7954 }, 4753 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4755 pbn_pericom_PI7C9X7958 }, 4756 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4758 pbn_pericom_PI7C9X7954 }, 4759 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4761 pbn_pericom_PI7C9X7958 }, 4762 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_pericom_PI7C9X7954 }, 4765 /* 4766 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4767 */ 4768 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b0_1_115200 }, 4771 /* 4772 * ITE 4773 */ 4774 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4775 PCI_ANY_ID, PCI_ANY_ID, 4776 0, 0, 4777 pbn_b1_bt_1_115200 }, 4778 4779 /* 4780 * IntaShield IS-200 4781 */ 4782 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4784 pbn_b2_2_115200 }, 4785 /* 4786 * IntaShield IS-400 4787 */ 4788 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4790 pbn_b2_4_115200 }, 4791 /* 4792 * BrainBoxes UC-260 4793 */ 4794 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4795 PCI_ANY_ID, PCI_ANY_ID, 4796 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4797 pbn_b2_4_115200 }, 4798 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4799 PCI_ANY_ID, PCI_ANY_ID, 4800 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4801 pbn_b2_4_115200 }, 4802 /* 4803 * Perle PCI-RAS cards 4804 */ 4805 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4806 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4807 0, 0, pbn_b2_4_921600 }, 4808 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4809 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4810 0, 0, pbn_b2_8_921600 }, 4811 4812 /* 4813 * Mainpine series cards: Fairly standard layout but fools 4814 * parts of the autodetect in some cases and uses otherwise 4815 * unmatched communications subclasses in the PCI Express case 4816 */ 4817 4818 { /* RockForceDUO */ 4819 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4820 PCI_VENDOR_ID_MAINPINE, 0x0200, 4821 0, 0, pbn_b0_2_115200 }, 4822 { /* RockForceQUATRO */ 4823 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4824 PCI_VENDOR_ID_MAINPINE, 0x0300, 4825 0, 0, pbn_b0_4_115200 }, 4826 { /* RockForceDUO+ */ 4827 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4828 PCI_VENDOR_ID_MAINPINE, 0x0400, 4829 0, 0, pbn_b0_2_115200 }, 4830 { /* RockForceQUATRO+ */ 4831 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4832 PCI_VENDOR_ID_MAINPINE, 0x0500, 4833 0, 0, pbn_b0_4_115200 }, 4834 { /* RockForce+ */ 4835 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4836 PCI_VENDOR_ID_MAINPINE, 0x0600, 4837 0, 0, pbn_b0_2_115200 }, 4838 { /* RockForce+ */ 4839 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4840 PCI_VENDOR_ID_MAINPINE, 0x0700, 4841 0, 0, pbn_b0_4_115200 }, 4842 { /* RockForceOCTO+ */ 4843 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4844 PCI_VENDOR_ID_MAINPINE, 0x0800, 4845 0, 0, pbn_b0_8_115200 }, 4846 { /* RockForceDUO+ */ 4847 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4848 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4849 0, 0, pbn_b0_2_115200 }, 4850 { /* RockForceQUARTRO+ */ 4851 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4852 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4853 0, 0, pbn_b0_4_115200 }, 4854 { /* RockForceOCTO+ */ 4855 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4856 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4857 0, 0, pbn_b0_8_115200 }, 4858 { /* RockForceD1 */ 4859 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4860 PCI_VENDOR_ID_MAINPINE, 0x2000, 4861 0, 0, pbn_b0_1_115200 }, 4862 { /* RockForceF1 */ 4863 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4864 PCI_VENDOR_ID_MAINPINE, 0x2100, 4865 0, 0, pbn_b0_1_115200 }, 4866 { /* RockForceD2 */ 4867 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4868 PCI_VENDOR_ID_MAINPINE, 0x2200, 4869 0, 0, pbn_b0_2_115200 }, 4870 { /* RockForceF2 */ 4871 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4872 PCI_VENDOR_ID_MAINPINE, 0x2300, 4873 0, 0, pbn_b0_2_115200 }, 4874 { /* RockForceD4 */ 4875 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4876 PCI_VENDOR_ID_MAINPINE, 0x2400, 4877 0, 0, pbn_b0_4_115200 }, 4878 { /* RockForceF4 */ 4879 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4880 PCI_VENDOR_ID_MAINPINE, 0x2500, 4881 0, 0, pbn_b0_4_115200 }, 4882 { /* RockForceD8 */ 4883 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4884 PCI_VENDOR_ID_MAINPINE, 0x2600, 4885 0, 0, pbn_b0_8_115200 }, 4886 { /* RockForceF8 */ 4887 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4888 PCI_VENDOR_ID_MAINPINE, 0x2700, 4889 0, 0, pbn_b0_8_115200 }, 4890 { /* IQ Express D1 */ 4891 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4892 PCI_VENDOR_ID_MAINPINE, 0x3000, 4893 0, 0, pbn_b0_1_115200 }, 4894 { /* IQ Express F1 */ 4895 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4896 PCI_VENDOR_ID_MAINPINE, 0x3100, 4897 0, 0, pbn_b0_1_115200 }, 4898 { /* IQ Express D2 */ 4899 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4900 PCI_VENDOR_ID_MAINPINE, 0x3200, 4901 0, 0, pbn_b0_2_115200 }, 4902 { /* IQ Express F2 */ 4903 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4904 PCI_VENDOR_ID_MAINPINE, 0x3300, 4905 0, 0, pbn_b0_2_115200 }, 4906 { /* IQ Express D4 */ 4907 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4908 PCI_VENDOR_ID_MAINPINE, 0x3400, 4909 0, 0, pbn_b0_4_115200 }, 4910 { /* IQ Express F4 */ 4911 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4912 PCI_VENDOR_ID_MAINPINE, 0x3500, 4913 0, 0, pbn_b0_4_115200 }, 4914 { /* IQ Express D8 */ 4915 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4916 PCI_VENDOR_ID_MAINPINE, 0x3C00, 4917 0, 0, pbn_b0_8_115200 }, 4918 { /* IQ Express F8 */ 4919 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4920 PCI_VENDOR_ID_MAINPINE, 0x3D00, 4921 0, 0, pbn_b0_8_115200 }, 4922 4923 4924 /* 4925 * PA Semi PA6T-1682M on-chip UART 4926 */ 4927 { PCI_VENDOR_ID_PASEMI, 0xa004, 4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4929 pbn_pasemi_1682M }, 4930 4931 /* 4932 * National Instruments 4933 */ 4934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4936 pbn_b1_16_115200 }, 4937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b1_8_115200 }, 4940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b1_bt_4_115200 }, 4943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b1_bt_2_115200 }, 4946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4948 pbn_b1_bt_4_115200 }, 4949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4951 pbn_b1_bt_2_115200 }, 4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4954 pbn_b1_16_115200 }, 4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4957 pbn_b1_8_115200 }, 4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4960 pbn_b1_bt_4_115200 }, 4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4963 pbn_b1_bt_2_115200 }, 4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4966 pbn_b1_bt_4_115200 }, 4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4969 pbn_b1_bt_2_115200 }, 4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4972 pbn_ni8430_2 }, 4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4975 pbn_ni8430_2 }, 4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4978 pbn_ni8430_4 }, 4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4981 pbn_ni8430_4 }, 4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4984 pbn_ni8430_8 }, 4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4987 pbn_ni8430_8 }, 4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4990 pbn_ni8430_16 }, 4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4993 pbn_ni8430_16 }, 4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4996 pbn_ni8430_2 }, 4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4999 pbn_ni8430_2 }, 5000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5002 pbn_ni8430_4 }, 5003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5005 pbn_ni8430_4 }, 5006 5007 /* 5008 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5009 */ 5010 { PCI_VENDOR_ID_ADDIDATA, 5011 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5012 PCI_ANY_ID, 5013 PCI_ANY_ID, 5014 0, 5015 0, 5016 pbn_b0_4_115200 }, 5017 5018 { PCI_VENDOR_ID_ADDIDATA, 5019 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5020 PCI_ANY_ID, 5021 PCI_ANY_ID, 5022 0, 5023 0, 5024 pbn_b0_2_115200 }, 5025 5026 { PCI_VENDOR_ID_ADDIDATA, 5027 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5028 PCI_ANY_ID, 5029 PCI_ANY_ID, 5030 0, 5031 0, 5032 pbn_b0_1_115200 }, 5033 5034 { PCI_VENDOR_ID_AMCC, 5035 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5036 PCI_ANY_ID, 5037 PCI_ANY_ID, 5038 0, 5039 0, 5040 pbn_b1_8_115200 }, 5041 5042 { PCI_VENDOR_ID_ADDIDATA, 5043 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5044 PCI_ANY_ID, 5045 PCI_ANY_ID, 5046 0, 5047 0, 5048 pbn_b0_4_115200 }, 5049 5050 { PCI_VENDOR_ID_ADDIDATA, 5051 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5052 PCI_ANY_ID, 5053 PCI_ANY_ID, 5054 0, 5055 0, 5056 pbn_b0_2_115200 }, 5057 5058 { PCI_VENDOR_ID_ADDIDATA, 5059 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5060 PCI_ANY_ID, 5061 PCI_ANY_ID, 5062 0, 5063 0, 5064 pbn_b0_1_115200 }, 5065 5066 { PCI_VENDOR_ID_ADDIDATA, 5067 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5068 PCI_ANY_ID, 5069 PCI_ANY_ID, 5070 0, 5071 0, 5072 pbn_b0_4_115200 }, 5073 5074 { PCI_VENDOR_ID_ADDIDATA, 5075 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5076 PCI_ANY_ID, 5077 PCI_ANY_ID, 5078 0, 5079 0, 5080 pbn_b0_2_115200 }, 5081 5082 { PCI_VENDOR_ID_ADDIDATA, 5083 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5084 PCI_ANY_ID, 5085 PCI_ANY_ID, 5086 0, 5087 0, 5088 pbn_b0_1_115200 }, 5089 5090 { PCI_VENDOR_ID_ADDIDATA, 5091 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5092 PCI_ANY_ID, 5093 PCI_ANY_ID, 5094 0, 5095 0, 5096 pbn_b0_8_115200 }, 5097 5098 { PCI_VENDOR_ID_ADDIDATA, 5099 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5100 PCI_ANY_ID, 5101 PCI_ANY_ID, 5102 0, 5103 0, 5104 pbn_ADDIDATA_PCIe_4_3906250 }, 5105 5106 { PCI_VENDOR_ID_ADDIDATA, 5107 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5108 PCI_ANY_ID, 5109 PCI_ANY_ID, 5110 0, 5111 0, 5112 pbn_ADDIDATA_PCIe_2_3906250 }, 5113 5114 { PCI_VENDOR_ID_ADDIDATA, 5115 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5116 PCI_ANY_ID, 5117 PCI_ANY_ID, 5118 0, 5119 0, 5120 pbn_ADDIDATA_PCIe_1_3906250 }, 5121 5122 { PCI_VENDOR_ID_ADDIDATA, 5123 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5124 PCI_ANY_ID, 5125 PCI_ANY_ID, 5126 0, 5127 0, 5128 pbn_ADDIDATA_PCIe_8_3906250 }, 5129 5130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5131 PCI_VENDOR_ID_IBM, 0x0299, 5132 0, 0, pbn_b0_bt_2_115200 }, 5133 5134 /* 5135 * other NetMos 9835 devices are most likely handled by the 5136 * parport_serial driver, check drivers/parport/parport_serial.c 5137 * before adding them here. 5138 */ 5139 5140 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5141 0xA000, 0x1000, 5142 0, 0, pbn_b0_1_115200 }, 5143 5144 /* the 9901 is a rebranded 9912 */ 5145 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5146 0xA000, 0x1000, 5147 0, 0, pbn_b0_1_115200 }, 5148 5149 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5150 0xA000, 0x1000, 5151 0, 0, pbn_b0_1_115200 }, 5152 5153 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5154 0xA000, 0x1000, 5155 0, 0, pbn_b0_1_115200 }, 5156 5157 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5158 0xA000, 0x1000, 5159 0, 0, pbn_b0_1_115200 }, 5160 5161 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5162 0xA000, 0x3002, 5163 0, 0, pbn_NETMOS9900_2s_115200 }, 5164 5165 /* 5166 * Best Connectivity and Rosewill PCI Multi I/O cards 5167 */ 5168 5169 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5170 0xA000, 0x1000, 5171 0, 0, pbn_b0_1_115200 }, 5172 5173 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5174 0xA000, 0x3002, 5175 0, 0, pbn_b0_bt_2_115200 }, 5176 5177 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5178 0xA000, 0x3004, 5179 0, 0, pbn_b0_bt_4_115200 }, 5180 /* Intel CE4100 */ 5181 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5183 pbn_ce4100_1_115200 }, 5184 5185 /* 5186 * Cronyx Omega PCI 5187 */ 5188 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5190 pbn_omegapci }, 5191 5192 /* 5193 * Broadcom TruManage 5194 */ 5195 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5197 pbn_brcm_trumanage }, 5198 5199 /* 5200 * AgeStar as-prs2-009 5201 */ 5202 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5203 PCI_ANY_ID, PCI_ANY_ID, 5204 0, 0, pbn_b0_bt_2_115200 }, 5205 5206 /* 5207 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5208 * so not listed here. 5209 */ 5210 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5211 PCI_ANY_ID, PCI_ANY_ID, 5212 0, 0, pbn_b0_bt_4_115200 }, 5213 5214 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5215 PCI_ANY_ID, PCI_ANY_ID, 5216 0, 0, pbn_b0_bt_2_115200 }, 5217 5218 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5219 PCI_ANY_ID, PCI_ANY_ID, 5220 0, 0, pbn_b0_bt_4_115200 }, 5221 5222 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5223 PCI_ANY_ID, PCI_ANY_ID, 5224 0, 0, pbn_wch382_2 }, 5225 5226 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5227 PCI_ANY_ID, PCI_ANY_ID, 5228 0, 0, pbn_wch384_4 }, 5229 5230 /* Fintek PCI serial cards */ 5231 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5232 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5233 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5234 5235 /* MKS Tenta SCOM-080x serial cards */ 5236 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5237 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5238 5239 /* Amazon PCI serial device */ 5240 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5241 5242 /* 5243 * These entries match devices with class COMMUNICATION_SERIAL, 5244 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5245 */ 5246 { PCI_ANY_ID, PCI_ANY_ID, 5247 PCI_ANY_ID, PCI_ANY_ID, 5248 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5249 0xffff00, pbn_default }, 5250 { PCI_ANY_ID, PCI_ANY_ID, 5251 PCI_ANY_ID, PCI_ANY_ID, 5252 PCI_CLASS_COMMUNICATION_MODEM << 8, 5253 0xffff00, pbn_default }, 5254 { PCI_ANY_ID, PCI_ANY_ID, 5255 PCI_ANY_ID, PCI_ANY_ID, 5256 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5257 0xffff00, pbn_default }, 5258 { 0, } 5259 }; 5260 5261 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5262 pci_channel_state_t state) 5263 { 5264 struct serial_private *priv = pci_get_drvdata(dev); 5265 5266 if (state == pci_channel_io_perm_failure) 5267 return PCI_ERS_RESULT_DISCONNECT; 5268 5269 if (priv) 5270 pciserial_detach_ports(priv); 5271 5272 pci_disable_device(dev); 5273 5274 return PCI_ERS_RESULT_NEED_RESET; 5275 } 5276 5277 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5278 { 5279 int rc; 5280 5281 rc = pci_enable_device(dev); 5282 5283 if (rc) 5284 return PCI_ERS_RESULT_DISCONNECT; 5285 5286 pci_restore_state(dev); 5287 pci_save_state(dev); 5288 5289 return PCI_ERS_RESULT_RECOVERED; 5290 } 5291 5292 static void serial8250_io_resume(struct pci_dev *dev) 5293 { 5294 struct serial_private *priv = pci_get_drvdata(dev); 5295 struct serial_private *new; 5296 5297 if (!priv) 5298 return; 5299 5300 new = pciserial_init_ports(dev, priv->board); 5301 if (!IS_ERR(new)) { 5302 pci_set_drvdata(dev, new); 5303 kfree(priv); 5304 } 5305 } 5306 5307 static const struct pci_error_handlers serial8250_err_handler = { 5308 .error_detected = serial8250_io_error_detected, 5309 .slot_reset = serial8250_io_slot_reset, 5310 .resume = serial8250_io_resume, 5311 }; 5312 5313 static struct pci_driver serial_pci_driver = { 5314 .name = "serial", 5315 .probe = pciserial_init_one, 5316 .remove = pciserial_remove_one, 5317 .driver = { 5318 .pm = &pciserial_pm_ops, 5319 }, 5320 .id_table = serial_pci_tbl, 5321 .err_handler = &serial8250_err_handler, 5322 }; 5323 5324 module_pci_driver(serial_pci_driver); 5325 5326 MODULE_LICENSE("GPL"); 5327 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5328 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5329