1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 #include "8250_pcilib.h" 28 29 /* 30 * init function returns: 31 * > 0 - number of ports 32 * = 0 - use board->num_ports 33 * < 0 - error 34 */ 35 struct pci_serial_quirk { 36 u32 vendor; 37 u32 device; 38 u32 subvendor; 39 u32 subdevice; 40 int (*probe)(struct pci_dev *dev); 41 int (*init)(struct pci_dev *dev); 42 int (*setup)(struct serial_private *, 43 const struct pciserial_board *, 44 struct uart_8250_port *, int); 45 void (*exit)(struct pci_dev *dev); 46 }; 47 48 struct f815xxa_data { 49 spinlock_t lock; 50 int idx; 51 }; 52 53 struct serial_private { 54 struct pci_dev *dev; 55 unsigned int nr; 56 struct pci_serial_quirk *quirk; 57 const struct pciserial_board *board; 58 int line[]; 59 }; 60 61 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 62 63 static const struct pci_device_id pci_use_msi[] = { 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 69 0xA000, 0x1000) }, 70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 71 PCI_ANY_ID, PCI_ANY_ID) }, 72 { } 73 }; 74 75 static int pci_default_setup(struct serial_private*, 76 const struct pciserial_board*, struct uart_8250_port *, int); 77 78 static void moan_device(const char *str, struct pci_dev *dev) 79 { 80 pci_err(dev, "%s\n" 81 "Please send the output of lspci -vv, this\n" 82 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 83 "manufacturer and name of serial board or\n" 84 "modem board to <linux-serial@vger.kernel.org>.\n", 85 str, dev->vendor, dev->device, 86 dev->subsystem_vendor, dev->subsystem_device); 87 } 88 89 static int 90 setup_port(struct serial_private *priv, struct uart_8250_port *port, 91 u8 bar, unsigned int offset, int regshift) 92 { 93 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 94 } 95 96 /* 97 * ADDI-DATA GmbH communication cards <info@addi-data.com> 98 */ 99 static int addidata_apci7800_setup(struct serial_private *priv, 100 const struct pciserial_board *board, 101 struct uart_8250_port *port, int idx) 102 { 103 unsigned int bar = 0, offset = board->first_offset; 104 bar = FL_GET_BASE(board->flags); 105 106 if (idx < 2) { 107 offset += idx * board->uart_offset; 108 } else if ((idx >= 2) && (idx < 4)) { 109 bar += 1; 110 offset += ((idx - 2) * board->uart_offset); 111 } else if ((idx >= 4) && (idx < 6)) { 112 bar += 2; 113 offset += ((idx - 4) * board->uart_offset); 114 } else if (idx >= 6) { 115 bar += 3; 116 offset += ((idx - 6) * board->uart_offset); 117 } 118 119 return setup_port(priv, port, bar, offset, board->reg_shift); 120 } 121 122 /* 123 * AFAVLAB uses a different mixture of BARs and offsets 124 * Not that ugly ;) -- HW 125 */ 126 static int 127 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 128 struct uart_8250_port *port, int idx) 129 { 130 unsigned int bar, offset = board->first_offset; 131 132 bar = FL_GET_BASE(board->flags); 133 if (idx < 4) 134 bar += idx; 135 else { 136 bar = 4; 137 offset += (idx - 4) * board->uart_offset; 138 } 139 140 return setup_port(priv, port, bar, offset, board->reg_shift); 141 } 142 143 /* 144 * HP's Remote Management Console. The Diva chip came in several 145 * different versions. N-class, L2000 and A500 have two Diva chips, each 146 * with 3 UARTs (the third UART on the second chip is unused). Superdome 147 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 148 * one Diva chip, but it has been expanded to 5 UARTs. 149 */ 150 static int pci_hp_diva_init(struct pci_dev *dev) 151 { 152 int rc = 0; 153 154 switch (dev->subsystem_device) { 155 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 156 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 157 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 158 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 159 rc = 3; 160 break; 161 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 162 rc = 2; 163 break; 164 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 165 rc = 4; 166 break; 167 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 168 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 169 rc = 1; 170 break; 171 } 172 173 return rc; 174 } 175 176 /* 177 * HP's Diva chip puts the 4th/5th serial port further out, and 178 * some serial ports are supposed to be hidden on certain models. 179 */ 180 static int 181 pci_hp_diva_setup(struct serial_private *priv, 182 const struct pciserial_board *board, 183 struct uart_8250_port *port, int idx) 184 { 185 unsigned int offset = board->first_offset; 186 unsigned int bar = FL_GET_BASE(board->flags); 187 188 switch (priv->dev->subsystem_device) { 189 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 190 if (idx == 3) 191 idx++; 192 break; 193 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 194 if (idx > 0) 195 idx++; 196 if (idx > 2) 197 idx++; 198 break; 199 } 200 if (idx > 2) 201 offset = 0x18; 202 203 offset += idx * board->uart_offset; 204 205 return setup_port(priv, port, bar, offset, board->reg_shift); 206 } 207 208 /* 209 * Added for EKF Intel i960 serial boards 210 */ 211 static int pci_inteli960ni_init(struct pci_dev *dev) 212 { 213 u32 oldval; 214 215 if (!(dev->subsystem_device & 0x1000)) 216 return -ENODEV; 217 218 /* is firmware started? */ 219 pci_read_config_dword(dev, 0x44, &oldval); 220 if (oldval == 0x00001000L) { /* RESET value */ 221 pci_dbg(dev, "Local i960 firmware missing\n"); 222 return -ENODEV; 223 } 224 return 0; 225 } 226 227 /* 228 * Some PCI serial cards using the PLX 9050 PCI interface chip require 229 * that the card interrupt be explicitly enabled or disabled. This 230 * seems to be mainly needed on card using the PLX which also use I/O 231 * mapped memory. 232 */ 233 static int pci_plx9050_init(struct pci_dev *dev) 234 { 235 u8 irq_config; 236 void __iomem *p; 237 238 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 239 moan_device("no memory in bar 0", dev); 240 return 0; 241 } 242 243 irq_config = 0x41; 244 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 245 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 246 irq_config = 0x43; 247 248 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 249 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 250 /* 251 * As the megawolf cards have the int pins active 252 * high, and have 2 UART chips, both ints must be 253 * enabled on the 9050. Also, the UARTS are set in 254 * 16450 mode by default, so we have to enable the 255 * 16C950 'enhanced' mode so that we can use the 256 * deep FIFOs 257 */ 258 irq_config = 0x5b; 259 /* 260 * enable/disable interrupts 261 */ 262 p = ioremap(pci_resource_start(dev, 0), 0x80); 263 if (p == NULL) 264 return -ENOMEM; 265 writel(irq_config, p + 0x4c); 266 267 /* 268 * Read the register back to ensure that it took effect. 269 */ 270 readl(p + 0x4c); 271 iounmap(p); 272 273 return 0; 274 } 275 276 static void pci_plx9050_exit(struct pci_dev *dev) 277 { 278 u8 __iomem *p; 279 280 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 281 return; 282 283 /* 284 * disable interrupts 285 */ 286 p = ioremap(pci_resource_start(dev, 0), 0x80); 287 if (p != NULL) { 288 writel(0, p + 0x4c); 289 290 /* 291 * Read the register back to ensure that it took effect. 292 */ 293 readl(p + 0x4c); 294 iounmap(p); 295 } 296 } 297 298 #define NI8420_INT_ENABLE_REG 0x38 299 #define NI8420_INT_ENABLE_BIT 0x2000 300 301 static void pci_ni8420_exit(struct pci_dev *dev) 302 { 303 void __iomem *p; 304 unsigned int bar = 0; 305 306 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 307 moan_device("no memory in bar", dev); 308 return; 309 } 310 311 p = pci_ioremap_bar(dev, bar); 312 if (p == NULL) 313 return; 314 315 /* Disable the CPU Interrupt */ 316 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 317 p + NI8420_INT_ENABLE_REG); 318 iounmap(p); 319 } 320 321 322 /* MITE registers */ 323 #define MITE_IOWBSR1 0xc4 324 #define MITE_IOWCR1 0xf4 325 #define MITE_LCIMR1 0x08 326 #define MITE_LCIMR2 0x10 327 328 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 329 330 static void pci_ni8430_exit(struct pci_dev *dev) 331 { 332 void __iomem *p; 333 unsigned int bar = 0; 334 335 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 336 moan_device("no memory in bar", dev); 337 return; 338 } 339 340 p = pci_ioremap_bar(dev, bar); 341 if (p == NULL) 342 return; 343 344 /* Disable the CPU Interrupt */ 345 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 346 iounmap(p); 347 } 348 349 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 350 static int 351 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 352 struct uart_8250_port *port, int idx) 353 { 354 unsigned int bar, offset = board->first_offset; 355 356 bar = 0; 357 358 if (idx < 4) { 359 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 360 offset += idx * board->uart_offset; 361 } else if (idx < 8) { 362 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 363 offset += idx * board->uart_offset + 0xC00; 364 } else /* we have only 8 ports on PMC-OCTALPRO */ 365 return 1; 366 367 return setup_port(priv, port, bar, offset, board->reg_shift); 368 } 369 370 /* 371 * This does initialization for PMC OCTALPRO cards: 372 * maps the device memory, resets the UARTs (needed, bc 373 * if the module is removed and inserted again, the card 374 * is in the sleep mode) and enables global interrupt. 375 */ 376 377 /* global control register offset for SBS PMC-OctalPro */ 378 #define OCT_REG_CR_OFF 0x500 379 380 static int sbs_init(struct pci_dev *dev) 381 { 382 u8 __iomem *p; 383 384 p = pci_ioremap_bar(dev, 0); 385 386 if (p == NULL) 387 return -ENOMEM; 388 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 389 writeb(0x10, p + OCT_REG_CR_OFF); 390 udelay(50); 391 writeb(0x0, p + OCT_REG_CR_OFF); 392 393 /* Set bit-2 (INTENABLE) of Control Register */ 394 writeb(0x4, p + OCT_REG_CR_OFF); 395 iounmap(p); 396 397 return 0; 398 } 399 400 /* 401 * Disables the global interrupt of PMC-OctalPro 402 */ 403 404 static void sbs_exit(struct pci_dev *dev) 405 { 406 u8 __iomem *p; 407 408 p = pci_ioremap_bar(dev, 0); 409 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 410 if (p != NULL) 411 writeb(0, p + OCT_REG_CR_OFF); 412 iounmap(p); 413 } 414 415 /* 416 * SIIG serial cards have an PCI interface chip which also controls 417 * the UART clocking frequency. Each UART can be clocked independently 418 * (except cards equipped with 4 UARTs) and initial clocking settings 419 * are stored in the EEPROM chip. It can cause problems because this 420 * version of serial driver doesn't support differently clocked UART's 421 * on single PCI card. To prevent this, initialization functions set 422 * high frequency clocking for all UART's on given card. It is safe (I 423 * hope) because it doesn't touch EEPROM settings to prevent conflicts 424 * with other OSes (like M$ DOS). 425 * 426 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 427 * 428 * There is two family of SIIG serial cards with different PCI 429 * interface chip and different configuration methods: 430 * - 10x cards have control registers in IO and/or memory space; 431 * - 20x cards have control registers in standard PCI configuration space. 432 * 433 * Note: all 10x cards have PCI device ids 0x10.. 434 * all 20x cards have PCI device ids 0x20.. 435 * 436 * There are also Quartet Serial cards which use Oxford Semiconductor 437 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 438 * 439 * Note: some SIIG cards are probed by the parport_serial object. 440 */ 441 442 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 443 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 444 445 static int pci_siig10x_init(struct pci_dev *dev) 446 { 447 u16 data; 448 void __iomem *p; 449 450 switch (dev->device & 0xfff8) { 451 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 452 data = 0xffdf; 453 break; 454 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 455 data = 0xf7ff; 456 break; 457 default: /* 1S1P, 4S */ 458 data = 0xfffb; 459 break; 460 } 461 462 p = ioremap(pci_resource_start(dev, 0), 0x80); 463 if (p == NULL) 464 return -ENOMEM; 465 466 writew(readw(p + 0x28) & data, p + 0x28); 467 readw(p + 0x28); 468 iounmap(p); 469 return 0; 470 } 471 472 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 473 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 474 475 static int pci_siig20x_init(struct pci_dev *dev) 476 { 477 u8 data; 478 479 /* Change clock frequency for the first UART. */ 480 pci_read_config_byte(dev, 0x6f, &data); 481 pci_write_config_byte(dev, 0x6f, data & 0xef); 482 483 /* If this card has 2 UART, we have to do the same with second UART. */ 484 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 485 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 486 pci_read_config_byte(dev, 0x73, &data); 487 pci_write_config_byte(dev, 0x73, data & 0xef); 488 } 489 return 0; 490 } 491 492 static int pci_siig_init(struct pci_dev *dev) 493 { 494 unsigned int type = dev->device & 0xff00; 495 496 if (type == 0x1000) 497 return pci_siig10x_init(dev); 498 if (type == 0x2000) 499 return pci_siig20x_init(dev); 500 501 moan_device("Unknown SIIG card", dev); 502 return -ENODEV; 503 } 504 505 static int pci_siig_setup(struct serial_private *priv, 506 const struct pciserial_board *board, 507 struct uart_8250_port *port, int idx) 508 { 509 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 510 511 if (idx > 3) { 512 bar = 4; 513 offset = (idx - 4) * 8; 514 } 515 516 return setup_port(priv, port, bar, offset, 0); 517 } 518 519 /* 520 * Timedia has an explosion of boards, and to avoid the PCI table from 521 * growing *huge*, we use this function to collapse some 70 entries 522 * in the PCI table into one, for sanity's and compactness's sake. 523 */ 524 static const unsigned short timedia_single_port[] = { 525 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 526 }; 527 528 static const unsigned short timedia_dual_port[] = { 529 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 530 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 531 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 532 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 533 0xD079, 0 534 }; 535 536 static const unsigned short timedia_quad_port[] = { 537 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 538 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 539 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 540 0xB157, 0 541 }; 542 543 static const unsigned short timedia_eight_port[] = { 544 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 545 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 546 }; 547 548 static const struct timedia_struct { 549 int num; 550 const unsigned short *ids; 551 } timedia_data[] = { 552 { 1, timedia_single_port }, 553 { 2, timedia_dual_port }, 554 { 4, timedia_quad_port }, 555 { 8, timedia_eight_port } 556 }; 557 558 /* 559 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 560 * listing them individually, this driver merely grabs them all with 561 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 562 * and should be left free to be claimed by parport_serial instead. 563 */ 564 static int pci_timedia_probe(struct pci_dev *dev) 565 { 566 /* 567 * Check the third digit of the subdevice ID 568 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 569 */ 570 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 571 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 572 dev->subsystem_device); 573 return -ENODEV; 574 } 575 576 return 0; 577 } 578 579 static int pci_timedia_init(struct pci_dev *dev) 580 { 581 const unsigned short *ids; 582 int i, j; 583 584 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 585 ids = timedia_data[i].ids; 586 for (j = 0; ids[j]; j++) 587 if (dev->subsystem_device == ids[j]) 588 return timedia_data[i].num; 589 } 590 return 0; 591 } 592 593 /* 594 * Timedia/SUNIX uses a mixture of BARs and offsets 595 * Ugh, this is ugly as all hell --- TYT 596 */ 597 static int 598 pci_timedia_setup(struct serial_private *priv, 599 const struct pciserial_board *board, 600 struct uart_8250_port *port, int idx) 601 { 602 unsigned int bar = 0, offset = board->first_offset; 603 604 switch (idx) { 605 case 0: 606 bar = 0; 607 break; 608 case 1: 609 offset = board->uart_offset; 610 bar = 0; 611 break; 612 case 2: 613 bar = 1; 614 break; 615 case 3: 616 offset = board->uart_offset; 617 fallthrough; 618 case 4: /* BAR 2 */ 619 case 5: /* BAR 3 */ 620 case 6: /* BAR 4 */ 621 case 7: /* BAR 5 */ 622 bar = idx - 2; 623 } 624 625 return setup_port(priv, port, bar, offset, board->reg_shift); 626 } 627 628 /* 629 * Some Titan cards are also a little weird 630 */ 631 static int 632 titan_400l_800l_setup(struct serial_private *priv, 633 const struct pciserial_board *board, 634 struct uart_8250_port *port, int idx) 635 { 636 unsigned int bar, offset = board->first_offset; 637 638 switch (idx) { 639 case 0: 640 bar = 1; 641 break; 642 case 1: 643 bar = 2; 644 break; 645 default: 646 bar = 4; 647 offset = (idx - 2) * board->uart_offset; 648 } 649 650 return setup_port(priv, port, bar, offset, board->reg_shift); 651 } 652 653 static int pci_xircom_init(struct pci_dev *dev) 654 { 655 msleep(100); 656 return 0; 657 } 658 659 static int pci_ni8420_init(struct pci_dev *dev) 660 { 661 void __iomem *p; 662 unsigned int bar = 0; 663 664 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 665 moan_device("no memory in bar", dev); 666 return 0; 667 } 668 669 p = pci_ioremap_bar(dev, bar); 670 if (p == NULL) 671 return -ENOMEM; 672 673 /* Enable CPU Interrupt */ 674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 675 p + NI8420_INT_ENABLE_REG); 676 677 iounmap(p); 678 return 0; 679 } 680 681 #define MITE_IOWBSR1_WSIZE 0xa 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800 683 #define MITE_IOWBSR1_WENAB (1 << 7) 684 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 687 688 static int pci_ni8430_init(struct pci_dev *dev) 689 { 690 void __iomem *p; 691 struct pci_bus_region region; 692 u32 device_window; 693 unsigned int bar = 0; 694 695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 696 moan_device("no memory in bar", dev); 697 return 0; 698 } 699 700 p = pci_ioremap_bar(dev, bar); 701 if (p == NULL) 702 return -ENOMEM; 703 704 /* 705 * Set device window address and size in BAR0, while acknowledging that 706 * the resource structure may contain a translated address that differs 707 * from the address the device responds to. 708 */ 709 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 710 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 711 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 712 writel(device_window, p + MITE_IOWBSR1); 713 714 /* Set window access to go to RAMSEL IO address space */ 715 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 716 p + MITE_IOWCR1); 717 718 /* Enable IO Bus Interrupt 0 */ 719 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 720 721 /* Enable CPU Interrupt */ 722 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 723 724 iounmap(p); 725 return 0; 726 } 727 728 /* UART Port Control Register */ 729 #define NI8430_PORTCON 0x0f 730 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 731 732 static int 733 pci_ni8430_setup(struct serial_private *priv, 734 const struct pciserial_board *board, 735 struct uart_8250_port *port, int idx) 736 { 737 struct pci_dev *dev = priv->dev; 738 void __iomem *p; 739 unsigned int bar, offset = board->first_offset; 740 741 if (idx >= board->num_ports) 742 return 1; 743 744 bar = FL_GET_BASE(board->flags); 745 offset += idx * board->uart_offset; 746 747 p = pci_ioremap_bar(dev, bar); 748 if (!p) 749 return -ENOMEM; 750 751 /* enable the transceiver */ 752 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 753 p + offset + NI8430_PORTCON); 754 755 iounmap(p); 756 757 return setup_port(priv, port, bar, offset, board->reg_shift); 758 } 759 760 static int pci_netmos_9900_setup(struct serial_private *priv, 761 const struct pciserial_board *board, 762 struct uart_8250_port *port, int idx) 763 { 764 unsigned int bar; 765 766 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 767 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 768 /* netmos apparently orders BARs by datasheet layout, so serial 769 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 770 */ 771 bar = 3 * idx; 772 773 return setup_port(priv, port, bar, 0, board->reg_shift); 774 } 775 776 return pci_default_setup(priv, board, port, idx); 777 } 778 779 /* the 99xx series comes with a range of device IDs and a variety 780 * of capabilities: 781 * 782 * 9900 has varying capabilities and can cascade to sub-controllers 783 * (cascading should be purely internal) 784 * 9904 is hardwired with 4 serial ports 785 * 9912 and 9922 are hardwired with 2 serial ports 786 */ 787 static int pci_netmos_9900_numports(struct pci_dev *dev) 788 { 789 unsigned int c = dev->class; 790 unsigned int pi; 791 unsigned short sub_serports; 792 793 pi = c & 0xff; 794 795 if (pi == 2) 796 return 1; 797 798 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 799 /* two possibilities: 0x30ps encodes number of parallel and 800 * serial ports, or 0x1000 indicates *something*. This is not 801 * immediately obvious, since the 2s1p+4s configuration seems 802 * to offer all functionality on functions 0..2, while still 803 * advertising the same function 3 as the 4s+2s1p config. 804 */ 805 sub_serports = dev->subsystem_device & 0xf; 806 if (sub_serports > 0) 807 return sub_serports; 808 809 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 810 return 0; 811 } 812 813 moan_device("unknown NetMos/Mostech program interface", dev); 814 return 0; 815 } 816 817 static int pci_netmos_init(struct pci_dev *dev) 818 { 819 /* subdevice 0x00PS means <P> parallel, <S> serial */ 820 unsigned int num_serial = dev->subsystem_device & 0xf; 821 822 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 823 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 824 return 0; 825 826 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 827 dev->subsystem_device == 0x0299) 828 return 0; 829 830 switch (dev->device) { /* FALLTHROUGH on all */ 831 case PCI_DEVICE_ID_NETMOS_9904: 832 case PCI_DEVICE_ID_NETMOS_9912: 833 case PCI_DEVICE_ID_NETMOS_9922: 834 case PCI_DEVICE_ID_NETMOS_9900: 835 num_serial = pci_netmos_9900_numports(dev); 836 break; 837 838 default: 839 break; 840 } 841 842 if (num_serial == 0) { 843 moan_device("unknown NetMos/Mostech device", dev); 844 return -ENODEV; 845 } 846 847 return num_serial; 848 } 849 850 /* 851 * These chips are available with optionally one parallel port and up to 852 * two serial ports. Unfortunately they all have the same product id. 853 * 854 * Basic configuration is done over a region of 32 I/O ports. The base 855 * ioport is called INTA or INTC, depending on docs/other drivers. 856 * 857 * The region of the 32 I/O ports is configured in POSIO0R... 858 */ 859 860 /* registers */ 861 #define ITE_887x_MISCR 0x9c 862 #define ITE_887x_INTCBAR 0x78 863 #define ITE_887x_UARTBAR 0x7c 864 #define ITE_887x_PS0BAR 0x10 865 #define ITE_887x_POSIO0 0x60 866 867 /* I/O space size */ 868 #define ITE_887x_IOSIZE 32 869 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 870 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 871 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 872 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 873 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 874 #define ITE_887x_POSIO_SPEED (3 << 29) 875 /* enable IO_Space bit */ 876 #define ITE_887x_POSIO_ENABLE (1 << 31) 877 878 /* inta_addr are the configuration addresses of the ITE */ 879 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 880 static int pci_ite887x_init(struct pci_dev *dev) 881 { 882 int ret, i, type; 883 struct resource *iobase = NULL; 884 u32 miscr, uartbar, ioport; 885 886 /* search for the base-ioport */ 887 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 888 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 889 "ite887x"); 890 if (iobase != NULL) { 891 /* write POSIO0R - speed | size | ioport */ 892 pci_write_config_dword(dev, ITE_887x_POSIO0, 893 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 894 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 895 /* write INTCBAR - ioport */ 896 pci_write_config_dword(dev, ITE_887x_INTCBAR, 897 inta_addr[i]); 898 ret = inb(inta_addr[i]); 899 if (ret != 0xff) { 900 /* ioport connected */ 901 break; 902 } 903 release_region(iobase->start, ITE_887x_IOSIZE); 904 } 905 } 906 907 if (i == ARRAY_SIZE(inta_addr)) { 908 pci_err(dev, "could not find iobase\n"); 909 return -ENODEV; 910 } 911 912 /* start of undocumented type checking (see parport_pc.c) */ 913 type = inb(iobase->start + 0x18) & 0x0f; 914 915 switch (type) { 916 case 0x2: /* ITE8871 (1P) */ 917 case 0xa: /* ITE8875 (1P) */ 918 ret = 0; 919 break; 920 case 0xe: /* ITE8872 (2S1P) */ 921 ret = 2; 922 break; 923 case 0x6: /* ITE8873 (1S) */ 924 ret = 1; 925 break; 926 case 0x8: /* ITE8874 (2S) */ 927 ret = 2; 928 break; 929 default: 930 moan_device("Unknown ITE887x", dev); 931 ret = -ENODEV; 932 } 933 934 /* configure all serial ports */ 935 for (i = 0; i < ret; i++) { 936 /* read the I/O port from the device */ 937 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 938 &ioport); 939 ioport &= 0x0000FF00; /* the actual base address */ 940 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 941 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 942 ITE_887x_POSIO_IOSIZE_8 | ioport); 943 944 /* write the ioport to the UARTBAR */ 945 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 946 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 947 uartbar |= (ioport << (16 * i)); /* set the ioport */ 948 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 949 950 /* get current config */ 951 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 952 /* disable interrupts (UARTx_Routing[3:0]) */ 953 miscr &= ~(0xf << (12 - 4 * i)); 954 /* activate the UART (UARTx_En) */ 955 miscr |= 1 << (23 - i); 956 /* write new config with activated UART */ 957 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 958 } 959 960 if (ret <= 0) { 961 /* the device has no UARTs if we get here */ 962 release_region(iobase->start, ITE_887x_IOSIZE); 963 } 964 965 return ret; 966 } 967 968 static void pci_ite887x_exit(struct pci_dev *dev) 969 { 970 u32 ioport; 971 /* the ioport is bit 0-15 in POSIO0R */ 972 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 973 ioport &= 0xffff; 974 release_region(ioport, ITE_887x_IOSIZE); 975 } 976 977 /* 978 * Oxford Semiconductor Inc. 979 * Check if an OxSemi device is part of the Tornado range of devices. 980 */ 981 #define PCI_VENDOR_ID_ENDRUN 0x7401 982 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 983 984 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 985 { 986 /* OxSemi Tornado devices are all 0xCxxx */ 987 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 988 (dev->device & 0xf000) != 0xc000) 989 return false; 990 991 /* EndRun devices are all 0xExxx */ 992 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 993 (dev->device & 0xf000) != 0xe000) 994 return false; 995 996 return true; 997 } 998 999 /* 1000 * Determine the number of ports available on a Tornado device. 1001 */ 1002 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1003 { 1004 u8 __iomem *p; 1005 unsigned long deviceID; 1006 unsigned int number_uarts = 0; 1007 1008 if (!pci_oxsemi_tornado_p(dev)) 1009 return 0; 1010 1011 p = pci_iomap(dev, 0, 5); 1012 if (p == NULL) 1013 return -ENOMEM; 1014 1015 deviceID = ioread32(p); 1016 /* Tornado device */ 1017 if (deviceID == 0x07000200) { 1018 number_uarts = ioread8(p + 4); 1019 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1020 number_uarts, 1021 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1022 "EndRun" : "Oxford"); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1029 #define OXSEMI_TORNADO_TCR_MASK 0xf 1030 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1031 #define OXSEMI_TORNADO_CPR_MIN 0x008 1032 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1033 1034 /* 1035 * Determine the oversampling rate, the clock prescaler, and the clock 1036 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1037 * which is four times the baud base, and the prescaler increments in 1038 * steps of 1/8. Therefore to make calculations on integers we need 1039 * to use a scaled clock rate, which is the baud base multiplied by 32 1040 * (or our assumed UART clock rate multiplied by 2). 1041 * 1042 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1043 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1044 * values between 1.000 and 63.875 inclusive (operation for values from 1045 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1046 * unsigned 16-bit integer. 1047 * 1048 * For the most accurate baud rate we use a table of predetermined 1049 * oversampling rates and clock prescalers that records all possible 1050 * products of the two parameters in the range from 4 up to 255 inclusive, 1051 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1052 * by 8. The table is sorted by the decreasing value of the oversampling 1053 * rate and ties are resolved by sorting by the decreasing value of the 1054 * product. This way preference is given to higher oversampling rates. 1055 * 1056 * We iterate over the table and choose the product of an oversampling 1057 * rate and a clock prescaler that gives the lowest integer division 1058 * result deviation, or if an exact integer divider is found we stop 1059 * looking for it right away. We do some fixup if the resulting clock 1060 * divisor required would be out of its unsigned 16-bit integer range. 1061 * 1062 * Finally we abuse the supposed fractional part returned to encode the 1063 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1064 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1065 */ 1066 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1067 unsigned int baud, 1068 unsigned int *frac) 1069 { 1070 static u8 p[][2] = { 1071 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1072 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1073 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1074 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1075 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1076 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1077 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1078 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1079 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1080 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1081 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1082 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1083 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1084 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1085 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1086 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1087 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1088 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1089 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1090 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1091 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1092 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1093 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1094 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1095 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1096 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1097 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1098 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1099 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1100 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1101 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1102 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1103 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1104 { 4, 9, }, { 4, 8, }, 1105 }; 1106 /* Scale the quotient for comparison to get the fractional part. */ 1107 const unsigned int quot_scale = 65536; 1108 unsigned int sclk = port->uartclk * 2; 1109 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1110 unsigned int best_squot; 1111 unsigned int squot; 1112 unsigned int quot; 1113 u16 cpr; 1114 u8 tcr; 1115 int i; 1116 1117 /* Old custom speed handling. */ 1118 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1119 unsigned int cust_div = port->custom_divisor; 1120 1121 quot = cust_div & UART_DIV_MAX; 1122 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1123 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1124 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1125 cpr = OXSEMI_TORNADO_CPR_DEF; 1126 } else { 1127 best_squot = quot_scale; 1128 for (i = 0; i < ARRAY_SIZE(p); i++) { 1129 unsigned int spre; 1130 unsigned int srem; 1131 u8 cp; 1132 u8 tc; 1133 1134 tc = p[i][0]; 1135 cp = p[i][1]; 1136 spre = tc * cp; 1137 1138 srem = sdiv % spre; 1139 if (srem > spre / 2) 1140 srem = spre - srem; 1141 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1142 1143 if (srem == 0) { 1144 tcr = tc; 1145 cpr = cp; 1146 quot = sdiv / spre; 1147 break; 1148 } else if (squot < best_squot) { 1149 best_squot = squot; 1150 tcr = tc; 1151 cpr = cp; 1152 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1153 } 1154 } 1155 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1156 quot % 2 == 0) { 1157 quot >>= 1; 1158 tcr <<= 1; 1159 } 1160 while (quot > UART_DIV_MAX) { 1161 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1162 quot >>= 1; 1163 tcr <<= 1; 1164 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1165 quot >>= 1; 1166 cpr <<= 1; 1167 } else { 1168 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1169 cpr = OXSEMI_TORNADO_CPR_MASK; 1170 } 1171 } 1172 } 1173 1174 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1175 return quot; 1176 } 1177 1178 /* 1179 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1180 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1181 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1182 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1183 * has to be written first, followed by CPR2, which occupies the location 1184 * of CKS used with earlier UART designs. 1185 */ 1186 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1187 unsigned int baud, 1188 unsigned int quot, 1189 unsigned int quot_frac) 1190 { 1191 struct uart_8250_port *up = up_to_u8250p(port); 1192 u8 cpr2 = quot_frac >> 16; 1193 u8 cpr = quot_frac >> 8; 1194 u8 tcr = quot_frac; 1195 1196 serial_icr_write(up, UART_TCR, tcr); 1197 serial_icr_write(up, UART_CPR, cpr); 1198 serial_icr_write(up, UART_CKS, cpr2); 1199 serial8250_do_set_divisor(port, baud, quot, 0); 1200 } 1201 1202 /* 1203 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1204 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1205 */ 1206 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1207 unsigned int mctrl) 1208 { 1209 struct uart_8250_port *up = up_to_u8250p(port); 1210 1211 up->mcr |= UART_MCR_CLKSEL; 1212 serial8250_do_set_mctrl(port, mctrl); 1213 } 1214 1215 /* 1216 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1217 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1218 */ 1219 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1220 const struct pciserial_board *board, 1221 struct uart_8250_port *up, int idx) 1222 { 1223 struct pci_dev *dev = priv->dev; 1224 1225 if (pci_oxsemi_tornado_p(dev)) { 1226 up->port.flags |= UPF_FULL_PROBE; 1227 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1228 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1229 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1230 } 1231 1232 return pci_default_setup(priv, board, up, idx); 1233 } 1234 1235 #define QPCR_TEST_FOR1 0x3F 1236 #define QPCR_TEST_GET1 0x00 1237 #define QPCR_TEST_FOR2 0x40 1238 #define QPCR_TEST_GET2 0x40 1239 #define QPCR_TEST_FOR3 0x80 1240 #define QPCR_TEST_GET3 0x40 1241 #define QPCR_TEST_FOR4 0xC0 1242 #define QPCR_TEST_GET4 0x80 1243 1244 #define QOPR_CLOCK_X1 0x0000 1245 #define QOPR_CLOCK_X2 0x0001 1246 #define QOPR_CLOCK_X4 0x0002 1247 #define QOPR_CLOCK_X8 0x0003 1248 #define QOPR_CLOCK_RATE_MASK 0x0003 1249 1250 /* Quatech devices have their own extra interface features */ 1251 static struct pci_device_id quatech_cards[] = { 1252 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1253 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1254 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1255 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1256 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1257 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1258 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1259 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1260 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1261 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1262 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1263 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1264 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1265 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1266 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1267 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1268 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1269 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1270 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1271 { 0, } 1272 }; 1273 1274 static int pci_quatech_rqopr(struct uart_8250_port *port) 1275 { 1276 unsigned long base = port->port.iobase; 1277 u8 LCR, val; 1278 1279 LCR = inb(base + UART_LCR); 1280 outb(0xBF, base + UART_LCR); 1281 val = inb(base + UART_SCR); 1282 outb(LCR, base + UART_LCR); 1283 return val; 1284 } 1285 1286 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1287 { 1288 unsigned long base = port->port.iobase; 1289 u8 LCR; 1290 1291 LCR = inb(base + UART_LCR); 1292 outb(0xBF, base + UART_LCR); 1293 inb(base + UART_SCR); 1294 outb(qopr, base + UART_SCR); 1295 outb(LCR, base + UART_LCR); 1296 } 1297 1298 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1299 { 1300 unsigned long base = port->port.iobase; 1301 u8 LCR, val, qmcr; 1302 1303 LCR = inb(base + UART_LCR); 1304 outb(0xBF, base + UART_LCR); 1305 val = inb(base + UART_SCR); 1306 outb(val | 0x10, base + UART_SCR); 1307 qmcr = inb(base + UART_MCR); 1308 outb(val, base + UART_SCR); 1309 outb(LCR, base + UART_LCR); 1310 1311 return qmcr; 1312 } 1313 1314 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1315 { 1316 unsigned long base = port->port.iobase; 1317 u8 LCR, val; 1318 1319 LCR = inb(base + UART_LCR); 1320 outb(0xBF, base + UART_LCR); 1321 val = inb(base + UART_SCR); 1322 outb(val | 0x10, base + UART_SCR); 1323 outb(qmcr, base + UART_MCR); 1324 outb(val, base + UART_SCR); 1325 outb(LCR, base + UART_LCR); 1326 } 1327 1328 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1329 { 1330 unsigned long base = port->port.iobase; 1331 u8 LCR, val; 1332 1333 LCR = inb(base + UART_LCR); 1334 outb(0xBF, base + UART_LCR); 1335 val = inb(base + UART_SCR); 1336 if (val & 0x20) { 1337 outb(0x80, UART_LCR); 1338 if (!(inb(UART_SCR) & 0x20)) { 1339 outb(LCR, base + UART_LCR); 1340 return 1; 1341 } 1342 } 1343 return 0; 1344 } 1345 1346 static int pci_quatech_test(struct uart_8250_port *port) 1347 { 1348 u8 reg, qopr; 1349 1350 qopr = pci_quatech_rqopr(port); 1351 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1352 reg = pci_quatech_rqopr(port) & 0xC0; 1353 if (reg != QPCR_TEST_GET1) 1354 return -EINVAL; 1355 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1356 reg = pci_quatech_rqopr(port) & 0xC0; 1357 if (reg != QPCR_TEST_GET2) 1358 return -EINVAL; 1359 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1360 reg = pci_quatech_rqopr(port) & 0xC0; 1361 if (reg != QPCR_TEST_GET3) 1362 return -EINVAL; 1363 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1364 reg = pci_quatech_rqopr(port) & 0xC0; 1365 if (reg != QPCR_TEST_GET4) 1366 return -EINVAL; 1367 1368 pci_quatech_wqopr(port, qopr); 1369 return 0; 1370 } 1371 1372 static int pci_quatech_clock(struct uart_8250_port *port) 1373 { 1374 u8 qopr, reg, set; 1375 unsigned long clock; 1376 1377 if (pci_quatech_test(port) < 0) 1378 return 1843200; 1379 1380 qopr = pci_quatech_rqopr(port); 1381 1382 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1383 reg = pci_quatech_rqopr(port); 1384 if (reg & QOPR_CLOCK_X8) { 1385 clock = 1843200; 1386 goto out; 1387 } 1388 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1389 reg = pci_quatech_rqopr(port); 1390 if (!(reg & QOPR_CLOCK_X8)) { 1391 clock = 1843200; 1392 goto out; 1393 } 1394 reg &= QOPR_CLOCK_X8; 1395 if (reg == QOPR_CLOCK_X2) { 1396 clock = 3685400; 1397 set = QOPR_CLOCK_X2; 1398 } else if (reg == QOPR_CLOCK_X4) { 1399 clock = 7372800; 1400 set = QOPR_CLOCK_X4; 1401 } else if (reg == QOPR_CLOCK_X8) { 1402 clock = 14745600; 1403 set = QOPR_CLOCK_X8; 1404 } else { 1405 clock = 1843200; 1406 set = QOPR_CLOCK_X1; 1407 } 1408 qopr &= ~QOPR_CLOCK_RATE_MASK; 1409 qopr |= set; 1410 1411 out: 1412 pci_quatech_wqopr(port, qopr); 1413 return clock; 1414 } 1415 1416 static int pci_quatech_rs422(struct uart_8250_port *port) 1417 { 1418 u8 qmcr; 1419 int rs422 = 0; 1420 1421 if (!pci_quatech_has_qmcr(port)) 1422 return 0; 1423 qmcr = pci_quatech_rqmcr(port); 1424 pci_quatech_wqmcr(port, 0xFF); 1425 if (pci_quatech_rqmcr(port)) 1426 rs422 = 1; 1427 pci_quatech_wqmcr(port, qmcr); 1428 return rs422; 1429 } 1430 1431 static int pci_quatech_init(struct pci_dev *dev) 1432 { 1433 const struct pci_device_id *match; 1434 bool amcc = false; 1435 1436 match = pci_match_id(quatech_cards, dev); 1437 if (match) 1438 amcc = match->driver_data; 1439 else 1440 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1441 1442 if (amcc) { 1443 unsigned long base = pci_resource_start(dev, 0); 1444 if (base) { 1445 u32 tmp; 1446 1447 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1448 tmp = inl(base + 0x3c); 1449 outl(tmp | 0x01000000, base + 0x3c); 1450 outl(tmp & ~0x01000000, base + 0x3c); 1451 } 1452 } 1453 return 0; 1454 } 1455 1456 static int pci_quatech_setup(struct serial_private *priv, 1457 const struct pciserial_board *board, 1458 struct uart_8250_port *port, int idx) 1459 { 1460 /* Needed by pci_quatech calls below */ 1461 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1462 /* Set up the clocking */ 1463 port->port.uartclk = pci_quatech_clock(port); 1464 /* For now just warn about RS422 */ 1465 if (pci_quatech_rs422(port)) 1466 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1467 return pci_default_setup(priv, board, port, idx); 1468 } 1469 1470 static int pci_default_setup(struct serial_private *priv, 1471 const struct pciserial_board *board, 1472 struct uart_8250_port *port, int idx) 1473 { 1474 unsigned int bar, offset = board->first_offset, maxnr; 1475 1476 bar = FL_GET_BASE(board->flags); 1477 if (board->flags & FL_BASE_BARS) 1478 bar += idx; 1479 else 1480 offset += idx * board->uart_offset; 1481 1482 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1483 (board->reg_shift + 3); 1484 1485 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1486 return 1; 1487 1488 return setup_port(priv, port, bar, offset, board->reg_shift); 1489 } 1490 1491 static int 1492 ce4100_serial_setup(struct serial_private *priv, 1493 const struct pciserial_board *board, 1494 struct uart_8250_port *port, int idx) 1495 { 1496 int ret; 1497 1498 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1499 port->port.iotype = UPIO_MEM32; 1500 port->port.type = PORT_XSCALE; 1501 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1502 port->port.regshift = 2; 1503 1504 return ret; 1505 } 1506 1507 static int 1508 pci_omegapci_setup(struct serial_private *priv, 1509 const struct pciserial_board *board, 1510 struct uart_8250_port *port, int idx) 1511 { 1512 return setup_port(priv, port, 2, idx * 8, 0); 1513 } 1514 1515 static int 1516 pci_brcm_trumanage_setup(struct serial_private *priv, 1517 const struct pciserial_board *board, 1518 struct uart_8250_port *port, int idx) 1519 { 1520 int ret = pci_default_setup(priv, board, port, idx); 1521 1522 port->port.type = PORT_BRCM_TRUMANAGE; 1523 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1524 return ret; 1525 } 1526 1527 /* RTS will control by MCR if this bit is 0 */ 1528 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1529 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1530 #define FINTEK_RTS_INVERT BIT(5) 1531 1532 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1533 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1534 struct serial_rs485 *rs485) 1535 { 1536 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1537 u8 setting; 1538 u8 *index = (u8 *) port->private_data; 1539 1540 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1541 1542 if (rs485->flags & SER_RS485_ENABLED) { 1543 /* Enable RTS H/W control mode */ 1544 setting |= FINTEK_RTS_CONTROL_BY_HW; 1545 1546 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1547 /* RTS driving high on TX */ 1548 setting &= ~FINTEK_RTS_INVERT; 1549 } else { 1550 /* RTS driving low on TX */ 1551 setting |= FINTEK_RTS_INVERT; 1552 } 1553 } else { 1554 /* Disable RTS H/W control mode */ 1555 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1556 } 1557 1558 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1559 1560 return 0; 1561 } 1562 1563 static const struct serial_rs485 pci_fintek_rs485_supported = { 1564 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1565 /* F81504/508/512 does not support RTS delay before or after send */ 1566 }; 1567 1568 static int pci_fintek_setup(struct serial_private *priv, 1569 const struct pciserial_board *board, 1570 struct uart_8250_port *port, int idx) 1571 { 1572 struct pci_dev *pdev = priv->dev; 1573 u8 *data; 1574 u8 config_base; 1575 u16 iobase; 1576 1577 config_base = 0x40 + 0x08 * idx; 1578 1579 /* Get the io address from configuration space */ 1580 pci_read_config_word(pdev, config_base + 4, &iobase); 1581 1582 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1583 1584 port->port.iotype = UPIO_PORT; 1585 port->port.iobase = iobase; 1586 port->port.rs485_config = pci_fintek_rs485_config; 1587 port->port.rs485_supported = pci_fintek_rs485_supported; 1588 1589 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1590 if (!data) 1591 return -ENOMEM; 1592 1593 /* preserve index in PCI configuration space */ 1594 *data = idx; 1595 port->port.private_data = data; 1596 1597 return 0; 1598 } 1599 1600 static int pci_fintek_init(struct pci_dev *dev) 1601 { 1602 unsigned long iobase; 1603 u32 max_port, i; 1604 resource_size_t bar_data[3]; 1605 u8 config_base; 1606 struct serial_private *priv = pci_get_drvdata(dev); 1607 1608 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1609 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1610 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1611 return -ENODEV; 1612 1613 switch (dev->device) { 1614 case 0x1104: /* 4 ports */ 1615 case 0x1108: /* 8 ports */ 1616 max_port = dev->device & 0xff; 1617 break; 1618 case 0x1112: /* 12 ports */ 1619 max_port = 12; 1620 break; 1621 default: 1622 return -EINVAL; 1623 } 1624 1625 /* Get the io address dispatch from the BIOS */ 1626 bar_data[0] = pci_resource_start(dev, 5); 1627 bar_data[1] = pci_resource_start(dev, 4); 1628 bar_data[2] = pci_resource_start(dev, 3); 1629 1630 for (i = 0; i < max_port; ++i) { 1631 /* UART0 configuration offset start from 0x40 */ 1632 config_base = 0x40 + 0x08 * i; 1633 1634 /* Calculate Real IO Port */ 1635 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1636 1637 /* Enable UART I/O port */ 1638 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1639 1640 /* Select 128-byte FIFO and 8x FIFO threshold */ 1641 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1642 1643 /* LSB UART */ 1644 pci_write_config_byte(dev, config_base + 0x04, 1645 (u8)(iobase & 0xff)); 1646 1647 /* MSB UART */ 1648 pci_write_config_byte(dev, config_base + 0x05, 1649 (u8)((iobase & 0xff00) >> 8)); 1650 1651 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1652 1653 if (!priv) { 1654 /* First init without port data 1655 * force init to RS232 Mode 1656 */ 1657 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1658 } 1659 } 1660 1661 return max_port; 1662 } 1663 1664 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1665 { 1666 struct f815xxa_data *data = p->private_data; 1667 unsigned long flags; 1668 1669 spin_lock_irqsave(&data->lock, flags); 1670 writeb(value, p->membase + offset); 1671 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1672 spin_unlock_irqrestore(&data->lock, flags); 1673 } 1674 1675 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1676 const struct pciserial_board *board, 1677 struct uart_8250_port *port, int idx) 1678 { 1679 struct pci_dev *pdev = priv->dev; 1680 struct f815xxa_data *data; 1681 1682 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1683 if (!data) 1684 return -ENOMEM; 1685 1686 data->idx = idx; 1687 spin_lock_init(&data->lock); 1688 1689 port->port.private_data = data; 1690 port->port.iotype = UPIO_MEM; 1691 port->port.flags |= UPF_IOREMAP; 1692 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1693 port->port.serial_out = f815xxa_mem_serial_out; 1694 1695 return 0; 1696 } 1697 1698 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1699 { 1700 u32 max_port, i; 1701 int config_base; 1702 1703 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1704 return -ENODEV; 1705 1706 switch (dev->device) { 1707 case 0x1204: /* 4 ports */ 1708 case 0x1208: /* 8 ports */ 1709 max_port = dev->device & 0xff; 1710 break; 1711 case 0x1212: /* 12 ports */ 1712 max_port = 12; 1713 break; 1714 default: 1715 return -EINVAL; 1716 } 1717 1718 /* Set to mmio decode */ 1719 pci_write_config_byte(dev, 0x209, 0x40); 1720 1721 for (i = 0; i < max_port; ++i) { 1722 /* UART0 configuration offset start from 0x2A0 */ 1723 config_base = 0x2A0 + 0x08 * i; 1724 1725 /* Select 128-byte FIFO and 8x FIFO threshold */ 1726 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1727 1728 /* Enable UART I/O port */ 1729 pci_write_config_byte(dev, config_base + 0, 0x01); 1730 } 1731 1732 return max_port; 1733 } 1734 1735 static int skip_tx_en_setup(struct serial_private *priv, 1736 const struct pciserial_board *board, 1737 struct uart_8250_port *port, int idx) 1738 { 1739 port->port.quirks |= UPQ_NO_TXEN_TEST; 1740 pci_dbg(priv->dev, 1741 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1742 priv->dev->vendor, priv->dev->device, 1743 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1744 1745 return pci_default_setup(priv, board, port, idx); 1746 } 1747 1748 static void kt_handle_break(struct uart_port *p) 1749 { 1750 struct uart_8250_port *up = up_to_u8250p(p); 1751 /* 1752 * On receipt of a BI, serial device in Intel ME (Intel 1753 * management engine) needs to have its fifos cleared for sane 1754 * SOL (Serial Over Lan) output. 1755 */ 1756 serial8250_clear_and_reinit_fifos(up); 1757 } 1758 1759 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1760 { 1761 struct uart_8250_port *up = up_to_u8250p(p); 1762 unsigned int val; 1763 1764 /* 1765 * When the Intel ME (management engine) gets reset its serial 1766 * port registers could return 0 momentarily. Functions like 1767 * serial8250_console_write, read and save the IER, perform 1768 * some operation and then restore it. In order to avoid 1769 * setting IER register inadvertently to 0, if the value read 1770 * is 0, double check with ier value in uart_8250_port and use 1771 * that instead. up->ier should be the same value as what is 1772 * currently configured. 1773 */ 1774 val = inb(p->iobase + offset); 1775 if (offset == UART_IER) { 1776 if (val == 0) 1777 val = up->ier; 1778 } 1779 return val; 1780 } 1781 1782 static int kt_serial_setup(struct serial_private *priv, 1783 const struct pciserial_board *board, 1784 struct uart_8250_port *port, int idx) 1785 { 1786 port->port.flags |= UPF_BUG_THRE; 1787 port->port.serial_in = kt_serial_in; 1788 port->port.handle_break = kt_handle_break; 1789 return skip_tx_en_setup(priv, board, port, idx); 1790 } 1791 1792 static int pci_eg20t_init(struct pci_dev *dev) 1793 { 1794 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1795 return -ENODEV; 1796 #else 1797 return 0; 1798 #endif 1799 } 1800 1801 static int 1802 pci_wch_ch353_setup(struct serial_private *priv, 1803 const struct pciserial_board *board, 1804 struct uart_8250_port *port, int idx) 1805 { 1806 port->port.flags |= UPF_FIXED_TYPE; 1807 port->port.type = PORT_16550A; 1808 return pci_default_setup(priv, board, port, idx); 1809 } 1810 1811 static int 1812 pci_wch_ch355_setup(struct serial_private *priv, 1813 const struct pciserial_board *board, 1814 struct uart_8250_port *port, int idx) 1815 { 1816 port->port.flags |= UPF_FIXED_TYPE; 1817 port->port.type = PORT_16550A; 1818 return pci_default_setup(priv, board, port, idx); 1819 } 1820 1821 static int 1822 pci_wch_ch38x_setup(struct serial_private *priv, 1823 const struct pciserial_board *board, 1824 struct uart_8250_port *port, int idx) 1825 { 1826 port->port.flags |= UPF_FIXED_TYPE; 1827 port->port.type = PORT_16850; 1828 return pci_default_setup(priv, board, port, idx); 1829 } 1830 1831 1832 #define CH384_XINT_ENABLE_REG 0xEB 1833 #define CH384_XINT_ENABLE_BIT 0x02 1834 1835 static int pci_wch_ch38x_init(struct pci_dev *dev) 1836 { 1837 int max_port; 1838 unsigned long iobase; 1839 1840 1841 switch (dev->device) { 1842 case 0x3853: /* 8 ports */ 1843 max_port = 8; 1844 break; 1845 default: 1846 return -EINVAL; 1847 } 1848 1849 iobase = pci_resource_start(dev, 0); 1850 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1851 1852 return max_port; 1853 } 1854 1855 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1856 { 1857 unsigned long iobase; 1858 1859 iobase = pci_resource_start(dev, 0); 1860 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1861 } 1862 1863 1864 static int 1865 pci_sunix_setup(struct serial_private *priv, 1866 const struct pciserial_board *board, 1867 struct uart_8250_port *port, int idx) 1868 { 1869 int bar; 1870 int offset; 1871 1872 port->port.flags |= UPF_FIXED_TYPE; 1873 port->port.type = PORT_SUNIX; 1874 1875 if (idx < 4) { 1876 bar = 0; 1877 offset = idx * board->uart_offset; 1878 } else { 1879 bar = 1; 1880 idx -= 4; 1881 idx = div_s64_rem(idx, 4, &offset); 1882 offset = idx * 64 + offset * board->uart_offset; 1883 } 1884 1885 return setup_port(priv, port, bar, offset, 0); 1886 } 1887 1888 static int 1889 pci_moxa_setup(struct serial_private *priv, 1890 const struct pciserial_board *board, 1891 struct uart_8250_port *port, int idx) 1892 { 1893 unsigned int bar = FL_GET_BASE(board->flags); 1894 int offset; 1895 1896 if (board->num_ports == 4 && idx == 3) 1897 offset = 7 * board->uart_offset; 1898 else 1899 offset = idx * board->uart_offset; 1900 1901 return setup_port(priv, port, bar, offset, 0); 1902 } 1903 1904 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1905 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1906 #define PCI_DEVICE_ID_OCTPRO 0x0001 1907 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1908 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1909 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1910 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1911 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1912 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1913 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1914 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1915 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 1916 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 1917 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1918 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1919 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1920 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1921 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1922 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1923 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1924 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1925 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1926 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1927 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1928 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1929 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1930 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1931 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1932 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1933 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1934 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1935 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1936 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1937 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1938 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1939 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1940 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1941 #define PCI_VENDOR_ID_WCH 0x4348 1942 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1943 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1944 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1945 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1946 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1947 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1948 #define PCI_VENDOR_ID_AGESTAR 0x5372 1949 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1950 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1951 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1952 1953 #define PCIE_VENDOR_ID_WCH 0x1c00 1954 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1955 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1956 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1957 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1958 1959 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1960 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1961 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1962 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1963 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1964 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1965 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1966 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1967 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1968 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1969 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1970 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1971 1972 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1973 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1974 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1975 1976 /* 1977 * Master list of serial port init/setup/exit quirks. 1978 * This does not describe the general nature of the port. 1979 * (ie, baud base, number and location of ports, etc) 1980 * 1981 * This list is ordered alphabetically by vendor then device. 1982 * Specific entries must come before more generic entries. 1983 */ 1984 static struct pci_serial_quirk pci_serial_quirks[] = { 1985 /* 1986 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1987 */ 1988 { 1989 .vendor = PCI_VENDOR_ID_AMCC, 1990 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1991 .subvendor = PCI_ANY_ID, 1992 .subdevice = PCI_ANY_ID, 1993 .setup = addidata_apci7800_setup, 1994 }, 1995 /* 1996 * AFAVLAB cards - these may be called via parport_serial 1997 * It is not clear whether this applies to all products. 1998 */ 1999 { 2000 .vendor = PCI_VENDOR_ID_AFAVLAB, 2001 .device = PCI_ANY_ID, 2002 .subvendor = PCI_ANY_ID, 2003 .subdevice = PCI_ANY_ID, 2004 .setup = afavlab_setup, 2005 }, 2006 /* 2007 * HP Diva 2008 */ 2009 { 2010 .vendor = PCI_VENDOR_ID_HP, 2011 .device = PCI_DEVICE_ID_HP_DIVA, 2012 .subvendor = PCI_ANY_ID, 2013 .subdevice = PCI_ANY_ID, 2014 .init = pci_hp_diva_init, 2015 .setup = pci_hp_diva_setup, 2016 }, 2017 /* 2018 * HPE PCI serial device 2019 */ 2020 { 2021 .vendor = PCI_VENDOR_ID_HP_3PAR, 2022 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2023 .subvendor = PCI_ANY_ID, 2024 .subdevice = PCI_ANY_ID, 2025 .setup = pci_hp_diva_setup, 2026 }, 2027 /* 2028 * Intel 2029 */ 2030 { 2031 .vendor = PCI_VENDOR_ID_INTEL, 2032 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2033 .subvendor = 0xe4bf, 2034 .subdevice = PCI_ANY_ID, 2035 .init = pci_inteli960ni_init, 2036 .setup = pci_default_setup, 2037 }, 2038 { 2039 .vendor = PCI_VENDOR_ID_INTEL, 2040 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2041 .subvendor = PCI_ANY_ID, 2042 .subdevice = PCI_ANY_ID, 2043 .setup = skip_tx_en_setup, 2044 }, 2045 { 2046 .vendor = PCI_VENDOR_ID_INTEL, 2047 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2048 .subvendor = PCI_ANY_ID, 2049 .subdevice = PCI_ANY_ID, 2050 .setup = skip_tx_en_setup, 2051 }, 2052 { 2053 .vendor = PCI_VENDOR_ID_INTEL, 2054 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2055 .subvendor = PCI_ANY_ID, 2056 .subdevice = PCI_ANY_ID, 2057 .setup = skip_tx_en_setup, 2058 }, 2059 { 2060 .vendor = PCI_VENDOR_ID_INTEL, 2061 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2062 .subvendor = PCI_ANY_ID, 2063 .subdevice = PCI_ANY_ID, 2064 .setup = ce4100_serial_setup, 2065 }, 2066 { 2067 .vendor = PCI_VENDOR_ID_INTEL, 2068 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2069 .subvendor = PCI_ANY_ID, 2070 .subdevice = PCI_ANY_ID, 2071 .setup = kt_serial_setup, 2072 }, 2073 /* 2074 * ITE 2075 */ 2076 { 2077 .vendor = PCI_VENDOR_ID_ITE, 2078 .device = PCI_DEVICE_ID_ITE_8872, 2079 .subvendor = PCI_ANY_ID, 2080 .subdevice = PCI_ANY_ID, 2081 .init = pci_ite887x_init, 2082 .setup = pci_default_setup, 2083 .exit = pci_ite887x_exit, 2084 }, 2085 /* 2086 * National Instruments 2087 */ 2088 { 2089 .vendor = PCI_VENDOR_ID_NI, 2090 .device = PCI_DEVICE_ID_NI_PCI23216, 2091 .subvendor = PCI_ANY_ID, 2092 .subdevice = PCI_ANY_ID, 2093 .init = pci_ni8420_init, 2094 .setup = pci_default_setup, 2095 .exit = pci_ni8420_exit, 2096 }, 2097 { 2098 .vendor = PCI_VENDOR_ID_NI, 2099 .device = PCI_DEVICE_ID_NI_PCI2328, 2100 .subvendor = PCI_ANY_ID, 2101 .subdevice = PCI_ANY_ID, 2102 .init = pci_ni8420_init, 2103 .setup = pci_default_setup, 2104 .exit = pci_ni8420_exit, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_NI, 2108 .device = PCI_DEVICE_ID_NI_PCI2324, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .init = pci_ni8420_init, 2112 .setup = pci_default_setup, 2113 .exit = pci_ni8420_exit, 2114 }, 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PCI2322, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PCI2324I, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_DEVICE_ID_NI_PCI2322I, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8420_init, 2139 .setup = pci_default_setup, 2140 .exit = pci_ni8420_exit, 2141 }, 2142 { 2143 .vendor = PCI_VENDOR_ID_NI, 2144 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2145 .subvendor = PCI_ANY_ID, 2146 .subdevice = PCI_ANY_ID, 2147 .init = pci_ni8420_init, 2148 .setup = pci_default_setup, 2149 .exit = pci_ni8420_exit, 2150 }, 2151 { 2152 .vendor = PCI_VENDOR_ID_NI, 2153 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_ni8420_init, 2157 .setup = pci_default_setup, 2158 .exit = pci_ni8420_exit, 2159 }, 2160 { 2161 .vendor = PCI_VENDOR_ID_NI, 2162 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2163 .subvendor = PCI_ANY_ID, 2164 .subdevice = PCI_ANY_ID, 2165 .init = pci_ni8420_init, 2166 .setup = pci_default_setup, 2167 .exit = pci_ni8420_exit, 2168 }, 2169 { 2170 .vendor = PCI_VENDOR_ID_NI, 2171 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2172 .subvendor = PCI_ANY_ID, 2173 .subdevice = PCI_ANY_ID, 2174 .init = pci_ni8420_init, 2175 .setup = pci_default_setup, 2176 .exit = pci_ni8420_exit, 2177 }, 2178 { 2179 .vendor = PCI_VENDOR_ID_NI, 2180 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2181 .subvendor = PCI_ANY_ID, 2182 .subdevice = PCI_ANY_ID, 2183 .init = pci_ni8420_init, 2184 .setup = pci_default_setup, 2185 .exit = pci_ni8420_exit, 2186 }, 2187 { 2188 .vendor = PCI_VENDOR_ID_NI, 2189 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2190 .subvendor = PCI_ANY_ID, 2191 .subdevice = PCI_ANY_ID, 2192 .init = pci_ni8420_init, 2193 .setup = pci_default_setup, 2194 .exit = pci_ni8420_exit, 2195 }, 2196 { 2197 .vendor = PCI_VENDOR_ID_NI, 2198 .device = PCI_ANY_ID, 2199 .subvendor = PCI_ANY_ID, 2200 .subdevice = PCI_ANY_ID, 2201 .init = pci_ni8430_init, 2202 .setup = pci_ni8430_setup, 2203 .exit = pci_ni8430_exit, 2204 }, 2205 /* Quatech */ 2206 { 2207 .vendor = PCI_VENDOR_ID_QUATECH, 2208 .device = PCI_ANY_ID, 2209 .subvendor = PCI_ANY_ID, 2210 .subdevice = PCI_ANY_ID, 2211 .init = pci_quatech_init, 2212 .setup = pci_quatech_setup, 2213 }, 2214 /* 2215 * Panacom 2216 */ 2217 { 2218 .vendor = PCI_VENDOR_ID_PANACOM, 2219 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2220 .subvendor = PCI_ANY_ID, 2221 .subdevice = PCI_ANY_ID, 2222 .init = pci_plx9050_init, 2223 .setup = pci_default_setup, 2224 .exit = pci_plx9050_exit, 2225 }, 2226 { 2227 .vendor = PCI_VENDOR_ID_PANACOM, 2228 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2229 .subvendor = PCI_ANY_ID, 2230 .subdevice = PCI_ANY_ID, 2231 .init = pci_plx9050_init, 2232 .setup = pci_default_setup, 2233 .exit = pci_plx9050_exit, 2234 }, 2235 /* 2236 * PLX 2237 */ 2238 { 2239 .vendor = PCI_VENDOR_ID_PLX, 2240 .device = PCI_DEVICE_ID_PLX_9050, 2241 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2242 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2243 .init = pci_plx9050_init, 2244 .setup = pci_default_setup, 2245 .exit = pci_plx9050_exit, 2246 }, 2247 { 2248 .vendor = PCI_VENDOR_ID_PLX, 2249 .device = PCI_DEVICE_ID_PLX_9050, 2250 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2251 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2252 .init = pci_plx9050_init, 2253 .setup = pci_default_setup, 2254 .exit = pci_plx9050_exit, 2255 }, 2256 { 2257 .vendor = PCI_VENDOR_ID_PLX, 2258 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2259 .subvendor = PCI_VENDOR_ID_PLX, 2260 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2261 .init = pci_plx9050_init, 2262 .setup = pci_default_setup, 2263 .exit = pci_plx9050_exit, 2264 }, 2265 /* 2266 * SBS Technologies, Inc., PMC-OCTALPRO 232 2267 */ 2268 { 2269 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2270 .device = PCI_DEVICE_ID_OCTPRO, 2271 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2272 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2273 .init = sbs_init, 2274 .setup = sbs_setup, 2275 .exit = sbs_exit, 2276 }, 2277 /* 2278 * SBS Technologies, Inc., PMC-OCTALPRO 422 2279 */ 2280 { 2281 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2282 .device = PCI_DEVICE_ID_OCTPRO, 2283 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2284 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2285 .init = sbs_init, 2286 .setup = sbs_setup, 2287 .exit = sbs_exit, 2288 }, 2289 /* 2290 * SBS Technologies, Inc., P-Octal 232 2291 */ 2292 { 2293 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2294 .device = PCI_DEVICE_ID_OCTPRO, 2295 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2296 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2297 .init = sbs_init, 2298 .setup = sbs_setup, 2299 .exit = sbs_exit, 2300 }, 2301 /* 2302 * SBS Technologies, Inc., P-Octal 422 2303 */ 2304 { 2305 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2306 .device = PCI_DEVICE_ID_OCTPRO, 2307 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2308 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2309 .init = sbs_init, 2310 .setup = sbs_setup, 2311 .exit = sbs_exit, 2312 }, 2313 /* 2314 * SIIG cards - these may be called via parport_serial 2315 */ 2316 { 2317 .vendor = PCI_VENDOR_ID_SIIG, 2318 .device = PCI_ANY_ID, 2319 .subvendor = PCI_ANY_ID, 2320 .subdevice = PCI_ANY_ID, 2321 .init = pci_siig_init, 2322 .setup = pci_siig_setup, 2323 }, 2324 /* 2325 * Titan cards 2326 */ 2327 { 2328 .vendor = PCI_VENDOR_ID_TITAN, 2329 .device = PCI_DEVICE_ID_TITAN_400L, 2330 .subvendor = PCI_ANY_ID, 2331 .subdevice = PCI_ANY_ID, 2332 .setup = titan_400l_800l_setup, 2333 }, 2334 { 2335 .vendor = PCI_VENDOR_ID_TITAN, 2336 .device = PCI_DEVICE_ID_TITAN_800L, 2337 .subvendor = PCI_ANY_ID, 2338 .subdevice = PCI_ANY_ID, 2339 .setup = titan_400l_800l_setup, 2340 }, 2341 /* 2342 * Timedia cards 2343 */ 2344 { 2345 .vendor = PCI_VENDOR_ID_TIMEDIA, 2346 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2347 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2348 .subdevice = PCI_ANY_ID, 2349 .probe = pci_timedia_probe, 2350 .init = pci_timedia_init, 2351 .setup = pci_timedia_setup, 2352 }, 2353 { 2354 .vendor = PCI_VENDOR_ID_TIMEDIA, 2355 .device = PCI_ANY_ID, 2356 .subvendor = PCI_ANY_ID, 2357 .subdevice = PCI_ANY_ID, 2358 .setup = pci_timedia_setup, 2359 }, 2360 /* 2361 * Sunix PCI serial boards 2362 */ 2363 { 2364 .vendor = PCI_VENDOR_ID_SUNIX, 2365 .device = PCI_DEVICE_ID_SUNIX_1999, 2366 .subvendor = PCI_VENDOR_ID_SUNIX, 2367 .subdevice = PCI_ANY_ID, 2368 .setup = pci_sunix_setup, 2369 }, 2370 /* 2371 * Xircom cards 2372 */ 2373 { 2374 .vendor = PCI_VENDOR_ID_XIRCOM, 2375 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2376 .subvendor = PCI_ANY_ID, 2377 .subdevice = PCI_ANY_ID, 2378 .init = pci_xircom_init, 2379 .setup = pci_default_setup, 2380 }, 2381 /* 2382 * Netmos cards - these may be called via parport_serial 2383 */ 2384 { 2385 .vendor = PCI_VENDOR_ID_NETMOS, 2386 .device = PCI_ANY_ID, 2387 .subvendor = PCI_ANY_ID, 2388 .subdevice = PCI_ANY_ID, 2389 .init = pci_netmos_init, 2390 .setup = pci_netmos_9900_setup, 2391 }, 2392 /* 2393 * EndRun Technologies 2394 */ 2395 { 2396 .vendor = PCI_VENDOR_ID_ENDRUN, 2397 .device = PCI_ANY_ID, 2398 .subvendor = PCI_ANY_ID, 2399 .subdevice = PCI_ANY_ID, 2400 .init = pci_oxsemi_tornado_init, 2401 .setup = pci_default_setup, 2402 }, 2403 /* 2404 * For Oxford Semiconductor Tornado based devices 2405 */ 2406 { 2407 .vendor = PCI_VENDOR_ID_OXSEMI, 2408 .device = PCI_ANY_ID, 2409 .subvendor = PCI_ANY_ID, 2410 .subdevice = PCI_ANY_ID, 2411 .init = pci_oxsemi_tornado_init, 2412 .setup = pci_oxsemi_tornado_setup, 2413 }, 2414 { 2415 .vendor = PCI_VENDOR_ID_MAINPINE, 2416 .device = PCI_ANY_ID, 2417 .subvendor = PCI_ANY_ID, 2418 .subdevice = PCI_ANY_ID, 2419 .init = pci_oxsemi_tornado_init, 2420 .setup = pci_oxsemi_tornado_setup, 2421 }, 2422 { 2423 .vendor = PCI_VENDOR_ID_DIGI, 2424 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2425 .subvendor = PCI_SUBVENDOR_ID_IBM, 2426 .subdevice = PCI_ANY_ID, 2427 .init = pci_oxsemi_tornado_init, 2428 .setup = pci_oxsemi_tornado_setup, 2429 }, 2430 { 2431 .vendor = PCI_VENDOR_ID_INTEL, 2432 .device = 0x8811, 2433 .subvendor = PCI_ANY_ID, 2434 .subdevice = PCI_ANY_ID, 2435 .init = pci_eg20t_init, 2436 .setup = pci_default_setup, 2437 }, 2438 { 2439 .vendor = PCI_VENDOR_ID_INTEL, 2440 .device = 0x8812, 2441 .subvendor = PCI_ANY_ID, 2442 .subdevice = PCI_ANY_ID, 2443 .init = pci_eg20t_init, 2444 .setup = pci_default_setup, 2445 }, 2446 { 2447 .vendor = PCI_VENDOR_ID_INTEL, 2448 .device = 0x8813, 2449 .subvendor = PCI_ANY_ID, 2450 .subdevice = PCI_ANY_ID, 2451 .init = pci_eg20t_init, 2452 .setup = pci_default_setup, 2453 }, 2454 { 2455 .vendor = PCI_VENDOR_ID_INTEL, 2456 .device = 0x8814, 2457 .subvendor = PCI_ANY_ID, 2458 .subdevice = PCI_ANY_ID, 2459 .init = pci_eg20t_init, 2460 .setup = pci_default_setup, 2461 }, 2462 { 2463 .vendor = 0x10DB, 2464 .device = 0x8027, 2465 .subvendor = PCI_ANY_ID, 2466 .subdevice = PCI_ANY_ID, 2467 .init = pci_eg20t_init, 2468 .setup = pci_default_setup, 2469 }, 2470 { 2471 .vendor = 0x10DB, 2472 .device = 0x8028, 2473 .subvendor = PCI_ANY_ID, 2474 .subdevice = PCI_ANY_ID, 2475 .init = pci_eg20t_init, 2476 .setup = pci_default_setup, 2477 }, 2478 { 2479 .vendor = 0x10DB, 2480 .device = 0x8029, 2481 .subvendor = PCI_ANY_ID, 2482 .subdevice = PCI_ANY_ID, 2483 .init = pci_eg20t_init, 2484 .setup = pci_default_setup, 2485 }, 2486 { 2487 .vendor = 0x10DB, 2488 .device = 0x800C, 2489 .subvendor = PCI_ANY_ID, 2490 .subdevice = PCI_ANY_ID, 2491 .init = pci_eg20t_init, 2492 .setup = pci_default_setup, 2493 }, 2494 { 2495 .vendor = 0x10DB, 2496 .device = 0x800D, 2497 .subvendor = PCI_ANY_ID, 2498 .subdevice = PCI_ANY_ID, 2499 .init = pci_eg20t_init, 2500 .setup = pci_default_setup, 2501 }, 2502 /* 2503 * Cronyx Omega PCI (PLX-chip based) 2504 */ 2505 { 2506 .vendor = PCI_VENDOR_ID_PLX, 2507 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2508 .subvendor = PCI_ANY_ID, 2509 .subdevice = PCI_ANY_ID, 2510 .setup = pci_omegapci_setup, 2511 }, 2512 /* WCH CH353 1S1P card (16550 clone) */ 2513 { 2514 .vendor = PCI_VENDOR_ID_WCH, 2515 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2516 .subvendor = PCI_ANY_ID, 2517 .subdevice = PCI_ANY_ID, 2518 .setup = pci_wch_ch353_setup, 2519 }, 2520 /* WCH CH353 2S1P card (16550 clone) */ 2521 { 2522 .vendor = PCI_VENDOR_ID_WCH, 2523 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2524 .subvendor = PCI_ANY_ID, 2525 .subdevice = PCI_ANY_ID, 2526 .setup = pci_wch_ch353_setup, 2527 }, 2528 /* WCH CH353 4S card (16550 clone) */ 2529 { 2530 .vendor = PCI_VENDOR_ID_WCH, 2531 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2532 .subvendor = PCI_ANY_ID, 2533 .subdevice = PCI_ANY_ID, 2534 .setup = pci_wch_ch353_setup, 2535 }, 2536 /* WCH CH353 2S1PF card (16550 clone) */ 2537 { 2538 .vendor = PCI_VENDOR_ID_WCH, 2539 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2540 .subvendor = PCI_ANY_ID, 2541 .subdevice = PCI_ANY_ID, 2542 .setup = pci_wch_ch353_setup, 2543 }, 2544 /* WCH CH352 2S card (16550 clone) */ 2545 { 2546 .vendor = PCI_VENDOR_ID_WCH, 2547 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2548 .subvendor = PCI_ANY_ID, 2549 .subdevice = PCI_ANY_ID, 2550 .setup = pci_wch_ch353_setup, 2551 }, 2552 /* WCH CH355 4S card (16550 clone) */ 2553 { 2554 .vendor = PCI_VENDOR_ID_WCH, 2555 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2556 .subvendor = PCI_ANY_ID, 2557 .subdevice = PCI_ANY_ID, 2558 .setup = pci_wch_ch355_setup, 2559 }, 2560 /* WCH CH382 2S card (16850 clone) */ 2561 { 2562 .vendor = PCIE_VENDOR_ID_WCH, 2563 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2564 .subvendor = PCI_ANY_ID, 2565 .subdevice = PCI_ANY_ID, 2566 .setup = pci_wch_ch38x_setup, 2567 }, 2568 /* WCH CH382 2S1P card (16850 clone) */ 2569 { 2570 .vendor = PCIE_VENDOR_ID_WCH, 2571 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2572 .subvendor = PCI_ANY_ID, 2573 .subdevice = PCI_ANY_ID, 2574 .setup = pci_wch_ch38x_setup, 2575 }, 2576 /* WCH CH384 4S card (16850 clone) */ 2577 { 2578 .vendor = PCIE_VENDOR_ID_WCH, 2579 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2580 .subvendor = PCI_ANY_ID, 2581 .subdevice = PCI_ANY_ID, 2582 .setup = pci_wch_ch38x_setup, 2583 }, 2584 /* WCH CH384 8S card (16850 clone) */ 2585 { 2586 .vendor = PCIE_VENDOR_ID_WCH, 2587 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2588 .subvendor = PCI_ANY_ID, 2589 .subdevice = PCI_ANY_ID, 2590 .init = pci_wch_ch38x_init, 2591 .exit = pci_wch_ch38x_exit, 2592 .setup = pci_wch_ch38x_setup, 2593 }, 2594 /* 2595 * Broadcom TruManage (NetXtreme) 2596 */ 2597 { 2598 .vendor = PCI_VENDOR_ID_BROADCOM, 2599 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2600 .subvendor = PCI_ANY_ID, 2601 .subdevice = PCI_ANY_ID, 2602 .setup = pci_brcm_trumanage_setup, 2603 }, 2604 { 2605 .vendor = 0x1c29, 2606 .device = 0x1104, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .setup = pci_fintek_setup, 2610 .init = pci_fintek_init, 2611 }, 2612 { 2613 .vendor = 0x1c29, 2614 .device = 0x1108, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .setup = pci_fintek_setup, 2618 .init = pci_fintek_init, 2619 }, 2620 { 2621 .vendor = 0x1c29, 2622 .device = 0x1112, 2623 .subvendor = PCI_ANY_ID, 2624 .subdevice = PCI_ANY_ID, 2625 .setup = pci_fintek_setup, 2626 .init = pci_fintek_init, 2627 }, 2628 /* 2629 * MOXA 2630 */ 2631 { 2632 .vendor = PCI_VENDOR_ID_MOXA, 2633 .device = PCI_ANY_ID, 2634 .subvendor = PCI_ANY_ID, 2635 .subdevice = PCI_ANY_ID, 2636 .setup = pci_moxa_setup, 2637 }, 2638 { 2639 .vendor = 0x1c29, 2640 .device = 0x1204, 2641 .subvendor = PCI_ANY_ID, 2642 .subdevice = PCI_ANY_ID, 2643 .setup = pci_fintek_f815xxa_setup, 2644 .init = pci_fintek_f815xxa_init, 2645 }, 2646 { 2647 .vendor = 0x1c29, 2648 .device = 0x1208, 2649 .subvendor = PCI_ANY_ID, 2650 .subdevice = PCI_ANY_ID, 2651 .setup = pci_fintek_f815xxa_setup, 2652 .init = pci_fintek_f815xxa_init, 2653 }, 2654 { 2655 .vendor = 0x1c29, 2656 .device = 0x1212, 2657 .subvendor = PCI_ANY_ID, 2658 .subdevice = PCI_ANY_ID, 2659 .setup = pci_fintek_f815xxa_setup, 2660 .init = pci_fintek_f815xxa_init, 2661 }, 2662 2663 /* 2664 * Default "match everything" terminator entry 2665 */ 2666 { 2667 .vendor = PCI_ANY_ID, 2668 .device = PCI_ANY_ID, 2669 .subvendor = PCI_ANY_ID, 2670 .subdevice = PCI_ANY_ID, 2671 .setup = pci_default_setup, 2672 } 2673 }; 2674 2675 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2676 { 2677 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2678 } 2679 2680 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2681 { 2682 struct pci_serial_quirk *quirk; 2683 2684 for (quirk = pci_serial_quirks; ; quirk++) 2685 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2686 quirk_id_matches(quirk->device, dev->device) && 2687 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2688 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2689 break; 2690 return quirk; 2691 } 2692 2693 /* 2694 * This is the configuration table for all of the PCI serial boards 2695 * which we support. It is directly indexed by the pci_board_num_t enum 2696 * value, which is encoded in the pci_device_id PCI probe table's 2697 * driver_data member. 2698 * 2699 * The makeup of these names are: 2700 * pbn_bn{_bt}_n_baud{_offsetinhex} 2701 * 2702 * bn = PCI BAR number 2703 * bt = Index using PCI BARs 2704 * n = number of serial ports 2705 * baud = baud rate 2706 * offsetinhex = offset for each sequential port (in hex) 2707 * 2708 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2709 * 2710 * Please note: in theory if n = 1, _bt infix should make no difference. 2711 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2712 */ 2713 enum pci_board_num_t { 2714 pbn_default = 0, 2715 2716 pbn_b0_1_115200, 2717 pbn_b0_2_115200, 2718 pbn_b0_4_115200, 2719 pbn_b0_5_115200, 2720 pbn_b0_8_115200, 2721 2722 pbn_b0_1_921600, 2723 pbn_b0_2_921600, 2724 pbn_b0_4_921600, 2725 2726 pbn_b0_2_1130000, 2727 2728 pbn_b0_4_1152000, 2729 2730 pbn_b0_4_1250000, 2731 2732 pbn_b0_2_1843200, 2733 pbn_b0_4_1843200, 2734 2735 pbn_b0_1_15625000, 2736 2737 pbn_b0_bt_1_115200, 2738 pbn_b0_bt_2_115200, 2739 pbn_b0_bt_4_115200, 2740 pbn_b0_bt_8_115200, 2741 2742 pbn_b0_bt_1_460800, 2743 pbn_b0_bt_2_460800, 2744 pbn_b0_bt_4_460800, 2745 2746 pbn_b0_bt_1_921600, 2747 pbn_b0_bt_2_921600, 2748 pbn_b0_bt_4_921600, 2749 pbn_b0_bt_8_921600, 2750 2751 pbn_b1_1_115200, 2752 pbn_b1_2_115200, 2753 pbn_b1_4_115200, 2754 pbn_b1_8_115200, 2755 pbn_b1_16_115200, 2756 2757 pbn_b1_1_921600, 2758 pbn_b1_2_921600, 2759 pbn_b1_4_921600, 2760 pbn_b1_8_921600, 2761 2762 pbn_b1_2_1250000, 2763 2764 pbn_b1_bt_1_115200, 2765 pbn_b1_bt_2_115200, 2766 pbn_b1_bt_4_115200, 2767 2768 pbn_b1_bt_2_921600, 2769 2770 pbn_b1_1_1382400, 2771 pbn_b1_2_1382400, 2772 pbn_b1_4_1382400, 2773 pbn_b1_8_1382400, 2774 2775 pbn_b2_1_115200, 2776 pbn_b2_2_115200, 2777 pbn_b2_4_115200, 2778 pbn_b2_8_115200, 2779 2780 pbn_b2_1_460800, 2781 pbn_b2_4_460800, 2782 pbn_b2_8_460800, 2783 pbn_b2_16_460800, 2784 2785 pbn_b2_1_921600, 2786 pbn_b2_4_921600, 2787 pbn_b2_8_921600, 2788 2789 pbn_b2_8_1152000, 2790 2791 pbn_b2_bt_1_115200, 2792 pbn_b2_bt_2_115200, 2793 pbn_b2_bt_4_115200, 2794 2795 pbn_b2_bt_2_921600, 2796 pbn_b2_bt_4_921600, 2797 2798 pbn_b3_2_115200, 2799 pbn_b3_4_115200, 2800 pbn_b3_8_115200, 2801 2802 pbn_b4_bt_2_921600, 2803 pbn_b4_bt_4_921600, 2804 pbn_b4_bt_8_921600, 2805 2806 /* 2807 * Board-specific versions. 2808 */ 2809 pbn_panacom, 2810 pbn_panacom2, 2811 pbn_panacom4, 2812 pbn_plx_romulus, 2813 pbn_oxsemi, 2814 pbn_oxsemi_1_15625000, 2815 pbn_oxsemi_2_15625000, 2816 pbn_oxsemi_4_15625000, 2817 pbn_oxsemi_8_15625000, 2818 pbn_intel_i960, 2819 pbn_sgi_ioc3, 2820 pbn_computone_4, 2821 pbn_computone_6, 2822 pbn_computone_8, 2823 pbn_sbsxrsio, 2824 pbn_pasemi_1682M, 2825 pbn_ni8430_2, 2826 pbn_ni8430_4, 2827 pbn_ni8430_8, 2828 pbn_ni8430_16, 2829 pbn_ADDIDATA_PCIe_1_3906250, 2830 pbn_ADDIDATA_PCIe_2_3906250, 2831 pbn_ADDIDATA_PCIe_4_3906250, 2832 pbn_ADDIDATA_PCIe_8_3906250, 2833 pbn_ce4100_1_115200, 2834 pbn_omegapci, 2835 pbn_NETMOS9900_2s_115200, 2836 pbn_brcm_trumanage, 2837 pbn_fintek_4, 2838 pbn_fintek_8, 2839 pbn_fintek_12, 2840 pbn_fintek_F81504A, 2841 pbn_fintek_F81508A, 2842 pbn_fintek_F81512A, 2843 pbn_wch382_2, 2844 pbn_wch384_4, 2845 pbn_wch384_8, 2846 pbn_sunix_pci_1s, 2847 pbn_sunix_pci_2s, 2848 pbn_sunix_pci_4s, 2849 pbn_sunix_pci_8s, 2850 pbn_sunix_pci_16s, 2851 pbn_titan_1_4000000, 2852 pbn_titan_2_4000000, 2853 pbn_titan_4_4000000, 2854 pbn_titan_8_4000000, 2855 pbn_moxa8250_2p, 2856 pbn_moxa8250_4p, 2857 pbn_moxa8250_8p, 2858 }; 2859 2860 /* 2861 * uart_offset - the space between channels 2862 * reg_shift - describes how the UART registers are mapped 2863 * to PCI memory by the card. 2864 * For example IER register on SBS, Inc. PMC-OctPro is located at 2865 * offset 0x10 from the UART base, while UART_IER is defined as 1 2866 * in include/linux/serial_reg.h, 2867 * see first lines of serial_in() and serial_out() in 8250.c 2868 */ 2869 2870 static struct pciserial_board pci_boards[] = { 2871 [pbn_default] = { 2872 .flags = FL_BASE0, 2873 .num_ports = 1, 2874 .base_baud = 115200, 2875 .uart_offset = 8, 2876 }, 2877 [pbn_b0_1_115200] = { 2878 .flags = FL_BASE0, 2879 .num_ports = 1, 2880 .base_baud = 115200, 2881 .uart_offset = 8, 2882 }, 2883 [pbn_b0_2_115200] = { 2884 .flags = FL_BASE0, 2885 .num_ports = 2, 2886 .base_baud = 115200, 2887 .uart_offset = 8, 2888 }, 2889 [pbn_b0_4_115200] = { 2890 .flags = FL_BASE0, 2891 .num_ports = 4, 2892 .base_baud = 115200, 2893 .uart_offset = 8, 2894 }, 2895 [pbn_b0_5_115200] = { 2896 .flags = FL_BASE0, 2897 .num_ports = 5, 2898 .base_baud = 115200, 2899 .uart_offset = 8, 2900 }, 2901 [pbn_b0_8_115200] = { 2902 .flags = FL_BASE0, 2903 .num_ports = 8, 2904 .base_baud = 115200, 2905 .uart_offset = 8, 2906 }, 2907 [pbn_b0_1_921600] = { 2908 .flags = FL_BASE0, 2909 .num_ports = 1, 2910 .base_baud = 921600, 2911 .uart_offset = 8, 2912 }, 2913 [pbn_b0_2_921600] = { 2914 .flags = FL_BASE0, 2915 .num_ports = 2, 2916 .base_baud = 921600, 2917 .uart_offset = 8, 2918 }, 2919 [pbn_b0_4_921600] = { 2920 .flags = FL_BASE0, 2921 .num_ports = 4, 2922 .base_baud = 921600, 2923 .uart_offset = 8, 2924 }, 2925 2926 [pbn_b0_2_1130000] = { 2927 .flags = FL_BASE0, 2928 .num_ports = 2, 2929 .base_baud = 1130000, 2930 .uart_offset = 8, 2931 }, 2932 2933 [pbn_b0_4_1152000] = { 2934 .flags = FL_BASE0, 2935 .num_ports = 4, 2936 .base_baud = 1152000, 2937 .uart_offset = 8, 2938 }, 2939 2940 [pbn_b0_4_1250000] = { 2941 .flags = FL_BASE0, 2942 .num_ports = 4, 2943 .base_baud = 1250000, 2944 .uart_offset = 8, 2945 }, 2946 2947 [pbn_b0_2_1843200] = { 2948 .flags = FL_BASE0, 2949 .num_ports = 2, 2950 .base_baud = 1843200, 2951 .uart_offset = 8, 2952 }, 2953 [pbn_b0_4_1843200] = { 2954 .flags = FL_BASE0, 2955 .num_ports = 4, 2956 .base_baud = 1843200, 2957 .uart_offset = 8, 2958 }, 2959 2960 [pbn_b0_1_15625000] = { 2961 .flags = FL_BASE0, 2962 .num_ports = 1, 2963 .base_baud = 15625000, 2964 .uart_offset = 8, 2965 }, 2966 2967 [pbn_b0_bt_1_115200] = { 2968 .flags = FL_BASE0|FL_BASE_BARS, 2969 .num_ports = 1, 2970 .base_baud = 115200, 2971 .uart_offset = 8, 2972 }, 2973 [pbn_b0_bt_2_115200] = { 2974 .flags = FL_BASE0|FL_BASE_BARS, 2975 .num_ports = 2, 2976 .base_baud = 115200, 2977 .uart_offset = 8, 2978 }, 2979 [pbn_b0_bt_4_115200] = { 2980 .flags = FL_BASE0|FL_BASE_BARS, 2981 .num_ports = 4, 2982 .base_baud = 115200, 2983 .uart_offset = 8, 2984 }, 2985 [pbn_b0_bt_8_115200] = { 2986 .flags = FL_BASE0|FL_BASE_BARS, 2987 .num_ports = 8, 2988 .base_baud = 115200, 2989 .uart_offset = 8, 2990 }, 2991 2992 [pbn_b0_bt_1_460800] = { 2993 .flags = FL_BASE0|FL_BASE_BARS, 2994 .num_ports = 1, 2995 .base_baud = 460800, 2996 .uart_offset = 8, 2997 }, 2998 [pbn_b0_bt_2_460800] = { 2999 .flags = FL_BASE0|FL_BASE_BARS, 3000 .num_ports = 2, 3001 .base_baud = 460800, 3002 .uart_offset = 8, 3003 }, 3004 [pbn_b0_bt_4_460800] = { 3005 .flags = FL_BASE0|FL_BASE_BARS, 3006 .num_ports = 4, 3007 .base_baud = 460800, 3008 .uart_offset = 8, 3009 }, 3010 3011 [pbn_b0_bt_1_921600] = { 3012 .flags = FL_BASE0|FL_BASE_BARS, 3013 .num_ports = 1, 3014 .base_baud = 921600, 3015 .uart_offset = 8, 3016 }, 3017 [pbn_b0_bt_2_921600] = { 3018 .flags = FL_BASE0|FL_BASE_BARS, 3019 .num_ports = 2, 3020 .base_baud = 921600, 3021 .uart_offset = 8, 3022 }, 3023 [pbn_b0_bt_4_921600] = { 3024 .flags = FL_BASE0|FL_BASE_BARS, 3025 .num_ports = 4, 3026 .base_baud = 921600, 3027 .uart_offset = 8, 3028 }, 3029 [pbn_b0_bt_8_921600] = { 3030 .flags = FL_BASE0|FL_BASE_BARS, 3031 .num_ports = 8, 3032 .base_baud = 921600, 3033 .uart_offset = 8, 3034 }, 3035 3036 [pbn_b1_1_115200] = { 3037 .flags = FL_BASE1, 3038 .num_ports = 1, 3039 .base_baud = 115200, 3040 .uart_offset = 8, 3041 }, 3042 [pbn_b1_2_115200] = { 3043 .flags = FL_BASE1, 3044 .num_ports = 2, 3045 .base_baud = 115200, 3046 .uart_offset = 8, 3047 }, 3048 [pbn_b1_4_115200] = { 3049 .flags = FL_BASE1, 3050 .num_ports = 4, 3051 .base_baud = 115200, 3052 .uart_offset = 8, 3053 }, 3054 [pbn_b1_8_115200] = { 3055 .flags = FL_BASE1, 3056 .num_ports = 8, 3057 .base_baud = 115200, 3058 .uart_offset = 8, 3059 }, 3060 [pbn_b1_16_115200] = { 3061 .flags = FL_BASE1, 3062 .num_ports = 16, 3063 .base_baud = 115200, 3064 .uart_offset = 8, 3065 }, 3066 3067 [pbn_b1_1_921600] = { 3068 .flags = FL_BASE1, 3069 .num_ports = 1, 3070 .base_baud = 921600, 3071 .uart_offset = 8, 3072 }, 3073 [pbn_b1_2_921600] = { 3074 .flags = FL_BASE1, 3075 .num_ports = 2, 3076 .base_baud = 921600, 3077 .uart_offset = 8, 3078 }, 3079 [pbn_b1_4_921600] = { 3080 .flags = FL_BASE1, 3081 .num_ports = 4, 3082 .base_baud = 921600, 3083 .uart_offset = 8, 3084 }, 3085 [pbn_b1_8_921600] = { 3086 .flags = FL_BASE1, 3087 .num_ports = 8, 3088 .base_baud = 921600, 3089 .uart_offset = 8, 3090 }, 3091 [pbn_b1_2_1250000] = { 3092 .flags = FL_BASE1, 3093 .num_ports = 2, 3094 .base_baud = 1250000, 3095 .uart_offset = 8, 3096 }, 3097 3098 [pbn_b1_bt_1_115200] = { 3099 .flags = FL_BASE1|FL_BASE_BARS, 3100 .num_ports = 1, 3101 .base_baud = 115200, 3102 .uart_offset = 8, 3103 }, 3104 [pbn_b1_bt_2_115200] = { 3105 .flags = FL_BASE1|FL_BASE_BARS, 3106 .num_ports = 2, 3107 .base_baud = 115200, 3108 .uart_offset = 8, 3109 }, 3110 [pbn_b1_bt_4_115200] = { 3111 .flags = FL_BASE1|FL_BASE_BARS, 3112 .num_ports = 4, 3113 .base_baud = 115200, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b1_bt_2_921600] = { 3118 .flags = FL_BASE1|FL_BASE_BARS, 3119 .num_ports = 2, 3120 .base_baud = 921600, 3121 .uart_offset = 8, 3122 }, 3123 3124 [pbn_b1_1_1382400] = { 3125 .flags = FL_BASE1, 3126 .num_ports = 1, 3127 .base_baud = 1382400, 3128 .uart_offset = 8, 3129 }, 3130 [pbn_b1_2_1382400] = { 3131 .flags = FL_BASE1, 3132 .num_ports = 2, 3133 .base_baud = 1382400, 3134 .uart_offset = 8, 3135 }, 3136 [pbn_b1_4_1382400] = { 3137 .flags = FL_BASE1, 3138 .num_ports = 4, 3139 .base_baud = 1382400, 3140 .uart_offset = 8, 3141 }, 3142 [pbn_b1_8_1382400] = { 3143 .flags = FL_BASE1, 3144 .num_ports = 8, 3145 .base_baud = 1382400, 3146 .uart_offset = 8, 3147 }, 3148 3149 [pbn_b2_1_115200] = { 3150 .flags = FL_BASE2, 3151 .num_ports = 1, 3152 .base_baud = 115200, 3153 .uart_offset = 8, 3154 }, 3155 [pbn_b2_2_115200] = { 3156 .flags = FL_BASE2, 3157 .num_ports = 2, 3158 .base_baud = 115200, 3159 .uart_offset = 8, 3160 }, 3161 [pbn_b2_4_115200] = { 3162 .flags = FL_BASE2, 3163 .num_ports = 4, 3164 .base_baud = 115200, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b2_8_115200] = { 3168 .flags = FL_BASE2, 3169 .num_ports = 8, 3170 .base_baud = 115200, 3171 .uart_offset = 8, 3172 }, 3173 3174 [pbn_b2_1_460800] = { 3175 .flags = FL_BASE2, 3176 .num_ports = 1, 3177 .base_baud = 460800, 3178 .uart_offset = 8, 3179 }, 3180 [pbn_b2_4_460800] = { 3181 .flags = FL_BASE2, 3182 .num_ports = 4, 3183 .base_baud = 460800, 3184 .uart_offset = 8, 3185 }, 3186 [pbn_b2_8_460800] = { 3187 .flags = FL_BASE2, 3188 .num_ports = 8, 3189 .base_baud = 460800, 3190 .uart_offset = 8, 3191 }, 3192 [pbn_b2_16_460800] = { 3193 .flags = FL_BASE2, 3194 .num_ports = 16, 3195 .base_baud = 460800, 3196 .uart_offset = 8, 3197 }, 3198 3199 [pbn_b2_1_921600] = { 3200 .flags = FL_BASE2, 3201 .num_ports = 1, 3202 .base_baud = 921600, 3203 .uart_offset = 8, 3204 }, 3205 [pbn_b2_4_921600] = { 3206 .flags = FL_BASE2, 3207 .num_ports = 4, 3208 .base_baud = 921600, 3209 .uart_offset = 8, 3210 }, 3211 [pbn_b2_8_921600] = { 3212 .flags = FL_BASE2, 3213 .num_ports = 8, 3214 .base_baud = 921600, 3215 .uart_offset = 8, 3216 }, 3217 3218 [pbn_b2_8_1152000] = { 3219 .flags = FL_BASE2, 3220 .num_ports = 8, 3221 .base_baud = 1152000, 3222 .uart_offset = 8, 3223 }, 3224 3225 [pbn_b2_bt_1_115200] = { 3226 .flags = FL_BASE2|FL_BASE_BARS, 3227 .num_ports = 1, 3228 .base_baud = 115200, 3229 .uart_offset = 8, 3230 }, 3231 [pbn_b2_bt_2_115200] = { 3232 .flags = FL_BASE2|FL_BASE_BARS, 3233 .num_ports = 2, 3234 .base_baud = 115200, 3235 .uart_offset = 8, 3236 }, 3237 [pbn_b2_bt_4_115200] = { 3238 .flags = FL_BASE2|FL_BASE_BARS, 3239 .num_ports = 4, 3240 .base_baud = 115200, 3241 .uart_offset = 8, 3242 }, 3243 3244 [pbn_b2_bt_2_921600] = { 3245 .flags = FL_BASE2|FL_BASE_BARS, 3246 .num_ports = 2, 3247 .base_baud = 921600, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b2_bt_4_921600] = { 3251 .flags = FL_BASE2|FL_BASE_BARS, 3252 .num_ports = 4, 3253 .base_baud = 921600, 3254 .uart_offset = 8, 3255 }, 3256 3257 [pbn_b3_2_115200] = { 3258 .flags = FL_BASE3, 3259 .num_ports = 2, 3260 .base_baud = 115200, 3261 .uart_offset = 8, 3262 }, 3263 [pbn_b3_4_115200] = { 3264 .flags = FL_BASE3, 3265 .num_ports = 4, 3266 .base_baud = 115200, 3267 .uart_offset = 8, 3268 }, 3269 [pbn_b3_8_115200] = { 3270 .flags = FL_BASE3, 3271 .num_ports = 8, 3272 .base_baud = 115200, 3273 .uart_offset = 8, 3274 }, 3275 3276 [pbn_b4_bt_2_921600] = { 3277 .flags = FL_BASE4, 3278 .num_ports = 2, 3279 .base_baud = 921600, 3280 .uart_offset = 8, 3281 }, 3282 [pbn_b4_bt_4_921600] = { 3283 .flags = FL_BASE4, 3284 .num_ports = 4, 3285 .base_baud = 921600, 3286 .uart_offset = 8, 3287 }, 3288 [pbn_b4_bt_8_921600] = { 3289 .flags = FL_BASE4, 3290 .num_ports = 8, 3291 .base_baud = 921600, 3292 .uart_offset = 8, 3293 }, 3294 3295 /* 3296 * Entries following this are board-specific. 3297 */ 3298 3299 /* 3300 * Panacom - IOMEM 3301 */ 3302 [pbn_panacom] = { 3303 .flags = FL_BASE2, 3304 .num_ports = 2, 3305 .base_baud = 921600, 3306 .uart_offset = 0x400, 3307 .reg_shift = 7, 3308 }, 3309 [pbn_panacom2] = { 3310 .flags = FL_BASE2|FL_BASE_BARS, 3311 .num_ports = 2, 3312 .base_baud = 921600, 3313 .uart_offset = 0x400, 3314 .reg_shift = 7, 3315 }, 3316 [pbn_panacom4] = { 3317 .flags = FL_BASE2|FL_BASE_BARS, 3318 .num_ports = 4, 3319 .base_baud = 921600, 3320 .uart_offset = 0x400, 3321 .reg_shift = 7, 3322 }, 3323 3324 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3325 [pbn_plx_romulus] = { 3326 .flags = FL_BASE2, 3327 .num_ports = 4, 3328 .base_baud = 921600, 3329 .uart_offset = 8 << 2, 3330 .reg_shift = 2, 3331 .first_offset = 0x03, 3332 }, 3333 3334 /* 3335 * This board uses the size of PCI Base region 0 to 3336 * signal now many ports are available 3337 */ 3338 [pbn_oxsemi] = { 3339 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3340 .num_ports = 32, 3341 .base_baud = 115200, 3342 .uart_offset = 8, 3343 }, 3344 [pbn_oxsemi_1_15625000] = { 3345 .flags = FL_BASE0, 3346 .num_ports = 1, 3347 .base_baud = 15625000, 3348 .uart_offset = 0x200, 3349 .first_offset = 0x1000, 3350 }, 3351 [pbn_oxsemi_2_15625000] = { 3352 .flags = FL_BASE0, 3353 .num_ports = 2, 3354 .base_baud = 15625000, 3355 .uart_offset = 0x200, 3356 .first_offset = 0x1000, 3357 }, 3358 [pbn_oxsemi_4_15625000] = { 3359 .flags = FL_BASE0, 3360 .num_ports = 4, 3361 .base_baud = 15625000, 3362 .uart_offset = 0x200, 3363 .first_offset = 0x1000, 3364 }, 3365 [pbn_oxsemi_8_15625000] = { 3366 .flags = FL_BASE0, 3367 .num_ports = 8, 3368 .base_baud = 15625000, 3369 .uart_offset = 0x200, 3370 .first_offset = 0x1000, 3371 }, 3372 3373 3374 /* 3375 * EKF addition for i960 Boards form EKF with serial port. 3376 * Max 256 ports. 3377 */ 3378 [pbn_intel_i960] = { 3379 .flags = FL_BASE0, 3380 .num_ports = 32, 3381 .base_baud = 921600, 3382 .uart_offset = 8 << 2, 3383 .reg_shift = 2, 3384 .first_offset = 0x10000, 3385 }, 3386 [pbn_sgi_ioc3] = { 3387 .flags = FL_BASE0|FL_NOIRQ, 3388 .num_ports = 1, 3389 .base_baud = 458333, 3390 .uart_offset = 8, 3391 .reg_shift = 0, 3392 .first_offset = 0x20178, 3393 }, 3394 3395 /* 3396 * Computone - uses IOMEM. 3397 */ 3398 [pbn_computone_4] = { 3399 .flags = FL_BASE0, 3400 .num_ports = 4, 3401 .base_baud = 921600, 3402 .uart_offset = 0x40, 3403 .reg_shift = 2, 3404 .first_offset = 0x200, 3405 }, 3406 [pbn_computone_6] = { 3407 .flags = FL_BASE0, 3408 .num_ports = 6, 3409 .base_baud = 921600, 3410 .uart_offset = 0x40, 3411 .reg_shift = 2, 3412 .first_offset = 0x200, 3413 }, 3414 [pbn_computone_8] = { 3415 .flags = FL_BASE0, 3416 .num_ports = 8, 3417 .base_baud = 921600, 3418 .uart_offset = 0x40, 3419 .reg_shift = 2, 3420 .first_offset = 0x200, 3421 }, 3422 [pbn_sbsxrsio] = { 3423 .flags = FL_BASE0, 3424 .num_ports = 8, 3425 .base_baud = 460800, 3426 .uart_offset = 256, 3427 .reg_shift = 4, 3428 }, 3429 /* 3430 * PA Semi PWRficient PA6T-1682M on-chip UART 3431 */ 3432 [pbn_pasemi_1682M] = { 3433 .flags = FL_BASE0, 3434 .num_ports = 1, 3435 .base_baud = 8333333, 3436 }, 3437 /* 3438 * National Instruments 843x 3439 */ 3440 [pbn_ni8430_16] = { 3441 .flags = FL_BASE0, 3442 .num_ports = 16, 3443 .base_baud = 3686400, 3444 .uart_offset = 0x10, 3445 .first_offset = 0x800, 3446 }, 3447 [pbn_ni8430_8] = { 3448 .flags = FL_BASE0, 3449 .num_ports = 8, 3450 .base_baud = 3686400, 3451 .uart_offset = 0x10, 3452 .first_offset = 0x800, 3453 }, 3454 [pbn_ni8430_4] = { 3455 .flags = FL_BASE0, 3456 .num_ports = 4, 3457 .base_baud = 3686400, 3458 .uart_offset = 0x10, 3459 .first_offset = 0x800, 3460 }, 3461 [pbn_ni8430_2] = { 3462 .flags = FL_BASE0, 3463 .num_ports = 2, 3464 .base_baud = 3686400, 3465 .uart_offset = 0x10, 3466 .first_offset = 0x800, 3467 }, 3468 /* 3469 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3470 */ 3471 [pbn_ADDIDATA_PCIe_1_3906250] = { 3472 .flags = FL_BASE0, 3473 .num_ports = 1, 3474 .base_baud = 3906250, 3475 .uart_offset = 0x200, 3476 .first_offset = 0x1000, 3477 }, 3478 [pbn_ADDIDATA_PCIe_2_3906250] = { 3479 .flags = FL_BASE0, 3480 .num_ports = 2, 3481 .base_baud = 3906250, 3482 .uart_offset = 0x200, 3483 .first_offset = 0x1000, 3484 }, 3485 [pbn_ADDIDATA_PCIe_4_3906250] = { 3486 .flags = FL_BASE0, 3487 .num_ports = 4, 3488 .base_baud = 3906250, 3489 .uart_offset = 0x200, 3490 .first_offset = 0x1000, 3491 }, 3492 [pbn_ADDIDATA_PCIe_8_3906250] = { 3493 .flags = FL_BASE0, 3494 .num_ports = 8, 3495 .base_baud = 3906250, 3496 .uart_offset = 0x200, 3497 .first_offset = 0x1000, 3498 }, 3499 [pbn_ce4100_1_115200] = { 3500 .flags = FL_BASE_BARS, 3501 .num_ports = 2, 3502 .base_baud = 921600, 3503 .reg_shift = 2, 3504 }, 3505 [pbn_omegapci] = { 3506 .flags = FL_BASE0, 3507 .num_ports = 8, 3508 .base_baud = 115200, 3509 .uart_offset = 0x200, 3510 }, 3511 [pbn_NETMOS9900_2s_115200] = { 3512 .flags = FL_BASE0, 3513 .num_ports = 2, 3514 .base_baud = 115200, 3515 }, 3516 [pbn_brcm_trumanage] = { 3517 .flags = FL_BASE0, 3518 .num_ports = 1, 3519 .reg_shift = 2, 3520 .base_baud = 115200, 3521 }, 3522 [pbn_fintek_4] = { 3523 .num_ports = 4, 3524 .uart_offset = 8, 3525 .base_baud = 115200, 3526 .first_offset = 0x40, 3527 }, 3528 [pbn_fintek_8] = { 3529 .num_ports = 8, 3530 .uart_offset = 8, 3531 .base_baud = 115200, 3532 .first_offset = 0x40, 3533 }, 3534 [pbn_fintek_12] = { 3535 .num_ports = 12, 3536 .uart_offset = 8, 3537 .base_baud = 115200, 3538 .first_offset = 0x40, 3539 }, 3540 [pbn_fintek_F81504A] = { 3541 .num_ports = 4, 3542 .uart_offset = 8, 3543 .base_baud = 115200, 3544 }, 3545 [pbn_fintek_F81508A] = { 3546 .num_ports = 8, 3547 .uart_offset = 8, 3548 .base_baud = 115200, 3549 }, 3550 [pbn_fintek_F81512A] = { 3551 .num_ports = 12, 3552 .uart_offset = 8, 3553 .base_baud = 115200, 3554 }, 3555 [pbn_wch382_2] = { 3556 .flags = FL_BASE0, 3557 .num_ports = 2, 3558 .base_baud = 115200, 3559 .uart_offset = 8, 3560 .first_offset = 0xC0, 3561 }, 3562 [pbn_wch384_4] = { 3563 .flags = FL_BASE0, 3564 .num_ports = 4, 3565 .base_baud = 115200, 3566 .uart_offset = 8, 3567 .first_offset = 0xC0, 3568 }, 3569 [pbn_wch384_8] = { 3570 .flags = FL_BASE0, 3571 .num_ports = 8, 3572 .base_baud = 115200, 3573 .uart_offset = 8, 3574 .first_offset = 0x00, 3575 }, 3576 [pbn_sunix_pci_1s] = { 3577 .num_ports = 1, 3578 .base_baud = 921600, 3579 .uart_offset = 0x8, 3580 }, 3581 [pbn_sunix_pci_2s] = { 3582 .num_ports = 2, 3583 .base_baud = 921600, 3584 .uart_offset = 0x8, 3585 }, 3586 [pbn_sunix_pci_4s] = { 3587 .num_ports = 4, 3588 .base_baud = 921600, 3589 .uart_offset = 0x8, 3590 }, 3591 [pbn_sunix_pci_8s] = { 3592 .num_ports = 8, 3593 .base_baud = 921600, 3594 .uart_offset = 0x8, 3595 }, 3596 [pbn_sunix_pci_16s] = { 3597 .num_ports = 16, 3598 .base_baud = 921600, 3599 .uart_offset = 0x8, 3600 }, 3601 [pbn_titan_1_4000000] = { 3602 .flags = FL_BASE0, 3603 .num_ports = 1, 3604 .base_baud = 4000000, 3605 .uart_offset = 0x200, 3606 .first_offset = 0x1000, 3607 }, 3608 [pbn_titan_2_4000000] = { 3609 .flags = FL_BASE0, 3610 .num_ports = 2, 3611 .base_baud = 4000000, 3612 .uart_offset = 0x200, 3613 .first_offset = 0x1000, 3614 }, 3615 [pbn_titan_4_4000000] = { 3616 .flags = FL_BASE0, 3617 .num_ports = 4, 3618 .base_baud = 4000000, 3619 .uart_offset = 0x200, 3620 .first_offset = 0x1000, 3621 }, 3622 [pbn_titan_8_4000000] = { 3623 .flags = FL_BASE0, 3624 .num_ports = 8, 3625 .base_baud = 4000000, 3626 .uart_offset = 0x200, 3627 .first_offset = 0x1000, 3628 }, 3629 [pbn_moxa8250_2p] = { 3630 .flags = FL_BASE1, 3631 .num_ports = 2, 3632 .base_baud = 921600, 3633 .uart_offset = 0x200, 3634 }, 3635 [pbn_moxa8250_4p] = { 3636 .flags = FL_BASE1, 3637 .num_ports = 4, 3638 .base_baud = 921600, 3639 .uart_offset = 0x200, 3640 }, 3641 [pbn_moxa8250_8p] = { 3642 .flags = FL_BASE1, 3643 .num_ports = 8, 3644 .base_baud = 921600, 3645 .uart_offset = 0x200, 3646 }, 3647 }; 3648 3649 #define REPORT_CONFIG(option) \ 3650 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3651 #define REPORT_8250_CONFIG(option) \ 3652 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3653 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3654 3655 static const struct pci_device_id blacklist[] = { 3656 /* softmodems */ 3657 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3658 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3659 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3660 3661 /* multi-io cards handled by parport_serial */ 3662 /* WCH CH353 2S1P */ 3663 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3664 /* WCH CH353 1S1P */ 3665 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3666 /* WCH CH382 2S1P */ 3667 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3668 3669 /* Intel platforms with MID UART */ 3670 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3671 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3672 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3673 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3674 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3675 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3676 3677 /* Intel platforms with DesignWare UART */ 3678 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3679 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3680 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3681 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3682 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3683 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3684 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3685 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3686 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3687 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3688 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3689 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3690 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3691 3692 /* Exar devices */ 3693 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3694 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3695 3696 /* Pericom devices */ 3697 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3698 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3699 3700 /* End of the black list */ 3701 { } 3702 }; 3703 3704 static int serial_pci_is_class_communication(struct pci_dev *dev) 3705 { 3706 /* 3707 * If it is not a communications device or the programming 3708 * interface is greater than 6, give up. 3709 */ 3710 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3711 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3712 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3713 (dev->class & 0xff) > 6) 3714 return -ENODEV; 3715 3716 return 0; 3717 } 3718 3719 /* 3720 * Given a complete unknown PCI device, try to use some heuristics to 3721 * guess what the configuration might be, based on the pitiful PCI 3722 * serial specs. Returns 0 on success, -ENODEV on failure. 3723 */ 3724 static int 3725 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3726 { 3727 int num_iomem, num_port, first_port = -1, i; 3728 int rc; 3729 3730 rc = serial_pci_is_class_communication(dev); 3731 if (rc) 3732 return rc; 3733 3734 /* 3735 * Should we try to make guesses for multiport serial devices later? 3736 */ 3737 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3738 return -ENODEV; 3739 3740 num_iomem = num_port = 0; 3741 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3742 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3743 num_port++; 3744 if (first_port == -1) 3745 first_port = i; 3746 } 3747 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3748 num_iomem++; 3749 } 3750 3751 /* 3752 * If there is 1 or 0 iomem regions, and exactly one port, 3753 * use it. We guess the number of ports based on the IO 3754 * region size. 3755 */ 3756 if (num_iomem <= 1 && num_port == 1) { 3757 board->flags = first_port; 3758 board->num_ports = pci_resource_len(dev, first_port) / 8; 3759 return 0; 3760 } 3761 3762 /* 3763 * Now guess if we've got a board which indexes by BARs. 3764 * Each IO BAR should be 8 bytes, and they should follow 3765 * consecutively. 3766 */ 3767 first_port = -1; 3768 num_port = 0; 3769 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3770 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3771 pci_resource_len(dev, i) == 8 && 3772 (first_port == -1 || (first_port + num_port) == i)) { 3773 num_port++; 3774 if (first_port == -1) 3775 first_port = i; 3776 } 3777 } 3778 3779 if (num_port > 1) { 3780 board->flags = first_port | FL_BASE_BARS; 3781 board->num_ports = num_port; 3782 return 0; 3783 } 3784 3785 return -ENODEV; 3786 } 3787 3788 static inline int 3789 serial_pci_matches(const struct pciserial_board *board, 3790 const struct pciserial_board *guessed) 3791 { 3792 return 3793 board->num_ports == guessed->num_ports && 3794 board->base_baud == guessed->base_baud && 3795 board->uart_offset == guessed->uart_offset && 3796 board->reg_shift == guessed->reg_shift && 3797 board->first_offset == guessed->first_offset; 3798 } 3799 3800 struct serial_private * 3801 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3802 { 3803 struct uart_8250_port uart; 3804 struct serial_private *priv; 3805 struct pci_serial_quirk *quirk; 3806 int rc, nr_ports, i; 3807 3808 nr_ports = board->num_ports; 3809 3810 /* 3811 * Find an init and setup quirks. 3812 */ 3813 quirk = find_quirk(dev); 3814 3815 /* 3816 * Run the new-style initialization function. 3817 * The initialization function returns: 3818 * <0 - error 3819 * 0 - use board->num_ports 3820 * >0 - number of ports 3821 */ 3822 if (quirk->init) { 3823 rc = quirk->init(dev); 3824 if (rc < 0) { 3825 priv = ERR_PTR(rc); 3826 goto err_out; 3827 } 3828 if (rc) 3829 nr_ports = rc; 3830 } 3831 3832 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3833 if (!priv) { 3834 priv = ERR_PTR(-ENOMEM); 3835 goto err_deinit; 3836 } 3837 3838 priv->dev = dev; 3839 priv->quirk = quirk; 3840 3841 memset(&uart, 0, sizeof(uart)); 3842 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3843 uart.port.uartclk = board->base_baud * 16; 3844 3845 if (board->flags & FL_NOIRQ) { 3846 uart.port.irq = 0; 3847 } else { 3848 if (pci_match_id(pci_use_msi, dev)) { 3849 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3850 pci_set_master(dev); 3851 uart.port.flags &= ~UPF_SHARE_IRQ; 3852 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3853 } else { 3854 pci_dbg(dev, "Using legacy interrupts\n"); 3855 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3856 } 3857 if (rc < 0) { 3858 kfree(priv); 3859 priv = ERR_PTR(rc); 3860 goto err_deinit; 3861 } 3862 3863 uart.port.irq = pci_irq_vector(dev, 0); 3864 } 3865 3866 uart.port.dev = &dev->dev; 3867 3868 for (i = 0; i < nr_ports; i++) { 3869 if (quirk->setup(priv, board, &uart, i)) 3870 break; 3871 3872 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3873 uart.port.iobase, uart.port.irq, uart.port.iotype); 3874 3875 priv->line[i] = serial8250_register_8250_port(&uart); 3876 if (priv->line[i] < 0) { 3877 pci_err(dev, 3878 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3879 uart.port.iobase, uart.port.irq, 3880 uart.port.iotype, priv->line[i]); 3881 break; 3882 } 3883 } 3884 priv->nr = i; 3885 priv->board = board; 3886 return priv; 3887 3888 err_deinit: 3889 if (quirk->exit) 3890 quirk->exit(dev); 3891 err_out: 3892 return priv; 3893 } 3894 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3895 3896 static void pciserial_detach_ports(struct serial_private *priv) 3897 { 3898 struct pci_serial_quirk *quirk; 3899 int i; 3900 3901 for (i = 0; i < priv->nr; i++) 3902 serial8250_unregister_port(priv->line[i]); 3903 3904 /* 3905 * Find the exit quirks. 3906 */ 3907 quirk = find_quirk(priv->dev); 3908 if (quirk->exit) 3909 quirk->exit(priv->dev); 3910 } 3911 3912 void pciserial_remove_ports(struct serial_private *priv) 3913 { 3914 pciserial_detach_ports(priv); 3915 kfree(priv); 3916 } 3917 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3918 3919 void pciserial_suspend_ports(struct serial_private *priv) 3920 { 3921 int i; 3922 3923 for (i = 0; i < priv->nr; i++) 3924 if (priv->line[i] >= 0) 3925 serial8250_suspend_port(priv->line[i]); 3926 3927 /* 3928 * Ensure that every init quirk is properly torn down 3929 */ 3930 if (priv->quirk->exit) 3931 priv->quirk->exit(priv->dev); 3932 } 3933 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3934 3935 void pciserial_resume_ports(struct serial_private *priv) 3936 { 3937 int i; 3938 3939 /* 3940 * Ensure that the board is correctly configured. 3941 */ 3942 if (priv->quirk->init) 3943 priv->quirk->init(priv->dev); 3944 3945 for (i = 0; i < priv->nr; i++) 3946 if (priv->line[i] >= 0) 3947 serial8250_resume_port(priv->line[i]); 3948 } 3949 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3950 3951 /* 3952 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3953 * to the arrangement of serial ports on a PCI card. 3954 */ 3955 static int 3956 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3957 { 3958 struct pci_serial_quirk *quirk; 3959 struct serial_private *priv; 3960 const struct pciserial_board *board; 3961 const struct pci_device_id *exclude; 3962 struct pciserial_board tmp; 3963 int rc; 3964 3965 quirk = find_quirk(dev); 3966 if (quirk->probe) { 3967 rc = quirk->probe(dev); 3968 if (rc) 3969 return rc; 3970 } 3971 3972 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3973 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 3974 return -EINVAL; 3975 } 3976 3977 board = &pci_boards[ent->driver_data]; 3978 3979 exclude = pci_match_id(blacklist, dev); 3980 if (exclude) { 3981 if (exclude->driver_data) 3982 pci_warn(dev, "ignoring port, enable %s to handle\n", 3983 (const char *)exclude->driver_data); 3984 return -ENODEV; 3985 } 3986 3987 rc = pcim_enable_device(dev); 3988 pci_save_state(dev); 3989 if (rc) 3990 return rc; 3991 3992 if (ent->driver_data == pbn_default) { 3993 /* 3994 * Use a copy of the pci_board entry for this; 3995 * avoid changing entries in the table. 3996 */ 3997 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3998 board = &tmp; 3999 4000 /* 4001 * We matched one of our class entries. Try to 4002 * determine the parameters of this board. 4003 */ 4004 rc = serial_pci_guess_board(dev, &tmp); 4005 if (rc) 4006 return rc; 4007 } else { 4008 /* 4009 * We matched an explicit entry. If we are able to 4010 * detect this boards settings with our heuristic, 4011 * then we no longer need this entry. 4012 */ 4013 memcpy(&tmp, &pci_boards[pbn_default], 4014 sizeof(struct pciserial_board)); 4015 rc = serial_pci_guess_board(dev, &tmp); 4016 if (rc == 0 && serial_pci_matches(board, &tmp)) 4017 moan_device("Redundant entry in serial pci_table.", 4018 dev); 4019 } 4020 4021 priv = pciserial_init_ports(dev, board); 4022 if (IS_ERR(priv)) 4023 return PTR_ERR(priv); 4024 4025 pci_set_drvdata(dev, priv); 4026 return 0; 4027 } 4028 4029 static void pciserial_remove_one(struct pci_dev *dev) 4030 { 4031 struct serial_private *priv = pci_get_drvdata(dev); 4032 4033 pciserial_remove_ports(priv); 4034 } 4035 4036 #ifdef CONFIG_PM_SLEEP 4037 static int pciserial_suspend_one(struct device *dev) 4038 { 4039 struct serial_private *priv = dev_get_drvdata(dev); 4040 4041 if (priv) 4042 pciserial_suspend_ports(priv); 4043 4044 return 0; 4045 } 4046 4047 static int pciserial_resume_one(struct device *dev) 4048 { 4049 struct pci_dev *pdev = to_pci_dev(dev); 4050 struct serial_private *priv = pci_get_drvdata(pdev); 4051 int err; 4052 4053 if (priv) { 4054 /* 4055 * The device may have been disabled. Re-enable it. 4056 */ 4057 err = pci_enable_device(pdev); 4058 /* FIXME: We cannot simply error out here */ 4059 if (err) 4060 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4061 pciserial_resume_ports(priv); 4062 } 4063 return 0; 4064 } 4065 #endif 4066 4067 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4068 pciserial_resume_one); 4069 4070 static const struct pci_device_id serial_pci_tbl[] = { 4071 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4072 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4073 pbn_b0_4_921600 }, 4074 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4075 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4076 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4077 pbn_b2_8_921600 }, 4078 /* Advantech also use 0x3618 and 0xf618 */ 4079 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4080 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4081 pbn_b0_4_921600 }, 4082 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4083 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4084 pbn_b0_4_921600 }, 4085 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4086 PCI_SUBVENDOR_ID_CONNECT_TECH, 4087 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4088 pbn_b1_8_1382400 }, 4089 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4090 PCI_SUBVENDOR_ID_CONNECT_TECH, 4091 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4092 pbn_b1_4_1382400 }, 4093 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4094 PCI_SUBVENDOR_ID_CONNECT_TECH, 4095 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4096 pbn_b1_2_1382400 }, 4097 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4098 PCI_SUBVENDOR_ID_CONNECT_TECH, 4099 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4100 pbn_b1_8_1382400 }, 4101 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4102 PCI_SUBVENDOR_ID_CONNECT_TECH, 4103 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4104 pbn_b1_4_1382400 }, 4105 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4106 PCI_SUBVENDOR_ID_CONNECT_TECH, 4107 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4108 pbn_b1_2_1382400 }, 4109 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4110 PCI_SUBVENDOR_ID_CONNECT_TECH, 4111 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4112 pbn_b1_8_921600 }, 4113 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4114 PCI_SUBVENDOR_ID_CONNECT_TECH, 4115 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4116 pbn_b1_8_921600 }, 4117 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4118 PCI_SUBVENDOR_ID_CONNECT_TECH, 4119 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4120 pbn_b1_4_921600 }, 4121 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4122 PCI_SUBVENDOR_ID_CONNECT_TECH, 4123 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4124 pbn_b1_4_921600 }, 4125 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4126 PCI_SUBVENDOR_ID_CONNECT_TECH, 4127 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4128 pbn_b1_2_921600 }, 4129 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4130 PCI_SUBVENDOR_ID_CONNECT_TECH, 4131 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4132 pbn_b1_8_921600 }, 4133 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4134 PCI_SUBVENDOR_ID_CONNECT_TECH, 4135 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4136 pbn_b1_8_921600 }, 4137 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4138 PCI_SUBVENDOR_ID_CONNECT_TECH, 4139 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4140 pbn_b1_4_921600 }, 4141 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4142 PCI_SUBVENDOR_ID_CONNECT_TECH, 4143 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4144 pbn_b1_2_1250000 }, 4145 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4146 PCI_SUBVENDOR_ID_CONNECT_TECH, 4147 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4148 pbn_b0_2_1843200 }, 4149 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4150 PCI_SUBVENDOR_ID_CONNECT_TECH, 4151 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4152 pbn_b0_4_1843200 }, 4153 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4154 PCI_VENDOR_ID_AFAVLAB, 4155 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4156 pbn_b0_4_1152000 }, 4157 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4159 pbn_b2_bt_1_115200 }, 4160 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4162 pbn_b2_bt_2_115200 }, 4163 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4165 pbn_b2_bt_4_115200 }, 4166 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4168 pbn_b2_bt_2_115200 }, 4169 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4171 pbn_b2_bt_4_115200 }, 4172 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4174 pbn_b2_8_115200 }, 4175 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4177 pbn_b2_8_460800 }, 4178 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4180 pbn_b2_8_115200 }, 4181 4182 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4184 pbn_b2_bt_2_115200 }, 4185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4187 pbn_b2_bt_2_921600 }, 4188 /* 4189 * VScom SPCOM800, from sl@s.pl 4190 */ 4191 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4193 pbn_b2_8_921600 }, 4194 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b2_4_921600 }, 4197 /* Unknown card - subdevice 0x1584 */ 4198 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4199 PCI_VENDOR_ID_PLX, 4200 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4201 pbn_b2_4_115200 }, 4202 /* Unknown card - subdevice 0x1588 */ 4203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4204 PCI_VENDOR_ID_PLX, 4205 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4206 pbn_b2_8_115200 }, 4207 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4208 PCI_SUBVENDOR_ID_KEYSPAN, 4209 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4210 pbn_panacom }, 4211 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_panacom4 }, 4214 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4216 pbn_panacom2 }, 4217 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4218 PCI_VENDOR_ID_ESDGMBH, 4219 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4220 pbn_b2_4_115200 }, 4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4222 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4223 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4224 pbn_b2_4_460800 }, 4225 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4226 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4227 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4228 pbn_b2_8_460800 }, 4229 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4230 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4231 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4232 pbn_b2_16_460800 }, 4233 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4234 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4235 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4236 pbn_b2_16_460800 }, 4237 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4238 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4239 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4240 pbn_b2_4_460800 }, 4241 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4242 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4243 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4244 pbn_b2_8_460800 }, 4245 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4246 PCI_SUBVENDOR_ID_EXSYS, 4247 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4248 pbn_b2_4_115200 }, 4249 /* 4250 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4251 * (Exoray@isys.ca) 4252 */ 4253 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4254 0x10b5, 0x106a, 0, 0, 4255 pbn_plx_romulus }, 4256 /* 4257 * Quatech cards. These actually have configurable clocks but for 4258 * now we just use the default. 4259 * 4260 * 100 series are RS232, 200 series RS422, 4261 */ 4262 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4264 pbn_b1_4_115200 }, 4265 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4267 pbn_b1_2_115200 }, 4268 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4270 pbn_b2_2_115200 }, 4271 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4273 pbn_b1_2_115200 }, 4274 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4276 pbn_b2_2_115200 }, 4277 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4279 pbn_b1_4_115200 }, 4280 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4282 pbn_b1_8_115200 }, 4283 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4285 pbn_b1_8_115200 }, 4286 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4288 pbn_b1_4_115200 }, 4289 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4291 pbn_b1_2_115200 }, 4292 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4294 pbn_b1_4_115200 }, 4295 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4297 pbn_b1_2_115200 }, 4298 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4300 pbn_b2_4_115200 }, 4301 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_b2_2_115200 }, 4304 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_b2_1_115200 }, 4307 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4309 pbn_b2_4_115200 }, 4310 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4312 pbn_b2_2_115200 }, 4313 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_b2_1_115200 }, 4316 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4318 pbn_b0_8_115200 }, 4319 4320 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4321 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4322 0, 0, 4323 pbn_b0_4_921600 }, 4324 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4325 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4326 0, 0, 4327 pbn_b0_4_1152000 }, 4328 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_b0_bt_2_921600 }, 4331 4332 /* 4333 * The below card is a little controversial since it is the 4334 * subject of a PCI vendor/device ID clash. (See 4335 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4336 * For now just used the hex ID 0x950a. 4337 */ 4338 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4339 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4340 0, 0, pbn_b0_2_115200 }, 4341 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4342 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4343 0, 0, pbn_b0_2_115200 }, 4344 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_b0_2_1130000 }, 4347 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4348 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4349 pbn_b0_1_921600 }, 4350 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_b0_4_115200 }, 4353 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4355 pbn_b0_bt_2_921600 }, 4356 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4358 pbn_b2_8_1152000 }, 4359 4360 /* 4361 * Oxford Semiconductor Inc. Tornado PCI express device range. 4362 */ 4363 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4365 pbn_b0_1_15625000 }, 4366 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4368 pbn_b0_1_15625000 }, 4369 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4371 pbn_oxsemi_1_15625000 }, 4372 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4374 pbn_oxsemi_1_15625000 }, 4375 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4377 pbn_b0_1_15625000 }, 4378 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4380 pbn_b0_1_15625000 }, 4381 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4383 pbn_oxsemi_1_15625000 }, 4384 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4386 pbn_oxsemi_1_15625000 }, 4387 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4389 pbn_b0_1_15625000 }, 4390 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4392 pbn_b0_1_15625000 }, 4393 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4395 pbn_b0_1_15625000 }, 4396 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4398 pbn_b0_1_15625000 }, 4399 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_oxsemi_2_15625000 }, 4402 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_oxsemi_2_15625000 }, 4405 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_oxsemi_4_15625000 }, 4408 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_oxsemi_4_15625000 }, 4411 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_oxsemi_8_15625000 }, 4414 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_oxsemi_8_15625000 }, 4417 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_oxsemi_1_15625000 }, 4420 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_oxsemi_1_15625000 }, 4423 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_oxsemi_1_15625000 }, 4426 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_oxsemi_1_15625000 }, 4429 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_oxsemi_1_15625000 }, 4432 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_oxsemi_1_15625000 }, 4435 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_oxsemi_1_15625000 }, 4438 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_oxsemi_1_15625000 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_oxsemi_1_15625000 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_oxsemi_1_15625000 }, 4447 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_oxsemi_1_15625000 }, 4450 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_oxsemi_1_15625000 }, 4453 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_oxsemi_1_15625000 }, 4456 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_oxsemi_1_15625000 }, 4459 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_oxsemi_1_15625000 }, 4462 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_oxsemi_1_15625000 }, 4465 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_oxsemi_1_15625000 }, 4468 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_oxsemi_1_15625000 }, 4471 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_oxsemi_1_15625000 }, 4474 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4476 pbn_oxsemi_1_15625000 }, 4477 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4479 pbn_oxsemi_1_15625000 }, 4480 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4482 pbn_oxsemi_1_15625000 }, 4483 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_oxsemi_1_15625000 }, 4486 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_oxsemi_1_15625000 }, 4489 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_oxsemi_1_15625000 }, 4492 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_oxsemi_1_15625000 }, 4495 /* 4496 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4497 */ 4498 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4499 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4500 pbn_oxsemi_1_15625000 }, 4501 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4502 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4503 pbn_oxsemi_2_15625000 }, 4504 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4505 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4506 pbn_oxsemi_4_15625000 }, 4507 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4508 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4509 pbn_oxsemi_8_15625000 }, 4510 4511 /* 4512 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4513 */ 4514 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4515 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_2_15625000 }, 4517 /* 4518 * EndRun Technologies. PCI express device range. 4519 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4520 */ 4521 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_oxsemi_2_15625000 }, 4524 4525 /* 4526 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4527 * from skokodyn@yahoo.com 4528 */ 4529 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4530 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4531 pbn_sbsxrsio }, 4532 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4533 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4534 pbn_sbsxrsio }, 4535 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4536 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4537 pbn_sbsxrsio }, 4538 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4539 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4540 pbn_sbsxrsio }, 4541 4542 /* 4543 * Digitan DS560-558, from jimd@esoft.com 4544 */ 4545 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4547 pbn_b1_1_115200 }, 4548 4549 /* 4550 * Titan Electronic cards 4551 * The 400L and 800L have a custom setup quirk. 4552 */ 4553 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4555 pbn_b0_1_921600 }, 4556 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4558 pbn_b0_2_921600 }, 4559 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4561 pbn_b0_4_921600 }, 4562 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_b0_4_921600 }, 4565 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4567 pbn_b1_1_921600 }, 4568 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4570 pbn_b1_bt_2_921600 }, 4571 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_b0_bt_4_921600 }, 4574 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_b0_bt_8_921600 }, 4577 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_b4_bt_2_921600 }, 4580 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_b4_bt_4_921600 }, 4583 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_b4_bt_8_921600 }, 4586 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_b0_4_921600 }, 4589 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_b0_4_921600 }, 4592 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_b0_4_921600 }, 4595 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4597 pbn_titan_1_4000000 }, 4598 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_titan_2_4000000 }, 4601 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4603 pbn_titan_4_4000000 }, 4604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_titan_8_4000000 }, 4607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_titan_2_4000000 }, 4610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_titan_2_4000000 }, 4613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_b0_bt_2_921600 }, 4616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_b0_4_921600 }, 4619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_b0_4_921600 }, 4622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_b0_4_921600 }, 4625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_b0_4_921600 }, 4628 4629 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b2_1_460800 }, 4632 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_b2_1_460800 }, 4635 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b2_1_460800 }, 4638 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_b2_bt_2_921600 }, 4641 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_b2_bt_2_921600 }, 4644 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_b2_bt_2_921600 }, 4647 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_b2_bt_4_921600 }, 4650 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b2_bt_4_921600 }, 4653 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b2_bt_4_921600 }, 4656 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b0_1_921600 }, 4659 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_1_921600 }, 4662 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_1_921600 }, 4665 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b0_bt_2_921600 }, 4668 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b0_bt_2_921600 }, 4671 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b0_bt_2_921600 }, 4674 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b0_bt_4_921600 }, 4677 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b0_bt_4_921600 }, 4680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b0_bt_4_921600 }, 4683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b0_bt_8_921600 }, 4686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b0_bt_8_921600 }, 4689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b0_bt_8_921600 }, 4692 4693 /* 4694 * Computone devices submitted by Doug McNash dmcnash@computone.com 4695 */ 4696 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4697 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4698 0, 0, pbn_computone_4 }, 4699 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4700 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4701 0, 0, pbn_computone_8 }, 4702 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4703 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4704 0, 0, pbn_computone_6 }, 4705 4706 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_oxsemi }, 4709 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4710 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4711 pbn_b0_bt_1_921600 }, 4712 4713 /* 4714 * Sunix PCI serial boards 4715 */ 4716 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4717 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4718 pbn_sunix_pci_1s }, 4719 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4720 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4721 pbn_sunix_pci_2s }, 4722 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4723 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4724 pbn_sunix_pci_4s }, 4725 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4726 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4727 pbn_sunix_pci_4s }, 4728 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4729 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4730 pbn_sunix_pci_8s }, 4731 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4732 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4733 pbn_sunix_pci_8s }, 4734 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4735 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4736 pbn_sunix_pci_16s }, 4737 4738 /* 4739 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4740 */ 4741 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_b0_bt_8_115200 }, 4744 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4746 pbn_b0_bt_8_115200 }, 4747 4748 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4750 pbn_b0_bt_2_115200 }, 4751 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4753 pbn_b0_bt_2_115200 }, 4754 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_b0_bt_2_115200 }, 4757 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_b0_bt_2_115200 }, 4760 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_b0_bt_2_115200 }, 4763 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_b0_bt_4_460800 }, 4766 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_b0_bt_4_460800 }, 4769 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_b0_bt_2_460800 }, 4772 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_b0_bt_2_460800 }, 4775 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_b0_bt_2_460800 }, 4778 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_b0_bt_1_115200 }, 4781 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_b0_bt_1_460800 }, 4784 4785 /* 4786 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4787 * Cards are identified by their subsystem vendor IDs, which 4788 * (in hex) match the model number. 4789 * 4790 * Note that JC140x are RS422/485 cards which require ox950 4791 * ACR = 0x10, and as such are not currently fully supported. 4792 */ 4793 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4794 0x1204, 0x0004, 0, 0, 4795 pbn_b0_4_921600 }, 4796 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4797 0x1208, 0x0004, 0, 0, 4798 pbn_b0_4_921600 }, 4799 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4800 0x1402, 0x0002, 0, 0, 4801 pbn_b0_2_921600 }, */ 4802 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4803 0x1404, 0x0004, 0, 0, 4804 pbn_b0_4_921600 }, */ 4805 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4806 0x1208, 0x0004, 0, 0, 4807 pbn_b0_4_921600 }, 4808 4809 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4810 0x1204, 0x0004, 0, 0, 4811 pbn_b0_4_921600 }, 4812 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4813 0x1208, 0x0004, 0, 0, 4814 pbn_b0_4_921600 }, 4815 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4816 0x1208, 0x0004, 0, 0, 4817 pbn_b0_4_921600 }, 4818 /* 4819 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4820 */ 4821 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4822 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4823 pbn_b1_1_1382400 }, 4824 4825 /* 4826 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4827 */ 4828 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4829 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4830 pbn_b1_1_1382400 }, 4831 4832 /* 4833 * RAStel 2 port modem, gerg@moreton.com.au 4834 */ 4835 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4837 pbn_b2_bt_2_115200 }, 4838 4839 /* 4840 * EKF addition for i960 Boards form EKF with serial port 4841 */ 4842 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4843 0xE4BF, PCI_ANY_ID, 0, 0, 4844 pbn_intel_i960 }, 4845 4846 /* 4847 * Xircom Cardbus/Ethernet combos 4848 */ 4849 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4851 pbn_b0_1_115200 }, 4852 /* 4853 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4854 */ 4855 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4857 pbn_b0_1_115200 }, 4858 4859 /* 4860 * Untested PCI modems, sent in from various folks... 4861 */ 4862 4863 /* 4864 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4865 */ 4866 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4867 0x1048, 0x1500, 0, 0, 4868 pbn_b1_1_115200 }, 4869 4870 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4871 0xFF00, 0, 0, 0, 4872 pbn_sgi_ioc3 }, 4873 4874 /* 4875 * HP Diva card 4876 */ 4877 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4878 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4879 pbn_b1_1_115200 }, 4880 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4882 pbn_b0_5_115200 }, 4883 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4885 pbn_b2_1_115200 }, 4886 /* HPE PCI serial device */ 4887 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4889 pbn_b1_1_115200 }, 4890 4891 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4893 pbn_b3_2_115200 }, 4894 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4896 pbn_b3_4_115200 }, 4897 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4899 pbn_b3_8_115200 }, 4900 /* 4901 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4902 */ 4903 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4905 pbn_b0_1_115200 }, 4906 /* 4907 * ITE 4908 */ 4909 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4910 PCI_ANY_ID, PCI_ANY_ID, 4911 0, 0, 4912 pbn_b1_bt_1_115200 }, 4913 4914 /* 4915 * IntaShield IS-200 4916 */ 4917 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4919 pbn_b2_2_115200 }, 4920 /* 4921 * IntaShield IS-400 4922 */ 4923 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4925 pbn_b2_4_115200 }, 4926 /* Brainboxes Devices */ 4927 /* 4928 * Brainboxes UC-101 4929 */ 4930 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4931 PCI_ANY_ID, PCI_ANY_ID, 4932 0, 0, 4933 pbn_b2_2_115200 }, 4934 /* 4935 * Brainboxes UC-235/246 4936 */ 4937 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4938 PCI_ANY_ID, PCI_ANY_ID, 4939 0, 0, 4940 pbn_b2_1_115200 }, 4941 /* 4942 * Brainboxes UC-257 4943 */ 4944 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4945 PCI_ANY_ID, PCI_ANY_ID, 4946 0, 0, 4947 pbn_b2_2_115200 }, 4948 /* 4949 * Brainboxes UC-260/271/701/756 4950 */ 4951 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4952 PCI_ANY_ID, PCI_ANY_ID, 4953 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4954 pbn_b2_4_115200 }, 4955 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4956 PCI_ANY_ID, PCI_ANY_ID, 4957 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4958 pbn_b2_4_115200 }, 4959 /* 4960 * Brainboxes UC-268 4961 */ 4962 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4963 PCI_ANY_ID, PCI_ANY_ID, 4964 0, 0, 4965 pbn_b2_4_115200 }, 4966 /* 4967 * Brainboxes UC-275/279 4968 */ 4969 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 4970 PCI_ANY_ID, PCI_ANY_ID, 4971 0, 0, 4972 pbn_b2_8_115200 }, 4973 /* 4974 * Brainboxes UC-302 4975 */ 4976 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 4977 PCI_ANY_ID, PCI_ANY_ID, 4978 0, 0, 4979 pbn_b2_2_115200 }, 4980 /* 4981 * Brainboxes UC-310 4982 */ 4983 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 4984 PCI_ANY_ID, PCI_ANY_ID, 4985 0, 0, 4986 pbn_b2_2_115200 }, 4987 /* 4988 * Brainboxes UC-313 4989 */ 4990 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 4991 PCI_ANY_ID, PCI_ANY_ID, 4992 0, 0, 4993 pbn_b2_2_115200 }, 4994 /* 4995 * Brainboxes UC-320/324 4996 */ 4997 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 4998 PCI_ANY_ID, PCI_ANY_ID, 4999 0, 0, 5000 pbn_b2_1_115200 }, 5001 /* 5002 * Brainboxes UC-346 5003 */ 5004 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5005 PCI_ANY_ID, PCI_ANY_ID, 5006 0, 0, 5007 pbn_b2_4_115200 }, 5008 /* 5009 * Brainboxes UC-357 5010 */ 5011 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5012 PCI_ANY_ID, PCI_ANY_ID, 5013 0, 0, 5014 pbn_b2_2_115200 }, 5015 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5016 PCI_ANY_ID, PCI_ANY_ID, 5017 0, 0, 5018 pbn_b2_2_115200 }, 5019 /* 5020 * Brainboxes UC-368 5021 */ 5022 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5023 PCI_ANY_ID, PCI_ANY_ID, 5024 0, 0, 5025 pbn_b2_4_115200 }, 5026 /* 5027 * Brainboxes UC-420/431 5028 */ 5029 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5030 PCI_ANY_ID, PCI_ANY_ID, 5031 0, 0, 5032 pbn_b2_4_115200 }, 5033 /* 5034 * Brainboxes PX-101 5035 */ 5036 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5037 PCI_ANY_ID, PCI_ANY_ID, 5038 0, 0, 5039 pbn_b0_2_115200 }, 5040 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5041 PCI_ANY_ID, PCI_ANY_ID, 5042 0, 0, 5043 pbn_oxsemi_2_15625000 }, 5044 /* 5045 * Brainboxes PX-235/246 5046 */ 5047 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5048 PCI_ANY_ID, PCI_ANY_ID, 5049 0, 0, 5050 pbn_b0_1_115200 }, 5051 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5052 PCI_ANY_ID, PCI_ANY_ID, 5053 0, 0, 5054 pbn_oxsemi_1_15625000 }, 5055 /* 5056 * Brainboxes PX-203/PX-257 5057 */ 5058 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5059 PCI_ANY_ID, PCI_ANY_ID, 5060 0, 0, 5061 pbn_b0_2_115200 }, 5062 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5063 PCI_ANY_ID, PCI_ANY_ID, 5064 0, 0, 5065 pbn_oxsemi_4_15625000 }, 5066 /* 5067 * Brainboxes PX-260/PX-701 5068 */ 5069 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5070 PCI_ANY_ID, PCI_ANY_ID, 5071 0, 0, 5072 pbn_oxsemi_4_15625000 }, 5073 /* 5074 * Brainboxes PX-310 5075 */ 5076 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5077 PCI_ANY_ID, PCI_ANY_ID, 5078 0, 0, 5079 pbn_oxsemi_2_15625000 }, 5080 /* 5081 * Brainboxes PX-313 5082 */ 5083 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5084 PCI_ANY_ID, PCI_ANY_ID, 5085 0, 0, 5086 pbn_oxsemi_2_15625000 }, 5087 /* 5088 * Brainboxes PX-320/324/PX-376/PX-387 5089 */ 5090 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5091 PCI_ANY_ID, PCI_ANY_ID, 5092 0, 0, 5093 pbn_oxsemi_1_15625000 }, 5094 /* 5095 * Brainboxes PX-335/346 5096 */ 5097 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5098 PCI_ANY_ID, PCI_ANY_ID, 5099 0, 0, 5100 pbn_oxsemi_4_15625000 }, 5101 /* 5102 * Brainboxes PX-368 5103 */ 5104 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5105 PCI_ANY_ID, PCI_ANY_ID, 5106 0, 0, 5107 pbn_oxsemi_4_15625000 }, 5108 /* 5109 * Brainboxes PX-420 5110 */ 5111 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5112 PCI_ANY_ID, PCI_ANY_ID, 5113 0, 0, 5114 pbn_b0_4_115200 }, 5115 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5116 PCI_ANY_ID, PCI_ANY_ID, 5117 0, 0, 5118 pbn_oxsemi_4_15625000 }, 5119 /* 5120 * Brainboxes PX-803 5121 */ 5122 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5123 PCI_ANY_ID, PCI_ANY_ID, 5124 0, 0, 5125 pbn_b0_1_115200 }, 5126 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5127 PCI_ANY_ID, PCI_ANY_ID, 5128 0, 0, 5129 pbn_oxsemi_1_15625000 }, 5130 /* 5131 * Brainboxes PX-846 5132 */ 5133 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5134 PCI_ANY_ID, PCI_ANY_ID, 5135 0, 0, 5136 pbn_b0_1_115200 }, 5137 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5138 PCI_ANY_ID, PCI_ANY_ID, 5139 0, 0, 5140 pbn_oxsemi_1_15625000 }, 5141 5142 /* 5143 * Perle PCI-RAS cards 5144 */ 5145 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5146 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5147 0, 0, pbn_b2_4_921600 }, 5148 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5149 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5150 0, 0, pbn_b2_8_921600 }, 5151 5152 /* 5153 * Mainpine series cards: Fairly standard layout but fools 5154 * parts of the autodetect in some cases and uses otherwise 5155 * unmatched communications subclasses in the PCI Express case 5156 */ 5157 5158 { /* RockForceDUO */ 5159 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5160 PCI_VENDOR_ID_MAINPINE, 0x0200, 5161 0, 0, pbn_b0_2_115200 }, 5162 { /* RockForceQUATRO */ 5163 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5164 PCI_VENDOR_ID_MAINPINE, 0x0300, 5165 0, 0, pbn_b0_4_115200 }, 5166 { /* RockForceDUO+ */ 5167 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5168 PCI_VENDOR_ID_MAINPINE, 0x0400, 5169 0, 0, pbn_b0_2_115200 }, 5170 { /* RockForceQUATRO+ */ 5171 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5172 PCI_VENDOR_ID_MAINPINE, 0x0500, 5173 0, 0, pbn_b0_4_115200 }, 5174 { /* RockForce+ */ 5175 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5176 PCI_VENDOR_ID_MAINPINE, 0x0600, 5177 0, 0, pbn_b0_2_115200 }, 5178 { /* RockForce+ */ 5179 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5180 PCI_VENDOR_ID_MAINPINE, 0x0700, 5181 0, 0, pbn_b0_4_115200 }, 5182 { /* RockForceOCTO+ */ 5183 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5184 PCI_VENDOR_ID_MAINPINE, 0x0800, 5185 0, 0, pbn_b0_8_115200 }, 5186 { /* RockForceDUO+ */ 5187 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5188 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5189 0, 0, pbn_b0_2_115200 }, 5190 { /* RockForceQUARTRO+ */ 5191 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5192 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5193 0, 0, pbn_b0_4_115200 }, 5194 { /* RockForceOCTO+ */ 5195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5196 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5197 0, 0, pbn_b0_8_115200 }, 5198 { /* RockForceD1 */ 5199 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5200 PCI_VENDOR_ID_MAINPINE, 0x2000, 5201 0, 0, pbn_b0_1_115200 }, 5202 { /* RockForceF1 */ 5203 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5204 PCI_VENDOR_ID_MAINPINE, 0x2100, 5205 0, 0, pbn_b0_1_115200 }, 5206 { /* RockForceD2 */ 5207 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5208 PCI_VENDOR_ID_MAINPINE, 0x2200, 5209 0, 0, pbn_b0_2_115200 }, 5210 { /* RockForceF2 */ 5211 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5212 PCI_VENDOR_ID_MAINPINE, 0x2300, 5213 0, 0, pbn_b0_2_115200 }, 5214 { /* RockForceD4 */ 5215 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5216 PCI_VENDOR_ID_MAINPINE, 0x2400, 5217 0, 0, pbn_b0_4_115200 }, 5218 { /* RockForceF4 */ 5219 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5220 PCI_VENDOR_ID_MAINPINE, 0x2500, 5221 0, 0, pbn_b0_4_115200 }, 5222 { /* RockForceD8 */ 5223 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5224 PCI_VENDOR_ID_MAINPINE, 0x2600, 5225 0, 0, pbn_b0_8_115200 }, 5226 { /* RockForceF8 */ 5227 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5228 PCI_VENDOR_ID_MAINPINE, 0x2700, 5229 0, 0, pbn_b0_8_115200 }, 5230 { /* IQ Express D1 */ 5231 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5232 PCI_VENDOR_ID_MAINPINE, 0x3000, 5233 0, 0, pbn_b0_1_115200 }, 5234 { /* IQ Express F1 */ 5235 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5236 PCI_VENDOR_ID_MAINPINE, 0x3100, 5237 0, 0, pbn_b0_1_115200 }, 5238 { /* IQ Express D2 */ 5239 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5240 PCI_VENDOR_ID_MAINPINE, 0x3200, 5241 0, 0, pbn_b0_2_115200 }, 5242 { /* IQ Express F2 */ 5243 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5244 PCI_VENDOR_ID_MAINPINE, 0x3300, 5245 0, 0, pbn_b0_2_115200 }, 5246 { /* IQ Express D4 */ 5247 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5248 PCI_VENDOR_ID_MAINPINE, 0x3400, 5249 0, 0, pbn_b0_4_115200 }, 5250 { /* IQ Express F4 */ 5251 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5252 PCI_VENDOR_ID_MAINPINE, 0x3500, 5253 0, 0, pbn_b0_4_115200 }, 5254 { /* IQ Express D8 */ 5255 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5256 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5257 0, 0, pbn_b0_8_115200 }, 5258 { /* IQ Express F8 */ 5259 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5260 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5261 0, 0, pbn_b0_8_115200 }, 5262 5263 5264 /* 5265 * PA Semi PA6T-1682M on-chip UART 5266 */ 5267 { PCI_VENDOR_ID_PASEMI, 0xa004, 5268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5269 pbn_pasemi_1682M }, 5270 5271 /* 5272 * National Instruments 5273 */ 5274 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5275 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5276 pbn_b1_16_115200 }, 5277 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5279 pbn_b1_8_115200 }, 5280 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5281 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5282 pbn_b1_bt_4_115200 }, 5283 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5285 pbn_b1_bt_2_115200 }, 5286 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5288 pbn_b1_bt_4_115200 }, 5289 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5291 pbn_b1_bt_2_115200 }, 5292 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5293 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5294 pbn_b1_16_115200 }, 5295 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5297 pbn_b1_8_115200 }, 5298 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5300 pbn_b1_bt_4_115200 }, 5301 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5303 pbn_b1_bt_2_115200 }, 5304 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5306 pbn_b1_bt_4_115200 }, 5307 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5309 pbn_b1_bt_2_115200 }, 5310 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5312 pbn_ni8430_2 }, 5313 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5315 pbn_ni8430_2 }, 5316 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5318 pbn_ni8430_4 }, 5319 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5321 pbn_ni8430_4 }, 5322 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5324 pbn_ni8430_8 }, 5325 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5327 pbn_ni8430_8 }, 5328 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5330 pbn_ni8430_16 }, 5331 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5333 pbn_ni8430_16 }, 5334 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5336 pbn_ni8430_2 }, 5337 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5339 pbn_ni8430_2 }, 5340 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5342 pbn_ni8430_4 }, 5343 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5345 pbn_ni8430_4 }, 5346 5347 /* 5348 * MOXA 5349 */ 5350 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5352 pbn_moxa8250_2p }, 5353 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5355 pbn_moxa8250_2p }, 5356 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5358 pbn_moxa8250_4p }, 5359 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5361 pbn_moxa8250_4p }, 5362 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5364 pbn_moxa8250_8p }, 5365 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5367 pbn_moxa8250_8p }, 5368 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5370 pbn_moxa8250_8p }, 5371 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5373 pbn_moxa8250_8p }, 5374 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5376 pbn_moxa8250_2p }, 5377 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5379 pbn_moxa8250_4p }, 5380 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5382 pbn_moxa8250_8p }, 5383 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5385 pbn_moxa8250_8p }, 5386 5387 /* 5388 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5389 */ 5390 { PCI_VENDOR_ID_ADDIDATA, 5391 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5392 PCI_ANY_ID, 5393 PCI_ANY_ID, 5394 0, 5395 0, 5396 pbn_b0_4_115200 }, 5397 5398 { PCI_VENDOR_ID_ADDIDATA, 5399 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5400 PCI_ANY_ID, 5401 PCI_ANY_ID, 5402 0, 5403 0, 5404 pbn_b0_2_115200 }, 5405 5406 { PCI_VENDOR_ID_ADDIDATA, 5407 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5408 PCI_ANY_ID, 5409 PCI_ANY_ID, 5410 0, 5411 0, 5412 pbn_b0_1_115200 }, 5413 5414 { PCI_VENDOR_ID_AMCC, 5415 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5416 PCI_ANY_ID, 5417 PCI_ANY_ID, 5418 0, 5419 0, 5420 pbn_b1_8_115200 }, 5421 5422 { PCI_VENDOR_ID_ADDIDATA, 5423 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5424 PCI_ANY_ID, 5425 PCI_ANY_ID, 5426 0, 5427 0, 5428 pbn_b0_4_115200 }, 5429 5430 { PCI_VENDOR_ID_ADDIDATA, 5431 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5432 PCI_ANY_ID, 5433 PCI_ANY_ID, 5434 0, 5435 0, 5436 pbn_b0_2_115200 }, 5437 5438 { PCI_VENDOR_ID_ADDIDATA, 5439 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5440 PCI_ANY_ID, 5441 PCI_ANY_ID, 5442 0, 5443 0, 5444 pbn_b0_1_115200 }, 5445 5446 { PCI_VENDOR_ID_ADDIDATA, 5447 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5448 PCI_ANY_ID, 5449 PCI_ANY_ID, 5450 0, 5451 0, 5452 pbn_b0_4_115200 }, 5453 5454 { PCI_VENDOR_ID_ADDIDATA, 5455 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5456 PCI_ANY_ID, 5457 PCI_ANY_ID, 5458 0, 5459 0, 5460 pbn_b0_2_115200 }, 5461 5462 { PCI_VENDOR_ID_ADDIDATA, 5463 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5464 PCI_ANY_ID, 5465 PCI_ANY_ID, 5466 0, 5467 0, 5468 pbn_b0_1_115200 }, 5469 5470 { PCI_VENDOR_ID_ADDIDATA, 5471 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5472 PCI_ANY_ID, 5473 PCI_ANY_ID, 5474 0, 5475 0, 5476 pbn_b0_8_115200 }, 5477 5478 { PCI_VENDOR_ID_ADDIDATA, 5479 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5480 PCI_ANY_ID, 5481 PCI_ANY_ID, 5482 0, 5483 0, 5484 pbn_ADDIDATA_PCIe_4_3906250 }, 5485 5486 { PCI_VENDOR_ID_ADDIDATA, 5487 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5488 PCI_ANY_ID, 5489 PCI_ANY_ID, 5490 0, 5491 0, 5492 pbn_ADDIDATA_PCIe_2_3906250 }, 5493 5494 { PCI_VENDOR_ID_ADDIDATA, 5495 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5496 PCI_ANY_ID, 5497 PCI_ANY_ID, 5498 0, 5499 0, 5500 pbn_ADDIDATA_PCIe_1_3906250 }, 5501 5502 { PCI_VENDOR_ID_ADDIDATA, 5503 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5504 PCI_ANY_ID, 5505 PCI_ANY_ID, 5506 0, 5507 0, 5508 pbn_ADDIDATA_PCIe_8_3906250 }, 5509 5510 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5511 PCI_VENDOR_ID_IBM, 0x0299, 5512 0, 0, pbn_b0_bt_2_115200 }, 5513 5514 /* 5515 * other NetMos 9835 devices are most likely handled by the 5516 * parport_serial driver, check drivers/parport/parport_serial.c 5517 * before adding them here. 5518 */ 5519 5520 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5521 0xA000, 0x1000, 5522 0, 0, pbn_b0_1_115200 }, 5523 5524 /* the 9901 is a rebranded 9912 */ 5525 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5526 0xA000, 0x1000, 5527 0, 0, pbn_b0_1_115200 }, 5528 5529 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5530 0xA000, 0x1000, 5531 0, 0, pbn_b0_1_115200 }, 5532 5533 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5534 0xA000, 0x1000, 5535 0, 0, pbn_b0_1_115200 }, 5536 5537 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5538 0xA000, 0x1000, 5539 0, 0, pbn_b0_1_115200 }, 5540 5541 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5542 0xA000, 0x3002, 5543 0, 0, pbn_NETMOS9900_2s_115200 }, 5544 5545 /* 5546 * Best Connectivity and Rosewill PCI Multi I/O cards 5547 */ 5548 5549 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5550 0xA000, 0x1000, 5551 0, 0, pbn_b0_1_115200 }, 5552 5553 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5554 0xA000, 0x3002, 5555 0, 0, pbn_b0_bt_2_115200 }, 5556 5557 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5558 0xA000, 0x3004, 5559 0, 0, pbn_b0_bt_4_115200 }, 5560 /* Intel CE4100 */ 5561 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5562 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5563 pbn_ce4100_1_115200 }, 5564 5565 /* 5566 * Cronyx Omega PCI 5567 */ 5568 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5570 pbn_omegapci }, 5571 5572 /* 5573 * Broadcom TruManage 5574 */ 5575 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5577 pbn_brcm_trumanage }, 5578 5579 /* 5580 * AgeStar as-prs2-009 5581 */ 5582 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5583 PCI_ANY_ID, PCI_ANY_ID, 5584 0, 0, pbn_b0_bt_2_115200 }, 5585 5586 /* 5587 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5588 * so not listed here. 5589 */ 5590 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5591 PCI_ANY_ID, PCI_ANY_ID, 5592 0, 0, pbn_b0_bt_4_115200 }, 5593 5594 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5595 PCI_ANY_ID, PCI_ANY_ID, 5596 0, 0, pbn_b0_bt_2_115200 }, 5597 5598 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5599 PCI_ANY_ID, PCI_ANY_ID, 5600 0, 0, pbn_b0_bt_4_115200 }, 5601 5602 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5603 PCI_ANY_ID, PCI_ANY_ID, 5604 0, 0, pbn_wch382_2 }, 5605 5606 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5607 PCI_ANY_ID, PCI_ANY_ID, 5608 0, 0, pbn_wch384_4 }, 5609 5610 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5611 PCI_ANY_ID, PCI_ANY_ID, 5612 0, 0, pbn_wch384_8 }, 5613 /* 5614 * Realtek RealManage 5615 */ 5616 { PCI_VENDOR_ID_REALTEK, 0x816a, 5617 PCI_ANY_ID, PCI_ANY_ID, 5618 0, 0, pbn_b0_1_115200 }, 5619 5620 { PCI_VENDOR_ID_REALTEK, 0x816b, 5621 PCI_ANY_ID, PCI_ANY_ID, 5622 0, 0, pbn_b0_1_115200 }, 5623 5624 /* Fintek PCI serial cards */ 5625 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5626 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5627 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5628 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5629 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5630 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5631 5632 /* MKS Tenta SCOM-080x serial cards */ 5633 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5634 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5635 5636 /* Amazon PCI serial device */ 5637 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5638 5639 /* 5640 * These entries match devices with class COMMUNICATION_SERIAL, 5641 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5642 */ 5643 { PCI_ANY_ID, PCI_ANY_ID, 5644 PCI_ANY_ID, PCI_ANY_ID, 5645 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5646 0xffff00, pbn_default }, 5647 { PCI_ANY_ID, PCI_ANY_ID, 5648 PCI_ANY_ID, PCI_ANY_ID, 5649 PCI_CLASS_COMMUNICATION_MODEM << 8, 5650 0xffff00, pbn_default }, 5651 { PCI_ANY_ID, PCI_ANY_ID, 5652 PCI_ANY_ID, PCI_ANY_ID, 5653 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5654 0xffff00, pbn_default }, 5655 { 0, } 5656 }; 5657 5658 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5659 pci_channel_state_t state) 5660 { 5661 struct serial_private *priv = pci_get_drvdata(dev); 5662 5663 if (state == pci_channel_io_perm_failure) 5664 return PCI_ERS_RESULT_DISCONNECT; 5665 5666 if (priv) 5667 pciserial_detach_ports(priv); 5668 5669 pci_disable_device(dev); 5670 5671 return PCI_ERS_RESULT_NEED_RESET; 5672 } 5673 5674 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5675 { 5676 int rc; 5677 5678 rc = pci_enable_device(dev); 5679 5680 if (rc) 5681 return PCI_ERS_RESULT_DISCONNECT; 5682 5683 pci_restore_state(dev); 5684 pci_save_state(dev); 5685 5686 return PCI_ERS_RESULT_RECOVERED; 5687 } 5688 5689 static void serial8250_io_resume(struct pci_dev *dev) 5690 { 5691 struct serial_private *priv = pci_get_drvdata(dev); 5692 struct serial_private *new; 5693 5694 if (!priv) 5695 return; 5696 5697 new = pciserial_init_ports(dev, priv->board); 5698 if (!IS_ERR(new)) { 5699 pci_set_drvdata(dev, new); 5700 kfree(priv); 5701 } 5702 } 5703 5704 static const struct pci_error_handlers serial8250_err_handler = { 5705 .error_detected = serial8250_io_error_detected, 5706 .slot_reset = serial8250_io_slot_reset, 5707 .resume = serial8250_io_resume, 5708 }; 5709 5710 static struct pci_driver serial_pci_driver = { 5711 .name = "serial", 5712 .probe = pciserial_init_one, 5713 .remove = pciserial_remove_one, 5714 .driver = { 5715 .pm = &pciserial_pm_ops, 5716 }, 5717 .id_table = serial_pci_tbl, 5718 .err_handler = &serial8250_err_handler, 5719 }; 5720 5721 module_pci_driver(serial_pci_driver); 5722 5723 MODULE_LICENSE("GPL"); 5724 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5725 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5726 MODULE_IMPORT_NS(SERIAL_8250_PCI); 5727