1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include <linux/dmaengine.h> 29 #include <linux/platform_data/dma-dw.h> 30 31 #include "8250.h" 32 33 /* 34 * init function returns: 35 * > 0 - number of ports 36 * = 0 - use board->num_ports 37 * < 0 - error 38 */ 39 struct pci_serial_quirk { 40 u32 vendor; 41 u32 device; 42 u32 subvendor; 43 u32 subdevice; 44 int (*probe)(struct pci_dev *dev); 45 int (*init)(struct pci_dev *dev); 46 int (*setup)(struct serial_private *, 47 const struct pciserial_board *, 48 struct uart_8250_port *, int); 49 void (*exit)(struct pci_dev *dev); 50 }; 51 52 #define PCI_NUM_BAR_RESOURCES 6 53 54 struct serial_private { 55 struct pci_dev *dev; 56 unsigned int nr; 57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 58 struct pci_serial_quirk *quirk; 59 int line[0]; 60 }; 61 62 static int pci_default_setup(struct serial_private*, 63 const struct pciserial_board*, struct uart_8250_port *, int); 64 65 static void moan_device(const char *str, struct pci_dev *dev) 66 { 67 dev_err(&dev->dev, 68 "%s: %s\n" 69 "Please send the output of lspci -vv, this\n" 70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 71 "manufacturer and name of serial board or\n" 72 "modem board to rmk+serial@arm.linux.org.uk.\n", 73 pci_name(dev), str, dev->vendor, dev->device, 74 dev->subsystem_vendor, dev->subsystem_device); 75 } 76 77 static int 78 setup_port(struct serial_private *priv, struct uart_8250_port *port, 79 int bar, int offset, int regshift) 80 { 81 struct pci_dev *dev = priv->dev; 82 83 if (bar >= PCI_NUM_BAR_RESOURCES) 84 return -EINVAL; 85 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 87 if (!priv->remapped_bar[bar]) 88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); 89 if (!priv->remapped_bar[bar]) 90 return -ENOMEM; 91 92 port->port.iotype = UPIO_MEM; 93 port->port.iobase = 0; 94 port->port.mapbase = pci_resource_start(dev, bar) + offset; 95 port->port.membase = priv->remapped_bar[bar] + offset; 96 port->port.regshift = regshift; 97 } else { 98 port->port.iotype = UPIO_PORT; 99 port->port.iobase = pci_resource_start(dev, bar) + offset; 100 port->port.mapbase = 0; 101 port->port.membase = NULL; 102 port->port.regshift = 0; 103 } 104 return 0; 105 } 106 107 /* 108 * ADDI-DATA GmbH communication cards <info@addi-data.com> 109 */ 110 static int addidata_apci7800_setup(struct serial_private *priv, 111 const struct pciserial_board *board, 112 struct uart_8250_port *port, int idx) 113 { 114 unsigned int bar = 0, offset = board->first_offset; 115 bar = FL_GET_BASE(board->flags); 116 117 if (idx < 2) { 118 offset += idx * board->uart_offset; 119 } else if ((idx >= 2) && (idx < 4)) { 120 bar += 1; 121 offset += ((idx - 2) * board->uart_offset); 122 } else if ((idx >= 4) && (idx < 6)) { 123 bar += 2; 124 offset += ((idx - 4) * board->uart_offset); 125 } else if (idx >= 6) { 126 bar += 3; 127 offset += ((idx - 6) * board->uart_offset); 128 } 129 130 return setup_port(priv, port, bar, offset, board->reg_shift); 131 } 132 133 /* 134 * AFAVLAB uses a different mixture of BARs and offsets 135 * Not that ugly ;) -- HW 136 */ 137 static int 138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 139 struct uart_8250_port *port, int idx) 140 { 141 unsigned int bar, offset = board->first_offset; 142 143 bar = FL_GET_BASE(board->flags); 144 if (idx < 4) 145 bar += idx; 146 else { 147 bar = 4; 148 offset += (idx - 4) * board->uart_offset; 149 } 150 151 return setup_port(priv, port, bar, offset, board->reg_shift); 152 } 153 154 /* 155 * HP's Remote Management Console. The Diva chip came in several 156 * different versions. N-class, L2000 and A500 have two Diva chips, each 157 * with 3 UARTs (the third UART on the second chip is unused). Superdome 158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 159 * one Diva chip, but it has been expanded to 5 UARTs. 160 */ 161 static int pci_hp_diva_init(struct pci_dev *dev) 162 { 163 int rc = 0; 164 165 switch (dev->subsystem_device) { 166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 169 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 170 rc = 3; 171 break; 172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 173 rc = 2; 174 break; 175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 176 rc = 4; 177 break; 178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 180 rc = 1; 181 break; 182 } 183 184 return rc; 185 } 186 187 /* 188 * HP's Diva chip puts the 4th/5th serial port further out, and 189 * some serial ports are supposed to be hidden on certain models. 190 */ 191 static int 192 pci_hp_diva_setup(struct serial_private *priv, 193 const struct pciserial_board *board, 194 struct uart_8250_port *port, int idx) 195 { 196 unsigned int offset = board->first_offset; 197 unsigned int bar = FL_GET_BASE(board->flags); 198 199 switch (priv->dev->subsystem_device) { 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 201 if (idx == 3) 202 idx++; 203 break; 204 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 205 if (idx > 0) 206 idx++; 207 if (idx > 2) 208 idx++; 209 break; 210 } 211 if (idx > 2) 212 offset = 0x18; 213 214 offset += idx * board->uart_offset; 215 216 return setup_port(priv, port, bar, offset, board->reg_shift); 217 } 218 219 /* 220 * Added for EKF Intel i960 serial boards 221 */ 222 static int pci_inteli960ni_init(struct pci_dev *dev) 223 { 224 unsigned long oldval; 225 226 if (!(dev->subsystem_device & 0x1000)) 227 return -ENODEV; 228 229 /* is firmware started? */ 230 pci_read_config_dword(dev, 0x44, (void *)&oldval); 231 if (oldval == 0x00001000L) { /* RESET value */ 232 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 233 return -ENODEV; 234 } 235 return 0; 236 } 237 238 /* 239 * Some PCI serial cards using the PLX 9050 PCI interface chip require 240 * that the card interrupt be explicitly enabled or disabled. This 241 * seems to be mainly needed on card using the PLX which also use I/O 242 * mapped memory. 243 */ 244 static int pci_plx9050_init(struct pci_dev *dev) 245 { 246 u8 irq_config; 247 void __iomem *p; 248 249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 250 moan_device("no memory in bar 0", dev); 251 return 0; 252 } 253 254 irq_config = 0x41; 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 257 irq_config = 0x43; 258 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 261 /* 262 * As the megawolf cards have the int pins active 263 * high, and have 2 UART chips, both ints must be 264 * enabled on the 9050. Also, the UARTS are set in 265 * 16450 mode by default, so we have to enable the 266 * 16C950 'enhanced' mode so that we can use the 267 * deep FIFOs 268 */ 269 irq_config = 0x5b; 270 /* 271 * enable/disable interrupts 272 */ 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 274 if (p == NULL) 275 return -ENOMEM; 276 writel(irq_config, p + 0x4c); 277 278 /* 279 * Read the register back to ensure that it took effect. 280 */ 281 readl(p + 0x4c); 282 iounmap(p); 283 284 return 0; 285 } 286 287 static void pci_plx9050_exit(struct pci_dev *dev) 288 { 289 u8 __iomem *p; 290 291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 292 return; 293 294 /* 295 * disable interrupts 296 */ 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 298 if (p != NULL) { 299 writel(0, p + 0x4c); 300 301 /* 302 * Read the register back to ensure that it took effect. 303 */ 304 readl(p + 0x4c); 305 iounmap(p); 306 } 307 } 308 309 #define NI8420_INT_ENABLE_REG 0x38 310 #define NI8420_INT_ENABLE_BIT 0x2000 311 312 static void pci_ni8420_exit(struct pci_dev *dev) 313 { 314 void __iomem *p; 315 unsigned int bar = 0; 316 317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 318 moan_device("no memory in bar", dev); 319 return; 320 } 321 322 p = pci_ioremap_bar(dev, bar); 323 if (p == NULL) 324 return; 325 326 /* Disable the CPU Interrupt */ 327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 328 p + NI8420_INT_ENABLE_REG); 329 iounmap(p); 330 } 331 332 333 /* MITE registers */ 334 #define MITE_IOWBSR1 0xc4 335 #define MITE_IOWCR1 0xf4 336 #define MITE_LCIMR1 0x08 337 #define MITE_LCIMR2 0x10 338 339 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 340 341 static void pci_ni8430_exit(struct pci_dev *dev) 342 { 343 void __iomem *p; 344 unsigned int bar = 0; 345 346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 347 moan_device("no memory in bar", dev); 348 return; 349 } 350 351 p = pci_ioremap_bar(dev, bar); 352 if (p == NULL) 353 return; 354 355 /* Disable the CPU Interrupt */ 356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 357 iounmap(p); 358 } 359 360 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 361 static int 362 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 363 struct uart_8250_port *port, int idx) 364 { 365 unsigned int bar, offset = board->first_offset; 366 367 bar = 0; 368 369 if (idx < 4) { 370 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 371 offset += idx * board->uart_offset; 372 } else if (idx < 8) { 373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 374 offset += idx * board->uart_offset + 0xC00; 375 } else /* we have only 8 ports on PMC-OCTALPRO */ 376 return 1; 377 378 return setup_port(priv, port, bar, offset, board->reg_shift); 379 } 380 381 /* 382 * This does initialization for PMC OCTALPRO cards: 383 * maps the device memory, resets the UARTs (needed, bc 384 * if the module is removed and inserted again, the card 385 * is in the sleep mode) and enables global interrupt. 386 */ 387 388 /* global control register offset for SBS PMC-OctalPro */ 389 #define OCT_REG_CR_OFF 0x500 390 391 static int sbs_init(struct pci_dev *dev) 392 { 393 u8 __iomem *p; 394 395 p = pci_ioremap_bar(dev, 0); 396 397 if (p == NULL) 398 return -ENOMEM; 399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 400 writeb(0x10, p + OCT_REG_CR_OFF); 401 udelay(50); 402 writeb(0x0, p + OCT_REG_CR_OFF); 403 404 /* Set bit-2 (INTENABLE) of Control Register */ 405 writeb(0x4, p + OCT_REG_CR_OFF); 406 iounmap(p); 407 408 return 0; 409 } 410 411 /* 412 * Disables the global interrupt of PMC-OctalPro 413 */ 414 415 static void sbs_exit(struct pci_dev *dev) 416 { 417 u8 __iomem *p; 418 419 p = pci_ioremap_bar(dev, 0); 420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 421 if (p != NULL) 422 writeb(0, p + OCT_REG_CR_OFF); 423 iounmap(p); 424 } 425 426 /* 427 * SIIG serial cards have an PCI interface chip which also controls 428 * the UART clocking frequency. Each UART can be clocked independently 429 * (except cards equipped with 4 UARTs) and initial clocking settings 430 * are stored in the EEPROM chip. It can cause problems because this 431 * version of serial driver doesn't support differently clocked UART's 432 * on single PCI card. To prevent this, initialization functions set 433 * high frequency clocking for all UART's on given card. It is safe (I 434 * hope) because it doesn't touch EEPROM settings to prevent conflicts 435 * with other OSes (like M$ DOS). 436 * 437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 438 * 439 * There is two family of SIIG serial cards with different PCI 440 * interface chip and different configuration methods: 441 * - 10x cards have control registers in IO and/or memory space; 442 * - 20x cards have control registers in standard PCI configuration space. 443 * 444 * Note: all 10x cards have PCI device ids 0x10.. 445 * all 20x cards have PCI device ids 0x20.. 446 * 447 * There are also Quartet Serial cards which use Oxford Semiconductor 448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 449 * 450 * Note: some SIIG cards are probed by the parport_serial object. 451 */ 452 453 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 454 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 455 456 static int pci_siig10x_init(struct pci_dev *dev) 457 { 458 u16 data; 459 void __iomem *p; 460 461 switch (dev->device & 0xfff8) { 462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 463 data = 0xffdf; 464 break; 465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 466 data = 0xf7ff; 467 break; 468 default: /* 1S1P, 4S */ 469 data = 0xfffb; 470 break; 471 } 472 473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 474 if (p == NULL) 475 return -ENOMEM; 476 477 writew(readw(p + 0x28) & data, p + 0x28); 478 readw(p + 0x28); 479 iounmap(p); 480 return 0; 481 } 482 483 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 484 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 485 486 static int pci_siig20x_init(struct pci_dev *dev) 487 { 488 u8 data; 489 490 /* Change clock frequency for the first UART. */ 491 pci_read_config_byte(dev, 0x6f, &data); 492 pci_write_config_byte(dev, 0x6f, data & 0xef); 493 494 /* If this card has 2 UART, we have to do the same with second UART. */ 495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 497 pci_read_config_byte(dev, 0x73, &data); 498 pci_write_config_byte(dev, 0x73, data & 0xef); 499 } 500 return 0; 501 } 502 503 static int pci_siig_init(struct pci_dev *dev) 504 { 505 unsigned int type = dev->device & 0xff00; 506 507 if (type == 0x1000) 508 return pci_siig10x_init(dev); 509 else if (type == 0x2000) 510 return pci_siig20x_init(dev); 511 512 moan_device("Unknown SIIG card", dev); 513 return -ENODEV; 514 } 515 516 static int pci_siig_setup(struct serial_private *priv, 517 const struct pciserial_board *board, 518 struct uart_8250_port *port, int idx) 519 { 520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 521 522 if (idx > 3) { 523 bar = 4; 524 offset = (idx - 4) * 8; 525 } 526 527 return setup_port(priv, port, bar, offset, 0); 528 } 529 530 /* 531 * Timedia has an explosion of boards, and to avoid the PCI table from 532 * growing *huge*, we use this function to collapse some 70 entries 533 * in the PCI table into one, for sanity's and compactness's sake. 534 */ 535 static const unsigned short timedia_single_port[] = { 536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 537 }; 538 539 static const unsigned short timedia_dual_port[] = { 540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 544 0xD079, 0 545 }; 546 547 static const unsigned short timedia_quad_port[] = { 548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 551 0xB157, 0 552 }; 553 554 static const unsigned short timedia_eight_port[] = { 555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 557 }; 558 559 static const struct timedia_struct { 560 int num; 561 const unsigned short *ids; 562 } timedia_data[] = { 563 { 1, timedia_single_port }, 564 { 2, timedia_dual_port }, 565 { 4, timedia_quad_port }, 566 { 8, timedia_eight_port } 567 }; 568 569 /* 570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 571 * listing them individually, this driver merely grabs them all with 572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 573 * and should be left free to be claimed by parport_serial instead. 574 */ 575 static int pci_timedia_probe(struct pci_dev *dev) 576 { 577 /* 578 * Check the third digit of the subdevice ID 579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 580 */ 581 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 582 dev_info(&dev->dev, 583 "ignoring Timedia subdevice %04x for parport_serial\n", 584 dev->subsystem_device); 585 return -ENODEV; 586 } 587 588 return 0; 589 } 590 591 static int pci_timedia_init(struct pci_dev *dev) 592 { 593 const unsigned short *ids; 594 int i, j; 595 596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 597 ids = timedia_data[i].ids; 598 for (j = 0; ids[j]; j++) 599 if (dev->subsystem_device == ids[j]) 600 return timedia_data[i].num; 601 } 602 return 0; 603 } 604 605 /* 606 * Timedia/SUNIX uses a mixture of BARs and offsets 607 * Ugh, this is ugly as all hell --- TYT 608 */ 609 static int 610 pci_timedia_setup(struct serial_private *priv, 611 const struct pciserial_board *board, 612 struct uart_8250_port *port, int idx) 613 { 614 unsigned int bar = 0, offset = board->first_offset; 615 616 switch (idx) { 617 case 0: 618 bar = 0; 619 break; 620 case 1: 621 offset = board->uart_offset; 622 bar = 0; 623 break; 624 case 2: 625 bar = 1; 626 break; 627 case 3: 628 offset = board->uart_offset; 629 /* FALLTHROUGH */ 630 case 4: /* BAR 2 */ 631 case 5: /* BAR 3 */ 632 case 6: /* BAR 4 */ 633 case 7: /* BAR 5 */ 634 bar = idx - 2; 635 } 636 637 return setup_port(priv, port, bar, offset, board->reg_shift); 638 } 639 640 /* 641 * Some Titan cards are also a little weird 642 */ 643 static int 644 titan_400l_800l_setup(struct serial_private *priv, 645 const struct pciserial_board *board, 646 struct uart_8250_port *port, int idx) 647 { 648 unsigned int bar, offset = board->first_offset; 649 650 switch (idx) { 651 case 0: 652 bar = 1; 653 break; 654 case 1: 655 bar = 2; 656 break; 657 default: 658 bar = 4; 659 offset = (idx - 2) * board->uart_offset; 660 } 661 662 return setup_port(priv, port, bar, offset, board->reg_shift); 663 } 664 665 static int pci_xircom_init(struct pci_dev *dev) 666 { 667 msleep(100); 668 return 0; 669 } 670 671 static int pci_ni8420_init(struct pci_dev *dev) 672 { 673 void __iomem *p; 674 unsigned int bar = 0; 675 676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 677 moan_device("no memory in bar", dev); 678 return 0; 679 } 680 681 p = pci_ioremap_bar(dev, bar); 682 if (p == NULL) 683 return -ENOMEM; 684 685 /* Enable CPU Interrupt */ 686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 687 p + NI8420_INT_ENABLE_REG); 688 689 iounmap(p); 690 return 0; 691 } 692 693 #define MITE_IOWBSR1_WSIZE 0xa 694 #define MITE_IOWBSR1_WIN_OFFSET 0x800 695 #define MITE_IOWBSR1_WENAB (1 << 7) 696 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 697 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 698 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 699 700 static int pci_ni8430_init(struct pci_dev *dev) 701 { 702 void __iomem *p; 703 struct pci_bus_region region; 704 u32 device_window; 705 unsigned int bar = 0; 706 707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 708 moan_device("no memory in bar", dev); 709 return 0; 710 } 711 712 p = pci_ioremap_bar(dev, bar); 713 if (p == NULL) 714 return -ENOMEM; 715 716 /* 717 * Set device window address and size in BAR0, while acknowledging that 718 * the resource structure may contain a translated address that differs 719 * from the address the device responds to. 720 */ 721 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 724 writel(device_window, p + MITE_IOWBSR1); 725 726 /* Set window access to go to RAMSEL IO address space */ 727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 728 p + MITE_IOWCR1); 729 730 /* Enable IO Bus Interrupt 0 */ 731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 732 733 /* Enable CPU Interrupt */ 734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 735 736 iounmap(p); 737 return 0; 738 } 739 740 /* UART Port Control Register */ 741 #define NI8430_PORTCON 0x0f 742 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 743 744 static int 745 pci_ni8430_setup(struct serial_private *priv, 746 const struct pciserial_board *board, 747 struct uart_8250_port *port, int idx) 748 { 749 struct pci_dev *dev = priv->dev; 750 void __iomem *p; 751 unsigned int bar, offset = board->first_offset; 752 753 if (idx >= board->num_ports) 754 return 1; 755 756 bar = FL_GET_BASE(board->flags); 757 offset += idx * board->uart_offset; 758 759 p = pci_ioremap_bar(dev, bar); 760 if (!p) 761 return -ENOMEM; 762 763 /* enable the transceiver */ 764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 765 p + offset + NI8430_PORTCON); 766 767 iounmap(p); 768 769 return setup_port(priv, port, bar, offset, board->reg_shift); 770 } 771 772 static int pci_netmos_9900_setup(struct serial_private *priv, 773 const struct pciserial_board *board, 774 struct uart_8250_port *port, int idx) 775 { 776 unsigned int bar; 777 778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 779 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 780 /* netmos apparently orders BARs by datasheet layout, so serial 781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 782 */ 783 bar = 3 * idx; 784 785 return setup_port(priv, port, bar, 0, board->reg_shift); 786 } else { 787 return pci_default_setup(priv, board, port, idx); 788 } 789 } 790 791 /* the 99xx series comes with a range of device IDs and a variety 792 * of capabilities: 793 * 794 * 9900 has varying capabilities and can cascade to sub-controllers 795 * (cascading should be purely internal) 796 * 9904 is hardwired with 4 serial ports 797 * 9912 and 9922 are hardwired with 2 serial ports 798 */ 799 static int pci_netmos_9900_numports(struct pci_dev *dev) 800 { 801 unsigned int c = dev->class; 802 unsigned int pi; 803 unsigned short sub_serports; 804 805 pi = (c & 0xff); 806 807 if (pi == 2) { 808 return 1; 809 } else if ((pi == 0) && 810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 811 /* two possibilities: 0x30ps encodes number of parallel and 812 * serial ports, or 0x1000 indicates *something*. This is not 813 * immediately obvious, since the 2s1p+4s configuration seems 814 * to offer all functionality on functions 0..2, while still 815 * advertising the same function 3 as the 4s+2s1p config. 816 */ 817 sub_serports = dev->subsystem_device & 0xf; 818 if (sub_serports > 0) { 819 return sub_serports; 820 } else { 821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 822 return 0; 823 } 824 } 825 826 moan_device("unknown NetMos/Mostech program interface", dev); 827 return 0; 828 } 829 830 static int pci_netmos_init(struct pci_dev *dev) 831 { 832 /* subdevice 0x00PS means <P> parallel, <S> serial */ 833 unsigned int num_serial = dev->subsystem_device & 0xf; 834 835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 836 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 837 return 0; 838 839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 840 dev->subsystem_device == 0x0299) 841 return 0; 842 843 switch (dev->device) { /* FALLTHROUGH on all */ 844 case PCI_DEVICE_ID_NETMOS_9904: 845 case PCI_DEVICE_ID_NETMOS_9912: 846 case PCI_DEVICE_ID_NETMOS_9922: 847 case PCI_DEVICE_ID_NETMOS_9900: 848 num_serial = pci_netmos_9900_numports(dev); 849 break; 850 851 default: 852 if (num_serial == 0 ) { 853 moan_device("unknown NetMos/Mostech device", dev); 854 } 855 } 856 857 if (num_serial == 0) 858 return -ENODEV; 859 860 return num_serial; 861 } 862 863 /* 864 * These chips are available with optionally one parallel port and up to 865 * two serial ports. Unfortunately they all have the same product id. 866 * 867 * Basic configuration is done over a region of 32 I/O ports. The base 868 * ioport is called INTA or INTC, depending on docs/other drivers. 869 * 870 * The region of the 32 I/O ports is configured in POSIO0R... 871 */ 872 873 /* registers */ 874 #define ITE_887x_MISCR 0x9c 875 #define ITE_887x_INTCBAR 0x78 876 #define ITE_887x_UARTBAR 0x7c 877 #define ITE_887x_PS0BAR 0x10 878 #define ITE_887x_POSIO0 0x60 879 880 /* I/O space size */ 881 #define ITE_887x_IOSIZE 32 882 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 883 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 884 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 885 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 886 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 887 #define ITE_887x_POSIO_SPEED (3 << 29) 888 /* enable IO_Space bit */ 889 #define ITE_887x_POSIO_ENABLE (1 << 31) 890 891 static int pci_ite887x_init(struct pci_dev *dev) 892 { 893 /* inta_addr are the configuration addresses of the ITE */ 894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 895 0x200, 0x280, 0 }; 896 int ret, i, type; 897 struct resource *iobase = NULL; 898 u32 miscr, uartbar, ioport; 899 900 /* search for the base-ioport */ 901 i = 0; 902 while (inta_addr[i] && iobase == NULL) { 903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 904 "ite887x"); 905 if (iobase != NULL) { 906 /* write POSIO0R - speed | size | ioport */ 907 pci_write_config_dword(dev, ITE_887x_POSIO0, 908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 910 /* write INTCBAR - ioport */ 911 pci_write_config_dword(dev, ITE_887x_INTCBAR, 912 inta_addr[i]); 913 ret = inb(inta_addr[i]); 914 if (ret != 0xff) { 915 /* ioport connected */ 916 break; 917 } 918 release_region(iobase->start, ITE_887x_IOSIZE); 919 iobase = NULL; 920 } 921 i++; 922 } 923 924 if (!inta_addr[i]) { 925 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 926 return -ENODEV; 927 } 928 929 /* start of undocumented type checking (see parport_pc.c) */ 930 type = inb(iobase->start + 0x18) & 0x0f; 931 932 switch (type) { 933 case 0x2: /* ITE8871 (1P) */ 934 case 0xa: /* ITE8875 (1P) */ 935 ret = 0; 936 break; 937 case 0xe: /* ITE8872 (2S1P) */ 938 ret = 2; 939 break; 940 case 0x6: /* ITE8873 (1S) */ 941 ret = 1; 942 break; 943 case 0x8: /* ITE8874 (2S) */ 944 ret = 2; 945 break; 946 default: 947 moan_device("Unknown ITE887x", dev); 948 ret = -ENODEV; 949 } 950 951 /* configure all serial ports */ 952 for (i = 0; i < ret; i++) { 953 /* read the I/O port from the device */ 954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 955 &ioport); 956 ioport &= 0x0000FF00; /* the actual base address */ 957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 959 ITE_887x_POSIO_IOSIZE_8 | ioport); 960 961 /* write the ioport to the UARTBAR */ 962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 964 uartbar |= (ioport << (16 * i)); /* set the ioport */ 965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 966 967 /* get current config */ 968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 969 /* disable interrupts (UARTx_Routing[3:0]) */ 970 miscr &= ~(0xf << (12 - 4 * i)); 971 /* activate the UART (UARTx_En) */ 972 miscr |= 1 << (23 - i); 973 /* write new config with activated UART */ 974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 975 } 976 977 if (ret <= 0) { 978 /* the device has no UARTs if we get here */ 979 release_region(iobase->start, ITE_887x_IOSIZE); 980 } 981 982 return ret; 983 } 984 985 static void pci_ite887x_exit(struct pci_dev *dev) 986 { 987 u32 ioport; 988 /* the ioport is bit 0-15 in POSIO0R */ 989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 990 ioport &= 0xffff; 991 release_region(ioport, ITE_887x_IOSIZE); 992 } 993 994 /* 995 * EndRun Technologies. 996 * Determine the number of ports available on the device. 997 */ 998 #define PCI_VENDOR_ID_ENDRUN 0x7401 999 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1000 1001 static int pci_endrun_init(struct pci_dev *dev) 1002 { 1003 u8 __iomem *p; 1004 unsigned long deviceID; 1005 unsigned int number_uarts = 0; 1006 1007 /* EndRun device is all 0xexxx */ 1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1009 (dev->device & 0xf000) != 0xe000) 1010 return 0; 1011 1012 p = pci_iomap(dev, 0, 5); 1013 if (p == NULL) 1014 return -ENOMEM; 1015 1016 deviceID = ioread32(p); 1017 /* EndRun device */ 1018 if (deviceID == 0x07000200) { 1019 number_uarts = ioread8(p + 4); 1020 dev_dbg(&dev->dev, 1021 "%d ports detected on EndRun PCI Express device\n", 1022 number_uarts); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* 1029 * Oxford Semiconductor Inc. 1030 * Check that device is part of the Tornado range of devices, then determine 1031 * the number of ports available on the device. 1032 */ 1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1034 { 1035 u8 __iomem *p; 1036 unsigned long deviceID; 1037 unsigned int number_uarts = 0; 1038 1039 /* OxSemi Tornado devices are all 0xCxxx */ 1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1041 (dev->device & 0xF000) != 0xC000) 1042 return 0; 1043 1044 p = pci_iomap(dev, 0, 5); 1045 if (p == NULL) 1046 return -ENOMEM; 1047 1048 deviceID = ioread32(p); 1049 /* Tornado device */ 1050 if (deviceID == 0x07000200) { 1051 number_uarts = ioread8(p + 4); 1052 dev_dbg(&dev->dev, 1053 "%d ports detected on Oxford PCI Express device\n", 1054 number_uarts); 1055 } 1056 pci_iounmap(dev, p); 1057 return number_uarts; 1058 } 1059 1060 static int pci_asix_setup(struct serial_private *priv, 1061 const struct pciserial_board *board, 1062 struct uart_8250_port *port, int idx) 1063 { 1064 port->bugs |= UART_BUG_PARITY; 1065 return pci_default_setup(priv, board, port, idx); 1066 } 1067 1068 /* Quatech devices have their own extra interface features */ 1069 1070 struct quatech_feature { 1071 u16 devid; 1072 bool amcc; 1073 }; 1074 1075 #define QPCR_TEST_FOR1 0x3F 1076 #define QPCR_TEST_GET1 0x00 1077 #define QPCR_TEST_FOR2 0x40 1078 #define QPCR_TEST_GET2 0x40 1079 #define QPCR_TEST_FOR3 0x80 1080 #define QPCR_TEST_GET3 0x40 1081 #define QPCR_TEST_FOR4 0xC0 1082 #define QPCR_TEST_GET4 0x80 1083 1084 #define QOPR_CLOCK_X1 0x0000 1085 #define QOPR_CLOCK_X2 0x0001 1086 #define QOPR_CLOCK_X4 0x0002 1087 #define QOPR_CLOCK_X8 0x0003 1088 #define QOPR_CLOCK_RATE_MASK 0x0003 1089 1090 1091 static struct quatech_feature quatech_cards[] = { 1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1111 { 0, } 1112 }; 1113 1114 static int pci_quatech_amcc(u16 devid) 1115 { 1116 struct quatech_feature *qf = &quatech_cards[0]; 1117 while (qf->devid) { 1118 if (qf->devid == devid) 1119 return qf->amcc; 1120 qf++; 1121 } 1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1123 return 0; 1124 }; 1125 1126 static int pci_quatech_rqopr(struct uart_8250_port *port) 1127 { 1128 unsigned long base = port->port.iobase; 1129 u8 LCR, val; 1130 1131 LCR = inb(base + UART_LCR); 1132 outb(0xBF, base + UART_LCR); 1133 val = inb(base + UART_SCR); 1134 outb(LCR, base + UART_LCR); 1135 return val; 1136 } 1137 1138 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1139 { 1140 unsigned long base = port->port.iobase; 1141 u8 LCR, val; 1142 1143 LCR = inb(base + UART_LCR); 1144 outb(0xBF, base + UART_LCR); 1145 val = inb(base + UART_SCR); 1146 outb(qopr, base + UART_SCR); 1147 outb(LCR, base + UART_LCR); 1148 } 1149 1150 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1151 { 1152 unsigned long base = port->port.iobase; 1153 u8 LCR, val, qmcr; 1154 1155 LCR = inb(base + UART_LCR); 1156 outb(0xBF, base + UART_LCR); 1157 val = inb(base + UART_SCR); 1158 outb(val | 0x10, base + UART_SCR); 1159 qmcr = inb(base + UART_MCR); 1160 outb(val, base + UART_SCR); 1161 outb(LCR, base + UART_LCR); 1162 1163 return qmcr; 1164 } 1165 1166 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1167 { 1168 unsigned long base = port->port.iobase; 1169 u8 LCR, val; 1170 1171 LCR = inb(base + UART_LCR); 1172 outb(0xBF, base + UART_LCR); 1173 val = inb(base + UART_SCR); 1174 outb(val | 0x10, base + UART_SCR); 1175 outb(qmcr, base + UART_MCR); 1176 outb(val, base + UART_SCR); 1177 outb(LCR, base + UART_LCR); 1178 } 1179 1180 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1181 { 1182 unsigned long base = port->port.iobase; 1183 u8 LCR, val; 1184 1185 LCR = inb(base + UART_LCR); 1186 outb(0xBF, base + UART_LCR); 1187 val = inb(base + UART_SCR); 1188 if (val & 0x20) { 1189 outb(0x80, UART_LCR); 1190 if (!(inb(UART_SCR) & 0x20)) { 1191 outb(LCR, base + UART_LCR); 1192 return 1; 1193 } 1194 } 1195 return 0; 1196 } 1197 1198 static int pci_quatech_test(struct uart_8250_port *port) 1199 { 1200 u8 reg; 1201 u8 qopr = pci_quatech_rqopr(port); 1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1203 reg = pci_quatech_rqopr(port) & 0xC0; 1204 if (reg != QPCR_TEST_GET1) 1205 return -EINVAL; 1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1207 reg = pci_quatech_rqopr(port) & 0xC0; 1208 if (reg != QPCR_TEST_GET2) 1209 return -EINVAL; 1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1211 reg = pci_quatech_rqopr(port) & 0xC0; 1212 if (reg != QPCR_TEST_GET3) 1213 return -EINVAL; 1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1215 reg = pci_quatech_rqopr(port) & 0xC0; 1216 if (reg != QPCR_TEST_GET4) 1217 return -EINVAL; 1218 1219 pci_quatech_wqopr(port, qopr); 1220 return 0; 1221 } 1222 1223 static int pci_quatech_clock(struct uart_8250_port *port) 1224 { 1225 u8 qopr, reg, set; 1226 unsigned long clock; 1227 1228 if (pci_quatech_test(port) < 0) 1229 return 1843200; 1230 1231 qopr = pci_quatech_rqopr(port); 1232 1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1234 reg = pci_quatech_rqopr(port); 1235 if (reg & QOPR_CLOCK_X8) { 1236 clock = 1843200; 1237 goto out; 1238 } 1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1240 reg = pci_quatech_rqopr(port); 1241 if (!(reg & QOPR_CLOCK_X8)) { 1242 clock = 1843200; 1243 goto out; 1244 } 1245 reg &= QOPR_CLOCK_X8; 1246 if (reg == QOPR_CLOCK_X2) { 1247 clock = 3685400; 1248 set = QOPR_CLOCK_X2; 1249 } else if (reg == QOPR_CLOCK_X4) { 1250 clock = 7372800; 1251 set = QOPR_CLOCK_X4; 1252 } else if (reg == QOPR_CLOCK_X8) { 1253 clock = 14745600; 1254 set = QOPR_CLOCK_X8; 1255 } else { 1256 clock = 1843200; 1257 set = QOPR_CLOCK_X1; 1258 } 1259 qopr &= ~QOPR_CLOCK_RATE_MASK; 1260 qopr |= set; 1261 1262 out: 1263 pci_quatech_wqopr(port, qopr); 1264 return clock; 1265 } 1266 1267 static int pci_quatech_rs422(struct uart_8250_port *port) 1268 { 1269 u8 qmcr; 1270 int rs422 = 0; 1271 1272 if (!pci_quatech_has_qmcr(port)) 1273 return 0; 1274 qmcr = pci_quatech_rqmcr(port); 1275 pci_quatech_wqmcr(port, 0xFF); 1276 if (pci_quatech_rqmcr(port)) 1277 rs422 = 1; 1278 pci_quatech_wqmcr(port, qmcr); 1279 return rs422; 1280 } 1281 1282 static int pci_quatech_init(struct pci_dev *dev) 1283 { 1284 if (pci_quatech_amcc(dev->device)) { 1285 unsigned long base = pci_resource_start(dev, 0); 1286 if (base) { 1287 u32 tmp; 1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1289 tmp = inl(base + 0x3c); 1290 outl(tmp | 0x01000000, base + 0x3c); 1291 outl(tmp &= ~0x01000000, base + 0x3c); 1292 } 1293 } 1294 return 0; 1295 } 1296 1297 static int pci_quatech_setup(struct serial_private *priv, 1298 const struct pciserial_board *board, 1299 struct uart_8250_port *port, int idx) 1300 { 1301 /* Needed by pci_quatech calls below */ 1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1303 /* Set up the clocking */ 1304 port->port.uartclk = pci_quatech_clock(port); 1305 /* For now just warn about RS422 */ 1306 if (pci_quatech_rs422(port)) 1307 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1308 return pci_default_setup(priv, board, port, idx); 1309 } 1310 1311 static void pci_quatech_exit(struct pci_dev *dev) 1312 { 1313 } 1314 1315 static int pci_default_setup(struct serial_private *priv, 1316 const struct pciserial_board *board, 1317 struct uart_8250_port *port, int idx) 1318 { 1319 unsigned int bar, offset = board->first_offset, maxnr; 1320 1321 bar = FL_GET_BASE(board->flags); 1322 if (board->flags & FL_BASE_BARS) 1323 bar += idx; 1324 else 1325 offset += idx * board->uart_offset; 1326 1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1328 (board->reg_shift + 3); 1329 1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1331 return 1; 1332 1333 return setup_port(priv, port, bar, offset, board->reg_shift); 1334 } 1335 1336 static int pci_pericom_setup(struct serial_private *priv, 1337 const struct pciserial_board *board, 1338 struct uart_8250_port *port, int idx) 1339 { 1340 unsigned int bar, offset = board->first_offset, maxnr; 1341 1342 bar = FL_GET_BASE(board->flags); 1343 if (board->flags & FL_BASE_BARS) 1344 bar += idx; 1345 else 1346 offset += idx * board->uart_offset; 1347 1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1349 (board->reg_shift + 3); 1350 1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1352 return 1; 1353 1354 port->port.uartclk = 14745600; 1355 1356 return setup_port(priv, port, bar, offset, board->reg_shift); 1357 } 1358 1359 static int 1360 ce4100_serial_setup(struct serial_private *priv, 1361 const struct pciserial_board *board, 1362 struct uart_8250_port *port, int idx) 1363 { 1364 int ret; 1365 1366 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1367 port->port.iotype = UPIO_MEM32; 1368 port->port.type = PORT_XSCALE; 1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1370 port->port.regshift = 2; 1371 1372 return ret; 1373 } 1374 1375 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1376 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1377 1378 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a 1379 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c 1380 1381 #define BYT_PRV_CLK 0x800 1382 #define BYT_PRV_CLK_EN (1 << 0) 1383 #define BYT_PRV_CLK_M_VAL_SHIFT 1 1384 #define BYT_PRV_CLK_N_VAL_SHIFT 16 1385 #define BYT_PRV_CLK_UPDATE (1 << 31) 1386 1387 #define BYT_TX_OVF_INT 0x820 1388 #define BYT_TX_OVF_INT_MASK (1 << 1) 1389 1390 static void 1391 byt_set_termios(struct uart_port *p, struct ktermios *termios, 1392 struct ktermios *old) 1393 { 1394 unsigned int baud = tty_termios_baud_rate(termios); 1395 unsigned int m, n; 1396 u32 reg; 1397 1398 /* 1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1400 * dividers must be adjusted. 1401 * 1402 * uartclk = (m / n) * 100 MHz, where m <= n 1403 */ 1404 switch (baud) { 1405 case 500000: 1406 case 1000000: 1407 case 2000000: 1408 case 4000000: 1409 m = 64; 1410 n = 100; 1411 p->uartclk = 64000000; 1412 break; 1413 case 3500000: 1414 m = 56; 1415 n = 100; 1416 p->uartclk = 56000000; 1417 break; 1418 case 1500000: 1419 case 3000000: 1420 m = 48; 1421 n = 100; 1422 p->uartclk = 48000000; 1423 break; 1424 case 2500000: 1425 m = 40; 1426 n = 100; 1427 p->uartclk = 40000000; 1428 break; 1429 default: 1430 m = 2304; 1431 n = 3125; 1432 p->uartclk = 73728000; 1433 } 1434 1435 /* Reset the clock */ 1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1437 writel(reg, p->membase + BYT_PRV_CLK); 1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1439 writel(reg, p->membase + BYT_PRV_CLK); 1440 1441 serial8250_do_set_termios(p, termios, old); 1442 } 1443 1444 static bool byt_dma_filter(struct dma_chan *chan, void *param) 1445 { 1446 struct dw_dma_slave *dws = param; 1447 1448 if (dws->dma_dev != chan->device->dev) 1449 return false; 1450 1451 chan->private = dws; 1452 return true; 1453 } 1454 1455 static int 1456 byt_serial_setup(struct serial_private *priv, 1457 const struct pciserial_board *board, 1458 struct uart_8250_port *port, int idx) 1459 { 1460 struct pci_dev *pdev = priv->dev; 1461 struct device *dev = port->port.dev; 1462 struct uart_8250_dma *dma; 1463 struct dw_dma_slave *tx_param, *rx_param; 1464 struct pci_dev *dma_dev; 1465 int ret; 1466 1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1468 if (!dma) 1469 return -ENOMEM; 1470 1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1472 if (!tx_param) 1473 return -ENOMEM; 1474 1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1476 if (!rx_param) 1477 return -ENOMEM; 1478 1479 switch (pdev->device) { 1480 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1481 case PCI_DEVICE_ID_INTEL_BSW_UART1: 1482 rx_param->src_id = 3; 1483 tx_param->dst_id = 2; 1484 break; 1485 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1486 case PCI_DEVICE_ID_INTEL_BSW_UART2: 1487 rx_param->src_id = 5; 1488 tx_param->dst_id = 4; 1489 break; 1490 default: 1491 return -EINVAL; 1492 } 1493 1494 rx_param->src_master = 1; 1495 rx_param->dst_master = 0; 1496 1497 dma->rxconf.src_maxburst = 16; 1498 1499 tx_param->src_master = 1; 1500 tx_param->dst_master = 0; 1501 1502 dma->txconf.dst_maxburst = 16; 1503 1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 1505 rx_param->dma_dev = &dma_dev->dev; 1506 tx_param->dma_dev = &dma_dev->dev; 1507 1508 dma->fn = byt_dma_filter; 1509 dma->rx_param = rx_param; 1510 dma->tx_param = tx_param; 1511 1512 ret = pci_default_setup(priv, board, port, idx); 1513 port->port.iotype = UPIO_MEM; 1514 port->port.type = PORT_16550A; 1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1516 port->port.set_termios = byt_set_termios; 1517 port->port.fifosize = 64; 1518 port->tx_loadsz = 64; 1519 port->dma = dma; 1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1521 1522 /* Disable Tx counter interrupts */ 1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1524 1525 return ret; 1526 } 1527 1528 static int 1529 pci_omegapci_setup(struct serial_private *priv, 1530 const struct pciserial_board *board, 1531 struct uart_8250_port *port, int idx) 1532 { 1533 return setup_port(priv, port, 2, idx * 8, 0); 1534 } 1535 1536 static int 1537 pci_brcm_trumanage_setup(struct serial_private *priv, 1538 const struct pciserial_board *board, 1539 struct uart_8250_port *port, int idx) 1540 { 1541 int ret = pci_default_setup(priv, board, port, idx); 1542 1543 port->port.type = PORT_BRCM_TRUMANAGE; 1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1545 return ret; 1546 } 1547 1548 static int pci_fintek_setup(struct serial_private *priv, 1549 const struct pciserial_board *board, 1550 struct uart_8250_port *port, int idx) 1551 { 1552 struct pci_dev *pdev = priv->dev; 1553 unsigned long base; 1554 unsigned long iobase; 1555 unsigned long ciobase = 0; 1556 u8 config_base; 1557 u32 bar_data[3]; 1558 1559 /* 1560 * Find each UARTs offset in PCI configuraion space 1561 */ 1562 switch (idx) { 1563 case 0: 1564 config_base = 0x40; 1565 break; 1566 case 1: 1567 config_base = 0x48; 1568 break; 1569 case 2: 1570 config_base = 0x50; 1571 break; 1572 case 3: 1573 config_base = 0x58; 1574 break; 1575 case 4: 1576 config_base = 0x60; 1577 break; 1578 case 5: 1579 config_base = 0x68; 1580 break; 1581 case 6: 1582 config_base = 0x70; 1583 break; 1584 case 7: 1585 config_base = 0x78; 1586 break; 1587 case 8: 1588 config_base = 0x80; 1589 break; 1590 case 9: 1591 config_base = 0x88; 1592 break; 1593 case 10: 1594 config_base = 0x90; 1595 break; 1596 case 11: 1597 config_base = 0x98; 1598 break; 1599 default: 1600 /* Unknown number of ports, get out of here */ 1601 return -EINVAL; 1602 } 1603 1604 if (idx < 4) { 1605 base = pci_resource_start(priv->dev, 3); 1606 ciobase = (int)(base + (0x8 * idx)); 1607 } 1608 1609 /* Get the io address dispatch from the BIOS */ 1610 pci_read_config_dword(pdev, 0x24, &bar_data[0]); 1611 pci_read_config_dword(pdev, 0x20, &bar_data[1]); 1612 pci_read_config_dword(pdev, 0x1c, &bar_data[2]); 1613 1614 /* Calculate Real IO Port */ 1615 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8; 1616 1617 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n", 1618 __func__, idx, iobase, ciobase, config_base); 1619 1620 /* Enable UART I/O port */ 1621 pci_write_config_byte(pdev, config_base + 0x00, 0x01); 1622 1623 /* Select 128-byte FIFO and 8x FIFO threshold */ 1624 pci_write_config_byte(pdev, config_base + 0x01, 0x33); 1625 1626 /* LSB UART */ 1627 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff)); 1628 1629 /* MSB UART */ 1630 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8)); 1631 1632 /* irq number, this usually fails, but the spec says to do it anyway. */ 1633 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq); 1634 1635 port->port.iotype = UPIO_PORT; 1636 port->port.iobase = iobase; 1637 port->port.mapbase = 0; 1638 port->port.membase = NULL; 1639 port->port.regshift = 0; 1640 1641 return 0; 1642 } 1643 1644 static int skip_tx_en_setup(struct serial_private *priv, 1645 const struct pciserial_board *board, 1646 struct uart_8250_port *port, int idx) 1647 { 1648 port->port.flags |= UPF_NO_TXEN_TEST; 1649 dev_dbg(&priv->dev->dev, 1650 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1651 priv->dev->vendor, priv->dev->device, 1652 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1653 1654 return pci_default_setup(priv, board, port, idx); 1655 } 1656 1657 static void kt_handle_break(struct uart_port *p) 1658 { 1659 struct uart_8250_port *up = up_to_u8250p(p); 1660 /* 1661 * On receipt of a BI, serial device in Intel ME (Intel 1662 * management engine) needs to have its fifos cleared for sane 1663 * SOL (Serial Over Lan) output. 1664 */ 1665 serial8250_clear_and_reinit_fifos(up); 1666 } 1667 1668 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1669 { 1670 struct uart_8250_port *up = up_to_u8250p(p); 1671 unsigned int val; 1672 1673 /* 1674 * When the Intel ME (management engine) gets reset its serial 1675 * port registers could return 0 momentarily. Functions like 1676 * serial8250_console_write, read and save the IER, perform 1677 * some operation and then restore it. In order to avoid 1678 * setting IER register inadvertently to 0, if the value read 1679 * is 0, double check with ier value in uart_8250_port and use 1680 * that instead. up->ier should be the same value as what is 1681 * currently configured. 1682 */ 1683 val = inb(p->iobase + offset); 1684 if (offset == UART_IER) { 1685 if (val == 0) 1686 val = up->ier; 1687 } 1688 return val; 1689 } 1690 1691 static int kt_serial_setup(struct serial_private *priv, 1692 const struct pciserial_board *board, 1693 struct uart_8250_port *port, int idx) 1694 { 1695 port->port.flags |= UPF_BUG_THRE; 1696 port->port.serial_in = kt_serial_in; 1697 port->port.handle_break = kt_handle_break; 1698 return skip_tx_en_setup(priv, board, port, idx); 1699 } 1700 1701 static int pci_eg20t_init(struct pci_dev *dev) 1702 { 1703 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1704 return -ENODEV; 1705 #else 1706 return 0; 1707 #endif 1708 } 1709 1710 static int 1711 pci_xr17c154_setup(struct serial_private *priv, 1712 const struct pciserial_board *board, 1713 struct uart_8250_port *port, int idx) 1714 { 1715 port->port.flags |= UPF_EXAR_EFR; 1716 return pci_default_setup(priv, board, port, idx); 1717 } 1718 1719 static int 1720 pci_xr17v35x_setup(struct serial_private *priv, 1721 const struct pciserial_board *board, 1722 struct uart_8250_port *port, int idx) 1723 { 1724 u8 __iomem *p; 1725 1726 p = pci_ioremap_bar(priv->dev, 0); 1727 if (p == NULL) 1728 return -ENOMEM; 1729 1730 port->port.flags |= UPF_EXAR_EFR; 1731 1732 /* 1733 * Setup Multipurpose Input/Output pins. 1734 */ 1735 if (idx == 0) { 1736 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1737 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1738 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1739 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1740 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1741 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1742 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1743 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1744 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1745 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1746 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1747 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1748 } 1749 writeb(0x00, p + UART_EXAR_8XMODE); 1750 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1751 writeb(128, p + UART_EXAR_TXTRG); 1752 writeb(128, p + UART_EXAR_RXTRG); 1753 iounmap(p); 1754 1755 return pci_default_setup(priv, board, port, idx); 1756 } 1757 1758 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1759 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1760 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1761 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1762 1763 static int 1764 pci_fastcom335_setup(struct serial_private *priv, 1765 const struct pciserial_board *board, 1766 struct uart_8250_port *port, int idx) 1767 { 1768 u8 __iomem *p; 1769 1770 p = pci_ioremap_bar(priv->dev, 0); 1771 if (p == NULL) 1772 return -ENOMEM; 1773 1774 port->port.flags |= UPF_EXAR_EFR; 1775 1776 /* 1777 * Setup Multipurpose Input/Output pins. 1778 */ 1779 if (idx == 0) { 1780 switch (priv->dev->device) { 1781 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1782 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1783 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1784 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1785 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1786 break; 1787 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1788 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1789 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1790 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1791 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1792 break; 1793 } 1794 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1795 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1796 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1797 } 1798 writeb(0x00, p + UART_EXAR_8XMODE); 1799 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1800 writeb(32, p + UART_EXAR_TXTRG); 1801 writeb(32, p + UART_EXAR_RXTRG); 1802 iounmap(p); 1803 1804 return pci_default_setup(priv, board, port, idx); 1805 } 1806 1807 static int 1808 pci_wch_ch353_setup(struct serial_private *priv, 1809 const struct pciserial_board *board, 1810 struct uart_8250_port *port, int idx) 1811 { 1812 port->port.flags |= UPF_FIXED_TYPE; 1813 port->port.type = PORT_16550A; 1814 return pci_default_setup(priv, board, port, idx); 1815 } 1816 1817 static int 1818 pci_wch_ch382_setup(struct serial_private *priv, 1819 const struct pciserial_board *board, 1820 struct uart_8250_port *port, int idx) 1821 { 1822 port->port.flags |= UPF_FIXED_TYPE; 1823 port->port.type = PORT_16850; 1824 return pci_default_setup(priv, board, port, idx); 1825 } 1826 1827 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1828 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1829 #define PCI_DEVICE_ID_OCTPRO 0x0001 1830 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1831 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1832 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1833 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1834 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1835 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1836 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1837 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1838 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1839 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1840 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1841 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1842 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1843 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1844 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1845 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1846 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1847 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1848 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1849 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1850 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1851 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1852 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1853 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1854 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1855 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1856 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1857 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1858 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1859 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1860 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1861 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1862 #define PCI_VENDOR_ID_WCH 0x4348 1863 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1864 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1865 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1866 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1867 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1868 #define PCI_VENDOR_ID_AGESTAR 0x5372 1869 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1870 #define PCI_VENDOR_ID_ASIX 0x9710 1871 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1872 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1873 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1874 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1875 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1876 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 1877 1878 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1879 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1880 1881 #define PCIE_VENDOR_ID_WCH 0x1c00 1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1883 1884 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1885 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1886 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1887 1888 /* 1889 * Master list of serial port init/setup/exit quirks. 1890 * This does not describe the general nature of the port. 1891 * (ie, baud base, number and location of ports, etc) 1892 * 1893 * This list is ordered alphabetically by vendor then device. 1894 * Specific entries must come before more generic entries. 1895 */ 1896 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1897 /* 1898 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1899 */ 1900 { 1901 .vendor = PCI_VENDOR_ID_AMCC, 1902 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1903 .subvendor = PCI_ANY_ID, 1904 .subdevice = PCI_ANY_ID, 1905 .setup = addidata_apci7800_setup, 1906 }, 1907 /* 1908 * AFAVLAB cards - these may be called via parport_serial 1909 * It is not clear whether this applies to all products. 1910 */ 1911 { 1912 .vendor = PCI_VENDOR_ID_AFAVLAB, 1913 .device = PCI_ANY_ID, 1914 .subvendor = PCI_ANY_ID, 1915 .subdevice = PCI_ANY_ID, 1916 .setup = afavlab_setup, 1917 }, 1918 /* 1919 * HP Diva 1920 */ 1921 { 1922 .vendor = PCI_VENDOR_ID_HP, 1923 .device = PCI_DEVICE_ID_HP_DIVA, 1924 .subvendor = PCI_ANY_ID, 1925 .subdevice = PCI_ANY_ID, 1926 .init = pci_hp_diva_init, 1927 .setup = pci_hp_diva_setup, 1928 }, 1929 /* 1930 * Intel 1931 */ 1932 { 1933 .vendor = PCI_VENDOR_ID_INTEL, 1934 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1935 .subvendor = 0xe4bf, 1936 .subdevice = PCI_ANY_ID, 1937 .init = pci_inteli960ni_init, 1938 .setup = pci_default_setup, 1939 }, 1940 { 1941 .vendor = PCI_VENDOR_ID_INTEL, 1942 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1943 .subvendor = PCI_ANY_ID, 1944 .subdevice = PCI_ANY_ID, 1945 .setup = skip_tx_en_setup, 1946 }, 1947 { 1948 .vendor = PCI_VENDOR_ID_INTEL, 1949 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1950 .subvendor = PCI_ANY_ID, 1951 .subdevice = PCI_ANY_ID, 1952 .setup = skip_tx_en_setup, 1953 }, 1954 { 1955 .vendor = PCI_VENDOR_ID_INTEL, 1956 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1957 .subvendor = PCI_ANY_ID, 1958 .subdevice = PCI_ANY_ID, 1959 .setup = skip_tx_en_setup, 1960 }, 1961 { 1962 .vendor = PCI_VENDOR_ID_INTEL, 1963 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1964 .subvendor = PCI_ANY_ID, 1965 .subdevice = PCI_ANY_ID, 1966 .setup = ce4100_serial_setup, 1967 }, 1968 { 1969 .vendor = PCI_VENDOR_ID_INTEL, 1970 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1971 .subvendor = PCI_ANY_ID, 1972 .subdevice = PCI_ANY_ID, 1973 .setup = kt_serial_setup, 1974 }, 1975 { 1976 .vendor = PCI_VENDOR_ID_INTEL, 1977 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 1978 .subvendor = PCI_ANY_ID, 1979 .subdevice = PCI_ANY_ID, 1980 .setup = byt_serial_setup, 1981 }, 1982 { 1983 .vendor = PCI_VENDOR_ID_INTEL, 1984 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 1985 .subvendor = PCI_ANY_ID, 1986 .subdevice = PCI_ANY_ID, 1987 .setup = byt_serial_setup, 1988 }, 1989 { 1990 .vendor = PCI_VENDOR_ID_INTEL, 1991 .device = PCI_DEVICE_ID_INTEL_QRK_UART, 1992 .subvendor = PCI_ANY_ID, 1993 .subdevice = PCI_ANY_ID, 1994 .setup = pci_default_setup, 1995 }, 1996 { 1997 .vendor = PCI_VENDOR_ID_INTEL, 1998 .device = PCI_DEVICE_ID_INTEL_BSW_UART1, 1999 .subvendor = PCI_ANY_ID, 2000 .subdevice = PCI_ANY_ID, 2001 .setup = byt_serial_setup, 2002 }, 2003 { 2004 .vendor = PCI_VENDOR_ID_INTEL, 2005 .device = PCI_DEVICE_ID_INTEL_BSW_UART2, 2006 .subvendor = PCI_ANY_ID, 2007 .subdevice = PCI_ANY_ID, 2008 .setup = byt_serial_setup, 2009 }, 2010 /* 2011 * ITE 2012 */ 2013 { 2014 .vendor = PCI_VENDOR_ID_ITE, 2015 .device = PCI_DEVICE_ID_ITE_8872, 2016 .subvendor = PCI_ANY_ID, 2017 .subdevice = PCI_ANY_ID, 2018 .init = pci_ite887x_init, 2019 .setup = pci_default_setup, 2020 .exit = pci_ite887x_exit, 2021 }, 2022 /* 2023 * National Instruments 2024 */ 2025 { 2026 .vendor = PCI_VENDOR_ID_NI, 2027 .device = PCI_DEVICE_ID_NI_PCI23216, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .init = pci_ni8420_init, 2031 .setup = pci_default_setup, 2032 .exit = pci_ni8420_exit, 2033 }, 2034 { 2035 .vendor = PCI_VENDOR_ID_NI, 2036 .device = PCI_DEVICE_ID_NI_PCI2328, 2037 .subvendor = PCI_ANY_ID, 2038 .subdevice = PCI_ANY_ID, 2039 .init = pci_ni8420_init, 2040 .setup = pci_default_setup, 2041 .exit = pci_ni8420_exit, 2042 }, 2043 { 2044 .vendor = PCI_VENDOR_ID_NI, 2045 .device = PCI_DEVICE_ID_NI_PCI2324, 2046 .subvendor = PCI_ANY_ID, 2047 .subdevice = PCI_ANY_ID, 2048 .init = pci_ni8420_init, 2049 .setup = pci_default_setup, 2050 .exit = pci_ni8420_exit, 2051 }, 2052 { 2053 .vendor = PCI_VENDOR_ID_NI, 2054 .device = PCI_DEVICE_ID_NI_PCI2322, 2055 .subvendor = PCI_ANY_ID, 2056 .subdevice = PCI_ANY_ID, 2057 .init = pci_ni8420_init, 2058 .setup = pci_default_setup, 2059 .exit = pci_ni8420_exit, 2060 }, 2061 { 2062 .vendor = PCI_VENDOR_ID_NI, 2063 .device = PCI_DEVICE_ID_NI_PCI2324I, 2064 .subvendor = PCI_ANY_ID, 2065 .subdevice = PCI_ANY_ID, 2066 .init = pci_ni8420_init, 2067 .setup = pci_default_setup, 2068 .exit = pci_ni8420_exit, 2069 }, 2070 { 2071 .vendor = PCI_VENDOR_ID_NI, 2072 .device = PCI_DEVICE_ID_NI_PCI2322I, 2073 .subvendor = PCI_ANY_ID, 2074 .subdevice = PCI_ANY_ID, 2075 .init = pci_ni8420_init, 2076 .setup = pci_default_setup, 2077 .exit = pci_ni8420_exit, 2078 }, 2079 { 2080 .vendor = PCI_VENDOR_ID_NI, 2081 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2082 .subvendor = PCI_ANY_ID, 2083 .subdevice = PCI_ANY_ID, 2084 .init = pci_ni8420_init, 2085 .setup = pci_default_setup, 2086 .exit = pci_ni8420_exit, 2087 }, 2088 { 2089 .vendor = PCI_VENDOR_ID_NI, 2090 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2091 .subvendor = PCI_ANY_ID, 2092 .subdevice = PCI_ANY_ID, 2093 .init = pci_ni8420_init, 2094 .setup = pci_default_setup, 2095 .exit = pci_ni8420_exit, 2096 }, 2097 { 2098 .vendor = PCI_VENDOR_ID_NI, 2099 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2100 .subvendor = PCI_ANY_ID, 2101 .subdevice = PCI_ANY_ID, 2102 .init = pci_ni8420_init, 2103 .setup = pci_default_setup, 2104 .exit = pci_ni8420_exit, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_NI, 2108 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .init = pci_ni8420_init, 2112 .setup = pci_default_setup, 2113 .exit = pci_ni8420_exit, 2114 }, 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_ANY_ID, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8430_init, 2139 .setup = pci_ni8430_setup, 2140 .exit = pci_ni8430_exit, 2141 }, 2142 /* Quatech */ 2143 { 2144 .vendor = PCI_VENDOR_ID_QUATECH, 2145 .device = PCI_ANY_ID, 2146 .subvendor = PCI_ANY_ID, 2147 .subdevice = PCI_ANY_ID, 2148 .init = pci_quatech_init, 2149 .setup = pci_quatech_setup, 2150 .exit = pci_quatech_exit, 2151 }, 2152 /* 2153 * Panacom 2154 */ 2155 { 2156 .vendor = PCI_VENDOR_ID_PANACOM, 2157 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2158 .subvendor = PCI_ANY_ID, 2159 .subdevice = PCI_ANY_ID, 2160 .init = pci_plx9050_init, 2161 .setup = pci_default_setup, 2162 .exit = pci_plx9050_exit, 2163 }, 2164 { 2165 .vendor = PCI_VENDOR_ID_PANACOM, 2166 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2167 .subvendor = PCI_ANY_ID, 2168 .subdevice = PCI_ANY_ID, 2169 .init = pci_plx9050_init, 2170 .setup = pci_default_setup, 2171 .exit = pci_plx9050_exit, 2172 }, 2173 /* 2174 * Pericom 2175 */ 2176 { 2177 .vendor = 0x12d8, 2178 .device = 0x7952, 2179 .subvendor = PCI_ANY_ID, 2180 .subdevice = PCI_ANY_ID, 2181 .setup = pci_pericom_setup, 2182 }, 2183 { 2184 .vendor = 0x12d8, 2185 .device = 0x7954, 2186 .subvendor = PCI_ANY_ID, 2187 .subdevice = PCI_ANY_ID, 2188 .setup = pci_pericom_setup, 2189 }, 2190 { 2191 .vendor = 0x12d8, 2192 .device = 0x7958, 2193 .subvendor = PCI_ANY_ID, 2194 .subdevice = PCI_ANY_ID, 2195 .setup = pci_pericom_setup, 2196 }, 2197 2198 /* 2199 * PLX 2200 */ 2201 { 2202 .vendor = PCI_VENDOR_ID_PLX, 2203 .device = PCI_DEVICE_ID_PLX_9030, 2204 .subvendor = PCI_SUBVENDOR_ID_PERLE, 2205 .subdevice = PCI_ANY_ID, 2206 .setup = pci_default_setup, 2207 }, 2208 { 2209 .vendor = PCI_VENDOR_ID_PLX, 2210 .device = PCI_DEVICE_ID_PLX_9050, 2211 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2212 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2213 .init = pci_plx9050_init, 2214 .setup = pci_default_setup, 2215 .exit = pci_plx9050_exit, 2216 }, 2217 { 2218 .vendor = PCI_VENDOR_ID_PLX, 2219 .device = PCI_DEVICE_ID_PLX_9050, 2220 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2221 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2222 .init = pci_plx9050_init, 2223 .setup = pci_default_setup, 2224 .exit = pci_plx9050_exit, 2225 }, 2226 { 2227 .vendor = PCI_VENDOR_ID_PLX, 2228 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2229 .subvendor = PCI_VENDOR_ID_PLX, 2230 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2231 .init = pci_plx9050_init, 2232 .setup = pci_default_setup, 2233 .exit = pci_plx9050_exit, 2234 }, 2235 /* 2236 * SBS Technologies, Inc., PMC-OCTALPRO 232 2237 */ 2238 { 2239 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2240 .device = PCI_DEVICE_ID_OCTPRO, 2241 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2242 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2243 .init = sbs_init, 2244 .setup = sbs_setup, 2245 .exit = sbs_exit, 2246 }, 2247 /* 2248 * SBS Technologies, Inc., PMC-OCTALPRO 422 2249 */ 2250 { 2251 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2252 .device = PCI_DEVICE_ID_OCTPRO, 2253 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2254 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2255 .init = sbs_init, 2256 .setup = sbs_setup, 2257 .exit = sbs_exit, 2258 }, 2259 /* 2260 * SBS Technologies, Inc., P-Octal 232 2261 */ 2262 { 2263 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2264 .device = PCI_DEVICE_ID_OCTPRO, 2265 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2266 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2267 .init = sbs_init, 2268 .setup = sbs_setup, 2269 .exit = sbs_exit, 2270 }, 2271 /* 2272 * SBS Technologies, Inc., P-Octal 422 2273 */ 2274 { 2275 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2276 .device = PCI_DEVICE_ID_OCTPRO, 2277 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2278 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2279 .init = sbs_init, 2280 .setup = sbs_setup, 2281 .exit = sbs_exit, 2282 }, 2283 /* 2284 * SIIG cards - these may be called via parport_serial 2285 */ 2286 { 2287 .vendor = PCI_VENDOR_ID_SIIG, 2288 .device = PCI_ANY_ID, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .init = pci_siig_init, 2292 .setup = pci_siig_setup, 2293 }, 2294 /* 2295 * Titan cards 2296 */ 2297 { 2298 .vendor = PCI_VENDOR_ID_TITAN, 2299 .device = PCI_DEVICE_ID_TITAN_400L, 2300 .subvendor = PCI_ANY_ID, 2301 .subdevice = PCI_ANY_ID, 2302 .setup = titan_400l_800l_setup, 2303 }, 2304 { 2305 .vendor = PCI_VENDOR_ID_TITAN, 2306 .device = PCI_DEVICE_ID_TITAN_800L, 2307 .subvendor = PCI_ANY_ID, 2308 .subdevice = PCI_ANY_ID, 2309 .setup = titan_400l_800l_setup, 2310 }, 2311 /* 2312 * Timedia cards 2313 */ 2314 { 2315 .vendor = PCI_VENDOR_ID_TIMEDIA, 2316 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2317 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2318 .subdevice = PCI_ANY_ID, 2319 .probe = pci_timedia_probe, 2320 .init = pci_timedia_init, 2321 .setup = pci_timedia_setup, 2322 }, 2323 { 2324 .vendor = PCI_VENDOR_ID_TIMEDIA, 2325 .device = PCI_ANY_ID, 2326 .subvendor = PCI_ANY_ID, 2327 .subdevice = PCI_ANY_ID, 2328 .setup = pci_timedia_setup, 2329 }, 2330 /* 2331 * SUNIX (Timedia) cards 2332 * Do not "probe" for these cards as there is at least one combination 2333 * card that should be handled by parport_pc that doesn't match the 2334 * rule in pci_timedia_probe. 2335 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2336 * There are some boards with part number SER5037AL that report 2337 * subdevice ID 0x0002. 2338 */ 2339 { 2340 .vendor = PCI_VENDOR_ID_SUNIX, 2341 .device = PCI_DEVICE_ID_SUNIX_1999, 2342 .subvendor = PCI_VENDOR_ID_SUNIX, 2343 .subdevice = PCI_ANY_ID, 2344 .init = pci_timedia_init, 2345 .setup = pci_timedia_setup, 2346 }, 2347 /* 2348 * Exar cards 2349 */ 2350 { 2351 .vendor = PCI_VENDOR_ID_EXAR, 2352 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2353 .subvendor = PCI_ANY_ID, 2354 .subdevice = PCI_ANY_ID, 2355 .setup = pci_xr17c154_setup, 2356 }, 2357 { 2358 .vendor = PCI_VENDOR_ID_EXAR, 2359 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2360 .subvendor = PCI_ANY_ID, 2361 .subdevice = PCI_ANY_ID, 2362 .setup = pci_xr17c154_setup, 2363 }, 2364 { 2365 .vendor = PCI_VENDOR_ID_EXAR, 2366 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2367 .subvendor = PCI_ANY_ID, 2368 .subdevice = PCI_ANY_ID, 2369 .setup = pci_xr17c154_setup, 2370 }, 2371 { 2372 .vendor = PCI_VENDOR_ID_EXAR, 2373 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2374 .subvendor = PCI_ANY_ID, 2375 .subdevice = PCI_ANY_ID, 2376 .setup = pci_xr17v35x_setup, 2377 }, 2378 { 2379 .vendor = PCI_VENDOR_ID_EXAR, 2380 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2381 .subvendor = PCI_ANY_ID, 2382 .subdevice = PCI_ANY_ID, 2383 .setup = pci_xr17v35x_setup, 2384 }, 2385 { 2386 .vendor = PCI_VENDOR_ID_EXAR, 2387 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2388 .subvendor = PCI_ANY_ID, 2389 .subdevice = PCI_ANY_ID, 2390 .setup = pci_xr17v35x_setup, 2391 }, 2392 /* 2393 * Xircom cards 2394 */ 2395 { 2396 .vendor = PCI_VENDOR_ID_XIRCOM, 2397 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2398 .subvendor = PCI_ANY_ID, 2399 .subdevice = PCI_ANY_ID, 2400 .init = pci_xircom_init, 2401 .setup = pci_default_setup, 2402 }, 2403 /* 2404 * Netmos cards - these may be called via parport_serial 2405 */ 2406 { 2407 .vendor = PCI_VENDOR_ID_NETMOS, 2408 .device = PCI_ANY_ID, 2409 .subvendor = PCI_ANY_ID, 2410 .subdevice = PCI_ANY_ID, 2411 .init = pci_netmos_init, 2412 .setup = pci_netmos_9900_setup, 2413 }, 2414 /* 2415 * EndRun Technologies 2416 */ 2417 { 2418 .vendor = PCI_VENDOR_ID_ENDRUN, 2419 .device = PCI_ANY_ID, 2420 .subvendor = PCI_ANY_ID, 2421 .subdevice = PCI_ANY_ID, 2422 .init = pci_endrun_init, 2423 .setup = pci_default_setup, 2424 }, 2425 /* 2426 * For Oxford Semiconductor Tornado based devices 2427 */ 2428 { 2429 .vendor = PCI_VENDOR_ID_OXSEMI, 2430 .device = PCI_ANY_ID, 2431 .subvendor = PCI_ANY_ID, 2432 .subdevice = PCI_ANY_ID, 2433 .init = pci_oxsemi_tornado_init, 2434 .setup = pci_default_setup, 2435 }, 2436 { 2437 .vendor = PCI_VENDOR_ID_MAINPINE, 2438 .device = PCI_ANY_ID, 2439 .subvendor = PCI_ANY_ID, 2440 .subdevice = PCI_ANY_ID, 2441 .init = pci_oxsemi_tornado_init, 2442 .setup = pci_default_setup, 2443 }, 2444 { 2445 .vendor = PCI_VENDOR_ID_DIGI, 2446 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2447 .subvendor = PCI_SUBVENDOR_ID_IBM, 2448 .subdevice = PCI_ANY_ID, 2449 .init = pci_oxsemi_tornado_init, 2450 .setup = pci_default_setup, 2451 }, 2452 { 2453 .vendor = PCI_VENDOR_ID_INTEL, 2454 .device = 0x8811, 2455 .subvendor = PCI_ANY_ID, 2456 .subdevice = PCI_ANY_ID, 2457 .init = pci_eg20t_init, 2458 .setup = pci_default_setup, 2459 }, 2460 { 2461 .vendor = PCI_VENDOR_ID_INTEL, 2462 .device = 0x8812, 2463 .subvendor = PCI_ANY_ID, 2464 .subdevice = PCI_ANY_ID, 2465 .init = pci_eg20t_init, 2466 .setup = pci_default_setup, 2467 }, 2468 { 2469 .vendor = PCI_VENDOR_ID_INTEL, 2470 .device = 0x8813, 2471 .subvendor = PCI_ANY_ID, 2472 .subdevice = PCI_ANY_ID, 2473 .init = pci_eg20t_init, 2474 .setup = pci_default_setup, 2475 }, 2476 { 2477 .vendor = PCI_VENDOR_ID_INTEL, 2478 .device = 0x8814, 2479 .subvendor = PCI_ANY_ID, 2480 .subdevice = PCI_ANY_ID, 2481 .init = pci_eg20t_init, 2482 .setup = pci_default_setup, 2483 }, 2484 { 2485 .vendor = 0x10DB, 2486 .device = 0x8027, 2487 .subvendor = PCI_ANY_ID, 2488 .subdevice = PCI_ANY_ID, 2489 .init = pci_eg20t_init, 2490 .setup = pci_default_setup, 2491 }, 2492 { 2493 .vendor = 0x10DB, 2494 .device = 0x8028, 2495 .subvendor = PCI_ANY_ID, 2496 .subdevice = PCI_ANY_ID, 2497 .init = pci_eg20t_init, 2498 .setup = pci_default_setup, 2499 }, 2500 { 2501 .vendor = 0x10DB, 2502 .device = 0x8029, 2503 .subvendor = PCI_ANY_ID, 2504 .subdevice = PCI_ANY_ID, 2505 .init = pci_eg20t_init, 2506 .setup = pci_default_setup, 2507 }, 2508 { 2509 .vendor = 0x10DB, 2510 .device = 0x800C, 2511 .subvendor = PCI_ANY_ID, 2512 .subdevice = PCI_ANY_ID, 2513 .init = pci_eg20t_init, 2514 .setup = pci_default_setup, 2515 }, 2516 { 2517 .vendor = 0x10DB, 2518 .device = 0x800D, 2519 .subvendor = PCI_ANY_ID, 2520 .subdevice = PCI_ANY_ID, 2521 .init = pci_eg20t_init, 2522 .setup = pci_default_setup, 2523 }, 2524 /* 2525 * Cronyx Omega PCI (PLX-chip based) 2526 */ 2527 { 2528 .vendor = PCI_VENDOR_ID_PLX, 2529 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2530 .subvendor = PCI_ANY_ID, 2531 .subdevice = PCI_ANY_ID, 2532 .setup = pci_omegapci_setup, 2533 }, 2534 /* WCH CH353 1S1P card (16550 clone) */ 2535 { 2536 .vendor = PCI_VENDOR_ID_WCH, 2537 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2538 .subvendor = PCI_ANY_ID, 2539 .subdevice = PCI_ANY_ID, 2540 .setup = pci_wch_ch353_setup, 2541 }, 2542 /* WCH CH353 2S1P card (16550 clone) */ 2543 { 2544 .vendor = PCI_VENDOR_ID_WCH, 2545 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2546 .subvendor = PCI_ANY_ID, 2547 .subdevice = PCI_ANY_ID, 2548 .setup = pci_wch_ch353_setup, 2549 }, 2550 /* WCH CH353 4S card (16550 clone) */ 2551 { 2552 .vendor = PCI_VENDOR_ID_WCH, 2553 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2554 .subvendor = PCI_ANY_ID, 2555 .subdevice = PCI_ANY_ID, 2556 .setup = pci_wch_ch353_setup, 2557 }, 2558 /* WCH CH353 2S1PF card (16550 clone) */ 2559 { 2560 .vendor = PCI_VENDOR_ID_WCH, 2561 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2562 .subvendor = PCI_ANY_ID, 2563 .subdevice = PCI_ANY_ID, 2564 .setup = pci_wch_ch353_setup, 2565 }, 2566 /* WCH CH352 2S card (16550 clone) */ 2567 { 2568 .vendor = PCI_VENDOR_ID_WCH, 2569 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2570 .subvendor = PCI_ANY_ID, 2571 .subdevice = PCI_ANY_ID, 2572 .setup = pci_wch_ch353_setup, 2573 }, 2574 /* WCH CH382 2S1P card (16750 clone) */ 2575 { 2576 .vendor = PCIE_VENDOR_ID_WCH, 2577 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2578 .subvendor = PCI_ANY_ID, 2579 .subdevice = PCI_ANY_ID, 2580 .setup = pci_wch_ch382_setup, 2581 }, 2582 /* 2583 * ASIX devices with FIFO bug 2584 */ 2585 { 2586 .vendor = PCI_VENDOR_ID_ASIX, 2587 .device = PCI_ANY_ID, 2588 .subvendor = PCI_ANY_ID, 2589 .subdevice = PCI_ANY_ID, 2590 .setup = pci_asix_setup, 2591 }, 2592 /* 2593 * Commtech, Inc. Fastcom adapters 2594 * 2595 */ 2596 { 2597 .vendor = PCI_VENDOR_ID_COMMTECH, 2598 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2599 .subvendor = PCI_ANY_ID, 2600 .subdevice = PCI_ANY_ID, 2601 .setup = pci_fastcom335_setup, 2602 }, 2603 { 2604 .vendor = PCI_VENDOR_ID_COMMTECH, 2605 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2606 .subvendor = PCI_ANY_ID, 2607 .subdevice = PCI_ANY_ID, 2608 .setup = pci_fastcom335_setup, 2609 }, 2610 { 2611 .vendor = PCI_VENDOR_ID_COMMTECH, 2612 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2613 .subvendor = PCI_ANY_ID, 2614 .subdevice = PCI_ANY_ID, 2615 .setup = pci_fastcom335_setup, 2616 }, 2617 { 2618 .vendor = PCI_VENDOR_ID_COMMTECH, 2619 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2620 .subvendor = PCI_ANY_ID, 2621 .subdevice = PCI_ANY_ID, 2622 .setup = pci_fastcom335_setup, 2623 }, 2624 { 2625 .vendor = PCI_VENDOR_ID_COMMTECH, 2626 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2627 .subvendor = PCI_ANY_ID, 2628 .subdevice = PCI_ANY_ID, 2629 .setup = pci_xr17v35x_setup, 2630 }, 2631 { 2632 .vendor = PCI_VENDOR_ID_COMMTECH, 2633 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2634 .subvendor = PCI_ANY_ID, 2635 .subdevice = PCI_ANY_ID, 2636 .setup = pci_xr17v35x_setup, 2637 }, 2638 { 2639 .vendor = PCI_VENDOR_ID_COMMTECH, 2640 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2641 .subvendor = PCI_ANY_ID, 2642 .subdevice = PCI_ANY_ID, 2643 .setup = pci_xr17v35x_setup, 2644 }, 2645 /* 2646 * Broadcom TruManage (NetXtreme) 2647 */ 2648 { 2649 .vendor = PCI_VENDOR_ID_BROADCOM, 2650 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2651 .subvendor = PCI_ANY_ID, 2652 .subdevice = PCI_ANY_ID, 2653 .setup = pci_brcm_trumanage_setup, 2654 }, 2655 { 2656 .vendor = 0x1c29, 2657 .device = 0x1104, 2658 .subvendor = PCI_ANY_ID, 2659 .subdevice = PCI_ANY_ID, 2660 .setup = pci_fintek_setup, 2661 }, 2662 { 2663 .vendor = 0x1c29, 2664 .device = 0x1108, 2665 .subvendor = PCI_ANY_ID, 2666 .subdevice = PCI_ANY_ID, 2667 .setup = pci_fintek_setup, 2668 }, 2669 { 2670 .vendor = 0x1c29, 2671 .device = 0x1112, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .setup = pci_fintek_setup, 2675 }, 2676 2677 /* 2678 * Default "match everything" terminator entry 2679 */ 2680 { 2681 .vendor = PCI_ANY_ID, 2682 .device = PCI_ANY_ID, 2683 .subvendor = PCI_ANY_ID, 2684 .subdevice = PCI_ANY_ID, 2685 .setup = pci_default_setup, 2686 } 2687 }; 2688 2689 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2690 { 2691 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2692 } 2693 2694 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2695 { 2696 struct pci_serial_quirk *quirk; 2697 2698 for (quirk = pci_serial_quirks; ; quirk++) 2699 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2700 quirk_id_matches(quirk->device, dev->device) && 2701 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2702 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2703 break; 2704 return quirk; 2705 } 2706 2707 static inline int get_pci_irq(struct pci_dev *dev, 2708 const struct pciserial_board *board) 2709 { 2710 if (board->flags & FL_NOIRQ) 2711 return 0; 2712 else 2713 return dev->irq; 2714 } 2715 2716 /* 2717 * This is the configuration table for all of the PCI serial boards 2718 * which we support. It is directly indexed by the pci_board_num_t enum 2719 * value, which is encoded in the pci_device_id PCI probe table's 2720 * driver_data member. 2721 * 2722 * The makeup of these names are: 2723 * pbn_bn{_bt}_n_baud{_offsetinhex} 2724 * 2725 * bn = PCI BAR number 2726 * bt = Index using PCI BARs 2727 * n = number of serial ports 2728 * baud = baud rate 2729 * offsetinhex = offset for each sequential port (in hex) 2730 * 2731 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2732 * 2733 * Please note: in theory if n = 1, _bt infix should make no difference. 2734 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2735 */ 2736 enum pci_board_num_t { 2737 pbn_default = 0, 2738 2739 pbn_b0_1_115200, 2740 pbn_b0_2_115200, 2741 pbn_b0_4_115200, 2742 pbn_b0_5_115200, 2743 pbn_b0_8_115200, 2744 2745 pbn_b0_1_921600, 2746 pbn_b0_2_921600, 2747 pbn_b0_4_921600, 2748 2749 pbn_b0_2_1130000, 2750 2751 pbn_b0_4_1152000, 2752 2753 pbn_b0_2_1152000_200, 2754 pbn_b0_4_1152000_200, 2755 pbn_b0_8_1152000_200, 2756 2757 pbn_b0_2_1843200, 2758 pbn_b0_4_1843200, 2759 2760 pbn_b0_2_1843200_200, 2761 pbn_b0_4_1843200_200, 2762 pbn_b0_8_1843200_200, 2763 2764 pbn_b0_1_4000000, 2765 2766 pbn_b0_bt_1_115200, 2767 pbn_b0_bt_2_115200, 2768 pbn_b0_bt_4_115200, 2769 pbn_b0_bt_8_115200, 2770 2771 pbn_b0_bt_1_460800, 2772 pbn_b0_bt_2_460800, 2773 pbn_b0_bt_4_460800, 2774 2775 pbn_b0_bt_1_921600, 2776 pbn_b0_bt_2_921600, 2777 pbn_b0_bt_4_921600, 2778 pbn_b0_bt_8_921600, 2779 2780 pbn_b1_1_115200, 2781 pbn_b1_2_115200, 2782 pbn_b1_4_115200, 2783 pbn_b1_8_115200, 2784 pbn_b1_16_115200, 2785 2786 pbn_b1_1_921600, 2787 pbn_b1_2_921600, 2788 pbn_b1_4_921600, 2789 pbn_b1_8_921600, 2790 2791 pbn_b1_2_1250000, 2792 2793 pbn_b1_bt_1_115200, 2794 pbn_b1_bt_2_115200, 2795 pbn_b1_bt_4_115200, 2796 2797 pbn_b1_bt_2_921600, 2798 2799 pbn_b1_1_1382400, 2800 pbn_b1_2_1382400, 2801 pbn_b1_4_1382400, 2802 pbn_b1_8_1382400, 2803 2804 pbn_b2_1_115200, 2805 pbn_b2_2_115200, 2806 pbn_b2_4_115200, 2807 pbn_b2_8_115200, 2808 2809 pbn_b2_1_460800, 2810 pbn_b2_4_460800, 2811 pbn_b2_8_460800, 2812 pbn_b2_16_460800, 2813 2814 pbn_b2_1_921600, 2815 pbn_b2_4_921600, 2816 pbn_b2_8_921600, 2817 2818 pbn_b2_8_1152000, 2819 2820 pbn_b2_bt_1_115200, 2821 pbn_b2_bt_2_115200, 2822 pbn_b2_bt_4_115200, 2823 2824 pbn_b2_bt_2_921600, 2825 pbn_b2_bt_4_921600, 2826 2827 pbn_b3_2_115200, 2828 pbn_b3_4_115200, 2829 pbn_b3_8_115200, 2830 2831 pbn_b4_bt_2_921600, 2832 pbn_b4_bt_4_921600, 2833 pbn_b4_bt_8_921600, 2834 2835 /* 2836 * Board-specific versions. 2837 */ 2838 pbn_panacom, 2839 pbn_panacom2, 2840 pbn_panacom4, 2841 pbn_plx_romulus, 2842 pbn_endrun_2_4000000, 2843 pbn_oxsemi, 2844 pbn_oxsemi_1_4000000, 2845 pbn_oxsemi_2_4000000, 2846 pbn_oxsemi_4_4000000, 2847 pbn_oxsemi_8_4000000, 2848 pbn_intel_i960, 2849 pbn_sgi_ioc3, 2850 pbn_computone_4, 2851 pbn_computone_6, 2852 pbn_computone_8, 2853 pbn_sbsxrsio, 2854 pbn_exar_XR17C152, 2855 pbn_exar_XR17C154, 2856 pbn_exar_XR17C158, 2857 pbn_exar_XR17V352, 2858 pbn_exar_XR17V354, 2859 pbn_exar_XR17V358, 2860 pbn_exar_ibm_saturn, 2861 pbn_pasemi_1682M, 2862 pbn_ni8430_2, 2863 pbn_ni8430_4, 2864 pbn_ni8430_8, 2865 pbn_ni8430_16, 2866 pbn_ADDIDATA_PCIe_1_3906250, 2867 pbn_ADDIDATA_PCIe_2_3906250, 2868 pbn_ADDIDATA_PCIe_4_3906250, 2869 pbn_ADDIDATA_PCIe_8_3906250, 2870 pbn_ce4100_1_115200, 2871 pbn_byt, 2872 pbn_qrk, 2873 pbn_omegapci, 2874 pbn_NETMOS9900_2s_115200, 2875 pbn_brcm_trumanage, 2876 pbn_fintek_4, 2877 pbn_fintek_8, 2878 pbn_fintek_12, 2879 }; 2880 2881 /* 2882 * uart_offset - the space between channels 2883 * reg_shift - describes how the UART registers are mapped 2884 * to PCI memory by the card. 2885 * For example IER register on SBS, Inc. PMC-OctPro is located at 2886 * offset 0x10 from the UART base, while UART_IER is defined as 1 2887 * in include/linux/serial_reg.h, 2888 * see first lines of serial_in() and serial_out() in 8250.c 2889 */ 2890 2891 static struct pciserial_board pci_boards[] = { 2892 [pbn_default] = { 2893 .flags = FL_BASE0, 2894 .num_ports = 1, 2895 .base_baud = 115200, 2896 .uart_offset = 8, 2897 }, 2898 [pbn_b0_1_115200] = { 2899 .flags = FL_BASE0, 2900 .num_ports = 1, 2901 .base_baud = 115200, 2902 .uart_offset = 8, 2903 }, 2904 [pbn_b0_2_115200] = { 2905 .flags = FL_BASE0, 2906 .num_ports = 2, 2907 .base_baud = 115200, 2908 .uart_offset = 8, 2909 }, 2910 [pbn_b0_4_115200] = { 2911 .flags = FL_BASE0, 2912 .num_ports = 4, 2913 .base_baud = 115200, 2914 .uart_offset = 8, 2915 }, 2916 [pbn_b0_5_115200] = { 2917 .flags = FL_BASE0, 2918 .num_ports = 5, 2919 .base_baud = 115200, 2920 .uart_offset = 8, 2921 }, 2922 [pbn_b0_8_115200] = { 2923 .flags = FL_BASE0, 2924 .num_ports = 8, 2925 .base_baud = 115200, 2926 .uart_offset = 8, 2927 }, 2928 [pbn_b0_1_921600] = { 2929 .flags = FL_BASE0, 2930 .num_ports = 1, 2931 .base_baud = 921600, 2932 .uart_offset = 8, 2933 }, 2934 [pbn_b0_2_921600] = { 2935 .flags = FL_BASE0, 2936 .num_ports = 2, 2937 .base_baud = 921600, 2938 .uart_offset = 8, 2939 }, 2940 [pbn_b0_4_921600] = { 2941 .flags = FL_BASE0, 2942 .num_ports = 4, 2943 .base_baud = 921600, 2944 .uart_offset = 8, 2945 }, 2946 2947 [pbn_b0_2_1130000] = { 2948 .flags = FL_BASE0, 2949 .num_ports = 2, 2950 .base_baud = 1130000, 2951 .uart_offset = 8, 2952 }, 2953 2954 [pbn_b0_4_1152000] = { 2955 .flags = FL_BASE0, 2956 .num_ports = 4, 2957 .base_baud = 1152000, 2958 .uart_offset = 8, 2959 }, 2960 2961 [pbn_b0_2_1152000_200] = { 2962 .flags = FL_BASE0, 2963 .num_ports = 2, 2964 .base_baud = 1152000, 2965 .uart_offset = 0x200, 2966 }, 2967 2968 [pbn_b0_4_1152000_200] = { 2969 .flags = FL_BASE0, 2970 .num_ports = 4, 2971 .base_baud = 1152000, 2972 .uart_offset = 0x200, 2973 }, 2974 2975 [pbn_b0_8_1152000_200] = { 2976 .flags = FL_BASE0, 2977 .num_ports = 8, 2978 .base_baud = 1152000, 2979 .uart_offset = 0x200, 2980 }, 2981 2982 [pbn_b0_2_1843200] = { 2983 .flags = FL_BASE0, 2984 .num_ports = 2, 2985 .base_baud = 1843200, 2986 .uart_offset = 8, 2987 }, 2988 [pbn_b0_4_1843200] = { 2989 .flags = FL_BASE0, 2990 .num_ports = 4, 2991 .base_baud = 1843200, 2992 .uart_offset = 8, 2993 }, 2994 2995 [pbn_b0_2_1843200_200] = { 2996 .flags = FL_BASE0, 2997 .num_ports = 2, 2998 .base_baud = 1843200, 2999 .uart_offset = 0x200, 3000 }, 3001 [pbn_b0_4_1843200_200] = { 3002 .flags = FL_BASE0, 3003 .num_ports = 4, 3004 .base_baud = 1843200, 3005 .uart_offset = 0x200, 3006 }, 3007 [pbn_b0_8_1843200_200] = { 3008 .flags = FL_BASE0, 3009 .num_ports = 8, 3010 .base_baud = 1843200, 3011 .uart_offset = 0x200, 3012 }, 3013 [pbn_b0_1_4000000] = { 3014 .flags = FL_BASE0, 3015 .num_ports = 1, 3016 .base_baud = 4000000, 3017 .uart_offset = 8, 3018 }, 3019 3020 [pbn_b0_bt_1_115200] = { 3021 .flags = FL_BASE0|FL_BASE_BARS, 3022 .num_ports = 1, 3023 .base_baud = 115200, 3024 .uart_offset = 8, 3025 }, 3026 [pbn_b0_bt_2_115200] = { 3027 .flags = FL_BASE0|FL_BASE_BARS, 3028 .num_ports = 2, 3029 .base_baud = 115200, 3030 .uart_offset = 8, 3031 }, 3032 [pbn_b0_bt_4_115200] = { 3033 .flags = FL_BASE0|FL_BASE_BARS, 3034 .num_ports = 4, 3035 .base_baud = 115200, 3036 .uart_offset = 8, 3037 }, 3038 [pbn_b0_bt_8_115200] = { 3039 .flags = FL_BASE0|FL_BASE_BARS, 3040 .num_ports = 8, 3041 .base_baud = 115200, 3042 .uart_offset = 8, 3043 }, 3044 3045 [pbn_b0_bt_1_460800] = { 3046 .flags = FL_BASE0|FL_BASE_BARS, 3047 .num_ports = 1, 3048 .base_baud = 460800, 3049 .uart_offset = 8, 3050 }, 3051 [pbn_b0_bt_2_460800] = { 3052 .flags = FL_BASE0|FL_BASE_BARS, 3053 .num_ports = 2, 3054 .base_baud = 460800, 3055 .uart_offset = 8, 3056 }, 3057 [pbn_b0_bt_4_460800] = { 3058 .flags = FL_BASE0|FL_BASE_BARS, 3059 .num_ports = 4, 3060 .base_baud = 460800, 3061 .uart_offset = 8, 3062 }, 3063 3064 [pbn_b0_bt_1_921600] = { 3065 .flags = FL_BASE0|FL_BASE_BARS, 3066 .num_ports = 1, 3067 .base_baud = 921600, 3068 .uart_offset = 8, 3069 }, 3070 [pbn_b0_bt_2_921600] = { 3071 .flags = FL_BASE0|FL_BASE_BARS, 3072 .num_ports = 2, 3073 .base_baud = 921600, 3074 .uart_offset = 8, 3075 }, 3076 [pbn_b0_bt_4_921600] = { 3077 .flags = FL_BASE0|FL_BASE_BARS, 3078 .num_ports = 4, 3079 .base_baud = 921600, 3080 .uart_offset = 8, 3081 }, 3082 [pbn_b0_bt_8_921600] = { 3083 .flags = FL_BASE0|FL_BASE_BARS, 3084 .num_ports = 8, 3085 .base_baud = 921600, 3086 .uart_offset = 8, 3087 }, 3088 3089 [pbn_b1_1_115200] = { 3090 .flags = FL_BASE1, 3091 .num_ports = 1, 3092 .base_baud = 115200, 3093 .uart_offset = 8, 3094 }, 3095 [pbn_b1_2_115200] = { 3096 .flags = FL_BASE1, 3097 .num_ports = 2, 3098 .base_baud = 115200, 3099 .uart_offset = 8, 3100 }, 3101 [pbn_b1_4_115200] = { 3102 .flags = FL_BASE1, 3103 .num_ports = 4, 3104 .base_baud = 115200, 3105 .uart_offset = 8, 3106 }, 3107 [pbn_b1_8_115200] = { 3108 .flags = FL_BASE1, 3109 .num_ports = 8, 3110 .base_baud = 115200, 3111 .uart_offset = 8, 3112 }, 3113 [pbn_b1_16_115200] = { 3114 .flags = FL_BASE1, 3115 .num_ports = 16, 3116 .base_baud = 115200, 3117 .uart_offset = 8, 3118 }, 3119 3120 [pbn_b1_1_921600] = { 3121 .flags = FL_BASE1, 3122 .num_ports = 1, 3123 .base_baud = 921600, 3124 .uart_offset = 8, 3125 }, 3126 [pbn_b1_2_921600] = { 3127 .flags = FL_BASE1, 3128 .num_ports = 2, 3129 .base_baud = 921600, 3130 .uart_offset = 8, 3131 }, 3132 [pbn_b1_4_921600] = { 3133 .flags = FL_BASE1, 3134 .num_ports = 4, 3135 .base_baud = 921600, 3136 .uart_offset = 8, 3137 }, 3138 [pbn_b1_8_921600] = { 3139 .flags = FL_BASE1, 3140 .num_ports = 8, 3141 .base_baud = 921600, 3142 .uart_offset = 8, 3143 }, 3144 [pbn_b1_2_1250000] = { 3145 .flags = FL_BASE1, 3146 .num_ports = 2, 3147 .base_baud = 1250000, 3148 .uart_offset = 8, 3149 }, 3150 3151 [pbn_b1_bt_1_115200] = { 3152 .flags = FL_BASE1|FL_BASE_BARS, 3153 .num_ports = 1, 3154 .base_baud = 115200, 3155 .uart_offset = 8, 3156 }, 3157 [pbn_b1_bt_2_115200] = { 3158 .flags = FL_BASE1|FL_BASE_BARS, 3159 .num_ports = 2, 3160 .base_baud = 115200, 3161 .uart_offset = 8, 3162 }, 3163 [pbn_b1_bt_4_115200] = { 3164 .flags = FL_BASE1|FL_BASE_BARS, 3165 .num_ports = 4, 3166 .base_baud = 115200, 3167 .uart_offset = 8, 3168 }, 3169 3170 [pbn_b1_bt_2_921600] = { 3171 .flags = FL_BASE1|FL_BASE_BARS, 3172 .num_ports = 2, 3173 .base_baud = 921600, 3174 .uart_offset = 8, 3175 }, 3176 3177 [pbn_b1_1_1382400] = { 3178 .flags = FL_BASE1, 3179 .num_ports = 1, 3180 .base_baud = 1382400, 3181 .uart_offset = 8, 3182 }, 3183 [pbn_b1_2_1382400] = { 3184 .flags = FL_BASE1, 3185 .num_ports = 2, 3186 .base_baud = 1382400, 3187 .uart_offset = 8, 3188 }, 3189 [pbn_b1_4_1382400] = { 3190 .flags = FL_BASE1, 3191 .num_ports = 4, 3192 .base_baud = 1382400, 3193 .uart_offset = 8, 3194 }, 3195 [pbn_b1_8_1382400] = { 3196 .flags = FL_BASE1, 3197 .num_ports = 8, 3198 .base_baud = 1382400, 3199 .uart_offset = 8, 3200 }, 3201 3202 [pbn_b2_1_115200] = { 3203 .flags = FL_BASE2, 3204 .num_ports = 1, 3205 .base_baud = 115200, 3206 .uart_offset = 8, 3207 }, 3208 [pbn_b2_2_115200] = { 3209 .flags = FL_BASE2, 3210 .num_ports = 2, 3211 .base_baud = 115200, 3212 .uart_offset = 8, 3213 }, 3214 [pbn_b2_4_115200] = { 3215 .flags = FL_BASE2, 3216 .num_ports = 4, 3217 .base_baud = 115200, 3218 .uart_offset = 8, 3219 }, 3220 [pbn_b2_8_115200] = { 3221 .flags = FL_BASE2, 3222 .num_ports = 8, 3223 .base_baud = 115200, 3224 .uart_offset = 8, 3225 }, 3226 3227 [pbn_b2_1_460800] = { 3228 .flags = FL_BASE2, 3229 .num_ports = 1, 3230 .base_baud = 460800, 3231 .uart_offset = 8, 3232 }, 3233 [pbn_b2_4_460800] = { 3234 .flags = FL_BASE2, 3235 .num_ports = 4, 3236 .base_baud = 460800, 3237 .uart_offset = 8, 3238 }, 3239 [pbn_b2_8_460800] = { 3240 .flags = FL_BASE2, 3241 .num_ports = 8, 3242 .base_baud = 460800, 3243 .uart_offset = 8, 3244 }, 3245 [pbn_b2_16_460800] = { 3246 .flags = FL_BASE2, 3247 .num_ports = 16, 3248 .base_baud = 460800, 3249 .uart_offset = 8, 3250 }, 3251 3252 [pbn_b2_1_921600] = { 3253 .flags = FL_BASE2, 3254 .num_ports = 1, 3255 .base_baud = 921600, 3256 .uart_offset = 8, 3257 }, 3258 [pbn_b2_4_921600] = { 3259 .flags = FL_BASE2, 3260 .num_ports = 4, 3261 .base_baud = 921600, 3262 .uart_offset = 8, 3263 }, 3264 [pbn_b2_8_921600] = { 3265 .flags = FL_BASE2, 3266 .num_ports = 8, 3267 .base_baud = 921600, 3268 .uart_offset = 8, 3269 }, 3270 3271 [pbn_b2_8_1152000] = { 3272 .flags = FL_BASE2, 3273 .num_ports = 8, 3274 .base_baud = 1152000, 3275 .uart_offset = 8, 3276 }, 3277 3278 [pbn_b2_bt_1_115200] = { 3279 .flags = FL_BASE2|FL_BASE_BARS, 3280 .num_ports = 1, 3281 .base_baud = 115200, 3282 .uart_offset = 8, 3283 }, 3284 [pbn_b2_bt_2_115200] = { 3285 .flags = FL_BASE2|FL_BASE_BARS, 3286 .num_ports = 2, 3287 .base_baud = 115200, 3288 .uart_offset = 8, 3289 }, 3290 [pbn_b2_bt_4_115200] = { 3291 .flags = FL_BASE2|FL_BASE_BARS, 3292 .num_ports = 4, 3293 .base_baud = 115200, 3294 .uart_offset = 8, 3295 }, 3296 3297 [pbn_b2_bt_2_921600] = { 3298 .flags = FL_BASE2|FL_BASE_BARS, 3299 .num_ports = 2, 3300 .base_baud = 921600, 3301 .uart_offset = 8, 3302 }, 3303 [pbn_b2_bt_4_921600] = { 3304 .flags = FL_BASE2|FL_BASE_BARS, 3305 .num_ports = 4, 3306 .base_baud = 921600, 3307 .uart_offset = 8, 3308 }, 3309 3310 [pbn_b3_2_115200] = { 3311 .flags = FL_BASE3, 3312 .num_ports = 2, 3313 .base_baud = 115200, 3314 .uart_offset = 8, 3315 }, 3316 [pbn_b3_4_115200] = { 3317 .flags = FL_BASE3, 3318 .num_ports = 4, 3319 .base_baud = 115200, 3320 .uart_offset = 8, 3321 }, 3322 [pbn_b3_8_115200] = { 3323 .flags = FL_BASE3, 3324 .num_ports = 8, 3325 .base_baud = 115200, 3326 .uart_offset = 8, 3327 }, 3328 3329 [pbn_b4_bt_2_921600] = { 3330 .flags = FL_BASE4, 3331 .num_ports = 2, 3332 .base_baud = 921600, 3333 .uart_offset = 8, 3334 }, 3335 [pbn_b4_bt_4_921600] = { 3336 .flags = FL_BASE4, 3337 .num_ports = 4, 3338 .base_baud = 921600, 3339 .uart_offset = 8, 3340 }, 3341 [pbn_b4_bt_8_921600] = { 3342 .flags = FL_BASE4, 3343 .num_ports = 8, 3344 .base_baud = 921600, 3345 .uart_offset = 8, 3346 }, 3347 3348 /* 3349 * Entries following this are board-specific. 3350 */ 3351 3352 /* 3353 * Panacom - IOMEM 3354 */ 3355 [pbn_panacom] = { 3356 .flags = FL_BASE2, 3357 .num_ports = 2, 3358 .base_baud = 921600, 3359 .uart_offset = 0x400, 3360 .reg_shift = 7, 3361 }, 3362 [pbn_panacom2] = { 3363 .flags = FL_BASE2|FL_BASE_BARS, 3364 .num_ports = 2, 3365 .base_baud = 921600, 3366 .uart_offset = 0x400, 3367 .reg_shift = 7, 3368 }, 3369 [pbn_panacom4] = { 3370 .flags = FL_BASE2|FL_BASE_BARS, 3371 .num_ports = 4, 3372 .base_baud = 921600, 3373 .uart_offset = 0x400, 3374 .reg_shift = 7, 3375 }, 3376 3377 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3378 [pbn_plx_romulus] = { 3379 .flags = FL_BASE2, 3380 .num_ports = 4, 3381 .base_baud = 921600, 3382 .uart_offset = 8 << 2, 3383 .reg_shift = 2, 3384 .first_offset = 0x03, 3385 }, 3386 3387 /* 3388 * EndRun Technologies 3389 * Uses the size of PCI Base region 0 to 3390 * signal now many ports are available 3391 * 2 port 952 Uart support 3392 */ 3393 [pbn_endrun_2_4000000] = { 3394 .flags = FL_BASE0, 3395 .num_ports = 2, 3396 .base_baud = 4000000, 3397 .uart_offset = 0x200, 3398 .first_offset = 0x1000, 3399 }, 3400 3401 /* 3402 * This board uses the size of PCI Base region 0 to 3403 * signal now many ports are available 3404 */ 3405 [pbn_oxsemi] = { 3406 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3407 .num_ports = 32, 3408 .base_baud = 115200, 3409 .uart_offset = 8, 3410 }, 3411 [pbn_oxsemi_1_4000000] = { 3412 .flags = FL_BASE0, 3413 .num_ports = 1, 3414 .base_baud = 4000000, 3415 .uart_offset = 0x200, 3416 .first_offset = 0x1000, 3417 }, 3418 [pbn_oxsemi_2_4000000] = { 3419 .flags = FL_BASE0, 3420 .num_ports = 2, 3421 .base_baud = 4000000, 3422 .uart_offset = 0x200, 3423 .first_offset = 0x1000, 3424 }, 3425 [pbn_oxsemi_4_4000000] = { 3426 .flags = FL_BASE0, 3427 .num_ports = 4, 3428 .base_baud = 4000000, 3429 .uart_offset = 0x200, 3430 .first_offset = 0x1000, 3431 }, 3432 [pbn_oxsemi_8_4000000] = { 3433 .flags = FL_BASE0, 3434 .num_ports = 8, 3435 .base_baud = 4000000, 3436 .uart_offset = 0x200, 3437 .first_offset = 0x1000, 3438 }, 3439 3440 3441 /* 3442 * EKF addition for i960 Boards form EKF with serial port. 3443 * Max 256 ports. 3444 */ 3445 [pbn_intel_i960] = { 3446 .flags = FL_BASE0, 3447 .num_ports = 32, 3448 .base_baud = 921600, 3449 .uart_offset = 8 << 2, 3450 .reg_shift = 2, 3451 .first_offset = 0x10000, 3452 }, 3453 [pbn_sgi_ioc3] = { 3454 .flags = FL_BASE0|FL_NOIRQ, 3455 .num_ports = 1, 3456 .base_baud = 458333, 3457 .uart_offset = 8, 3458 .reg_shift = 0, 3459 .first_offset = 0x20178, 3460 }, 3461 3462 /* 3463 * Computone - uses IOMEM. 3464 */ 3465 [pbn_computone_4] = { 3466 .flags = FL_BASE0, 3467 .num_ports = 4, 3468 .base_baud = 921600, 3469 .uart_offset = 0x40, 3470 .reg_shift = 2, 3471 .first_offset = 0x200, 3472 }, 3473 [pbn_computone_6] = { 3474 .flags = FL_BASE0, 3475 .num_ports = 6, 3476 .base_baud = 921600, 3477 .uart_offset = 0x40, 3478 .reg_shift = 2, 3479 .first_offset = 0x200, 3480 }, 3481 [pbn_computone_8] = { 3482 .flags = FL_BASE0, 3483 .num_ports = 8, 3484 .base_baud = 921600, 3485 .uart_offset = 0x40, 3486 .reg_shift = 2, 3487 .first_offset = 0x200, 3488 }, 3489 [pbn_sbsxrsio] = { 3490 .flags = FL_BASE0, 3491 .num_ports = 8, 3492 .base_baud = 460800, 3493 .uart_offset = 256, 3494 .reg_shift = 4, 3495 }, 3496 /* 3497 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3498 * Only basic 16550A support. 3499 * XR17C15[24] are not tested, but they should work. 3500 */ 3501 [pbn_exar_XR17C152] = { 3502 .flags = FL_BASE0, 3503 .num_ports = 2, 3504 .base_baud = 921600, 3505 .uart_offset = 0x200, 3506 }, 3507 [pbn_exar_XR17C154] = { 3508 .flags = FL_BASE0, 3509 .num_ports = 4, 3510 .base_baud = 921600, 3511 .uart_offset = 0x200, 3512 }, 3513 [pbn_exar_XR17C158] = { 3514 .flags = FL_BASE0, 3515 .num_ports = 8, 3516 .base_baud = 921600, 3517 .uart_offset = 0x200, 3518 }, 3519 [pbn_exar_XR17V352] = { 3520 .flags = FL_BASE0, 3521 .num_ports = 2, 3522 .base_baud = 7812500, 3523 .uart_offset = 0x400, 3524 .reg_shift = 0, 3525 .first_offset = 0, 3526 }, 3527 [pbn_exar_XR17V354] = { 3528 .flags = FL_BASE0, 3529 .num_ports = 4, 3530 .base_baud = 7812500, 3531 .uart_offset = 0x400, 3532 .reg_shift = 0, 3533 .first_offset = 0, 3534 }, 3535 [pbn_exar_XR17V358] = { 3536 .flags = FL_BASE0, 3537 .num_ports = 8, 3538 .base_baud = 7812500, 3539 .uart_offset = 0x400, 3540 .reg_shift = 0, 3541 .first_offset = 0, 3542 }, 3543 [pbn_exar_ibm_saturn] = { 3544 .flags = FL_BASE0, 3545 .num_ports = 1, 3546 .base_baud = 921600, 3547 .uart_offset = 0x200, 3548 }, 3549 3550 /* 3551 * PA Semi PWRficient PA6T-1682M on-chip UART 3552 */ 3553 [pbn_pasemi_1682M] = { 3554 .flags = FL_BASE0, 3555 .num_ports = 1, 3556 .base_baud = 8333333, 3557 }, 3558 /* 3559 * National Instruments 843x 3560 */ 3561 [pbn_ni8430_16] = { 3562 .flags = FL_BASE0, 3563 .num_ports = 16, 3564 .base_baud = 3686400, 3565 .uart_offset = 0x10, 3566 .first_offset = 0x800, 3567 }, 3568 [pbn_ni8430_8] = { 3569 .flags = FL_BASE0, 3570 .num_ports = 8, 3571 .base_baud = 3686400, 3572 .uart_offset = 0x10, 3573 .first_offset = 0x800, 3574 }, 3575 [pbn_ni8430_4] = { 3576 .flags = FL_BASE0, 3577 .num_ports = 4, 3578 .base_baud = 3686400, 3579 .uart_offset = 0x10, 3580 .first_offset = 0x800, 3581 }, 3582 [pbn_ni8430_2] = { 3583 .flags = FL_BASE0, 3584 .num_ports = 2, 3585 .base_baud = 3686400, 3586 .uart_offset = 0x10, 3587 .first_offset = 0x800, 3588 }, 3589 /* 3590 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3591 */ 3592 [pbn_ADDIDATA_PCIe_1_3906250] = { 3593 .flags = FL_BASE0, 3594 .num_ports = 1, 3595 .base_baud = 3906250, 3596 .uart_offset = 0x200, 3597 .first_offset = 0x1000, 3598 }, 3599 [pbn_ADDIDATA_PCIe_2_3906250] = { 3600 .flags = FL_BASE0, 3601 .num_ports = 2, 3602 .base_baud = 3906250, 3603 .uart_offset = 0x200, 3604 .first_offset = 0x1000, 3605 }, 3606 [pbn_ADDIDATA_PCIe_4_3906250] = { 3607 .flags = FL_BASE0, 3608 .num_ports = 4, 3609 .base_baud = 3906250, 3610 .uart_offset = 0x200, 3611 .first_offset = 0x1000, 3612 }, 3613 [pbn_ADDIDATA_PCIe_8_3906250] = { 3614 .flags = FL_BASE0, 3615 .num_ports = 8, 3616 .base_baud = 3906250, 3617 .uart_offset = 0x200, 3618 .first_offset = 0x1000, 3619 }, 3620 [pbn_ce4100_1_115200] = { 3621 .flags = FL_BASE_BARS, 3622 .num_ports = 2, 3623 .base_baud = 921600, 3624 .reg_shift = 2, 3625 }, 3626 /* 3627 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3628 * but is overridden by byt_set_termios. 3629 */ 3630 [pbn_byt] = { 3631 .flags = FL_BASE0, 3632 .num_ports = 1, 3633 .base_baud = 2764800, 3634 .uart_offset = 0x80, 3635 .reg_shift = 2, 3636 }, 3637 [pbn_qrk] = { 3638 .flags = FL_BASE0, 3639 .num_ports = 1, 3640 .base_baud = 2764800, 3641 .reg_shift = 2, 3642 }, 3643 [pbn_omegapci] = { 3644 .flags = FL_BASE0, 3645 .num_ports = 8, 3646 .base_baud = 115200, 3647 .uart_offset = 0x200, 3648 }, 3649 [pbn_NETMOS9900_2s_115200] = { 3650 .flags = FL_BASE0, 3651 .num_ports = 2, 3652 .base_baud = 115200, 3653 }, 3654 [pbn_brcm_trumanage] = { 3655 .flags = FL_BASE0, 3656 .num_ports = 1, 3657 .reg_shift = 2, 3658 .base_baud = 115200, 3659 }, 3660 [pbn_fintek_4] = { 3661 .num_ports = 4, 3662 .uart_offset = 8, 3663 .base_baud = 115200, 3664 .first_offset = 0x40, 3665 }, 3666 [pbn_fintek_8] = { 3667 .num_ports = 8, 3668 .uart_offset = 8, 3669 .base_baud = 115200, 3670 .first_offset = 0x40, 3671 }, 3672 [pbn_fintek_12] = { 3673 .num_ports = 12, 3674 .uart_offset = 8, 3675 .base_baud = 115200, 3676 .first_offset = 0x40, 3677 }, 3678 }; 3679 3680 static const struct pci_device_id blacklist[] = { 3681 /* softmodems */ 3682 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3683 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3684 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3685 3686 /* multi-io cards handled by parport_serial */ 3687 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3688 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3689 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3690 }; 3691 3692 /* 3693 * Given a complete unknown PCI device, try to use some heuristics to 3694 * guess what the configuration might be, based on the pitiful PCI 3695 * serial specs. Returns 0 on success, 1 on failure. 3696 */ 3697 static int 3698 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3699 { 3700 const struct pci_device_id *bldev; 3701 int num_iomem, num_port, first_port = -1, i; 3702 3703 /* 3704 * If it is not a communications device or the programming 3705 * interface is greater than 6, give up. 3706 * 3707 * (Should we try to make guesses for multiport serial devices 3708 * later?) 3709 */ 3710 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3711 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3712 (dev->class & 0xff) > 6) 3713 return -ENODEV; 3714 3715 /* 3716 * Do not access blacklisted devices that are known not to 3717 * feature serial ports or are handled by other modules. 3718 */ 3719 for (bldev = blacklist; 3720 bldev < blacklist + ARRAY_SIZE(blacklist); 3721 bldev++) { 3722 if (dev->vendor == bldev->vendor && 3723 dev->device == bldev->device) 3724 return -ENODEV; 3725 } 3726 3727 num_iomem = num_port = 0; 3728 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3729 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3730 num_port++; 3731 if (first_port == -1) 3732 first_port = i; 3733 } 3734 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3735 num_iomem++; 3736 } 3737 3738 /* 3739 * If there is 1 or 0 iomem regions, and exactly one port, 3740 * use it. We guess the number of ports based on the IO 3741 * region size. 3742 */ 3743 if (num_iomem <= 1 && num_port == 1) { 3744 board->flags = first_port; 3745 board->num_ports = pci_resource_len(dev, first_port) / 8; 3746 return 0; 3747 } 3748 3749 /* 3750 * Now guess if we've got a board which indexes by BARs. 3751 * Each IO BAR should be 8 bytes, and they should follow 3752 * consecutively. 3753 */ 3754 first_port = -1; 3755 num_port = 0; 3756 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3757 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3758 pci_resource_len(dev, i) == 8 && 3759 (first_port == -1 || (first_port + num_port) == i)) { 3760 num_port++; 3761 if (first_port == -1) 3762 first_port = i; 3763 } 3764 } 3765 3766 if (num_port > 1) { 3767 board->flags = first_port | FL_BASE_BARS; 3768 board->num_ports = num_port; 3769 return 0; 3770 } 3771 3772 return -ENODEV; 3773 } 3774 3775 static inline int 3776 serial_pci_matches(const struct pciserial_board *board, 3777 const struct pciserial_board *guessed) 3778 { 3779 return 3780 board->num_ports == guessed->num_ports && 3781 board->base_baud == guessed->base_baud && 3782 board->uart_offset == guessed->uart_offset && 3783 board->reg_shift == guessed->reg_shift && 3784 board->first_offset == guessed->first_offset; 3785 } 3786 3787 struct serial_private * 3788 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3789 { 3790 struct uart_8250_port uart; 3791 struct serial_private *priv; 3792 struct pci_serial_quirk *quirk; 3793 int rc, nr_ports, i; 3794 3795 nr_ports = board->num_ports; 3796 3797 /* 3798 * Find an init and setup quirks. 3799 */ 3800 quirk = find_quirk(dev); 3801 3802 /* 3803 * Run the new-style initialization function. 3804 * The initialization function returns: 3805 * <0 - error 3806 * 0 - use board->num_ports 3807 * >0 - number of ports 3808 */ 3809 if (quirk->init) { 3810 rc = quirk->init(dev); 3811 if (rc < 0) { 3812 priv = ERR_PTR(rc); 3813 goto err_out; 3814 } 3815 if (rc) 3816 nr_ports = rc; 3817 } 3818 3819 priv = kzalloc(sizeof(struct serial_private) + 3820 sizeof(unsigned int) * nr_ports, 3821 GFP_KERNEL); 3822 if (!priv) { 3823 priv = ERR_PTR(-ENOMEM); 3824 goto err_deinit; 3825 } 3826 3827 priv->dev = dev; 3828 priv->quirk = quirk; 3829 3830 memset(&uart, 0, sizeof(uart)); 3831 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3832 uart.port.uartclk = board->base_baud * 16; 3833 uart.port.irq = get_pci_irq(dev, board); 3834 uart.port.dev = &dev->dev; 3835 3836 for (i = 0; i < nr_ports; i++) { 3837 if (quirk->setup(priv, board, &uart, i)) 3838 break; 3839 3840 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3841 uart.port.iobase, uart.port.irq, uart.port.iotype); 3842 3843 priv->line[i] = serial8250_register_8250_port(&uart); 3844 if (priv->line[i] < 0) { 3845 dev_err(&dev->dev, 3846 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3847 uart.port.iobase, uart.port.irq, 3848 uart.port.iotype, priv->line[i]); 3849 break; 3850 } 3851 } 3852 priv->nr = i; 3853 return priv; 3854 3855 err_deinit: 3856 if (quirk->exit) 3857 quirk->exit(dev); 3858 err_out: 3859 return priv; 3860 } 3861 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3862 3863 void pciserial_remove_ports(struct serial_private *priv) 3864 { 3865 struct pci_serial_quirk *quirk; 3866 int i; 3867 3868 for (i = 0; i < priv->nr; i++) 3869 serial8250_unregister_port(priv->line[i]); 3870 3871 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3872 if (priv->remapped_bar[i]) 3873 iounmap(priv->remapped_bar[i]); 3874 priv->remapped_bar[i] = NULL; 3875 } 3876 3877 /* 3878 * Find the exit quirks. 3879 */ 3880 quirk = find_quirk(priv->dev); 3881 if (quirk->exit) 3882 quirk->exit(priv->dev); 3883 3884 kfree(priv); 3885 } 3886 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3887 3888 void pciserial_suspend_ports(struct serial_private *priv) 3889 { 3890 int i; 3891 3892 for (i = 0; i < priv->nr; i++) 3893 if (priv->line[i] >= 0) 3894 serial8250_suspend_port(priv->line[i]); 3895 3896 /* 3897 * Ensure that every init quirk is properly torn down 3898 */ 3899 if (priv->quirk->exit) 3900 priv->quirk->exit(priv->dev); 3901 } 3902 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3903 3904 void pciserial_resume_ports(struct serial_private *priv) 3905 { 3906 int i; 3907 3908 /* 3909 * Ensure that the board is correctly configured. 3910 */ 3911 if (priv->quirk->init) 3912 priv->quirk->init(priv->dev); 3913 3914 for (i = 0; i < priv->nr; i++) 3915 if (priv->line[i] >= 0) 3916 serial8250_resume_port(priv->line[i]); 3917 } 3918 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3919 3920 /* 3921 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3922 * to the arrangement of serial ports on a PCI card. 3923 */ 3924 static int 3925 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3926 { 3927 struct pci_serial_quirk *quirk; 3928 struct serial_private *priv; 3929 const struct pciserial_board *board; 3930 struct pciserial_board tmp; 3931 int rc; 3932 3933 quirk = find_quirk(dev); 3934 if (quirk->probe) { 3935 rc = quirk->probe(dev); 3936 if (rc) 3937 return rc; 3938 } 3939 3940 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3941 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3942 ent->driver_data); 3943 return -EINVAL; 3944 } 3945 3946 board = &pci_boards[ent->driver_data]; 3947 3948 rc = pci_enable_device(dev); 3949 pci_save_state(dev); 3950 if (rc) 3951 return rc; 3952 3953 if (ent->driver_data == pbn_default) { 3954 /* 3955 * Use a copy of the pci_board entry for this; 3956 * avoid changing entries in the table. 3957 */ 3958 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3959 board = &tmp; 3960 3961 /* 3962 * We matched one of our class entries. Try to 3963 * determine the parameters of this board. 3964 */ 3965 rc = serial_pci_guess_board(dev, &tmp); 3966 if (rc) 3967 goto disable; 3968 } else { 3969 /* 3970 * We matched an explicit entry. If we are able to 3971 * detect this boards settings with our heuristic, 3972 * then we no longer need this entry. 3973 */ 3974 memcpy(&tmp, &pci_boards[pbn_default], 3975 sizeof(struct pciserial_board)); 3976 rc = serial_pci_guess_board(dev, &tmp); 3977 if (rc == 0 && serial_pci_matches(board, &tmp)) 3978 moan_device("Redundant entry in serial pci_table.", 3979 dev); 3980 } 3981 3982 priv = pciserial_init_ports(dev, board); 3983 if (!IS_ERR(priv)) { 3984 pci_set_drvdata(dev, priv); 3985 return 0; 3986 } 3987 3988 rc = PTR_ERR(priv); 3989 3990 disable: 3991 pci_disable_device(dev); 3992 return rc; 3993 } 3994 3995 static void pciserial_remove_one(struct pci_dev *dev) 3996 { 3997 struct serial_private *priv = pci_get_drvdata(dev); 3998 3999 pciserial_remove_ports(priv); 4000 4001 pci_disable_device(dev); 4002 } 4003 4004 #ifdef CONFIG_PM 4005 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) 4006 { 4007 struct serial_private *priv = pci_get_drvdata(dev); 4008 4009 if (priv) 4010 pciserial_suspend_ports(priv); 4011 4012 pci_save_state(dev); 4013 pci_set_power_state(dev, pci_choose_state(dev, state)); 4014 return 0; 4015 } 4016 4017 static int pciserial_resume_one(struct pci_dev *dev) 4018 { 4019 int err; 4020 struct serial_private *priv = pci_get_drvdata(dev); 4021 4022 pci_set_power_state(dev, PCI_D0); 4023 pci_restore_state(dev); 4024 4025 if (priv) { 4026 /* 4027 * The device may have been disabled. Re-enable it. 4028 */ 4029 err = pci_enable_device(dev); 4030 /* FIXME: We cannot simply error out here */ 4031 if (err) 4032 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n"); 4033 pciserial_resume_ports(priv); 4034 } 4035 return 0; 4036 } 4037 #endif 4038 4039 static struct pci_device_id serial_pci_tbl[] = { 4040 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4041 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4042 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4043 pbn_b2_8_921600 }, 4044 /* Advantech also use 0x3618 and 0xf618 */ 4045 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4046 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4047 pbn_b0_4_921600 }, 4048 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4049 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4050 pbn_b0_4_921600 }, 4051 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4052 PCI_SUBVENDOR_ID_CONNECT_TECH, 4053 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4054 pbn_b1_8_1382400 }, 4055 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4056 PCI_SUBVENDOR_ID_CONNECT_TECH, 4057 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4058 pbn_b1_4_1382400 }, 4059 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4060 PCI_SUBVENDOR_ID_CONNECT_TECH, 4061 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4062 pbn_b1_2_1382400 }, 4063 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4064 PCI_SUBVENDOR_ID_CONNECT_TECH, 4065 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4066 pbn_b1_8_1382400 }, 4067 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4068 PCI_SUBVENDOR_ID_CONNECT_TECH, 4069 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4070 pbn_b1_4_1382400 }, 4071 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4072 PCI_SUBVENDOR_ID_CONNECT_TECH, 4073 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4074 pbn_b1_2_1382400 }, 4075 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4076 PCI_SUBVENDOR_ID_CONNECT_TECH, 4077 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4078 pbn_b1_8_921600 }, 4079 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4080 PCI_SUBVENDOR_ID_CONNECT_TECH, 4081 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4082 pbn_b1_8_921600 }, 4083 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4084 PCI_SUBVENDOR_ID_CONNECT_TECH, 4085 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4086 pbn_b1_4_921600 }, 4087 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4088 PCI_SUBVENDOR_ID_CONNECT_TECH, 4089 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4090 pbn_b1_4_921600 }, 4091 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4092 PCI_SUBVENDOR_ID_CONNECT_TECH, 4093 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4094 pbn_b1_2_921600 }, 4095 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4096 PCI_SUBVENDOR_ID_CONNECT_TECH, 4097 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4098 pbn_b1_8_921600 }, 4099 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4100 PCI_SUBVENDOR_ID_CONNECT_TECH, 4101 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4102 pbn_b1_8_921600 }, 4103 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4104 PCI_SUBVENDOR_ID_CONNECT_TECH, 4105 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4106 pbn_b1_4_921600 }, 4107 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4108 PCI_SUBVENDOR_ID_CONNECT_TECH, 4109 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4110 pbn_b1_2_1250000 }, 4111 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4112 PCI_SUBVENDOR_ID_CONNECT_TECH, 4113 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4114 pbn_b0_2_1843200 }, 4115 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4116 PCI_SUBVENDOR_ID_CONNECT_TECH, 4117 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4118 pbn_b0_4_1843200 }, 4119 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4120 PCI_VENDOR_ID_AFAVLAB, 4121 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4122 pbn_b0_4_1152000 }, 4123 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4124 PCI_SUBVENDOR_ID_CONNECT_TECH, 4125 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4126 pbn_b0_2_1843200_200 }, 4127 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4128 PCI_SUBVENDOR_ID_CONNECT_TECH, 4129 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4130 pbn_b0_4_1843200_200 }, 4131 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4132 PCI_SUBVENDOR_ID_CONNECT_TECH, 4133 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4134 pbn_b0_8_1843200_200 }, 4135 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4136 PCI_SUBVENDOR_ID_CONNECT_TECH, 4137 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4138 pbn_b0_2_1843200_200 }, 4139 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4140 PCI_SUBVENDOR_ID_CONNECT_TECH, 4141 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4142 pbn_b0_4_1843200_200 }, 4143 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4144 PCI_SUBVENDOR_ID_CONNECT_TECH, 4145 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4146 pbn_b0_8_1843200_200 }, 4147 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4148 PCI_SUBVENDOR_ID_CONNECT_TECH, 4149 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4150 pbn_b0_2_1843200_200 }, 4151 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4152 PCI_SUBVENDOR_ID_CONNECT_TECH, 4153 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4154 pbn_b0_4_1843200_200 }, 4155 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4156 PCI_SUBVENDOR_ID_CONNECT_TECH, 4157 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4158 pbn_b0_8_1843200_200 }, 4159 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4160 PCI_SUBVENDOR_ID_CONNECT_TECH, 4161 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4162 pbn_b0_2_1843200_200 }, 4163 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4164 PCI_SUBVENDOR_ID_CONNECT_TECH, 4165 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4166 pbn_b0_4_1843200_200 }, 4167 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4168 PCI_SUBVENDOR_ID_CONNECT_TECH, 4169 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4170 pbn_b0_8_1843200_200 }, 4171 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4172 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4173 0, 0, pbn_exar_ibm_saturn }, 4174 4175 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4177 pbn_b2_bt_1_115200 }, 4178 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4180 pbn_b2_bt_2_115200 }, 4181 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4183 pbn_b2_bt_4_115200 }, 4184 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4186 pbn_b2_bt_2_115200 }, 4187 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4189 pbn_b2_bt_4_115200 }, 4190 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4192 pbn_b2_8_115200 }, 4193 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4195 pbn_b2_8_460800 }, 4196 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4198 pbn_b2_8_115200 }, 4199 4200 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4202 pbn_b2_bt_2_115200 }, 4203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b2_bt_2_921600 }, 4206 /* 4207 * VScom SPCOM800, from sl@s.pl 4208 */ 4209 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4211 pbn_b2_8_921600 }, 4212 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4214 pbn_b2_4_921600 }, 4215 /* Unknown card - subdevice 0x1584 */ 4216 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4217 PCI_VENDOR_ID_PLX, 4218 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4219 pbn_b2_4_115200 }, 4220 /* Unknown card - subdevice 0x1588 */ 4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4222 PCI_VENDOR_ID_PLX, 4223 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4224 pbn_b2_8_115200 }, 4225 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4226 PCI_SUBVENDOR_ID_KEYSPAN, 4227 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4228 pbn_panacom }, 4229 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4231 pbn_panacom4 }, 4232 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4234 pbn_panacom2 }, 4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4236 PCI_VENDOR_ID_ESDGMBH, 4237 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4238 pbn_b2_4_115200 }, 4239 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4240 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4241 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4242 pbn_b2_4_460800 }, 4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4244 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4245 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4246 pbn_b2_8_460800 }, 4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4248 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4249 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4250 pbn_b2_16_460800 }, 4251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4252 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4253 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4254 pbn_b2_16_460800 }, 4255 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4256 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4257 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4258 pbn_b2_4_460800 }, 4259 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4260 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4261 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4262 pbn_b2_8_460800 }, 4263 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4264 PCI_SUBVENDOR_ID_EXSYS, 4265 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4266 pbn_b2_4_115200 }, 4267 /* 4268 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4269 * (Exoray@isys.ca) 4270 */ 4271 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4272 0x10b5, 0x106a, 0, 0, 4273 pbn_plx_romulus }, 4274 /* 4275 * EndRun Technologies. PCI express device range. 4276 * EndRun PTP/1588 has 2 Native UARTs. 4277 */ 4278 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4280 pbn_endrun_2_4000000 }, 4281 /* 4282 * Quatech cards. These actually have configurable clocks but for 4283 * now we just use the default. 4284 * 4285 * 100 series are RS232, 200 series RS422, 4286 */ 4287 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_b1_4_115200 }, 4290 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4292 pbn_b1_2_115200 }, 4293 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4295 pbn_b2_2_115200 }, 4296 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_b1_2_115200 }, 4299 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_b2_2_115200 }, 4302 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_b1_4_115200 }, 4305 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_b1_8_115200 }, 4308 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_b1_8_115200 }, 4311 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_b1_4_115200 }, 4314 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_b1_2_115200 }, 4317 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_b1_4_115200 }, 4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_b1_2_115200 }, 4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_b2_4_115200 }, 4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_b2_2_115200 }, 4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_b2_1_115200 }, 4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_b2_4_115200 }, 4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_b2_2_115200 }, 4338 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4340 pbn_b2_1_115200 }, 4341 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_b0_8_115200 }, 4344 4345 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4346 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4347 0, 0, 4348 pbn_b0_4_921600 }, 4349 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4350 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4351 0, 0, 4352 pbn_b0_4_1152000 }, 4353 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4355 pbn_b0_bt_2_921600 }, 4356 4357 /* 4358 * The below card is a little controversial since it is the 4359 * subject of a PCI vendor/device ID clash. (See 4360 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4361 * For now just used the hex ID 0x950a. 4362 */ 4363 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4364 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4365 0, 0, pbn_b0_2_115200 }, 4366 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4367 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4368 0, 0, pbn_b0_2_115200 }, 4369 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4371 pbn_b0_2_1130000 }, 4372 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4373 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4374 pbn_b0_1_921600 }, 4375 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4377 pbn_b0_4_115200 }, 4378 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4380 pbn_b0_bt_2_921600 }, 4381 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4382 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4383 pbn_b2_8_1152000 }, 4384 4385 /* 4386 * Oxford Semiconductor Inc. Tornado PCI express device range. 4387 */ 4388 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_b0_1_4000000 }, 4391 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4393 pbn_b0_1_4000000 }, 4394 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4396 pbn_oxsemi_1_4000000 }, 4397 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4399 pbn_oxsemi_1_4000000 }, 4400 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4402 pbn_b0_1_4000000 }, 4403 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4405 pbn_b0_1_4000000 }, 4406 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4408 pbn_oxsemi_1_4000000 }, 4409 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_oxsemi_1_4000000 }, 4412 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b0_1_4000000 }, 4415 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_b0_1_4000000 }, 4418 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_b0_1_4000000 }, 4421 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_b0_1_4000000 }, 4424 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_oxsemi_2_4000000 }, 4427 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_oxsemi_2_4000000 }, 4430 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_oxsemi_4_4000000 }, 4433 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_oxsemi_4_4000000 }, 4436 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_oxsemi_8_4000000 }, 4439 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_oxsemi_8_4000000 }, 4442 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_oxsemi_1_4000000 }, 4445 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_oxsemi_1_4000000 }, 4448 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_oxsemi_1_4000000 }, 4451 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_oxsemi_1_4000000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_oxsemi_1_4000000 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_oxsemi_1_4000000 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_oxsemi_1_4000000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_oxsemi_1_4000000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_1_4000000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_4000000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_1_4000000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_oxsemi_1_4000000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_4000000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_4000000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_4000000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_oxsemi_1_4000000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_oxsemi_1_4000000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_oxsemi_1_4000000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_1_4000000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_1_4000000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_1_4000000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_1_4000000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_1_4000000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_1_4000000 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_1_4000000 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_4000000 }, 4520 /* 4521 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4522 */ 4523 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4524 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4525 pbn_oxsemi_1_4000000 }, 4526 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4527 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4528 pbn_oxsemi_2_4000000 }, 4529 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4530 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4531 pbn_oxsemi_4_4000000 }, 4532 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4533 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4534 pbn_oxsemi_8_4000000 }, 4535 4536 /* 4537 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4538 */ 4539 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4540 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4541 pbn_oxsemi_2_4000000 }, 4542 4543 /* 4544 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4545 * from skokodyn@yahoo.com 4546 */ 4547 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4548 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4549 pbn_sbsxrsio }, 4550 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4551 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4552 pbn_sbsxrsio }, 4553 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4554 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4555 pbn_sbsxrsio }, 4556 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4557 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4558 pbn_sbsxrsio }, 4559 4560 /* 4561 * Digitan DS560-558, from jimd@esoft.com 4562 */ 4563 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4565 pbn_b1_1_115200 }, 4566 4567 /* 4568 * Titan Electronic cards 4569 * The 400L and 800L have a custom setup quirk. 4570 */ 4571 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_b0_1_921600 }, 4574 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_b0_2_921600 }, 4577 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_b0_4_921600 }, 4580 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_b0_4_921600 }, 4583 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_b1_1_921600 }, 4586 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_b1_bt_2_921600 }, 4589 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_b0_bt_4_921600 }, 4592 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_b0_bt_8_921600 }, 4595 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4597 pbn_b4_bt_2_921600 }, 4598 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_b4_bt_4_921600 }, 4601 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4603 pbn_b4_bt_8_921600 }, 4604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_b0_4_921600 }, 4607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_b0_4_921600 }, 4610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_b0_4_921600 }, 4613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_oxsemi_1_4000000 }, 4616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_oxsemi_2_4000000 }, 4619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_oxsemi_4_4000000 }, 4622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_oxsemi_8_4000000 }, 4625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_oxsemi_2_4000000 }, 4628 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_oxsemi_2_4000000 }, 4631 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_b0_bt_2_921600 }, 4634 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_b0_4_921600 }, 4637 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_b0_4_921600 }, 4640 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_b0_4_921600 }, 4643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_b0_4_921600 }, 4646 4647 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_b2_1_460800 }, 4650 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b2_1_460800 }, 4653 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b2_1_460800 }, 4656 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b2_bt_2_921600 }, 4659 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b2_bt_2_921600 }, 4662 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b2_bt_2_921600 }, 4665 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b2_bt_4_921600 }, 4668 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b2_bt_4_921600 }, 4671 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b2_bt_4_921600 }, 4674 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b0_1_921600 }, 4677 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b0_1_921600 }, 4680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b0_1_921600 }, 4683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b0_bt_2_921600 }, 4686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b0_bt_2_921600 }, 4689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b0_bt_2_921600 }, 4692 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b0_bt_4_921600 }, 4695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_b0_bt_4_921600 }, 4698 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_b0_bt_4_921600 }, 4701 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_b0_bt_8_921600 }, 4704 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_b0_bt_8_921600 }, 4707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_b0_bt_8_921600 }, 4710 4711 /* 4712 * Computone devices submitted by Doug McNash dmcnash@computone.com 4713 */ 4714 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4715 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4716 0, 0, pbn_computone_4 }, 4717 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4718 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4719 0, 0, pbn_computone_8 }, 4720 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4721 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4722 0, 0, pbn_computone_6 }, 4723 4724 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4726 pbn_oxsemi }, 4727 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4728 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4729 pbn_b0_bt_1_921600 }, 4730 4731 /* 4732 * SUNIX (TIMEDIA) 4733 */ 4734 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4735 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4736 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4737 pbn_b0_bt_1_921600 }, 4738 4739 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4740 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4741 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4742 pbn_b0_bt_1_921600 }, 4743 4744 /* 4745 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4746 */ 4747 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4749 pbn_b0_bt_8_115200 }, 4750 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4752 pbn_b0_bt_8_115200 }, 4753 4754 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4756 pbn_b0_bt_2_115200 }, 4757 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4759 pbn_b0_bt_2_115200 }, 4760 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_b0_bt_2_115200 }, 4763 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_b0_bt_2_115200 }, 4766 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_b0_bt_2_115200 }, 4769 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_b0_bt_4_460800 }, 4772 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4774 pbn_b0_bt_4_460800 }, 4775 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4777 pbn_b0_bt_2_460800 }, 4778 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4780 pbn_b0_bt_2_460800 }, 4781 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4783 pbn_b0_bt_2_460800 }, 4784 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_b0_bt_1_115200 }, 4787 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_b0_bt_1_460800 }, 4790 4791 /* 4792 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4793 * Cards are identified by their subsystem vendor IDs, which 4794 * (in hex) match the model number. 4795 * 4796 * Note that JC140x are RS422/485 cards which require ox950 4797 * ACR = 0x10, and as such are not currently fully supported. 4798 */ 4799 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4800 0x1204, 0x0004, 0, 0, 4801 pbn_b0_4_921600 }, 4802 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4803 0x1208, 0x0004, 0, 0, 4804 pbn_b0_4_921600 }, 4805 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4806 0x1402, 0x0002, 0, 0, 4807 pbn_b0_2_921600 }, */ 4808 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4809 0x1404, 0x0004, 0, 0, 4810 pbn_b0_4_921600 }, */ 4811 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4812 0x1208, 0x0004, 0, 0, 4813 pbn_b0_4_921600 }, 4814 4815 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4816 0x1204, 0x0004, 0, 0, 4817 pbn_b0_4_921600 }, 4818 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4819 0x1208, 0x0004, 0, 0, 4820 pbn_b0_4_921600 }, 4821 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4822 0x1208, 0x0004, 0, 0, 4823 pbn_b0_4_921600 }, 4824 /* 4825 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4826 */ 4827 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4828 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4829 pbn_b1_1_1382400 }, 4830 4831 /* 4832 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4833 */ 4834 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4836 pbn_b1_1_1382400 }, 4837 4838 /* 4839 * RAStel 2 port modem, gerg@moreton.com.au 4840 */ 4841 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4843 pbn_b2_bt_2_115200 }, 4844 4845 /* 4846 * EKF addition for i960 Boards form EKF with serial port 4847 */ 4848 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4849 0xE4BF, PCI_ANY_ID, 0, 0, 4850 pbn_intel_i960 }, 4851 4852 /* 4853 * Xircom Cardbus/Ethernet combos 4854 */ 4855 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4857 pbn_b0_1_115200 }, 4858 /* 4859 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4860 */ 4861 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4862 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4863 pbn_b0_1_115200 }, 4864 4865 /* 4866 * Untested PCI modems, sent in from various folks... 4867 */ 4868 4869 /* 4870 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4871 */ 4872 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4873 0x1048, 0x1500, 0, 0, 4874 pbn_b1_1_115200 }, 4875 4876 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4877 0xFF00, 0, 0, 0, 4878 pbn_sgi_ioc3 }, 4879 4880 /* 4881 * HP Diva card 4882 */ 4883 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4884 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4885 pbn_b1_1_115200 }, 4886 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4888 pbn_b0_5_115200 }, 4889 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4891 pbn_b2_1_115200 }, 4892 4893 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4895 pbn_b3_2_115200 }, 4896 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4898 pbn_b3_4_115200 }, 4899 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_b3_8_115200 }, 4902 4903 /* 4904 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4905 */ 4906 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4907 PCI_ANY_ID, PCI_ANY_ID, 4908 0, 4909 0, pbn_exar_XR17C152 }, 4910 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4911 PCI_ANY_ID, PCI_ANY_ID, 4912 0, 4913 0, pbn_exar_XR17C154 }, 4914 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4915 PCI_ANY_ID, PCI_ANY_ID, 4916 0, 4917 0, pbn_exar_XR17C158 }, 4918 /* 4919 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs 4920 */ 4921 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4922 PCI_ANY_ID, PCI_ANY_ID, 4923 0, 4924 0, pbn_exar_XR17V352 }, 4925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4926 PCI_ANY_ID, PCI_ANY_ID, 4927 0, 4928 0, pbn_exar_XR17V354 }, 4929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4930 PCI_ANY_ID, PCI_ANY_ID, 4931 0, 4932 0, pbn_exar_XR17V358 }, 4933 4934 /* 4935 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4936 */ 4937 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b0_1_115200 }, 4940 /* 4941 * ITE 4942 */ 4943 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4944 PCI_ANY_ID, PCI_ANY_ID, 4945 0, 0, 4946 pbn_b1_bt_1_115200 }, 4947 4948 /* 4949 * IntaShield IS-200 4950 */ 4951 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4953 pbn_b2_2_115200 }, 4954 /* 4955 * IntaShield IS-400 4956 */ 4957 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4959 pbn_b2_4_115200 }, 4960 /* 4961 * Perle PCI-RAS cards 4962 */ 4963 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4964 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4965 0, 0, pbn_b2_4_921600 }, 4966 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4967 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4968 0, 0, pbn_b2_8_921600 }, 4969 4970 /* 4971 * Mainpine series cards: Fairly standard layout but fools 4972 * parts of the autodetect in some cases and uses otherwise 4973 * unmatched communications subclasses in the PCI Express case 4974 */ 4975 4976 { /* RockForceDUO */ 4977 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4978 PCI_VENDOR_ID_MAINPINE, 0x0200, 4979 0, 0, pbn_b0_2_115200 }, 4980 { /* RockForceQUATRO */ 4981 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4982 PCI_VENDOR_ID_MAINPINE, 0x0300, 4983 0, 0, pbn_b0_4_115200 }, 4984 { /* RockForceDUO+ */ 4985 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4986 PCI_VENDOR_ID_MAINPINE, 0x0400, 4987 0, 0, pbn_b0_2_115200 }, 4988 { /* RockForceQUATRO+ */ 4989 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4990 PCI_VENDOR_ID_MAINPINE, 0x0500, 4991 0, 0, pbn_b0_4_115200 }, 4992 { /* RockForce+ */ 4993 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4994 PCI_VENDOR_ID_MAINPINE, 0x0600, 4995 0, 0, pbn_b0_2_115200 }, 4996 { /* RockForce+ */ 4997 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4998 PCI_VENDOR_ID_MAINPINE, 0x0700, 4999 0, 0, pbn_b0_4_115200 }, 5000 { /* RockForceOCTO+ */ 5001 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5002 PCI_VENDOR_ID_MAINPINE, 0x0800, 5003 0, 0, pbn_b0_8_115200 }, 5004 { /* RockForceDUO+ */ 5005 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5006 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5007 0, 0, pbn_b0_2_115200 }, 5008 { /* RockForceQUARTRO+ */ 5009 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5010 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5011 0, 0, pbn_b0_4_115200 }, 5012 { /* RockForceOCTO+ */ 5013 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5014 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5015 0, 0, pbn_b0_8_115200 }, 5016 { /* RockForceD1 */ 5017 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5018 PCI_VENDOR_ID_MAINPINE, 0x2000, 5019 0, 0, pbn_b0_1_115200 }, 5020 { /* RockForceF1 */ 5021 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5022 PCI_VENDOR_ID_MAINPINE, 0x2100, 5023 0, 0, pbn_b0_1_115200 }, 5024 { /* RockForceD2 */ 5025 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5026 PCI_VENDOR_ID_MAINPINE, 0x2200, 5027 0, 0, pbn_b0_2_115200 }, 5028 { /* RockForceF2 */ 5029 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5030 PCI_VENDOR_ID_MAINPINE, 0x2300, 5031 0, 0, pbn_b0_2_115200 }, 5032 { /* RockForceD4 */ 5033 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5034 PCI_VENDOR_ID_MAINPINE, 0x2400, 5035 0, 0, pbn_b0_4_115200 }, 5036 { /* RockForceF4 */ 5037 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5038 PCI_VENDOR_ID_MAINPINE, 0x2500, 5039 0, 0, pbn_b0_4_115200 }, 5040 { /* RockForceD8 */ 5041 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5042 PCI_VENDOR_ID_MAINPINE, 0x2600, 5043 0, 0, pbn_b0_8_115200 }, 5044 { /* RockForceF8 */ 5045 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5046 PCI_VENDOR_ID_MAINPINE, 0x2700, 5047 0, 0, pbn_b0_8_115200 }, 5048 { /* IQ Express D1 */ 5049 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5050 PCI_VENDOR_ID_MAINPINE, 0x3000, 5051 0, 0, pbn_b0_1_115200 }, 5052 { /* IQ Express F1 */ 5053 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5054 PCI_VENDOR_ID_MAINPINE, 0x3100, 5055 0, 0, pbn_b0_1_115200 }, 5056 { /* IQ Express D2 */ 5057 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5058 PCI_VENDOR_ID_MAINPINE, 0x3200, 5059 0, 0, pbn_b0_2_115200 }, 5060 { /* IQ Express F2 */ 5061 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5062 PCI_VENDOR_ID_MAINPINE, 0x3300, 5063 0, 0, pbn_b0_2_115200 }, 5064 { /* IQ Express D4 */ 5065 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5066 PCI_VENDOR_ID_MAINPINE, 0x3400, 5067 0, 0, pbn_b0_4_115200 }, 5068 { /* IQ Express F4 */ 5069 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5070 PCI_VENDOR_ID_MAINPINE, 0x3500, 5071 0, 0, pbn_b0_4_115200 }, 5072 { /* IQ Express D8 */ 5073 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5074 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5075 0, 0, pbn_b0_8_115200 }, 5076 { /* IQ Express F8 */ 5077 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5078 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5079 0, 0, pbn_b0_8_115200 }, 5080 5081 5082 /* 5083 * PA Semi PA6T-1682M on-chip UART 5084 */ 5085 { PCI_VENDOR_ID_PASEMI, 0xa004, 5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5087 pbn_pasemi_1682M }, 5088 5089 /* 5090 * National Instruments 5091 */ 5092 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5094 pbn_b1_16_115200 }, 5095 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5097 pbn_b1_8_115200 }, 5098 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5100 pbn_b1_bt_4_115200 }, 5101 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5103 pbn_b1_bt_2_115200 }, 5104 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5106 pbn_b1_bt_4_115200 }, 5107 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5109 pbn_b1_bt_2_115200 }, 5110 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5112 pbn_b1_16_115200 }, 5113 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5115 pbn_b1_8_115200 }, 5116 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5118 pbn_b1_bt_4_115200 }, 5119 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5121 pbn_b1_bt_2_115200 }, 5122 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5124 pbn_b1_bt_4_115200 }, 5125 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5127 pbn_b1_bt_2_115200 }, 5128 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5130 pbn_ni8430_2 }, 5131 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5133 pbn_ni8430_2 }, 5134 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5136 pbn_ni8430_4 }, 5137 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5139 pbn_ni8430_4 }, 5140 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5142 pbn_ni8430_8 }, 5143 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5145 pbn_ni8430_8 }, 5146 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5148 pbn_ni8430_16 }, 5149 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5151 pbn_ni8430_16 }, 5152 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5154 pbn_ni8430_2 }, 5155 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5157 pbn_ni8430_2 }, 5158 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5159 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5160 pbn_ni8430_4 }, 5161 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5163 pbn_ni8430_4 }, 5164 5165 /* 5166 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5167 */ 5168 { PCI_VENDOR_ID_ADDIDATA, 5169 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5170 PCI_ANY_ID, 5171 PCI_ANY_ID, 5172 0, 5173 0, 5174 pbn_b0_4_115200 }, 5175 5176 { PCI_VENDOR_ID_ADDIDATA, 5177 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5178 PCI_ANY_ID, 5179 PCI_ANY_ID, 5180 0, 5181 0, 5182 pbn_b0_2_115200 }, 5183 5184 { PCI_VENDOR_ID_ADDIDATA, 5185 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5186 PCI_ANY_ID, 5187 PCI_ANY_ID, 5188 0, 5189 0, 5190 pbn_b0_1_115200 }, 5191 5192 { PCI_VENDOR_ID_AMCC, 5193 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5194 PCI_ANY_ID, 5195 PCI_ANY_ID, 5196 0, 5197 0, 5198 pbn_b1_8_115200 }, 5199 5200 { PCI_VENDOR_ID_ADDIDATA, 5201 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5202 PCI_ANY_ID, 5203 PCI_ANY_ID, 5204 0, 5205 0, 5206 pbn_b0_4_115200 }, 5207 5208 { PCI_VENDOR_ID_ADDIDATA, 5209 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5210 PCI_ANY_ID, 5211 PCI_ANY_ID, 5212 0, 5213 0, 5214 pbn_b0_2_115200 }, 5215 5216 { PCI_VENDOR_ID_ADDIDATA, 5217 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5218 PCI_ANY_ID, 5219 PCI_ANY_ID, 5220 0, 5221 0, 5222 pbn_b0_1_115200 }, 5223 5224 { PCI_VENDOR_ID_ADDIDATA, 5225 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5226 PCI_ANY_ID, 5227 PCI_ANY_ID, 5228 0, 5229 0, 5230 pbn_b0_4_115200 }, 5231 5232 { PCI_VENDOR_ID_ADDIDATA, 5233 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5234 PCI_ANY_ID, 5235 PCI_ANY_ID, 5236 0, 5237 0, 5238 pbn_b0_2_115200 }, 5239 5240 { PCI_VENDOR_ID_ADDIDATA, 5241 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5242 PCI_ANY_ID, 5243 PCI_ANY_ID, 5244 0, 5245 0, 5246 pbn_b0_1_115200 }, 5247 5248 { PCI_VENDOR_ID_ADDIDATA, 5249 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5250 PCI_ANY_ID, 5251 PCI_ANY_ID, 5252 0, 5253 0, 5254 pbn_b0_8_115200 }, 5255 5256 { PCI_VENDOR_ID_ADDIDATA, 5257 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5258 PCI_ANY_ID, 5259 PCI_ANY_ID, 5260 0, 5261 0, 5262 pbn_ADDIDATA_PCIe_4_3906250 }, 5263 5264 { PCI_VENDOR_ID_ADDIDATA, 5265 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5266 PCI_ANY_ID, 5267 PCI_ANY_ID, 5268 0, 5269 0, 5270 pbn_ADDIDATA_PCIe_2_3906250 }, 5271 5272 { PCI_VENDOR_ID_ADDIDATA, 5273 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5274 PCI_ANY_ID, 5275 PCI_ANY_ID, 5276 0, 5277 0, 5278 pbn_ADDIDATA_PCIe_1_3906250 }, 5279 5280 { PCI_VENDOR_ID_ADDIDATA, 5281 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5282 PCI_ANY_ID, 5283 PCI_ANY_ID, 5284 0, 5285 0, 5286 pbn_ADDIDATA_PCIe_8_3906250 }, 5287 5288 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5289 PCI_VENDOR_ID_IBM, 0x0299, 5290 0, 0, pbn_b0_bt_2_115200 }, 5291 5292 /* 5293 * other NetMos 9835 devices are most likely handled by the 5294 * parport_serial driver, check drivers/parport/parport_serial.c 5295 * before adding them here. 5296 */ 5297 5298 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5299 0xA000, 0x1000, 5300 0, 0, pbn_b0_1_115200 }, 5301 5302 /* the 9901 is a rebranded 9912 */ 5303 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5304 0xA000, 0x1000, 5305 0, 0, pbn_b0_1_115200 }, 5306 5307 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5308 0xA000, 0x1000, 5309 0, 0, pbn_b0_1_115200 }, 5310 5311 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5312 0xA000, 0x1000, 5313 0, 0, pbn_b0_1_115200 }, 5314 5315 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5316 0xA000, 0x1000, 5317 0, 0, pbn_b0_1_115200 }, 5318 5319 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5320 0xA000, 0x3002, 5321 0, 0, pbn_NETMOS9900_2s_115200 }, 5322 5323 /* 5324 * Best Connectivity and Rosewill PCI Multi I/O cards 5325 */ 5326 5327 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5328 0xA000, 0x1000, 5329 0, 0, pbn_b0_1_115200 }, 5330 5331 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5332 0xA000, 0x3002, 5333 0, 0, pbn_b0_bt_2_115200 }, 5334 5335 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5336 0xA000, 0x3004, 5337 0, 0, pbn_b0_bt_4_115200 }, 5338 /* Intel CE4100 */ 5339 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5341 pbn_ce4100_1_115200 }, 5342 /* Intel BayTrail */ 5343 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5344 PCI_ANY_ID, PCI_ANY_ID, 5345 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5346 pbn_byt }, 5347 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5348 PCI_ANY_ID, PCI_ANY_ID, 5349 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5350 pbn_byt }, 5351 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, 5352 PCI_ANY_ID, PCI_ANY_ID, 5353 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5354 pbn_byt }, 5355 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, 5356 PCI_ANY_ID, PCI_ANY_ID, 5357 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5358 pbn_byt }, 5359 5360 /* 5361 * Intel Quark x1000 5362 */ 5363 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, 5364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5365 pbn_qrk }, 5366 /* 5367 * Cronyx Omega PCI 5368 */ 5369 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5371 pbn_omegapci }, 5372 5373 /* 5374 * Broadcom TruManage 5375 */ 5376 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5378 pbn_brcm_trumanage }, 5379 5380 /* 5381 * AgeStar as-prs2-009 5382 */ 5383 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5384 PCI_ANY_ID, PCI_ANY_ID, 5385 0, 0, pbn_b0_bt_2_115200 }, 5386 5387 /* 5388 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5389 * so not listed here. 5390 */ 5391 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5392 PCI_ANY_ID, PCI_ANY_ID, 5393 0, 0, pbn_b0_bt_4_115200 }, 5394 5395 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5396 PCI_ANY_ID, PCI_ANY_ID, 5397 0, 0, pbn_b0_bt_2_115200 }, 5398 5399 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S, 5400 PCI_ANY_ID, PCI_ANY_ID, 5401 0, 0, pbn_b0_bt_2_115200 }, 5402 5403 /* 5404 * Commtech, Inc. Fastcom adapters 5405 */ 5406 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5407 PCI_ANY_ID, PCI_ANY_ID, 5408 0, 5409 0, pbn_b0_2_1152000_200 }, 5410 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5411 PCI_ANY_ID, PCI_ANY_ID, 5412 0, 5413 0, pbn_b0_4_1152000_200 }, 5414 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5415 PCI_ANY_ID, PCI_ANY_ID, 5416 0, 5417 0, pbn_b0_4_1152000_200 }, 5418 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5419 PCI_ANY_ID, PCI_ANY_ID, 5420 0, 5421 0, pbn_b0_8_1152000_200 }, 5422 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5423 PCI_ANY_ID, PCI_ANY_ID, 5424 0, 5425 0, pbn_exar_XR17V352 }, 5426 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5427 PCI_ANY_ID, PCI_ANY_ID, 5428 0, 5429 0, pbn_exar_XR17V354 }, 5430 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5431 PCI_ANY_ID, PCI_ANY_ID, 5432 0, 5433 0, pbn_exar_XR17V358 }, 5434 5435 /* Fintek PCI serial cards */ 5436 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5437 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5438 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5439 5440 /* 5441 * These entries match devices with class COMMUNICATION_SERIAL, 5442 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5443 */ 5444 { PCI_ANY_ID, PCI_ANY_ID, 5445 PCI_ANY_ID, PCI_ANY_ID, 5446 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5447 0xffff00, pbn_default }, 5448 { PCI_ANY_ID, PCI_ANY_ID, 5449 PCI_ANY_ID, PCI_ANY_ID, 5450 PCI_CLASS_COMMUNICATION_MODEM << 8, 5451 0xffff00, pbn_default }, 5452 { PCI_ANY_ID, PCI_ANY_ID, 5453 PCI_ANY_ID, PCI_ANY_ID, 5454 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5455 0xffff00, pbn_default }, 5456 { 0, } 5457 }; 5458 5459 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5460 pci_channel_state_t state) 5461 { 5462 struct serial_private *priv = pci_get_drvdata(dev); 5463 5464 if (state == pci_channel_io_perm_failure) 5465 return PCI_ERS_RESULT_DISCONNECT; 5466 5467 if (priv) 5468 pciserial_suspend_ports(priv); 5469 5470 pci_disable_device(dev); 5471 5472 return PCI_ERS_RESULT_NEED_RESET; 5473 } 5474 5475 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5476 { 5477 int rc; 5478 5479 rc = pci_enable_device(dev); 5480 5481 if (rc) 5482 return PCI_ERS_RESULT_DISCONNECT; 5483 5484 pci_restore_state(dev); 5485 pci_save_state(dev); 5486 5487 return PCI_ERS_RESULT_RECOVERED; 5488 } 5489 5490 static void serial8250_io_resume(struct pci_dev *dev) 5491 { 5492 struct serial_private *priv = pci_get_drvdata(dev); 5493 5494 if (priv) 5495 pciserial_resume_ports(priv); 5496 } 5497 5498 static const struct pci_error_handlers serial8250_err_handler = { 5499 .error_detected = serial8250_io_error_detected, 5500 .slot_reset = serial8250_io_slot_reset, 5501 .resume = serial8250_io_resume, 5502 }; 5503 5504 static struct pci_driver serial_pci_driver = { 5505 .name = "serial", 5506 .probe = pciserial_init_one, 5507 .remove = pciserial_remove_one, 5508 #ifdef CONFIG_PM 5509 .suspend = pciserial_suspend_one, 5510 .resume = pciserial_resume_one, 5511 #endif 5512 .id_table = serial_pci_tbl, 5513 .err_handler = &serial8250_err_handler, 5514 }; 5515 5516 module_pci_driver(serial_pci_driver); 5517 5518 MODULE_LICENSE("GPL"); 5519 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5520 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5521