1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 #include "8250_pcilib.h" 28 29 /* 30 * init function returns: 31 * > 0 - number of ports 32 * = 0 - use board->num_ports 33 * < 0 - error 34 */ 35 struct pci_serial_quirk { 36 u32 vendor; 37 u32 device; 38 u32 subvendor; 39 u32 subdevice; 40 int (*probe)(struct pci_dev *dev); 41 int (*init)(struct pci_dev *dev); 42 int (*setup)(struct serial_private *, 43 const struct pciserial_board *, 44 struct uart_8250_port *, int); 45 void (*exit)(struct pci_dev *dev); 46 }; 47 48 struct f815xxa_data { 49 spinlock_t lock; 50 int idx; 51 }; 52 53 struct serial_private { 54 struct pci_dev *dev; 55 unsigned int nr; 56 struct pci_serial_quirk *quirk; 57 const struct pciserial_board *board; 58 int line[]; 59 }; 60 61 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 62 63 static const struct pci_device_id pci_use_msi[] = { 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 69 0xA000, 0x1000) }, 70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 71 PCI_ANY_ID, PCI_ANY_ID) }, 72 { } 73 }; 74 75 static int pci_default_setup(struct serial_private*, 76 const struct pciserial_board*, struct uart_8250_port *, int); 77 78 static void moan_device(const char *str, struct pci_dev *dev) 79 { 80 pci_err(dev, "%s\n" 81 "Please send the output of lspci -vv, this\n" 82 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 83 "manufacturer and name of serial board or\n" 84 "modem board to <linux-serial@vger.kernel.org>.\n", 85 str, dev->vendor, dev->device, 86 dev->subsystem_vendor, dev->subsystem_device); 87 } 88 89 static int 90 setup_port(struct serial_private *priv, struct uart_8250_port *port, 91 u8 bar, unsigned int offset, int regshift) 92 { 93 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 94 } 95 96 /* 97 * ADDI-DATA GmbH communication cards <info@addi-data.com> 98 */ 99 static int addidata_apci7800_setup(struct serial_private *priv, 100 const struct pciserial_board *board, 101 struct uart_8250_port *port, int idx) 102 { 103 unsigned int bar = 0, offset = board->first_offset; 104 bar = FL_GET_BASE(board->flags); 105 106 if (idx < 2) { 107 offset += idx * board->uart_offset; 108 } else if ((idx >= 2) && (idx < 4)) { 109 bar += 1; 110 offset += ((idx - 2) * board->uart_offset); 111 } else if ((idx >= 4) && (idx < 6)) { 112 bar += 2; 113 offset += ((idx - 4) * board->uart_offset); 114 } else if (idx >= 6) { 115 bar += 3; 116 offset += ((idx - 6) * board->uart_offset); 117 } 118 119 return setup_port(priv, port, bar, offset, board->reg_shift); 120 } 121 122 /* 123 * AFAVLAB uses a different mixture of BARs and offsets 124 * Not that ugly ;) -- HW 125 */ 126 static int 127 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 128 struct uart_8250_port *port, int idx) 129 { 130 unsigned int bar, offset = board->first_offset; 131 132 bar = FL_GET_BASE(board->flags); 133 if (idx < 4) 134 bar += idx; 135 else { 136 bar = 4; 137 offset += (idx - 4) * board->uart_offset; 138 } 139 140 return setup_port(priv, port, bar, offset, board->reg_shift); 141 } 142 143 /* 144 * HP's Remote Management Console. The Diva chip came in several 145 * different versions. N-class, L2000 and A500 have two Diva chips, each 146 * with 3 UARTs (the third UART on the second chip is unused). Superdome 147 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 148 * one Diva chip, but it has been expanded to 5 UARTs. 149 */ 150 static int pci_hp_diva_init(struct pci_dev *dev) 151 { 152 int rc = 0; 153 154 switch (dev->subsystem_device) { 155 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 156 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 157 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 158 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 159 rc = 3; 160 break; 161 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 162 rc = 2; 163 break; 164 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 165 rc = 4; 166 break; 167 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 168 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 169 rc = 1; 170 break; 171 } 172 173 return rc; 174 } 175 176 /* 177 * HP's Diva chip puts the 4th/5th serial port further out, and 178 * some serial ports are supposed to be hidden on certain models. 179 */ 180 static int 181 pci_hp_diva_setup(struct serial_private *priv, 182 const struct pciserial_board *board, 183 struct uart_8250_port *port, int idx) 184 { 185 unsigned int offset = board->first_offset; 186 unsigned int bar = FL_GET_BASE(board->flags); 187 188 switch (priv->dev->subsystem_device) { 189 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 190 if (idx == 3) 191 idx++; 192 break; 193 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 194 if (idx > 0) 195 idx++; 196 if (idx > 2) 197 idx++; 198 break; 199 } 200 if (idx > 2) 201 offset = 0x18; 202 203 offset += idx * board->uart_offset; 204 205 return setup_port(priv, port, bar, offset, board->reg_shift); 206 } 207 208 /* 209 * Added for EKF Intel i960 serial boards 210 */ 211 static int pci_inteli960ni_init(struct pci_dev *dev) 212 { 213 u32 oldval; 214 215 if (!(dev->subsystem_device & 0x1000)) 216 return -ENODEV; 217 218 /* is firmware started? */ 219 pci_read_config_dword(dev, 0x44, &oldval); 220 if (oldval == 0x00001000L) { /* RESET value */ 221 pci_dbg(dev, "Local i960 firmware missing\n"); 222 return -ENODEV; 223 } 224 return 0; 225 } 226 227 /* 228 * Some PCI serial cards using the PLX 9050 PCI interface chip require 229 * that the card interrupt be explicitly enabled or disabled. This 230 * seems to be mainly needed on card using the PLX which also use I/O 231 * mapped memory. 232 */ 233 static int pci_plx9050_init(struct pci_dev *dev) 234 { 235 u8 irq_config; 236 void __iomem *p; 237 238 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 239 moan_device("no memory in bar 0", dev); 240 return 0; 241 } 242 243 irq_config = 0x41; 244 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 245 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 246 irq_config = 0x43; 247 248 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 249 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 250 /* 251 * As the megawolf cards have the int pins active 252 * high, and have 2 UART chips, both ints must be 253 * enabled on the 9050. Also, the UARTS are set in 254 * 16450 mode by default, so we have to enable the 255 * 16C950 'enhanced' mode so that we can use the 256 * deep FIFOs 257 */ 258 irq_config = 0x5b; 259 /* 260 * enable/disable interrupts 261 */ 262 p = ioremap(pci_resource_start(dev, 0), 0x80); 263 if (p == NULL) 264 return -ENOMEM; 265 writel(irq_config, p + 0x4c); 266 267 /* 268 * Read the register back to ensure that it took effect. 269 */ 270 readl(p + 0x4c); 271 iounmap(p); 272 273 return 0; 274 } 275 276 static void pci_plx9050_exit(struct pci_dev *dev) 277 { 278 u8 __iomem *p; 279 280 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 281 return; 282 283 /* 284 * disable interrupts 285 */ 286 p = ioremap(pci_resource_start(dev, 0), 0x80); 287 if (p != NULL) { 288 writel(0, p + 0x4c); 289 290 /* 291 * Read the register back to ensure that it took effect. 292 */ 293 readl(p + 0x4c); 294 iounmap(p); 295 } 296 } 297 298 #define NI8420_INT_ENABLE_REG 0x38 299 #define NI8420_INT_ENABLE_BIT 0x2000 300 301 static void pci_ni8420_exit(struct pci_dev *dev) 302 { 303 void __iomem *p; 304 unsigned int bar = 0; 305 306 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 307 moan_device("no memory in bar", dev); 308 return; 309 } 310 311 p = pci_ioremap_bar(dev, bar); 312 if (p == NULL) 313 return; 314 315 /* Disable the CPU Interrupt */ 316 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 317 p + NI8420_INT_ENABLE_REG); 318 iounmap(p); 319 } 320 321 322 /* MITE registers */ 323 #define MITE_IOWBSR1 0xc4 324 #define MITE_IOWCR1 0xf4 325 #define MITE_LCIMR1 0x08 326 #define MITE_LCIMR2 0x10 327 328 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 329 330 static void pci_ni8430_exit(struct pci_dev *dev) 331 { 332 void __iomem *p; 333 unsigned int bar = 0; 334 335 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 336 moan_device("no memory in bar", dev); 337 return; 338 } 339 340 p = pci_ioremap_bar(dev, bar); 341 if (p == NULL) 342 return; 343 344 /* Disable the CPU Interrupt */ 345 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 346 iounmap(p); 347 } 348 349 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 350 static int 351 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 352 struct uart_8250_port *port, int idx) 353 { 354 unsigned int bar, offset = board->first_offset; 355 356 bar = 0; 357 358 if (idx < 4) { 359 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 360 offset += idx * board->uart_offset; 361 } else if (idx < 8) { 362 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 363 offset += idx * board->uart_offset + 0xC00; 364 } else /* we have only 8 ports on PMC-OCTALPRO */ 365 return 1; 366 367 return setup_port(priv, port, bar, offset, board->reg_shift); 368 } 369 370 /* 371 * This does initialization for PMC OCTALPRO cards: 372 * maps the device memory, resets the UARTs (needed, bc 373 * if the module is removed and inserted again, the card 374 * is in the sleep mode) and enables global interrupt. 375 */ 376 377 /* global control register offset for SBS PMC-OctalPro */ 378 #define OCT_REG_CR_OFF 0x500 379 380 static int sbs_init(struct pci_dev *dev) 381 { 382 u8 __iomem *p; 383 384 p = pci_ioremap_bar(dev, 0); 385 386 if (p == NULL) 387 return -ENOMEM; 388 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 389 writeb(0x10, p + OCT_REG_CR_OFF); 390 udelay(50); 391 writeb(0x0, p + OCT_REG_CR_OFF); 392 393 /* Set bit-2 (INTENABLE) of Control Register */ 394 writeb(0x4, p + OCT_REG_CR_OFF); 395 iounmap(p); 396 397 return 0; 398 } 399 400 /* 401 * Disables the global interrupt of PMC-OctalPro 402 */ 403 404 static void sbs_exit(struct pci_dev *dev) 405 { 406 u8 __iomem *p; 407 408 p = pci_ioremap_bar(dev, 0); 409 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 410 if (p != NULL) 411 writeb(0, p + OCT_REG_CR_OFF); 412 iounmap(p); 413 } 414 415 /* 416 * SIIG serial cards have an PCI interface chip which also controls 417 * the UART clocking frequency. Each UART can be clocked independently 418 * (except cards equipped with 4 UARTs) and initial clocking settings 419 * are stored in the EEPROM chip. It can cause problems because this 420 * version of serial driver doesn't support differently clocked UART's 421 * on single PCI card. To prevent this, initialization functions set 422 * high frequency clocking for all UART's on given card. It is safe (I 423 * hope) because it doesn't touch EEPROM settings to prevent conflicts 424 * with other OSes (like M$ DOS). 425 * 426 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 427 * 428 * There is two family of SIIG serial cards with different PCI 429 * interface chip and different configuration methods: 430 * - 10x cards have control registers in IO and/or memory space; 431 * - 20x cards have control registers in standard PCI configuration space. 432 * 433 * Note: all 10x cards have PCI device ids 0x10.. 434 * all 20x cards have PCI device ids 0x20.. 435 * 436 * There are also Quartet Serial cards which use Oxford Semiconductor 437 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 438 * 439 * Note: some SIIG cards are probed by the parport_serial object. 440 */ 441 442 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 443 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 444 445 static int pci_siig10x_init(struct pci_dev *dev) 446 { 447 u16 data; 448 void __iomem *p; 449 450 switch (dev->device & 0xfff8) { 451 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 452 data = 0xffdf; 453 break; 454 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 455 data = 0xf7ff; 456 break; 457 default: /* 1S1P, 4S */ 458 data = 0xfffb; 459 break; 460 } 461 462 p = ioremap(pci_resource_start(dev, 0), 0x80); 463 if (p == NULL) 464 return -ENOMEM; 465 466 writew(readw(p + 0x28) & data, p + 0x28); 467 readw(p + 0x28); 468 iounmap(p); 469 return 0; 470 } 471 472 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 473 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 474 475 static int pci_siig20x_init(struct pci_dev *dev) 476 { 477 u8 data; 478 479 /* Change clock frequency for the first UART. */ 480 pci_read_config_byte(dev, 0x6f, &data); 481 pci_write_config_byte(dev, 0x6f, data & 0xef); 482 483 /* If this card has 2 UART, we have to do the same with second UART. */ 484 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 485 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 486 pci_read_config_byte(dev, 0x73, &data); 487 pci_write_config_byte(dev, 0x73, data & 0xef); 488 } 489 return 0; 490 } 491 492 static int pci_siig_init(struct pci_dev *dev) 493 { 494 unsigned int type = dev->device & 0xff00; 495 496 if (type == 0x1000) 497 return pci_siig10x_init(dev); 498 if (type == 0x2000) 499 return pci_siig20x_init(dev); 500 501 moan_device("Unknown SIIG card", dev); 502 return -ENODEV; 503 } 504 505 static int pci_siig_setup(struct serial_private *priv, 506 const struct pciserial_board *board, 507 struct uart_8250_port *port, int idx) 508 { 509 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 510 511 if (idx > 3) { 512 bar = 4; 513 offset = (idx - 4) * 8; 514 } 515 516 return setup_port(priv, port, bar, offset, 0); 517 } 518 519 /* 520 * Timedia has an explosion of boards, and to avoid the PCI table from 521 * growing *huge*, we use this function to collapse some 70 entries 522 * in the PCI table into one, for sanity's and compactness's sake. 523 */ 524 static const unsigned short timedia_single_port[] = { 525 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 526 }; 527 528 static const unsigned short timedia_dual_port[] = { 529 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 530 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 531 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 532 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 533 0xD079, 0 534 }; 535 536 static const unsigned short timedia_quad_port[] = { 537 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 538 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 539 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 540 0xB157, 0 541 }; 542 543 static const unsigned short timedia_eight_port[] = { 544 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 545 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 546 }; 547 548 static const struct timedia_struct { 549 int num; 550 const unsigned short *ids; 551 } timedia_data[] = { 552 { 1, timedia_single_port }, 553 { 2, timedia_dual_port }, 554 { 4, timedia_quad_port }, 555 { 8, timedia_eight_port } 556 }; 557 558 /* 559 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 560 * listing them individually, this driver merely grabs them all with 561 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 562 * and should be left free to be claimed by parport_serial instead. 563 */ 564 static int pci_timedia_probe(struct pci_dev *dev) 565 { 566 /* 567 * Check the third digit of the subdevice ID 568 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 569 */ 570 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 571 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 572 dev->subsystem_device); 573 return -ENODEV; 574 } 575 576 return 0; 577 } 578 579 static int pci_timedia_init(struct pci_dev *dev) 580 { 581 const unsigned short *ids; 582 int i, j; 583 584 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 585 ids = timedia_data[i].ids; 586 for (j = 0; ids[j]; j++) 587 if (dev->subsystem_device == ids[j]) 588 return timedia_data[i].num; 589 } 590 return 0; 591 } 592 593 /* 594 * Timedia/SUNIX uses a mixture of BARs and offsets 595 * Ugh, this is ugly as all hell --- TYT 596 */ 597 static int 598 pci_timedia_setup(struct serial_private *priv, 599 const struct pciserial_board *board, 600 struct uart_8250_port *port, int idx) 601 { 602 unsigned int bar = 0, offset = board->first_offset; 603 604 switch (idx) { 605 case 0: 606 bar = 0; 607 break; 608 case 1: 609 offset = board->uart_offset; 610 bar = 0; 611 break; 612 case 2: 613 bar = 1; 614 break; 615 case 3: 616 offset = board->uart_offset; 617 fallthrough; 618 case 4: /* BAR 2 */ 619 case 5: /* BAR 3 */ 620 case 6: /* BAR 4 */ 621 case 7: /* BAR 5 */ 622 bar = idx - 2; 623 } 624 625 return setup_port(priv, port, bar, offset, board->reg_shift); 626 } 627 628 /* 629 * Some Titan cards are also a little weird 630 */ 631 static int 632 titan_400l_800l_setup(struct serial_private *priv, 633 const struct pciserial_board *board, 634 struct uart_8250_port *port, int idx) 635 { 636 unsigned int bar, offset = board->first_offset; 637 638 switch (idx) { 639 case 0: 640 bar = 1; 641 break; 642 case 1: 643 bar = 2; 644 break; 645 default: 646 bar = 4; 647 offset = (idx - 2) * board->uart_offset; 648 } 649 650 return setup_port(priv, port, bar, offset, board->reg_shift); 651 } 652 653 static int pci_xircom_init(struct pci_dev *dev) 654 { 655 msleep(100); 656 return 0; 657 } 658 659 static int pci_ni8420_init(struct pci_dev *dev) 660 { 661 void __iomem *p; 662 unsigned int bar = 0; 663 664 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 665 moan_device("no memory in bar", dev); 666 return 0; 667 } 668 669 p = pci_ioremap_bar(dev, bar); 670 if (p == NULL) 671 return -ENOMEM; 672 673 /* Enable CPU Interrupt */ 674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 675 p + NI8420_INT_ENABLE_REG); 676 677 iounmap(p); 678 return 0; 679 } 680 681 #define MITE_IOWBSR1_WSIZE 0xa 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800 683 #define MITE_IOWBSR1_WENAB (1 << 7) 684 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 687 688 static int pci_ni8430_init(struct pci_dev *dev) 689 { 690 void __iomem *p; 691 struct pci_bus_region region; 692 u32 device_window; 693 unsigned int bar = 0; 694 695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 696 moan_device("no memory in bar", dev); 697 return 0; 698 } 699 700 p = pci_ioremap_bar(dev, bar); 701 if (p == NULL) 702 return -ENOMEM; 703 704 /* 705 * Set device window address and size in BAR0, while acknowledging that 706 * the resource structure may contain a translated address that differs 707 * from the address the device responds to. 708 */ 709 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 710 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 711 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 712 writel(device_window, p + MITE_IOWBSR1); 713 714 /* Set window access to go to RAMSEL IO address space */ 715 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 716 p + MITE_IOWCR1); 717 718 /* Enable IO Bus Interrupt 0 */ 719 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 720 721 /* Enable CPU Interrupt */ 722 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 723 724 iounmap(p); 725 return 0; 726 } 727 728 /* UART Port Control Register */ 729 #define NI8430_PORTCON 0x0f 730 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 731 732 static int 733 pci_ni8430_setup(struct serial_private *priv, 734 const struct pciserial_board *board, 735 struct uart_8250_port *port, int idx) 736 { 737 struct pci_dev *dev = priv->dev; 738 void __iomem *p; 739 unsigned int bar, offset = board->first_offset; 740 741 if (idx >= board->num_ports) 742 return 1; 743 744 bar = FL_GET_BASE(board->flags); 745 offset += idx * board->uart_offset; 746 747 p = pci_ioremap_bar(dev, bar); 748 if (!p) 749 return -ENOMEM; 750 751 /* enable the transceiver */ 752 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 753 p + offset + NI8430_PORTCON); 754 755 iounmap(p); 756 757 return setup_port(priv, port, bar, offset, board->reg_shift); 758 } 759 760 static int pci_netmos_9900_setup(struct serial_private *priv, 761 const struct pciserial_board *board, 762 struct uart_8250_port *port, int idx) 763 { 764 unsigned int bar; 765 766 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 767 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 768 /* netmos apparently orders BARs by datasheet layout, so serial 769 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 770 */ 771 bar = 3 * idx; 772 773 return setup_port(priv, port, bar, 0, board->reg_shift); 774 } 775 776 return pci_default_setup(priv, board, port, idx); 777 } 778 779 /* the 99xx series comes with a range of device IDs and a variety 780 * of capabilities: 781 * 782 * 9900 has varying capabilities and can cascade to sub-controllers 783 * (cascading should be purely internal) 784 * 9904 is hardwired with 4 serial ports 785 * 9912 and 9922 are hardwired with 2 serial ports 786 */ 787 static int pci_netmos_9900_numports(struct pci_dev *dev) 788 { 789 unsigned int c = dev->class; 790 unsigned int pi; 791 unsigned short sub_serports; 792 793 pi = c & 0xff; 794 795 if (pi == 2) 796 return 1; 797 798 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 799 /* two possibilities: 0x30ps encodes number of parallel and 800 * serial ports, or 0x1000 indicates *something*. This is not 801 * immediately obvious, since the 2s1p+4s configuration seems 802 * to offer all functionality on functions 0..2, while still 803 * advertising the same function 3 as the 4s+2s1p config. 804 */ 805 sub_serports = dev->subsystem_device & 0xf; 806 if (sub_serports > 0) 807 return sub_serports; 808 809 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 810 return 0; 811 } 812 813 moan_device("unknown NetMos/Mostech program interface", dev); 814 return 0; 815 } 816 817 static int pci_netmos_init(struct pci_dev *dev) 818 { 819 /* subdevice 0x00PS means <P> parallel, <S> serial */ 820 unsigned int num_serial = dev->subsystem_device & 0xf; 821 822 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 823 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 824 return 0; 825 826 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 827 dev->subsystem_device == 0x0299) 828 return 0; 829 830 switch (dev->device) { /* FALLTHROUGH on all */ 831 case PCI_DEVICE_ID_NETMOS_9904: 832 case PCI_DEVICE_ID_NETMOS_9912: 833 case PCI_DEVICE_ID_NETMOS_9922: 834 case PCI_DEVICE_ID_NETMOS_9900: 835 num_serial = pci_netmos_9900_numports(dev); 836 break; 837 838 default: 839 break; 840 } 841 842 if (num_serial == 0) { 843 moan_device("unknown NetMos/Mostech device", dev); 844 return -ENODEV; 845 } 846 847 return num_serial; 848 } 849 850 /* 851 * These chips are available with optionally one parallel port and up to 852 * two serial ports. Unfortunately they all have the same product id. 853 * 854 * Basic configuration is done over a region of 32 I/O ports. The base 855 * ioport is called INTA or INTC, depending on docs/other drivers. 856 * 857 * The region of the 32 I/O ports is configured in POSIO0R... 858 */ 859 860 /* registers */ 861 #define ITE_887x_MISCR 0x9c 862 #define ITE_887x_INTCBAR 0x78 863 #define ITE_887x_UARTBAR 0x7c 864 #define ITE_887x_PS0BAR 0x10 865 #define ITE_887x_POSIO0 0x60 866 867 /* I/O space size */ 868 #define ITE_887x_IOSIZE 32 869 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 870 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 871 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 872 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 873 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 874 #define ITE_887x_POSIO_SPEED (3 << 29) 875 /* enable IO_Space bit */ 876 #define ITE_887x_POSIO_ENABLE (1 << 31) 877 878 /* inta_addr are the configuration addresses of the ITE */ 879 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 880 static int pci_ite887x_init(struct pci_dev *dev) 881 { 882 int ret, i, type; 883 struct resource *iobase = NULL; 884 u32 miscr, uartbar, ioport; 885 886 /* search for the base-ioport */ 887 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 888 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 889 "ite887x"); 890 if (iobase != NULL) { 891 /* write POSIO0R - speed | size | ioport */ 892 pci_write_config_dword(dev, ITE_887x_POSIO0, 893 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 894 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 895 /* write INTCBAR - ioport */ 896 pci_write_config_dword(dev, ITE_887x_INTCBAR, 897 inta_addr[i]); 898 ret = inb(inta_addr[i]); 899 if (ret != 0xff) { 900 /* ioport connected */ 901 break; 902 } 903 release_region(iobase->start, ITE_887x_IOSIZE); 904 } 905 } 906 907 if (i == ARRAY_SIZE(inta_addr)) { 908 pci_err(dev, "could not find iobase\n"); 909 return -ENODEV; 910 } 911 912 /* start of undocumented type checking (see parport_pc.c) */ 913 type = inb(iobase->start + 0x18) & 0x0f; 914 915 switch (type) { 916 case 0x2: /* ITE8871 (1P) */ 917 case 0xa: /* ITE8875 (1P) */ 918 ret = 0; 919 break; 920 case 0xe: /* ITE8872 (2S1P) */ 921 ret = 2; 922 break; 923 case 0x6: /* ITE8873 (1S) */ 924 ret = 1; 925 break; 926 case 0x8: /* ITE8874 (2S) */ 927 ret = 2; 928 break; 929 default: 930 moan_device("Unknown ITE887x", dev); 931 ret = -ENODEV; 932 } 933 934 /* configure all serial ports */ 935 for (i = 0; i < ret; i++) { 936 /* read the I/O port from the device */ 937 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 938 &ioport); 939 ioport &= 0x0000FF00; /* the actual base address */ 940 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 941 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 942 ITE_887x_POSIO_IOSIZE_8 | ioport); 943 944 /* write the ioport to the UARTBAR */ 945 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 946 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 947 uartbar |= (ioport << (16 * i)); /* set the ioport */ 948 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 949 950 /* get current config */ 951 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 952 /* disable interrupts (UARTx_Routing[3:0]) */ 953 miscr &= ~(0xf << (12 - 4 * i)); 954 /* activate the UART (UARTx_En) */ 955 miscr |= 1 << (23 - i); 956 /* write new config with activated UART */ 957 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 958 } 959 960 if (ret <= 0) { 961 /* the device has no UARTs if we get here */ 962 release_region(iobase->start, ITE_887x_IOSIZE); 963 } 964 965 return ret; 966 } 967 968 static void pci_ite887x_exit(struct pci_dev *dev) 969 { 970 u32 ioport; 971 /* the ioport is bit 0-15 in POSIO0R */ 972 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 973 ioport &= 0xffff; 974 release_region(ioport, ITE_887x_IOSIZE); 975 } 976 977 /* 978 * Oxford Semiconductor Inc. 979 * Check if an OxSemi device is part of the Tornado range of devices. 980 */ 981 #define PCI_VENDOR_ID_ENDRUN 0x7401 982 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 983 984 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 985 { 986 /* OxSemi Tornado devices are all 0xCxxx */ 987 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 988 (dev->device & 0xf000) != 0xc000) 989 return false; 990 991 /* EndRun devices are all 0xExxx */ 992 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 993 (dev->device & 0xf000) != 0xe000) 994 return false; 995 996 return true; 997 } 998 999 /* 1000 * Determine the number of ports available on a Tornado device. 1001 */ 1002 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1003 { 1004 u8 __iomem *p; 1005 unsigned long deviceID; 1006 unsigned int number_uarts = 0; 1007 1008 if (!pci_oxsemi_tornado_p(dev)) 1009 return 0; 1010 1011 p = pci_iomap(dev, 0, 5); 1012 if (p == NULL) 1013 return -ENOMEM; 1014 1015 deviceID = ioread32(p); 1016 /* Tornado device */ 1017 if (deviceID == 0x07000200) { 1018 number_uarts = ioread8(p + 4); 1019 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1020 number_uarts, 1021 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1022 "EndRun" : "Oxford"); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1029 #define OXSEMI_TORNADO_TCR_MASK 0xf 1030 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1031 #define OXSEMI_TORNADO_CPR_MIN 0x008 1032 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1033 1034 /* 1035 * Determine the oversampling rate, the clock prescaler, and the clock 1036 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1037 * which is four times the baud base, and the prescaler increments in 1038 * steps of 1/8. Therefore to make calculations on integers we need 1039 * to use a scaled clock rate, which is the baud base multiplied by 32 1040 * (or our assumed UART clock rate multiplied by 2). 1041 * 1042 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1043 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1044 * values between 1.000 and 63.875 inclusive (operation for values from 1045 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1046 * unsigned 16-bit integer. 1047 * 1048 * For the most accurate baud rate we use a table of predetermined 1049 * oversampling rates and clock prescalers that records all possible 1050 * products of the two parameters in the range from 4 up to 255 inclusive, 1051 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1052 * by 8. The table is sorted by the decreasing value of the oversampling 1053 * rate and ties are resolved by sorting by the decreasing value of the 1054 * product. This way preference is given to higher oversampling rates. 1055 * 1056 * We iterate over the table and choose the product of an oversampling 1057 * rate and a clock prescaler that gives the lowest integer division 1058 * result deviation, or if an exact integer divider is found we stop 1059 * looking for it right away. We do some fixup if the resulting clock 1060 * divisor required would be out of its unsigned 16-bit integer range. 1061 * 1062 * Finally we abuse the supposed fractional part returned to encode the 1063 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1064 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1065 */ 1066 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1067 unsigned int baud, 1068 unsigned int *frac) 1069 { 1070 static u8 p[][2] = { 1071 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1072 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1073 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1074 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1075 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1076 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1077 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1078 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1079 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1080 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1081 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1082 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1083 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1084 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1085 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1086 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1087 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1088 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1089 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1090 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1091 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1092 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1093 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1094 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1095 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1096 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1097 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1098 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1099 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1100 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1101 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1102 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1103 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1104 { 4, 9, }, { 4, 8, }, 1105 }; 1106 /* Scale the quotient for comparison to get the fractional part. */ 1107 const unsigned int quot_scale = 65536; 1108 unsigned int sclk = port->uartclk * 2; 1109 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1110 unsigned int best_squot; 1111 unsigned int squot; 1112 unsigned int quot; 1113 u16 cpr; 1114 u8 tcr; 1115 int i; 1116 1117 /* Old custom speed handling. */ 1118 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1119 unsigned int cust_div = port->custom_divisor; 1120 1121 quot = cust_div & UART_DIV_MAX; 1122 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1123 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1124 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1125 cpr = OXSEMI_TORNADO_CPR_DEF; 1126 } else { 1127 best_squot = quot_scale; 1128 for (i = 0; i < ARRAY_SIZE(p); i++) { 1129 unsigned int spre; 1130 unsigned int srem; 1131 u8 cp; 1132 u8 tc; 1133 1134 tc = p[i][0]; 1135 cp = p[i][1]; 1136 spre = tc * cp; 1137 1138 srem = sdiv % spre; 1139 if (srem > spre / 2) 1140 srem = spre - srem; 1141 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1142 1143 if (srem == 0) { 1144 tcr = tc; 1145 cpr = cp; 1146 quot = sdiv / spre; 1147 break; 1148 } else if (squot < best_squot) { 1149 best_squot = squot; 1150 tcr = tc; 1151 cpr = cp; 1152 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1153 } 1154 } 1155 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1156 quot % 2 == 0) { 1157 quot >>= 1; 1158 tcr <<= 1; 1159 } 1160 while (quot > UART_DIV_MAX) { 1161 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1162 quot >>= 1; 1163 tcr <<= 1; 1164 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1165 quot >>= 1; 1166 cpr <<= 1; 1167 } else { 1168 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1169 cpr = OXSEMI_TORNADO_CPR_MASK; 1170 } 1171 } 1172 } 1173 1174 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1175 return quot; 1176 } 1177 1178 /* 1179 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1180 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1181 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1182 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1183 * has to be written first, followed by CPR2, which occupies the location 1184 * of CKS used with earlier UART designs. 1185 */ 1186 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1187 unsigned int baud, 1188 unsigned int quot, 1189 unsigned int quot_frac) 1190 { 1191 struct uart_8250_port *up = up_to_u8250p(port); 1192 u8 cpr2 = quot_frac >> 16; 1193 u8 cpr = quot_frac >> 8; 1194 u8 tcr = quot_frac; 1195 1196 serial_icr_write(up, UART_TCR, tcr); 1197 serial_icr_write(up, UART_CPR, cpr); 1198 serial_icr_write(up, UART_CKS, cpr2); 1199 serial8250_do_set_divisor(port, baud, quot, 0); 1200 } 1201 1202 /* 1203 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1204 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1205 */ 1206 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1207 unsigned int mctrl) 1208 { 1209 struct uart_8250_port *up = up_to_u8250p(port); 1210 1211 up->mcr |= UART_MCR_CLKSEL; 1212 serial8250_do_set_mctrl(port, mctrl); 1213 } 1214 1215 /* 1216 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1217 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1218 */ 1219 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1220 const struct pciserial_board *board, 1221 struct uart_8250_port *up, int idx) 1222 { 1223 struct pci_dev *dev = priv->dev; 1224 1225 if (pci_oxsemi_tornado_p(dev)) { 1226 up->port.flags |= UPF_FULL_PROBE; 1227 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1228 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1229 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1230 } 1231 1232 return pci_default_setup(priv, board, up, idx); 1233 } 1234 1235 static int pci_asix_setup(struct serial_private *priv, 1236 const struct pciserial_board *board, 1237 struct uart_8250_port *port, int idx) 1238 { 1239 port->bugs |= UART_BUG_PARITY; 1240 return pci_default_setup(priv, board, port, idx); 1241 } 1242 1243 #define QPCR_TEST_FOR1 0x3F 1244 #define QPCR_TEST_GET1 0x00 1245 #define QPCR_TEST_FOR2 0x40 1246 #define QPCR_TEST_GET2 0x40 1247 #define QPCR_TEST_FOR3 0x80 1248 #define QPCR_TEST_GET3 0x40 1249 #define QPCR_TEST_FOR4 0xC0 1250 #define QPCR_TEST_GET4 0x80 1251 1252 #define QOPR_CLOCK_X1 0x0000 1253 #define QOPR_CLOCK_X2 0x0001 1254 #define QOPR_CLOCK_X4 0x0002 1255 #define QOPR_CLOCK_X8 0x0003 1256 #define QOPR_CLOCK_RATE_MASK 0x0003 1257 1258 /* Quatech devices have their own extra interface features */ 1259 static struct pci_device_id quatech_cards[] = { 1260 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1261 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1262 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1263 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1264 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1265 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1266 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1267 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1268 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1269 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1270 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1271 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1272 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1273 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1274 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1275 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1276 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1277 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1278 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1279 { 0, } 1280 }; 1281 1282 static int pci_quatech_rqopr(struct uart_8250_port *port) 1283 { 1284 unsigned long base = port->port.iobase; 1285 u8 LCR, val; 1286 1287 LCR = inb(base + UART_LCR); 1288 outb(0xBF, base + UART_LCR); 1289 val = inb(base + UART_SCR); 1290 outb(LCR, base + UART_LCR); 1291 return val; 1292 } 1293 1294 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1295 { 1296 unsigned long base = port->port.iobase; 1297 u8 LCR; 1298 1299 LCR = inb(base + UART_LCR); 1300 outb(0xBF, base + UART_LCR); 1301 inb(base + UART_SCR); 1302 outb(qopr, base + UART_SCR); 1303 outb(LCR, base + UART_LCR); 1304 } 1305 1306 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1307 { 1308 unsigned long base = port->port.iobase; 1309 u8 LCR, val, qmcr; 1310 1311 LCR = inb(base + UART_LCR); 1312 outb(0xBF, base + UART_LCR); 1313 val = inb(base + UART_SCR); 1314 outb(val | 0x10, base + UART_SCR); 1315 qmcr = inb(base + UART_MCR); 1316 outb(val, base + UART_SCR); 1317 outb(LCR, base + UART_LCR); 1318 1319 return qmcr; 1320 } 1321 1322 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1323 { 1324 unsigned long base = port->port.iobase; 1325 u8 LCR, val; 1326 1327 LCR = inb(base + UART_LCR); 1328 outb(0xBF, base + UART_LCR); 1329 val = inb(base + UART_SCR); 1330 outb(val | 0x10, base + UART_SCR); 1331 outb(qmcr, base + UART_MCR); 1332 outb(val, base + UART_SCR); 1333 outb(LCR, base + UART_LCR); 1334 } 1335 1336 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1337 { 1338 unsigned long base = port->port.iobase; 1339 u8 LCR, val; 1340 1341 LCR = inb(base + UART_LCR); 1342 outb(0xBF, base + UART_LCR); 1343 val = inb(base + UART_SCR); 1344 if (val & 0x20) { 1345 outb(0x80, UART_LCR); 1346 if (!(inb(UART_SCR) & 0x20)) { 1347 outb(LCR, base + UART_LCR); 1348 return 1; 1349 } 1350 } 1351 return 0; 1352 } 1353 1354 static int pci_quatech_test(struct uart_8250_port *port) 1355 { 1356 u8 reg, qopr; 1357 1358 qopr = pci_quatech_rqopr(port); 1359 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1360 reg = pci_quatech_rqopr(port) & 0xC0; 1361 if (reg != QPCR_TEST_GET1) 1362 return -EINVAL; 1363 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1364 reg = pci_quatech_rqopr(port) & 0xC0; 1365 if (reg != QPCR_TEST_GET2) 1366 return -EINVAL; 1367 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1368 reg = pci_quatech_rqopr(port) & 0xC0; 1369 if (reg != QPCR_TEST_GET3) 1370 return -EINVAL; 1371 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1372 reg = pci_quatech_rqopr(port) & 0xC0; 1373 if (reg != QPCR_TEST_GET4) 1374 return -EINVAL; 1375 1376 pci_quatech_wqopr(port, qopr); 1377 return 0; 1378 } 1379 1380 static int pci_quatech_clock(struct uart_8250_port *port) 1381 { 1382 u8 qopr, reg, set; 1383 unsigned long clock; 1384 1385 if (pci_quatech_test(port) < 0) 1386 return 1843200; 1387 1388 qopr = pci_quatech_rqopr(port); 1389 1390 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1391 reg = pci_quatech_rqopr(port); 1392 if (reg & QOPR_CLOCK_X8) { 1393 clock = 1843200; 1394 goto out; 1395 } 1396 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1397 reg = pci_quatech_rqopr(port); 1398 if (!(reg & QOPR_CLOCK_X8)) { 1399 clock = 1843200; 1400 goto out; 1401 } 1402 reg &= QOPR_CLOCK_X8; 1403 if (reg == QOPR_CLOCK_X2) { 1404 clock = 3685400; 1405 set = QOPR_CLOCK_X2; 1406 } else if (reg == QOPR_CLOCK_X4) { 1407 clock = 7372800; 1408 set = QOPR_CLOCK_X4; 1409 } else if (reg == QOPR_CLOCK_X8) { 1410 clock = 14745600; 1411 set = QOPR_CLOCK_X8; 1412 } else { 1413 clock = 1843200; 1414 set = QOPR_CLOCK_X1; 1415 } 1416 qopr &= ~QOPR_CLOCK_RATE_MASK; 1417 qopr |= set; 1418 1419 out: 1420 pci_quatech_wqopr(port, qopr); 1421 return clock; 1422 } 1423 1424 static int pci_quatech_rs422(struct uart_8250_port *port) 1425 { 1426 u8 qmcr; 1427 int rs422 = 0; 1428 1429 if (!pci_quatech_has_qmcr(port)) 1430 return 0; 1431 qmcr = pci_quatech_rqmcr(port); 1432 pci_quatech_wqmcr(port, 0xFF); 1433 if (pci_quatech_rqmcr(port)) 1434 rs422 = 1; 1435 pci_quatech_wqmcr(port, qmcr); 1436 return rs422; 1437 } 1438 1439 static int pci_quatech_init(struct pci_dev *dev) 1440 { 1441 const struct pci_device_id *match; 1442 bool amcc = false; 1443 1444 match = pci_match_id(quatech_cards, dev); 1445 if (match) 1446 amcc = match->driver_data; 1447 else 1448 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1449 1450 if (amcc) { 1451 unsigned long base = pci_resource_start(dev, 0); 1452 if (base) { 1453 u32 tmp; 1454 1455 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1456 tmp = inl(base + 0x3c); 1457 outl(tmp | 0x01000000, base + 0x3c); 1458 outl(tmp & ~0x01000000, base + 0x3c); 1459 } 1460 } 1461 return 0; 1462 } 1463 1464 static int pci_quatech_setup(struct serial_private *priv, 1465 const struct pciserial_board *board, 1466 struct uart_8250_port *port, int idx) 1467 { 1468 /* Needed by pci_quatech calls below */ 1469 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1470 /* Set up the clocking */ 1471 port->port.uartclk = pci_quatech_clock(port); 1472 /* For now just warn about RS422 */ 1473 if (pci_quatech_rs422(port)) 1474 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1475 return pci_default_setup(priv, board, port, idx); 1476 } 1477 1478 static int pci_default_setup(struct serial_private *priv, 1479 const struct pciserial_board *board, 1480 struct uart_8250_port *port, int idx) 1481 { 1482 unsigned int bar, offset = board->first_offset, maxnr; 1483 1484 bar = FL_GET_BASE(board->flags); 1485 if (board->flags & FL_BASE_BARS) 1486 bar += idx; 1487 else 1488 offset += idx * board->uart_offset; 1489 1490 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1491 (board->reg_shift + 3); 1492 1493 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1494 return 1; 1495 1496 return setup_port(priv, port, bar, offset, board->reg_shift); 1497 } 1498 1499 static int 1500 ce4100_serial_setup(struct serial_private *priv, 1501 const struct pciserial_board *board, 1502 struct uart_8250_port *port, int idx) 1503 { 1504 int ret; 1505 1506 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1507 port->port.iotype = UPIO_MEM32; 1508 port->port.type = PORT_XSCALE; 1509 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1510 port->port.regshift = 2; 1511 1512 return ret; 1513 } 1514 1515 static int 1516 pci_omegapci_setup(struct serial_private *priv, 1517 const struct pciserial_board *board, 1518 struct uart_8250_port *port, int idx) 1519 { 1520 return setup_port(priv, port, 2, idx * 8, 0); 1521 } 1522 1523 static int 1524 pci_brcm_trumanage_setup(struct serial_private *priv, 1525 const struct pciserial_board *board, 1526 struct uart_8250_port *port, int idx) 1527 { 1528 int ret = pci_default_setup(priv, board, port, idx); 1529 1530 port->port.type = PORT_BRCM_TRUMANAGE; 1531 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1532 return ret; 1533 } 1534 1535 /* RTS will control by MCR if this bit is 0 */ 1536 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1537 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1538 #define FINTEK_RTS_INVERT BIT(5) 1539 1540 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1541 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1542 struct serial_rs485 *rs485) 1543 { 1544 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1545 u8 setting; 1546 u8 *index = (u8 *) port->private_data; 1547 1548 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1549 1550 if (rs485->flags & SER_RS485_ENABLED) { 1551 /* Enable RTS H/W control mode */ 1552 setting |= FINTEK_RTS_CONTROL_BY_HW; 1553 1554 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1555 /* RTS driving high on TX */ 1556 setting &= ~FINTEK_RTS_INVERT; 1557 } else { 1558 /* RTS driving low on TX */ 1559 setting |= FINTEK_RTS_INVERT; 1560 } 1561 } else { 1562 /* Disable RTS H/W control mode */ 1563 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1564 } 1565 1566 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1567 1568 return 0; 1569 } 1570 1571 static const struct serial_rs485 pci_fintek_rs485_supported = { 1572 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1573 /* F81504/508/512 does not support RTS delay before or after send */ 1574 }; 1575 1576 static int pci_fintek_setup(struct serial_private *priv, 1577 const struct pciserial_board *board, 1578 struct uart_8250_port *port, int idx) 1579 { 1580 struct pci_dev *pdev = priv->dev; 1581 u8 *data; 1582 u8 config_base; 1583 u16 iobase; 1584 1585 config_base = 0x40 + 0x08 * idx; 1586 1587 /* Get the io address from configuration space */ 1588 pci_read_config_word(pdev, config_base + 4, &iobase); 1589 1590 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1591 1592 port->port.iotype = UPIO_PORT; 1593 port->port.iobase = iobase; 1594 port->port.rs485_config = pci_fintek_rs485_config; 1595 port->port.rs485_supported = pci_fintek_rs485_supported; 1596 1597 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1598 if (!data) 1599 return -ENOMEM; 1600 1601 /* preserve index in PCI configuration space */ 1602 *data = idx; 1603 port->port.private_data = data; 1604 1605 return 0; 1606 } 1607 1608 static int pci_fintek_init(struct pci_dev *dev) 1609 { 1610 unsigned long iobase; 1611 u32 max_port, i; 1612 resource_size_t bar_data[3]; 1613 u8 config_base; 1614 struct serial_private *priv = pci_get_drvdata(dev); 1615 1616 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1617 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1618 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1619 return -ENODEV; 1620 1621 switch (dev->device) { 1622 case 0x1104: /* 4 ports */ 1623 case 0x1108: /* 8 ports */ 1624 max_port = dev->device & 0xff; 1625 break; 1626 case 0x1112: /* 12 ports */ 1627 max_port = 12; 1628 break; 1629 default: 1630 return -EINVAL; 1631 } 1632 1633 /* Get the io address dispatch from the BIOS */ 1634 bar_data[0] = pci_resource_start(dev, 5); 1635 bar_data[1] = pci_resource_start(dev, 4); 1636 bar_data[2] = pci_resource_start(dev, 3); 1637 1638 for (i = 0; i < max_port; ++i) { 1639 /* UART0 configuration offset start from 0x40 */ 1640 config_base = 0x40 + 0x08 * i; 1641 1642 /* Calculate Real IO Port */ 1643 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1644 1645 /* Enable UART I/O port */ 1646 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1647 1648 /* Select 128-byte FIFO and 8x FIFO threshold */ 1649 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1650 1651 /* LSB UART */ 1652 pci_write_config_byte(dev, config_base + 0x04, 1653 (u8)(iobase & 0xff)); 1654 1655 /* MSB UART */ 1656 pci_write_config_byte(dev, config_base + 0x05, 1657 (u8)((iobase & 0xff00) >> 8)); 1658 1659 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1660 1661 if (!priv) { 1662 /* First init without port data 1663 * force init to RS232 Mode 1664 */ 1665 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1666 } 1667 } 1668 1669 return max_port; 1670 } 1671 1672 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1673 { 1674 struct f815xxa_data *data = p->private_data; 1675 unsigned long flags; 1676 1677 spin_lock_irqsave(&data->lock, flags); 1678 writeb(value, p->membase + offset); 1679 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1680 spin_unlock_irqrestore(&data->lock, flags); 1681 } 1682 1683 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1684 const struct pciserial_board *board, 1685 struct uart_8250_port *port, int idx) 1686 { 1687 struct pci_dev *pdev = priv->dev; 1688 struct f815xxa_data *data; 1689 1690 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1691 if (!data) 1692 return -ENOMEM; 1693 1694 data->idx = idx; 1695 spin_lock_init(&data->lock); 1696 1697 port->port.private_data = data; 1698 port->port.iotype = UPIO_MEM; 1699 port->port.flags |= UPF_IOREMAP; 1700 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1701 port->port.serial_out = f815xxa_mem_serial_out; 1702 1703 return 0; 1704 } 1705 1706 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1707 { 1708 u32 max_port, i; 1709 int config_base; 1710 1711 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1712 return -ENODEV; 1713 1714 switch (dev->device) { 1715 case 0x1204: /* 4 ports */ 1716 case 0x1208: /* 8 ports */ 1717 max_port = dev->device & 0xff; 1718 break; 1719 case 0x1212: /* 12 ports */ 1720 max_port = 12; 1721 break; 1722 default: 1723 return -EINVAL; 1724 } 1725 1726 /* Set to mmio decode */ 1727 pci_write_config_byte(dev, 0x209, 0x40); 1728 1729 for (i = 0; i < max_port; ++i) { 1730 /* UART0 configuration offset start from 0x2A0 */ 1731 config_base = 0x2A0 + 0x08 * i; 1732 1733 /* Select 128-byte FIFO and 8x FIFO threshold */ 1734 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1735 1736 /* Enable UART I/O port */ 1737 pci_write_config_byte(dev, config_base + 0, 0x01); 1738 } 1739 1740 return max_port; 1741 } 1742 1743 static int skip_tx_en_setup(struct serial_private *priv, 1744 const struct pciserial_board *board, 1745 struct uart_8250_port *port, int idx) 1746 { 1747 port->port.quirks |= UPQ_NO_TXEN_TEST; 1748 pci_dbg(priv->dev, 1749 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1750 priv->dev->vendor, priv->dev->device, 1751 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1752 1753 return pci_default_setup(priv, board, port, idx); 1754 } 1755 1756 static void kt_handle_break(struct uart_port *p) 1757 { 1758 struct uart_8250_port *up = up_to_u8250p(p); 1759 /* 1760 * On receipt of a BI, serial device in Intel ME (Intel 1761 * management engine) needs to have its fifos cleared for sane 1762 * SOL (Serial Over Lan) output. 1763 */ 1764 serial8250_clear_and_reinit_fifos(up); 1765 } 1766 1767 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1768 { 1769 struct uart_8250_port *up = up_to_u8250p(p); 1770 unsigned int val; 1771 1772 /* 1773 * When the Intel ME (management engine) gets reset its serial 1774 * port registers could return 0 momentarily. Functions like 1775 * serial8250_console_write, read and save the IER, perform 1776 * some operation and then restore it. In order to avoid 1777 * setting IER register inadvertently to 0, if the value read 1778 * is 0, double check with ier value in uart_8250_port and use 1779 * that instead. up->ier should be the same value as what is 1780 * currently configured. 1781 */ 1782 val = inb(p->iobase + offset); 1783 if (offset == UART_IER) { 1784 if (val == 0) 1785 val = up->ier; 1786 } 1787 return val; 1788 } 1789 1790 static int kt_serial_setup(struct serial_private *priv, 1791 const struct pciserial_board *board, 1792 struct uart_8250_port *port, int idx) 1793 { 1794 port->port.flags |= UPF_BUG_THRE; 1795 port->port.serial_in = kt_serial_in; 1796 port->port.handle_break = kt_handle_break; 1797 return skip_tx_en_setup(priv, board, port, idx); 1798 } 1799 1800 static int pci_eg20t_init(struct pci_dev *dev) 1801 { 1802 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1803 return -ENODEV; 1804 #else 1805 return 0; 1806 #endif 1807 } 1808 1809 static int 1810 pci_wch_ch353_setup(struct serial_private *priv, 1811 const struct pciserial_board *board, 1812 struct uart_8250_port *port, int idx) 1813 { 1814 port->port.flags |= UPF_FIXED_TYPE; 1815 port->port.type = PORT_16550A; 1816 return pci_default_setup(priv, board, port, idx); 1817 } 1818 1819 static int 1820 pci_wch_ch355_setup(struct serial_private *priv, 1821 const struct pciserial_board *board, 1822 struct uart_8250_port *port, int idx) 1823 { 1824 port->port.flags |= UPF_FIXED_TYPE; 1825 port->port.type = PORT_16550A; 1826 return pci_default_setup(priv, board, port, idx); 1827 } 1828 1829 static int 1830 pci_wch_ch38x_setup(struct serial_private *priv, 1831 const struct pciserial_board *board, 1832 struct uart_8250_port *port, int idx) 1833 { 1834 port->port.flags |= UPF_FIXED_TYPE; 1835 port->port.type = PORT_16850; 1836 return pci_default_setup(priv, board, port, idx); 1837 } 1838 1839 1840 #define CH384_XINT_ENABLE_REG 0xEB 1841 #define CH384_XINT_ENABLE_BIT 0x02 1842 1843 static int pci_wch_ch38x_init(struct pci_dev *dev) 1844 { 1845 int max_port; 1846 unsigned long iobase; 1847 1848 1849 switch (dev->device) { 1850 case 0x3853: /* 8 ports */ 1851 max_port = 8; 1852 break; 1853 default: 1854 return -EINVAL; 1855 } 1856 1857 iobase = pci_resource_start(dev, 0); 1858 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1859 1860 return max_port; 1861 } 1862 1863 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1864 { 1865 unsigned long iobase; 1866 1867 iobase = pci_resource_start(dev, 0); 1868 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1869 } 1870 1871 1872 static int 1873 pci_sunix_setup(struct serial_private *priv, 1874 const struct pciserial_board *board, 1875 struct uart_8250_port *port, int idx) 1876 { 1877 int bar; 1878 int offset; 1879 1880 port->port.flags |= UPF_FIXED_TYPE; 1881 port->port.type = PORT_SUNIX; 1882 1883 if (idx < 4) { 1884 bar = 0; 1885 offset = idx * board->uart_offset; 1886 } else { 1887 bar = 1; 1888 idx -= 4; 1889 idx = div_s64_rem(idx, 4, &offset); 1890 offset = idx * 64 + offset * board->uart_offset; 1891 } 1892 1893 return setup_port(priv, port, bar, offset, 0); 1894 } 1895 1896 static int 1897 pci_moxa_setup(struct serial_private *priv, 1898 const struct pciserial_board *board, 1899 struct uart_8250_port *port, int idx) 1900 { 1901 unsigned int bar = FL_GET_BASE(board->flags); 1902 int offset; 1903 1904 if (board->num_ports == 4 && idx == 3) 1905 offset = 7 * board->uart_offset; 1906 else 1907 offset = idx * board->uart_offset; 1908 1909 return setup_port(priv, port, bar, offset, 0); 1910 } 1911 1912 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1913 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1914 #define PCI_DEVICE_ID_OCTPRO 0x0001 1915 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1916 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1917 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1918 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1919 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1920 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1921 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1922 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1923 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 1924 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 1925 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1926 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1927 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1928 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1929 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1930 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1931 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1932 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1933 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1934 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1935 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1936 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1937 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1938 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1939 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1940 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1941 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1942 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1943 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1944 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1945 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1946 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1947 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1948 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1949 #define PCI_VENDOR_ID_WCH 0x4348 1950 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1951 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1952 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1953 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1954 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1955 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1956 #define PCI_VENDOR_ID_AGESTAR 0x5372 1957 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1958 #define PCI_VENDOR_ID_ASIX 0x9710 1959 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1960 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1961 1962 #define PCIE_VENDOR_ID_WCH 0x1c00 1963 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1964 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1965 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1966 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1967 1968 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1969 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1970 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1971 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1972 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1973 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1974 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1975 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1976 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1977 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1978 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1979 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1980 1981 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1982 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1983 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1984 1985 /* 1986 * Master list of serial port init/setup/exit quirks. 1987 * This does not describe the general nature of the port. 1988 * (ie, baud base, number and location of ports, etc) 1989 * 1990 * This list is ordered alphabetically by vendor then device. 1991 * Specific entries must come before more generic entries. 1992 */ 1993 static struct pci_serial_quirk pci_serial_quirks[] = { 1994 /* 1995 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1996 */ 1997 { 1998 .vendor = PCI_VENDOR_ID_AMCC, 1999 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2000 .subvendor = PCI_ANY_ID, 2001 .subdevice = PCI_ANY_ID, 2002 .setup = addidata_apci7800_setup, 2003 }, 2004 /* 2005 * AFAVLAB cards - these may be called via parport_serial 2006 * It is not clear whether this applies to all products. 2007 */ 2008 { 2009 .vendor = PCI_VENDOR_ID_AFAVLAB, 2010 .device = PCI_ANY_ID, 2011 .subvendor = PCI_ANY_ID, 2012 .subdevice = PCI_ANY_ID, 2013 .setup = afavlab_setup, 2014 }, 2015 /* 2016 * HP Diva 2017 */ 2018 { 2019 .vendor = PCI_VENDOR_ID_HP, 2020 .device = PCI_DEVICE_ID_HP_DIVA, 2021 .subvendor = PCI_ANY_ID, 2022 .subdevice = PCI_ANY_ID, 2023 .init = pci_hp_diva_init, 2024 .setup = pci_hp_diva_setup, 2025 }, 2026 /* 2027 * HPE PCI serial device 2028 */ 2029 { 2030 .vendor = PCI_VENDOR_ID_HP_3PAR, 2031 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2032 .subvendor = PCI_ANY_ID, 2033 .subdevice = PCI_ANY_ID, 2034 .setup = pci_hp_diva_setup, 2035 }, 2036 /* 2037 * Intel 2038 */ 2039 { 2040 .vendor = PCI_VENDOR_ID_INTEL, 2041 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2042 .subvendor = 0xe4bf, 2043 .subdevice = PCI_ANY_ID, 2044 .init = pci_inteli960ni_init, 2045 .setup = pci_default_setup, 2046 }, 2047 { 2048 .vendor = PCI_VENDOR_ID_INTEL, 2049 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2050 .subvendor = PCI_ANY_ID, 2051 .subdevice = PCI_ANY_ID, 2052 .setup = skip_tx_en_setup, 2053 }, 2054 { 2055 .vendor = PCI_VENDOR_ID_INTEL, 2056 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2057 .subvendor = PCI_ANY_ID, 2058 .subdevice = PCI_ANY_ID, 2059 .setup = skip_tx_en_setup, 2060 }, 2061 { 2062 .vendor = PCI_VENDOR_ID_INTEL, 2063 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2064 .subvendor = PCI_ANY_ID, 2065 .subdevice = PCI_ANY_ID, 2066 .setup = skip_tx_en_setup, 2067 }, 2068 { 2069 .vendor = PCI_VENDOR_ID_INTEL, 2070 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2071 .subvendor = PCI_ANY_ID, 2072 .subdevice = PCI_ANY_ID, 2073 .setup = ce4100_serial_setup, 2074 }, 2075 { 2076 .vendor = PCI_VENDOR_ID_INTEL, 2077 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2078 .subvendor = PCI_ANY_ID, 2079 .subdevice = PCI_ANY_ID, 2080 .setup = kt_serial_setup, 2081 }, 2082 /* 2083 * ITE 2084 */ 2085 { 2086 .vendor = PCI_VENDOR_ID_ITE, 2087 .device = PCI_DEVICE_ID_ITE_8872, 2088 .subvendor = PCI_ANY_ID, 2089 .subdevice = PCI_ANY_ID, 2090 .init = pci_ite887x_init, 2091 .setup = pci_default_setup, 2092 .exit = pci_ite887x_exit, 2093 }, 2094 /* 2095 * National Instruments 2096 */ 2097 { 2098 .vendor = PCI_VENDOR_ID_NI, 2099 .device = PCI_DEVICE_ID_NI_PCI23216, 2100 .subvendor = PCI_ANY_ID, 2101 .subdevice = PCI_ANY_ID, 2102 .init = pci_ni8420_init, 2103 .setup = pci_default_setup, 2104 .exit = pci_ni8420_exit, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_NI, 2108 .device = PCI_DEVICE_ID_NI_PCI2328, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .init = pci_ni8420_init, 2112 .setup = pci_default_setup, 2113 .exit = pci_ni8420_exit, 2114 }, 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PCI2324, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PCI2322, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_DEVICE_ID_NI_PCI2324I, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8420_init, 2139 .setup = pci_default_setup, 2140 .exit = pci_ni8420_exit, 2141 }, 2142 { 2143 .vendor = PCI_VENDOR_ID_NI, 2144 .device = PCI_DEVICE_ID_NI_PCI2322I, 2145 .subvendor = PCI_ANY_ID, 2146 .subdevice = PCI_ANY_ID, 2147 .init = pci_ni8420_init, 2148 .setup = pci_default_setup, 2149 .exit = pci_ni8420_exit, 2150 }, 2151 { 2152 .vendor = PCI_VENDOR_ID_NI, 2153 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_ni8420_init, 2157 .setup = pci_default_setup, 2158 .exit = pci_ni8420_exit, 2159 }, 2160 { 2161 .vendor = PCI_VENDOR_ID_NI, 2162 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2163 .subvendor = PCI_ANY_ID, 2164 .subdevice = PCI_ANY_ID, 2165 .init = pci_ni8420_init, 2166 .setup = pci_default_setup, 2167 .exit = pci_ni8420_exit, 2168 }, 2169 { 2170 .vendor = PCI_VENDOR_ID_NI, 2171 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2172 .subvendor = PCI_ANY_ID, 2173 .subdevice = PCI_ANY_ID, 2174 .init = pci_ni8420_init, 2175 .setup = pci_default_setup, 2176 .exit = pci_ni8420_exit, 2177 }, 2178 { 2179 .vendor = PCI_VENDOR_ID_NI, 2180 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2181 .subvendor = PCI_ANY_ID, 2182 .subdevice = PCI_ANY_ID, 2183 .init = pci_ni8420_init, 2184 .setup = pci_default_setup, 2185 .exit = pci_ni8420_exit, 2186 }, 2187 { 2188 .vendor = PCI_VENDOR_ID_NI, 2189 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2190 .subvendor = PCI_ANY_ID, 2191 .subdevice = PCI_ANY_ID, 2192 .init = pci_ni8420_init, 2193 .setup = pci_default_setup, 2194 .exit = pci_ni8420_exit, 2195 }, 2196 { 2197 .vendor = PCI_VENDOR_ID_NI, 2198 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2199 .subvendor = PCI_ANY_ID, 2200 .subdevice = PCI_ANY_ID, 2201 .init = pci_ni8420_init, 2202 .setup = pci_default_setup, 2203 .exit = pci_ni8420_exit, 2204 }, 2205 { 2206 .vendor = PCI_VENDOR_ID_NI, 2207 .device = PCI_ANY_ID, 2208 .subvendor = PCI_ANY_ID, 2209 .subdevice = PCI_ANY_ID, 2210 .init = pci_ni8430_init, 2211 .setup = pci_ni8430_setup, 2212 .exit = pci_ni8430_exit, 2213 }, 2214 /* Quatech */ 2215 { 2216 .vendor = PCI_VENDOR_ID_QUATECH, 2217 .device = PCI_ANY_ID, 2218 .subvendor = PCI_ANY_ID, 2219 .subdevice = PCI_ANY_ID, 2220 .init = pci_quatech_init, 2221 .setup = pci_quatech_setup, 2222 }, 2223 /* 2224 * Panacom 2225 */ 2226 { 2227 .vendor = PCI_VENDOR_ID_PANACOM, 2228 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2229 .subvendor = PCI_ANY_ID, 2230 .subdevice = PCI_ANY_ID, 2231 .init = pci_plx9050_init, 2232 .setup = pci_default_setup, 2233 .exit = pci_plx9050_exit, 2234 }, 2235 { 2236 .vendor = PCI_VENDOR_ID_PANACOM, 2237 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2238 .subvendor = PCI_ANY_ID, 2239 .subdevice = PCI_ANY_ID, 2240 .init = pci_plx9050_init, 2241 .setup = pci_default_setup, 2242 .exit = pci_plx9050_exit, 2243 }, 2244 /* 2245 * PLX 2246 */ 2247 { 2248 .vendor = PCI_VENDOR_ID_PLX, 2249 .device = PCI_DEVICE_ID_PLX_9050, 2250 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2251 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2252 .init = pci_plx9050_init, 2253 .setup = pci_default_setup, 2254 .exit = pci_plx9050_exit, 2255 }, 2256 { 2257 .vendor = PCI_VENDOR_ID_PLX, 2258 .device = PCI_DEVICE_ID_PLX_9050, 2259 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2260 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2261 .init = pci_plx9050_init, 2262 .setup = pci_default_setup, 2263 .exit = pci_plx9050_exit, 2264 }, 2265 { 2266 .vendor = PCI_VENDOR_ID_PLX, 2267 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2268 .subvendor = PCI_VENDOR_ID_PLX, 2269 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2270 .init = pci_plx9050_init, 2271 .setup = pci_default_setup, 2272 .exit = pci_plx9050_exit, 2273 }, 2274 /* 2275 * SBS Technologies, Inc., PMC-OCTALPRO 232 2276 */ 2277 { 2278 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2279 .device = PCI_DEVICE_ID_OCTPRO, 2280 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2281 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2282 .init = sbs_init, 2283 .setup = sbs_setup, 2284 .exit = sbs_exit, 2285 }, 2286 /* 2287 * SBS Technologies, Inc., PMC-OCTALPRO 422 2288 */ 2289 { 2290 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2291 .device = PCI_DEVICE_ID_OCTPRO, 2292 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2293 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2294 .init = sbs_init, 2295 .setup = sbs_setup, 2296 .exit = sbs_exit, 2297 }, 2298 /* 2299 * SBS Technologies, Inc., P-Octal 232 2300 */ 2301 { 2302 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2303 .device = PCI_DEVICE_ID_OCTPRO, 2304 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2305 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2306 .init = sbs_init, 2307 .setup = sbs_setup, 2308 .exit = sbs_exit, 2309 }, 2310 /* 2311 * SBS Technologies, Inc., P-Octal 422 2312 */ 2313 { 2314 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2315 .device = PCI_DEVICE_ID_OCTPRO, 2316 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2317 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2318 .init = sbs_init, 2319 .setup = sbs_setup, 2320 .exit = sbs_exit, 2321 }, 2322 /* 2323 * SIIG cards - these may be called via parport_serial 2324 */ 2325 { 2326 .vendor = PCI_VENDOR_ID_SIIG, 2327 .device = PCI_ANY_ID, 2328 .subvendor = PCI_ANY_ID, 2329 .subdevice = PCI_ANY_ID, 2330 .init = pci_siig_init, 2331 .setup = pci_siig_setup, 2332 }, 2333 /* 2334 * Titan cards 2335 */ 2336 { 2337 .vendor = PCI_VENDOR_ID_TITAN, 2338 .device = PCI_DEVICE_ID_TITAN_400L, 2339 .subvendor = PCI_ANY_ID, 2340 .subdevice = PCI_ANY_ID, 2341 .setup = titan_400l_800l_setup, 2342 }, 2343 { 2344 .vendor = PCI_VENDOR_ID_TITAN, 2345 .device = PCI_DEVICE_ID_TITAN_800L, 2346 .subvendor = PCI_ANY_ID, 2347 .subdevice = PCI_ANY_ID, 2348 .setup = titan_400l_800l_setup, 2349 }, 2350 /* 2351 * Timedia cards 2352 */ 2353 { 2354 .vendor = PCI_VENDOR_ID_TIMEDIA, 2355 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2356 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2357 .subdevice = PCI_ANY_ID, 2358 .probe = pci_timedia_probe, 2359 .init = pci_timedia_init, 2360 .setup = pci_timedia_setup, 2361 }, 2362 { 2363 .vendor = PCI_VENDOR_ID_TIMEDIA, 2364 .device = PCI_ANY_ID, 2365 .subvendor = PCI_ANY_ID, 2366 .subdevice = PCI_ANY_ID, 2367 .setup = pci_timedia_setup, 2368 }, 2369 /* 2370 * Sunix PCI serial boards 2371 */ 2372 { 2373 .vendor = PCI_VENDOR_ID_SUNIX, 2374 .device = PCI_DEVICE_ID_SUNIX_1999, 2375 .subvendor = PCI_VENDOR_ID_SUNIX, 2376 .subdevice = PCI_ANY_ID, 2377 .setup = pci_sunix_setup, 2378 }, 2379 /* 2380 * Xircom cards 2381 */ 2382 { 2383 .vendor = PCI_VENDOR_ID_XIRCOM, 2384 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2385 .subvendor = PCI_ANY_ID, 2386 .subdevice = PCI_ANY_ID, 2387 .init = pci_xircom_init, 2388 .setup = pci_default_setup, 2389 }, 2390 /* 2391 * Netmos cards - these may be called via parport_serial 2392 */ 2393 { 2394 .vendor = PCI_VENDOR_ID_NETMOS, 2395 .device = PCI_ANY_ID, 2396 .subvendor = PCI_ANY_ID, 2397 .subdevice = PCI_ANY_ID, 2398 .init = pci_netmos_init, 2399 .setup = pci_netmos_9900_setup, 2400 }, 2401 /* 2402 * EndRun Technologies 2403 */ 2404 { 2405 .vendor = PCI_VENDOR_ID_ENDRUN, 2406 .device = PCI_ANY_ID, 2407 .subvendor = PCI_ANY_ID, 2408 .subdevice = PCI_ANY_ID, 2409 .init = pci_oxsemi_tornado_init, 2410 .setup = pci_default_setup, 2411 }, 2412 /* 2413 * For Oxford Semiconductor Tornado based devices 2414 */ 2415 { 2416 .vendor = PCI_VENDOR_ID_OXSEMI, 2417 .device = PCI_ANY_ID, 2418 .subvendor = PCI_ANY_ID, 2419 .subdevice = PCI_ANY_ID, 2420 .init = pci_oxsemi_tornado_init, 2421 .setup = pci_oxsemi_tornado_setup, 2422 }, 2423 { 2424 .vendor = PCI_VENDOR_ID_MAINPINE, 2425 .device = PCI_ANY_ID, 2426 .subvendor = PCI_ANY_ID, 2427 .subdevice = PCI_ANY_ID, 2428 .init = pci_oxsemi_tornado_init, 2429 .setup = pci_oxsemi_tornado_setup, 2430 }, 2431 { 2432 .vendor = PCI_VENDOR_ID_DIGI, 2433 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2434 .subvendor = PCI_SUBVENDOR_ID_IBM, 2435 .subdevice = PCI_ANY_ID, 2436 .init = pci_oxsemi_tornado_init, 2437 .setup = pci_oxsemi_tornado_setup, 2438 }, 2439 { 2440 .vendor = PCI_VENDOR_ID_INTEL, 2441 .device = 0x8811, 2442 .subvendor = PCI_ANY_ID, 2443 .subdevice = PCI_ANY_ID, 2444 .init = pci_eg20t_init, 2445 .setup = pci_default_setup, 2446 }, 2447 { 2448 .vendor = PCI_VENDOR_ID_INTEL, 2449 .device = 0x8812, 2450 .subvendor = PCI_ANY_ID, 2451 .subdevice = PCI_ANY_ID, 2452 .init = pci_eg20t_init, 2453 .setup = pci_default_setup, 2454 }, 2455 { 2456 .vendor = PCI_VENDOR_ID_INTEL, 2457 .device = 0x8813, 2458 .subvendor = PCI_ANY_ID, 2459 .subdevice = PCI_ANY_ID, 2460 .init = pci_eg20t_init, 2461 .setup = pci_default_setup, 2462 }, 2463 { 2464 .vendor = PCI_VENDOR_ID_INTEL, 2465 .device = 0x8814, 2466 .subvendor = PCI_ANY_ID, 2467 .subdevice = PCI_ANY_ID, 2468 .init = pci_eg20t_init, 2469 .setup = pci_default_setup, 2470 }, 2471 { 2472 .vendor = 0x10DB, 2473 .device = 0x8027, 2474 .subvendor = PCI_ANY_ID, 2475 .subdevice = PCI_ANY_ID, 2476 .init = pci_eg20t_init, 2477 .setup = pci_default_setup, 2478 }, 2479 { 2480 .vendor = 0x10DB, 2481 .device = 0x8028, 2482 .subvendor = PCI_ANY_ID, 2483 .subdevice = PCI_ANY_ID, 2484 .init = pci_eg20t_init, 2485 .setup = pci_default_setup, 2486 }, 2487 { 2488 .vendor = 0x10DB, 2489 .device = 0x8029, 2490 .subvendor = PCI_ANY_ID, 2491 .subdevice = PCI_ANY_ID, 2492 .init = pci_eg20t_init, 2493 .setup = pci_default_setup, 2494 }, 2495 { 2496 .vendor = 0x10DB, 2497 .device = 0x800C, 2498 .subvendor = PCI_ANY_ID, 2499 .subdevice = PCI_ANY_ID, 2500 .init = pci_eg20t_init, 2501 .setup = pci_default_setup, 2502 }, 2503 { 2504 .vendor = 0x10DB, 2505 .device = 0x800D, 2506 .subvendor = PCI_ANY_ID, 2507 .subdevice = PCI_ANY_ID, 2508 .init = pci_eg20t_init, 2509 .setup = pci_default_setup, 2510 }, 2511 /* 2512 * Cronyx Omega PCI (PLX-chip based) 2513 */ 2514 { 2515 .vendor = PCI_VENDOR_ID_PLX, 2516 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2517 .subvendor = PCI_ANY_ID, 2518 .subdevice = PCI_ANY_ID, 2519 .setup = pci_omegapci_setup, 2520 }, 2521 /* WCH CH353 1S1P card (16550 clone) */ 2522 { 2523 .vendor = PCI_VENDOR_ID_WCH, 2524 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2525 .subvendor = PCI_ANY_ID, 2526 .subdevice = PCI_ANY_ID, 2527 .setup = pci_wch_ch353_setup, 2528 }, 2529 /* WCH CH353 2S1P card (16550 clone) */ 2530 { 2531 .vendor = PCI_VENDOR_ID_WCH, 2532 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2533 .subvendor = PCI_ANY_ID, 2534 .subdevice = PCI_ANY_ID, 2535 .setup = pci_wch_ch353_setup, 2536 }, 2537 /* WCH CH353 4S card (16550 clone) */ 2538 { 2539 .vendor = PCI_VENDOR_ID_WCH, 2540 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2541 .subvendor = PCI_ANY_ID, 2542 .subdevice = PCI_ANY_ID, 2543 .setup = pci_wch_ch353_setup, 2544 }, 2545 /* WCH CH353 2S1PF card (16550 clone) */ 2546 { 2547 .vendor = PCI_VENDOR_ID_WCH, 2548 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2549 .subvendor = PCI_ANY_ID, 2550 .subdevice = PCI_ANY_ID, 2551 .setup = pci_wch_ch353_setup, 2552 }, 2553 /* WCH CH352 2S card (16550 clone) */ 2554 { 2555 .vendor = PCI_VENDOR_ID_WCH, 2556 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2557 .subvendor = PCI_ANY_ID, 2558 .subdevice = PCI_ANY_ID, 2559 .setup = pci_wch_ch353_setup, 2560 }, 2561 /* WCH CH355 4S card (16550 clone) */ 2562 { 2563 .vendor = PCI_VENDOR_ID_WCH, 2564 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2565 .subvendor = PCI_ANY_ID, 2566 .subdevice = PCI_ANY_ID, 2567 .setup = pci_wch_ch355_setup, 2568 }, 2569 /* WCH CH382 2S card (16850 clone) */ 2570 { 2571 .vendor = PCIE_VENDOR_ID_WCH, 2572 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2573 .subvendor = PCI_ANY_ID, 2574 .subdevice = PCI_ANY_ID, 2575 .setup = pci_wch_ch38x_setup, 2576 }, 2577 /* WCH CH382 2S1P card (16850 clone) */ 2578 { 2579 .vendor = PCIE_VENDOR_ID_WCH, 2580 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2581 .subvendor = PCI_ANY_ID, 2582 .subdevice = PCI_ANY_ID, 2583 .setup = pci_wch_ch38x_setup, 2584 }, 2585 /* WCH CH384 4S card (16850 clone) */ 2586 { 2587 .vendor = PCIE_VENDOR_ID_WCH, 2588 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2589 .subvendor = PCI_ANY_ID, 2590 .subdevice = PCI_ANY_ID, 2591 .setup = pci_wch_ch38x_setup, 2592 }, 2593 /* WCH CH384 8S card (16850 clone) */ 2594 { 2595 .vendor = PCIE_VENDOR_ID_WCH, 2596 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2597 .subvendor = PCI_ANY_ID, 2598 .subdevice = PCI_ANY_ID, 2599 .init = pci_wch_ch38x_init, 2600 .exit = pci_wch_ch38x_exit, 2601 .setup = pci_wch_ch38x_setup, 2602 }, 2603 /* 2604 * ASIX devices with FIFO bug 2605 */ 2606 { 2607 .vendor = PCI_VENDOR_ID_ASIX, 2608 .device = PCI_ANY_ID, 2609 .subvendor = PCI_ANY_ID, 2610 .subdevice = PCI_ANY_ID, 2611 .setup = pci_asix_setup, 2612 }, 2613 /* 2614 * Broadcom TruManage (NetXtreme) 2615 */ 2616 { 2617 .vendor = PCI_VENDOR_ID_BROADCOM, 2618 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2619 .subvendor = PCI_ANY_ID, 2620 .subdevice = PCI_ANY_ID, 2621 .setup = pci_brcm_trumanage_setup, 2622 }, 2623 { 2624 .vendor = 0x1c29, 2625 .device = 0x1104, 2626 .subvendor = PCI_ANY_ID, 2627 .subdevice = PCI_ANY_ID, 2628 .setup = pci_fintek_setup, 2629 .init = pci_fintek_init, 2630 }, 2631 { 2632 .vendor = 0x1c29, 2633 .device = 0x1108, 2634 .subvendor = PCI_ANY_ID, 2635 .subdevice = PCI_ANY_ID, 2636 .setup = pci_fintek_setup, 2637 .init = pci_fintek_init, 2638 }, 2639 { 2640 .vendor = 0x1c29, 2641 .device = 0x1112, 2642 .subvendor = PCI_ANY_ID, 2643 .subdevice = PCI_ANY_ID, 2644 .setup = pci_fintek_setup, 2645 .init = pci_fintek_init, 2646 }, 2647 /* 2648 * MOXA 2649 */ 2650 { 2651 .vendor = PCI_VENDOR_ID_MOXA, 2652 .device = PCI_ANY_ID, 2653 .subvendor = PCI_ANY_ID, 2654 .subdevice = PCI_ANY_ID, 2655 .setup = pci_moxa_setup, 2656 }, 2657 { 2658 .vendor = 0x1c29, 2659 .device = 0x1204, 2660 .subvendor = PCI_ANY_ID, 2661 .subdevice = PCI_ANY_ID, 2662 .setup = pci_fintek_f815xxa_setup, 2663 .init = pci_fintek_f815xxa_init, 2664 }, 2665 { 2666 .vendor = 0x1c29, 2667 .device = 0x1208, 2668 .subvendor = PCI_ANY_ID, 2669 .subdevice = PCI_ANY_ID, 2670 .setup = pci_fintek_f815xxa_setup, 2671 .init = pci_fintek_f815xxa_init, 2672 }, 2673 { 2674 .vendor = 0x1c29, 2675 .device = 0x1212, 2676 .subvendor = PCI_ANY_ID, 2677 .subdevice = PCI_ANY_ID, 2678 .setup = pci_fintek_f815xxa_setup, 2679 .init = pci_fintek_f815xxa_init, 2680 }, 2681 2682 /* 2683 * Default "match everything" terminator entry 2684 */ 2685 { 2686 .vendor = PCI_ANY_ID, 2687 .device = PCI_ANY_ID, 2688 .subvendor = PCI_ANY_ID, 2689 .subdevice = PCI_ANY_ID, 2690 .setup = pci_default_setup, 2691 } 2692 }; 2693 2694 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2695 { 2696 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2697 } 2698 2699 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2700 { 2701 struct pci_serial_quirk *quirk; 2702 2703 for (quirk = pci_serial_quirks; ; quirk++) 2704 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2705 quirk_id_matches(quirk->device, dev->device) && 2706 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2707 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2708 break; 2709 return quirk; 2710 } 2711 2712 /* 2713 * This is the configuration table for all of the PCI serial boards 2714 * which we support. It is directly indexed by the pci_board_num_t enum 2715 * value, which is encoded in the pci_device_id PCI probe table's 2716 * driver_data member. 2717 * 2718 * The makeup of these names are: 2719 * pbn_bn{_bt}_n_baud{_offsetinhex} 2720 * 2721 * bn = PCI BAR number 2722 * bt = Index using PCI BARs 2723 * n = number of serial ports 2724 * baud = baud rate 2725 * offsetinhex = offset for each sequential port (in hex) 2726 * 2727 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2728 * 2729 * Please note: in theory if n = 1, _bt infix should make no difference. 2730 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2731 */ 2732 enum pci_board_num_t { 2733 pbn_default = 0, 2734 2735 pbn_b0_1_115200, 2736 pbn_b0_2_115200, 2737 pbn_b0_4_115200, 2738 pbn_b0_5_115200, 2739 pbn_b0_8_115200, 2740 2741 pbn_b0_1_921600, 2742 pbn_b0_2_921600, 2743 pbn_b0_4_921600, 2744 2745 pbn_b0_2_1130000, 2746 2747 pbn_b0_4_1152000, 2748 2749 pbn_b0_4_1250000, 2750 2751 pbn_b0_2_1843200, 2752 pbn_b0_4_1843200, 2753 2754 pbn_b0_1_15625000, 2755 2756 pbn_b0_bt_1_115200, 2757 pbn_b0_bt_2_115200, 2758 pbn_b0_bt_4_115200, 2759 pbn_b0_bt_8_115200, 2760 2761 pbn_b0_bt_1_460800, 2762 pbn_b0_bt_2_460800, 2763 pbn_b0_bt_4_460800, 2764 2765 pbn_b0_bt_1_921600, 2766 pbn_b0_bt_2_921600, 2767 pbn_b0_bt_4_921600, 2768 pbn_b0_bt_8_921600, 2769 2770 pbn_b1_1_115200, 2771 pbn_b1_2_115200, 2772 pbn_b1_4_115200, 2773 pbn_b1_8_115200, 2774 pbn_b1_16_115200, 2775 2776 pbn_b1_1_921600, 2777 pbn_b1_2_921600, 2778 pbn_b1_4_921600, 2779 pbn_b1_8_921600, 2780 2781 pbn_b1_2_1250000, 2782 2783 pbn_b1_bt_1_115200, 2784 pbn_b1_bt_2_115200, 2785 pbn_b1_bt_4_115200, 2786 2787 pbn_b1_bt_2_921600, 2788 2789 pbn_b1_1_1382400, 2790 pbn_b1_2_1382400, 2791 pbn_b1_4_1382400, 2792 pbn_b1_8_1382400, 2793 2794 pbn_b2_1_115200, 2795 pbn_b2_2_115200, 2796 pbn_b2_4_115200, 2797 pbn_b2_8_115200, 2798 2799 pbn_b2_1_460800, 2800 pbn_b2_4_460800, 2801 pbn_b2_8_460800, 2802 pbn_b2_16_460800, 2803 2804 pbn_b2_1_921600, 2805 pbn_b2_4_921600, 2806 pbn_b2_8_921600, 2807 2808 pbn_b2_8_1152000, 2809 2810 pbn_b2_bt_1_115200, 2811 pbn_b2_bt_2_115200, 2812 pbn_b2_bt_4_115200, 2813 2814 pbn_b2_bt_2_921600, 2815 pbn_b2_bt_4_921600, 2816 2817 pbn_b3_2_115200, 2818 pbn_b3_4_115200, 2819 pbn_b3_8_115200, 2820 2821 pbn_b4_bt_2_921600, 2822 pbn_b4_bt_4_921600, 2823 pbn_b4_bt_8_921600, 2824 2825 /* 2826 * Board-specific versions. 2827 */ 2828 pbn_panacom, 2829 pbn_panacom2, 2830 pbn_panacom4, 2831 pbn_plx_romulus, 2832 pbn_oxsemi, 2833 pbn_oxsemi_1_15625000, 2834 pbn_oxsemi_2_15625000, 2835 pbn_oxsemi_4_15625000, 2836 pbn_oxsemi_8_15625000, 2837 pbn_intel_i960, 2838 pbn_sgi_ioc3, 2839 pbn_computone_4, 2840 pbn_computone_6, 2841 pbn_computone_8, 2842 pbn_sbsxrsio, 2843 pbn_pasemi_1682M, 2844 pbn_ni8430_2, 2845 pbn_ni8430_4, 2846 pbn_ni8430_8, 2847 pbn_ni8430_16, 2848 pbn_ADDIDATA_PCIe_1_3906250, 2849 pbn_ADDIDATA_PCIe_2_3906250, 2850 pbn_ADDIDATA_PCIe_4_3906250, 2851 pbn_ADDIDATA_PCIe_8_3906250, 2852 pbn_ce4100_1_115200, 2853 pbn_omegapci, 2854 pbn_NETMOS9900_2s_115200, 2855 pbn_brcm_trumanage, 2856 pbn_fintek_4, 2857 pbn_fintek_8, 2858 pbn_fintek_12, 2859 pbn_fintek_F81504A, 2860 pbn_fintek_F81508A, 2861 pbn_fintek_F81512A, 2862 pbn_wch382_2, 2863 pbn_wch384_4, 2864 pbn_wch384_8, 2865 pbn_sunix_pci_1s, 2866 pbn_sunix_pci_2s, 2867 pbn_sunix_pci_4s, 2868 pbn_sunix_pci_8s, 2869 pbn_sunix_pci_16s, 2870 pbn_titan_1_4000000, 2871 pbn_titan_2_4000000, 2872 pbn_titan_4_4000000, 2873 pbn_titan_8_4000000, 2874 pbn_moxa8250_2p, 2875 pbn_moxa8250_4p, 2876 pbn_moxa8250_8p, 2877 }; 2878 2879 /* 2880 * uart_offset - the space between channels 2881 * reg_shift - describes how the UART registers are mapped 2882 * to PCI memory by the card. 2883 * For example IER register on SBS, Inc. PMC-OctPro is located at 2884 * offset 0x10 from the UART base, while UART_IER is defined as 1 2885 * in include/linux/serial_reg.h, 2886 * see first lines of serial_in() and serial_out() in 8250.c 2887 */ 2888 2889 static struct pciserial_board pci_boards[] = { 2890 [pbn_default] = { 2891 .flags = FL_BASE0, 2892 .num_ports = 1, 2893 .base_baud = 115200, 2894 .uart_offset = 8, 2895 }, 2896 [pbn_b0_1_115200] = { 2897 .flags = FL_BASE0, 2898 .num_ports = 1, 2899 .base_baud = 115200, 2900 .uart_offset = 8, 2901 }, 2902 [pbn_b0_2_115200] = { 2903 .flags = FL_BASE0, 2904 .num_ports = 2, 2905 .base_baud = 115200, 2906 .uart_offset = 8, 2907 }, 2908 [pbn_b0_4_115200] = { 2909 .flags = FL_BASE0, 2910 .num_ports = 4, 2911 .base_baud = 115200, 2912 .uart_offset = 8, 2913 }, 2914 [pbn_b0_5_115200] = { 2915 .flags = FL_BASE0, 2916 .num_ports = 5, 2917 .base_baud = 115200, 2918 .uart_offset = 8, 2919 }, 2920 [pbn_b0_8_115200] = { 2921 .flags = FL_BASE0, 2922 .num_ports = 8, 2923 .base_baud = 115200, 2924 .uart_offset = 8, 2925 }, 2926 [pbn_b0_1_921600] = { 2927 .flags = FL_BASE0, 2928 .num_ports = 1, 2929 .base_baud = 921600, 2930 .uart_offset = 8, 2931 }, 2932 [pbn_b0_2_921600] = { 2933 .flags = FL_BASE0, 2934 .num_ports = 2, 2935 .base_baud = 921600, 2936 .uart_offset = 8, 2937 }, 2938 [pbn_b0_4_921600] = { 2939 .flags = FL_BASE0, 2940 .num_ports = 4, 2941 .base_baud = 921600, 2942 .uart_offset = 8, 2943 }, 2944 2945 [pbn_b0_2_1130000] = { 2946 .flags = FL_BASE0, 2947 .num_ports = 2, 2948 .base_baud = 1130000, 2949 .uart_offset = 8, 2950 }, 2951 2952 [pbn_b0_4_1152000] = { 2953 .flags = FL_BASE0, 2954 .num_ports = 4, 2955 .base_baud = 1152000, 2956 .uart_offset = 8, 2957 }, 2958 2959 [pbn_b0_4_1250000] = { 2960 .flags = FL_BASE0, 2961 .num_ports = 4, 2962 .base_baud = 1250000, 2963 .uart_offset = 8, 2964 }, 2965 2966 [pbn_b0_2_1843200] = { 2967 .flags = FL_BASE0, 2968 .num_ports = 2, 2969 .base_baud = 1843200, 2970 .uart_offset = 8, 2971 }, 2972 [pbn_b0_4_1843200] = { 2973 .flags = FL_BASE0, 2974 .num_ports = 4, 2975 .base_baud = 1843200, 2976 .uart_offset = 8, 2977 }, 2978 2979 [pbn_b0_1_15625000] = { 2980 .flags = FL_BASE0, 2981 .num_ports = 1, 2982 .base_baud = 15625000, 2983 .uart_offset = 8, 2984 }, 2985 2986 [pbn_b0_bt_1_115200] = { 2987 .flags = FL_BASE0|FL_BASE_BARS, 2988 .num_ports = 1, 2989 .base_baud = 115200, 2990 .uart_offset = 8, 2991 }, 2992 [pbn_b0_bt_2_115200] = { 2993 .flags = FL_BASE0|FL_BASE_BARS, 2994 .num_ports = 2, 2995 .base_baud = 115200, 2996 .uart_offset = 8, 2997 }, 2998 [pbn_b0_bt_4_115200] = { 2999 .flags = FL_BASE0|FL_BASE_BARS, 3000 .num_ports = 4, 3001 .base_baud = 115200, 3002 .uart_offset = 8, 3003 }, 3004 [pbn_b0_bt_8_115200] = { 3005 .flags = FL_BASE0|FL_BASE_BARS, 3006 .num_ports = 8, 3007 .base_baud = 115200, 3008 .uart_offset = 8, 3009 }, 3010 3011 [pbn_b0_bt_1_460800] = { 3012 .flags = FL_BASE0|FL_BASE_BARS, 3013 .num_ports = 1, 3014 .base_baud = 460800, 3015 .uart_offset = 8, 3016 }, 3017 [pbn_b0_bt_2_460800] = { 3018 .flags = FL_BASE0|FL_BASE_BARS, 3019 .num_ports = 2, 3020 .base_baud = 460800, 3021 .uart_offset = 8, 3022 }, 3023 [pbn_b0_bt_4_460800] = { 3024 .flags = FL_BASE0|FL_BASE_BARS, 3025 .num_ports = 4, 3026 .base_baud = 460800, 3027 .uart_offset = 8, 3028 }, 3029 3030 [pbn_b0_bt_1_921600] = { 3031 .flags = FL_BASE0|FL_BASE_BARS, 3032 .num_ports = 1, 3033 .base_baud = 921600, 3034 .uart_offset = 8, 3035 }, 3036 [pbn_b0_bt_2_921600] = { 3037 .flags = FL_BASE0|FL_BASE_BARS, 3038 .num_ports = 2, 3039 .base_baud = 921600, 3040 .uart_offset = 8, 3041 }, 3042 [pbn_b0_bt_4_921600] = { 3043 .flags = FL_BASE0|FL_BASE_BARS, 3044 .num_ports = 4, 3045 .base_baud = 921600, 3046 .uart_offset = 8, 3047 }, 3048 [pbn_b0_bt_8_921600] = { 3049 .flags = FL_BASE0|FL_BASE_BARS, 3050 .num_ports = 8, 3051 .base_baud = 921600, 3052 .uart_offset = 8, 3053 }, 3054 3055 [pbn_b1_1_115200] = { 3056 .flags = FL_BASE1, 3057 .num_ports = 1, 3058 .base_baud = 115200, 3059 .uart_offset = 8, 3060 }, 3061 [pbn_b1_2_115200] = { 3062 .flags = FL_BASE1, 3063 .num_ports = 2, 3064 .base_baud = 115200, 3065 .uart_offset = 8, 3066 }, 3067 [pbn_b1_4_115200] = { 3068 .flags = FL_BASE1, 3069 .num_ports = 4, 3070 .base_baud = 115200, 3071 .uart_offset = 8, 3072 }, 3073 [pbn_b1_8_115200] = { 3074 .flags = FL_BASE1, 3075 .num_ports = 8, 3076 .base_baud = 115200, 3077 .uart_offset = 8, 3078 }, 3079 [pbn_b1_16_115200] = { 3080 .flags = FL_BASE1, 3081 .num_ports = 16, 3082 .base_baud = 115200, 3083 .uart_offset = 8, 3084 }, 3085 3086 [pbn_b1_1_921600] = { 3087 .flags = FL_BASE1, 3088 .num_ports = 1, 3089 .base_baud = 921600, 3090 .uart_offset = 8, 3091 }, 3092 [pbn_b1_2_921600] = { 3093 .flags = FL_BASE1, 3094 .num_ports = 2, 3095 .base_baud = 921600, 3096 .uart_offset = 8, 3097 }, 3098 [pbn_b1_4_921600] = { 3099 .flags = FL_BASE1, 3100 .num_ports = 4, 3101 .base_baud = 921600, 3102 .uart_offset = 8, 3103 }, 3104 [pbn_b1_8_921600] = { 3105 .flags = FL_BASE1, 3106 .num_ports = 8, 3107 .base_baud = 921600, 3108 .uart_offset = 8, 3109 }, 3110 [pbn_b1_2_1250000] = { 3111 .flags = FL_BASE1, 3112 .num_ports = 2, 3113 .base_baud = 1250000, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b1_bt_1_115200] = { 3118 .flags = FL_BASE1|FL_BASE_BARS, 3119 .num_ports = 1, 3120 .base_baud = 115200, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b1_bt_2_115200] = { 3124 .flags = FL_BASE1|FL_BASE_BARS, 3125 .num_ports = 2, 3126 .base_baud = 115200, 3127 .uart_offset = 8, 3128 }, 3129 [pbn_b1_bt_4_115200] = { 3130 .flags = FL_BASE1|FL_BASE_BARS, 3131 .num_ports = 4, 3132 .base_baud = 115200, 3133 .uart_offset = 8, 3134 }, 3135 3136 [pbn_b1_bt_2_921600] = { 3137 .flags = FL_BASE1|FL_BASE_BARS, 3138 .num_ports = 2, 3139 .base_baud = 921600, 3140 .uart_offset = 8, 3141 }, 3142 3143 [pbn_b1_1_1382400] = { 3144 .flags = FL_BASE1, 3145 .num_ports = 1, 3146 .base_baud = 1382400, 3147 .uart_offset = 8, 3148 }, 3149 [pbn_b1_2_1382400] = { 3150 .flags = FL_BASE1, 3151 .num_ports = 2, 3152 .base_baud = 1382400, 3153 .uart_offset = 8, 3154 }, 3155 [pbn_b1_4_1382400] = { 3156 .flags = FL_BASE1, 3157 .num_ports = 4, 3158 .base_baud = 1382400, 3159 .uart_offset = 8, 3160 }, 3161 [pbn_b1_8_1382400] = { 3162 .flags = FL_BASE1, 3163 .num_ports = 8, 3164 .base_baud = 1382400, 3165 .uart_offset = 8, 3166 }, 3167 3168 [pbn_b2_1_115200] = { 3169 .flags = FL_BASE2, 3170 .num_ports = 1, 3171 .base_baud = 115200, 3172 .uart_offset = 8, 3173 }, 3174 [pbn_b2_2_115200] = { 3175 .flags = FL_BASE2, 3176 .num_ports = 2, 3177 .base_baud = 115200, 3178 .uart_offset = 8, 3179 }, 3180 [pbn_b2_4_115200] = { 3181 .flags = FL_BASE2, 3182 .num_ports = 4, 3183 .base_baud = 115200, 3184 .uart_offset = 8, 3185 }, 3186 [pbn_b2_8_115200] = { 3187 .flags = FL_BASE2, 3188 .num_ports = 8, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 3193 [pbn_b2_1_460800] = { 3194 .flags = FL_BASE2, 3195 .num_ports = 1, 3196 .base_baud = 460800, 3197 .uart_offset = 8, 3198 }, 3199 [pbn_b2_4_460800] = { 3200 .flags = FL_BASE2, 3201 .num_ports = 4, 3202 .base_baud = 460800, 3203 .uart_offset = 8, 3204 }, 3205 [pbn_b2_8_460800] = { 3206 .flags = FL_BASE2, 3207 .num_ports = 8, 3208 .base_baud = 460800, 3209 .uart_offset = 8, 3210 }, 3211 [pbn_b2_16_460800] = { 3212 .flags = FL_BASE2, 3213 .num_ports = 16, 3214 .base_baud = 460800, 3215 .uart_offset = 8, 3216 }, 3217 3218 [pbn_b2_1_921600] = { 3219 .flags = FL_BASE2, 3220 .num_ports = 1, 3221 .base_baud = 921600, 3222 .uart_offset = 8, 3223 }, 3224 [pbn_b2_4_921600] = { 3225 .flags = FL_BASE2, 3226 .num_ports = 4, 3227 .base_baud = 921600, 3228 .uart_offset = 8, 3229 }, 3230 [pbn_b2_8_921600] = { 3231 .flags = FL_BASE2, 3232 .num_ports = 8, 3233 .base_baud = 921600, 3234 .uart_offset = 8, 3235 }, 3236 3237 [pbn_b2_8_1152000] = { 3238 .flags = FL_BASE2, 3239 .num_ports = 8, 3240 .base_baud = 1152000, 3241 .uart_offset = 8, 3242 }, 3243 3244 [pbn_b2_bt_1_115200] = { 3245 .flags = FL_BASE2|FL_BASE_BARS, 3246 .num_ports = 1, 3247 .base_baud = 115200, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b2_bt_2_115200] = { 3251 .flags = FL_BASE2|FL_BASE_BARS, 3252 .num_ports = 2, 3253 .base_baud = 115200, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b2_bt_4_115200] = { 3257 .flags = FL_BASE2|FL_BASE_BARS, 3258 .num_ports = 4, 3259 .base_baud = 115200, 3260 .uart_offset = 8, 3261 }, 3262 3263 [pbn_b2_bt_2_921600] = { 3264 .flags = FL_BASE2|FL_BASE_BARS, 3265 .num_ports = 2, 3266 .base_baud = 921600, 3267 .uart_offset = 8, 3268 }, 3269 [pbn_b2_bt_4_921600] = { 3270 .flags = FL_BASE2|FL_BASE_BARS, 3271 .num_ports = 4, 3272 .base_baud = 921600, 3273 .uart_offset = 8, 3274 }, 3275 3276 [pbn_b3_2_115200] = { 3277 .flags = FL_BASE3, 3278 .num_ports = 2, 3279 .base_baud = 115200, 3280 .uart_offset = 8, 3281 }, 3282 [pbn_b3_4_115200] = { 3283 .flags = FL_BASE3, 3284 .num_ports = 4, 3285 .base_baud = 115200, 3286 .uart_offset = 8, 3287 }, 3288 [pbn_b3_8_115200] = { 3289 .flags = FL_BASE3, 3290 .num_ports = 8, 3291 .base_baud = 115200, 3292 .uart_offset = 8, 3293 }, 3294 3295 [pbn_b4_bt_2_921600] = { 3296 .flags = FL_BASE4, 3297 .num_ports = 2, 3298 .base_baud = 921600, 3299 .uart_offset = 8, 3300 }, 3301 [pbn_b4_bt_4_921600] = { 3302 .flags = FL_BASE4, 3303 .num_ports = 4, 3304 .base_baud = 921600, 3305 .uart_offset = 8, 3306 }, 3307 [pbn_b4_bt_8_921600] = { 3308 .flags = FL_BASE4, 3309 .num_ports = 8, 3310 .base_baud = 921600, 3311 .uart_offset = 8, 3312 }, 3313 3314 /* 3315 * Entries following this are board-specific. 3316 */ 3317 3318 /* 3319 * Panacom - IOMEM 3320 */ 3321 [pbn_panacom] = { 3322 .flags = FL_BASE2, 3323 .num_ports = 2, 3324 .base_baud = 921600, 3325 .uart_offset = 0x400, 3326 .reg_shift = 7, 3327 }, 3328 [pbn_panacom2] = { 3329 .flags = FL_BASE2|FL_BASE_BARS, 3330 .num_ports = 2, 3331 .base_baud = 921600, 3332 .uart_offset = 0x400, 3333 .reg_shift = 7, 3334 }, 3335 [pbn_panacom4] = { 3336 .flags = FL_BASE2|FL_BASE_BARS, 3337 .num_ports = 4, 3338 .base_baud = 921600, 3339 .uart_offset = 0x400, 3340 .reg_shift = 7, 3341 }, 3342 3343 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3344 [pbn_plx_romulus] = { 3345 .flags = FL_BASE2, 3346 .num_ports = 4, 3347 .base_baud = 921600, 3348 .uart_offset = 8 << 2, 3349 .reg_shift = 2, 3350 .first_offset = 0x03, 3351 }, 3352 3353 /* 3354 * This board uses the size of PCI Base region 0 to 3355 * signal now many ports are available 3356 */ 3357 [pbn_oxsemi] = { 3358 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3359 .num_ports = 32, 3360 .base_baud = 115200, 3361 .uart_offset = 8, 3362 }, 3363 [pbn_oxsemi_1_15625000] = { 3364 .flags = FL_BASE0, 3365 .num_ports = 1, 3366 .base_baud = 15625000, 3367 .uart_offset = 0x200, 3368 .first_offset = 0x1000, 3369 }, 3370 [pbn_oxsemi_2_15625000] = { 3371 .flags = FL_BASE0, 3372 .num_ports = 2, 3373 .base_baud = 15625000, 3374 .uart_offset = 0x200, 3375 .first_offset = 0x1000, 3376 }, 3377 [pbn_oxsemi_4_15625000] = { 3378 .flags = FL_BASE0, 3379 .num_ports = 4, 3380 .base_baud = 15625000, 3381 .uart_offset = 0x200, 3382 .first_offset = 0x1000, 3383 }, 3384 [pbn_oxsemi_8_15625000] = { 3385 .flags = FL_BASE0, 3386 .num_ports = 8, 3387 .base_baud = 15625000, 3388 .uart_offset = 0x200, 3389 .first_offset = 0x1000, 3390 }, 3391 3392 3393 /* 3394 * EKF addition for i960 Boards form EKF with serial port. 3395 * Max 256 ports. 3396 */ 3397 [pbn_intel_i960] = { 3398 .flags = FL_BASE0, 3399 .num_ports = 32, 3400 .base_baud = 921600, 3401 .uart_offset = 8 << 2, 3402 .reg_shift = 2, 3403 .first_offset = 0x10000, 3404 }, 3405 [pbn_sgi_ioc3] = { 3406 .flags = FL_BASE0|FL_NOIRQ, 3407 .num_ports = 1, 3408 .base_baud = 458333, 3409 .uart_offset = 8, 3410 .reg_shift = 0, 3411 .first_offset = 0x20178, 3412 }, 3413 3414 /* 3415 * Computone - uses IOMEM. 3416 */ 3417 [pbn_computone_4] = { 3418 .flags = FL_BASE0, 3419 .num_ports = 4, 3420 .base_baud = 921600, 3421 .uart_offset = 0x40, 3422 .reg_shift = 2, 3423 .first_offset = 0x200, 3424 }, 3425 [pbn_computone_6] = { 3426 .flags = FL_BASE0, 3427 .num_ports = 6, 3428 .base_baud = 921600, 3429 .uart_offset = 0x40, 3430 .reg_shift = 2, 3431 .first_offset = 0x200, 3432 }, 3433 [pbn_computone_8] = { 3434 .flags = FL_BASE0, 3435 .num_ports = 8, 3436 .base_baud = 921600, 3437 .uart_offset = 0x40, 3438 .reg_shift = 2, 3439 .first_offset = 0x200, 3440 }, 3441 [pbn_sbsxrsio] = { 3442 .flags = FL_BASE0, 3443 .num_ports = 8, 3444 .base_baud = 460800, 3445 .uart_offset = 256, 3446 .reg_shift = 4, 3447 }, 3448 /* 3449 * PA Semi PWRficient PA6T-1682M on-chip UART 3450 */ 3451 [pbn_pasemi_1682M] = { 3452 .flags = FL_BASE0, 3453 .num_ports = 1, 3454 .base_baud = 8333333, 3455 }, 3456 /* 3457 * National Instruments 843x 3458 */ 3459 [pbn_ni8430_16] = { 3460 .flags = FL_BASE0, 3461 .num_ports = 16, 3462 .base_baud = 3686400, 3463 .uart_offset = 0x10, 3464 .first_offset = 0x800, 3465 }, 3466 [pbn_ni8430_8] = { 3467 .flags = FL_BASE0, 3468 .num_ports = 8, 3469 .base_baud = 3686400, 3470 .uart_offset = 0x10, 3471 .first_offset = 0x800, 3472 }, 3473 [pbn_ni8430_4] = { 3474 .flags = FL_BASE0, 3475 .num_ports = 4, 3476 .base_baud = 3686400, 3477 .uart_offset = 0x10, 3478 .first_offset = 0x800, 3479 }, 3480 [pbn_ni8430_2] = { 3481 .flags = FL_BASE0, 3482 .num_ports = 2, 3483 .base_baud = 3686400, 3484 .uart_offset = 0x10, 3485 .first_offset = 0x800, 3486 }, 3487 /* 3488 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3489 */ 3490 [pbn_ADDIDATA_PCIe_1_3906250] = { 3491 .flags = FL_BASE0, 3492 .num_ports = 1, 3493 .base_baud = 3906250, 3494 .uart_offset = 0x200, 3495 .first_offset = 0x1000, 3496 }, 3497 [pbn_ADDIDATA_PCIe_2_3906250] = { 3498 .flags = FL_BASE0, 3499 .num_ports = 2, 3500 .base_baud = 3906250, 3501 .uart_offset = 0x200, 3502 .first_offset = 0x1000, 3503 }, 3504 [pbn_ADDIDATA_PCIe_4_3906250] = { 3505 .flags = FL_BASE0, 3506 .num_ports = 4, 3507 .base_baud = 3906250, 3508 .uart_offset = 0x200, 3509 .first_offset = 0x1000, 3510 }, 3511 [pbn_ADDIDATA_PCIe_8_3906250] = { 3512 .flags = FL_BASE0, 3513 .num_ports = 8, 3514 .base_baud = 3906250, 3515 .uart_offset = 0x200, 3516 .first_offset = 0x1000, 3517 }, 3518 [pbn_ce4100_1_115200] = { 3519 .flags = FL_BASE_BARS, 3520 .num_ports = 2, 3521 .base_baud = 921600, 3522 .reg_shift = 2, 3523 }, 3524 [pbn_omegapci] = { 3525 .flags = FL_BASE0, 3526 .num_ports = 8, 3527 .base_baud = 115200, 3528 .uart_offset = 0x200, 3529 }, 3530 [pbn_NETMOS9900_2s_115200] = { 3531 .flags = FL_BASE0, 3532 .num_ports = 2, 3533 .base_baud = 115200, 3534 }, 3535 [pbn_brcm_trumanage] = { 3536 .flags = FL_BASE0, 3537 .num_ports = 1, 3538 .reg_shift = 2, 3539 .base_baud = 115200, 3540 }, 3541 [pbn_fintek_4] = { 3542 .num_ports = 4, 3543 .uart_offset = 8, 3544 .base_baud = 115200, 3545 .first_offset = 0x40, 3546 }, 3547 [pbn_fintek_8] = { 3548 .num_ports = 8, 3549 .uart_offset = 8, 3550 .base_baud = 115200, 3551 .first_offset = 0x40, 3552 }, 3553 [pbn_fintek_12] = { 3554 .num_ports = 12, 3555 .uart_offset = 8, 3556 .base_baud = 115200, 3557 .first_offset = 0x40, 3558 }, 3559 [pbn_fintek_F81504A] = { 3560 .num_ports = 4, 3561 .uart_offset = 8, 3562 .base_baud = 115200, 3563 }, 3564 [pbn_fintek_F81508A] = { 3565 .num_ports = 8, 3566 .uart_offset = 8, 3567 .base_baud = 115200, 3568 }, 3569 [pbn_fintek_F81512A] = { 3570 .num_ports = 12, 3571 .uart_offset = 8, 3572 .base_baud = 115200, 3573 }, 3574 [pbn_wch382_2] = { 3575 .flags = FL_BASE0, 3576 .num_ports = 2, 3577 .base_baud = 115200, 3578 .uart_offset = 8, 3579 .first_offset = 0xC0, 3580 }, 3581 [pbn_wch384_4] = { 3582 .flags = FL_BASE0, 3583 .num_ports = 4, 3584 .base_baud = 115200, 3585 .uart_offset = 8, 3586 .first_offset = 0xC0, 3587 }, 3588 [pbn_wch384_8] = { 3589 .flags = FL_BASE0, 3590 .num_ports = 8, 3591 .base_baud = 115200, 3592 .uart_offset = 8, 3593 .first_offset = 0x00, 3594 }, 3595 [pbn_sunix_pci_1s] = { 3596 .num_ports = 1, 3597 .base_baud = 921600, 3598 .uart_offset = 0x8, 3599 }, 3600 [pbn_sunix_pci_2s] = { 3601 .num_ports = 2, 3602 .base_baud = 921600, 3603 .uart_offset = 0x8, 3604 }, 3605 [pbn_sunix_pci_4s] = { 3606 .num_ports = 4, 3607 .base_baud = 921600, 3608 .uart_offset = 0x8, 3609 }, 3610 [pbn_sunix_pci_8s] = { 3611 .num_ports = 8, 3612 .base_baud = 921600, 3613 .uart_offset = 0x8, 3614 }, 3615 [pbn_sunix_pci_16s] = { 3616 .num_ports = 16, 3617 .base_baud = 921600, 3618 .uart_offset = 0x8, 3619 }, 3620 [pbn_titan_1_4000000] = { 3621 .flags = FL_BASE0, 3622 .num_ports = 1, 3623 .base_baud = 4000000, 3624 .uart_offset = 0x200, 3625 .first_offset = 0x1000, 3626 }, 3627 [pbn_titan_2_4000000] = { 3628 .flags = FL_BASE0, 3629 .num_ports = 2, 3630 .base_baud = 4000000, 3631 .uart_offset = 0x200, 3632 .first_offset = 0x1000, 3633 }, 3634 [pbn_titan_4_4000000] = { 3635 .flags = FL_BASE0, 3636 .num_ports = 4, 3637 .base_baud = 4000000, 3638 .uart_offset = 0x200, 3639 .first_offset = 0x1000, 3640 }, 3641 [pbn_titan_8_4000000] = { 3642 .flags = FL_BASE0, 3643 .num_ports = 8, 3644 .base_baud = 4000000, 3645 .uart_offset = 0x200, 3646 .first_offset = 0x1000, 3647 }, 3648 [pbn_moxa8250_2p] = { 3649 .flags = FL_BASE1, 3650 .num_ports = 2, 3651 .base_baud = 921600, 3652 .uart_offset = 0x200, 3653 }, 3654 [pbn_moxa8250_4p] = { 3655 .flags = FL_BASE1, 3656 .num_ports = 4, 3657 .base_baud = 921600, 3658 .uart_offset = 0x200, 3659 }, 3660 [pbn_moxa8250_8p] = { 3661 .flags = FL_BASE1, 3662 .num_ports = 8, 3663 .base_baud = 921600, 3664 .uart_offset = 0x200, 3665 }, 3666 }; 3667 3668 #define REPORT_CONFIG(option) \ 3669 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3670 #define REPORT_8250_CONFIG(option) \ 3671 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3672 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3673 3674 static const struct pci_device_id blacklist[] = { 3675 /* softmodems */ 3676 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3677 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3678 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3679 3680 /* multi-io cards handled by parport_serial */ 3681 /* WCH CH353 2S1P */ 3682 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3683 /* WCH CH353 1S1P */ 3684 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3685 /* WCH CH382 2S1P */ 3686 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3687 3688 /* Intel platforms with MID UART */ 3689 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3690 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3691 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3692 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3693 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3694 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3695 3696 /* Intel platforms with DesignWare UART */ 3697 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3698 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3699 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3700 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3701 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3702 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3703 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3704 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3705 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3706 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3707 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3708 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3709 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3710 3711 /* Exar devices */ 3712 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3713 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3714 3715 /* Pericom devices */ 3716 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3717 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3718 3719 /* End of the black list */ 3720 { } 3721 }; 3722 3723 static int serial_pci_is_class_communication(struct pci_dev *dev) 3724 { 3725 /* 3726 * If it is not a communications device or the programming 3727 * interface is greater than 6, give up. 3728 */ 3729 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3730 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3731 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3732 (dev->class & 0xff) > 6) 3733 return -ENODEV; 3734 3735 return 0; 3736 } 3737 3738 /* 3739 * Given a complete unknown PCI device, try to use some heuristics to 3740 * guess what the configuration might be, based on the pitiful PCI 3741 * serial specs. Returns 0 on success, -ENODEV on failure. 3742 */ 3743 static int 3744 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3745 { 3746 int num_iomem, num_port, first_port = -1, i; 3747 int rc; 3748 3749 rc = serial_pci_is_class_communication(dev); 3750 if (rc) 3751 return rc; 3752 3753 /* 3754 * Should we try to make guesses for multiport serial devices later? 3755 */ 3756 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3757 return -ENODEV; 3758 3759 num_iomem = num_port = 0; 3760 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3761 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3762 num_port++; 3763 if (first_port == -1) 3764 first_port = i; 3765 } 3766 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3767 num_iomem++; 3768 } 3769 3770 /* 3771 * If there is 1 or 0 iomem regions, and exactly one port, 3772 * use it. We guess the number of ports based on the IO 3773 * region size. 3774 */ 3775 if (num_iomem <= 1 && num_port == 1) { 3776 board->flags = first_port; 3777 board->num_ports = pci_resource_len(dev, first_port) / 8; 3778 return 0; 3779 } 3780 3781 /* 3782 * Now guess if we've got a board which indexes by BARs. 3783 * Each IO BAR should be 8 bytes, and they should follow 3784 * consecutively. 3785 */ 3786 first_port = -1; 3787 num_port = 0; 3788 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3789 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3790 pci_resource_len(dev, i) == 8 && 3791 (first_port == -1 || (first_port + num_port) == i)) { 3792 num_port++; 3793 if (first_port == -1) 3794 first_port = i; 3795 } 3796 } 3797 3798 if (num_port > 1) { 3799 board->flags = first_port | FL_BASE_BARS; 3800 board->num_ports = num_port; 3801 return 0; 3802 } 3803 3804 return -ENODEV; 3805 } 3806 3807 static inline int 3808 serial_pci_matches(const struct pciserial_board *board, 3809 const struct pciserial_board *guessed) 3810 { 3811 return 3812 board->num_ports == guessed->num_ports && 3813 board->base_baud == guessed->base_baud && 3814 board->uart_offset == guessed->uart_offset && 3815 board->reg_shift == guessed->reg_shift && 3816 board->first_offset == guessed->first_offset; 3817 } 3818 3819 struct serial_private * 3820 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3821 { 3822 struct uart_8250_port uart; 3823 struct serial_private *priv; 3824 struct pci_serial_quirk *quirk; 3825 int rc, nr_ports, i; 3826 3827 nr_ports = board->num_ports; 3828 3829 /* 3830 * Find an init and setup quirks. 3831 */ 3832 quirk = find_quirk(dev); 3833 3834 /* 3835 * Run the new-style initialization function. 3836 * The initialization function returns: 3837 * <0 - error 3838 * 0 - use board->num_ports 3839 * >0 - number of ports 3840 */ 3841 if (quirk->init) { 3842 rc = quirk->init(dev); 3843 if (rc < 0) { 3844 priv = ERR_PTR(rc); 3845 goto err_out; 3846 } 3847 if (rc) 3848 nr_ports = rc; 3849 } 3850 3851 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3852 if (!priv) { 3853 priv = ERR_PTR(-ENOMEM); 3854 goto err_deinit; 3855 } 3856 3857 priv->dev = dev; 3858 priv->quirk = quirk; 3859 3860 memset(&uart, 0, sizeof(uart)); 3861 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3862 uart.port.uartclk = board->base_baud * 16; 3863 3864 if (board->flags & FL_NOIRQ) { 3865 uart.port.irq = 0; 3866 } else { 3867 if (pci_match_id(pci_use_msi, dev)) { 3868 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3869 pci_set_master(dev); 3870 uart.port.flags &= ~UPF_SHARE_IRQ; 3871 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3872 } else { 3873 pci_dbg(dev, "Using legacy interrupts\n"); 3874 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3875 } 3876 if (rc < 0) { 3877 kfree(priv); 3878 priv = ERR_PTR(rc); 3879 goto err_deinit; 3880 } 3881 3882 uart.port.irq = pci_irq_vector(dev, 0); 3883 } 3884 3885 uart.port.dev = &dev->dev; 3886 3887 for (i = 0; i < nr_ports; i++) { 3888 if (quirk->setup(priv, board, &uart, i)) 3889 break; 3890 3891 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3892 uart.port.iobase, uart.port.irq, uart.port.iotype); 3893 3894 priv->line[i] = serial8250_register_8250_port(&uart); 3895 if (priv->line[i] < 0) { 3896 pci_err(dev, 3897 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3898 uart.port.iobase, uart.port.irq, 3899 uart.port.iotype, priv->line[i]); 3900 break; 3901 } 3902 } 3903 priv->nr = i; 3904 priv->board = board; 3905 return priv; 3906 3907 err_deinit: 3908 if (quirk->exit) 3909 quirk->exit(dev); 3910 err_out: 3911 return priv; 3912 } 3913 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3914 3915 static void pciserial_detach_ports(struct serial_private *priv) 3916 { 3917 struct pci_serial_quirk *quirk; 3918 int i; 3919 3920 for (i = 0; i < priv->nr; i++) 3921 serial8250_unregister_port(priv->line[i]); 3922 3923 /* 3924 * Find the exit quirks. 3925 */ 3926 quirk = find_quirk(priv->dev); 3927 if (quirk->exit) 3928 quirk->exit(priv->dev); 3929 } 3930 3931 void pciserial_remove_ports(struct serial_private *priv) 3932 { 3933 pciserial_detach_ports(priv); 3934 kfree(priv); 3935 } 3936 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3937 3938 void pciserial_suspend_ports(struct serial_private *priv) 3939 { 3940 int i; 3941 3942 for (i = 0; i < priv->nr; i++) 3943 if (priv->line[i] >= 0) 3944 serial8250_suspend_port(priv->line[i]); 3945 3946 /* 3947 * Ensure that every init quirk is properly torn down 3948 */ 3949 if (priv->quirk->exit) 3950 priv->quirk->exit(priv->dev); 3951 } 3952 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3953 3954 void pciserial_resume_ports(struct serial_private *priv) 3955 { 3956 int i; 3957 3958 /* 3959 * Ensure that the board is correctly configured. 3960 */ 3961 if (priv->quirk->init) 3962 priv->quirk->init(priv->dev); 3963 3964 for (i = 0; i < priv->nr; i++) 3965 if (priv->line[i] >= 0) 3966 serial8250_resume_port(priv->line[i]); 3967 } 3968 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3969 3970 /* 3971 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3972 * to the arrangement of serial ports on a PCI card. 3973 */ 3974 static int 3975 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3976 { 3977 struct pci_serial_quirk *quirk; 3978 struct serial_private *priv; 3979 const struct pciserial_board *board; 3980 const struct pci_device_id *exclude; 3981 struct pciserial_board tmp; 3982 int rc; 3983 3984 quirk = find_quirk(dev); 3985 if (quirk->probe) { 3986 rc = quirk->probe(dev); 3987 if (rc) 3988 return rc; 3989 } 3990 3991 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3992 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 3993 return -EINVAL; 3994 } 3995 3996 board = &pci_boards[ent->driver_data]; 3997 3998 exclude = pci_match_id(blacklist, dev); 3999 if (exclude) { 4000 if (exclude->driver_data) 4001 pci_warn(dev, "ignoring port, enable %s to handle\n", 4002 (const char *)exclude->driver_data); 4003 return -ENODEV; 4004 } 4005 4006 rc = pcim_enable_device(dev); 4007 pci_save_state(dev); 4008 if (rc) 4009 return rc; 4010 4011 if (ent->driver_data == pbn_default) { 4012 /* 4013 * Use a copy of the pci_board entry for this; 4014 * avoid changing entries in the table. 4015 */ 4016 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4017 board = &tmp; 4018 4019 /* 4020 * We matched one of our class entries. Try to 4021 * determine the parameters of this board. 4022 */ 4023 rc = serial_pci_guess_board(dev, &tmp); 4024 if (rc) 4025 return rc; 4026 } else { 4027 /* 4028 * We matched an explicit entry. If we are able to 4029 * detect this boards settings with our heuristic, 4030 * then we no longer need this entry. 4031 */ 4032 memcpy(&tmp, &pci_boards[pbn_default], 4033 sizeof(struct pciserial_board)); 4034 rc = serial_pci_guess_board(dev, &tmp); 4035 if (rc == 0 && serial_pci_matches(board, &tmp)) 4036 moan_device("Redundant entry in serial pci_table.", 4037 dev); 4038 } 4039 4040 priv = pciserial_init_ports(dev, board); 4041 if (IS_ERR(priv)) 4042 return PTR_ERR(priv); 4043 4044 pci_set_drvdata(dev, priv); 4045 return 0; 4046 } 4047 4048 static void pciserial_remove_one(struct pci_dev *dev) 4049 { 4050 struct serial_private *priv = pci_get_drvdata(dev); 4051 4052 pciserial_remove_ports(priv); 4053 } 4054 4055 #ifdef CONFIG_PM_SLEEP 4056 static int pciserial_suspend_one(struct device *dev) 4057 { 4058 struct serial_private *priv = dev_get_drvdata(dev); 4059 4060 if (priv) 4061 pciserial_suspend_ports(priv); 4062 4063 return 0; 4064 } 4065 4066 static int pciserial_resume_one(struct device *dev) 4067 { 4068 struct pci_dev *pdev = to_pci_dev(dev); 4069 struct serial_private *priv = pci_get_drvdata(pdev); 4070 int err; 4071 4072 if (priv) { 4073 /* 4074 * The device may have been disabled. Re-enable it. 4075 */ 4076 err = pci_enable_device(pdev); 4077 /* FIXME: We cannot simply error out here */ 4078 if (err) 4079 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4080 pciserial_resume_ports(priv); 4081 } 4082 return 0; 4083 } 4084 #endif 4085 4086 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4087 pciserial_resume_one); 4088 4089 static const struct pci_device_id serial_pci_tbl[] = { 4090 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4091 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID, 0, 0, 4092 pbn_b0_4_921600 }, 4093 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4094 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4095 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4096 pbn_b2_8_921600 }, 4097 /* Advantech also use 0x3618 and 0xf618 */ 4098 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4099 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4100 pbn_b0_4_921600 }, 4101 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4102 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4103 pbn_b0_4_921600 }, 4104 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4105 PCI_SUBVENDOR_ID_CONNECT_TECH, 4106 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4107 pbn_b1_8_1382400 }, 4108 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4109 PCI_SUBVENDOR_ID_CONNECT_TECH, 4110 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4111 pbn_b1_4_1382400 }, 4112 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4113 PCI_SUBVENDOR_ID_CONNECT_TECH, 4114 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4115 pbn_b1_2_1382400 }, 4116 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4117 PCI_SUBVENDOR_ID_CONNECT_TECH, 4118 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4119 pbn_b1_8_1382400 }, 4120 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4121 PCI_SUBVENDOR_ID_CONNECT_TECH, 4122 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4123 pbn_b1_4_1382400 }, 4124 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4125 PCI_SUBVENDOR_ID_CONNECT_TECH, 4126 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4127 pbn_b1_2_1382400 }, 4128 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4129 PCI_SUBVENDOR_ID_CONNECT_TECH, 4130 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4131 pbn_b1_8_921600 }, 4132 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4133 PCI_SUBVENDOR_ID_CONNECT_TECH, 4134 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4135 pbn_b1_8_921600 }, 4136 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4137 PCI_SUBVENDOR_ID_CONNECT_TECH, 4138 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4139 pbn_b1_4_921600 }, 4140 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4141 PCI_SUBVENDOR_ID_CONNECT_TECH, 4142 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4143 pbn_b1_4_921600 }, 4144 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4145 PCI_SUBVENDOR_ID_CONNECT_TECH, 4146 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4147 pbn_b1_2_921600 }, 4148 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4149 PCI_SUBVENDOR_ID_CONNECT_TECH, 4150 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4151 pbn_b1_8_921600 }, 4152 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4153 PCI_SUBVENDOR_ID_CONNECT_TECH, 4154 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4155 pbn_b1_8_921600 }, 4156 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4157 PCI_SUBVENDOR_ID_CONNECT_TECH, 4158 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4159 pbn_b1_4_921600 }, 4160 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4161 PCI_SUBVENDOR_ID_CONNECT_TECH, 4162 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4163 pbn_b1_2_1250000 }, 4164 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4165 PCI_SUBVENDOR_ID_CONNECT_TECH, 4166 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4167 pbn_b0_2_1843200 }, 4168 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4169 PCI_SUBVENDOR_ID_CONNECT_TECH, 4170 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4171 pbn_b0_4_1843200 }, 4172 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4173 PCI_VENDOR_ID_AFAVLAB, 4174 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4175 pbn_b0_4_1152000 }, 4176 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4178 pbn_b2_bt_1_115200 }, 4179 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4181 pbn_b2_bt_2_115200 }, 4182 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4184 pbn_b2_bt_4_115200 }, 4185 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4187 pbn_b2_bt_2_115200 }, 4188 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4190 pbn_b2_bt_4_115200 }, 4191 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4193 pbn_b2_8_115200 }, 4194 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b2_8_460800 }, 4197 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4199 pbn_b2_8_115200 }, 4200 4201 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4203 pbn_b2_bt_2_115200 }, 4204 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4206 pbn_b2_bt_2_921600 }, 4207 /* 4208 * VScom SPCOM800, from sl@s.pl 4209 */ 4210 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4212 pbn_b2_8_921600 }, 4213 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4215 pbn_b2_4_921600 }, 4216 /* Unknown card - subdevice 0x1584 */ 4217 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4218 PCI_VENDOR_ID_PLX, 4219 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4220 pbn_b2_4_115200 }, 4221 /* Unknown card - subdevice 0x1588 */ 4222 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4223 PCI_VENDOR_ID_PLX, 4224 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4225 pbn_b2_8_115200 }, 4226 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4227 PCI_SUBVENDOR_ID_KEYSPAN, 4228 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4229 pbn_panacom }, 4230 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4232 pbn_panacom4 }, 4233 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4235 pbn_panacom2 }, 4236 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4237 PCI_VENDOR_ID_ESDGMBH, 4238 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4239 pbn_b2_4_115200 }, 4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4241 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4242 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4243 pbn_b2_4_460800 }, 4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4245 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4246 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4247 pbn_b2_8_460800 }, 4248 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4249 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4250 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4251 pbn_b2_16_460800 }, 4252 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4253 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4254 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4255 pbn_b2_16_460800 }, 4256 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4257 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4258 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4259 pbn_b2_4_460800 }, 4260 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4261 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4262 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4263 pbn_b2_8_460800 }, 4264 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4265 PCI_SUBVENDOR_ID_EXSYS, 4266 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4267 pbn_b2_4_115200 }, 4268 /* 4269 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4270 * (Exoray@isys.ca) 4271 */ 4272 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4273 0x10b5, 0x106a, 0, 0, 4274 pbn_plx_romulus }, 4275 /* 4276 * Quatech cards. These actually have configurable clocks but for 4277 * now we just use the default. 4278 * 4279 * 100 series are RS232, 200 series RS422, 4280 */ 4281 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4283 pbn_b1_4_115200 }, 4284 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4286 pbn_b1_2_115200 }, 4287 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_b2_2_115200 }, 4290 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4292 pbn_b1_2_115200 }, 4293 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4295 pbn_b2_2_115200 }, 4296 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_b1_4_115200 }, 4299 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_b1_8_115200 }, 4302 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_b1_8_115200 }, 4305 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_b1_4_115200 }, 4308 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_b1_2_115200 }, 4311 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_b1_4_115200 }, 4314 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_b1_2_115200 }, 4317 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_b2_4_115200 }, 4320 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_b2_2_115200 }, 4323 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_b2_1_115200 }, 4326 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_b2_4_115200 }, 4329 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_b2_2_115200 }, 4332 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_b2_1_115200 }, 4335 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_b0_8_115200 }, 4338 4339 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4340 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4341 0, 0, 4342 pbn_b0_4_921600 }, 4343 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4344 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4345 0, 0, 4346 pbn_b0_4_1152000 }, 4347 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4349 pbn_b0_bt_2_921600 }, 4350 4351 /* 4352 * The below card is a little controversial since it is the 4353 * subject of a PCI vendor/device ID clash. (See 4354 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4355 * For now just used the hex ID 0x950a. 4356 */ 4357 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4358 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4359 0, 0, pbn_b0_2_115200 }, 4360 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4361 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4362 0, 0, pbn_b0_2_115200 }, 4363 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4365 pbn_b0_2_1130000 }, 4366 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4367 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4368 pbn_b0_1_921600 }, 4369 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4371 pbn_b0_4_115200 }, 4372 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4374 pbn_b0_bt_2_921600 }, 4375 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4377 pbn_b2_8_1152000 }, 4378 4379 /* 4380 * Oxford Semiconductor Inc. Tornado PCI express device range. 4381 */ 4382 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4384 pbn_b0_1_15625000 }, 4385 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4387 pbn_b0_1_15625000 }, 4388 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_oxsemi_1_15625000 }, 4391 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4393 pbn_oxsemi_1_15625000 }, 4394 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4396 pbn_b0_1_15625000 }, 4397 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4399 pbn_b0_1_15625000 }, 4400 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4402 pbn_oxsemi_1_15625000 }, 4403 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4405 pbn_oxsemi_1_15625000 }, 4406 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4408 pbn_b0_1_15625000 }, 4409 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4411 pbn_b0_1_15625000 }, 4412 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4414 pbn_b0_1_15625000 }, 4415 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4417 pbn_b0_1_15625000 }, 4418 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4420 pbn_oxsemi_2_15625000 }, 4421 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4423 pbn_oxsemi_2_15625000 }, 4424 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4426 pbn_oxsemi_4_15625000 }, 4427 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4429 pbn_oxsemi_4_15625000 }, 4430 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4432 pbn_oxsemi_8_15625000 }, 4433 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4435 pbn_oxsemi_8_15625000 }, 4436 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4438 pbn_oxsemi_1_15625000 }, 4439 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4441 pbn_oxsemi_1_15625000 }, 4442 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4444 pbn_oxsemi_1_15625000 }, 4445 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4447 pbn_oxsemi_1_15625000 }, 4448 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4449 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4450 pbn_oxsemi_1_15625000 }, 4451 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4452 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4453 pbn_oxsemi_1_15625000 }, 4454 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4455 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4456 pbn_oxsemi_1_15625000 }, 4457 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4458 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4459 pbn_oxsemi_1_15625000 }, 4460 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_oxsemi_1_15625000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_oxsemi_1_15625000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_1_15625000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_15625000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_oxsemi_1_15625000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_oxsemi_1_15625000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_15625000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_15625000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_oxsemi_1_15625000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_oxsemi_1_15625000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_oxsemi_1_15625000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_oxsemi_1_15625000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_1_15625000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_1_15625000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_1_15625000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_1_15625000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_1_15625000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_1_15625000 }, 4514 /* 4515 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4516 */ 4517 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4518 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4519 pbn_oxsemi_1_15625000 }, 4520 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4521 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4522 pbn_oxsemi_2_15625000 }, 4523 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4524 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4525 pbn_oxsemi_4_15625000 }, 4526 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4527 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4528 pbn_oxsemi_8_15625000 }, 4529 4530 /* 4531 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4532 */ 4533 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4534 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4535 pbn_oxsemi_2_15625000 }, 4536 /* 4537 * EndRun Technologies. PCI express device range. 4538 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4539 */ 4540 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4542 pbn_oxsemi_2_15625000 }, 4543 4544 /* 4545 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4546 * from skokodyn@yahoo.com 4547 */ 4548 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4549 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4550 pbn_sbsxrsio }, 4551 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4552 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4553 pbn_sbsxrsio }, 4554 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4555 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4556 pbn_sbsxrsio }, 4557 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4558 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4559 pbn_sbsxrsio }, 4560 4561 /* 4562 * Digitan DS560-558, from jimd@esoft.com 4563 */ 4564 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4566 pbn_b1_1_115200 }, 4567 4568 /* 4569 * Titan Electronic cards 4570 * The 400L and 800L have a custom setup quirk. 4571 */ 4572 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4574 pbn_b0_1_921600 }, 4575 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4577 pbn_b0_2_921600 }, 4578 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4580 pbn_b0_4_921600 }, 4581 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_b0_4_921600 }, 4584 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4586 pbn_b1_1_921600 }, 4587 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4589 pbn_b1_bt_2_921600 }, 4590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_b0_bt_4_921600 }, 4593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_b0_bt_8_921600 }, 4596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b4_bt_2_921600 }, 4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b4_bt_4_921600 }, 4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b4_bt_8_921600 }, 4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b0_4_921600 }, 4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b0_4_921600 }, 4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b0_4_921600 }, 4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_titan_1_4000000 }, 4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_titan_2_4000000 }, 4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_titan_4_4000000 }, 4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_titan_8_4000000 }, 4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_titan_2_4000000 }, 4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_titan_2_4000000 }, 4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_b0_bt_2_921600 }, 4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b0_4_921600 }, 4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_b0_4_921600 }, 4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_b0_4_921600 }, 4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_b0_4_921600 }, 4647 4648 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4650 pbn_b2_1_460800 }, 4651 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4653 pbn_b2_1_460800 }, 4654 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4656 pbn_b2_1_460800 }, 4657 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4659 pbn_b2_bt_2_921600 }, 4660 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4662 pbn_b2_bt_2_921600 }, 4663 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4665 pbn_b2_bt_2_921600 }, 4666 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_b2_bt_4_921600 }, 4669 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_b2_bt_4_921600 }, 4672 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_b2_bt_4_921600 }, 4675 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b0_1_921600 }, 4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b0_1_921600 }, 4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_b0_1_921600 }, 4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b0_bt_2_921600 }, 4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b0_bt_2_921600 }, 4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_b0_bt_2_921600 }, 4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b0_bt_4_921600 }, 4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b0_bt_4_921600 }, 4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b0_bt_4_921600 }, 4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b0_bt_8_921600 }, 4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_bt_8_921600 }, 4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_b0_bt_8_921600 }, 4711 4712 /* 4713 * Computone devices submitted by Doug McNash dmcnash@computone.com 4714 */ 4715 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4716 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4717 0, 0, pbn_computone_4 }, 4718 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4719 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4720 0, 0, pbn_computone_8 }, 4721 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4722 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4723 0, 0, pbn_computone_6 }, 4724 4725 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_oxsemi }, 4728 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4729 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4730 pbn_b0_bt_1_921600 }, 4731 4732 /* 4733 * Sunix PCI serial boards 4734 */ 4735 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4736 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4737 pbn_sunix_pci_1s }, 4738 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4739 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4740 pbn_sunix_pci_2s }, 4741 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4742 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4743 pbn_sunix_pci_4s }, 4744 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4745 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4746 pbn_sunix_pci_4s }, 4747 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4748 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4749 pbn_sunix_pci_8s }, 4750 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4751 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4752 pbn_sunix_pci_8s }, 4753 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4754 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4755 pbn_sunix_pci_16s }, 4756 4757 /* 4758 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4759 */ 4760 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4762 pbn_b0_bt_8_115200 }, 4763 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4765 pbn_b0_bt_8_115200 }, 4766 4767 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4769 pbn_b0_bt_2_115200 }, 4770 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4772 pbn_b0_bt_2_115200 }, 4773 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4775 pbn_b0_bt_2_115200 }, 4776 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4778 pbn_b0_bt_2_115200 }, 4779 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4781 pbn_b0_bt_2_115200 }, 4782 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4784 pbn_b0_bt_4_460800 }, 4785 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4787 pbn_b0_bt_4_460800 }, 4788 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4790 pbn_b0_bt_2_460800 }, 4791 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4793 pbn_b0_bt_2_460800 }, 4794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_b0_bt_2_460800 }, 4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_b0_bt_1_115200 }, 4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4802 pbn_b0_bt_1_460800 }, 4803 4804 /* 4805 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4806 * Cards are identified by their subsystem vendor IDs, which 4807 * (in hex) match the model number. 4808 * 4809 * Note that JC140x are RS422/485 cards which require ox950 4810 * ACR = 0x10, and as such are not currently fully supported. 4811 */ 4812 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4813 0x1204, 0x0004, 0, 0, 4814 pbn_b0_4_921600 }, 4815 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4816 0x1208, 0x0004, 0, 0, 4817 pbn_b0_4_921600 }, 4818 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4819 0x1402, 0x0002, 0, 0, 4820 pbn_b0_2_921600 }, */ 4821 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4822 0x1404, 0x0004, 0, 0, 4823 pbn_b0_4_921600 }, */ 4824 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4825 0x1208, 0x0004, 0, 0, 4826 pbn_b0_4_921600 }, 4827 4828 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4829 0x1204, 0x0004, 0, 0, 4830 pbn_b0_4_921600 }, 4831 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4832 0x1208, 0x0004, 0, 0, 4833 pbn_b0_4_921600 }, 4834 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4835 0x1208, 0x0004, 0, 0, 4836 pbn_b0_4_921600 }, 4837 /* 4838 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4839 */ 4840 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4842 pbn_b1_1_1382400 }, 4843 4844 /* 4845 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4846 */ 4847 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4849 pbn_b1_1_1382400 }, 4850 4851 /* 4852 * RAStel 2 port modem, gerg@moreton.com.au 4853 */ 4854 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4855 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4856 pbn_b2_bt_2_115200 }, 4857 4858 /* 4859 * EKF addition for i960 Boards form EKF with serial port 4860 */ 4861 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4862 0xE4BF, PCI_ANY_ID, 0, 0, 4863 pbn_intel_i960 }, 4864 4865 /* 4866 * Xircom Cardbus/Ethernet combos 4867 */ 4868 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4870 pbn_b0_1_115200 }, 4871 /* 4872 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4873 */ 4874 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b0_1_115200 }, 4877 4878 /* 4879 * Untested PCI modems, sent in from various folks... 4880 */ 4881 4882 /* 4883 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4884 */ 4885 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4886 0x1048, 0x1500, 0, 0, 4887 pbn_b1_1_115200 }, 4888 4889 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4890 0xFF00, 0, 0, 0, 4891 pbn_sgi_ioc3 }, 4892 4893 /* 4894 * HP Diva card 4895 */ 4896 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4897 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4898 pbn_b1_1_115200 }, 4899 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4901 pbn_b0_5_115200 }, 4902 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4904 pbn_b2_1_115200 }, 4905 /* HPE PCI serial device */ 4906 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4908 pbn_b1_1_115200 }, 4909 4910 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4912 pbn_b3_2_115200 }, 4913 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4915 pbn_b3_4_115200 }, 4916 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4918 pbn_b3_8_115200 }, 4919 /* 4920 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4921 */ 4922 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4924 pbn_b0_1_115200 }, 4925 /* 4926 * ITE 4927 */ 4928 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4929 PCI_ANY_ID, PCI_ANY_ID, 4930 0, 0, 4931 pbn_b1_bt_1_115200 }, 4932 4933 /* 4934 * IntaShield IS-200 4935 */ 4936 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4938 pbn_b2_2_115200 }, 4939 /* 4940 * IntaShield IS-400 4941 */ 4942 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4944 pbn_b2_4_115200 }, 4945 /* Brainboxes Devices */ 4946 /* 4947 * Brainboxes UC-101 4948 */ 4949 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4950 PCI_ANY_ID, PCI_ANY_ID, 4951 0, 0, 4952 pbn_b2_2_115200 }, 4953 /* 4954 * Brainboxes UC-235/246 4955 */ 4956 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4957 PCI_ANY_ID, PCI_ANY_ID, 4958 0, 0, 4959 pbn_b2_1_115200 }, 4960 /* 4961 * Brainboxes UC-257 4962 */ 4963 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4964 PCI_ANY_ID, PCI_ANY_ID, 4965 0, 0, 4966 pbn_b2_2_115200 }, 4967 /* 4968 * Brainboxes UC-260/271/701/756 4969 */ 4970 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4971 PCI_ANY_ID, PCI_ANY_ID, 4972 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4973 pbn_b2_4_115200 }, 4974 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4975 PCI_ANY_ID, PCI_ANY_ID, 4976 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4977 pbn_b2_4_115200 }, 4978 /* 4979 * Brainboxes UC-268 4980 */ 4981 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4982 PCI_ANY_ID, PCI_ANY_ID, 4983 0, 0, 4984 pbn_b2_4_115200 }, 4985 /* 4986 * Brainboxes UC-275/279 4987 */ 4988 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 4989 PCI_ANY_ID, PCI_ANY_ID, 4990 0, 0, 4991 pbn_b2_8_115200 }, 4992 /* 4993 * Brainboxes UC-302 4994 */ 4995 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 4996 PCI_ANY_ID, PCI_ANY_ID, 4997 0, 0, 4998 pbn_b2_2_115200 }, 4999 /* 5000 * Brainboxes UC-310 5001 */ 5002 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5003 PCI_ANY_ID, PCI_ANY_ID, 5004 0, 0, 5005 pbn_b2_2_115200 }, 5006 /* 5007 * Brainboxes UC-313 5008 */ 5009 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5010 PCI_ANY_ID, PCI_ANY_ID, 5011 0, 0, 5012 pbn_b2_2_115200 }, 5013 /* 5014 * Brainboxes UC-320/324 5015 */ 5016 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5017 PCI_ANY_ID, PCI_ANY_ID, 5018 0, 0, 5019 pbn_b2_1_115200 }, 5020 /* 5021 * Brainboxes UC-346 5022 */ 5023 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5024 PCI_ANY_ID, PCI_ANY_ID, 5025 0, 0, 5026 pbn_b2_4_115200 }, 5027 /* 5028 * Brainboxes UC-357 5029 */ 5030 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5031 PCI_ANY_ID, PCI_ANY_ID, 5032 0, 0, 5033 pbn_b2_2_115200 }, 5034 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5035 PCI_ANY_ID, PCI_ANY_ID, 5036 0, 0, 5037 pbn_b2_2_115200 }, 5038 /* 5039 * Brainboxes UC-368 5040 */ 5041 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5042 PCI_ANY_ID, PCI_ANY_ID, 5043 0, 0, 5044 pbn_b2_4_115200 }, 5045 /* 5046 * Brainboxes UC-420/431 5047 */ 5048 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5049 PCI_ANY_ID, PCI_ANY_ID, 5050 0, 0, 5051 pbn_b2_4_115200 }, 5052 /* 5053 * Brainboxes PX-101 5054 */ 5055 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5056 PCI_ANY_ID, PCI_ANY_ID, 5057 0, 0, 5058 pbn_b0_2_115200 }, 5059 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5060 PCI_ANY_ID, PCI_ANY_ID, 5061 0, 0, 5062 pbn_oxsemi_2_15625000 }, 5063 /* 5064 * Brainboxes PX-235/246 5065 */ 5066 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5067 PCI_ANY_ID, PCI_ANY_ID, 5068 0, 0, 5069 pbn_b0_1_115200 }, 5070 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5071 PCI_ANY_ID, PCI_ANY_ID, 5072 0, 0, 5073 pbn_oxsemi_1_15625000 }, 5074 /* 5075 * Brainboxes PX-203/PX-257 5076 */ 5077 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5078 PCI_ANY_ID, PCI_ANY_ID, 5079 0, 0, 5080 pbn_b0_2_115200 }, 5081 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5082 PCI_ANY_ID, PCI_ANY_ID, 5083 0, 0, 5084 pbn_oxsemi_4_15625000 }, 5085 /* 5086 * Brainboxes PX-260/PX-701 5087 */ 5088 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5089 PCI_ANY_ID, PCI_ANY_ID, 5090 0, 0, 5091 pbn_oxsemi_4_15625000 }, 5092 /* 5093 * Brainboxes PX-310 5094 */ 5095 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5096 PCI_ANY_ID, PCI_ANY_ID, 5097 0, 0, 5098 pbn_oxsemi_2_15625000 }, 5099 /* 5100 * Brainboxes PX-313 5101 */ 5102 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5103 PCI_ANY_ID, PCI_ANY_ID, 5104 0, 0, 5105 pbn_oxsemi_2_15625000 }, 5106 /* 5107 * Brainboxes PX-320/324/PX-376/PX-387 5108 */ 5109 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5110 PCI_ANY_ID, PCI_ANY_ID, 5111 0, 0, 5112 pbn_oxsemi_1_15625000 }, 5113 /* 5114 * Brainboxes PX-335/346 5115 */ 5116 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5117 PCI_ANY_ID, PCI_ANY_ID, 5118 0, 0, 5119 pbn_oxsemi_4_15625000 }, 5120 /* 5121 * Brainboxes PX-368 5122 */ 5123 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5124 PCI_ANY_ID, PCI_ANY_ID, 5125 0, 0, 5126 pbn_oxsemi_4_15625000 }, 5127 /* 5128 * Brainboxes PX-420 5129 */ 5130 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5131 PCI_ANY_ID, PCI_ANY_ID, 5132 0, 0, 5133 pbn_b0_4_115200 }, 5134 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5135 PCI_ANY_ID, PCI_ANY_ID, 5136 0, 0, 5137 pbn_oxsemi_4_15625000 }, 5138 /* 5139 * Brainboxes PX-803 5140 */ 5141 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5142 PCI_ANY_ID, PCI_ANY_ID, 5143 0, 0, 5144 pbn_b0_1_115200 }, 5145 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5146 PCI_ANY_ID, PCI_ANY_ID, 5147 0, 0, 5148 pbn_oxsemi_1_15625000 }, 5149 /* 5150 * Brainboxes PX-846 5151 */ 5152 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5153 PCI_ANY_ID, PCI_ANY_ID, 5154 0, 0, 5155 pbn_b0_1_115200 }, 5156 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5157 PCI_ANY_ID, PCI_ANY_ID, 5158 0, 0, 5159 pbn_oxsemi_1_15625000 }, 5160 5161 /* 5162 * Perle PCI-RAS cards 5163 */ 5164 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5165 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5166 0, 0, pbn_b2_4_921600 }, 5167 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5168 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5169 0, 0, pbn_b2_8_921600 }, 5170 5171 /* 5172 * Mainpine series cards: Fairly standard layout but fools 5173 * parts of the autodetect in some cases and uses otherwise 5174 * unmatched communications subclasses in the PCI Express case 5175 */ 5176 5177 { /* RockForceDUO */ 5178 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5179 PCI_VENDOR_ID_MAINPINE, 0x0200, 5180 0, 0, pbn_b0_2_115200 }, 5181 { /* RockForceQUATRO */ 5182 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5183 PCI_VENDOR_ID_MAINPINE, 0x0300, 5184 0, 0, pbn_b0_4_115200 }, 5185 { /* RockForceDUO+ */ 5186 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5187 PCI_VENDOR_ID_MAINPINE, 0x0400, 5188 0, 0, pbn_b0_2_115200 }, 5189 { /* RockForceQUATRO+ */ 5190 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5191 PCI_VENDOR_ID_MAINPINE, 0x0500, 5192 0, 0, pbn_b0_4_115200 }, 5193 { /* RockForce+ */ 5194 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5195 PCI_VENDOR_ID_MAINPINE, 0x0600, 5196 0, 0, pbn_b0_2_115200 }, 5197 { /* RockForce+ */ 5198 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5199 PCI_VENDOR_ID_MAINPINE, 0x0700, 5200 0, 0, pbn_b0_4_115200 }, 5201 { /* RockForceOCTO+ */ 5202 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5203 PCI_VENDOR_ID_MAINPINE, 0x0800, 5204 0, 0, pbn_b0_8_115200 }, 5205 { /* RockForceDUO+ */ 5206 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5207 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5208 0, 0, pbn_b0_2_115200 }, 5209 { /* RockForceQUARTRO+ */ 5210 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5211 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5212 0, 0, pbn_b0_4_115200 }, 5213 { /* RockForceOCTO+ */ 5214 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5215 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5216 0, 0, pbn_b0_8_115200 }, 5217 { /* RockForceD1 */ 5218 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5219 PCI_VENDOR_ID_MAINPINE, 0x2000, 5220 0, 0, pbn_b0_1_115200 }, 5221 { /* RockForceF1 */ 5222 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5223 PCI_VENDOR_ID_MAINPINE, 0x2100, 5224 0, 0, pbn_b0_1_115200 }, 5225 { /* RockForceD2 */ 5226 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5227 PCI_VENDOR_ID_MAINPINE, 0x2200, 5228 0, 0, pbn_b0_2_115200 }, 5229 { /* RockForceF2 */ 5230 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5231 PCI_VENDOR_ID_MAINPINE, 0x2300, 5232 0, 0, pbn_b0_2_115200 }, 5233 { /* RockForceD4 */ 5234 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5235 PCI_VENDOR_ID_MAINPINE, 0x2400, 5236 0, 0, pbn_b0_4_115200 }, 5237 { /* RockForceF4 */ 5238 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5239 PCI_VENDOR_ID_MAINPINE, 0x2500, 5240 0, 0, pbn_b0_4_115200 }, 5241 { /* RockForceD8 */ 5242 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5243 PCI_VENDOR_ID_MAINPINE, 0x2600, 5244 0, 0, pbn_b0_8_115200 }, 5245 { /* RockForceF8 */ 5246 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5247 PCI_VENDOR_ID_MAINPINE, 0x2700, 5248 0, 0, pbn_b0_8_115200 }, 5249 { /* IQ Express D1 */ 5250 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5251 PCI_VENDOR_ID_MAINPINE, 0x3000, 5252 0, 0, pbn_b0_1_115200 }, 5253 { /* IQ Express F1 */ 5254 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5255 PCI_VENDOR_ID_MAINPINE, 0x3100, 5256 0, 0, pbn_b0_1_115200 }, 5257 { /* IQ Express D2 */ 5258 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5259 PCI_VENDOR_ID_MAINPINE, 0x3200, 5260 0, 0, pbn_b0_2_115200 }, 5261 { /* IQ Express F2 */ 5262 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5263 PCI_VENDOR_ID_MAINPINE, 0x3300, 5264 0, 0, pbn_b0_2_115200 }, 5265 { /* IQ Express D4 */ 5266 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5267 PCI_VENDOR_ID_MAINPINE, 0x3400, 5268 0, 0, pbn_b0_4_115200 }, 5269 { /* IQ Express F4 */ 5270 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5271 PCI_VENDOR_ID_MAINPINE, 0x3500, 5272 0, 0, pbn_b0_4_115200 }, 5273 { /* IQ Express D8 */ 5274 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5275 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5276 0, 0, pbn_b0_8_115200 }, 5277 { /* IQ Express F8 */ 5278 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5279 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5280 0, 0, pbn_b0_8_115200 }, 5281 5282 5283 /* 5284 * PA Semi PA6T-1682M on-chip UART 5285 */ 5286 { PCI_VENDOR_ID_PASEMI, 0xa004, 5287 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5288 pbn_pasemi_1682M }, 5289 5290 /* 5291 * National Instruments 5292 */ 5293 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5295 pbn_b1_16_115200 }, 5296 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5298 pbn_b1_8_115200 }, 5299 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5301 pbn_b1_bt_4_115200 }, 5302 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5304 pbn_b1_bt_2_115200 }, 5305 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5307 pbn_b1_bt_4_115200 }, 5308 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5310 pbn_b1_bt_2_115200 }, 5311 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5313 pbn_b1_16_115200 }, 5314 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5316 pbn_b1_8_115200 }, 5317 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5319 pbn_b1_bt_4_115200 }, 5320 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5322 pbn_b1_bt_2_115200 }, 5323 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5325 pbn_b1_bt_4_115200 }, 5326 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5328 pbn_b1_bt_2_115200 }, 5329 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5331 pbn_ni8430_2 }, 5332 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5334 pbn_ni8430_2 }, 5335 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5337 pbn_ni8430_4 }, 5338 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5340 pbn_ni8430_4 }, 5341 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5343 pbn_ni8430_8 }, 5344 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5346 pbn_ni8430_8 }, 5347 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5349 pbn_ni8430_16 }, 5350 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5352 pbn_ni8430_16 }, 5353 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5355 pbn_ni8430_2 }, 5356 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5358 pbn_ni8430_2 }, 5359 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5361 pbn_ni8430_4 }, 5362 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5364 pbn_ni8430_4 }, 5365 5366 /* 5367 * MOXA 5368 */ 5369 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5371 pbn_moxa8250_2p }, 5372 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5374 pbn_moxa8250_2p }, 5375 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5377 pbn_moxa8250_4p }, 5378 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5379 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5380 pbn_moxa8250_4p }, 5381 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5383 pbn_moxa8250_8p }, 5384 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5385 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5386 pbn_moxa8250_8p }, 5387 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5389 pbn_moxa8250_8p }, 5390 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5391 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5392 pbn_moxa8250_8p }, 5393 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5395 pbn_moxa8250_2p }, 5396 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5397 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5398 pbn_moxa8250_4p }, 5399 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5401 pbn_moxa8250_8p }, 5402 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5404 pbn_moxa8250_8p }, 5405 5406 /* 5407 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5408 */ 5409 { PCI_VENDOR_ID_ADDIDATA, 5410 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5411 PCI_ANY_ID, 5412 PCI_ANY_ID, 5413 0, 5414 0, 5415 pbn_b0_4_115200 }, 5416 5417 { PCI_VENDOR_ID_ADDIDATA, 5418 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5419 PCI_ANY_ID, 5420 PCI_ANY_ID, 5421 0, 5422 0, 5423 pbn_b0_2_115200 }, 5424 5425 { PCI_VENDOR_ID_ADDIDATA, 5426 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5427 PCI_ANY_ID, 5428 PCI_ANY_ID, 5429 0, 5430 0, 5431 pbn_b0_1_115200 }, 5432 5433 { PCI_VENDOR_ID_AMCC, 5434 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5435 PCI_ANY_ID, 5436 PCI_ANY_ID, 5437 0, 5438 0, 5439 pbn_b1_8_115200 }, 5440 5441 { PCI_VENDOR_ID_ADDIDATA, 5442 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5443 PCI_ANY_ID, 5444 PCI_ANY_ID, 5445 0, 5446 0, 5447 pbn_b0_4_115200 }, 5448 5449 { PCI_VENDOR_ID_ADDIDATA, 5450 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5451 PCI_ANY_ID, 5452 PCI_ANY_ID, 5453 0, 5454 0, 5455 pbn_b0_2_115200 }, 5456 5457 { PCI_VENDOR_ID_ADDIDATA, 5458 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5459 PCI_ANY_ID, 5460 PCI_ANY_ID, 5461 0, 5462 0, 5463 pbn_b0_1_115200 }, 5464 5465 { PCI_VENDOR_ID_ADDIDATA, 5466 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5467 PCI_ANY_ID, 5468 PCI_ANY_ID, 5469 0, 5470 0, 5471 pbn_b0_4_115200 }, 5472 5473 { PCI_VENDOR_ID_ADDIDATA, 5474 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5475 PCI_ANY_ID, 5476 PCI_ANY_ID, 5477 0, 5478 0, 5479 pbn_b0_2_115200 }, 5480 5481 { PCI_VENDOR_ID_ADDIDATA, 5482 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5483 PCI_ANY_ID, 5484 PCI_ANY_ID, 5485 0, 5486 0, 5487 pbn_b0_1_115200 }, 5488 5489 { PCI_VENDOR_ID_ADDIDATA, 5490 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5491 PCI_ANY_ID, 5492 PCI_ANY_ID, 5493 0, 5494 0, 5495 pbn_b0_8_115200 }, 5496 5497 { PCI_VENDOR_ID_ADDIDATA, 5498 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5499 PCI_ANY_ID, 5500 PCI_ANY_ID, 5501 0, 5502 0, 5503 pbn_ADDIDATA_PCIe_4_3906250 }, 5504 5505 { PCI_VENDOR_ID_ADDIDATA, 5506 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5507 PCI_ANY_ID, 5508 PCI_ANY_ID, 5509 0, 5510 0, 5511 pbn_ADDIDATA_PCIe_2_3906250 }, 5512 5513 { PCI_VENDOR_ID_ADDIDATA, 5514 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5515 PCI_ANY_ID, 5516 PCI_ANY_ID, 5517 0, 5518 0, 5519 pbn_ADDIDATA_PCIe_1_3906250 }, 5520 5521 { PCI_VENDOR_ID_ADDIDATA, 5522 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5523 PCI_ANY_ID, 5524 PCI_ANY_ID, 5525 0, 5526 0, 5527 pbn_ADDIDATA_PCIe_8_3906250 }, 5528 5529 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5530 PCI_VENDOR_ID_IBM, 0x0299, 5531 0, 0, pbn_b0_bt_2_115200 }, 5532 5533 /* 5534 * other NetMos 9835 devices are most likely handled by the 5535 * parport_serial driver, check drivers/parport/parport_serial.c 5536 * before adding them here. 5537 */ 5538 5539 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5540 0xA000, 0x1000, 5541 0, 0, pbn_b0_1_115200 }, 5542 5543 /* the 9901 is a rebranded 9912 */ 5544 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5545 0xA000, 0x1000, 5546 0, 0, pbn_b0_1_115200 }, 5547 5548 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5549 0xA000, 0x1000, 5550 0, 0, pbn_b0_1_115200 }, 5551 5552 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5553 0xA000, 0x1000, 5554 0, 0, pbn_b0_1_115200 }, 5555 5556 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5557 0xA000, 0x1000, 5558 0, 0, pbn_b0_1_115200 }, 5559 5560 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5561 0xA000, 0x3002, 5562 0, 0, pbn_NETMOS9900_2s_115200 }, 5563 5564 /* 5565 * Best Connectivity and Rosewill PCI Multi I/O cards 5566 */ 5567 5568 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5569 0xA000, 0x1000, 5570 0, 0, pbn_b0_1_115200 }, 5571 5572 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5573 0xA000, 0x3002, 5574 0, 0, pbn_b0_bt_2_115200 }, 5575 5576 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5577 0xA000, 0x3004, 5578 0, 0, pbn_b0_bt_4_115200 }, 5579 /* Intel CE4100 */ 5580 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5582 pbn_ce4100_1_115200 }, 5583 5584 /* 5585 * Cronyx Omega PCI 5586 */ 5587 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5588 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5589 pbn_omegapci }, 5590 5591 /* 5592 * Broadcom TruManage 5593 */ 5594 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5596 pbn_brcm_trumanage }, 5597 5598 /* 5599 * AgeStar as-prs2-009 5600 */ 5601 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5602 PCI_ANY_ID, PCI_ANY_ID, 5603 0, 0, pbn_b0_bt_2_115200 }, 5604 5605 /* 5606 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5607 * so not listed here. 5608 */ 5609 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5610 PCI_ANY_ID, PCI_ANY_ID, 5611 0, 0, pbn_b0_bt_4_115200 }, 5612 5613 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5614 PCI_ANY_ID, PCI_ANY_ID, 5615 0, 0, pbn_b0_bt_2_115200 }, 5616 5617 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5618 PCI_ANY_ID, PCI_ANY_ID, 5619 0, 0, pbn_b0_bt_4_115200 }, 5620 5621 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5622 PCI_ANY_ID, PCI_ANY_ID, 5623 0, 0, pbn_wch382_2 }, 5624 5625 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5626 PCI_ANY_ID, PCI_ANY_ID, 5627 0, 0, pbn_wch384_4 }, 5628 5629 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5630 PCI_ANY_ID, PCI_ANY_ID, 5631 0, 0, pbn_wch384_8 }, 5632 /* 5633 * Realtek RealManage 5634 */ 5635 { PCI_VENDOR_ID_REALTEK, 0x816a, 5636 PCI_ANY_ID, PCI_ANY_ID, 5637 0, 0, pbn_b0_1_115200 }, 5638 5639 { PCI_VENDOR_ID_REALTEK, 0x816b, 5640 PCI_ANY_ID, PCI_ANY_ID, 5641 0, 0, pbn_b0_1_115200 }, 5642 5643 /* Fintek PCI serial cards */ 5644 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5645 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5646 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5647 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5648 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5649 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5650 5651 /* MKS Tenta SCOM-080x serial cards */ 5652 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5653 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5654 5655 /* Amazon PCI serial device */ 5656 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5657 5658 /* 5659 * These entries match devices with class COMMUNICATION_SERIAL, 5660 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5661 */ 5662 { PCI_ANY_ID, PCI_ANY_ID, 5663 PCI_ANY_ID, PCI_ANY_ID, 5664 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5665 0xffff00, pbn_default }, 5666 { PCI_ANY_ID, PCI_ANY_ID, 5667 PCI_ANY_ID, PCI_ANY_ID, 5668 PCI_CLASS_COMMUNICATION_MODEM << 8, 5669 0xffff00, pbn_default }, 5670 { PCI_ANY_ID, PCI_ANY_ID, 5671 PCI_ANY_ID, PCI_ANY_ID, 5672 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5673 0xffff00, pbn_default }, 5674 { 0, } 5675 }; 5676 5677 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5678 pci_channel_state_t state) 5679 { 5680 struct serial_private *priv = pci_get_drvdata(dev); 5681 5682 if (state == pci_channel_io_perm_failure) 5683 return PCI_ERS_RESULT_DISCONNECT; 5684 5685 if (priv) 5686 pciserial_detach_ports(priv); 5687 5688 pci_disable_device(dev); 5689 5690 return PCI_ERS_RESULT_NEED_RESET; 5691 } 5692 5693 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5694 { 5695 int rc; 5696 5697 rc = pci_enable_device(dev); 5698 5699 if (rc) 5700 return PCI_ERS_RESULT_DISCONNECT; 5701 5702 pci_restore_state(dev); 5703 pci_save_state(dev); 5704 5705 return PCI_ERS_RESULT_RECOVERED; 5706 } 5707 5708 static void serial8250_io_resume(struct pci_dev *dev) 5709 { 5710 struct serial_private *priv = pci_get_drvdata(dev); 5711 struct serial_private *new; 5712 5713 if (!priv) 5714 return; 5715 5716 new = pciserial_init_ports(dev, priv->board); 5717 if (!IS_ERR(new)) { 5718 pci_set_drvdata(dev, new); 5719 kfree(priv); 5720 } 5721 } 5722 5723 static const struct pci_error_handlers serial8250_err_handler = { 5724 .error_detected = serial8250_io_error_detected, 5725 .slot_reset = serial8250_io_slot_reset, 5726 .resume = serial8250_io_resume, 5727 }; 5728 5729 static struct pci_driver serial_pci_driver = { 5730 .name = "serial", 5731 .probe = pciserial_init_one, 5732 .remove = pciserial_remove_one, 5733 .driver = { 5734 .pm = &pciserial_pm_ops, 5735 }, 5736 .id_table = serial_pci_tbl, 5737 .err_handler = &serial8250_err_handler, 5738 }; 5739 5740 module_pci_driver(serial_pci_driver); 5741 5742 MODULE_LICENSE("GPL"); 5743 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5744 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5745 MODULE_IMPORT_NS(SERIAL_8250_PCI); 5746