xref: /openbmc/linux/drivers/tty/serial/8250/8250_pci.c (revision 6aa7de05)
1 /*
2  *  Probe module for 8250/16550-type PCI serial ports.
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License.
11  */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24 
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27 
28 #include "8250.h"
29 
30 /*
31  * init function returns:
32  *  > 0 - number of ports
33  *  = 0 - use board->num_ports
34  *  < 0 - error
35  */
36 struct pci_serial_quirk {
37 	u32	vendor;
38 	u32	device;
39 	u32	subvendor;
40 	u32	subdevice;
41 	int	(*probe)(struct pci_dev *dev);
42 	int	(*init)(struct pci_dev *dev);
43 	int	(*setup)(struct serial_private *,
44 			 const struct pciserial_board *,
45 			 struct uart_8250_port *, int);
46 	void	(*exit)(struct pci_dev *dev);
47 };
48 
49 #define PCI_NUM_BAR_RESOURCES	6
50 
51 struct serial_private {
52 	struct pci_dev		*dev;
53 	unsigned int		nr;
54 	struct pci_serial_quirk	*quirk;
55 	const struct pciserial_board *board;
56 	int			line[0];
57 };
58 
59 static int pci_default_setup(struct serial_private*,
60 	  const struct pciserial_board*, struct uart_8250_port *, int);
61 
62 static void moan_device(const char *str, struct pci_dev *dev)
63 {
64 	dev_err(&dev->dev,
65 	       "%s: %s\n"
66 	       "Please send the output of lspci -vv, this\n"
67 	       "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 	       "manufacturer and name of serial board or\n"
69 	       "modem board to <linux-serial@vger.kernel.org>.\n",
70 	       pci_name(dev), str, dev->vendor, dev->device,
71 	       dev->subsystem_vendor, dev->subsystem_device);
72 }
73 
74 static int
75 setup_port(struct serial_private *priv, struct uart_8250_port *port,
76 	   int bar, int offset, int regshift)
77 {
78 	struct pci_dev *dev = priv->dev;
79 
80 	if (bar >= PCI_NUM_BAR_RESOURCES)
81 		return -EINVAL;
82 
83 	if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
84 		if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
85 			return -ENOMEM;
86 
87 		port->port.iotype = UPIO_MEM;
88 		port->port.iobase = 0;
89 		port->port.mapbase = pci_resource_start(dev, bar) + offset;
90 		port->port.membase = pcim_iomap_table(dev)[bar] + offset;
91 		port->port.regshift = regshift;
92 	} else {
93 		port->port.iotype = UPIO_PORT;
94 		port->port.iobase = pci_resource_start(dev, bar) + offset;
95 		port->port.mapbase = 0;
96 		port->port.membase = NULL;
97 		port->port.regshift = 0;
98 	}
99 	return 0;
100 }
101 
102 /*
103  * ADDI-DATA GmbH communication cards <info@addi-data.com>
104  */
105 static int addidata_apci7800_setup(struct serial_private *priv,
106 				const struct pciserial_board *board,
107 				struct uart_8250_port *port, int idx)
108 {
109 	unsigned int bar = 0, offset = board->first_offset;
110 	bar = FL_GET_BASE(board->flags);
111 
112 	if (idx < 2) {
113 		offset += idx * board->uart_offset;
114 	} else if ((idx >= 2) && (idx < 4)) {
115 		bar += 1;
116 		offset += ((idx - 2) * board->uart_offset);
117 	} else if ((idx >= 4) && (idx < 6)) {
118 		bar += 2;
119 		offset += ((idx - 4) * board->uart_offset);
120 	} else if (idx >= 6) {
121 		bar += 3;
122 		offset += ((idx - 6) * board->uart_offset);
123 	}
124 
125 	return setup_port(priv, port, bar, offset, board->reg_shift);
126 }
127 
128 /*
129  * AFAVLAB uses a different mixture of BARs and offsets
130  * Not that ugly ;) -- HW
131  */
132 static int
133 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
134 	      struct uart_8250_port *port, int idx)
135 {
136 	unsigned int bar, offset = board->first_offset;
137 
138 	bar = FL_GET_BASE(board->flags);
139 	if (idx < 4)
140 		bar += idx;
141 	else {
142 		bar = 4;
143 		offset += (idx - 4) * board->uart_offset;
144 	}
145 
146 	return setup_port(priv, port, bar, offset, board->reg_shift);
147 }
148 
149 /*
150  * HP's Remote Management Console.  The Diva chip came in several
151  * different versions.  N-class, L2000 and A500 have two Diva chips, each
152  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
153  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
154  * one Diva chip, but it has been expanded to 5 UARTs.
155  */
156 static int pci_hp_diva_init(struct pci_dev *dev)
157 {
158 	int rc = 0;
159 
160 	switch (dev->subsystem_device) {
161 	case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
162 	case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
163 	case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
164 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
165 		rc = 3;
166 		break;
167 	case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
168 		rc = 2;
169 		break;
170 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
171 		rc = 4;
172 		break;
173 	case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
174 	case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
175 		rc = 1;
176 		break;
177 	}
178 
179 	return rc;
180 }
181 
182 /*
183  * HP's Diva chip puts the 4th/5th serial port further out, and
184  * some serial ports are supposed to be hidden on certain models.
185  */
186 static int
187 pci_hp_diva_setup(struct serial_private *priv,
188 		const struct pciserial_board *board,
189 		struct uart_8250_port *port, int idx)
190 {
191 	unsigned int offset = board->first_offset;
192 	unsigned int bar = FL_GET_BASE(board->flags);
193 
194 	switch (priv->dev->subsystem_device) {
195 	case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
196 		if (idx == 3)
197 			idx++;
198 		break;
199 	case PCI_DEVICE_ID_HP_DIVA_EVEREST:
200 		if (idx > 0)
201 			idx++;
202 		if (idx > 2)
203 			idx++;
204 		break;
205 	}
206 	if (idx > 2)
207 		offset = 0x18;
208 
209 	offset += idx * board->uart_offset;
210 
211 	return setup_port(priv, port, bar, offset, board->reg_shift);
212 }
213 
214 /*
215  * Added for EKF Intel i960 serial boards
216  */
217 static int pci_inteli960ni_init(struct pci_dev *dev)
218 {
219 	u32 oldval;
220 
221 	if (!(dev->subsystem_device & 0x1000))
222 		return -ENODEV;
223 
224 	/* is firmware started? */
225 	pci_read_config_dword(dev, 0x44, &oldval);
226 	if (oldval == 0x00001000L) { /* RESET value */
227 		dev_dbg(&dev->dev, "Local i960 firmware missing\n");
228 		return -ENODEV;
229 	}
230 	return 0;
231 }
232 
233 /*
234  * Some PCI serial cards using the PLX 9050 PCI interface chip require
235  * that the card interrupt be explicitly enabled or disabled.  This
236  * seems to be mainly needed on card using the PLX which also use I/O
237  * mapped memory.
238  */
239 static int pci_plx9050_init(struct pci_dev *dev)
240 {
241 	u8 irq_config;
242 	void __iomem *p;
243 
244 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
245 		moan_device("no memory in bar 0", dev);
246 		return 0;
247 	}
248 
249 	irq_config = 0x41;
250 	if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
251 	    dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
252 		irq_config = 0x43;
253 
254 	if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
255 	    (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
256 		/*
257 		 * As the megawolf cards have the int pins active
258 		 * high, and have 2 UART chips, both ints must be
259 		 * enabled on the 9050. Also, the UARTS are set in
260 		 * 16450 mode by default, so we have to enable the
261 		 * 16C950 'enhanced' mode so that we can use the
262 		 * deep FIFOs
263 		 */
264 		irq_config = 0x5b;
265 	/*
266 	 * enable/disable interrupts
267 	 */
268 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
269 	if (p == NULL)
270 		return -ENOMEM;
271 	writel(irq_config, p + 0x4c);
272 
273 	/*
274 	 * Read the register back to ensure that it took effect.
275 	 */
276 	readl(p + 0x4c);
277 	iounmap(p);
278 
279 	return 0;
280 }
281 
282 static void pci_plx9050_exit(struct pci_dev *dev)
283 {
284 	u8 __iomem *p;
285 
286 	if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
287 		return;
288 
289 	/*
290 	 * disable interrupts
291 	 */
292 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
293 	if (p != NULL) {
294 		writel(0, p + 0x4c);
295 
296 		/*
297 		 * Read the register back to ensure that it took effect.
298 		 */
299 		readl(p + 0x4c);
300 		iounmap(p);
301 	}
302 }
303 
304 #define NI8420_INT_ENABLE_REG	0x38
305 #define NI8420_INT_ENABLE_BIT	0x2000
306 
307 static void pci_ni8420_exit(struct pci_dev *dev)
308 {
309 	void __iomem *p;
310 	unsigned int bar = 0;
311 
312 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
313 		moan_device("no memory in bar", dev);
314 		return;
315 	}
316 
317 	p = pci_ioremap_bar(dev, bar);
318 	if (p == NULL)
319 		return;
320 
321 	/* Disable the CPU Interrupt */
322 	writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
323 	       p + NI8420_INT_ENABLE_REG);
324 	iounmap(p);
325 }
326 
327 
328 /* MITE registers */
329 #define MITE_IOWBSR1	0xc4
330 #define MITE_IOWCR1	0xf4
331 #define MITE_LCIMR1	0x08
332 #define MITE_LCIMR2	0x10
333 
334 #define MITE_LCIMR2_CLR_CPU_IE	(1 << 30)
335 
336 static void pci_ni8430_exit(struct pci_dev *dev)
337 {
338 	void __iomem *p;
339 	unsigned int bar = 0;
340 
341 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
342 		moan_device("no memory in bar", dev);
343 		return;
344 	}
345 
346 	p = pci_ioremap_bar(dev, bar);
347 	if (p == NULL)
348 		return;
349 
350 	/* Disable the CPU Interrupt */
351 	writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
352 	iounmap(p);
353 }
354 
355 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
356 static int
357 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
358 		struct uart_8250_port *port, int idx)
359 {
360 	unsigned int bar, offset = board->first_offset;
361 
362 	bar = 0;
363 
364 	if (idx < 4) {
365 		/* first four channels map to 0, 0x100, 0x200, 0x300 */
366 		offset += idx * board->uart_offset;
367 	} else if (idx < 8) {
368 		/* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
369 		offset += idx * board->uart_offset + 0xC00;
370 	} else /* we have only 8 ports on PMC-OCTALPRO */
371 		return 1;
372 
373 	return setup_port(priv, port, bar, offset, board->reg_shift);
374 }
375 
376 /*
377 * This does initialization for PMC OCTALPRO cards:
378 * maps the device memory, resets the UARTs (needed, bc
379 * if the module is removed and inserted again, the card
380 * is in the sleep mode) and enables global interrupt.
381 */
382 
383 /* global control register offset for SBS PMC-OctalPro */
384 #define OCT_REG_CR_OFF		0x500
385 
386 static int sbs_init(struct pci_dev *dev)
387 {
388 	u8 __iomem *p;
389 
390 	p = pci_ioremap_bar(dev, 0);
391 
392 	if (p == NULL)
393 		return -ENOMEM;
394 	/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
395 	writeb(0x10, p + OCT_REG_CR_OFF);
396 	udelay(50);
397 	writeb(0x0, p + OCT_REG_CR_OFF);
398 
399 	/* Set bit-2 (INTENABLE) of Control Register */
400 	writeb(0x4, p + OCT_REG_CR_OFF);
401 	iounmap(p);
402 
403 	return 0;
404 }
405 
406 /*
407  * Disables the global interrupt of PMC-OctalPro
408  */
409 
410 static void sbs_exit(struct pci_dev *dev)
411 {
412 	u8 __iomem *p;
413 
414 	p = pci_ioremap_bar(dev, 0);
415 	/* FIXME: What if resource_len < OCT_REG_CR_OFF */
416 	if (p != NULL)
417 		writeb(0, p + OCT_REG_CR_OFF);
418 	iounmap(p);
419 }
420 
421 /*
422  * SIIG serial cards have an PCI interface chip which also controls
423  * the UART clocking frequency. Each UART can be clocked independently
424  * (except cards equipped with 4 UARTs) and initial clocking settings
425  * are stored in the EEPROM chip. It can cause problems because this
426  * version of serial driver doesn't support differently clocked UART's
427  * on single PCI card. To prevent this, initialization functions set
428  * high frequency clocking for all UART's on given card. It is safe (I
429  * hope) because it doesn't touch EEPROM settings to prevent conflicts
430  * with other OSes (like M$ DOS).
431  *
432  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
433  *
434  * There is two family of SIIG serial cards with different PCI
435  * interface chip and different configuration methods:
436  *     - 10x cards have control registers in IO and/or memory space;
437  *     - 20x cards have control registers in standard PCI configuration space.
438  *
439  * Note: all 10x cards have PCI device ids 0x10..
440  *       all 20x cards have PCI device ids 0x20..
441  *
442  * There are also Quartet Serial cards which use Oxford Semiconductor
443  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
444  *
445  * Note: some SIIG cards are probed by the parport_serial object.
446  */
447 
448 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
449 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
450 
451 static int pci_siig10x_init(struct pci_dev *dev)
452 {
453 	u16 data;
454 	void __iomem *p;
455 
456 	switch (dev->device & 0xfff8) {
457 	case PCI_DEVICE_ID_SIIG_1S_10x:	/* 1S */
458 		data = 0xffdf;
459 		break;
460 	case PCI_DEVICE_ID_SIIG_2S_10x:	/* 2S, 2S1P */
461 		data = 0xf7ff;
462 		break;
463 	default:			/* 1S1P, 4S */
464 		data = 0xfffb;
465 		break;
466 	}
467 
468 	p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
469 	if (p == NULL)
470 		return -ENOMEM;
471 
472 	writew(readw(p + 0x28) & data, p + 0x28);
473 	readw(p + 0x28);
474 	iounmap(p);
475 	return 0;
476 }
477 
478 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
479 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
480 
481 static int pci_siig20x_init(struct pci_dev *dev)
482 {
483 	u8 data;
484 
485 	/* Change clock frequency for the first UART. */
486 	pci_read_config_byte(dev, 0x6f, &data);
487 	pci_write_config_byte(dev, 0x6f, data & 0xef);
488 
489 	/* If this card has 2 UART, we have to do the same with second UART. */
490 	if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
491 	    ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
492 		pci_read_config_byte(dev, 0x73, &data);
493 		pci_write_config_byte(dev, 0x73, data & 0xef);
494 	}
495 	return 0;
496 }
497 
498 static int pci_siig_init(struct pci_dev *dev)
499 {
500 	unsigned int type = dev->device & 0xff00;
501 
502 	if (type == 0x1000)
503 		return pci_siig10x_init(dev);
504 	else if (type == 0x2000)
505 		return pci_siig20x_init(dev);
506 
507 	moan_device("Unknown SIIG card", dev);
508 	return -ENODEV;
509 }
510 
511 static int pci_siig_setup(struct serial_private *priv,
512 			  const struct pciserial_board *board,
513 			  struct uart_8250_port *port, int idx)
514 {
515 	unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
516 
517 	if (idx > 3) {
518 		bar = 4;
519 		offset = (idx - 4) * 8;
520 	}
521 
522 	return setup_port(priv, port, bar, offset, 0);
523 }
524 
525 /*
526  * Timedia has an explosion of boards, and to avoid the PCI table from
527  * growing *huge*, we use this function to collapse some 70 entries
528  * in the PCI table into one, for sanity's and compactness's sake.
529  */
530 static const unsigned short timedia_single_port[] = {
531 	0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
532 };
533 
534 static const unsigned short timedia_dual_port[] = {
535 	0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
536 	0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
537 	0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
538 	0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
539 	0xD079, 0
540 };
541 
542 static const unsigned short timedia_quad_port[] = {
543 	0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
544 	0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
545 	0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
546 	0xB157, 0
547 };
548 
549 static const unsigned short timedia_eight_port[] = {
550 	0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
551 	0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
552 };
553 
554 static const struct timedia_struct {
555 	int num;
556 	const unsigned short *ids;
557 } timedia_data[] = {
558 	{ 1, timedia_single_port },
559 	{ 2, timedia_dual_port },
560 	{ 4, timedia_quad_port },
561 	{ 8, timedia_eight_port }
562 };
563 
564 /*
565  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
566  * listing them individually, this driver merely grabs them all with
567  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
568  * and should be left free to be claimed by parport_serial instead.
569  */
570 static int pci_timedia_probe(struct pci_dev *dev)
571 {
572 	/*
573 	 * Check the third digit of the subdevice ID
574 	 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
575 	 */
576 	if ((dev->subsystem_device & 0x00f0) >= 0x70) {
577 		dev_info(&dev->dev,
578 			"ignoring Timedia subdevice %04x for parport_serial\n",
579 			dev->subsystem_device);
580 		return -ENODEV;
581 	}
582 
583 	return 0;
584 }
585 
586 static int pci_timedia_init(struct pci_dev *dev)
587 {
588 	const unsigned short *ids;
589 	int i, j;
590 
591 	for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
592 		ids = timedia_data[i].ids;
593 		for (j = 0; ids[j]; j++)
594 			if (dev->subsystem_device == ids[j])
595 				return timedia_data[i].num;
596 	}
597 	return 0;
598 }
599 
600 /*
601  * Timedia/SUNIX uses a mixture of BARs and offsets
602  * Ugh, this is ugly as all hell --- TYT
603  */
604 static int
605 pci_timedia_setup(struct serial_private *priv,
606 		  const struct pciserial_board *board,
607 		  struct uart_8250_port *port, int idx)
608 {
609 	unsigned int bar = 0, offset = board->first_offset;
610 
611 	switch (idx) {
612 	case 0:
613 		bar = 0;
614 		break;
615 	case 1:
616 		offset = board->uart_offset;
617 		bar = 0;
618 		break;
619 	case 2:
620 		bar = 1;
621 		break;
622 	case 3:
623 		offset = board->uart_offset;
624 		/* FALLTHROUGH */
625 	case 4: /* BAR 2 */
626 	case 5: /* BAR 3 */
627 	case 6: /* BAR 4 */
628 	case 7: /* BAR 5 */
629 		bar = idx - 2;
630 	}
631 
632 	return setup_port(priv, port, bar, offset, board->reg_shift);
633 }
634 
635 /*
636  * Some Titan cards are also a little weird
637  */
638 static int
639 titan_400l_800l_setup(struct serial_private *priv,
640 		      const struct pciserial_board *board,
641 		      struct uart_8250_port *port, int idx)
642 {
643 	unsigned int bar, offset = board->first_offset;
644 
645 	switch (idx) {
646 	case 0:
647 		bar = 1;
648 		break;
649 	case 1:
650 		bar = 2;
651 		break;
652 	default:
653 		bar = 4;
654 		offset = (idx - 2) * board->uart_offset;
655 	}
656 
657 	return setup_port(priv, port, bar, offset, board->reg_shift);
658 }
659 
660 static int pci_xircom_init(struct pci_dev *dev)
661 {
662 	msleep(100);
663 	return 0;
664 }
665 
666 static int pci_ni8420_init(struct pci_dev *dev)
667 {
668 	void __iomem *p;
669 	unsigned int bar = 0;
670 
671 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
672 		moan_device("no memory in bar", dev);
673 		return 0;
674 	}
675 
676 	p = pci_ioremap_bar(dev, bar);
677 	if (p == NULL)
678 		return -ENOMEM;
679 
680 	/* Enable CPU Interrupt */
681 	writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
682 	       p + NI8420_INT_ENABLE_REG);
683 
684 	iounmap(p);
685 	return 0;
686 }
687 
688 #define MITE_IOWBSR1_WSIZE	0xa
689 #define MITE_IOWBSR1_WIN_OFFSET	0x800
690 #define MITE_IOWBSR1_WENAB	(1 << 7)
691 #define MITE_LCIMR1_IO_IE_0	(1 << 24)
692 #define MITE_LCIMR2_SET_CPU_IE	(1 << 31)
693 #define MITE_IOWCR1_RAMSEL_MASK	0xfffffffe
694 
695 static int pci_ni8430_init(struct pci_dev *dev)
696 {
697 	void __iomem *p;
698 	struct pci_bus_region region;
699 	u32 device_window;
700 	unsigned int bar = 0;
701 
702 	if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
703 		moan_device("no memory in bar", dev);
704 		return 0;
705 	}
706 
707 	p = pci_ioremap_bar(dev, bar);
708 	if (p == NULL)
709 		return -ENOMEM;
710 
711 	/*
712 	 * Set device window address and size in BAR0, while acknowledging that
713 	 * the resource structure may contain a translated address that differs
714 	 * from the address the device responds to.
715 	 */
716 	pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
717 	device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
718 			| MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
719 	writel(device_window, p + MITE_IOWBSR1);
720 
721 	/* Set window access to go to RAMSEL IO address space */
722 	writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
723 	       p + MITE_IOWCR1);
724 
725 	/* Enable IO Bus Interrupt 0 */
726 	writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
727 
728 	/* Enable CPU Interrupt */
729 	writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
730 
731 	iounmap(p);
732 	return 0;
733 }
734 
735 /* UART Port Control Register */
736 #define NI8430_PORTCON	0x0f
737 #define NI8430_PORTCON_TXVR_ENABLE	(1 << 3)
738 
739 static int
740 pci_ni8430_setup(struct serial_private *priv,
741 		 const struct pciserial_board *board,
742 		 struct uart_8250_port *port, int idx)
743 {
744 	struct pci_dev *dev = priv->dev;
745 	void __iomem *p;
746 	unsigned int bar, offset = board->first_offset;
747 
748 	if (idx >= board->num_ports)
749 		return 1;
750 
751 	bar = FL_GET_BASE(board->flags);
752 	offset += idx * board->uart_offset;
753 
754 	p = pci_ioremap_bar(dev, bar);
755 	if (!p)
756 		return -ENOMEM;
757 
758 	/* enable the transceiver */
759 	writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
760 	       p + offset + NI8430_PORTCON);
761 
762 	iounmap(p);
763 
764 	return setup_port(priv, port, bar, offset, board->reg_shift);
765 }
766 
767 static int pci_netmos_9900_setup(struct serial_private *priv,
768 				const struct pciserial_board *board,
769 				struct uart_8250_port *port, int idx)
770 {
771 	unsigned int bar;
772 
773 	if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
774 	    (priv->dev->subsystem_device & 0xff00) == 0x3000) {
775 		/* netmos apparently orders BARs by datasheet layout, so serial
776 		 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
777 		 */
778 		bar = 3 * idx;
779 
780 		return setup_port(priv, port, bar, 0, board->reg_shift);
781 	} else {
782 		return pci_default_setup(priv, board, port, idx);
783 	}
784 }
785 
786 /* the 99xx series comes with a range of device IDs and a variety
787  * of capabilities:
788  *
789  * 9900 has varying capabilities and can cascade to sub-controllers
790  *   (cascading should be purely internal)
791  * 9904 is hardwired with 4 serial ports
792  * 9912 and 9922 are hardwired with 2 serial ports
793  */
794 static int pci_netmos_9900_numports(struct pci_dev *dev)
795 {
796 	unsigned int c = dev->class;
797 	unsigned int pi;
798 	unsigned short sub_serports;
799 
800 	pi = c & 0xff;
801 
802 	if (pi == 2)
803 		return 1;
804 
805 	if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
806 		/* two possibilities: 0x30ps encodes number of parallel and
807 		 * serial ports, or 0x1000 indicates *something*. This is not
808 		 * immediately obvious, since the 2s1p+4s configuration seems
809 		 * to offer all functionality on functions 0..2, while still
810 		 * advertising the same function 3 as the 4s+2s1p config.
811 		 */
812 		sub_serports = dev->subsystem_device & 0xf;
813 		if (sub_serports > 0)
814 			return sub_serports;
815 
816 		dev_err(&dev->dev,
817 			"NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
818 		return 0;
819 	}
820 
821 	moan_device("unknown NetMos/Mostech program interface", dev);
822 	return 0;
823 }
824 
825 static int pci_netmos_init(struct pci_dev *dev)
826 {
827 	/* subdevice 0x00PS means <P> parallel, <S> serial */
828 	unsigned int num_serial = dev->subsystem_device & 0xf;
829 
830 	if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
831 		(dev->device == PCI_DEVICE_ID_NETMOS_9865))
832 		return 0;
833 
834 	if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
835 			dev->subsystem_device == 0x0299)
836 		return 0;
837 
838 	switch (dev->device) { /* FALLTHROUGH on all */
839 	case PCI_DEVICE_ID_NETMOS_9904:
840 	case PCI_DEVICE_ID_NETMOS_9912:
841 	case PCI_DEVICE_ID_NETMOS_9922:
842 	case PCI_DEVICE_ID_NETMOS_9900:
843 		num_serial = pci_netmos_9900_numports(dev);
844 		break;
845 
846 	default:
847 		break;
848 	}
849 
850 	if (num_serial == 0) {
851 		moan_device("unknown NetMos/Mostech device", dev);
852 		return -ENODEV;
853 	}
854 
855 	return num_serial;
856 }
857 
858 /*
859  * These chips are available with optionally one parallel port and up to
860  * two serial ports. Unfortunately they all have the same product id.
861  *
862  * Basic configuration is done over a region of 32 I/O ports. The base
863  * ioport is called INTA or INTC, depending on docs/other drivers.
864  *
865  * The region of the 32 I/O ports is configured in POSIO0R...
866  */
867 
868 /* registers */
869 #define ITE_887x_MISCR		0x9c
870 #define ITE_887x_INTCBAR	0x78
871 #define ITE_887x_UARTBAR	0x7c
872 #define ITE_887x_PS0BAR		0x10
873 #define ITE_887x_POSIO0		0x60
874 
875 /* I/O space size */
876 #define ITE_887x_IOSIZE		32
877 /* I/O space size (bits 26-24; 8 bytes = 011b) */
878 #define ITE_887x_POSIO_IOSIZE_8		(3 << 24)
879 /* I/O space size (bits 26-24; 32 bytes = 101b) */
880 #define ITE_887x_POSIO_IOSIZE_32	(5 << 24)
881 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
882 #define ITE_887x_POSIO_SPEED		(3 << 29)
883 /* enable IO_Space bit */
884 #define ITE_887x_POSIO_ENABLE		(1 << 31)
885 
886 static int pci_ite887x_init(struct pci_dev *dev)
887 {
888 	/* inta_addr are the configuration addresses of the ITE */
889 	static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
890 							0x200, 0x280, 0 };
891 	int ret, i, type;
892 	struct resource *iobase = NULL;
893 	u32 miscr, uartbar, ioport;
894 
895 	/* search for the base-ioport */
896 	i = 0;
897 	while (inta_addr[i] && iobase == NULL) {
898 		iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
899 								"ite887x");
900 		if (iobase != NULL) {
901 			/* write POSIO0R - speed | size | ioport */
902 			pci_write_config_dword(dev, ITE_887x_POSIO0,
903 				ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
904 				ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
905 			/* write INTCBAR - ioport */
906 			pci_write_config_dword(dev, ITE_887x_INTCBAR,
907 								inta_addr[i]);
908 			ret = inb(inta_addr[i]);
909 			if (ret != 0xff) {
910 				/* ioport connected */
911 				break;
912 			}
913 			release_region(iobase->start, ITE_887x_IOSIZE);
914 			iobase = NULL;
915 		}
916 		i++;
917 	}
918 
919 	if (!inta_addr[i]) {
920 		dev_err(&dev->dev, "ite887x: could not find iobase\n");
921 		return -ENODEV;
922 	}
923 
924 	/* start of undocumented type checking (see parport_pc.c) */
925 	type = inb(iobase->start + 0x18) & 0x0f;
926 
927 	switch (type) {
928 	case 0x2:	/* ITE8871 (1P) */
929 	case 0xa:	/* ITE8875 (1P) */
930 		ret = 0;
931 		break;
932 	case 0xe:	/* ITE8872 (2S1P) */
933 		ret = 2;
934 		break;
935 	case 0x6:	/* ITE8873 (1S) */
936 		ret = 1;
937 		break;
938 	case 0x8:	/* ITE8874 (2S) */
939 		ret = 2;
940 		break;
941 	default:
942 		moan_device("Unknown ITE887x", dev);
943 		ret = -ENODEV;
944 	}
945 
946 	/* configure all serial ports */
947 	for (i = 0; i < ret; i++) {
948 		/* read the I/O port from the device */
949 		pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
950 								&ioport);
951 		ioport &= 0x0000FF00;	/* the actual base address */
952 		pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
953 			ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
954 			ITE_887x_POSIO_IOSIZE_8 | ioport);
955 
956 		/* write the ioport to the UARTBAR */
957 		pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
958 		uartbar &= ~(0xffff << (16 * i));	/* clear half the reg */
959 		uartbar |= (ioport << (16 * i));	/* set the ioport */
960 		pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
961 
962 		/* get current config */
963 		pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
964 		/* disable interrupts (UARTx_Routing[3:0]) */
965 		miscr &= ~(0xf << (12 - 4 * i));
966 		/* activate the UART (UARTx_En) */
967 		miscr |= 1 << (23 - i);
968 		/* write new config with activated UART */
969 		pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
970 	}
971 
972 	if (ret <= 0) {
973 		/* the device has no UARTs if we get here */
974 		release_region(iobase->start, ITE_887x_IOSIZE);
975 	}
976 
977 	return ret;
978 }
979 
980 static void pci_ite887x_exit(struct pci_dev *dev)
981 {
982 	u32 ioport;
983 	/* the ioport is bit 0-15 in POSIO0R */
984 	pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
985 	ioport &= 0xffff;
986 	release_region(ioport, ITE_887x_IOSIZE);
987 }
988 
989 /*
990  * EndRun Technologies.
991  * Determine the number of ports available on the device.
992  */
993 #define PCI_VENDOR_ID_ENDRUN			0x7401
994 #define PCI_DEVICE_ID_ENDRUN_1588	0xe100
995 
996 static int pci_endrun_init(struct pci_dev *dev)
997 {
998 	u8 __iomem *p;
999 	unsigned long deviceID;
1000 	unsigned int  number_uarts = 0;
1001 
1002 	/* EndRun device is all 0xexxx */
1003 	if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1004 		(dev->device & 0xf000) != 0xe000)
1005 		return 0;
1006 
1007 	p = pci_iomap(dev, 0, 5);
1008 	if (p == NULL)
1009 		return -ENOMEM;
1010 
1011 	deviceID = ioread32(p);
1012 	/* EndRun device */
1013 	if (deviceID == 0x07000200) {
1014 		number_uarts = ioread8(p + 4);
1015 		dev_dbg(&dev->dev,
1016 			"%d ports detected on EndRun PCI Express device\n",
1017 			number_uarts);
1018 	}
1019 	pci_iounmap(dev, p);
1020 	return number_uarts;
1021 }
1022 
1023 /*
1024  * Oxford Semiconductor Inc.
1025  * Check that device is part of the Tornado range of devices, then determine
1026  * the number of ports available on the device.
1027  */
1028 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1029 {
1030 	u8 __iomem *p;
1031 	unsigned long deviceID;
1032 	unsigned int  number_uarts = 0;
1033 
1034 	/* OxSemi Tornado devices are all 0xCxxx */
1035 	if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1036 	    (dev->device & 0xF000) != 0xC000)
1037 		return 0;
1038 
1039 	p = pci_iomap(dev, 0, 5);
1040 	if (p == NULL)
1041 		return -ENOMEM;
1042 
1043 	deviceID = ioread32(p);
1044 	/* Tornado device */
1045 	if (deviceID == 0x07000200) {
1046 		number_uarts = ioread8(p + 4);
1047 		dev_dbg(&dev->dev,
1048 			"%d ports detected on Oxford PCI Express device\n",
1049 			number_uarts);
1050 	}
1051 	pci_iounmap(dev, p);
1052 	return number_uarts;
1053 }
1054 
1055 static int pci_asix_setup(struct serial_private *priv,
1056 		  const struct pciserial_board *board,
1057 		  struct uart_8250_port *port, int idx)
1058 {
1059 	port->bugs |= UART_BUG_PARITY;
1060 	return pci_default_setup(priv, board, port, idx);
1061 }
1062 
1063 /* Quatech devices have their own extra interface features */
1064 
1065 struct quatech_feature {
1066 	u16 devid;
1067 	bool amcc;
1068 };
1069 
1070 #define QPCR_TEST_FOR1		0x3F
1071 #define QPCR_TEST_GET1		0x00
1072 #define QPCR_TEST_FOR2		0x40
1073 #define QPCR_TEST_GET2		0x40
1074 #define QPCR_TEST_FOR3		0x80
1075 #define QPCR_TEST_GET3		0x40
1076 #define QPCR_TEST_FOR4		0xC0
1077 #define QPCR_TEST_GET4		0x80
1078 
1079 #define QOPR_CLOCK_X1		0x0000
1080 #define QOPR_CLOCK_X2		0x0001
1081 #define QOPR_CLOCK_X4		0x0002
1082 #define QOPR_CLOCK_X8		0x0003
1083 #define QOPR_CLOCK_RATE_MASK	0x0003
1084 
1085 
1086 static struct quatech_feature quatech_cards[] = {
1087 	{ PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1088 	{ PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1089 	{ PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1090 	{ PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1091 	{ PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1092 	{ PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1093 	{ PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1094 	{ PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1095 	{ PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1096 	{ PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1097 	{ PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1098 	{ PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1099 	{ PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1100 	{ PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1101 	{ PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1102 	{ PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1103 	{ PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1104 	{ PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1105 	{ PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1106 	{ 0, }
1107 };
1108 
1109 static int pci_quatech_amcc(u16 devid)
1110 {
1111 	struct quatech_feature *qf = &quatech_cards[0];
1112 	while (qf->devid) {
1113 		if (qf->devid == devid)
1114 			return qf->amcc;
1115 		qf++;
1116 	}
1117 	pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1118 	return 0;
1119 };
1120 
1121 static int pci_quatech_rqopr(struct uart_8250_port *port)
1122 {
1123 	unsigned long base = port->port.iobase;
1124 	u8 LCR, val;
1125 
1126 	LCR = inb(base + UART_LCR);
1127 	outb(0xBF, base + UART_LCR);
1128 	val = inb(base + UART_SCR);
1129 	outb(LCR, base + UART_LCR);
1130 	return val;
1131 }
1132 
1133 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1134 {
1135 	unsigned long base = port->port.iobase;
1136 	u8 LCR;
1137 
1138 	LCR = inb(base + UART_LCR);
1139 	outb(0xBF, base + UART_LCR);
1140 	inb(base + UART_SCR);
1141 	outb(qopr, base + UART_SCR);
1142 	outb(LCR, base + UART_LCR);
1143 }
1144 
1145 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1146 {
1147 	unsigned long base = port->port.iobase;
1148 	u8 LCR, val, qmcr;
1149 
1150 	LCR = inb(base + UART_LCR);
1151 	outb(0xBF, base + UART_LCR);
1152 	val = inb(base + UART_SCR);
1153 	outb(val | 0x10, base + UART_SCR);
1154 	qmcr = inb(base + UART_MCR);
1155 	outb(val, base + UART_SCR);
1156 	outb(LCR, base + UART_LCR);
1157 
1158 	return qmcr;
1159 }
1160 
1161 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1162 {
1163 	unsigned long base = port->port.iobase;
1164 	u8 LCR, val;
1165 
1166 	LCR = inb(base + UART_LCR);
1167 	outb(0xBF, base + UART_LCR);
1168 	val = inb(base + UART_SCR);
1169 	outb(val | 0x10, base + UART_SCR);
1170 	outb(qmcr, base + UART_MCR);
1171 	outb(val, base + UART_SCR);
1172 	outb(LCR, base + UART_LCR);
1173 }
1174 
1175 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1176 {
1177 	unsigned long base = port->port.iobase;
1178 	u8 LCR, val;
1179 
1180 	LCR = inb(base + UART_LCR);
1181 	outb(0xBF, base + UART_LCR);
1182 	val = inb(base + UART_SCR);
1183 	if (val & 0x20) {
1184 		outb(0x80, UART_LCR);
1185 		if (!(inb(UART_SCR) & 0x20)) {
1186 			outb(LCR, base + UART_LCR);
1187 			return 1;
1188 		}
1189 	}
1190 	return 0;
1191 }
1192 
1193 static int pci_quatech_test(struct uart_8250_port *port)
1194 {
1195 	u8 reg, qopr;
1196 
1197 	qopr = pci_quatech_rqopr(port);
1198 	pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1199 	reg = pci_quatech_rqopr(port) & 0xC0;
1200 	if (reg != QPCR_TEST_GET1)
1201 		return -EINVAL;
1202 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1203 	reg = pci_quatech_rqopr(port) & 0xC0;
1204 	if (reg != QPCR_TEST_GET2)
1205 		return -EINVAL;
1206 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1207 	reg = pci_quatech_rqopr(port) & 0xC0;
1208 	if (reg != QPCR_TEST_GET3)
1209 		return -EINVAL;
1210 	pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1211 	reg = pci_quatech_rqopr(port) & 0xC0;
1212 	if (reg != QPCR_TEST_GET4)
1213 		return -EINVAL;
1214 
1215 	pci_quatech_wqopr(port, qopr);
1216 	return 0;
1217 }
1218 
1219 static int pci_quatech_clock(struct uart_8250_port *port)
1220 {
1221 	u8 qopr, reg, set;
1222 	unsigned long clock;
1223 
1224 	if (pci_quatech_test(port) < 0)
1225 		return 1843200;
1226 
1227 	qopr = pci_quatech_rqopr(port);
1228 
1229 	pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1230 	reg = pci_quatech_rqopr(port);
1231 	if (reg & QOPR_CLOCK_X8) {
1232 		clock = 1843200;
1233 		goto out;
1234 	}
1235 	pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1236 	reg = pci_quatech_rqopr(port);
1237 	if (!(reg & QOPR_CLOCK_X8)) {
1238 		clock = 1843200;
1239 		goto out;
1240 	}
1241 	reg &= QOPR_CLOCK_X8;
1242 	if (reg == QOPR_CLOCK_X2) {
1243 		clock =  3685400;
1244 		set = QOPR_CLOCK_X2;
1245 	} else if (reg == QOPR_CLOCK_X4) {
1246 		clock = 7372800;
1247 		set = QOPR_CLOCK_X4;
1248 	} else if (reg == QOPR_CLOCK_X8) {
1249 		clock = 14745600;
1250 		set = QOPR_CLOCK_X8;
1251 	} else {
1252 		clock = 1843200;
1253 		set = QOPR_CLOCK_X1;
1254 	}
1255 	qopr &= ~QOPR_CLOCK_RATE_MASK;
1256 	qopr |= set;
1257 
1258 out:
1259 	pci_quatech_wqopr(port, qopr);
1260 	return clock;
1261 }
1262 
1263 static int pci_quatech_rs422(struct uart_8250_port *port)
1264 {
1265 	u8 qmcr;
1266 	int rs422 = 0;
1267 
1268 	if (!pci_quatech_has_qmcr(port))
1269 		return 0;
1270 	qmcr = pci_quatech_rqmcr(port);
1271 	pci_quatech_wqmcr(port, 0xFF);
1272 	if (pci_quatech_rqmcr(port))
1273 		rs422 = 1;
1274 	pci_quatech_wqmcr(port, qmcr);
1275 	return rs422;
1276 }
1277 
1278 static int pci_quatech_init(struct pci_dev *dev)
1279 {
1280 	if (pci_quatech_amcc(dev->device)) {
1281 		unsigned long base = pci_resource_start(dev, 0);
1282 		if (base) {
1283 			u32 tmp;
1284 
1285 			outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1286 			tmp = inl(base + 0x3c);
1287 			outl(tmp | 0x01000000, base + 0x3c);
1288 			outl(tmp &= ~0x01000000, base + 0x3c);
1289 		}
1290 	}
1291 	return 0;
1292 }
1293 
1294 static int pci_quatech_setup(struct serial_private *priv,
1295 		  const struct pciserial_board *board,
1296 		  struct uart_8250_port *port, int idx)
1297 {
1298 	/* Needed by pci_quatech calls below */
1299 	port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1300 	/* Set up the clocking */
1301 	port->port.uartclk = pci_quatech_clock(port);
1302 	/* For now just warn about RS422 */
1303 	if (pci_quatech_rs422(port))
1304 		pr_warn("quatech: software control of RS422 features not currently supported.\n");
1305 	return pci_default_setup(priv, board, port, idx);
1306 }
1307 
1308 static void pci_quatech_exit(struct pci_dev *dev)
1309 {
1310 }
1311 
1312 static int pci_default_setup(struct serial_private *priv,
1313 		  const struct pciserial_board *board,
1314 		  struct uart_8250_port *port, int idx)
1315 {
1316 	unsigned int bar, offset = board->first_offset, maxnr;
1317 
1318 	bar = FL_GET_BASE(board->flags);
1319 	if (board->flags & FL_BASE_BARS)
1320 		bar += idx;
1321 	else
1322 		offset += idx * board->uart_offset;
1323 
1324 	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1325 		(board->reg_shift + 3);
1326 
1327 	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1328 		return 1;
1329 
1330 	return setup_port(priv, port, bar, offset, board->reg_shift);
1331 }
1332 
1333 static int pci_pericom_setup(struct serial_private *priv,
1334 		  const struct pciserial_board *board,
1335 		  struct uart_8250_port *port, int idx)
1336 {
1337 	unsigned int bar, offset = board->first_offset, maxnr;
1338 
1339 	bar = FL_GET_BASE(board->flags);
1340 	if (board->flags & FL_BASE_BARS)
1341 		bar += idx;
1342 	else
1343 		offset += idx * board->uart_offset;
1344 
1345 	if (idx==3)
1346 		offset = 0x38;
1347 
1348 	maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 		(board->reg_shift + 3);
1350 
1351 	if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1352 		return 1;
1353 
1354 	return setup_port(priv, port, bar, offset, board->reg_shift);
1355 }
1356 
1357 static int
1358 ce4100_serial_setup(struct serial_private *priv,
1359 		  const struct pciserial_board *board,
1360 		  struct uart_8250_port *port, int idx)
1361 {
1362 	int ret;
1363 
1364 	ret = setup_port(priv, port, idx, 0, board->reg_shift);
1365 	port->port.iotype = UPIO_MEM32;
1366 	port->port.type = PORT_XSCALE;
1367 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1368 	port->port.regshift = 2;
1369 
1370 	return ret;
1371 }
1372 
1373 static int
1374 pci_omegapci_setup(struct serial_private *priv,
1375 		      const struct pciserial_board *board,
1376 		      struct uart_8250_port *port, int idx)
1377 {
1378 	return setup_port(priv, port, 2, idx * 8, 0);
1379 }
1380 
1381 static int
1382 pci_brcm_trumanage_setup(struct serial_private *priv,
1383 			 const struct pciserial_board *board,
1384 			 struct uart_8250_port *port, int idx)
1385 {
1386 	int ret = pci_default_setup(priv, board, port, idx);
1387 
1388 	port->port.type = PORT_BRCM_TRUMANAGE;
1389 	port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1390 	return ret;
1391 }
1392 
1393 /* RTS will control by MCR if this bit is 0 */
1394 #define FINTEK_RTS_CONTROL_BY_HW	BIT(4)
1395 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1396 #define FINTEK_RTS_INVERT		BIT(5)
1397 
1398 /* We should do proper H/W transceiver setting before change to RS485 mode */
1399 static int pci_fintek_rs485_config(struct uart_port *port,
1400 			       struct serial_rs485 *rs485)
1401 {
1402 	struct pci_dev *pci_dev = to_pci_dev(port->dev);
1403 	u8 setting;
1404 	u8 *index = (u8 *) port->private_data;
1405 
1406 	pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1407 
1408 	if (!rs485)
1409 		rs485 = &port->rs485;
1410 	else if (rs485->flags & SER_RS485_ENABLED)
1411 		memset(rs485->padding, 0, sizeof(rs485->padding));
1412 	else
1413 		memset(rs485, 0, sizeof(*rs485));
1414 
1415 	/* F81504/508/512 not support RTS delay before or after send */
1416 	rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1417 
1418 	if (rs485->flags & SER_RS485_ENABLED) {
1419 		/* Enable RTS H/W control mode */
1420 		setting |= FINTEK_RTS_CONTROL_BY_HW;
1421 
1422 		if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1423 			/* RTS driving high on TX */
1424 			setting &= ~FINTEK_RTS_INVERT;
1425 		} else {
1426 			/* RTS driving low on TX */
1427 			setting |= FINTEK_RTS_INVERT;
1428 		}
1429 
1430 		rs485->delay_rts_after_send = 0;
1431 		rs485->delay_rts_before_send = 0;
1432 	} else {
1433 		/* Disable RTS H/W control mode */
1434 		setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1435 	}
1436 
1437 	pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1438 
1439 	if (rs485 != &port->rs485)
1440 		port->rs485 = *rs485;
1441 
1442 	return 0;
1443 }
1444 
1445 static int pci_fintek_setup(struct serial_private *priv,
1446 			    const struct pciserial_board *board,
1447 			    struct uart_8250_port *port, int idx)
1448 {
1449 	struct pci_dev *pdev = priv->dev;
1450 	u8 *data;
1451 	u8 config_base;
1452 	u16 iobase;
1453 
1454 	config_base = 0x40 + 0x08 * idx;
1455 
1456 	/* Get the io address from configuration space */
1457 	pci_read_config_word(pdev, config_base + 4, &iobase);
1458 
1459 	dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1460 
1461 	port->port.iotype = UPIO_PORT;
1462 	port->port.iobase = iobase;
1463 	port->port.rs485_config = pci_fintek_rs485_config;
1464 
1465 	data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1466 	if (!data)
1467 		return -ENOMEM;
1468 
1469 	/* preserve index in PCI configuration space */
1470 	*data = idx;
1471 	port->port.private_data = data;
1472 
1473 	return 0;
1474 }
1475 
1476 static int pci_fintek_init(struct pci_dev *dev)
1477 {
1478 	unsigned long iobase;
1479 	u32 max_port, i;
1480 	resource_size_t bar_data[3];
1481 	u8 config_base;
1482 	struct serial_private *priv = pci_get_drvdata(dev);
1483 	struct uart_8250_port *port;
1484 
1485 	if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1486 			!(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1487 			!(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1488 		return -ENODEV;
1489 
1490 	switch (dev->device) {
1491 	case 0x1104: /* 4 ports */
1492 	case 0x1108: /* 8 ports */
1493 		max_port = dev->device & 0xff;
1494 		break;
1495 	case 0x1112: /* 12 ports */
1496 		max_port = 12;
1497 		break;
1498 	default:
1499 		return -EINVAL;
1500 	}
1501 
1502 	/* Get the io address dispatch from the BIOS */
1503 	bar_data[0] = pci_resource_start(dev, 5);
1504 	bar_data[1] = pci_resource_start(dev, 4);
1505 	bar_data[2] = pci_resource_start(dev, 3);
1506 
1507 	for (i = 0; i < max_port; ++i) {
1508 		/* UART0 configuration offset start from 0x40 */
1509 		config_base = 0x40 + 0x08 * i;
1510 
1511 		/* Calculate Real IO Port */
1512 		iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1513 
1514 		/* Enable UART I/O port */
1515 		pci_write_config_byte(dev, config_base + 0x00, 0x01);
1516 
1517 		/* Select 128-byte FIFO and 8x FIFO threshold */
1518 		pci_write_config_byte(dev, config_base + 0x01, 0x33);
1519 
1520 		/* LSB UART */
1521 		pci_write_config_byte(dev, config_base + 0x04,
1522 				(u8)(iobase & 0xff));
1523 
1524 		/* MSB UART */
1525 		pci_write_config_byte(dev, config_base + 0x05,
1526 				(u8)((iobase & 0xff00) >> 8));
1527 
1528 		pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1529 
1530 		if (priv) {
1531 			/* re-apply RS232/485 mode when
1532 			 * pciserial_resume_ports()
1533 			 */
1534 			port = serial8250_get_port(priv->line[i]);
1535 			pci_fintek_rs485_config(&port->port, NULL);
1536 		} else {
1537 			/* First init without port data
1538 			 * force init to RS232 Mode
1539 			 */
1540 			pci_write_config_byte(dev, config_base + 0x07, 0x01);
1541 		}
1542 	}
1543 
1544 	return max_port;
1545 }
1546 
1547 static int skip_tx_en_setup(struct serial_private *priv,
1548 			const struct pciserial_board *board,
1549 			struct uart_8250_port *port, int idx)
1550 {
1551 	port->port.quirks |= UPQ_NO_TXEN_TEST;
1552 	dev_dbg(&priv->dev->dev,
1553 		"serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1554 		priv->dev->vendor, priv->dev->device,
1555 		priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1556 
1557 	return pci_default_setup(priv, board, port, idx);
1558 }
1559 
1560 static void kt_handle_break(struct uart_port *p)
1561 {
1562 	struct uart_8250_port *up = up_to_u8250p(p);
1563 	/*
1564 	 * On receipt of a BI, serial device in Intel ME (Intel
1565 	 * management engine) needs to have its fifos cleared for sane
1566 	 * SOL (Serial Over Lan) output.
1567 	 */
1568 	serial8250_clear_and_reinit_fifos(up);
1569 }
1570 
1571 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1572 {
1573 	struct uart_8250_port *up = up_to_u8250p(p);
1574 	unsigned int val;
1575 
1576 	/*
1577 	 * When the Intel ME (management engine) gets reset its serial
1578 	 * port registers could return 0 momentarily.  Functions like
1579 	 * serial8250_console_write, read and save the IER, perform
1580 	 * some operation and then restore it.  In order to avoid
1581 	 * setting IER register inadvertently to 0, if the value read
1582 	 * is 0, double check with ier value in uart_8250_port and use
1583 	 * that instead.  up->ier should be the same value as what is
1584 	 * currently configured.
1585 	 */
1586 	val = inb(p->iobase + offset);
1587 	if (offset == UART_IER) {
1588 		if (val == 0)
1589 			val = up->ier;
1590 	}
1591 	return val;
1592 }
1593 
1594 static int kt_serial_setup(struct serial_private *priv,
1595 			   const struct pciserial_board *board,
1596 			   struct uart_8250_port *port, int idx)
1597 {
1598 	port->port.flags |= UPF_BUG_THRE;
1599 	port->port.serial_in = kt_serial_in;
1600 	port->port.handle_break = kt_handle_break;
1601 	return skip_tx_en_setup(priv, board, port, idx);
1602 }
1603 
1604 static int pci_eg20t_init(struct pci_dev *dev)
1605 {
1606 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1607 	return -ENODEV;
1608 #else
1609 	return 0;
1610 #endif
1611 }
1612 
1613 static int
1614 pci_wch_ch353_setup(struct serial_private *priv,
1615 		    const struct pciserial_board *board,
1616 		    struct uart_8250_port *port, int idx)
1617 {
1618 	port->port.flags |= UPF_FIXED_TYPE;
1619 	port->port.type = PORT_16550A;
1620 	return pci_default_setup(priv, board, port, idx);
1621 }
1622 
1623 static int
1624 pci_wch_ch355_setup(struct serial_private *priv,
1625 		const struct pciserial_board *board,
1626 		struct uart_8250_port *port, int idx)
1627 {
1628 	port->port.flags |= UPF_FIXED_TYPE;
1629 	port->port.type = PORT_16550A;
1630 	return pci_default_setup(priv, board, port, idx);
1631 }
1632 
1633 static int
1634 pci_wch_ch38x_setup(struct serial_private *priv,
1635 		    const struct pciserial_board *board,
1636 		    struct uart_8250_port *port, int idx)
1637 {
1638 	port->port.flags |= UPF_FIXED_TYPE;
1639 	port->port.type = PORT_16850;
1640 	return pci_default_setup(priv, board, port, idx);
1641 }
1642 
1643 #define PCI_VENDOR_ID_SBSMODULARIO	0x124B
1644 #define PCI_SUBVENDOR_ID_SBSMODULARIO	0x124B
1645 #define PCI_DEVICE_ID_OCTPRO		0x0001
1646 #define PCI_SUBDEVICE_ID_OCTPRO232	0x0108
1647 #define PCI_SUBDEVICE_ID_OCTPRO422	0x0208
1648 #define PCI_SUBDEVICE_ID_POCTAL232	0x0308
1649 #define PCI_SUBDEVICE_ID_POCTAL422	0x0408
1650 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00	0x2500
1651 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30	0x2530
1652 #define PCI_VENDOR_ID_ADVANTECH		0x13fe
1653 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1654 #define PCI_DEVICE_ID_ADVANTECH_PCI3620	0x3620
1655 #define PCI_DEVICE_ID_ADVANTECH_PCI3618	0x3618
1656 #define PCI_DEVICE_ID_ADVANTECH_PCIf618	0xf618
1657 #define PCI_DEVICE_ID_TITAN_200I	0x8028
1658 #define PCI_DEVICE_ID_TITAN_400I	0x8048
1659 #define PCI_DEVICE_ID_TITAN_800I	0x8088
1660 #define PCI_DEVICE_ID_TITAN_800EH	0xA007
1661 #define PCI_DEVICE_ID_TITAN_800EHB	0xA008
1662 #define PCI_DEVICE_ID_TITAN_400EH	0xA009
1663 #define PCI_DEVICE_ID_TITAN_100E	0xA010
1664 #define PCI_DEVICE_ID_TITAN_200E	0xA012
1665 #define PCI_DEVICE_ID_TITAN_400E	0xA013
1666 #define PCI_DEVICE_ID_TITAN_800E	0xA014
1667 #define PCI_DEVICE_ID_TITAN_200EI	0xA016
1668 #define PCI_DEVICE_ID_TITAN_200EISI	0xA017
1669 #define PCI_DEVICE_ID_TITAN_200V3	0xA306
1670 #define PCI_DEVICE_ID_TITAN_400V3	0xA310
1671 #define PCI_DEVICE_ID_TITAN_410V3	0xA312
1672 #define PCI_DEVICE_ID_TITAN_800V3	0xA314
1673 #define PCI_DEVICE_ID_TITAN_800V3B	0xA315
1674 #define PCI_DEVICE_ID_OXSEMI_16PCI958	0x9538
1675 #define PCIE_DEVICE_ID_NEO_2_OX_IBM	0x00F6
1676 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA	0xc001
1677 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1678 #define PCI_VENDOR_ID_WCH		0x4348
1679 #define PCI_DEVICE_ID_WCH_CH352_2S	0x3253
1680 #define PCI_DEVICE_ID_WCH_CH353_4S	0x3453
1681 #define PCI_DEVICE_ID_WCH_CH353_2S1PF	0x5046
1682 #define PCI_DEVICE_ID_WCH_CH353_1S1P	0x5053
1683 #define PCI_DEVICE_ID_WCH_CH353_2S1P	0x7053
1684 #define PCI_DEVICE_ID_WCH_CH355_4S	0x7173
1685 #define PCI_VENDOR_ID_AGESTAR		0x5372
1686 #define PCI_DEVICE_ID_AGESTAR_9375	0x6872
1687 #define PCI_VENDOR_ID_ASIX		0x9710
1688 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1689 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1690 
1691 #define PCI_VENDOR_ID_SUNIX		0x1fd4
1692 #define PCI_DEVICE_ID_SUNIX_1999	0x1999
1693 
1694 #define PCIE_VENDOR_ID_WCH		0x1c00
1695 #define PCIE_DEVICE_ID_WCH_CH382_2S1P	0x3250
1696 #define PCIE_DEVICE_ID_WCH_CH384_4S	0x3470
1697 #define PCIE_DEVICE_ID_WCH_CH382_2S	0x3253
1698 
1699 #define PCI_VENDOR_ID_PERICOM			0x12D8
1700 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951	0x7951
1701 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952	0x7952
1702 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954	0x7954
1703 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958	0x7958
1704 
1705 #define PCI_VENDOR_ID_ACCESIO			0x494f
1706 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB	0x1051
1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S	0x1053
1708 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB	0x105C
1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S	0x105E
1710 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB	0x1091
1711 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2	0x1093
1712 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB	0x1099
1713 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4	0x109B
1714 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB	0x10D1
1715 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM	0x10D3
1716 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB	0x10DA
1717 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM	0x10DC
1718 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1	0x1108
1719 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2	0x1110
1720 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2	0x1111
1721 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4	0x1118
1722 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4	0x1119
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S	0x1152
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S	0x115A
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2	0x1190
1726 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2	0x1191
1727 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4	0x1198
1728 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4	0x1199
1729 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM	0x11D0
1730 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4	0x105A
1731 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4	0x105B
1732 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8	0x106A
1733 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8	0x106B
1734 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4	0x1098
1735 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8	0x10A9
1736 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM	0x10D9
1737 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM	0x10E9
1738 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM	0x11D8
1739 
1740 
1741 
1742 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1743 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584	0x1584
1744 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588	0x1588
1745 
1746 /*
1747  * Master list of serial port init/setup/exit quirks.
1748  * This does not describe the general nature of the port.
1749  * (ie, baud base, number and location of ports, etc)
1750  *
1751  * This list is ordered alphabetically by vendor then device.
1752  * Specific entries must come before more generic entries.
1753  */
1754 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1755 	/*
1756 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
1757 	*/
1758 	{
1759 		.vendor         = PCI_VENDOR_ID_AMCC,
1760 		.device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1761 		.subvendor      = PCI_ANY_ID,
1762 		.subdevice      = PCI_ANY_ID,
1763 		.setup          = addidata_apci7800_setup,
1764 	},
1765 	/*
1766 	 * AFAVLAB cards - these may be called via parport_serial
1767 	 *  It is not clear whether this applies to all products.
1768 	 */
1769 	{
1770 		.vendor		= PCI_VENDOR_ID_AFAVLAB,
1771 		.device		= PCI_ANY_ID,
1772 		.subvendor	= PCI_ANY_ID,
1773 		.subdevice	= PCI_ANY_ID,
1774 		.setup		= afavlab_setup,
1775 	},
1776 	/*
1777 	 * HP Diva
1778 	 */
1779 	{
1780 		.vendor		= PCI_VENDOR_ID_HP,
1781 		.device		= PCI_DEVICE_ID_HP_DIVA,
1782 		.subvendor	= PCI_ANY_ID,
1783 		.subdevice	= PCI_ANY_ID,
1784 		.init		= pci_hp_diva_init,
1785 		.setup		= pci_hp_diva_setup,
1786 	},
1787 	/*
1788 	 * Intel
1789 	 */
1790 	{
1791 		.vendor		= PCI_VENDOR_ID_INTEL,
1792 		.device		= PCI_DEVICE_ID_INTEL_80960_RP,
1793 		.subvendor	= 0xe4bf,
1794 		.subdevice	= PCI_ANY_ID,
1795 		.init		= pci_inteli960ni_init,
1796 		.setup		= pci_default_setup,
1797 	},
1798 	{
1799 		.vendor		= PCI_VENDOR_ID_INTEL,
1800 		.device		= PCI_DEVICE_ID_INTEL_8257X_SOL,
1801 		.subvendor	= PCI_ANY_ID,
1802 		.subdevice	= PCI_ANY_ID,
1803 		.setup		= skip_tx_en_setup,
1804 	},
1805 	{
1806 		.vendor		= PCI_VENDOR_ID_INTEL,
1807 		.device		= PCI_DEVICE_ID_INTEL_82573L_SOL,
1808 		.subvendor	= PCI_ANY_ID,
1809 		.subdevice	= PCI_ANY_ID,
1810 		.setup		= skip_tx_en_setup,
1811 	},
1812 	{
1813 		.vendor		= PCI_VENDOR_ID_INTEL,
1814 		.device		= PCI_DEVICE_ID_INTEL_82573E_SOL,
1815 		.subvendor	= PCI_ANY_ID,
1816 		.subdevice	= PCI_ANY_ID,
1817 		.setup		= skip_tx_en_setup,
1818 	},
1819 	{
1820 		.vendor		= PCI_VENDOR_ID_INTEL,
1821 		.device		= PCI_DEVICE_ID_INTEL_CE4100_UART,
1822 		.subvendor	= PCI_ANY_ID,
1823 		.subdevice	= PCI_ANY_ID,
1824 		.setup		= ce4100_serial_setup,
1825 	},
1826 	{
1827 		.vendor		= PCI_VENDOR_ID_INTEL,
1828 		.device		= PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1829 		.subvendor	= PCI_ANY_ID,
1830 		.subdevice	= PCI_ANY_ID,
1831 		.setup		= kt_serial_setup,
1832 	},
1833 	/*
1834 	 * ITE
1835 	 */
1836 	{
1837 		.vendor		= PCI_VENDOR_ID_ITE,
1838 		.device		= PCI_DEVICE_ID_ITE_8872,
1839 		.subvendor	= PCI_ANY_ID,
1840 		.subdevice	= PCI_ANY_ID,
1841 		.init		= pci_ite887x_init,
1842 		.setup		= pci_default_setup,
1843 		.exit		= pci_ite887x_exit,
1844 	},
1845 	/*
1846 	 * National Instruments
1847 	 */
1848 	{
1849 		.vendor		= PCI_VENDOR_ID_NI,
1850 		.device		= PCI_DEVICE_ID_NI_PCI23216,
1851 		.subvendor	= PCI_ANY_ID,
1852 		.subdevice	= PCI_ANY_ID,
1853 		.init		= pci_ni8420_init,
1854 		.setup		= pci_default_setup,
1855 		.exit		= pci_ni8420_exit,
1856 	},
1857 	{
1858 		.vendor		= PCI_VENDOR_ID_NI,
1859 		.device		= PCI_DEVICE_ID_NI_PCI2328,
1860 		.subvendor	= PCI_ANY_ID,
1861 		.subdevice	= PCI_ANY_ID,
1862 		.init		= pci_ni8420_init,
1863 		.setup		= pci_default_setup,
1864 		.exit		= pci_ni8420_exit,
1865 	},
1866 	{
1867 		.vendor		= PCI_VENDOR_ID_NI,
1868 		.device		= PCI_DEVICE_ID_NI_PCI2324,
1869 		.subvendor	= PCI_ANY_ID,
1870 		.subdevice	= PCI_ANY_ID,
1871 		.init		= pci_ni8420_init,
1872 		.setup		= pci_default_setup,
1873 		.exit		= pci_ni8420_exit,
1874 	},
1875 	{
1876 		.vendor		= PCI_VENDOR_ID_NI,
1877 		.device		= PCI_DEVICE_ID_NI_PCI2322,
1878 		.subvendor	= PCI_ANY_ID,
1879 		.subdevice	= PCI_ANY_ID,
1880 		.init		= pci_ni8420_init,
1881 		.setup		= pci_default_setup,
1882 		.exit		= pci_ni8420_exit,
1883 	},
1884 	{
1885 		.vendor		= PCI_VENDOR_ID_NI,
1886 		.device		= PCI_DEVICE_ID_NI_PCI2324I,
1887 		.subvendor	= PCI_ANY_ID,
1888 		.subdevice	= PCI_ANY_ID,
1889 		.init		= pci_ni8420_init,
1890 		.setup		= pci_default_setup,
1891 		.exit		= pci_ni8420_exit,
1892 	},
1893 	{
1894 		.vendor		= PCI_VENDOR_ID_NI,
1895 		.device		= PCI_DEVICE_ID_NI_PCI2322I,
1896 		.subvendor	= PCI_ANY_ID,
1897 		.subdevice	= PCI_ANY_ID,
1898 		.init		= pci_ni8420_init,
1899 		.setup		= pci_default_setup,
1900 		.exit		= pci_ni8420_exit,
1901 	},
1902 	{
1903 		.vendor		= PCI_VENDOR_ID_NI,
1904 		.device		= PCI_DEVICE_ID_NI_PXI8420_23216,
1905 		.subvendor	= PCI_ANY_ID,
1906 		.subdevice	= PCI_ANY_ID,
1907 		.init		= pci_ni8420_init,
1908 		.setup		= pci_default_setup,
1909 		.exit		= pci_ni8420_exit,
1910 	},
1911 	{
1912 		.vendor		= PCI_VENDOR_ID_NI,
1913 		.device		= PCI_DEVICE_ID_NI_PXI8420_2328,
1914 		.subvendor	= PCI_ANY_ID,
1915 		.subdevice	= PCI_ANY_ID,
1916 		.init		= pci_ni8420_init,
1917 		.setup		= pci_default_setup,
1918 		.exit		= pci_ni8420_exit,
1919 	},
1920 	{
1921 		.vendor		= PCI_VENDOR_ID_NI,
1922 		.device		= PCI_DEVICE_ID_NI_PXI8420_2324,
1923 		.subvendor	= PCI_ANY_ID,
1924 		.subdevice	= PCI_ANY_ID,
1925 		.init		= pci_ni8420_init,
1926 		.setup		= pci_default_setup,
1927 		.exit		= pci_ni8420_exit,
1928 	},
1929 	{
1930 		.vendor		= PCI_VENDOR_ID_NI,
1931 		.device		= PCI_DEVICE_ID_NI_PXI8420_2322,
1932 		.subvendor	= PCI_ANY_ID,
1933 		.subdevice	= PCI_ANY_ID,
1934 		.init		= pci_ni8420_init,
1935 		.setup		= pci_default_setup,
1936 		.exit		= pci_ni8420_exit,
1937 	},
1938 	{
1939 		.vendor		= PCI_VENDOR_ID_NI,
1940 		.device		= PCI_DEVICE_ID_NI_PXI8422_2324,
1941 		.subvendor	= PCI_ANY_ID,
1942 		.subdevice	= PCI_ANY_ID,
1943 		.init		= pci_ni8420_init,
1944 		.setup		= pci_default_setup,
1945 		.exit		= pci_ni8420_exit,
1946 	},
1947 	{
1948 		.vendor		= PCI_VENDOR_ID_NI,
1949 		.device		= PCI_DEVICE_ID_NI_PXI8422_2322,
1950 		.subvendor	= PCI_ANY_ID,
1951 		.subdevice	= PCI_ANY_ID,
1952 		.init		= pci_ni8420_init,
1953 		.setup		= pci_default_setup,
1954 		.exit		= pci_ni8420_exit,
1955 	},
1956 	{
1957 		.vendor		= PCI_VENDOR_ID_NI,
1958 		.device		= PCI_ANY_ID,
1959 		.subvendor	= PCI_ANY_ID,
1960 		.subdevice	= PCI_ANY_ID,
1961 		.init		= pci_ni8430_init,
1962 		.setup		= pci_ni8430_setup,
1963 		.exit		= pci_ni8430_exit,
1964 	},
1965 	/* Quatech */
1966 	{
1967 		.vendor		= PCI_VENDOR_ID_QUATECH,
1968 		.device		= PCI_ANY_ID,
1969 		.subvendor	= PCI_ANY_ID,
1970 		.subdevice	= PCI_ANY_ID,
1971 		.init		= pci_quatech_init,
1972 		.setup		= pci_quatech_setup,
1973 		.exit		= pci_quatech_exit,
1974 	},
1975 	/*
1976 	 * Panacom
1977 	 */
1978 	{
1979 		.vendor		= PCI_VENDOR_ID_PANACOM,
1980 		.device		= PCI_DEVICE_ID_PANACOM_QUADMODEM,
1981 		.subvendor	= PCI_ANY_ID,
1982 		.subdevice	= PCI_ANY_ID,
1983 		.init		= pci_plx9050_init,
1984 		.setup		= pci_default_setup,
1985 		.exit		= pci_plx9050_exit,
1986 	},
1987 	{
1988 		.vendor		= PCI_VENDOR_ID_PANACOM,
1989 		.device		= PCI_DEVICE_ID_PANACOM_DUALMODEM,
1990 		.subvendor	= PCI_ANY_ID,
1991 		.subdevice	= PCI_ANY_ID,
1992 		.init		= pci_plx9050_init,
1993 		.setup		= pci_default_setup,
1994 		.exit		= pci_plx9050_exit,
1995 	},
1996 	/*
1997 	 * Pericom (Only 7954 - It have a offset jump for port 4)
1998 	 */
1999 	{
2000 		.vendor		= PCI_VENDOR_ID_PERICOM,
2001 		.device		= PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2002 		.subvendor	= PCI_ANY_ID,
2003 		.subdevice	= PCI_ANY_ID,
2004 		.setup		= pci_pericom_setup,
2005 	},
2006 	/*
2007 	 * PLX
2008 	 */
2009 	{
2010 		.vendor		= PCI_VENDOR_ID_PLX,
2011 		.device		= PCI_DEVICE_ID_PLX_9050,
2012 		.subvendor	= PCI_SUBVENDOR_ID_EXSYS,
2013 		.subdevice	= PCI_SUBDEVICE_ID_EXSYS_4055,
2014 		.init		= pci_plx9050_init,
2015 		.setup		= pci_default_setup,
2016 		.exit		= pci_plx9050_exit,
2017 	},
2018 	{
2019 		.vendor		= PCI_VENDOR_ID_PLX,
2020 		.device		= PCI_DEVICE_ID_PLX_9050,
2021 		.subvendor	= PCI_SUBVENDOR_ID_KEYSPAN,
2022 		.subdevice	= PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2023 		.init		= pci_plx9050_init,
2024 		.setup		= pci_default_setup,
2025 		.exit		= pci_plx9050_exit,
2026 	},
2027 	{
2028 		.vendor		= PCI_VENDOR_ID_PLX,
2029 		.device		= PCI_DEVICE_ID_PLX_ROMULUS,
2030 		.subvendor	= PCI_VENDOR_ID_PLX,
2031 		.subdevice	= PCI_DEVICE_ID_PLX_ROMULUS,
2032 		.init		= pci_plx9050_init,
2033 		.setup		= pci_default_setup,
2034 		.exit		= pci_plx9050_exit,
2035 	},
2036 	/*
2037 	 * SBS Technologies, Inc., PMC-OCTALPRO 232
2038 	 */
2039 	{
2040 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2041 		.device		= PCI_DEVICE_ID_OCTPRO,
2042 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2043 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO232,
2044 		.init		= sbs_init,
2045 		.setup		= sbs_setup,
2046 		.exit		= sbs_exit,
2047 	},
2048 	/*
2049 	 * SBS Technologies, Inc., PMC-OCTALPRO 422
2050 	 */
2051 	{
2052 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2053 		.device		= PCI_DEVICE_ID_OCTPRO,
2054 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2055 		.subdevice	= PCI_SUBDEVICE_ID_OCTPRO422,
2056 		.init		= sbs_init,
2057 		.setup		= sbs_setup,
2058 		.exit		= sbs_exit,
2059 	},
2060 	/*
2061 	 * SBS Technologies, Inc., P-Octal 232
2062 	 */
2063 	{
2064 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2065 		.device		= PCI_DEVICE_ID_OCTPRO,
2066 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2067 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL232,
2068 		.init		= sbs_init,
2069 		.setup		= sbs_setup,
2070 		.exit		= sbs_exit,
2071 	},
2072 	/*
2073 	 * SBS Technologies, Inc., P-Octal 422
2074 	 */
2075 	{
2076 		.vendor		= PCI_VENDOR_ID_SBSMODULARIO,
2077 		.device		= PCI_DEVICE_ID_OCTPRO,
2078 		.subvendor	= PCI_SUBVENDOR_ID_SBSMODULARIO,
2079 		.subdevice	= PCI_SUBDEVICE_ID_POCTAL422,
2080 		.init		= sbs_init,
2081 		.setup		= sbs_setup,
2082 		.exit		= sbs_exit,
2083 	},
2084 	/*
2085 	 * SIIG cards - these may be called via parport_serial
2086 	 */
2087 	{
2088 		.vendor		= PCI_VENDOR_ID_SIIG,
2089 		.device		= PCI_ANY_ID,
2090 		.subvendor	= PCI_ANY_ID,
2091 		.subdevice	= PCI_ANY_ID,
2092 		.init		= pci_siig_init,
2093 		.setup		= pci_siig_setup,
2094 	},
2095 	/*
2096 	 * Titan cards
2097 	 */
2098 	{
2099 		.vendor		= PCI_VENDOR_ID_TITAN,
2100 		.device		= PCI_DEVICE_ID_TITAN_400L,
2101 		.subvendor	= PCI_ANY_ID,
2102 		.subdevice	= PCI_ANY_ID,
2103 		.setup		= titan_400l_800l_setup,
2104 	},
2105 	{
2106 		.vendor		= PCI_VENDOR_ID_TITAN,
2107 		.device		= PCI_DEVICE_ID_TITAN_800L,
2108 		.subvendor	= PCI_ANY_ID,
2109 		.subdevice	= PCI_ANY_ID,
2110 		.setup		= titan_400l_800l_setup,
2111 	},
2112 	/*
2113 	 * Timedia cards
2114 	 */
2115 	{
2116 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2117 		.device		= PCI_DEVICE_ID_TIMEDIA_1889,
2118 		.subvendor	= PCI_VENDOR_ID_TIMEDIA,
2119 		.subdevice	= PCI_ANY_ID,
2120 		.probe		= pci_timedia_probe,
2121 		.init		= pci_timedia_init,
2122 		.setup		= pci_timedia_setup,
2123 	},
2124 	{
2125 		.vendor		= PCI_VENDOR_ID_TIMEDIA,
2126 		.device		= PCI_ANY_ID,
2127 		.subvendor	= PCI_ANY_ID,
2128 		.subdevice	= PCI_ANY_ID,
2129 		.setup		= pci_timedia_setup,
2130 	},
2131 	/*
2132 	 * SUNIX (Timedia) cards
2133 	 * Do not "probe" for these cards as there is at least one combination
2134 	 * card that should be handled by parport_pc that doesn't match the
2135 	 * rule in pci_timedia_probe.
2136 	 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2137 	 * There are some boards with part number SER5037AL that report
2138 	 * subdevice ID 0x0002.
2139 	 */
2140 	{
2141 		.vendor		= PCI_VENDOR_ID_SUNIX,
2142 		.device		= PCI_DEVICE_ID_SUNIX_1999,
2143 		.subvendor	= PCI_VENDOR_ID_SUNIX,
2144 		.subdevice	= PCI_ANY_ID,
2145 		.init		= pci_timedia_init,
2146 		.setup		= pci_timedia_setup,
2147 	},
2148 	/*
2149 	 * Xircom cards
2150 	 */
2151 	{
2152 		.vendor		= PCI_VENDOR_ID_XIRCOM,
2153 		.device		= PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2154 		.subvendor	= PCI_ANY_ID,
2155 		.subdevice	= PCI_ANY_ID,
2156 		.init		= pci_xircom_init,
2157 		.setup		= pci_default_setup,
2158 	},
2159 	/*
2160 	 * Netmos cards - these may be called via parport_serial
2161 	 */
2162 	{
2163 		.vendor		= PCI_VENDOR_ID_NETMOS,
2164 		.device		= PCI_ANY_ID,
2165 		.subvendor	= PCI_ANY_ID,
2166 		.subdevice	= PCI_ANY_ID,
2167 		.init		= pci_netmos_init,
2168 		.setup		= pci_netmos_9900_setup,
2169 	},
2170 	/*
2171 	 * EndRun Technologies
2172 	*/
2173 	{
2174 		.vendor		= PCI_VENDOR_ID_ENDRUN,
2175 		.device		= PCI_ANY_ID,
2176 		.subvendor	= PCI_ANY_ID,
2177 		.subdevice	= PCI_ANY_ID,
2178 		.init		= pci_endrun_init,
2179 		.setup		= pci_default_setup,
2180 	},
2181 	/*
2182 	 * For Oxford Semiconductor Tornado based devices
2183 	 */
2184 	{
2185 		.vendor		= PCI_VENDOR_ID_OXSEMI,
2186 		.device		= PCI_ANY_ID,
2187 		.subvendor	= PCI_ANY_ID,
2188 		.subdevice	= PCI_ANY_ID,
2189 		.init		= pci_oxsemi_tornado_init,
2190 		.setup		= pci_default_setup,
2191 	},
2192 	{
2193 		.vendor		= PCI_VENDOR_ID_MAINPINE,
2194 		.device		= PCI_ANY_ID,
2195 		.subvendor	= PCI_ANY_ID,
2196 		.subdevice	= PCI_ANY_ID,
2197 		.init		= pci_oxsemi_tornado_init,
2198 		.setup		= pci_default_setup,
2199 	},
2200 	{
2201 		.vendor		= PCI_VENDOR_ID_DIGI,
2202 		.device		= PCIE_DEVICE_ID_NEO_2_OX_IBM,
2203 		.subvendor		= PCI_SUBVENDOR_ID_IBM,
2204 		.subdevice		= PCI_ANY_ID,
2205 		.init			= pci_oxsemi_tornado_init,
2206 		.setup		= pci_default_setup,
2207 	},
2208 	{
2209 		.vendor         = PCI_VENDOR_ID_INTEL,
2210 		.device         = 0x8811,
2211 		.subvendor	= PCI_ANY_ID,
2212 		.subdevice	= PCI_ANY_ID,
2213 		.init		= pci_eg20t_init,
2214 		.setup		= pci_default_setup,
2215 	},
2216 	{
2217 		.vendor         = PCI_VENDOR_ID_INTEL,
2218 		.device         = 0x8812,
2219 		.subvendor	= PCI_ANY_ID,
2220 		.subdevice	= PCI_ANY_ID,
2221 		.init		= pci_eg20t_init,
2222 		.setup		= pci_default_setup,
2223 	},
2224 	{
2225 		.vendor         = PCI_VENDOR_ID_INTEL,
2226 		.device         = 0x8813,
2227 		.subvendor	= PCI_ANY_ID,
2228 		.subdevice	= PCI_ANY_ID,
2229 		.init		= pci_eg20t_init,
2230 		.setup		= pci_default_setup,
2231 	},
2232 	{
2233 		.vendor         = PCI_VENDOR_ID_INTEL,
2234 		.device         = 0x8814,
2235 		.subvendor	= PCI_ANY_ID,
2236 		.subdevice	= PCI_ANY_ID,
2237 		.init		= pci_eg20t_init,
2238 		.setup		= pci_default_setup,
2239 	},
2240 	{
2241 		.vendor         = 0x10DB,
2242 		.device         = 0x8027,
2243 		.subvendor	= PCI_ANY_ID,
2244 		.subdevice	= PCI_ANY_ID,
2245 		.init		= pci_eg20t_init,
2246 		.setup		= pci_default_setup,
2247 	},
2248 	{
2249 		.vendor         = 0x10DB,
2250 		.device         = 0x8028,
2251 		.subvendor	= PCI_ANY_ID,
2252 		.subdevice	= PCI_ANY_ID,
2253 		.init		= pci_eg20t_init,
2254 		.setup		= pci_default_setup,
2255 	},
2256 	{
2257 		.vendor         = 0x10DB,
2258 		.device         = 0x8029,
2259 		.subvendor	= PCI_ANY_ID,
2260 		.subdevice	= PCI_ANY_ID,
2261 		.init		= pci_eg20t_init,
2262 		.setup		= pci_default_setup,
2263 	},
2264 	{
2265 		.vendor         = 0x10DB,
2266 		.device         = 0x800C,
2267 		.subvendor	= PCI_ANY_ID,
2268 		.subdevice	= PCI_ANY_ID,
2269 		.init		= pci_eg20t_init,
2270 		.setup		= pci_default_setup,
2271 	},
2272 	{
2273 		.vendor         = 0x10DB,
2274 		.device         = 0x800D,
2275 		.subvendor	= PCI_ANY_ID,
2276 		.subdevice	= PCI_ANY_ID,
2277 		.init		= pci_eg20t_init,
2278 		.setup		= pci_default_setup,
2279 	},
2280 	/*
2281 	 * Cronyx Omega PCI (PLX-chip based)
2282 	 */
2283 	{
2284 		.vendor		= PCI_VENDOR_ID_PLX,
2285 		.device		= PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2286 		.subvendor	= PCI_ANY_ID,
2287 		.subdevice	= PCI_ANY_ID,
2288 		.setup		= pci_omegapci_setup,
2289 	},
2290 	/* WCH CH353 1S1P card (16550 clone) */
2291 	{
2292 		.vendor         = PCI_VENDOR_ID_WCH,
2293 		.device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2294 		.subvendor      = PCI_ANY_ID,
2295 		.subdevice      = PCI_ANY_ID,
2296 		.setup          = pci_wch_ch353_setup,
2297 	},
2298 	/* WCH CH353 2S1P card (16550 clone) */
2299 	{
2300 		.vendor         = PCI_VENDOR_ID_WCH,
2301 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2302 		.subvendor      = PCI_ANY_ID,
2303 		.subdevice      = PCI_ANY_ID,
2304 		.setup          = pci_wch_ch353_setup,
2305 	},
2306 	/* WCH CH353 4S card (16550 clone) */
2307 	{
2308 		.vendor         = PCI_VENDOR_ID_WCH,
2309 		.device         = PCI_DEVICE_ID_WCH_CH353_4S,
2310 		.subvendor      = PCI_ANY_ID,
2311 		.subdevice      = PCI_ANY_ID,
2312 		.setup          = pci_wch_ch353_setup,
2313 	},
2314 	/* WCH CH353 2S1PF card (16550 clone) */
2315 	{
2316 		.vendor         = PCI_VENDOR_ID_WCH,
2317 		.device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2318 		.subvendor      = PCI_ANY_ID,
2319 		.subdevice      = PCI_ANY_ID,
2320 		.setup          = pci_wch_ch353_setup,
2321 	},
2322 	/* WCH CH352 2S card (16550 clone) */
2323 	{
2324 		.vendor		= PCI_VENDOR_ID_WCH,
2325 		.device		= PCI_DEVICE_ID_WCH_CH352_2S,
2326 		.subvendor	= PCI_ANY_ID,
2327 		.subdevice	= PCI_ANY_ID,
2328 		.setup		= pci_wch_ch353_setup,
2329 	},
2330 	/* WCH CH355 4S card (16550 clone) */
2331 	{
2332 		.vendor		= PCI_VENDOR_ID_WCH,
2333 		.device		= PCI_DEVICE_ID_WCH_CH355_4S,
2334 		.subvendor	= PCI_ANY_ID,
2335 		.subdevice	= PCI_ANY_ID,
2336 		.setup		= pci_wch_ch355_setup,
2337 	},
2338 	/* WCH CH382 2S card (16850 clone) */
2339 	{
2340 		.vendor         = PCIE_VENDOR_ID_WCH,
2341 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2342 		.subvendor      = PCI_ANY_ID,
2343 		.subdevice      = PCI_ANY_ID,
2344 		.setup          = pci_wch_ch38x_setup,
2345 	},
2346 	/* WCH CH382 2S1P card (16850 clone) */
2347 	{
2348 		.vendor         = PCIE_VENDOR_ID_WCH,
2349 		.device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2350 		.subvendor      = PCI_ANY_ID,
2351 		.subdevice      = PCI_ANY_ID,
2352 		.setup          = pci_wch_ch38x_setup,
2353 	},
2354 	/* WCH CH384 4S card (16850 clone) */
2355 	{
2356 		.vendor         = PCIE_VENDOR_ID_WCH,
2357 		.device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2358 		.subvendor      = PCI_ANY_ID,
2359 		.subdevice      = PCI_ANY_ID,
2360 		.setup          = pci_wch_ch38x_setup,
2361 	},
2362 	/*
2363 	 * ASIX devices with FIFO bug
2364 	 */
2365 	{
2366 		.vendor		= PCI_VENDOR_ID_ASIX,
2367 		.device		= PCI_ANY_ID,
2368 		.subvendor	= PCI_ANY_ID,
2369 		.subdevice	= PCI_ANY_ID,
2370 		.setup		= pci_asix_setup,
2371 	},
2372 	/*
2373 	 * Broadcom TruManage (NetXtreme)
2374 	 */
2375 	{
2376 		.vendor		= PCI_VENDOR_ID_BROADCOM,
2377 		.device		= PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2378 		.subvendor	= PCI_ANY_ID,
2379 		.subdevice	= PCI_ANY_ID,
2380 		.setup		= pci_brcm_trumanage_setup,
2381 	},
2382 	{
2383 		.vendor		= 0x1c29,
2384 		.device		= 0x1104,
2385 		.subvendor	= PCI_ANY_ID,
2386 		.subdevice	= PCI_ANY_ID,
2387 		.setup		= pci_fintek_setup,
2388 		.init		= pci_fintek_init,
2389 	},
2390 	{
2391 		.vendor		= 0x1c29,
2392 		.device		= 0x1108,
2393 		.subvendor	= PCI_ANY_ID,
2394 		.subdevice	= PCI_ANY_ID,
2395 		.setup		= pci_fintek_setup,
2396 		.init		= pci_fintek_init,
2397 	},
2398 	{
2399 		.vendor		= 0x1c29,
2400 		.device		= 0x1112,
2401 		.subvendor	= PCI_ANY_ID,
2402 		.subdevice	= PCI_ANY_ID,
2403 		.setup		= pci_fintek_setup,
2404 		.init		= pci_fintek_init,
2405 	},
2406 
2407 	/*
2408 	 * Default "match everything" terminator entry
2409 	 */
2410 	{
2411 		.vendor		= PCI_ANY_ID,
2412 		.device		= PCI_ANY_ID,
2413 		.subvendor	= PCI_ANY_ID,
2414 		.subdevice	= PCI_ANY_ID,
2415 		.setup		= pci_default_setup,
2416 	}
2417 };
2418 
2419 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2420 {
2421 	return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2422 }
2423 
2424 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2425 {
2426 	struct pci_serial_quirk *quirk;
2427 
2428 	for (quirk = pci_serial_quirks; ; quirk++)
2429 		if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2430 		    quirk_id_matches(quirk->device, dev->device) &&
2431 		    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2432 		    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2433 			break;
2434 	return quirk;
2435 }
2436 
2437 static inline int get_pci_irq(struct pci_dev *dev,
2438 				const struct pciserial_board *board)
2439 {
2440 	if (board->flags & FL_NOIRQ)
2441 		return 0;
2442 	else
2443 		return dev->irq;
2444 }
2445 
2446 /*
2447  * This is the configuration table for all of the PCI serial boards
2448  * which we support.  It is directly indexed by the pci_board_num_t enum
2449  * value, which is encoded in the pci_device_id PCI probe table's
2450  * driver_data member.
2451  *
2452  * The makeup of these names are:
2453  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2454  *
2455  *  bn		= PCI BAR number
2456  *  bt		= Index using PCI BARs
2457  *  n		= number of serial ports
2458  *  baud	= baud rate
2459  *  offsetinhex	= offset for each sequential port (in hex)
2460  *
2461  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2462  *
2463  * Please note: in theory if n = 1, _bt infix should make no difference.
2464  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2465  */
2466 enum pci_board_num_t {
2467 	pbn_default = 0,
2468 
2469 	pbn_b0_1_115200,
2470 	pbn_b0_2_115200,
2471 	pbn_b0_4_115200,
2472 	pbn_b0_5_115200,
2473 	pbn_b0_8_115200,
2474 
2475 	pbn_b0_1_921600,
2476 	pbn_b0_2_921600,
2477 	pbn_b0_4_921600,
2478 
2479 	pbn_b0_2_1130000,
2480 
2481 	pbn_b0_4_1152000,
2482 
2483 	pbn_b0_4_1250000,
2484 
2485 	pbn_b0_2_1843200,
2486 	pbn_b0_4_1843200,
2487 
2488 	pbn_b0_1_4000000,
2489 
2490 	pbn_b0_bt_1_115200,
2491 	pbn_b0_bt_2_115200,
2492 	pbn_b0_bt_4_115200,
2493 	pbn_b0_bt_8_115200,
2494 
2495 	pbn_b0_bt_1_460800,
2496 	pbn_b0_bt_2_460800,
2497 	pbn_b0_bt_4_460800,
2498 
2499 	pbn_b0_bt_1_921600,
2500 	pbn_b0_bt_2_921600,
2501 	pbn_b0_bt_4_921600,
2502 	pbn_b0_bt_8_921600,
2503 
2504 	pbn_b1_1_115200,
2505 	pbn_b1_2_115200,
2506 	pbn_b1_4_115200,
2507 	pbn_b1_8_115200,
2508 	pbn_b1_16_115200,
2509 
2510 	pbn_b1_1_921600,
2511 	pbn_b1_2_921600,
2512 	pbn_b1_4_921600,
2513 	pbn_b1_8_921600,
2514 
2515 	pbn_b1_2_1250000,
2516 
2517 	pbn_b1_bt_1_115200,
2518 	pbn_b1_bt_2_115200,
2519 	pbn_b1_bt_4_115200,
2520 
2521 	pbn_b1_bt_2_921600,
2522 
2523 	pbn_b1_1_1382400,
2524 	pbn_b1_2_1382400,
2525 	pbn_b1_4_1382400,
2526 	pbn_b1_8_1382400,
2527 
2528 	pbn_b2_1_115200,
2529 	pbn_b2_2_115200,
2530 	pbn_b2_4_115200,
2531 	pbn_b2_8_115200,
2532 
2533 	pbn_b2_1_460800,
2534 	pbn_b2_4_460800,
2535 	pbn_b2_8_460800,
2536 	pbn_b2_16_460800,
2537 
2538 	pbn_b2_1_921600,
2539 	pbn_b2_4_921600,
2540 	pbn_b2_8_921600,
2541 
2542 	pbn_b2_8_1152000,
2543 
2544 	pbn_b2_bt_1_115200,
2545 	pbn_b2_bt_2_115200,
2546 	pbn_b2_bt_4_115200,
2547 
2548 	pbn_b2_bt_2_921600,
2549 	pbn_b2_bt_4_921600,
2550 
2551 	pbn_b3_2_115200,
2552 	pbn_b3_4_115200,
2553 	pbn_b3_8_115200,
2554 
2555 	pbn_b4_bt_2_921600,
2556 	pbn_b4_bt_4_921600,
2557 	pbn_b4_bt_8_921600,
2558 
2559 	/*
2560 	 * Board-specific versions.
2561 	 */
2562 	pbn_panacom,
2563 	pbn_panacom2,
2564 	pbn_panacom4,
2565 	pbn_plx_romulus,
2566 	pbn_endrun_2_4000000,
2567 	pbn_oxsemi,
2568 	pbn_oxsemi_1_4000000,
2569 	pbn_oxsemi_2_4000000,
2570 	pbn_oxsemi_4_4000000,
2571 	pbn_oxsemi_8_4000000,
2572 	pbn_intel_i960,
2573 	pbn_sgi_ioc3,
2574 	pbn_computone_4,
2575 	pbn_computone_6,
2576 	pbn_computone_8,
2577 	pbn_sbsxrsio,
2578 	pbn_pasemi_1682M,
2579 	pbn_ni8430_2,
2580 	pbn_ni8430_4,
2581 	pbn_ni8430_8,
2582 	pbn_ni8430_16,
2583 	pbn_ADDIDATA_PCIe_1_3906250,
2584 	pbn_ADDIDATA_PCIe_2_3906250,
2585 	pbn_ADDIDATA_PCIe_4_3906250,
2586 	pbn_ADDIDATA_PCIe_8_3906250,
2587 	pbn_ce4100_1_115200,
2588 	pbn_omegapci,
2589 	pbn_NETMOS9900_2s_115200,
2590 	pbn_brcm_trumanage,
2591 	pbn_fintek_4,
2592 	pbn_fintek_8,
2593 	pbn_fintek_12,
2594 	pbn_wch382_2,
2595 	pbn_wch384_4,
2596 	pbn_pericom_PI7C9X7951,
2597 	pbn_pericom_PI7C9X7952,
2598 	pbn_pericom_PI7C9X7954,
2599 	pbn_pericom_PI7C9X7958,
2600 };
2601 
2602 /*
2603  * uart_offset - the space between channels
2604  * reg_shift   - describes how the UART registers are mapped
2605  *               to PCI memory by the card.
2606  * For example IER register on SBS, Inc. PMC-OctPro is located at
2607  * offset 0x10 from the UART base, while UART_IER is defined as 1
2608  * in include/linux/serial_reg.h,
2609  * see first lines of serial_in() and serial_out() in 8250.c
2610 */
2611 
2612 static struct pciserial_board pci_boards[] = {
2613 	[pbn_default] = {
2614 		.flags		= FL_BASE0,
2615 		.num_ports	= 1,
2616 		.base_baud	= 115200,
2617 		.uart_offset	= 8,
2618 	},
2619 	[pbn_b0_1_115200] = {
2620 		.flags		= FL_BASE0,
2621 		.num_ports	= 1,
2622 		.base_baud	= 115200,
2623 		.uart_offset	= 8,
2624 	},
2625 	[pbn_b0_2_115200] = {
2626 		.flags		= FL_BASE0,
2627 		.num_ports	= 2,
2628 		.base_baud	= 115200,
2629 		.uart_offset	= 8,
2630 	},
2631 	[pbn_b0_4_115200] = {
2632 		.flags		= FL_BASE0,
2633 		.num_ports	= 4,
2634 		.base_baud	= 115200,
2635 		.uart_offset	= 8,
2636 	},
2637 	[pbn_b0_5_115200] = {
2638 		.flags		= FL_BASE0,
2639 		.num_ports	= 5,
2640 		.base_baud	= 115200,
2641 		.uart_offset	= 8,
2642 	},
2643 	[pbn_b0_8_115200] = {
2644 		.flags		= FL_BASE0,
2645 		.num_ports	= 8,
2646 		.base_baud	= 115200,
2647 		.uart_offset	= 8,
2648 	},
2649 	[pbn_b0_1_921600] = {
2650 		.flags		= FL_BASE0,
2651 		.num_ports	= 1,
2652 		.base_baud	= 921600,
2653 		.uart_offset	= 8,
2654 	},
2655 	[pbn_b0_2_921600] = {
2656 		.flags		= FL_BASE0,
2657 		.num_ports	= 2,
2658 		.base_baud	= 921600,
2659 		.uart_offset	= 8,
2660 	},
2661 	[pbn_b0_4_921600] = {
2662 		.flags		= FL_BASE0,
2663 		.num_ports	= 4,
2664 		.base_baud	= 921600,
2665 		.uart_offset	= 8,
2666 	},
2667 
2668 	[pbn_b0_2_1130000] = {
2669 		.flags          = FL_BASE0,
2670 		.num_ports      = 2,
2671 		.base_baud      = 1130000,
2672 		.uart_offset    = 8,
2673 	},
2674 
2675 	[pbn_b0_4_1152000] = {
2676 		.flags		= FL_BASE0,
2677 		.num_ports	= 4,
2678 		.base_baud	= 1152000,
2679 		.uart_offset	= 8,
2680 	},
2681 
2682 	[pbn_b0_4_1250000] = {
2683 		.flags		= FL_BASE0,
2684 		.num_ports	= 4,
2685 		.base_baud	= 1250000,
2686 		.uart_offset	= 8,
2687 	},
2688 
2689 	[pbn_b0_2_1843200] = {
2690 		.flags		= FL_BASE0,
2691 		.num_ports	= 2,
2692 		.base_baud	= 1843200,
2693 		.uart_offset	= 8,
2694 	},
2695 	[pbn_b0_4_1843200] = {
2696 		.flags		= FL_BASE0,
2697 		.num_ports	= 4,
2698 		.base_baud	= 1843200,
2699 		.uart_offset	= 8,
2700 	},
2701 
2702 	[pbn_b0_1_4000000] = {
2703 		.flags		= FL_BASE0,
2704 		.num_ports	= 1,
2705 		.base_baud	= 4000000,
2706 		.uart_offset	= 8,
2707 	},
2708 
2709 	[pbn_b0_bt_1_115200] = {
2710 		.flags		= FL_BASE0|FL_BASE_BARS,
2711 		.num_ports	= 1,
2712 		.base_baud	= 115200,
2713 		.uart_offset	= 8,
2714 	},
2715 	[pbn_b0_bt_2_115200] = {
2716 		.flags		= FL_BASE0|FL_BASE_BARS,
2717 		.num_ports	= 2,
2718 		.base_baud	= 115200,
2719 		.uart_offset	= 8,
2720 	},
2721 	[pbn_b0_bt_4_115200] = {
2722 		.flags		= FL_BASE0|FL_BASE_BARS,
2723 		.num_ports	= 4,
2724 		.base_baud	= 115200,
2725 		.uart_offset	= 8,
2726 	},
2727 	[pbn_b0_bt_8_115200] = {
2728 		.flags		= FL_BASE0|FL_BASE_BARS,
2729 		.num_ports	= 8,
2730 		.base_baud	= 115200,
2731 		.uart_offset	= 8,
2732 	},
2733 
2734 	[pbn_b0_bt_1_460800] = {
2735 		.flags		= FL_BASE0|FL_BASE_BARS,
2736 		.num_ports	= 1,
2737 		.base_baud	= 460800,
2738 		.uart_offset	= 8,
2739 	},
2740 	[pbn_b0_bt_2_460800] = {
2741 		.flags		= FL_BASE0|FL_BASE_BARS,
2742 		.num_ports	= 2,
2743 		.base_baud	= 460800,
2744 		.uart_offset	= 8,
2745 	},
2746 	[pbn_b0_bt_4_460800] = {
2747 		.flags		= FL_BASE0|FL_BASE_BARS,
2748 		.num_ports	= 4,
2749 		.base_baud	= 460800,
2750 		.uart_offset	= 8,
2751 	},
2752 
2753 	[pbn_b0_bt_1_921600] = {
2754 		.flags		= FL_BASE0|FL_BASE_BARS,
2755 		.num_ports	= 1,
2756 		.base_baud	= 921600,
2757 		.uart_offset	= 8,
2758 	},
2759 	[pbn_b0_bt_2_921600] = {
2760 		.flags		= FL_BASE0|FL_BASE_BARS,
2761 		.num_ports	= 2,
2762 		.base_baud	= 921600,
2763 		.uart_offset	= 8,
2764 	},
2765 	[pbn_b0_bt_4_921600] = {
2766 		.flags		= FL_BASE0|FL_BASE_BARS,
2767 		.num_ports	= 4,
2768 		.base_baud	= 921600,
2769 		.uart_offset	= 8,
2770 	},
2771 	[pbn_b0_bt_8_921600] = {
2772 		.flags		= FL_BASE0|FL_BASE_BARS,
2773 		.num_ports	= 8,
2774 		.base_baud	= 921600,
2775 		.uart_offset	= 8,
2776 	},
2777 
2778 	[pbn_b1_1_115200] = {
2779 		.flags		= FL_BASE1,
2780 		.num_ports	= 1,
2781 		.base_baud	= 115200,
2782 		.uart_offset	= 8,
2783 	},
2784 	[pbn_b1_2_115200] = {
2785 		.flags		= FL_BASE1,
2786 		.num_ports	= 2,
2787 		.base_baud	= 115200,
2788 		.uart_offset	= 8,
2789 	},
2790 	[pbn_b1_4_115200] = {
2791 		.flags		= FL_BASE1,
2792 		.num_ports	= 4,
2793 		.base_baud	= 115200,
2794 		.uart_offset	= 8,
2795 	},
2796 	[pbn_b1_8_115200] = {
2797 		.flags		= FL_BASE1,
2798 		.num_ports	= 8,
2799 		.base_baud	= 115200,
2800 		.uart_offset	= 8,
2801 	},
2802 	[pbn_b1_16_115200] = {
2803 		.flags		= FL_BASE1,
2804 		.num_ports	= 16,
2805 		.base_baud	= 115200,
2806 		.uart_offset	= 8,
2807 	},
2808 
2809 	[pbn_b1_1_921600] = {
2810 		.flags		= FL_BASE1,
2811 		.num_ports	= 1,
2812 		.base_baud	= 921600,
2813 		.uart_offset	= 8,
2814 	},
2815 	[pbn_b1_2_921600] = {
2816 		.flags		= FL_BASE1,
2817 		.num_ports	= 2,
2818 		.base_baud	= 921600,
2819 		.uart_offset	= 8,
2820 	},
2821 	[pbn_b1_4_921600] = {
2822 		.flags		= FL_BASE1,
2823 		.num_ports	= 4,
2824 		.base_baud	= 921600,
2825 		.uart_offset	= 8,
2826 	},
2827 	[pbn_b1_8_921600] = {
2828 		.flags		= FL_BASE1,
2829 		.num_ports	= 8,
2830 		.base_baud	= 921600,
2831 		.uart_offset	= 8,
2832 	},
2833 	[pbn_b1_2_1250000] = {
2834 		.flags		= FL_BASE1,
2835 		.num_ports	= 2,
2836 		.base_baud	= 1250000,
2837 		.uart_offset	= 8,
2838 	},
2839 
2840 	[pbn_b1_bt_1_115200] = {
2841 		.flags		= FL_BASE1|FL_BASE_BARS,
2842 		.num_ports	= 1,
2843 		.base_baud	= 115200,
2844 		.uart_offset	= 8,
2845 	},
2846 	[pbn_b1_bt_2_115200] = {
2847 		.flags		= FL_BASE1|FL_BASE_BARS,
2848 		.num_ports	= 2,
2849 		.base_baud	= 115200,
2850 		.uart_offset	= 8,
2851 	},
2852 	[pbn_b1_bt_4_115200] = {
2853 		.flags		= FL_BASE1|FL_BASE_BARS,
2854 		.num_ports	= 4,
2855 		.base_baud	= 115200,
2856 		.uart_offset	= 8,
2857 	},
2858 
2859 	[pbn_b1_bt_2_921600] = {
2860 		.flags		= FL_BASE1|FL_BASE_BARS,
2861 		.num_ports	= 2,
2862 		.base_baud	= 921600,
2863 		.uart_offset	= 8,
2864 	},
2865 
2866 	[pbn_b1_1_1382400] = {
2867 		.flags		= FL_BASE1,
2868 		.num_ports	= 1,
2869 		.base_baud	= 1382400,
2870 		.uart_offset	= 8,
2871 	},
2872 	[pbn_b1_2_1382400] = {
2873 		.flags		= FL_BASE1,
2874 		.num_ports	= 2,
2875 		.base_baud	= 1382400,
2876 		.uart_offset	= 8,
2877 	},
2878 	[pbn_b1_4_1382400] = {
2879 		.flags		= FL_BASE1,
2880 		.num_ports	= 4,
2881 		.base_baud	= 1382400,
2882 		.uart_offset	= 8,
2883 	},
2884 	[pbn_b1_8_1382400] = {
2885 		.flags		= FL_BASE1,
2886 		.num_ports	= 8,
2887 		.base_baud	= 1382400,
2888 		.uart_offset	= 8,
2889 	},
2890 
2891 	[pbn_b2_1_115200] = {
2892 		.flags		= FL_BASE2,
2893 		.num_ports	= 1,
2894 		.base_baud	= 115200,
2895 		.uart_offset	= 8,
2896 	},
2897 	[pbn_b2_2_115200] = {
2898 		.flags		= FL_BASE2,
2899 		.num_ports	= 2,
2900 		.base_baud	= 115200,
2901 		.uart_offset	= 8,
2902 	},
2903 	[pbn_b2_4_115200] = {
2904 		.flags          = FL_BASE2,
2905 		.num_ports      = 4,
2906 		.base_baud      = 115200,
2907 		.uart_offset    = 8,
2908 	},
2909 	[pbn_b2_8_115200] = {
2910 		.flags		= FL_BASE2,
2911 		.num_ports	= 8,
2912 		.base_baud	= 115200,
2913 		.uart_offset	= 8,
2914 	},
2915 
2916 	[pbn_b2_1_460800] = {
2917 		.flags		= FL_BASE2,
2918 		.num_ports	= 1,
2919 		.base_baud	= 460800,
2920 		.uart_offset	= 8,
2921 	},
2922 	[pbn_b2_4_460800] = {
2923 		.flags		= FL_BASE2,
2924 		.num_ports	= 4,
2925 		.base_baud	= 460800,
2926 		.uart_offset	= 8,
2927 	},
2928 	[pbn_b2_8_460800] = {
2929 		.flags		= FL_BASE2,
2930 		.num_ports	= 8,
2931 		.base_baud	= 460800,
2932 		.uart_offset	= 8,
2933 	},
2934 	[pbn_b2_16_460800] = {
2935 		.flags		= FL_BASE2,
2936 		.num_ports	= 16,
2937 		.base_baud	= 460800,
2938 		.uart_offset	= 8,
2939 	 },
2940 
2941 	[pbn_b2_1_921600] = {
2942 		.flags		= FL_BASE2,
2943 		.num_ports	= 1,
2944 		.base_baud	= 921600,
2945 		.uart_offset	= 8,
2946 	},
2947 	[pbn_b2_4_921600] = {
2948 		.flags		= FL_BASE2,
2949 		.num_ports	= 4,
2950 		.base_baud	= 921600,
2951 		.uart_offset	= 8,
2952 	},
2953 	[pbn_b2_8_921600] = {
2954 		.flags		= FL_BASE2,
2955 		.num_ports	= 8,
2956 		.base_baud	= 921600,
2957 		.uart_offset	= 8,
2958 	},
2959 
2960 	[pbn_b2_8_1152000] = {
2961 		.flags		= FL_BASE2,
2962 		.num_ports	= 8,
2963 		.base_baud	= 1152000,
2964 		.uart_offset	= 8,
2965 	},
2966 
2967 	[pbn_b2_bt_1_115200] = {
2968 		.flags		= FL_BASE2|FL_BASE_BARS,
2969 		.num_ports	= 1,
2970 		.base_baud	= 115200,
2971 		.uart_offset	= 8,
2972 	},
2973 	[pbn_b2_bt_2_115200] = {
2974 		.flags		= FL_BASE2|FL_BASE_BARS,
2975 		.num_ports	= 2,
2976 		.base_baud	= 115200,
2977 		.uart_offset	= 8,
2978 	},
2979 	[pbn_b2_bt_4_115200] = {
2980 		.flags		= FL_BASE2|FL_BASE_BARS,
2981 		.num_ports	= 4,
2982 		.base_baud	= 115200,
2983 		.uart_offset	= 8,
2984 	},
2985 
2986 	[pbn_b2_bt_2_921600] = {
2987 		.flags		= FL_BASE2|FL_BASE_BARS,
2988 		.num_ports	= 2,
2989 		.base_baud	= 921600,
2990 		.uart_offset	= 8,
2991 	},
2992 	[pbn_b2_bt_4_921600] = {
2993 		.flags		= FL_BASE2|FL_BASE_BARS,
2994 		.num_ports	= 4,
2995 		.base_baud	= 921600,
2996 		.uart_offset	= 8,
2997 	},
2998 
2999 	[pbn_b3_2_115200] = {
3000 		.flags		= FL_BASE3,
3001 		.num_ports	= 2,
3002 		.base_baud	= 115200,
3003 		.uart_offset	= 8,
3004 	},
3005 	[pbn_b3_4_115200] = {
3006 		.flags		= FL_BASE3,
3007 		.num_ports	= 4,
3008 		.base_baud	= 115200,
3009 		.uart_offset	= 8,
3010 	},
3011 	[pbn_b3_8_115200] = {
3012 		.flags		= FL_BASE3,
3013 		.num_ports	= 8,
3014 		.base_baud	= 115200,
3015 		.uart_offset	= 8,
3016 	},
3017 
3018 	[pbn_b4_bt_2_921600] = {
3019 		.flags		= FL_BASE4,
3020 		.num_ports	= 2,
3021 		.base_baud	= 921600,
3022 		.uart_offset	= 8,
3023 	},
3024 	[pbn_b4_bt_4_921600] = {
3025 		.flags		= FL_BASE4,
3026 		.num_ports	= 4,
3027 		.base_baud	= 921600,
3028 		.uart_offset	= 8,
3029 	},
3030 	[pbn_b4_bt_8_921600] = {
3031 		.flags		= FL_BASE4,
3032 		.num_ports	= 8,
3033 		.base_baud	= 921600,
3034 		.uart_offset	= 8,
3035 	},
3036 
3037 	/*
3038 	 * Entries following this are board-specific.
3039 	 */
3040 
3041 	/*
3042 	 * Panacom - IOMEM
3043 	 */
3044 	[pbn_panacom] = {
3045 		.flags		= FL_BASE2,
3046 		.num_ports	= 2,
3047 		.base_baud	= 921600,
3048 		.uart_offset	= 0x400,
3049 		.reg_shift	= 7,
3050 	},
3051 	[pbn_panacom2] = {
3052 		.flags		= FL_BASE2|FL_BASE_BARS,
3053 		.num_ports	= 2,
3054 		.base_baud	= 921600,
3055 		.uart_offset	= 0x400,
3056 		.reg_shift	= 7,
3057 	},
3058 	[pbn_panacom4] = {
3059 		.flags		= FL_BASE2|FL_BASE_BARS,
3060 		.num_ports	= 4,
3061 		.base_baud	= 921600,
3062 		.uart_offset	= 0x400,
3063 		.reg_shift	= 7,
3064 	},
3065 
3066 	/* I think this entry is broken - the first_offset looks wrong --rmk */
3067 	[pbn_plx_romulus] = {
3068 		.flags		= FL_BASE2,
3069 		.num_ports	= 4,
3070 		.base_baud	= 921600,
3071 		.uart_offset	= 8 << 2,
3072 		.reg_shift	= 2,
3073 		.first_offset	= 0x03,
3074 	},
3075 
3076 	/*
3077 	 * EndRun Technologies
3078 	* Uses the size of PCI Base region 0 to
3079 	* signal now many ports are available
3080 	* 2 port 952 Uart support
3081 	*/
3082 	[pbn_endrun_2_4000000] = {
3083 		.flags		= FL_BASE0,
3084 		.num_ports	= 2,
3085 		.base_baud	= 4000000,
3086 		.uart_offset	= 0x200,
3087 		.first_offset	= 0x1000,
3088 	},
3089 
3090 	/*
3091 	 * This board uses the size of PCI Base region 0 to
3092 	 * signal now many ports are available
3093 	 */
3094 	[pbn_oxsemi] = {
3095 		.flags		= FL_BASE0|FL_REGION_SZ_CAP,
3096 		.num_ports	= 32,
3097 		.base_baud	= 115200,
3098 		.uart_offset	= 8,
3099 	},
3100 	[pbn_oxsemi_1_4000000] = {
3101 		.flags		= FL_BASE0,
3102 		.num_ports	= 1,
3103 		.base_baud	= 4000000,
3104 		.uart_offset	= 0x200,
3105 		.first_offset	= 0x1000,
3106 	},
3107 	[pbn_oxsemi_2_4000000] = {
3108 		.flags		= FL_BASE0,
3109 		.num_ports	= 2,
3110 		.base_baud	= 4000000,
3111 		.uart_offset	= 0x200,
3112 		.first_offset	= 0x1000,
3113 	},
3114 	[pbn_oxsemi_4_4000000] = {
3115 		.flags		= FL_BASE0,
3116 		.num_ports	= 4,
3117 		.base_baud	= 4000000,
3118 		.uart_offset	= 0x200,
3119 		.first_offset	= 0x1000,
3120 	},
3121 	[pbn_oxsemi_8_4000000] = {
3122 		.flags		= FL_BASE0,
3123 		.num_ports	= 8,
3124 		.base_baud	= 4000000,
3125 		.uart_offset	= 0x200,
3126 		.first_offset	= 0x1000,
3127 	},
3128 
3129 
3130 	/*
3131 	 * EKF addition for i960 Boards form EKF with serial port.
3132 	 * Max 256 ports.
3133 	 */
3134 	[pbn_intel_i960] = {
3135 		.flags		= FL_BASE0,
3136 		.num_ports	= 32,
3137 		.base_baud	= 921600,
3138 		.uart_offset	= 8 << 2,
3139 		.reg_shift	= 2,
3140 		.first_offset	= 0x10000,
3141 	},
3142 	[pbn_sgi_ioc3] = {
3143 		.flags		= FL_BASE0|FL_NOIRQ,
3144 		.num_ports	= 1,
3145 		.base_baud	= 458333,
3146 		.uart_offset	= 8,
3147 		.reg_shift	= 0,
3148 		.first_offset	= 0x20178,
3149 	},
3150 
3151 	/*
3152 	 * Computone - uses IOMEM.
3153 	 */
3154 	[pbn_computone_4] = {
3155 		.flags		= FL_BASE0,
3156 		.num_ports	= 4,
3157 		.base_baud	= 921600,
3158 		.uart_offset	= 0x40,
3159 		.reg_shift	= 2,
3160 		.first_offset	= 0x200,
3161 	},
3162 	[pbn_computone_6] = {
3163 		.flags		= FL_BASE0,
3164 		.num_ports	= 6,
3165 		.base_baud	= 921600,
3166 		.uart_offset	= 0x40,
3167 		.reg_shift	= 2,
3168 		.first_offset	= 0x200,
3169 	},
3170 	[pbn_computone_8] = {
3171 		.flags		= FL_BASE0,
3172 		.num_ports	= 8,
3173 		.base_baud	= 921600,
3174 		.uart_offset	= 0x40,
3175 		.reg_shift	= 2,
3176 		.first_offset	= 0x200,
3177 	},
3178 	[pbn_sbsxrsio] = {
3179 		.flags		= FL_BASE0,
3180 		.num_ports	= 8,
3181 		.base_baud	= 460800,
3182 		.uart_offset	= 256,
3183 		.reg_shift	= 4,
3184 	},
3185 	/*
3186 	 * PA Semi PWRficient PA6T-1682M on-chip UART
3187 	 */
3188 	[pbn_pasemi_1682M] = {
3189 		.flags		= FL_BASE0,
3190 		.num_ports	= 1,
3191 		.base_baud	= 8333333,
3192 	},
3193 	/*
3194 	 * National Instruments 843x
3195 	 */
3196 	[pbn_ni8430_16] = {
3197 		.flags		= FL_BASE0,
3198 		.num_ports	= 16,
3199 		.base_baud	= 3686400,
3200 		.uart_offset	= 0x10,
3201 		.first_offset	= 0x800,
3202 	},
3203 	[pbn_ni8430_8] = {
3204 		.flags		= FL_BASE0,
3205 		.num_ports	= 8,
3206 		.base_baud	= 3686400,
3207 		.uart_offset	= 0x10,
3208 		.first_offset	= 0x800,
3209 	},
3210 	[pbn_ni8430_4] = {
3211 		.flags		= FL_BASE0,
3212 		.num_ports	= 4,
3213 		.base_baud	= 3686400,
3214 		.uart_offset	= 0x10,
3215 		.first_offset	= 0x800,
3216 	},
3217 	[pbn_ni8430_2] = {
3218 		.flags		= FL_BASE0,
3219 		.num_ports	= 2,
3220 		.base_baud	= 3686400,
3221 		.uart_offset	= 0x10,
3222 		.first_offset	= 0x800,
3223 	},
3224 	/*
3225 	 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3226 	 */
3227 	[pbn_ADDIDATA_PCIe_1_3906250] = {
3228 		.flags		= FL_BASE0,
3229 		.num_ports	= 1,
3230 		.base_baud	= 3906250,
3231 		.uart_offset	= 0x200,
3232 		.first_offset	= 0x1000,
3233 	},
3234 	[pbn_ADDIDATA_PCIe_2_3906250] = {
3235 		.flags		= FL_BASE0,
3236 		.num_ports	= 2,
3237 		.base_baud	= 3906250,
3238 		.uart_offset	= 0x200,
3239 		.first_offset	= 0x1000,
3240 	},
3241 	[pbn_ADDIDATA_PCIe_4_3906250] = {
3242 		.flags		= FL_BASE0,
3243 		.num_ports	= 4,
3244 		.base_baud	= 3906250,
3245 		.uart_offset	= 0x200,
3246 		.first_offset	= 0x1000,
3247 	},
3248 	[pbn_ADDIDATA_PCIe_8_3906250] = {
3249 		.flags		= FL_BASE0,
3250 		.num_ports	= 8,
3251 		.base_baud	= 3906250,
3252 		.uart_offset	= 0x200,
3253 		.first_offset	= 0x1000,
3254 	},
3255 	[pbn_ce4100_1_115200] = {
3256 		.flags		= FL_BASE_BARS,
3257 		.num_ports	= 2,
3258 		.base_baud	= 921600,
3259 		.reg_shift      = 2,
3260 	},
3261 	[pbn_omegapci] = {
3262 		.flags		= FL_BASE0,
3263 		.num_ports	= 8,
3264 		.base_baud	= 115200,
3265 		.uart_offset	= 0x200,
3266 	},
3267 	[pbn_NETMOS9900_2s_115200] = {
3268 		.flags		= FL_BASE0,
3269 		.num_ports	= 2,
3270 		.base_baud	= 115200,
3271 	},
3272 	[pbn_brcm_trumanage] = {
3273 		.flags		= FL_BASE0,
3274 		.num_ports	= 1,
3275 		.reg_shift	= 2,
3276 		.base_baud	= 115200,
3277 	},
3278 	[pbn_fintek_4] = {
3279 		.num_ports	= 4,
3280 		.uart_offset	= 8,
3281 		.base_baud	= 115200,
3282 		.first_offset	= 0x40,
3283 	},
3284 	[pbn_fintek_8] = {
3285 		.num_ports	= 8,
3286 		.uart_offset	= 8,
3287 		.base_baud	= 115200,
3288 		.first_offset	= 0x40,
3289 	},
3290 	[pbn_fintek_12] = {
3291 		.num_ports	= 12,
3292 		.uart_offset	= 8,
3293 		.base_baud	= 115200,
3294 		.first_offset	= 0x40,
3295 	},
3296 	[pbn_wch382_2] = {
3297 		.flags		= FL_BASE0,
3298 		.num_ports	= 2,
3299 		.base_baud	= 115200,
3300 		.uart_offset	= 8,
3301 		.first_offset	= 0xC0,
3302 	},
3303 	[pbn_wch384_4] = {
3304 		.flags		= FL_BASE0,
3305 		.num_ports	= 4,
3306 		.base_baud      = 115200,
3307 		.uart_offset    = 8,
3308 		.first_offset   = 0xC0,
3309 	},
3310 	/*
3311 	 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3312 	 */
3313 	[pbn_pericom_PI7C9X7951] = {
3314 		.flags          = FL_BASE0,
3315 		.num_ports      = 1,
3316 		.base_baud      = 921600,
3317 		.uart_offset	= 0x8,
3318 	},
3319 	[pbn_pericom_PI7C9X7952] = {
3320 		.flags          = FL_BASE0,
3321 		.num_ports      = 2,
3322 		.base_baud      = 921600,
3323 		.uart_offset	= 0x8,
3324 	},
3325 	[pbn_pericom_PI7C9X7954] = {
3326 		.flags          = FL_BASE0,
3327 		.num_ports      = 4,
3328 		.base_baud      = 921600,
3329 		.uart_offset	= 0x8,
3330 	},
3331 	[pbn_pericom_PI7C9X7958] = {
3332 		.flags          = FL_BASE0,
3333 		.num_ports      = 8,
3334 		.base_baud      = 921600,
3335 		.uart_offset	= 0x8,
3336 	},
3337 };
3338 
3339 static const struct pci_device_id blacklist[] = {
3340 	/* softmodems */
3341 	{ PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3342 	{ PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3343 	{ PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3344 
3345 	/* multi-io cards handled by parport_serial */
3346 	{ PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3347 	{ PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3348 	{ PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
3349 	{ PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3350 	{ PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3351 
3352 	/* Moxa Smartio MUE boards handled by 8250_moxa */
3353 	{ PCI_VDEVICE(MOXA, 0x1024), },
3354 	{ PCI_VDEVICE(MOXA, 0x1025), },
3355 	{ PCI_VDEVICE(MOXA, 0x1045), },
3356 	{ PCI_VDEVICE(MOXA, 0x1144), },
3357 	{ PCI_VDEVICE(MOXA, 0x1160), },
3358 	{ PCI_VDEVICE(MOXA, 0x1161), },
3359 	{ PCI_VDEVICE(MOXA, 0x1182), },
3360 	{ PCI_VDEVICE(MOXA, 0x1183), },
3361 	{ PCI_VDEVICE(MOXA, 0x1322), },
3362 	{ PCI_VDEVICE(MOXA, 0x1342), },
3363 	{ PCI_VDEVICE(MOXA, 0x1381), },
3364 	{ PCI_VDEVICE(MOXA, 0x1683), },
3365 
3366 	/* Intel platforms with MID UART */
3367 	{ PCI_VDEVICE(INTEL, 0x081b), },
3368 	{ PCI_VDEVICE(INTEL, 0x081c), },
3369 	{ PCI_VDEVICE(INTEL, 0x081d), },
3370 	{ PCI_VDEVICE(INTEL, 0x1191), },
3371 	{ PCI_VDEVICE(INTEL, 0x19d8), },
3372 
3373 	/* Intel platforms with DesignWare UART */
3374 	{ PCI_VDEVICE(INTEL, 0x0936), },
3375 	{ PCI_VDEVICE(INTEL, 0x0f0a), },
3376 	{ PCI_VDEVICE(INTEL, 0x0f0c), },
3377 	{ PCI_VDEVICE(INTEL, 0x228a), },
3378 	{ PCI_VDEVICE(INTEL, 0x228c), },
3379 	{ PCI_VDEVICE(INTEL, 0x9ce3), },
3380 	{ PCI_VDEVICE(INTEL, 0x9ce4), },
3381 
3382 	/* Exar devices */
3383 	{ PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3384 	{ PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3385 };
3386 
3387 static int serial_pci_is_class_communication(struct pci_dev *dev)
3388 {
3389 	/*
3390 	 * If it is not a communications device or the programming
3391 	 * interface is greater than 6, give up.
3392 	 *
3393 	 * (Should we try to make guesses for multiport serial devices
3394 	 * later?)
3395 	 */
3396 	if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3397 	     ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3398 	    (dev->class & 0xff) > 6)
3399 		return -ENODEV;
3400 
3401 	return 0;
3402 }
3403 
3404 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3405 {
3406 	const struct pci_device_id *bldev;
3407 
3408 	/*
3409 	 * Do not access blacklisted devices that are known not to
3410 	 * feature serial ports or are handled by other modules.
3411 	 */
3412 	for (bldev = blacklist;
3413 	     bldev < blacklist + ARRAY_SIZE(blacklist);
3414 	     bldev++) {
3415 		if (dev->vendor == bldev->vendor &&
3416 		    dev->device == bldev->device)
3417 			return -ENODEV;
3418 	}
3419 
3420 	return 0;
3421 }
3422 
3423 /*
3424  * Given a complete unknown PCI device, try to use some heuristics to
3425  * guess what the configuration might be, based on the pitiful PCI
3426  * serial specs.  Returns 0 on success, -ENODEV on failure.
3427  */
3428 static int
3429 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3430 {
3431 	int num_iomem, num_port, first_port = -1, i;
3432 
3433 	num_iomem = num_port = 0;
3434 	for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3435 		if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3436 			num_port++;
3437 			if (first_port == -1)
3438 				first_port = i;
3439 		}
3440 		if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3441 			num_iomem++;
3442 	}
3443 
3444 	/*
3445 	 * If there is 1 or 0 iomem regions, and exactly one port,
3446 	 * use it.  We guess the number of ports based on the IO
3447 	 * region size.
3448 	 */
3449 	if (num_iomem <= 1 && num_port == 1) {
3450 		board->flags = first_port;
3451 		board->num_ports = pci_resource_len(dev, first_port) / 8;
3452 		return 0;
3453 	}
3454 
3455 	/*
3456 	 * Now guess if we've got a board which indexes by BARs.
3457 	 * Each IO BAR should be 8 bytes, and they should follow
3458 	 * consecutively.
3459 	 */
3460 	first_port = -1;
3461 	num_port = 0;
3462 	for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3463 		if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3464 		    pci_resource_len(dev, i) == 8 &&
3465 		    (first_port == -1 || (first_port + num_port) == i)) {
3466 			num_port++;
3467 			if (first_port == -1)
3468 				first_port = i;
3469 		}
3470 	}
3471 
3472 	if (num_port > 1) {
3473 		board->flags = first_port | FL_BASE_BARS;
3474 		board->num_ports = num_port;
3475 		return 0;
3476 	}
3477 
3478 	return -ENODEV;
3479 }
3480 
3481 static inline int
3482 serial_pci_matches(const struct pciserial_board *board,
3483 		   const struct pciserial_board *guessed)
3484 {
3485 	return
3486 	    board->num_ports == guessed->num_ports &&
3487 	    board->base_baud == guessed->base_baud &&
3488 	    board->uart_offset == guessed->uart_offset &&
3489 	    board->reg_shift == guessed->reg_shift &&
3490 	    board->first_offset == guessed->first_offset;
3491 }
3492 
3493 struct serial_private *
3494 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3495 {
3496 	struct uart_8250_port uart;
3497 	struct serial_private *priv;
3498 	struct pci_serial_quirk *quirk;
3499 	int rc, nr_ports, i;
3500 
3501 	nr_ports = board->num_ports;
3502 
3503 	/*
3504 	 * Find an init and setup quirks.
3505 	 */
3506 	quirk = find_quirk(dev);
3507 
3508 	/*
3509 	 * Run the new-style initialization function.
3510 	 * The initialization function returns:
3511 	 *  <0  - error
3512 	 *   0  - use board->num_ports
3513 	 *  >0  - number of ports
3514 	 */
3515 	if (quirk->init) {
3516 		rc = quirk->init(dev);
3517 		if (rc < 0) {
3518 			priv = ERR_PTR(rc);
3519 			goto err_out;
3520 		}
3521 		if (rc)
3522 			nr_ports = rc;
3523 	}
3524 
3525 	priv = kzalloc(sizeof(struct serial_private) +
3526 		       sizeof(unsigned int) * nr_ports,
3527 		       GFP_KERNEL);
3528 	if (!priv) {
3529 		priv = ERR_PTR(-ENOMEM);
3530 		goto err_deinit;
3531 	}
3532 
3533 	priv->dev = dev;
3534 	priv->quirk = quirk;
3535 
3536 	memset(&uart, 0, sizeof(uart));
3537 	uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3538 	uart.port.uartclk = board->base_baud * 16;
3539 	uart.port.irq = get_pci_irq(dev, board);
3540 	uart.port.dev = &dev->dev;
3541 
3542 	for (i = 0; i < nr_ports; i++) {
3543 		if (quirk->setup(priv, board, &uart, i))
3544 			break;
3545 
3546 		dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3547 			uart.port.iobase, uart.port.irq, uart.port.iotype);
3548 
3549 		priv->line[i] = serial8250_register_8250_port(&uart);
3550 		if (priv->line[i] < 0) {
3551 			dev_err(&dev->dev,
3552 				"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3553 				uart.port.iobase, uart.port.irq,
3554 				uart.port.iotype, priv->line[i]);
3555 			break;
3556 		}
3557 	}
3558 	priv->nr = i;
3559 	priv->board = board;
3560 	return priv;
3561 
3562 err_deinit:
3563 	if (quirk->exit)
3564 		quirk->exit(dev);
3565 err_out:
3566 	return priv;
3567 }
3568 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3569 
3570 static void pciserial_detach_ports(struct serial_private *priv)
3571 {
3572 	struct pci_serial_quirk *quirk;
3573 	int i;
3574 
3575 	for (i = 0; i < priv->nr; i++)
3576 		serial8250_unregister_port(priv->line[i]);
3577 
3578 	/*
3579 	 * Find the exit quirks.
3580 	 */
3581 	quirk = find_quirk(priv->dev);
3582 	if (quirk->exit)
3583 		quirk->exit(priv->dev);
3584 }
3585 
3586 void pciserial_remove_ports(struct serial_private *priv)
3587 {
3588 	pciserial_detach_ports(priv);
3589 	kfree(priv);
3590 }
3591 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3592 
3593 void pciserial_suspend_ports(struct serial_private *priv)
3594 {
3595 	int i;
3596 
3597 	for (i = 0; i < priv->nr; i++)
3598 		if (priv->line[i] >= 0)
3599 			serial8250_suspend_port(priv->line[i]);
3600 
3601 	/*
3602 	 * Ensure that every init quirk is properly torn down
3603 	 */
3604 	if (priv->quirk->exit)
3605 		priv->quirk->exit(priv->dev);
3606 }
3607 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3608 
3609 void pciserial_resume_ports(struct serial_private *priv)
3610 {
3611 	int i;
3612 
3613 	/*
3614 	 * Ensure that the board is correctly configured.
3615 	 */
3616 	if (priv->quirk->init)
3617 		priv->quirk->init(priv->dev);
3618 
3619 	for (i = 0; i < priv->nr; i++)
3620 		if (priv->line[i] >= 0)
3621 			serial8250_resume_port(priv->line[i]);
3622 }
3623 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3624 
3625 /*
3626  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3627  * to the arrangement of serial ports on a PCI card.
3628  */
3629 static int
3630 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3631 {
3632 	struct pci_serial_quirk *quirk;
3633 	struct serial_private *priv;
3634 	const struct pciserial_board *board;
3635 	struct pciserial_board tmp;
3636 	int rc;
3637 
3638 	quirk = find_quirk(dev);
3639 	if (quirk->probe) {
3640 		rc = quirk->probe(dev);
3641 		if (rc)
3642 			return rc;
3643 	}
3644 
3645 	if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3646 		dev_err(&dev->dev, "invalid driver_data: %ld\n",
3647 			ent->driver_data);
3648 		return -EINVAL;
3649 	}
3650 
3651 	board = &pci_boards[ent->driver_data];
3652 
3653 	rc = serial_pci_is_class_communication(dev);
3654 	if (rc)
3655 		return rc;
3656 
3657 	rc = serial_pci_is_blacklisted(dev);
3658 	if (rc)
3659 		return rc;
3660 
3661 	rc = pcim_enable_device(dev);
3662 	pci_save_state(dev);
3663 	if (rc)
3664 		return rc;
3665 
3666 	if (ent->driver_data == pbn_default) {
3667 		/*
3668 		 * Use a copy of the pci_board entry for this;
3669 		 * avoid changing entries in the table.
3670 		 */
3671 		memcpy(&tmp, board, sizeof(struct pciserial_board));
3672 		board = &tmp;
3673 
3674 		/*
3675 		 * We matched one of our class entries.  Try to
3676 		 * determine the parameters of this board.
3677 		 */
3678 		rc = serial_pci_guess_board(dev, &tmp);
3679 		if (rc)
3680 			return rc;
3681 	} else {
3682 		/*
3683 		 * We matched an explicit entry.  If we are able to
3684 		 * detect this boards settings with our heuristic,
3685 		 * then we no longer need this entry.
3686 		 */
3687 		memcpy(&tmp, &pci_boards[pbn_default],
3688 		       sizeof(struct pciserial_board));
3689 		rc = serial_pci_guess_board(dev, &tmp);
3690 		if (rc == 0 && serial_pci_matches(board, &tmp))
3691 			moan_device("Redundant entry in serial pci_table.",
3692 				    dev);
3693 	}
3694 
3695 	priv = pciserial_init_ports(dev, board);
3696 	if (IS_ERR(priv))
3697 		return PTR_ERR(priv);
3698 
3699 	pci_set_drvdata(dev, priv);
3700 	return 0;
3701 }
3702 
3703 static void pciserial_remove_one(struct pci_dev *dev)
3704 {
3705 	struct serial_private *priv = pci_get_drvdata(dev);
3706 
3707 	pciserial_remove_ports(priv);
3708 }
3709 
3710 #ifdef CONFIG_PM_SLEEP
3711 static int pciserial_suspend_one(struct device *dev)
3712 {
3713 	struct pci_dev *pdev = to_pci_dev(dev);
3714 	struct serial_private *priv = pci_get_drvdata(pdev);
3715 
3716 	if (priv)
3717 		pciserial_suspend_ports(priv);
3718 
3719 	return 0;
3720 }
3721 
3722 static int pciserial_resume_one(struct device *dev)
3723 {
3724 	struct pci_dev *pdev = to_pci_dev(dev);
3725 	struct serial_private *priv = pci_get_drvdata(pdev);
3726 	int err;
3727 
3728 	if (priv) {
3729 		/*
3730 		 * The device may have been disabled.  Re-enable it.
3731 		 */
3732 		err = pci_enable_device(pdev);
3733 		/* FIXME: We cannot simply error out here */
3734 		if (err)
3735 			dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3736 		pciserial_resume_ports(priv);
3737 	}
3738 	return 0;
3739 }
3740 #endif
3741 
3742 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3743 			 pciserial_resume_one);
3744 
3745 static const struct pci_device_id serial_pci_tbl[] = {
3746 	/* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3747 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3748 		PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3749 		pbn_b2_8_921600 },
3750 	/* Advantech also use 0x3618 and 0xf618 */
3751 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3752 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3753 		pbn_b0_4_921600 },
3754 	{	PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3755 		PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3756 		pbn_b0_4_921600 },
3757 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3758 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3759 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3760 		pbn_b1_8_1382400 },
3761 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3762 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3763 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3764 		pbn_b1_4_1382400 },
3765 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3766 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3767 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3768 		pbn_b1_2_1382400 },
3769 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3770 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3771 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3772 		pbn_b1_8_1382400 },
3773 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3774 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3775 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3776 		pbn_b1_4_1382400 },
3777 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3778 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3779 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3780 		pbn_b1_2_1382400 },
3781 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3782 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3783 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3784 		pbn_b1_8_921600 },
3785 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3786 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3787 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3788 		pbn_b1_8_921600 },
3789 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3790 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3791 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3792 		pbn_b1_4_921600 },
3793 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3794 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3795 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3796 		pbn_b1_4_921600 },
3797 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3798 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3799 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3800 		pbn_b1_2_921600 },
3801 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3802 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3803 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3804 		pbn_b1_8_921600 },
3805 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3806 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3807 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3808 		pbn_b1_8_921600 },
3809 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3810 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3811 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3812 		pbn_b1_4_921600 },
3813 	{	PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3814 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3815 		PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3816 		pbn_b1_2_1250000 },
3817 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3818 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3819 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3820 		pbn_b0_2_1843200 },
3821 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3822 		PCI_SUBVENDOR_ID_CONNECT_TECH,
3823 		PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3824 		pbn_b0_4_1843200 },
3825 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3826 		PCI_VENDOR_ID_AFAVLAB,
3827 		PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3828 		pbn_b0_4_1152000 },
3829 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3830 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 		pbn_b2_bt_1_115200 },
3832 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3833 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 		pbn_b2_bt_2_115200 },
3835 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3836 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 		pbn_b2_bt_4_115200 },
3838 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3839 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 		pbn_b2_bt_2_115200 },
3841 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3842 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843 		pbn_b2_bt_4_115200 },
3844 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3845 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 		pbn_b2_8_115200 },
3847 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3848 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849 		pbn_b2_8_460800 },
3850 	{	PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3851 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852 		pbn_b2_8_115200 },
3853 
3854 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3855 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 		pbn_b2_bt_2_115200 },
3857 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3858 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3859 		pbn_b2_bt_2_921600 },
3860 	/*
3861 	 * VScom SPCOM800, from sl@s.pl
3862 	 */
3863 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3864 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3865 		pbn_b2_8_921600 },
3866 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3867 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3868 		pbn_b2_4_921600 },
3869 	/* Unknown card - subdevice 0x1584 */
3870 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3871 		PCI_VENDOR_ID_PLX,
3872 		PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3873 		pbn_b2_4_115200 },
3874 	/* Unknown card - subdevice 0x1588 */
3875 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3876 		PCI_VENDOR_ID_PLX,
3877 		PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3878 		pbn_b2_8_115200 },
3879 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3880 		PCI_SUBVENDOR_ID_KEYSPAN,
3881 		PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3882 		pbn_panacom },
3883 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3884 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885 		pbn_panacom4 },
3886 	{	PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3887 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888 		pbn_panacom2 },
3889 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3890 		PCI_VENDOR_ID_ESDGMBH,
3891 		PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3892 		pbn_b2_4_115200 },
3893 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3894 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3895 		PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3896 		pbn_b2_4_460800 },
3897 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3898 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3899 		PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3900 		pbn_b2_8_460800 },
3901 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3902 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3903 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3904 		pbn_b2_16_460800 },
3905 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3906 		PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3907 		PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3908 		pbn_b2_16_460800 },
3909 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3910 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3911 		PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3912 		pbn_b2_4_460800 },
3913 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3914 		PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3915 		PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3916 		pbn_b2_8_460800 },
3917 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3918 		PCI_SUBVENDOR_ID_EXSYS,
3919 		PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3920 		pbn_b2_4_115200 },
3921 	/*
3922 	 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3923 	 * (Exoray@isys.ca)
3924 	 */
3925 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3926 		0x10b5, 0x106a, 0, 0,
3927 		pbn_plx_romulus },
3928 	/*
3929 	* EndRun Technologies. PCI express device range.
3930 	*    EndRun PTP/1588 has 2 Native UARTs.
3931 	*/
3932 	{	PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
3933 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 		pbn_endrun_2_4000000 },
3935 	/*
3936 	 * Quatech cards. These actually have configurable clocks but for
3937 	 * now we just use the default.
3938 	 *
3939 	 * 100 series are RS232, 200 series RS422,
3940 	 */
3941 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3942 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 		pbn_b1_4_115200 },
3944 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3945 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 		pbn_b1_2_115200 },
3947 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3948 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 		pbn_b2_2_115200 },
3950 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3951 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 		pbn_b1_2_115200 },
3953 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3954 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 		pbn_b2_2_115200 },
3956 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3957 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 		pbn_b1_4_115200 },
3959 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3960 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961 		pbn_b1_8_115200 },
3962 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3963 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 		pbn_b1_8_115200 },
3965 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3966 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 		pbn_b1_4_115200 },
3968 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3969 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970 		pbn_b1_2_115200 },
3971 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3972 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973 		pbn_b1_4_115200 },
3974 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3975 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976 		pbn_b1_2_115200 },
3977 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3978 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3979 		pbn_b2_4_115200 },
3980 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3981 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982 		pbn_b2_2_115200 },
3983 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3984 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985 		pbn_b2_1_115200 },
3986 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3987 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988 		pbn_b2_4_115200 },
3989 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3990 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991 		pbn_b2_2_115200 },
3992 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3993 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 		pbn_b2_1_115200 },
3995 	{	PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3996 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997 		pbn_b0_8_115200 },
3998 
3999 	{	PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4000 		PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4001 		0, 0,
4002 		pbn_b0_4_921600 },
4003 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4004 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4005 		0, 0,
4006 		pbn_b0_4_1152000 },
4007 	{	PCI_VENDOR_ID_OXSEMI, 0x9505,
4008 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009 		pbn_b0_bt_2_921600 },
4010 
4011 		/*
4012 		 * The below card is a little controversial since it is the
4013 		 * subject of a PCI vendor/device ID clash.  (See
4014 		 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4015 		 * For now just used the hex ID 0x950a.
4016 		 */
4017 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4018 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4019 		0, 0, pbn_b0_2_115200 },
4020 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4021 		PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4022 		0, 0, pbn_b0_2_115200 },
4023 	{	PCI_VENDOR_ID_OXSEMI, 0x950a,
4024 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4025 		pbn_b0_2_1130000 },
4026 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4027 		PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4028 		pbn_b0_1_921600 },
4029 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4030 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 		pbn_b0_4_115200 },
4032 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4033 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4034 		pbn_b0_bt_2_921600 },
4035 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4036 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037 		pbn_b2_8_1152000 },
4038 
4039 	/*
4040 	 * Oxford Semiconductor Inc. Tornado PCI express device range.
4041 	 */
4042 	{	PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
4043 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4044 		pbn_b0_1_4000000 },
4045 	{	PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
4046 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4047 		pbn_b0_1_4000000 },
4048 	{	PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
4049 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050 		pbn_oxsemi_1_4000000 },
4051 	{	PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
4052 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4053 		pbn_oxsemi_1_4000000 },
4054 	{	PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
4055 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4056 		pbn_b0_1_4000000 },
4057 	{	PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
4058 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059 		pbn_b0_1_4000000 },
4060 	{	PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
4061 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4062 		pbn_oxsemi_1_4000000 },
4063 	{	PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
4064 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4065 		pbn_oxsemi_1_4000000 },
4066 	{	PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
4067 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4068 		pbn_b0_1_4000000 },
4069 	{	PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
4070 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4071 		pbn_b0_1_4000000 },
4072 	{	PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
4073 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4074 		pbn_b0_1_4000000 },
4075 	{	PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
4076 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 		pbn_b0_1_4000000 },
4078 	{	PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
4079 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4080 		pbn_oxsemi_2_4000000 },
4081 	{	PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
4082 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 		pbn_oxsemi_2_4000000 },
4084 	{	PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
4085 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4086 		pbn_oxsemi_4_4000000 },
4087 	{	PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
4088 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4089 		pbn_oxsemi_4_4000000 },
4090 	{	PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
4091 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4092 		pbn_oxsemi_8_4000000 },
4093 	{	PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
4094 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4095 		pbn_oxsemi_8_4000000 },
4096 	{	PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
4097 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4098 		pbn_oxsemi_1_4000000 },
4099 	{	PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
4100 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101 		pbn_oxsemi_1_4000000 },
4102 	{	PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
4103 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4104 		pbn_oxsemi_1_4000000 },
4105 	{	PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
4106 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4107 		pbn_oxsemi_1_4000000 },
4108 	{	PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
4109 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110 		pbn_oxsemi_1_4000000 },
4111 	{	PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
4112 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113 		pbn_oxsemi_1_4000000 },
4114 	{	PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
4115 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 		pbn_oxsemi_1_4000000 },
4117 	{	PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
4118 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119 		pbn_oxsemi_1_4000000 },
4120 	{	PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
4121 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 		pbn_oxsemi_1_4000000 },
4123 	{	PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
4124 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 		pbn_oxsemi_1_4000000 },
4126 	{	PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
4127 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 		pbn_oxsemi_1_4000000 },
4129 	{	PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
4130 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 		pbn_oxsemi_1_4000000 },
4132 	{	PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
4133 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 		pbn_oxsemi_1_4000000 },
4135 	{	PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
4136 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 		pbn_oxsemi_1_4000000 },
4138 	{	PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
4139 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 		pbn_oxsemi_1_4000000 },
4141 	{	PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
4142 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 		pbn_oxsemi_1_4000000 },
4144 	{	PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
4145 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 		pbn_oxsemi_1_4000000 },
4147 	{	PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
4148 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 		pbn_oxsemi_1_4000000 },
4150 	{	PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
4151 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 		pbn_oxsemi_1_4000000 },
4153 	{	PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4154 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 		pbn_oxsemi_1_4000000 },
4156 	{	PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4157 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 		pbn_oxsemi_1_4000000 },
4159 	{	PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4160 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 		pbn_oxsemi_1_4000000 },
4162 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4163 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 		pbn_oxsemi_1_4000000 },
4165 	{	PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4166 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 		pbn_oxsemi_1_4000000 },
4168 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4169 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 		pbn_oxsemi_1_4000000 },
4171 	{	PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4172 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 		pbn_oxsemi_1_4000000 },
4174 	/*
4175 	 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4176 	 */
4177 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 1 Port V.34 Super-G3 Fax */
4178 		PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4179 		pbn_oxsemi_1_4000000 },
4180 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 2 Port V.34 Super-G3 Fax */
4181 		PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4182 		pbn_oxsemi_2_4000000 },
4183 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 4 Port V.34 Super-G3 Fax */
4184 		PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4185 		pbn_oxsemi_4_4000000 },
4186 	{	PCI_VENDOR_ID_MAINPINE, 0x4000,	/* IQ Express 8 Port V.34 Super-G3 Fax */
4187 		PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4188 		pbn_oxsemi_8_4000000 },
4189 
4190 	/*
4191 	 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4192 	 */
4193 	{	PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4194 		PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4195 		pbn_oxsemi_2_4000000 },
4196 
4197 	/*
4198 	 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4199 	 * from skokodyn@yahoo.com
4200 	 */
4201 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4202 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4203 		pbn_sbsxrsio },
4204 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4205 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4206 		pbn_sbsxrsio },
4207 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4208 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4209 		pbn_sbsxrsio },
4210 	{	PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4211 		PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4212 		pbn_sbsxrsio },
4213 
4214 	/*
4215 	 * Digitan DS560-558, from jimd@esoft.com
4216 	 */
4217 	{	PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4218 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 		pbn_b1_1_115200 },
4220 
4221 	/*
4222 	 * Titan Electronic cards
4223 	 *  The 400L and 800L have a custom setup quirk.
4224 	 */
4225 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4226 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4227 		pbn_b0_1_921600 },
4228 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4229 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4230 		pbn_b0_2_921600 },
4231 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4232 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233 		pbn_b0_4_921600 },
4234 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4235 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 		pbn_b0_4_921600 },
4237 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4238 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 		pbn_b1_1_921600 },
4240 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4241 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4242 		pbn_b1_bt_2_921600 },
4243 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4244 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 		pbn_b0_bt_4_921600 },
4246 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4247 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 		pbn_b0_bt_8_921600 },
4249 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4250 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 		pbn_b4_bt_2_921600 },
4252 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4253 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 		pbn_b4_bt_4_921600 },
4255 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4256 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 		pbn_b4_bt_8_921600 },
4258 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4259 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 		pbn_b0_4_921600 },
4261 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4262 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 		pbn_b0_4_921600 },
4264 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4265 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 		pbn_b0_4_921600 },
4267 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4268 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 		pbn_oxsemi_1_4000000 },
4270 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4271 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 		pbn_oxsemi_2_4000000 },
4273 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4274 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 		pbn_oxsemi_4_4000000 },
4276 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4277 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 		pbn_oxsemi_8_4000000 },
4279 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4280 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 		pbn_oxsemi_2_4000000 },
4282 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4283 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 		pbn_oxsemi_2_4000000 },
4285 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4286 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 		pbn_b0_bt_2_921600 },
4288 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4289 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 		pbn_b0_4_921600 },
4291 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4292 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 		pbn_b0_4_921600 },
4294 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4295 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 		pbn_b0_4_921600 },
4297 	{	PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4298 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 		pbn_b0_4_921600 },
4300 
4301 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4302 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 		pbn_b2_1_460800 },
4304 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4305 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 		pbn_b2_1_460800 },
4307 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4308 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 		pbn_b2_1_460800 },
4310 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4311 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 		pbn_b2_bt_2_921600 },
4313 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4314 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 		pbn_b2_bt_2_921600 },
4316 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4317 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 		pbn_b2_bt_2_921600 },
4319 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4320 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 		pbn_b2_bt_4_921600 },
4322 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4323 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 		pbn_b2_bt_4_921600 },
4325 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4326 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 		pbn_b2_bt_4_921600 },
4328 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4329 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 		pbn_b0_1_921600 },
4331 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4332 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 		pbn_b0_1_921600 },
4334 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4335 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 		pbn_b0_1_921600 },
4337 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4338 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 		pbn_b0_bt_2_921600 },
4340 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4341 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 		pbn_b0_bt_2_921600 },
4343 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4344 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 		pbn_b0_bt_2_921600 },
4346 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4347 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 		pbn_b0_bt_4_921600 },
4349 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4350 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 		pbn_b0_bt_4_921600 },
4352 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4353 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 		pbn_b0_bt_4_921600 },
4355 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4356 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 		pbn_b0_bt_8_921600 },
4358 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4359 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 		pbn_b0_bt_8_921600 },
4361 	{	PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4362 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 		pbn_b0_bt_8_921600 },
4364 
4365 	/*
4366 	 * Computone devices submitted by Doug McNash dmcnash@computone.com
4367 	 */
4368 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4369 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4370 		0, 0, pbn_computone_4 },
4371 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4372 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4373 		0, 0, pbn_computone_8 },
4374 	{	PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4375 		PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4376 		0, 0, pbn_computone_6 },
4377 
4378 	{	PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4379 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 		pbn_oxsemi },
4381 	{	PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4382 		PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4383 		pbn_b0_bt_1_921600 },
4384 
4385 	/*
4386 	 * SUNIX (TIMEDIA)
4387 	 */
4388 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4389 		PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4390 		PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4391 		pbn_b0_bt_1_921600 },
4392 
4393 	{	PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4394 		PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4395 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4396 		pbn_b0_bt_1_921600 },
4397 
4398 	/*
4399 	 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4400 	 */
4401 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4402 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 		pbn_b0_bt_8_115200 },
4404 	{	PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4405 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 		pbn_b0_bt_8_115200 },
4407 
4408 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4409 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 		pbn_b0_bt_2_115200 },
4411 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4412 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 		pbn_b0_bt_2_115200 },
4414 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4415 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 		pbn_b0_bt_2_115200 },
4417 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4418 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 		pbn_b0_bt_2_115200 },
4420 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4421 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 		pbn_b0_bt_2_115200 },
4423 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4424 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 		pbn_b0_bt_4_460800 },
4426 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4427 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 		pbn_b0_bt_4_460800 },
4429 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4430 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 		pbn_b0_bt_2_460800 },
4432 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4433 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 		pbn_b0_bt_2_460800 },
4435 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4436 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 		pbn_b0_bt_2_460800 },
4438 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4439 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 		pbn_b0_bt_1_115200 },
4441 	{	PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4442 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 		pbn_b0_bt_1_460800 },
4444 
4445 	/*
4446 	 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4447 	 * Cards are identified by their subsystem vendor IDs, which
4448 	 * (in hex) match the model number.
4449 	 *
4450 	 * Note that JC140x are RS422/485 cards which require ox950
4451 	 * ACR = 0x10, and as such are not currently fully supported.
4452 	 */
4453 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4454 		0x1204, 0x0004, 0, 0,
4455 		pbn_b0_4_921600 },
4456 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4457 		0x1208, 0x0004, 0, 0,
4458 		pbn_b0_4_921600 },
4459 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4460 		0x1402, 0x0002, 0, 0,
4461 		pbn_b0_2_921600 }, */
4462 /*	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4463 		0x1404, 0x0004, 0, 0,
4464 		pbn_b0_4_921600 }, */
4465 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4466 		0x1208, 0x0004, 0, 0,
4467 		pbn_b0_4_921600 },
4468 
4469 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4470 		0x1204, 0x0004, 0, 0,
4471 		pbn_b0_4_921600 },
4472 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4473 		0x1208, 0x0004, 0, 0,
4474 		pbn_b0_4_921600 },
4475 	{	PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4476 		0x1208, 0x0004, 0, 0,
4477 		pbn_b0_4_921600 },
4478 	/*
4479 	 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4480 	 */
4481 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4482 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 		pbn_b1_1_1382400 },
4484 
4485 	/*
4486 	 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4487 	 */
4488 	{	PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4489 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 		pbn_b1_1_1382400 },
4491 
4492 	/*
4493 	 * RAStel 2 port modem, gerg@moreton.com.au
4494 	 */
4495 	{	PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4496 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 		pbn_b2_bt_2_115200 },
4498 
4499 	/*
4500 	 * EKF addition for i960 Boards form EKF with serial port
4501 	 */
4502 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4503 		0xE4BF, PCI_ANY_ID, 0, 0,
4504 		pbn_intel_i960 },
4505 
4506 	/*
4507 	 * Xircom Cardbus/Ethernet combos
4508 	 */
4509 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4510 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4511 		pbn_b0_1_115200 },
4512 	/*
4513 	 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4514 	 */
4515 	{	PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4516 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4517 		pbn_b0_1_115200 },
4518 
4519 	/*
4520 	 * Untested PCI modems, sent in from various folks...
4521 	 */
4522 
4523 	/*
4524 	 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4525 	 */
4526 	{	PCI_VENDOR_ID_ROCKWELL, 0x1004,
4527 		0x1048, 0x1500, 0, 0,
4528 		pbn_b1_1_115200 },
4529 
4530 	{	PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4531 		0xFF00, 0, 0, 0,
4532 		pbn_sgi_ioc3 },
4533 
4534 	/*
4535 	 * HP Diva card
4536 	 */
4537 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4538 		PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4539 		pbn_b1_1_115200 },
4540 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4541 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 		pbn_b0_5_115200 },
4543 	{	PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4544 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 		pbn_b2_1_115200 },
4546 
4547 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4548 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4549 		pbn_b3_2_115200 },
4550 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4551 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4552 		pbn_b3_4_115200 },
4553 	{	PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4554 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 		pbn_b3_8_115200 },
4556 	/*
4557 	 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4558 	 */
4559 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4560 		PCI_ANY_ID, PCI_ANY_ID,
4561 		0,
4562 		0, pbn_pericom_PI7C9X7951 },
4563 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4564 		PCI_ANY_ID, PCI_ANY_ID,
4565 		0,
4566 		0, pbn_pericom_PI7C9X7952 },
4567 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4568 		PCI_ANY_ID, PCI_ANY_ID,
4569 		0,
4570 		0, pbn_pericom_PI7C9X7954 },
4571 	{   PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4572 		PCI_ANY_ID, PCI_ANY_ID,
4573 		0,
4574 		0, pbn_pericom_PI7C9X7958 },
4575 	/*
4576 	 * ACCES I/O Products quad
4577 	 */
4578 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4579 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 		pbn_pericom_PI7C9X7954 },
4581 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4582 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 		pbn_pericom_PI7C9X7954 },
4584 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4585 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 		pbn_pericom_PI7C9X7954 },
4587 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4588 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 		pbn_pericom_PI7C9X7954 },
4590 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4591 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 		pbn_pericom_PI7C9X7954 },
4593 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4594 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 		pbn_pericom_PI7C9X7954 },
4596 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4597 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 		pbn_pericom_PI7C9X7954 },
4599 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4600 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 		pbn_pericom_PI7C9X7954 },
4602 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4603 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 		pbn_pericom_PI7C9X7954 },
4605 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4606 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 		pbn_pericom_PI7C9X7954 },
4608 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4609 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 		pbn_pericom_PI7C9X7954 },
4611 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4612 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 		pbn_pericom_PI7C9X7954 },
4614 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4615 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 		pbn_pericom_PI7C9X7954 },
4617 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4618 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 		pbn_pericom_PI7C9X7954 },
4620 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4621 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 		pbn_pericom_PI7C9X7954 },
4623 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4624 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 		pbn_pericom_PI7C9X7954 },
4626 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4627 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 		pbn_pericom_PI7C9X7954 },
4629 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4630 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 		pbn_pericom_PI7C9X7954 },
4632 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4633 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 		pbn_pericom_PI7C9X7954 },
4635 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4636 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 		pbn_pericom_PI7C9X7954 },
4638 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4639 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4640 		pbn_pericom_PI7C9X7954 },
4641 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4642 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4643 		pbn_pericom_PI7C9X7954 },
4644 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4645 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 		pbn_pericom_PI7C9X7954 },
4647 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4648 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 		pbn_pericom_PI7C9X7954 },
4650 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4651 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 		pbn_pericom_PI7C9X7958 },
4653 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4654 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4655 		pbn_pericom_PI7C9X7958 },
4656 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4657 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4658 		pbn_pericom_PI7C9X7958 },
4659 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4660 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4661 		pbn_pericom_PI7C9X7958 },
4662 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4663 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 		pbn_pericom_PI7C9X7958 },
4665 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4666 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4667 		pbn_pericom_PI7C9X7958 },
4668 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4669 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4670 		pbn_pericom_PI7C9X7958 },
4671 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4672 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4673 		pbn_pericom_PI7C9X7958 },
4674 	{	PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4675 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4676 		pbn_pericom_PI7C9X7958 },
4677 	/*
4678 	 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4679 	 */
4680 	{	PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4681 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 		pbn_b0_1_115200 },
4683 	/*
4684 	 * ITE
4685 	 */
4686 	{	PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4687 		PCI_ANY_ID, PCI_ANY_ID,
4688 		0, 0,
4689 		pbn_b1_bt_1_115200 },
4690 
4691 	/*
4692 	 * IntaShield IS-200
4693 	 */
4694 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4695 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,	/* 135a.0811 */
4696 		pbn_b2_2_115200 },
4697 	/*
4698 	 * IntaShield IS-400
4699 	 */
4700 	{	PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4701 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4702 		pbn_b2_4_115200 },
4703 	/*
4704 	 * Perle PCI-RAS cards
4705 	 */
4706 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4707 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4708 		0, 0, pbn_b2_4_921600 },
4709 	{       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4710 		PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4711 		0, 0, pbn_b2_8_921600 },
4712 
4713 	/*
4714 	 * Mainpine series cards: Fairly standard layout but fools
4715 	 * parts of the autodetect in some cases and uses otherwise
4716 	 * unmatched communications subclasses in the PCI Express case
4717 	 */
4718 
4719 	{	/* RockForceDUO */
4720 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4721 		PCI_VENDOR_ID_MAINPINE, 0x0200,
4722 		0, 0, pbn_b0_2_115200 },
4723 	{	/* RockForceQUATRO */
4724 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4725 		PCI_VENDOR_ID_MAINPINE, 0x0300,
4726 		0, 0, pbn_b0_4_115200 },
4727 	{	/* RockForceDUO+ */
4728 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4729 		PCI_VENDOR_ID_MAINPINE, 0x0400,
4730 		0, 0, pbn_b0_2_115200 },
4731 	{	/* RockForceQUATRO+ */
4732 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4733 		PCI_VENDOR_ID_MAINPINE, 0x0500,
4734 		0, 0, pbn_b0_4_115200 },
4735 	{	/* RockForce+ */
4736 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4737 		PCI_VENDOR_ID_MAINPINE, 0x0600,
4738 		0, 0, pbn_b0_2_115200 },
4739 	{	/* RockForce+ */
4740 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4741 		PCI_VENDOR_ID_MAINPINE, 0x0700,
4742 		0, 0, pbn_b0_4_115200 },
4743 	{	/* RockForceOCTO+ */
4744 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4745 		PCI_VENDOR_ID_MAINPINE, 0x0800,
4746 		0, 0, pbn_b0_8_115200 },
4747 	{	/* RockForceDUO+ */
4748 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4749 		PCI_VENDOR_ID_MAINPINE, 0x0C00,
4750 		0, 0, pbn_b0_2_115200 },
4751 	{	/* RockForceQUARTRO+ */
4752 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4753 		PCI_VENDOR_ID_MAINPINE, 0x0D00,
4754 		0, 0, pbn_b0_4_115200 },
4755 	{	/* RockForceOCTO+ */
4756 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4757 		PCI_VENDOR_ID_MAINPINE, 0x1D00,
4758 		0, 0, pbn_b0_8_115200 },
4759 	{	/* RockForceD1 */
4760 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4761 		PCI_VENDOR_ID_MAINPINE, 0x2000,
4762 		0, 0, pbn_b0_1_115200 },
4763 	{	/* RockForceF1 */
4764 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4765 		PCI_VENDOR_ID_MAINPINE, 0x2100,
4766 		0, 0, pbn_b0_1_115200 },
4767 	{	/* RockForceD2 */
4768 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4769 		PCI_VENDOR_ID_MAINPINE, 0x2200,
4770 		0, 0, pbn_b0_2_115200 },
4771 	{	/* RockForceF2 */
4772 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4773 		PCI_VENDOR_ID_MAINPINE, 0x2300,
4774 		0, 0, pbn_b0_2_115200 },
4775 	{	/* RockForceD4 */
4776 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4777 		PCI_VENDOR_ID_MAINPINE, 0x2400,
4778 		0, 0, pbn_b0_4_115200 },
4779 	{	/* RockForceF4 */
4780 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4781 		PCI_VENDOR_ID_MAINPINE, 0x2500,
4782 		0, 0, pbn_b0_4_115200 },
4783 	{	/* RockForceD8 */
4784 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4785 		PCI_VENDOR_ID_MAINPINE, 0x2600,
4786 		0, 0, pbn_b0_8_115200 },
4787 	{	/* RockForceF8 */
4788 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4789 		PCI_VENDOR_ID_MAINPINE, 0x2700,
4790 		0, 0, pbn_b0_8_115200 },
4791 	{	/* IQ Express D1 */
4792 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4793 		PCI_VENDOR_ID_MAINPINE, 0x3000,
4794 		0, 0, pbn_b0_1_115200 },
4795 	{	/* IQ Express F1 */
4796 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4797 		PCI_VENDOR_ID_MAINPINE, 0x3100,
4798 		0, 0, pbn_b0_1_115200 },
4799 	{	/* IQ Express D2 */
4800 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4801 		PCI_VENDOR_ID_MAINPINE, 0x3200,
4802 		0, 0, pbn_b0_2_115200 },
4803 	{	/* IQ Express F2 */
4804 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4805 		PCI_VENDOR_ID_MAINPINE, 0x3300,
4806 		0, 0, pbn_b0_2_115200 },
4807 	{	/* IQ Express D4 */
4808 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4809 		PCI_VENDOR_ID_MAINPINE, 0x3400,
4810 		0, 0, pbn_b0_4_115200 },
4811 	{	/* IQ Express F4 */
4812 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4813 		PCI_VENDOR_ID_MAINPINE, 0x3500,
4814 		0, 0, pbn_b0_4_115200 },
4815 	{	/* IQ Express D8 */
4816 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4817 		PCI_VENDOR_ID_MAINPINE, 0x3C00,
4818 		0, 0, pbn_b0_8_115200 },
4819 	{	/* IQ Express F8 */
4820 		PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4821 		PCI_VENDOR_ID_MAINPINE, 0x3D00,
4822 		0, 0, pbn_b0_8_115200 },
4823 
4824 
4825 	/*
4826 	 * PA Semi PA6T-1682M on-chip UART
4827 	 */
4828 	{	PCI_VENDOR_ID_PASEMI, 0xa004,
4829 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4830 		pbn_pasemi_1682M },
4831 
4832 	/*
4833 	 * National Instruments
4834 	 */
4835 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4836 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 		pbn_b1_16_115200 },
4838 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4839 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4840 		pbn_b1_8_115200 },
4841 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4842 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 		pbn_b1_bt_4_115200 },
4844 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4845 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 		pbn_b1_bt_2_115200 },
4847 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4848 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 		pbn_b1_bt_4_115200 },
4850 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4851 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4852 		pbn_b1_bt_2_115200 },
4853 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4854 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4855 		pbn_b1_16_115200 },
4856 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4857 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4858 		pbn_b1_8_115200 },
4859 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4860 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 		pbn_b1_bt_4_115200 },
4862 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4863 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4864 		pbn_b1_bt_2_115200 },
4865 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4866 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 		pbn_b1_bt_4_115200 },
4868 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4869 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 		pbn_b1_bt_2_115200 },
4871 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4872 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 		pbn_ni8430_2 },
4874 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4875 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 		pbn_ni8430_2 },
4877 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4878 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 		pbn_ni8430_4 },
4880 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4881 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 		pbn_ni8430_4 },
4883 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4884 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 		pbn_ni8430_8 },
4886 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4887 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 		pbn_ni8430_8 },
4889 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4890 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 		pbn_ni8430_16 },
4892 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4893 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 		pbn_ni8430_16 },
4895 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4896 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 		pbn_ni8430_2 },
4898 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4899 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 		pbn_ni8430_2 },
4901 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4902 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 		pbn_ni8430_4 },
4904 	{	PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4905 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 		pbn_ni8430_4 },
4907 
4908 	/*
4909 	* ADDI-DATA GmbH communication cards <info@addi-data.com>
4910 	*/
4911 	{	PCI_VENDOR_ID_ADDIDATA,
4912 		PCI_DEVICE_ID_ADDIDATA_APCI7500,
4913 		PCI_ANY_ID,
4914 		PCI_ANY_ID,
4915 		0,
4916 		0,
4917 		pbn_b0_4_115200 },
4918 
4919 	{	PCI_VENDOR_ID_ADDIDATA,
4920 		PCI_DEVICE_ID_ADDIDATA_APCI7420,
4921 		PCI_ANY_ID,
4922 		PCI_ANY_ID,
4923 		0,
4924 		0,
4925 		pbn_b0_2_115200 },
4926 
4927 	{	PCI_VENDOR_ID_ADDIDATA,
4928 		PCI_DEVICE_ID_ADDIDATA_APCI7300,
4929 		PCI_ANY_ID,
4930 		PCI_ANY_ID,
4931 		0,
4932 		0,
4933 		pbn_b0_1_115200 },
4934 
4935 	{	PCI_VENDOR_ID_AMCC,
4936 		PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
4937 		PCI_ANY_ID,
4938 		PCI_ANY_ID,
4939 		0,
4940 		0,
4941 		pbn_b1_8_115200 },
4942 
4943 	{	PCI_VENDOR_ID_ADDIDATA,
4944 		PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4945 		PCI_ANY_ID,
4946 		PCI_ANY_ID,
4947 		0,
4948 		0,
4949 		pbn_b0_4_115200 },
4950 
4951 	{	PCI_VENDOR_ID_ADDIDATA,
4952 		PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4953 		PCI_ANY_ID,
4954 		PCI_ANY_ID,
4955 		0,
4956 		0,
4957 		pbn_b0_2_115200 },
4958 
4959 	{	PCI_VENDOR_ID_ADDIDATA,
4960 		PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4961 		PCI_ANY_ID,
4962 		PCI_ANY_ID,
4963 		0,
4964 		0,
4965 		pbn_b0_1_115200 },
4966 
4967 	{	PCI_VENDOR_ID_ADDIDATA,
4968 		PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4969 		PCI_ANY_ID,
4970 		PCI_ANY_ID,
4971 		0,
4972 		0,
4973 		pbn_b0_4_115200 },
4974 
4975 	{	PCI_VENDOR_ID_ADDIDATA,
4976 		PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4977 		PCI_ANY_ID,
4978 		PCI_ANY_ID,
4979 		0,
4980 		0,
4981 		pbn_b0_2_115200 },
4982 
4983 	{	PCI_VENDOR_ID_ADDIDATA,
4984 		PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4985 		PCI_ANY_ID,
4986 		PCI_ANY_ID,
4987 		0,
4988 		0,
4989 		pbn_b0_1_115200 },
4990 
4991 	{	PCI_VENDOR_ID_ADDIDATA,
4992 		PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4993 		PCI_ANY_ID,
4994 		PCI_ANY_ID,
4995 		0,
4996 		0,
4997 		pbn_b0_8_115200 },
4998 
4999 	{	PCI_VENDOR_ID_ADDIDATA,
5000 		PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5001 		PCI_ANY_ID,
5002 		PCI_ANY_ID,
5003 		0,
5004 		0,
5005 		pbn_ADDIDATA_PCIe_4_3906250 },
5006 
5007 	{	PCI_VENDOR_ID_ADDIDATA,
5008 		PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5009 		PCI_ANY_ID,
5010 		PCI_ANY_ID,
5011 		0,
5012 		0,
5013 		pbn_ADDIDATA_PCIe_2_3906250 },
5014 
5015 	{	PCI_VENDOR_ID_ADDIDATA,
5016 		PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5017 		PCI_ANY_ID,
5018 		PCI_ANY_ID,
5019 		0,
5020 		0,
5021 		pbn_ADDIDATA_PCIe_1_3906250 },
5022 
5023 	{	PCI_VENDOR_ID_ADDIDATA,
5024 		PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5025 		PCI_ANY_ID,
5026 		PCI_ANY_ID,
5027 		0,
5028 		0,
5029 		pbn_ADDIDATA_PCIe_8_3906250 },
5030 
5031 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5032 		PCI_VENDOR_ID_IBM, 0x0299,
5033 		0, 0, pbn_b0_bt_2_115200 },
5034 
5035 	/*
5036 	 * other NetMos 9835 devices are most likely handled by the
5037 	 * parport_serial driver, check drivers/parport/parport_serial.c
5038 	 * before adding them here.
5039 	 */
5040 
5041 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5042 		0xA000, 0x1000,
5043 		0, 0, pbn_b0_1_115200 },
5044 
5045 	/* the 9901 is a rebranded 9912 */
5046 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5047 		0xA000, 0x1000,
5048 		0, 0, pbn_b0_1_115200 },
5049 
5050 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5051 		0xA000, 0x1000,
5052 		0, 0, pbn_b0_1_115200 },
5053 
5054 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5055 		0xA000, 0x1000,
5056 		0, 0, pbn_b0_1_115200 },
5057 
5058 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5059 		0xA000, 0x1000,
5060 		0, 0, pbn_b0_1_115200 },
5061 
5062 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5063 		0xA000, 0x3002,
5064 		0, 0, pbn_NETMOS9900_2s_115200 },
5065 
5066 	/*
5067 	 * Best Connectivity and Rosewill PCI Multi I/O cards
5068 	 */
5069 
5070 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5071 		0xA000, 0x1000,
5072 		0, 0, pbn_b0_1_115200 },
5073 
5074 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5075 		0xA000, 0x3002,
5076 		0, 0, pbn_b0_bt_2_115200 },
5077 
5078 	{	PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5079 		0xA000, 0x3004,
5080 		0, 0, pbn_b0_bt_4_115200 },
5081 	/* Intel CE4100 */
5082 	{	PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5083 		PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
5084 		pbn_ce4100_1_115200 },
5085 
5086 	/*
5087 	 * Cronyx Omega PCI
5088 	 */
5089 	{	PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5090 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 		pbn_omegapci },
5092 
5093 	/*
5094 	 * Broadcom TruManage
5095 	 */
5096 	{	PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5097 		PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5098 		pbn_brcm_trumanage },
5099 
5100 	/*
5101 	 * AgeStar as-prs2-009
5102 	 */
5103 	{	PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5104 		PCI_ANY_ID, PCI_ANY_ID,
5105 		0, 0, pbn_b0_bt_2_115200 },
5106 
5107 	/*
5108 	 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5109 	 * so not listed here.
5110 	 */
5111 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5112 		PCI_ANY_ID, PCI_ANY_ID,
5113 		0, 0, pbn_b0_bt_4_115200 },
5114 
5115 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5116 		PCI_ANY_ID, PCI_ANY_ID,
5117 		0, 0, pbn_b0_bt_2_115200 },
5118 
5119 	{	PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5120 		PCI_ANY_ID, PCI_ANY_ID,
5121 		0, 0, pbn_b0_bt_4_115200 },
5122 
5123 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5124 		PCI_ANY_ID, PCI_ANY_ID,
5125 		0, 0, pbn_wch382_2 },
5126 
5127 	{	PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5128 		PCI_ANY_ID, PCI_ANY_ID,
5129 		0, 0, pbn_wch384_4 },
5130 
5131 	/* Fintek PCI serial cards */
5132 	{ PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5133 	{ PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5134 	{ PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5135 
5136 	/* MKS Tenta SCOM-080x serial cards */
5137 	{ PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5138 	{ PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5139 
5140 	/*
5141 	 * These entries match devices with class COMMUNICATION_SERIAL,
5142 	 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5143 	 */
5144 	{	PCI_ANY_ID, PCI_ANY_ID,
5145 		PCI_ANY_ID, PCI_ANY_ID,
5146 		PCI_CLASS_COMMUNICATION_SERIAL << 8,
5147 		0xffff00, pbn_default },
5148 	{	PCI_ANY_ID, PCI_ANY_ID,
5149 		PCI_ANY_ID, PCI_ANY_ID,
5150 		PCI_CLASS_COMMUNICATION_MODEM << 8,
5151 		0xffff00, pbn_default },
5152 	{	PCI_ANY_ID, PCI_ANY_ID,
5153 		PCI_ANY_ID, PCI_ANY_ID,
5154 		PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5155 		0xffff00, pbn_default },
5156 	{ 0, }
5157 };
5158 
5159 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5160 						pci_channel_state_t state)
5161 {
5162 	struct serial_private *priv = pci_get_drvdata(dev);
5163 
5164 	if (state == pci_channel_io_perm_failure)
5165 		return PCI_ERS_RESULT_DISCONNECT;
5166 
5167 	if (priv)
5168 		pciserial_detach_ports(priv);
5169 
5170 	pci_disable_device(dev);
5171 
5172 	return PCI_ERS_RESULT_NEED_RESET;
5173 }
5174 
5175 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5176 {
5177 	int rc;
5178 
5179 	rc = pci_enable_device(dev);
5180 
5181 	if (rc)
5182 		return PCI_ERS_RESULT_DISCONNECT;
5183 
5184 	pci_restore_state(dev);
5185 	pci_save_state(dev);
5186 
5187 	return PCI_ERS_RESULT_RECOVERED;
5188 }
5189 
5190 static void serial8250_io_resume(struct pci_dev *dev)
5191 {
5192 	struct serial_private *priv = pci_get_drvdata(dev);
5193 	struct serial_private *new;
5194 
5195 	if (!priv)
5196 		return;
5197 
5198 	new = pciserial_init_ports(dev, priv->board);
5199 	if (!IS_ERR(new)) {
5200 		pci_set_drvdata(dev, new);
5201 		kfree(priv);
5202 	}
5203 }
5204 
5205 static const struct pci_error_handlers serial8250_err_handler = {
5206 	.error_detected = serial8250_io_error_detected,
5207 	.slot_reset = serial8250_io_slot_reset,
5208 	.resume = serial8250_io_resume,
5209 };
5210 
5211 static struct pci_driver serial_pci_driver = {
5212 	.name		= "serial",
5213 	.probe		= pciserial_init_one,
5214 	.remove		= pciserial_remove_one,
5215 	.driver         = {
5216 		.pm     = &pciserial_pm_ops,
5217 	},
5218 	.id_table	= serial_pci_tbl,
5219 	.err_handler	= &serial8250_err_handler,
5220 };
5221 
5222 module_pci_driver(serial_pci_driver);
5223 
5224 MODULE_LICENSE("GPL");
5225 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5226 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5227