1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 28 /* 29 * init function returns: 30 * > 0 - number of ports 31 * = 0 - use board->num_ports 32 * < 0 - error 33 */ 34 struct pci_serial_quirk { 35 u32 vendor; 36 u32 device; 37 u32 subvendor; 38 u32 subdevice; 39 int (*probe)(struct pci_dev *dev); 40 int (*init)(struct pci_dev *dev); 41 int (*setup)(struct serial_private *, 42 const struct pciserial_board *, 43 struct uart_8250_port *, int); 44 void (*exit)(struct pci_dev *dev); 45 }; 46 47 struct f815xxa_data { 48 spinlock_t lock; 49 int idx; 50 }; 51 52 struct serial_private { 53 struct pci_dev *dev; 54 unsigned int nr; 55 struct pci_serial_quirk *quirk; 56 const struct pciserial_board *board; 57 int line[]; 58 }; 59 60 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 61 62 static const struct pci_device_id pci_use_msi[] = { 63 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 64 0xA000, 0x1000) }, 65 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 66 0xA000, 0x1000) }, 67 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 68 0xA000, 0x1000) }, 69 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 70 PCI_ANY_ID, PCI_ANY_ID) }, 71 { } 72 }; 73 74 static int pci_default_setup(struct serial_private*, 75 const struct pciserial_board*, struct uart_8250_port *, int); 76 77 static void moan_device(const char *str, struct pci_dev *dev) 78 { 79 pci_err(dev, "%s\n" 80 "Please send the output of lspci -vv, this\n" 81 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 82 "manufacturer and name of serial board or\n" 83 "modem board to <linux-serial@vger.kernel.org>.\n", 84 str, dev->vendor, dev->device, 85 dev->subsystem_vendor, dev->subsystem_device); 86 } 87 88 static int 89 setup_port(struct serial_private *priv, struct uart_8250_port *port, 90 u8 bar, unsigned int offset, int regshift) 91 { 92 struct pci_dev *dev = priv->dev; 93 94 if (bar >= PCI_STD_NUM_BARS) 95 return -EINVAL; 96 97 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 98 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 99 return -ENOMEM; 100 101 port->port.iotype = UPIO_MEM; 102 port->port.iobase = 0; 103 port->port.mapbase = pci_resource_start(dev, bar) + offset; 104 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 105 port->port.regshift = regshift; 106 } else { 107 port->port.iotype = UPIO_PORT; 108 port->port.iobase = pci_resource_start(dev, bar) + offset; 109 port->port.mapbase = 0; 110 port->port.membase = NULL; 111 port->port.regshift = 0; 112 } 113 return 0; 114 } 115 116 /* 117 * ADDI-DATA GmbH communication cards <info@addi-data.com> 118 */ 119 static int addidata_apci7800_setup(struct serial_private *priv, 120 const struct pciserial_board *board, 121 struct uart_8250_port *port, int idx) 122 { 123 unsigned int bar = 0, offset = board->first_offset; 124 bar = FL_GET_BASE(board->flags); 125 126 if (idx < 2) { 127 offset += idx * board->uart_offset; 128 } else if ((idx >= 2) && (idx < 4)) { 129 bar += 1; 130 offset += ((idx - 2) * board->uart_offset); 131 } else if ((idx >= 4) && (idx < 6)) { 132 bar += 2; 133 offset += ((idx - 4) * board->uart_offset); 134 } else if (idx >= 6) { 135 bar += 3; 136 offset += ((idx - 6) * board->uart_offset); 137 } 138 139 return setup_port(priv, port, bar, offset, board->reg_shift); 140 } 141 142 /* 143 * AFAVLAB uses a different mixture of BARs and offsets 144 * Not that ugly ;) -- HW 145 */ 146 static int 147 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 148 struct uart_8250_port *port, int idx) 149 { 150 unsigned int bar, offset = board->first_offset; 151 152 bar = FL_GET_BASE(board->flags); 153 if (idx < 4) 154 bar += idx; 155 else { 156 bar = 4; 157 offset += (idx - 4) * board->uart_offset; 158 } 159 160 return setup_port(priv, port, bar, offset, board->reg_shift); 161 } 162 163 /* 164 * HP's Remote Management Console. The Diva chip came in several 165 * different versions. N-class, L2000 and A500 have two Diva chips, each 166 * with 3 UARTs (the third UART on the second chip is unused). Superdome 167 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 168 * one Diva chip, but it has been expanded to 5 UARTs. 169 */ 170 static int pci_hp_diva_init(struct pci_dev *dev) 171 { 172 int rc = 0; 173 174 switch (dev->subsystem_device) { 175 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 176 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 177 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 178 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 179 rc = 3; 180 break; 181 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 182 rc = 2; 183 break; 184 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 185 rc = 4; 186 break; 187 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 188 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 189 rc = 1; 190 break; 191 } 192 193 return rc; 194 } 195 196 /* 197 * HP's Diva chip puts the 4th/5th serial port further out, and 198 * some serial ports are supposed to be hidden on certain models. 199 */ 200 static int 201 pci_hp_diva_setup(struct serial_private *priv, 202 const struct pciserial_board *board, 203 struct uart_8250_port *port, int idx) 204 { 205 unsigned int offset = board->first_offset; 206 unsigned int bar = FL_GET_BASE(board->flags); 207 208 switch (priv->dev->subsystem_device) { 209 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 210 if (idx == 3) 211 idx++; 212 break; 213 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 214 if (idx > 0) 215 idx++; 216 if (idx > 2) 217 idx++; 218 break; 219 } 220 if (idx > 2) 221 offset = 0x18; 222 223 offset += idx * board->uart_offset; 224 225 return setup_port(priv, port, bar, offset, board->reg_shift); 226 } 227 228 /* 229 * Added for EKF Intel i960 serial boards 230 */ 231 static int pci_inteli960ni_init(struct pci_dev *dev) 232 { 233 u32 oldval; 234 235 if (!(dev->subsystem_device & 0x1000)) 236 return -ENODEV; 237 238 /* is firmware started? */ 239 pci_read_config_dword(dev, 0x44, &oldval); 240 if (oldval == 0x00001000L) { /* RESET value */ 241 pci_dbg(dev, "Local i960 firmware missing\n"); 242 return -ENODEV; 243 } 244 return 0; 245 } 246 247 /* 248 * Some PCI serial cards using the PLX 9050 PCI interface chip require 249 * that the card interrupt be explicitly enabled or disabled. This 250 * seems to be mainly needed on card using the PLX which also use I/O 251 * mapped memory. 252 */ 253 static int pci_plx9050_init(struct pci_dev *dev) 254 { 255 u8 irq_config; 256 void __iomem *p; 257 258 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 259 moan_device("no memory in bar 0", dev); 260 return 0; 261 } 262 263 irq_config = 0x41; 264 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 265 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 266 irq_config = 0x43; 267 268 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 269 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 270 /* 271 * As the megawolf cards have the int pins active 272 * high, and have 2 UART chips, both ints must be 273 * enabled on the 9050. Also, the UARTS are set in 274 * 16450 mode by default, so we have to enable the 275 * 16C950 'enhanced' mode so that we can use the 276 * deep FIFOs 277 */ 278 irq_config = 0x5b; 279 /* 280 * enable/disable interrupts 281 */ 282 p = ioremap(pci_resource_start(dev, 0), 0x80); 283 if (p == NULL) 284 return -ENOMEM; 285 writel(irq_config, p + 0x4c); 286 287 /* 288 * Read the register back to ensure that it took effect. 289 */ 290 readl(p + 0x4c); 291 iounmap(p); 292 293 return 0; 294 } 295 296 static void pci_plx9050_exit(struct pci_dev *dev) 297 { 298 u8 __iomem *p; 299 300 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 301 return; 302 303 /* 304 * disable interrupts 305 */ 306 p = ioremap(pci_resource_start(dev, 0), 0x80); 307 if (p != NULL) { 308 writel(0, p + 0x4c); 309 310 /* 311 * Read the register back to ensure that it took effect. 312 */ 313 readl(p + 0x4c); 314 iounmap(p); 315 } 316 } 317 318 #define NI8420_INT_ENABLE_REG 0x38 319 #define NI8420_INT_ENABLE_BIT 0x2000 320 321 static void pci_ni8420_exit(struct pci_dev *dev) 322 { 323 void __iomem *p; 324 unsigned int bar = 0; 325 326 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 327 moan_device("no memory in bar", dev); 328 return; 329 } 330 331 p = pci_ioremap_bar(dev, bar); 332 if (p == NULL) 333 return; 334 335 /* Disable the CPU Interrupt */ 336 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 337 p + NI8420_INT_ENABLE_REG); 338 iounmap(p); 339 } 340 341 342 /* MITE registers */ 343 #define MITE_IOWBSR1 0xc4 344 #define MITE_IOWCR1 0xf4 345 #define MITE_LCIMR1 0x08 346 #define MITE_LCIMR2 0x10 347 348 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 349 350 static void pci_ni8430_exit(struct pci_dev *dev) 351 { 352 void __iomem *p; 353 unsigned int bar = 0; 354 355 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 356 moan_device("no memory in bar", dev); 357 return; 358 } 359 360 p = pci_ioremap_bar(dev, bar); 361 if (p == NULL) 362 return; 363 364 /* Disable the CPU Interrupt */ 365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 366 iounmap(p); 367 } 368 369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 370 static int 371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 372 struct uart_8250_port *port, int idx) 373 { 374 unsigned int bar, offset = board->first_offset; 375 376 bar = 0; 377 378 if (idx < 4) { 379 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 380 offset += idx * board->uart_offset; 381 } else if (idx < 8) { 382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 383 offset += idx * board->uart_offset + 0xC00; 384 } else /* we have only 8 ports on PMC-OCTALPRO */ 385 return 1; 386 387 return setup_port(priv, port, bar, offset, board->reg_shift); 388 } 389 390 /* 391 * This does initialization for PMC OCTALPRO cards: 392 * maps the device memory, resets the UARTs (needed, bc 393 * if the module is removed and inserted again, the card 394 * is in the sleep mode) and enables global interrupt. 395 */ 396 397 /* global control register offset for SBS PMC-OctalPro */ 398 #define OCT_REG_CR_OFF 0x500 399 400 static int sbs_init(struct pci_dev *dev) 401 { 402 u8 __iomem *p; 403 404 p = pci_ioremap_bar(dev, 0); 405 406 if (p == NULL) 407 return -ENOMEM; 408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 409 writeb(0x10, p + OCT_REG_CR_OFF); 410 udelay(50); 411 writeb(0x0, p + OCT_REG_CR_OFF); 412 413 /* Set bit-2 (INTENABLE) of Control Register */ 414 writeb(0x4, p + OCT_REG_CR_OFF); 415 iounmap(p); 416 417 return 0; 418 } 419 420 /* 421 * Disables the global interrupt of PMC-OctalPro 422 */ 423 424 static void sbs_exit(struct pci_dev *dev) 425 { 426 u8 __iomem *p; 427 428 p = pci_ioremap_bar(dev, 0); 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 430 if (p != NULL) 431 writeb(0, p + OCT_REG_CR_OFF); 432 iounmap(p); 433 } 434 435 /* 436 * SIIG serial cards have an PCI interface chip which also controls 437 * the UART clocking frequency. Each UART can be clocked independently 438 * (except cards equipped with 4 UARTs) and initial clocking settings 439 * are stored in the EEPROM chip. It can cause problems because this 440 * version of serial driver doesn't support differently clocked UART's 441 * on single PCI card. To prevent this, initialization functions set 442 * high frequency clocking for all UART's on given card. It is safe (I 443 * hope) because it doesn't touch EEPROM settings to prevent conflicts 444 * with other OSes (like M$ DOS). 445 * 446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 447 * 448 * There is two family of SIIG serial cards with different PCI 449 * interface chip and different configuration methods: 450 * - 10x cards have control registers in IO and/or memory space; 451 * - 20x cards have control registers in standard PCI configuration space. 452 * 453 * Note: all 10x cards have PCI device ids 0x10.. 454 * all 20x cards have PCI device ids 0x20.. 455 * 456 * There are also Quartet Serial cards which use Oxford Semiconductor 457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 458 * 459 * Note: some SIIG cards are probed by the parport_serial object. 460 */ 461 462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 464 465 static int pci_siig10x_init(struct pci_dev *dev) 466 { 467 u16 data; 468 void __iomem *p; 469 470 switch (dev->device & 0xfff8) { 471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 472 data = 0xffdf; 473 break; 474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 475 data = 0xf7ff; 476 break; 477 default: /* 1S1P, 4S */ 478 data = 0xfffb; 479 break; 480 } 481 482 p = ioremap(pci_resource_start(dev, 0), 0x80); 483 if (p == NULL) 484 return -ENOMEM; 485 486 writew(readw(p + 0x28) & data, p + 0x28); 487 readw(p + 0x28); 488 iounmap(p); 489 return 0; 490 } 491 492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 494 495 static int pci_siig20x_init(struct pci_dev *dev) 496 { 497 u8 data; 498 499 /* Change clock frequency for the first UART. */ 500 pci_read_config_byte(dev, 0x6f, &data); 501 pci_write_config_byte(dev, 0x6f, data & 0xef); 502 503 /* If this card has 2 UART, we have to do the same with second UART. */ 504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 506 pci_read_config_byte(dev, 0x73, &data); 507 pci_write_config_byte(dev, 0x73, data & 0xef); 508 } 509 return 0; 510 } 511 512 static int pci_siig_init(struct pci_dev *dev) 513 { 514 unsigned int type = dev->device & 0xff00; 515 516 if (type == 0x1000) 517 return pci_siig10x_init(dev); 518 if (type == 0x2000) 519 return pci_siig20x_init(dev); 520 521 moan_device("Unknown SIIG card", dev); 522 return -ENODEV; 523 } 524 525 static int pci_siig_setup(struct serial_private *priv, 526 const struct pciserial_board *board, 527 struct uart_8250_port *port, int idx) 528 { 529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 530 531 if (idx > 3) { 532 bar = 4; 533 offset = (idx - 4) * 8; 534 } 535 536 return setup_port(priv, port, bar, offset, 0); 537 } 538 539 /* 540 * Timedia has an explosion of boards, and to avoid the PCI table from 541 * growing *huge*, we use this function to collapse some 70 entries 542 * in the PCI table into one, for sanity's and compactness's sake. 543 */ 544 static const unsigned short timedia_single_port[] = { 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 546 }; 547 548 static const unsigned short timedia_dual_port[] = { 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 553 0xD079, 0 554 }; 555 556 static const unsigned short timedia_quad_port[] = { 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 560 0xB157, 0 561 }; 562 563 static const unsigned short timedia_eight_port[] = { 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 566 }; 567 568 static const struct timedia_struct { 569 int num; 570 const unsigned short *ids; 571 } timedia_data[] = { 572 { 1, timedia_single_port }, 573 { 2, timedia_dual_port }, 574 { 4, timedia_quad_port }, 575 { 8, timedia_eight_port } 576 }; 577 578 /* 579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 580 * listing them individually, this driver merely grabs them all with 581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 582 * and should be left free to be claimed by parport_serial instead. 583 */ 584 static int pci_timedia_probe(struct pci_dev *dev) 585 { 586 /* 587 * Check the third digit of the subdevice ID 588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 589 */ 590 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 591 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 592 dev->subsystem_device); 593 return -ENODEV; 594 } 595 596 return 0; 597 } 598 599 static int pci_timedia_init(struct pci_dev *dev) 600 { 601 const unsigned short *ids; 602 int i, j; 603 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 605 ids = timedia_data[i].ids; 606 for (j = 0; ids[j]; j++) 607 if (dev->subsystem_device == ids[j]) 608 return timedia_data[i].num; 609 } 610 return 0; 611 } 612 613 /* 614 * Timedia/SUNIX uses a mixture of BARs and offsets 615 * Ugh, this is ugly as all hell --- TYT 616 */ 617 static int 618 pci_timedia_setup(struct serial_private *priv, 619 const struct pciserial_board *board, 620 struct uart_8250_port *port, int idx) 621 { 622 unsigned int bar = 0, offset = board->first_offset; 623 624 switch (idx) { 625 case 0: 626 bar = 0; 627 break; 628 case 1: 629 offset = board->uart_offset; 630 bar = 0; 631 break; 632 case 2: 633 bar = 1; 634 break; 635 case 3: 636 offset = board->uart_offset; 637 fallthrough; 638 case 4: /* BAR 2 */ 639 case 5: /* BAR 3 */ 640 case 6: /* BAR 4 */ 641 case 7: /* BAR 5 */ 642 bar = idx - 2; 643 } 644 645 return setup_port(priv, port, bar, offset, board->reg_shift); 646 } 647 648 /* 649 * Some Titan cards are also a little weird 650 */ 651 static int 652 titan_400l_800l_setup(struct serial_private *priv, 653 const struct pciserial_board *board, 654 struct uart_8250_port *port, int idx) 655 { 656 unsigned int bar, offset = board->first_offset; 657 658 switch (idx) { 659 case 0: 660 bar = 1; 661 break; 662 case 1: 663 bar = 2; 664 break; 665 default: 666 bar = 4; 667 offset = (idx - 2) * board->uart_offset; 668 } 669 670 return setup_port(priv, port, bar, offset, board->reg_shift); 671 } 672 673 static int pci_xircom_init(struct pci_dev *dev) 674 { 675 msleep(100); 676 return 0; 677 } 678 679 static int pci_ni8420_init(struct pci_dev *dev) 680 { 681 void __iomem *p; 682 unsigned int bar = 0; 683 684 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 685 moan_device("no memory in bar", dev); 686 return 0; 687 } 688 689 p = pci_ioremap_bar(dev, bar); 690 if (p == NULL) 691 return -ENOMEM; 692 693 /* Enable CPU Interrupt */ 694 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 695 p + NI8420_INT_ENABLE_REG); 696 697 iounmap(p); 698 return 0; 699 } 700 701 #define MITE_IOWBSR1_WSIZE 0xa 702 #define MITE_IOWBSR1_WIN_OFFSET 0x800 703 #define MITE_IOWBSR1_WENAB (1 << 7) 704 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 705 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 706 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 707 708 static int pci_ni8430_init(struct pci_dev *dev) 709 { 710 void __iomem *p; 711 struct pci_bus_region region; 712 u32 device_window; 713 unsigned int bar = 0; 714 715 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 716 moan_device("no memory in bar", dev); 717 return 0; 718 } 719 720 p = pci_ioremap_bar(dev, bar); 721 if (p == NULL) 722 return -ENOMEM; 723 724 /* 725 * Set device window address and size in BAR0, while acknowledging that 726 * the resource structure may contain a translated address that differs 727 * from the address the device responds to. 728 */ 729 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 730 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 732 writel(device_window, p + MITE_IOWBSR1); 733 734 /* Set window access to go to RAMSEL IO address space */ 735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 736 p + MITE_IOWCR1); 737 738 /* Enable IO Bus Interrupt 0 */ 739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 740 741 /* Enable CPU Interrupt */ 742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 743 744 iounmap(p); 745 return 0; 746 } 747 748 /* UART Port Control Register */ 749 #define NI8430_PORTCON 0x0f 750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 751 752 static int 753 pci_ni8430_setup(struct serial_private *priv, 754 const struct pciserial_board *board, 755 struct uart_8250_port *port, int idx) 756 { 757 struct pci_dev *dev = priv->dev; 758 void __iomem *p; 759 unsigned int bar, offset = board->first_offset; 760 761 if (idx >= board->num_ports) 762 return 1; 763 764 bar = FL_GET_BASE(board->flags); 765 offset += idx * board->uart_offset; 766 767 p = pci_ioremap_bar(dev, bar); 768 if (!p) 769 return -ENOMEM; 770 771 /* enable the transceiver */ 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 773 p + offset + NI8430_PORTCON); 774 775 iounmap(p); 776 777 return setup_port(priv, port, bar, offset, board->reg_shift); 778 } 779 780 static int pci_netmos_9900_setup(struct serial_private *priv, 781 const struct pciserial_board *board, 782 struct uart_8250_port *port, int idx) 783 { 784 unsigned int bar; 785 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 788 /* netmos apparently orders BARs by datasheet layout, so serial 789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 790 */ 791 bar = 3 * idx; 792 793 return setup_port(priv, port, bar, 0, board->reg_shift); 794 } 795 796 return pci_default_setup(priv, board, port, idx); 797 } 798 799 /* the 99xx series comes with a range of device IDs and a variety 800 * of capabilities: 801 * 802 * 9900 has varying capabilities and can cascade to sub-controllers 803 * (cascading should be purely internal) 804 * 9904 is hardwired with 4 serial ports 805 * 9912 and 9922 are hardwired with 2 serial ports 806 */ 807 static int pci_netmos_9900_numports(struct pci_dev *dev) 808 { 809 unsigned int c = dev->class; 810 unsigned int pi; 811 unsigned short sub_serports; 812 813 pi = c & 0xff; 814 815 if (pi == 2) 816 return 1; 817 818 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 819 /* two possibilities: 0x30ps encodes number of parallel and 820 * serial ports, or 0x1000 indicates *something*. This is not 821 * immediately obvious, since the 2s1p+4s configuration seems 822 * to offer all functionality on functions 0..2, while still 823 * advertising the same function 3 as the 4s+2s1p config. 824 */ 825 sub_serports = dev->subsystem_device & 0xf; 826 if (sub_serports > 0) 827 return sub_serports; 828 829 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 830 return 0; 831 } 832 833 moan_device("unknown NetMos/Mostech program interface", dev); 834 return 0; 835 } 836 837 static int pci_netmos_init(struct pci_dev *dev) 838 { 839 /* subdevice 0x00PS means <P> parallel, <S> serial */ 840 unsigned int num_serial = dev->subsystem_device & 0xf; 841 842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 843 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 844 return 0; 845 846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 847 dev->subsystem_device == 0x0299) 848 return 0; 849 850 switch (dev->device) { /* FALLTHROUGH on all */ 851 case PCI_DEVICE_ID_NETMOS_9904: 852 case PCI_DEVICE_ID_NETMOS_9912: 853 case PCI_DEVICE_ID_NETMOS_9922: 854 case PCI_DEVICE_ID_NETMOS_9900: 855 num_serial = pci_netmos_9900_numports(dev); 856 break; 857 858 default: 859 break; 860 } 861 862 if (num_serial == 0) { 863 moan_device("unknown NetMos/Mostech device", dev); 864 return -ENODEV; 865 } 866 867 return num_serial; 868 } 869 870 /* 871 * These chips are available with optionally one parallel port and up to 872 * two serial ports. Unfortunately they all have the same product id. 873 * 874 * Basic configuration is done over a region of 32 I/O ports. The base 875 * ioport is called INTA or INTC, depending on docs/other drivers. 876 * 877 * The region of the 32 I/O ports is configured in POSIO0R... 878 */ 879 880 /* registers */ 881 #define ITE_887x_MISCR 0x9c 882 #define ITE_887x_INTCBAR 0x78 883 #define ITE_887x_UARTBAR 0x7c 884 #define ITE_887x_PS0BAR 0x10 885 #define ITE_887x_POSIO0 0x60 886 887 /* I/O space size */ 888 #define ITE_887x_IOSIZE 32 889 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 890 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 891 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 892 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 893 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 894 #define ITE_887x_POSIO_SPEED (3 << 29) 895 /* enable IO_Space bit */ 896 #define ITE_887x_POSIO_ENABLE (1 << 31) 897 898 /* inta_addr are the configuration addresses of the ITE */ 899 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 900 static int pci_ite887x_init(struct pci_dev *dev) 901 { 902 int ret, i, type; 903 struct resource *iobase = NULL; 904 u32 miscr, uartbar, ioport; 905 906 /* search for the base-ioport */ 907 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 908 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 909 "ite887x"); 910 if (iobase != NULL) { 911 /* write POSIO0R - speed | size | ioport */ 912 pci_write_config_dword(dev, ITE_887x_POSIO0, 913 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 914 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 915 /* write INTCBAR - ioport */ 916 pci_write_config_dword(dev, ITE_887x_INTCBAR, 917 inta_addr[i]); 918 ret = inb(inta_addr[i]); 919 if (ret != 0xff) { 920 /* ioport connected */ 921 break; 922 } 923 release_region(iobase->start, ITE_887x_IOSIZE); 924 } 925 } 926 927 if (i == ARRAY_SIZE(inta_addr)) { 928 pci_err(dev, "could not find iobase\n"); 929 return -ENODEV; 930 } 931 932 /* start of undocumented type checking (see parport_pc.c) */ 933 type = inb(iobase->start + 0x18) & 0x0f; 934 935 switch (type) { 936 case 0x2: /* ITE8871 (1P) */ 937 case 0xa: /* ITE8875 (1P) */ 938 ret = 0; 939 break; 940 case 0xe: /* ITE8872 (2S1P) */ 941 ret = 2; 942 break; 943 case 0x6: /* ITE8873 (1S) */ 944 ret = 1; 945 break; 946 case 0x8: /* ITE8874 (2S) */ 947 ret = 2; 948 break; 949 default: 950 moan_device("Unknown ITE887x", dev); 951 ret = -ENODEV; 952 } 953 954 /* configure all serial ports */ 955 for (i = 0; i < ret; i++) { 956 /* read the I/O port from the device */ 957 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 958 &ioport); 959 ioport &= 0x0000FF00; /* the actual base address */ 960 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 961 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 962 ITE_887x_POSIO_IOSIZE_8 | ioport); 963 964 /* write the ioport to the UARTBAR */ 965 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 966 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 967 uartbar |= (ioport << (16 * i)); /* set the ioport */ 968 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 969 970 /* get current config */ 971 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 972 /* disable interrupts (UARTx_Routing[3:0]) */ 973 miscr &= ~(0xf << (12 - 4 * i)); 974 /* activate the UART (UARTx_En) */ 975 miscr |= 1 << (23 - i); 976 /* write new config with activated UART */ 977 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 978 } 979 980 if (ret <= 0) { 981 /* the device has no UARTs if we get here */ 982 release_region(iobase->start, ITE_887x_IOSIZE); 983 } 984 985 return ret; 986 } 987 988 static void pci_ite887x_exit(struct pci_dev *dev) 989 { 990 u32 ioport; 991 /* the ioport is bit 0-15 in POSIO0R */ 992 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 993 ioport &= 0xffff; 994 release_region(ioport, ITE_887x_IOSIZE); 995 } 996 997 /* 998 * Oxford Semiconductor Inc. 999 * Check if an OxSemi device is part of the Tornado range of devices. 1000 */ 1001 #define PCI_VENDOR_ID_ENDRUN 0x7401 1002 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1003 1004 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1005 { 1006 /* OxSemi Tornado devices are all 0xCxxx */ 1007 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1008 (dev->device & 0xf000) != 0xc000) 1009 return false; 1010 1011 /* EndRun devices are all 0xExxx */ 1012 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1013 (dev->device & 0xf000) != 0xe000) 1014 return false; 1015 1016 return true; 1017 } 1018 1019 /* 1020 * Determine the number of ports available on a Tornado device. 1021 */ 1022 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1023 { 1024 u8 __iomem *p; 1025 unsigned long deviceID; 1026 unsigned int number_uarts = 0; 1027 1028 if (!pci_oxsemi_tornado_p(dev)) 1029 return 0; 1030 1031 p = pci_iomap(dev, 0, 5); 1032 if (p == NULL) 1033 return -ENOMEM; 1034 1035 deviceID = ioread32(p); 1036 /* Tornado device */ 1037 if (deviceID == 0x07000200) { 1038 number_uarts = ioread8(p + 4); 1039 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1040 number_uarts, 1041 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1042 "EndRun" : "Oxford"); 1043 } 1044 pci_iounmap(dev, p); 1045 return number_uarts; 1046 } 1047 1048 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1049 #define OXSEMI_TORNADO_TCR_MASK 0xf 1050 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1051 #define OXSEMI_TORNADO_CPR_MIN 0x008 1052 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1053 1054 /* 1055 * Determine the oversampling rate, the clock prescaler, and the clock 1056 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1057 * which is four times the baud base, and the prescaler increments in 1058 * steps of 1/8. Therefore to make calculations on integers we need 1059 * to use a scaled clock rate, which is the baud base multiplied by 32 1060 * (or our assumed UART clock rate multiplied by 2). 1061 * 1062 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1063 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1064 * values between 1.000 and 63.875 inclusive (operation for values from 1065 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1066 * unsigned 16-bit integer. 1067 * 1068 * For the most accurate baud rate we use a table of predetermined 1069 * oversampling rates and clock prescalers that records all possible 1070 * products of the two parameters in the range from 4 up to 255 inclusive, 1071 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1072 * by 8. The table is sorted by the decreasing value of the oversampling 1073 * rate and ties are resolved by sorting by the decreasing value of the 1074 * product. This way preference is given to higher oversampling rates. 1075 * 1076 * We iterate over the table and choose the product of an oversampling 1077 * rate and a clock prescaler that gives the lowest integer division 1078 * result deviation, or if an exact integer divider is found we stop 1079 * looking for it right away. We do some fixup if the resulting clock 1080 * divisor required would be out of its unsigned 16-bit integer range. 1081 * 1082 * Finally we abuse the supposed fractional part returned to encode the 1083 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1084 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1085 */ 1086 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1087 unsigned int baud, 1088 unsigned int *frac) 1089 { 1090 static u8 p[][2] = { 1091 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1092 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1093 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1094 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1095 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1096 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1097 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1098 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1099 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1100 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1101 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1102 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1103 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1104 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1105 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1106 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1107 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1108 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1109 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1110 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1111 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1112 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1113 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1114 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1115 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1116 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1117 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1118 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1119 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1120 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1121 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1122 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1123 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1124 { 4, 9, }, { 4, 8, }, 1125 }; 1126 /* Scale the quotient for comparison to get the fractional part. */ 1127 const unsigned int quot_scale = 65536; 1128 unsigned int sclk = port->uartclk * 2; 1129 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1130 unsigned int best_squot; 1131 unsigned int squot; 1132 unsigned int quot; 1133 u16 cpr; 1134 u8 tcr; 1135 int i; 1136 1137 /* Old custom speed handling. */ 1138 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1139 unsigned int cust_div = port->custom_divisor; 1140 1141 quot = cust_div & UART_DIV_MAX; 1142 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1143 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1144 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1145 cpr = OXSEMI_TORNADO_CPR_DEF; 1146 } else { 1147 best_squot = quot_scale; 1148 for (i = 0; i < ARRAY_SIZE(p); i++) { 1149 unsigned int spre; 1150 unsigned int srem; 1151 u8 cp; 1152 u8 tc; 1153 1154 tc = p[i][0]; 1155 cp = p[i][1]; 1156 spre = tc * cp; 1157 1158 srem = sdiv % spre; 1159 if (srem > spre / 2) 1160 srem = spre - srem; 1161 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1162 1163 if (srem == 0) { 1164 tcr = tc; 1165 cpr = cp; 1166 quot = sdiv / spre; 1167 break; 1168 } else if (squot < best_squot) { 1169 best_squot = squot; 1170 tcr = tc; 1171 cpr = cp; 1172 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1173 } 1174 } 1175 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1176 quot % 2 == 0) { 1177 quot >>= 1; 1178 tcr <<= 1; 1179 } 1180 while (quot > UART_DIV_MAX) { 1181 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1182 quot >>= 1; 1183 tcr <<= 1; 1184 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1185 quot >>= 1; 1186 cpr <<= 1; 1187 } else { 1188 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1189 cpr = OXSEMI_TORNADO_CPR_MASK; 1190 } 1191 } 1192 } 1193 1194 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1195 return quot; 1196 } 1197 1198 /* 1199 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1200 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1201 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1202 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1203 * has to be written first, followed by CPR2, which occupies the location 1204 * of CKS used with earlier UART designs. 1205 */ 1206 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1207 unsigned int baud, 1208 unsigned int quot, 1209 unsigned int quot_frac) 1210 { 1211 struct uart_8250_port *up = up_to_u8250p(port); 1212 u8 cpr2 = quot_frac >> 16; 1213 u8 cpr = quot_frac >> 8; 1214 u8 tcr = quot_frac; 1215 1216 serial_icr_write(up, UART_TCR, tcr); 1217 serial_icr_write(up, UART_CPR, cpr); 1218 serial_icr_write(up, UART_CKS, cpr2); 1219 serial8250_do_set_divisor(port, baud, quot, 0); 1220 } 1221 1222 /* 1223 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1224 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1225 */ 1226 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1227 unsigned int mctrl) 1228 { 1229 struct uart_8250_port *up = up_to_u8250p(port); 1230 1231 up->mcr |= UART_MCR_CLKSEL; 1232 serial8250_do_set_mctrl(port, mctrl); 1233 } 1234 1235 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1236 const struct pciserial_board *board, 1237 struct uart_8250_port *up, int idx) 1238 { 1239 struct pci_dev *dev = priv->dev; 1240 1241 if (pci_oxsemi_tornado_p(dev)) { 1242 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1243 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1244 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1245 } 1246 1247 return pci_default_setup(priv, board, up, idx); 1248 } 1249 1250 static int pci_asix_setup(struct serial_private *priv, 1251 const struct pciserial_board *board, 1252 struct uart_8250_port *port, int idx) 1253 { 1254 port->bugs |= UART_BUG_PARITY; 1255 return pci_default_setup(priv, board, port, idx); 1256 } 1257 1258 #define QPCR_TEST_FOR1 0x3F 1259 #define QPCR_TEST_GET1 0x00 1260 #define QPCR_TEST_FOR2 0x40 1261 #define QPCR_TEST_GET2 0x40 1262 #define QPCR_TEST_FOR3 0x80 1263 #define QPCR_TEST_GET3 0x40 1264 #define QPCR_TEST_FOR4 0xC0 1265 #define QPCR_TEST_GET4 0x80 1266 1267 #define QOPR_CLOCK_X1 0x0000 1268 #define QOPR_CLOCK_X2 0x0001 1269 #define QOPR_CLOCK_X4 0x0002 1270 #define QOPR_CLOCK_X8 0x0003 1271 #define QOPR_CLOCK_RATE_MASK 0x0003 1272 1273 /* Quatech devices have their own extra interface features */ 1274 static struct pci_device_id quatech_cards[] = { 1275 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1276 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1277 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1278 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1279 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1280 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1281 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1282 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1283 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1284 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1285 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1286 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1287 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1288 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1289 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1290 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1291 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1292 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1293 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1294 { 0, } 1295 }; 1296 1297 static int pci_quatech_rqopr(struct uart_8250_port *port) 1298 { 1299 unsigned long base = port->port.iobase; 1300 u8 LCR, val; 1301 1302 LCR = inb(base + UART_LCR); 1303 outb(0xBF, base + UART_LCR); 1304 val = inb(base + UART_SCR); 1305 outb(LCR, base + UART_LCR); 1306 return val; 1307 } 1308 1309 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1310 { 1311 unsigned long base = port->port.iobase; 1312 u8 LCR; 1313 1314 LCR = inb(base + UART_LCR); 1315 outb(0xBF, base + UART_LCR); 1316 inb(base + UART_SCR); 1317 outb(qopr, base + UART_SCR); 1318 outb(LCR, base + UART_LCR); 1319 } 1320 1321 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1322 { 1323 unsigned long base = port->port.iobase; 1324 u8 LCR, val, qmcr; 1325 1326 LCR = inb(base + UART_LCR); 1327 outb(0xBF, base + UART_LCR); 1328 val = inb(base + UART_SCR); 1329 outb(val | 0x10, base + UART_SCR); 1330 qmcr = inb(base + UART_MCR); 1331 outb(val, base + UART_SCR); 1332 outb(LCR, base + UART_LCR); 1333 1334 return qmcr; 1335 } 1336 1337 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1338 { 1339 unsigned long base = port->port.iobase; 1340 u8 LCR, val; 1341 1342 LCR = inb(base + UART_LCR); 1343 outb(0xBF, base + UART_LCR); 1344 val = inb(base + UART_SCR); 1345 outb(val | 0x10, base + UART_SCR); 1346 outb(qmcr, base + UART_MCR); 1347 outb(val, base + UART_SCR); 1348 outb(LCR, base + UART_LCR); 1349 } 1350 1351 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1352 { 1353 unsigned long base = port->port.iobase; 1354 u8 LCR, val; 1355 1356 LCR = inb(base + UART_LCR); 1357 outb(0xBF, base + UART_LCR); 1358 val = inb(base + UART_SCR); 1359 if (val & 0x20) { 1360 outb(0x80, UART_LCR); 1361 if (!(inb(UART_SCR) & 0x20)) { 1362 outb(LCR, base + UART_LCR); 1363 return 1; 1364 } 1365 } 1366 return 0; 1367 } 1368 1369 static int pci_quatech_test(struct uart_8250_port *port) 1370 { 1371 u8 reg, qopr; 1372 1373 qopr = pci_quatech_rqopr(port); 1374 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1375 reg = pci_quatech_rqopr(port) & 0xC0; 1376 if (reg != QPCR_TEST_GET1) 1377 return -EINVAL; 1378 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1379 reg = pci_quatech_rqopr(port) & 0xC0; 1380 if (reg != QPCR_TEST_GET2) 1381 return -EINVAL; 1382 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1383 reg = pci_quatech_rqopr(port) & 0xC0; 1384 if (reg != QPCR_TEST_GET3) 1385 return -EINVAL; 1386 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1387 reg = pci_quatech_rqopr(port) & 0xC0; 1388 if (reg != QPCR_TEST_GET4) 1389 return -EINVAL; 1390 1391 pci_quatech_wqopr(port, qopr); 1392 return 0; 1393 } 1394 1395 static int pci_quatech_clock(struct uart_8250_port *port) 1396 { 1397 u8 qopr, reg, set; 1398 unsigned long clock; 1399 1400 if (pci_quatech_test(port) < 0) 1401 return 1843200; 1402 1403 qopr = pci_quatech_rqopr(port); 1404 1405 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1406 reg = pci_quatech_rqopr(port); 1407 if (reg & QOPR_CLOCK_X8) { 1408 clock = 1843200; 1409 goto out; 1410 } 1411 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1412 reg = pci_quatech_rqopr(port); 1413 if (!(reg & QOPR_CLOCK_X8)) { 1414 clock = 1843200; 1415 goto out; 1416 } 1417 reg &= QOPR_CLOCK_X8; 1418 if (reg == QOPR_CLOCK_X2) { 1419 clock = 3685400; 1420 set = QOPR_CLOCK_X2; 1421 } else if (reg == QOPR_CLOCK_X4) { 1422 clock = 7372800; 1423 set = QOPR_CLOCK_X4; 1424 } else if (reg == QOPR_CLOCK_X8) { 1425 clock = 14745600; 1426 set = QOPR_CLOCK_X8; 1427 } else { 1428 clock = 1843200; 1429 set = QOPR_CLOCK_X1; 1430 } 1431 qopr &= ~QOPR_CLOCK_RATE_MASK; 1432 qopr |= set; 1433 1434 out: 1435 pci_quatech_wqopr(port, qopr); 1436 return clock; 1437 } 1438 1439 static int pci_quatech_rs422(struct uart_8250_port *port) 1440 { 1441 u8 qmcr; 1442 int rs422 = 0; 1443 1444 if (!pci_quatech_has_qmcr(port)) 1445 return 0; 1446 qmcr = pci_quatech_rqmcr(port); 1447 pci_quatech_wqmcr(port, 0xFF); 1448 if (pci_quatech_rqmcr(port)) 1449 rs422 = 1; 1450 pci_quatech_wqmcr(port, qmcr); 1451 return rs422; 1452 } 1453 1454 static int pci_quatech_init(struct pci_dev *dev) 1455 { 1456 const struct pci_device_id *match; 1457 bool amcc = false; 1458 1459 match = pci_match_id(quatech_cards, dev); 1460 if (match) 1461 amcc = match->driver_data; 1462 else 1463 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1464 1465 if (amcc) { 1466 unsigned long base = pci_resource_start(dev, 0); 1467 if (base) { 1468 u32 tmp; 1469 1470 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1471 tmp = inl(base + 0x3c); 1472 outl(tmp | 0x01000000, base + 0x3c); 1473 outl(tmp & ~0x01000000, base + 0x3c); 1474 } 1475 } 1476 return 0; 1477 } 1478 1479 static int pci_quatech_setup(struct serial_private *priv, 1480 const struct pciserial_board *board, 1481 struct uart_8250_port *port, int idx) 1482 { 1483 /* Needed by pci_quatech calls below */ 1484 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1485 /* Set up the clocking */ 1486 port->port.uartclk = pci_quatech_clock(port); 1487 /* For now just warn about RS422 */ 1488 if (pci_quatech_rs422(port)) 1489 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1490 return pci_default_setup(priv, board, port, idx); 1491 } 1492 1493 static int pci_default_setup(struct serial_private *priv, 1494 const struct pciserial_board *board, 1495 struct uart_8250_port *port, int idx) 1496 { 1497 unsigned int bar, offset = board->first_offset, maxnr; 1498 1499 bar = FL_GET_BASE(board->flags); 1500 if (board->flags & FL_BASE_BARS) 1501 bar += idx; 1502 else 1503 offset += idx * board->uart_offset; 1504 1505 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1506 (board->reg_shift + 3); 1507 1508 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1509 return 1; 1510 1511 return setup_port(priv, port, bar, offset, board->reg_shift); 1512 } 1513 1514 static int 1515 ce4100_serial_setup(struct serial_private *priv, 1516 const struct pciserial_board *board, 1517 struct uart_8250_port *port, int idx) 1518 { 1519 int ret; 1520 1521 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1522 port->port.iotype = UPIO_MEM32; 1523 port->port.type = PORT_XSCALE; 1524 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1525 port->port.regshift = 2; 1526 1527 return ret; 1528 } 1529 1530 static int 1531 pci_omegapci_setup(struct serial_private *priv, 1532 const struct pciserial_board *board, 1533 struct uart_8250_port *port, int idx) 1534 { 1535 return setup_port(priv, port, 2, idx * 8, 0); 1536 } 1537 1538 static int 1539 pci_brcm_trumanage_setup(struct serial_private *priv, 1540 const struct pciserial_board *board, 1541 struct uart_8250_port *port, int idx) 1542 { 1543 int ret = pci_default_setup(priv, board, port, idx); 1544 1545 port->port.type = PORT_BRCM_TRUMANAGE; 1546 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1547 return ret; 1548 } 1549 1550 /* RTS will control by MCR if this bit is 0 */ 1551 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1552 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1553 #define FINTEK_RTS_INVERT BIT(5) 1554 1555 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1556 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1557 struct serial_rs485 *rs485) 1558 { 1559 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1560 u8 setting; 1561 u8 *index = (u8 *) port->private_data; 1562 1563 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1564 1565 if (rs485->flags & SER_RS485_ENABLED) { 1566 /* Enable RTS H/W control mode */ 1567 setting |= FINTEK_RTS_CONTROL_BY_HW; 1568 1569 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1570 /* RTS driving high on TX */ 1571 setting &= ~FINTEK_RTS_INVERT; 1572 } else { 1573 /* RTS driving low on TX */ 1574 setting |= FINTEK_RTS_INVERT; 1575 } 1576 } else { 1577 /* Disable RTS H/W control mode */ 1578 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1579 } 1580 1581 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1582 1583 return 0; 1584 } 1585 1586 static const struct serial_rs485 pci_fintek_rs485_supported = { 1587 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1588 /* F81504/508/512 does not support RTS delay before or after send */ 1589 }; 1590 1591 static int pci_fintek_setup(struct serial_private *priv, 1592 const struct pciserial_board *board, 1593 struct uart_8250_port *port, int idx) 1594 { 1595 struct pci_dev *pdev = priv->dev; 1596 u8 *data; 1597 u8 config_base; 1598 u16 iobase; 1599 1600 config_base = 0x40 + 0x08 * idx; 1601 1602 /* Get the io address from configuration space */ 1603 pci_read_config_word(pdev, config_base + 4, &iobase); 1604 1605 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1606 1607 port->port.iotype = UPIO_PORT; 1608 port->port.iobase = iobase; 1609 port->port.rs485_config = pci_fintek_rs485_config; 1610 port->port.rs485_supported = pci_fintek_rs485_supported; 1611 1612 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1613 if (!data) 1614 return -ENOMEM; 1615 1616 /* preserve index in PCI configuration space */ 1617 *data = idx; 1618 port->port.private_data = data; 1619 1620 return 0; 1621 } 1622 1623 static int pci_fintek_init(struct pci_dev *dev) 1624 { 1625 unsigned long iobase; 1626 u32 max_port, i; 1627 resource_size_t bar_data[3]; 1628 u8 config_base; 1629 struct serial_private *priv = pci_get_drvdata(dev); 1630 struct uart_8250_port *port; 1631 1632 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1633 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1634 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1635 return -ENODEV; 1636 1637 switch (dev->device) { 1638 case 0x1104: /* 4 ports */ 1639 case 0x1108: /* 8 ports */ 1640 max_port = dev->device & 0xff; 1641 break; 1642 case 0x1112: /* 12 ports */ 1643 max_port = 12; 1644 break; 1645 default: 1646 return -EINVAL; 1647 } 1648 1649 /* Get the io address dispatch from the BIOS */ 1650 bar_data[0] = pci_resource_start(dev, 5); 1651 bar_data[1] = pci_resource_start(dev, 4); 1652 bar_data[2] = pci_resource_start(dev, 3); 1653 1654 for (i = 0; i < max_port; ++i) { 1655 /* UART0 configuration offset start from 0x40 */ 1656 config_base = 0x40 + 0x08 * i; 1657 1658 /* Calculate Real IO Port */ 1659 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1660 1661 /* Enable UART I/O port */ 1662 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1663 1664 /* Select 128-byte FIFO and 8x FIFO threshold */ 1665 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1666 1667 /* LSB UART */ 1668 pci_write_config_byte(dev, config_base + 0x04, 1669 (u8)(iobase & 0xff)); 1670 1671 /* MSB UART */ 1672 pci_write_config_byte(dev, config_base + 0x05, 1673 (u8)((iobase & 0xff00) >> 8)); 1674 1675 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1676 1677 if (priv) { 1678 /* re-apply RS232/485 mode when 1679 * pciserial_resume_ports() 1680 */ 1681 port = serial8250_get_port(priv->line[i]); 1682 uart_rs485_config(&port->port); 1683 } else { 1684 /* First init without port data 1685 * force init to RS232 Mode 1686 */ 1687 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1688 } 1689 } 1690 1691 return max_port; 1692 } 1693 1694 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1695 { 1696 struct f815xxa_data *data = p->private_data; 1697 unsigned long flags; 1698 1699 spin_lock_irqsave(&data->lock, flags); 1700 writeb(value, p->membase + offset); 1701 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1702 spin_unlock_irqrestore(&data->lock, flags); 1703 } 1704 1705 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1706 const struct pciserial_board *board, 1707 struct uart_8250_port *port, int idx) 1708 { 1709 struct pci_dev *pdev = priv->dev; 1710 struct f815xxa_data *data; 1711 1712 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1713 if (!data) 1714 return -ENOMEM; 1715 1716 data->idx = idx; 1717 spin_lock_init(&data->lock); 1718 1719 port->port.private_data = data; 1720 port->port.iotype = UPIO_MEM; 1721 port->port.flags |= UPF_IOREMAP; 1722 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1723 port->port.serial_out = f815xxa_mem_serial_out; 1724 1725 return 0; 1726 } 1727 1728 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1729 { 1730 u32 max_port, i; 1731 int config_base; 1732 1733 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1734 return -ENODEV; 1735 1736 switch (dev->device) { 1737 case 0x1204: /* 4 ports */ 1738 case 0x1208: /* 8 ports */ 1739 max_port = dev->device & 0xff; 1740 break; 1741 case 0x1212: /* 12 ports */ 1742 max_port = 12; 1743 break; 1744 default: 1745 return -EINVAL; 1746 } 1747 1748 /* Set to mmio decode */ 1749 pci_write_config_byte(dev, 0x209, 0x40); 1750 1751 for (i = 0; i < max_port; ++i) { 1752 /* UART0 configuration offset start from 0x2A0 */ 1753 config_base = 0x2A0 + 0x08 * i; 1754 1755 /* Select 128-byte FIFO and 8x FIFO threshold */ 1756 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1757 1758 /* Enable UART I/O port */ 1759 pci_write_config_byte(dev, config_base + 0, 0x01); 1760 } 1761 1762 return max_port; 1763 } 1764 1765 static int skip_tx_en_setup(struct serial_private *priv, 1766 const struct pciserial_board *board, 1767 struct uart_8250_port *port, int idx) 1768 { 1769 port->port.quirks |= UPQ_NO_TXEN_TEST; 1770 pci_dbg(priv->dev, 1771 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1772 priv->dev->vendor, priv->dev->device, 1773 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1774 1775 return pci_default_setup(priv, board, port, idx); 1776 } 1777 1778 static void kt_handle_break(struct uart_port *p) 1779 { 1780 struct uart_8250_port *up = up_to_u8250p(p); 1781 /* 1782 * On receipt of a BI, serial device in Intel ME (Intel 1783 * management engine) needs to have its fifos cleared for sane 1784 * SOL (Serial Over Lan) output. 1785 */ 1786 serial8250_clear_and_reinit_fifos(up); 1787 } 1788 1789 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1790 { 1791 struct uart_8250_port *up = up_to_u8250p(p); 1792 unsigned int val; 1793 1794 /* 1795 * When the Intel ME (management engine) gets reset its serial 1796 * port registers could return 0 momentarily. Functions like 1797 * serial8250_console_write, read and save the IER, perform 1798 * some operation and then restore it. In order to avoid 1799 * setting IER register inadvertently to 0, if the value read 1800 * is 0, double check with ier value in uart_8250_port and use 1801 * that instead. up->ier should be the same value as what is 1802 * currently configured. 1803 */ 1804 val = inb(p->iobase + offset); 1805 if (offset == UART_IER) { 1806 if (val == 0) 1807 val = up->ier; 1808 } 1809 return val; 1810 } 1811 1812 static int kt_serial_setup(struct serial_private *priv, 1813 const struct pciserial_board *board, 1814 struct uart_8250_port *port, int idx) 1815 { 1816 port->port.flags |= UPF_BUG_THRE; 1817 port->port.serial_in = kt_serial_in; 1818 port->port.handle_break = kt_handle_break; 1819 return skip_tx_en_setup(priv, board, port, idx); 1820 } 1821 1822 static int pci_eg20t_init(struct pci_dev *dev) 1823 { 1824 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1825 return -ENODEV; 1826 #else 1827 return 0; 1828 #endif 1829 } 1830 1831 static int 1832 pci_wch_ch353_setup(struct serial_private *priv, 1833 const struct pciserial_board *board, 1834 struct uart_8250_port *port, int idx) 1835 { 1836 port->port.flags |= UPF_FIXED_TYPE; 1837 port->port.type = PORT_16550A; 1838 return pci_default_setup(priv, board, port, idx); 1839 } 1840 1841 static int 1842 pci_wch_ch355_setup(struct serial_private *priv, 1843 const struct pciserial_board *board, 1844 struct uart_8250_port *port, int idx) 1845 { 1846 port->port.flags |= UPF_FIXED_TYPE; 1847 port->port.type = PORT_16550A; 1848 return pci_default_setup(priv, board, port, idx); 1849 } 1850 1851 static int 1852 pci_wch_ch38x_setup(struct serial_private *priv, 1853 const struct pciserial_board *board, 1854 struct uart_8250_port *port, int idx) 1855 { 1856 port->port.flags |= UPF_FIXED_TYPE; 1857 port->port.type = PORT_16850; 1858 return pci_default_setup(priv, board, port, idx); 1859 } 1860 1861 1862 #define CH384_XINT_ENABLE_REG 0xEB 1863 #define CH384_XINT_ENABLE_BIT 0x02 1864 1865 static int pci_wch_ch38x_init(struct pci_dev *dev) 1866 { 1867 int max_port; 1868 unsigned long iobase; 1869 1870 1871 switch (dev->device) { 1872 case 0x3853: /* 8 ports */ 1873 max_port = 8; 1874 break; 1875 default: 1876 return -EINVAL; 1877 } 1878 1879 iobase = pci_resource_start(dev, 0); 1880 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1881 1882 return max_port; 1883 } 1884 1885 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1886 { 1887 unsigned long iobase; 1888 1889 iobase = pci_resource_start(dev, 0); 1890 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1891 } 1892 1893 1894 static int 1895 pci_sunix_setup(struct serial_private *priv, 1896 const struct pciserial_board *board, 1897 struct uart_8250_port *port, int idx) 1898 { 1899 int bar; 1900 int offset; 1901 1902 port->port.flags |= UPF_FIXED_TYPE; 1903 port->port.type = PORT_SUNIX; 1904 1905 if (idx < 4) { 1906 bar = 0; 1907 offset = idx * board->uart_offset; 1908 } else { 1909 bar = 1; 1910 idx -= 4; 1911 idx = div_s64_rem(idx, 4, &offset); 1912 offset = idx * 64 + offset * board->uart_offset; 1913 } 1914 1915 return setup_port(priv, port, bar, offset, 0); 1916 } 1917 1918 static int 1919 pci_moxa_setup(struct serial_private *priv, 1920 const struct pciserial_board *board, 1921 struct uart_8250_port *port, int idx) 1922 { 1923 unsigned int bar = FL_GET_BASE(board->flags); 1924 int offset; 1925 1926 if (board->num_ports == 4 && idx == 3) 1927 offset = 7 * board->uart_offset; 1928 else 1929 offset = idx * board->uart_offset; 1930 1931 return setup_port(priv, port, bar, offset, 0); 1932 } 1933 1934 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1935 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1936 #define PCI_DEVICE_ID_OCTPRO 0x0001 1937 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1938 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1939 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1940 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1941 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1942 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1943 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1944 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1945 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1946 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1947 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1948 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1949 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1950 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1951 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1952 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1953 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1954 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1955 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1956 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1957 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1958 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1959 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1960 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1961 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1962 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1963 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1964 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1965 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1966 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1967 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1968 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1969 #define PCI_VENDOR_ID_WCH 0x4348 1970 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1971 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1972 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1973 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1974 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1975 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1976 #define PCI_VENDOR_ID_AGESTAR 0x5372 1977 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1978 #define PCI_VENDOR_ID_ASIX 0x9710 1979 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1980 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1981 1982 #define PCIE_VENDOR_ID_WCH 0x1c00 1983 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1984 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1985 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1986 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1987 1988 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1989 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1990 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1991 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1992 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1993 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1994 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1995 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1996 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1997 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1998 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1999 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 2000 2001 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 2002 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 2003 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 2004 2005 /* 2006 * Master list of serial port init/setup/exit quirks. 2007 * This does not describe the general nature of the port. 2008 * (ie, baud base, number and location of ports, etc) 2009 * 2010 * This list is ordered alphabetically by vendor then device. 2011 * Specific entries must come before more generic entries. 2012 */ 2013 static struct pci_serial_quirk pci_serial_quirks[] = { 2014 /* 2015 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2016 */ 2017 { 2018 .vendor = PCI_VENDOR_ID_AMCC, 2019 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2020 .subvendor = PCI_ANY_ID, 2021 .subdevice = PCI_ANY_ID, 2022 .setup = addidata_apci7800_setup, 2023 }, 2024 /* 2025 * AFAVLAB cards - these may be called via parport_serial 2026 * It is not clear whether this applies to all products. 2027 */ 2028 { 2029 .vendor = PCI_VENDOR_ID_AFAVLAB, 2030 .device = PCI_ANY_ID, 2031 .subvendor = PCI_ANY_ID, 2032 .subdevice = PCI_ANY_ID, 2033 .setup = afavlab_setup, 2034 }, 2035 /* 2036 * HP Diva 2037 */ 2038 { 2039 .vendor = PCI_VENDOR_ID_HP, 2040 .device = PCI_DEVICE_ID_HP_DIVA, 2041 .subvendor = PCI_ANY_ID, 2042 .subdevice = PCI_ANY_ID, 2043 .init = pci_hp_diva_init, 2044 .setup = pci_hp_diva_setup, 2045 }, 2046 /* 2047 * HPE PCI serial device 2048 */ 2049 { 2050 .vendor = PCI_VENDOR_ID_HP_3PAR, 2051 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2052 .subvendor = PCI_ANY_ID, 2053 .subdevice = PCI_ANY_ID, 2054 .setup = pci_hp_diva_setup, 2055 }, 2056 /* 2057 * Intel 2058 */ 2059 { 2060 .vendor = PCI_VENDOR_ID_INTEL, 2061 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2062 .subvendor = 0xe4bf, 2063 .subdevice = PCI_ANY_ID, 2064 .init = pci_inteli960ni_init, 2065 .setup = pci_default_setup, 2066 }, 2067 { 2068 .vendor = PCI_VENDOR_ID_INTEL, 2069 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2070 .subvendor = PCI_ANY_ID, 2071 .subdevice = PCI_ANY_ID, 2072 .setup = skip_tx_en_setup, 2073 }, 2074 { 2075 .vendor = PCI_VENDOR_ID_INTEL, 2076 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2077 .subvendor = PCI_ANY_ID, 2078 .subdevice = PCI_ANY_ID, 2079 .setup = skip_tx_en_setup, 2080 }, 2081 { 2082 .vendor = PCI_VENDOR_ID_INTEL, 2083 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2084 .subvendor = PCI_ANY_ID, 2085 .subdevice = PCI_ANY_ID, 2086 .setup = skip_tx_en_setup, 2087 }, 2088 { 2089 .vendor = PCI_VENDOR_ID_INTEL, 2090 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2091 .subvendor = PCI_ANY_ID, 2092 .subdevice = PCI_ANY_ID, 2093 .setup = ce4100_serial_setup, 2094 }, 2095 { 2096 .vendor = PCI_VENDOR_ID_INTEL, 2097 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2098 .subvendor = PCI_ANY_ID, 2099 .subdevice = PCI_ANY_ID, 2100 .setup = kt_serial_setup, 2101 }, 2102 /* 2103 * ITE 2104 */ 2105 { 2106 .vendor = PCI_VENDOR_ID_ITE, 2107 .device = PCI_DEVICE_ID_ITE_8872, 2108 .subvendor = PCI_ANY_ID, 2109 .subdevice = PCI_ANY_ID, 2110 .init = pci_ite887x_init, 2111 .setup = pci_default_setup, 2112 .exit = pci_ite887x_exit, 2113 }, 2114 /* 2115 * National Instruments 2116 */ 2117 { 2118 .vendor = PCI_VENDOR_ID_NI, 2119 .device = PCI_DEVICE_ID_NI_PCI23216, 2120 .subvendor = PCI_ANY_ID, 2121 .subdevice = PCI_ANY_ID, 2122 .init = pci_ni8420_init, 2123 .setup = pci_default_setup, 2124 .exit = pci_ni8420_exit, 2125 }, 2126 { 2127 .vendor = PCI_VENDOR_ID_NI, 2128 .device = PCI_DEVICE_ID_NI_PCI2328, 2129 .subvendor = PCI_ANY_ID, 2130 .subdevice = PCI_ANY_ID, 2131 .init = pci_ni8420_init, 2132 .setup = pci_default_setup, 2133 .exit = pci_ni8420_exit, 2134 }, 2135 { 2136 .vendor = PCI_VENDOR_ID_NI, 2137 .device = PCI_DEVICE_ID_NI_PCI2324, 2138 .subvendor = PCI_ANY_ID, 2139 .subdevice = PCI_ANY_ID, 2140 .init = pci_ni8420_init, 2141 .setup = pci_default_setup, 2142 .exit = pci_ni8420_exit, 2143 }, 2144 { 2145 .vendor = PCI_VENDOR_ID_NI, 2146 .device = PCI_DEVICE_ID_NI_PCI2322, 2147 .subvendor = PCI_ANY_ID, 2148 .subdevice = PCI_ANY_ID, 2149 .init = pci_ni8420_init, 2150 .setup = pci_default_setup, 2151 .exit = pci_ni8420_exit, 2152 }, 2153 { 2154 .vendor = PCI_VENDOR_ID_NI, 2155 .device = PCI_DEVICE_ID_NI_PCI2324I, 2156 .subvendor = PCI_ANY_ID, 2157 .subdevice = PCI_ANY_ID, 2158 .init = pci_ni8420_init, 2159 .setup = pci_default_setup, 2160 .exit = pci_ni8420_exit, 2161 }, 2162 { 2163 .vendor = PCI_VENDOR_ID_NI, 2164 .device = PCI_DEVICE_ID_NI_PCI2322I, 2165 .subvendor = PCI_ANY_ID, 2166 .subdevice = PCI_ANY_ID, 2167 .init = pci_ni8420_init, 2168 .setup = pci_default_setup, 2169 .exit = pci_ni8420_exit, 2170 }, 2171 { 2172 .vendor = PCI_VENDOR_ID_NI, 2173 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2174 .subvendor = PCI_ANY_ID, 2175 .subdevice = PCI_ANY_ID, 2176 .init = pci_ni8420_init, 2177 .setup = pci_default_setup, 2178 .exit = pci_ni8420_exit, 2179 }, 2180 { 2181 .vendor = PCI_VENDOR_ID_NI, 2182 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2183 .subvendor = PCI_ANY_ID, 2184 .subdevice = PCI_ANY_ID, 2185 .init = pci_ni8420_init, 2186 .setup = pci_default_setup, 2187 .exit = pci_ni8420_exit, 2188 }, 2189 { 2190 .vendor = PCI_VENDOR_ID_NI, 2191 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2192 .subvendor = PCI_ANY_ID, 2193 .subdevice = PCI_ANY_ID, 2194 .init = pci_ni8420_init, 2195 .setup = pci_default_setup, 2196 .exit = pci_ni8420_exit, 2197 }, 2198 { 2199 .vendor = PCI_VENDOR_ID_NI, 2200 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2201 .subvendor = PCI_ANY_ID, 2202 .subdevice = PCI_ANY_ID, 2203 .init = pci_ni8420_init, 2204 .setup = pci_default_setup, 2205 .exit = pci_ni8420_exit, 2206 }, 2207 { 2208 .vendor = PCI_VENDOR_ID_NI, 2209 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2210 .subvendor = PCI_ANY_ID, 2211 .subdevice = PCI_ANY_ID, 2212 .init = pci_ni8420_init, 2213 .setup = pci_default_setup, 2214 .exit = pci_ni8420_exit, 2215 }, 2216 { 2217 .vendor = PCI_VENDOR_ID_NI, 2218 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2219 .subvendor = PCI_ANY_ID, 2220 .subdevice = PCI_ANY_ID, 2221 .init = pci_ni8420_init, 2222 .setup = pci_default_setup, 2223 .exit = pci_ni8420_exit, 2224 }, 2225 { 2226 .vendor = PCI_VENDOR_ID_NI, 2227 .device = PCI_ANY_ID, 2228 .subvendor = PCI_ANY_ID, 2229 .subdevice = PCI_ANY_ID, 2230 .init = pci_ni8430_init, 2231 .setup = pci_ni8430_setup, 2232 .exit = pci_ni8430_exit, 2233 }, 2234 /* Quatech */ 2235 { 2236 .vendor = PCI_VENDOR_ID_QUATECH, 2237 .device = PCI_ANY_ID, 2238 .subvendor = PCI_ANY_ID, 2239 .subdevice = PCI_ANY_ID, 2240 .init = pci_quatech_init, 2241 .setup = pci_quatech_setup, 2242 }, 2243 /* 2244 * Panacom 2245 */ 2246 { 2247 .vendor = PCI_VENDOR_ID_PANACOM, 2248 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2249 .subvendor = PCI_ANY_ID, 2250 .subdevice = PCI_ANY_ID, 2251 .init = pci_plx9050_init, 2252 .setup = pci_default_setup, 2253 .exit = pci_plx9050_exit, 2254 }, 2255 { 2256 .vendor = PCI_VENDOR_ID_PANACOM, 2257 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2258 .subvendor = PCI_ANY_ID, 2259 .subdevice = PCI_ANY_ID, 2260 .init = pci_plx9050_init, 2261 .setup = pci_default_setup, 2262 .exit = pci_plx9050_exit, 2263 }, 2264 /* 2265 * PLX 2266 */ 2267 { 2268 .vendor = PCI_VENDOR_ID_PLX, 2269 .device = PCI_DEVICE_ID_PLX_9050, 2270 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2271 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2272 .init = pci_plx9050_init, 2273 .setup = pci_default_setup, 2274 .exit = pci_plx9050_exit, 2275 }, 2276 { 2277 .vendor = PCI_VENDOR_ID_PLX, 2278 .device = PCI_DEVICE_ID_PLX_9050, 2279 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2280 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2281 .init = pci_plx9050_init, 2282 .setup = pci_default_setup, 2283 .exit = pci_plx9050_exit, 2284 }, 2285 { 2286 .vendor = PCI_VENDOR_ID_PLX, 2287 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2288 .subvendor = PCI_VENDOR_ID_PLX, 2289 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2290 .init = pci_plx9050_init, 2291 .setup = pci_default_setup, 2292 .exit = pci_plx9050_exit, 2293 }, 2294 /* 2295 * SBS Technologies, Inc., PMC-OCTALPRO 232 2296 */ 2297 { 2298 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2299 .device = PCI_DEVICE_ID_OCTPRO, 2300 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2301 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2302 .init = sbs_init, 2303 .setup = sbs_setup, 2304 .exit = sbs_exit, 2305 }, 2306 /* 2307 * SBS Technologies, Inc., PMC-OCTALPRO 422 2308 */ 2309 { 2310 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2311 .device = PCI_DEVICE_ID_OCTPRO, 2312 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2313 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2314 .init = sbs_init, 2315 .setup = sbs_setup, 2316 .exit = sbs_exit, 2317 }, 2318 /* 2319 * SBS Technologies, Inc., P-Octal 232 2320 */ 2321 { 2322 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2323 .device = PCI_DEVICE_ID_OCTPRO, 2324 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2325 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2326 .init = sbs_init, 2327 .setup = sbs_setup, 2328 .exit = sbs_exit, 2329 }, 2330 /* 2331 * SBS Technologies, Inc., P-Octal 422 2332 */ 2333 { 2334 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2335 .device = PCI_DEVICE_ID_OCTPRO, 2336 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2337 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2338 .init = sbs_init, 2339 .setup = sbs_setup, 2340 .exit = sbs_exit, 2341 }, 2342 /* 2343 * SIIG cards - these may be called via parport_serial 2344 */ 2345 { 2346 .vendor = PCI_VENDOR_ID_SIIG, 2347 .device = PCI_ANY_ID, 2348 .subvendor = PCI_ANY_ID, 2349 .subdevice = PCI_ANY_ID, 2350 .init = pci_siig_init, 2351 .setup = pci_siig_setup, 2352 }, 2353 /* 2354 * Titan cards 2355 */ 2356 { 2357 .vendor = PCI_VENDOR_ID_TITAN, 2358 .device = PCI_DEVICE_ID_TITAN_400L, 2359 .subvendor = PCI_ANY_ID, 2360 .subdevice = PCI_ANY_ID, 2361 .setup = titan_400l_800l_setup, 2362 }, 2363 { 2364 .vendor = PCI_VENDOR_ID_TITAN, 2365 .device = PCI_DEVICE_ID_TITAN_800L, 2366 .subvendor = PCI_ANY_ID, 2367 .subdevice = PCI_ANY_ID, 2368 .setup = titan_400l_800l_setup, 2369 }, 2370 /* 2371 * Timedia cards 2372 */ 2373 { 2374 .vendor = PCI_VENDOR_ID_TIMEDIA, 2375 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2376 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2377 .subdevice = PCI_ANY_ID, 2378 .probe = pci_timedia_probe, 2379 .init = pci_timedia_init, 2380 .setup = pci_timedia_setup, 2381 }, 2382 { 2383 .vendor = PCI_VENDOR_ID_TIMEDIA, 2384 .device = PCI_ANY_ID, 2385 .subvendor = PCI_ANY_ID, 2386 .subdevice = PCI_ANY_ID, 2387 .setup = pci_timedia_setup, 2388 }, 2389 /* 2390 * Sunix PCI serial boards 2391 */ 2392 { 2393 .vendor = PCI_VENDOR_ID_SUNIX, 2394 .device = PCI_DEVICE_ID_SUNIX_1999, 2395 .subvendor = PCI_VENDOR_ID_SUNIX, 2396 .subdevice = PCI_ANY_ID, 2397 .setup = pci_sunix_setup, 2398 }, 2399 /* 2400 * Xircom cards 2401 */ 2402 { 2403 .vendor = PCI_VENDOR_ID_XIRCOM, 2404 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2405 .subvendor = PCI_ANY_ID, 2406 .subdevice = PCI_ANY_ID, 2407 .init = pci_xircom_init, 2408 .setup = pci_default_setup, 2409 }, 2410 /* 2411 * Netmos cards - these may be called via parport_serial 2412 */ 2413 { 2414 .vendor = PCI_VENDOR_ID_NETMOS, 2415 .device = PCI_ANY_ID, 2416 .subvendor = PCI_ANY_ID, 2417 .subdevice = PCI_ANY_ID, 2418 .init = pci_netmos_init, 2419 .setup = pci_netmos_9900_setup, 2420 }, 2421 /* 2422 * EndRun Technologies 2423 */ 2424 { 2425 .vendor = PCI_VENDOR_ID_ENDRUN, 2426 .device = PCI_ANY_ID, 2427 .subvendor = PCI_ANY_ID, 2428 .subdevice = PCI_ANY_ID, 2429 .init = pci_oxsemi_tornado_init, 2430 .setup = pci_default_setup, 2431 }, 2432 /* 2433 * For Oxford Semiconductor Tornado based devices 2434 */ 2435 { 2436 .vendor = PCI_VENDOR_ID_OXSEMI, 2437 .device = PCI_ANY_ID, 2438 .subvendor = PCI_ANY_ID, 2439 .subdevice = PCI_ANY_ID, 2440 .init = pci_oxsemi_tornado_init, 2441 .setup = pci_oxsemi_tornado_setup, 2442 }, 2443 { 2444 .vendor = PCI_VENDOR_ID_MAINPINE, 2445 .device = PCI_ANY_ID, 2446 .subvendor = PCI_ANY_ID, 2447 .subdevice = PCI_ANY_ID, 2448 .init = pci_oxsemi_tornado_init, 2449 .setup = pci_oxsemi_tornado_setup, 2450 }, 2451 { 2452 .vendor = PCI_VENDOR_ID_DIGI, 2453 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2454 .subvendor = PCI_SUBVENDOR_ID_IBM, 2455 .subdevice = PCI_ANY_ID, 2456 .init = pci_oxsemi_tornado_init, 2457 .setup = pci_oxsemi_tornado_setup, 2458 }, 2459 { 2460 .vendor = PCI_VENDOR_ID_INTEL, 2461 .device = 0x8811, 2462 .subvendor = PCI_ANY_ID, 2463 .subdevice = PCI_ANY_ID, 2464 .init = pci_eg20t_init, 2465 .setup = pci_default_setup, 2466 }, 2467 { 2468 .vendor = PCI_VENDOR_ID_INTEL, 2469 .device = 0x8812, 2470 .subvendor = PCI_ANY_ID, 2471 .subdevice = PCI_ANY_ID, 2472 .init = pci_eg20t_init, 2473 .setup = pci_default_setup, 2474 }, 2475 { 2476 .vendor = PCI_VENDOR_ID_INTEL, 2477 .device = 0x8813, 2478 .subvendor = PCI_ANY_ID, 2479 .subdevice = PCI_ANY_ID, 2480 .init = pci_eg20t_init, 2481 .setup = pci_default_setup, 2482 }, 2483 { 2484 .vendor = PCI_VENDOR_ID_INTEL, 2485 .device = 0x8814, 2486 .subvendor = PCI_ANY_ID, 2487 .subdevice = PCI_ANY_ID, 2488 .init = pci_eg20t_init, 2489 .setup = pci_default_setup, 2490 }, 2491 { 2492 .vendor = 0x10DB, 2493 .device = 0x8027, 2494 .subvendor = PCI_ANY_ID, 2495 .subdevice = PCI_ANY_ID, 2496 .init = pci_eg20t_init, 2497 .setup = pci_default_setup, 2498 }, 2499 { 2500 .vendor = 0x10DB, 2501 .device = 0x8028, 2502 .subvendor = PCI_ANY_ID, 2503 .subdevice = PCI_ANY_ID, 2504 .init = pci_eg20t_init, 2505 .setup = pci_default_setup, 2506 }, 2507 { 2508 .vendor = 0x10DB, 2509 .device = 0x8029, 2510 .subvendor = PCI_ANY_ID, 2511 .subdevice = PCI_ANY_ID, 2512 .init = pci_eg20t_init, 2513 .setup = pci_default_setup, 2514 }, 2515 { 2516 .vendor = 0x10DB, 2517 .device = 0x800C, 2518 .subvendor = PCI_ANY_ID, 2519 .subdevice = PCI_ANY_ID, 2520 .init = pci_eg20t_init, 2521 .setup = pci_default_setup, 2522 }, 2523 { 2524 .vendor = 0x10DB, 2525 .device = 0x800D, 2526 .subvendor = PCI_ANY_ID, 2527 .subdevice = PCI_ANY_ID, 2528 .init = pci_eg20t_init, 2529 .setup = pci_default_setup, 2530 }, 2531 /* 2532 * Cronyx Omega PCI (PLX-chip based) 2533 */ 2534 { 2535 .vendor = PCI_VENDOR_ID_PLX, 2536 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2537 .subvendor = PCI_ANY_ID, 2538 .subdevice = PCI_ANY_ID, 2539 .setup = pci_omegapci_setup, 2540 }, 2541 /* WCH CH353 1S1P card (16550 clone) */ 2542 { 2543 .vendor = PCI_VENDOR_ID_WCH, 2544 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2545 .subvendor = PCI_ANY_ID, 2546 .subdevice = PCI_ANY_ID, 2547 .setup = pci_wch_ch353_setup, 2548 }, 2549 /* WCH CH353 2S1P card (16550 clone) */ 2550 { 2551 .vendor = PCI_VENDOR_ID_WCH, 2552 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2553 .subvendor = PCI_ANY_ID, 2554 .subdevice = PCI_ANY_ID, 2555 .setup = pci_wch_ch353_setup, 2556 }, 2557 /* WCH CH353 4S card (16550 clone) */ 2558 { 2559 .vendor = PCI_VENDOR_ID_WCH, 2560 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2561 .subvendor = PCI_ANY_ID, 2562 .subdevice = PCI_ANY_ID, 2563 .setup = pci_wch_ch353_setup, 2564 }, 2565 /* WCH CH353 2S1PF card (16550 clone) */ 2566 { 2567 .vendor = PCI_VENDOR_ID_WCH, 2568 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2569 .subvendor = PCI_ANY_ID, 2570 .subdevice = PCI_ANY_ID, 2571 .setup = pci_wch_ch353_setup, 2572 }, 2573 /* WCH CH352 2S card (16550 clone) */ 2574 { 2575 .vendor = PCI_VENDOR_ID_WCH, 2576 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2577 .subvendor = PCI_ANY_ID, 2578 .subdevice = PCI_ANY_ID, 2579 .setup = pci_wch_ch353_setup, 2580 }, 2581 /* WCH CH355 4S card (16550 clone) */ 2582 { 2583 .vendor = PCI_VENDOR_ID_WCH, 2584 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2585 .subvendor = PCI_ANY_ID, 2586 .subdevice = PCI_ANY_ID, 2587 .setup = pci_wch_ch355_setup, 2588 }, 2589 /* WCH CH382 2S card (16850 clone) */ 2590 { 2591 .vendor = PCIE_VENDOR_ID_WCH, 2592 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2593 .subvendor = PCI_ANY_ID, 2594 .subdevice = PCI_ANY_ID, 2595 .setup = pci_wch_ch38x_setup, 2596 }, 2597 /* WCH CH382 2S1P card (16850 clone) */ 2598 { 2599 .vendor = PCIE_VENDOR_ID_WCH, 2600 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2601 .subvendor = PCI_ANY_ID, 2602 .subdevice = PCI_ANY_ID, 2603 .setup = pci_wch_ch38x_setup, 2604 }, 2605 /* WCH CH384 4S card (16850 clone) */ 2606 { 2607 .vendor = PCIE_VENDOR_ID_WCH, 2608 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2609 .subvendor = PCI_ANY_ID, 2610 .subdevice = PCI_ANY_ID, 2611 .setup = pci_wch_ch38x_setup, 2612 }, 2613 /* WCH CH384 8S card (16850 clone) */ 2614 { 2615 .vendor = PCIE_VENDOR_ID_WCH, 2616 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .init = pci_wch_ch38x_init, 2620 .exit = pci_wch_ch38x_exit, 2621 .setup = pci_wch_ch38x_setup, 2622 }, 2623 /* 2624 * ASIX devices with FIFO bug 2625 */ 2626 { 2627 .vendor = PCI_VENDOR_ID_ASIX, 2628 .device = PCI_ANY_ID, 2629 .subvendor = PCI_ANY_ID, 2630 .subdevice = PCI_ANY_ID, 2631 .setup = pci_asix_setup, 2632 }, 2633 /* 2634 * Broadcom TruManage (NetXtreme) 2635 */ 2636 { 2637 .vendor = PCI_VENDOR_ID_BROADCOM, 2638 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2639 .subvendor = PCI_ANY_ID, 2640 .subdevice = PCI_ANY_ID, 2641 .setup = pci_brcm_trumanage_setup, 2642 }, 2643 { 2644 .vendor = 0x1c29, 2645 .device = 0x1104, 2646 .subvendor = PCI_ANY_ID, 2647 .subdevice = PCI_ANY_ID, 2648 .setup = pci_fintek_setup, 2649 .init = pci_fintek_init, 2650 }, 2651 { 2652 .vendor = 0x1c29, 2653 .device = 0x1108, 2654 .subvendor = PCI_ANY_ID, 2655 .subdevice = PCI_ANY_ID, 2656 .setup = pci_fintek_setup, 2657 .init = pci_fintek_init, 2658 }, 2659 { 2660 .vendor = 0x1c29, 2661 .device = 0x1112, 2662 .subvendor = PCI_ANY_ID, 2663 .subdevice = PCI_ANY_ID, 2664 .setup = pci_fintek_setup, 2665 .init = pci_fintek_init, 2666 }, 2667 /* 2668 * MOXA 2669 */ 2670 { 2671 .vendor = PCI_VENDOR_ID_MOXA, 2672 .device = PCI_ANY_ID, 2673 .subvendor = PCI_ANY_ID, 2674 .subdevice = PCI_ANY_ID, 2675 .setup = pci_moxa_setup, 2676 }, 2677 { 2678 .vendor = 0x1c29, 2679 .device = 0x1204, 2680 .subvendor = PCI_ANY_ID, 2681 .subdevice = PCI_ANY_ID, 2682 .setup = pci_fintek_f815xxa_setup, 2683 .init = pci_fintek_f815xxa_init, 2684 }, 2685 { 2686 .vendor = 0x1c29, 2687 .device = 0x1208, 2688 .subvendor = PCI_ANY_ID, 2689 .subdevice = PCI_ANY_ID, 2690 .setup = pci_fintek_f815xxa_setup, 2691 .init = pci_fintek_f815xxa_init, 2692 }, 2693 { 2694 .vendor = 0x1c29, 2695 .device = 0x1212, 2696 .subvendor = PCI_ANY_ID, 2697 .subdevice = PCI_ANY_ID, 2698 .setup = pci_fintek_f815xxa_setup, 2699 .init = pci_fintek_f815xxa_init, 2700 }, 2701 2702 /* 2703 * Default "match everything" terminator entry 2704 */ 2705 { 2706 .vendor = PCI_ANY_ID, 2707 .device = PCI_ANY_ID, 2708 .subvendor = PCI_ANY_ID, 2709 .subdevice = PCI_ANY_ID, 2710 .setup = pci_default_setup, 2711 } 2712 }; 2713 2714 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2715 { 2716 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2717 } 2718 2719 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2720 { 2721 struct pci_serial_quirk *quirk; 2722 2723 for (quirk = pci_serial_quirks; ; quirk++) 2724 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2725 quirk_id_matches(quirk->device, dev->device) && 2726 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2727 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2728 break; 2729 return quirk; 2730 } 2731 2732 /* 2733 * This is the configuration table for all of the PCI serial boards 2734 * which we support. It is directly indexed by the pci_board_num_t enum 2735 * value, which is encoded in the pci_device_id PCI probe table's 2736 * driver_data member. 2737 * 2738 * The makeup of these names are: 2739 * pbn_bn{_bt}_n_baud{_offsetinhex} 2740 * 2741 * bn = PCI BAR number 2742 * bt = Index using PCI BARs 2743 * n = number of serial ports 2744 * baud = baud rate 2745 * offsetinhex = offset for each sequential port (in hex) 2746 * 2747 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2748 * 2749 * Please note: in theory if n = 1, _bt infix should make no difference. 2750 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2751 */ 2752 enum pci_board_num_t { 2753 pbn_default = 0, 2754 2755 pbn_b0_1_115200, 2756 pbn_b0_2_115200, 2757 pbn_b0_4_115200, 2758 pbn_b0_5_115200, 2759 pbn_b0_8_115200, 2760 2761 pbn_b0_1_921600, 2762 pbn_b0_2_921600, 2763 pbn_b0_4_921600, 2764 2765 pbn_b0_2_1130000, 2766 2767 pbn_b0_4_1152000, 2768 2769 pbn_b0_4_1250000, 2770 2771 pbn_b0_2_1843200, 2772 pbn_b0_4_1843200, 2773 2774 pbn_b0_1_15625000, 2775 2776 pbn_b0_bt_1_115200, 2777 pbn_b0_bt_2_115200, 2778 pbn_b0_bt_4_115200, 2779 pbn_b0_bt_8_115200, 2780 2781 pbn_b0_bt_1_460800, 2782 pbn_b0_bt_2_460800, 2783 pbn_b0_bt_4_460800, 2784 2785 pbn_b0_bt_1_921600, 2786 pbn_b0_bt_2_921600, 2787 pbn_b0_bt_4_921600, 2788 pbn_b0_bt_8_921600, 2789 2790 pbn_b1_1_115200, 2791 pbn_b1_2_115200, 2792 pbn_b1_4_115200, 2793 pbn_b1_8_115200, 2794 pbn_b1_16_115200, 2795 2796 pbn_b1_1_921600, 2797 pbn_b1_2_921600, 2798 pbn_b1_4_921600, 2799 pbn_b1_8_921600, 2800 2801 pbn_b1_2_1250000, 2802 2803 pbn_b1_bt_1_115200, 2804 pbn_b1_bt_2_115200, 2805 pbn_b1_bt_4_115200, 2806 2807 pbn_b1_bt_2_921600, 2808 2809 pbn_b1_1_1382400, 2810 pbn_b1_2_1382400, 2811 pbn_b1_4_1382400, 2812 pbn_b1_8_1382400, 2813 2814 pbn_b2_1_115200, 2815 pbn_b2_2_115200, 2816 pbn_b2_4_115200, 2817 pbn_b2_8_115200, 2818 2819 pbn_b2_1_460800, 2820 pbn_b2_4_460800, 2821 pbn_b2_8_460800, 2822 pbn_b2_16_460800, 2823 2824 pbn_b2_1_921600, 2825 pbn_b2_4_921600, 2826 pbn_b2_8_921600, 2827 2828 pbn_b2_8_1152000, 2829 2830 pbn_b2_bt_1_115200, 2831 pbn_b2_bt_2_115200, 2832 pbn_b2_bt_4_115200, 2833 2834 pbn_b2_bt_2_921600, 2835 pbn_b2_bt_4_921600, 2836 2837 pbn_b3_2_115200, 2838 pbn_b3_4_115200, 2839 pbn_b3_8_115200, 2840 2841 pbn_b4_bt_2_921600, 2842 pbn_b4_bt_4_921600, 2843 pbn_b4_bt_8_921600, 2844 2845 /* 2846 * Board-specific versions. 2847 */ 2848 pbn_panacom, 2849 pbn_panacom2, 2850 pbn_panacom4, 2851 pbn_plx_romulus, 2852 pbn_oxsemi, 2853 pbn_oxsemi_1_15625000, 2854 pbn_oxsemi_2_15625000, 2855 pbn_oxsemi_4_15625000, 2856 pbn_oxsemi_8_15625000, 2857 pbn_intel_i960, 2858 pbn_sgi_ioc3, 2859 pbn_computone_4, 2860 pbn_computone_6, 2861 pbn_computone_8, 2862 pbn_sbsxrsio, 2863 pbn_pasemi_1682M, 2864 pbn_ni8430_2, 2865 pbn_ni8430_4, 2866 pbn_ni8430_8, 2867 pbn_ni8430_16, 2868 pbn_ADDIDATA_PCIe_1_3906250, 2869 pbn_ADDIDATA_PCIe_2_3906250, 2870 pbn_ADDIDATA_PCIe_4_3906250, 2871 pbn_ADDIDATA_PCIe_8_3906250, 2872 pbn_ce4100_1_115200, 2873 pbn_omegapci, 2874 pbn_NETMOS9900_2s_115200, 2875 pbn_brcm_trumanage, 2876 pbn_fintek_4, 2877 pbn_fintek_8, 2878 pbn_fintek_12, 2879 pbn_fintek_F81504A, 2880 pbn_fintek_F81508A, 2881 pbn_fintek_F81512A, 2882 pbn_wch382_2, 2883 pbn_wch384_4, 2884 pbn_wch384_8, 2885 pbn_sunix_pci_1s, 2886 pbn_sunix_pci_2s, 2887 pbn_sunix_pci_4s, 2888 pbn_sunix_pci_8s, 2889 pbn_sunix_pci_16s, 2890 pbn_titan_1_4000000, 2891 pbn_titan_2_4000000, 2892 pbn_titan_4_4000000, 2893 pbn_titan_8_4000000, 2894 pbn_moxa8250_2p, 2895 pbn_moxa8250_4p, 2896 pbn_moxa8250_8p, 2897 }; 2898 2899 /* 2900 * uart_offset - the space between channels 2901 * reg_shift - describes how the UART registers are mapped 2902 * to PCI memory by the card. 2903 * For example IER register on SBS, Inc. PMC-OctPro is located at 2904 * offset 0x10 from the UART base, while UART_IER is defined as 1 2905 * in include/linux/serial_reg.h, 2906 * see first lines of serial_in() and serial_out() in 8250.c 2907 */ 2908 2909 static struct pciserial_board pci_boards[] = { 2910 [pbn_default] = { 2911 .flags = FL_BASE0, 2912 .num_ports = 1, 2913 .base_baud = 115200, 2914 .uart_offset = 8, 2915 }, 2916 [pbn_b0_1_115200] = { 2917 .flags = FL_BASE0, 2918 .num_ports = 1, 2919 .base_baud = 115200, 2920 .uart_offset = 8, 2921 }, 2922 [pbn_b0_2_115200] = { 2923 .flags = FL_BASE0, 2924 .num_ports = 2, 2925 .base_baud = 115200, 2926 .uart_offset = 8, 2927 }, 2928 [pbn_b0_4_115200] = { 2929 .flags = FL_BASE0, 2930 .num_ports = 4, 2931 .base_baud = 115200, 2932 .uart_offset = 8, 2933 }, 2934 [pbn_b0_5_115200] = { 2935 .flags = FL_BASE0, 2936 .num_ports = 5, 2937 .base_baud = 115200, 2938 .uart_offset = 8, 2939 }, 2940 [pbn_b0_8_115200] = { 2941 .flags = FL_BASE0, 2942 .num_ports = 8, 2943 .base_baud = 115200, 2944 .uart_offset = 8, 2945 }, 2946 [pbn_b0_1_921600] = { 2947 .flags = FL_BASE0, 2948 .num_ports = 1, 2949 .base_baud = 921600, 2950 .uart_offset = 8, 2951 }, 2952 [pbn_b0_2_921600] = { 2953 .flags = FL_BASE0, 2954 .num_ports = 2, 2955 .base_baud = 921600, 2956 .uart_offset = 8, 2957 }, 2958 [pbn_b0_4_921600] = { 2959 .flags = FL_BASE0, 2960 .num_ports = 4, 2961 .base_baud = 921600, 2962 .uart_offset = 8, 2963 }, 2964 2965 [pbn_b0_2_1130000] = { 2966 .flags = FL_BASE0, 2967 .num_ports = 2, 2968 .base_baud = 1130000, 2969 .uart_offset = 8, 2970 }, 2971 2972 [pbn_b0_4_1152000] = { 2973 .flags = FL_BASE0, 2974 .num_ports = 4, 2975 .base_baud = 1152000, 2976 .uart_offset = 8, 2977 }, 2978 2979 [pbn_b0_4_1250000] = { 2980 .flags = FL_BASE0, 2981 .num_ports = 4, 2982 .base_baud = 1250000, 2983 .uart_offset = 8, 2984 }, 2985 2986 [pbn_b0_2_1843200] = { 2987 .flags = FL_BASE0, 2988 .num_ports = 2, 2989 .base_baud = 1843200, 2990 .uart_offset = 8, 2991 }, 2992 [pbn_b0_4_1843200] = { 2993 .flags = FL_BASE0, 2994 .num_ports = 4, 2995 .base_baud = 1843200, 2996 .uart_offset = 8, 2997 }, 2998 2999 [pbn_b0_1_15625000] = { 3000 .flags = FL_BASE0, 3001 .num_ports = 1, 3002 .base_baud = 15625000, 3003 .uart_offset = 8, 3004 }, 3005 3006 [pbn_b0_bt_1_115200] = { 3007 .flags = FL_BASE0|FL_BASE_BARS, 3008 .num_ports = 1, 3009 .base_baud = 115200, 3010 .uart_offset = 8, 3011 }, 3012 [pbn_b0_bt_2_115200] = { 3013 .flags = FL_BASE0|FL_BASE_BARS, 3014 .num_ports = 2, 3015 .base_baud = 115200, 3016 .uart_offset = 8, 3017 }, 3018 [pbn_b0_bt_4_115200] = { 3019 .flags = FL_BASE0|FL_BASE_BARS, 3020 .num_ports = 4, 3021 .base_baud = 115200, 3022 .uart_offset = 8, 3023 }, 3024 [pbn_b0_bt_8_115200] = { 3025 .flags = FL_BASE0|FL_BASE_BARS, 3026 .num_ports = 8, 3027 .base_baud = 115200, 3028 .uart_offset = 8, 3029 }, 3030 3031 [pbn_b0_bt_1_460800] = { 3032 .flags = FL_BASE0|FL_BASE_BARS, 3033 .num_ports = 1, 3034 .base_baud = 460800, 3035 .uart_offset = 8, 3036 }, 3037 [pbn_b0_bt_2_460800] = { 3038 .flags = FL_BASE0|FL_BASE_BARS, 3039 .num_ports = 2, 3040 .base_baud = 460800, 3041 .uart_offset = 8, 3042 }, 3043 [pbn_b0_bt_4_460800] = { 3044 .flags = FL_BASE0|FL_BASE_BARS, 3045 .num_ports = 4, 3046 .base_baud = 460800, 3047 .uart_offset = 8, 3048 }, 3049 3050 [pbn_b0_bt_1_921600] = { 3051 .flags = FL_BASE0|FL_BASE_BARS, 3052 .num_ports = 1, 3053 .base_baud = 921600, 3054 .uart_offset = 8, 3055 }, 3056 [pbn_b0_bt_2_921600] = { 3057 .flags = FL_BASE0|FL_BASE_BARS, 3058 .num_ports = 2, 3059 .base_baud = 921600, 3060 .uart_offset = 8, 3061 }, 3062 [pbn_b0_bt_4_921600] = { 3063 .flags = FL_BASE0|FL_BASE_BARS, 3064 .num_ports = 4, 3065 .base_baud = 921600, 3066 .uart_offset = 8, 3067 }, 3068 [pbn_b0_bt_8_921600] = { 3069 .flags = FL_BASE0|FL_BASE_BARS, 3070 .num_ports = 8, 3071 .base_baud = 921600, 3072 .uart_offset = 8, 3073 }, 3074 3075 [pbn_b1_1_115200] = { 3076 .flags = FL_BASE1, 3077 .num_ports = 1, 3078 .base_baud = 115200, 3079 .uart_offset = 8, 3080 }, 3081 [pbn_b1_2_115200] = { 3082 .flags = FL_BASE1, 3083 .num_ports = 2, 3084 .base_baud = 115200, 3085 .uart_offset = 8, 3086 }, 3087 [pbn_b1_4_115200] = { 3088 .flags = FL_BASE1, 3089 .num_ports = 4, 3090 .base_baud = 115200, 3091 .uart_offset = 8, 3092 }, 3093 [pbn_b1_8_115200] = { 3094 .flags = FL_BASE1, 3095 .num_ports = 8, 3096 .base_baud = 115200, 3097 .uart_offset = 8, 3098 }, 3099 [pbn_b1_16_115200] = { 3100 .flags = FL_BASE1, 3101 .num_ports = 16, 3102 .base_baud = 115200, 3103 .uart_offset = 8, 3104 }, 3105 3106 [pbn_b1_1_921600] = { 3107 .flags = FL_BASE1, 3108 .num_ports = 1, 3109 .base_baud = 921600, 3110 .uart_offset = 8, 3111 }, 3112 [pbn_b1_2_921600] = { 3113 .flags = FL_BASE1, 3114 .num_ports = 2, 3115 .base_baud = 921600, 3116 .uart_offset = 8, 3117 }, 3118 [pbn_b1_4_921600] = { 3119 .flags = FL_BASE1, 3120 .num_ports = 4, 3121 .base_baud = 921600, 3122 .uart_offset = 8, 3123 }, 3124 [pbn_b1_8_921600] = { 3125 .flags = FL_BASE1, 3126 .num_ports = 8, 3127 .base_baud = 921600, 3128 .uart_offset = 8, 3129 }, 3130 [pbn_b1_2_1250000] = { 3131 .flags = FL_BASE1, 3132 .num_ports = 2, 3133 .base_baud = 1250000, 3134 .uart_offset = 8, 3135 }, 3136 3137 [pbn_b1_bt_1_115200] = { 3138 .flags = FL_BASE1|FL_BASE_BARS, 3139 .num_ports = 1, 3140 .base_baud = 115200, 3141 .uart_offset = 8, 3142 }, 3143 [pbn_b1_bt_2_115200] = { 3144 .flags = FL_BASE1|FL_BASE_BARS, 3145 .num_ports = 2, 3146 .base_baud = 115200, 3147 .uart_offset = 8, 3148 }, 3149 [pbn_b1_bt_4_115200] = { 3150 .flags = FL_BASE1|FL_BASE_BARS, 3151 .num_ports = 4, 3152 .base_baud = 115200, 3153 .uart_offset = 8, 3154 }, 3155 3156 [pbn_b1_bt_2_921600] = { 3157 .flags = FL_BASE1|FL_BASE_BARS, 3158 .num_ports = 2, 3159 .base_baud = 921600, 3160 .uart_offset = 8, 3161 }, 3162 3163 [pbn_b1_1_1382400] = { 3164 .flags = FL_BASE1, 3165 .num_ports = 1, 3166 .base_baud = 1382400, 3167 .uart_offset = 8, 3168 }, 3169 [pbn_b1_2_1382400] = { 3170 .flags = FL_BASE1, 3171 .num_ports = 2, 3172 .base_baud = 1382400, 3173 .uart_offset = 8, 3174 }, 3175 [pbn_b1_4_1382400] = { 3176 .flags = FL_BASE1, 3177 .num_ports = 4, 3178 .base_baud = 1382400, 3179 .uart_offset = 8, 3180 }, 3181 [pbn_b1_8_1382400] = { 3182 .flags = FL_BASE1, 3183 .num_ports = 8, 3184 .base_baud = 1382400, 3185 .uart_offset = 8, 3186 }, 3187 3188 [pbn_b2_1_115200] = { 3189 .flags = FL_BASE2, 3190 .num_ports = 1, 3191 .base_baud = 115200, 3192 .uart_offset = 8, 3193 }, 3194 [pbn_b2_2_115200] = { 3195 .flags = FL_BASE2, 3196 .num_ports = 2, 3197 .base_baud = 115200, 3198 .uart_offset = 8, 3199 }, 3200 [pbn_b2_4_115200] = { 3201 .flags = FL_BASE2, 3202 .num_ports = 4, 3203 .base_baud = 115200, 3204 .uart_offset = 8, 3205 }, 3206 [pbn_b2_8_115200] = { 3207 .flags = FL_BASE2, 3208 .num_ports = 8, 3209 .base_baud = 115200, 3210 .uart_offset = 8, 3211 }, 3212 3213 [pbn_b2_1_460800] = { 3214 .flags = FL_BASE2, 3215 .num_ports = 1, 3216 .base_baud = 460800, 3217 .uart_offset = 8, 3218 }, 3219 [pbn_b2_4_460800] = { 3220 .flags = FL_BASE2, 3221 .num_ports = 4, 3222 .base_baud = 460800, 3223 .uart_offset = 8, 3224 }, 3225 [pbn_b2_8_460800] = { 3226 .flags = FL_BASE2, 3227 .num_ports = 8, 3228 .base_baud = 460800, 3229 .uart_offset = 8, 3230 }, 3231 [pbn_b2_16_460800] = { 3232 .flags = FL_BASE2, 3233 .num_ports = 16, 3234 .base_baud = 460800, 3235 .uart_offset = 8, 3236 }, 3237 3238 [pbn_b2_1_921600] = { 3239 .flags = FL_BASE2, 3240 .num_ports = 1, 3241 .base_baud = 921600, 3242 .uart_offset = 8, 3243 }, 3244 [pbn_b2_4_921600] = { 3245 .flags = FL_BASE2, 3246 .num_ports = 4, 3247 .base_baud = 921600, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b2_8_921600] = { 3251 .flags = FL_BASE2, 3252 .num_ports = 8, 3253 .base_baud = 921600, 3254 .uart_offset = 8, 3255 }, 3256 3257 [pbn_b2_8_1152000] = { 3258 .flags = FL_BASE2, 3259 .num_ports = 8, 3260 .base_baud = 1152000, 3261 .uart_offset = 8, 3262 }, 3263 3264 [pbn_b2_bt_1_115200] = { 3265 .flags = FL_BASE2|FL_BASE_BARS, 3266 .num_ports = 1, 3267 .base_baud = 115200, 3268 .uart_offset = 8, 3269 }, 3270 [pbn_b2_bt_2_115200] = { 3271 .flags = FL_BASE2|FL_BASE_BARS, 3272 .num_ports = 2, 3273 .base_baud = 115200, 3274 .uart_offset = 8, 3275 }, 3276 [pbn_b2_bt_4_115200] = { 3277 .flags = FL_BASE2|FL_BASE_BARS, 3278 .num_ports = 4, 3279 .base_baud = 115200, 3280 .uart_offset = 8, 3281 }, 3282 3283 [pbn_b2_bt_2_921600] = { 3284 .flags = FL_BASE2|FL_BASE_BARS, 3285 .num_ports = 2, 3286 .base_baud = 921600, 3287 .uart_offset = 8, 3288 }, 3289 [pbn_b2_bt_4_921600] = { 3290 .flags = FL_BASE2|FL_BASE_BARS, 3291 .num_ports = 4, 3292 .base_baud = 921600, 3293 .uart_offset = 8, 3294 }, 3295 3296 [pbn_b3_2_115200] = { 3297 .flags = FL_BASE3, 3298 .num_ports = 2, 3299 .base_baud = 115200, 3300 .uart_offset = 8, 3301 }, 3302 [pbn_b3_4_115200] = { 3303 .flags = FL_BASE3, 3304 .num_ports = 4, 3305 .base_baud = 115200, 3306 .uart_offset = 8, 3307 }, 3308 [pbn_b3_8_115200] = { 3309 .flags = FL_BASE3, 3310 .num_ports = 8, 3311 .base_baud = 115200, 3312 .uart_offset = 8, 3313 }, 3314 3315 [pbn_b4_bt_2_921600] = { 3316 .flags = FL_BASE4, 3317 .num_ports = 2, 3318 .base_baud = 921600, 3319 .uart_offset = 8, 3320 }, 3321 [pbn_b4_bt_4_921600] = { 3322 .flags = FL_BASE4, 3323 .num_ports = 4, 3324 .base_baud = 921600, 3325 .uart_offset = 8, 3326 }, 3327 [pbn_b4_bt_8_921600] = { 3328 .flags = FL_BASE4, 3329 .num_ports = 8, 3330 .base_baud = 921600, 3331 .uart_offset = 8, 3332 }, 3333 3334 /* 3335 * Entries following this are board-specific. 3336 */ 3337 3338 /* 3339 * Panacom - IOMEM 3340 */ 3341 [pbn_panacom] = { 3342 .flags = FL_BASE2, 3343 .num_ports = 2, 3344 .base_baud = 921600, 3345 .uart_offset = 0x400, 3346 .reg_shift = 7, 3347 }, 3348 [pbn_panacom2] = { 3349 .flags = FL_BASE2|FL_BASE_BARS, 3350 .num_ports = 2, 3351 .base_baud = 921600, 3352 .uart_offset = 0x400, 3353 .reg_shift = 7, 3354 }, 3355 [pbn_panacom4] = { 3356 .flags = FL_BASE2|FL_BASE_BARS, 3357 .num_ports = 4, 3358 .base_baud = 921600, 3359 .uart_offset = 0x400, 3360 .reg_shift = 7, 3361 }, 3362 3363 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3364 [pbn_plx_romulus] = { 3365 .flags = FL_BASE2, 3366 .num_ports = 4, 3367 .base_baud = 921600, 3368 .uart_offset = 8 << 2, 3369 .reg_shift = 2, 3370 .first_offset = 0x03, 3371 }, 3372 3373 /* 3374 * This board uses the size of PCI Base region 0 to 3375 * signal now many ports are available 3376 */ 3377 [pbn_oxsemi] = { 3378 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3379 .num_ports = 32, 3380 .base_baud = 115200, 3381 .uart_offset = 8, 3382 }, 3383 [pbn_oxsemi_1_15625000] = { 3384 .flags = FL_BASE0, 3385 .num_ports = 1, 3386 .base_baud = 15625000, 3387 .uart_offset = 0x200, 3388 .first_offset = 0x1000, 3389 }, 3390 [pbn_oxsemi_2_15625000] = { 3391 .flags = FL_BASE0, 3392 .num_ports = 2, 3393 .base_baud = 15625000, 3394 .uart_offset = 0x200, 3395 .first_offset = 0x1000, 3396 }, 3397 [pbn_oxsemi_4_15625000] = { 3398 .flags = FL_BASE0, 3399 .num_ports = 4, 3400 .base_baud = 15625000, 3401 .uart_offset = 0x200, 3402 .first_offset = 0x1000, 3403 }, 3404 [pbn_oxsemi_8_15625000] = { 3405 .flags = FL_BASE0, 3406 .num_ports = 8, 3407 .base_baud = 15625000, 3408 .uart_offset = 0x200, 3409 .first_offset = 0x1000, 3410 }, 3411 3412 3413 /* 3414 * EKF addition for i960 Boards form EKF with serial port. 3415 * Max 256 ports. 3416 */ 3417 [pbn_intel_i960] = { 3418 .flags = FL_BASE0, 3419 .num_ports = 32, 3420 .base_baud = 921600, 3421 .uart_offset = 8 << 2, 3422 .reg_shift = 2, 3423 .first_offset = 0x10000, 3424 }, 3425 [pbn_sgi_ioc3] = { 3426 .flags = FL_BASE0|FL_NOIRQ, 3427 .num_ports = 1, 3428 .base_baud = 458333, 3429 .uart_offset = 8, 3430 .reg_shift = 0, 3431 .first_offset = 0x20178, 3432 }, 3433 3434 /* 3435 * Computone - uses IOMEM. 3436 */ 3437 [pbn_computone_4] = { 3438 .flags = FL_BASE0, 3439 .num_ports = 4, 3440 .base_baud = 921600, 3441 .uart_offset = 0x40, 3442 .reg_shift = 2, 3443 .first_offset = 0x200, 3444 }, 3445 [pbn_computone_6] = { 3446 .flags = FL_BASE0, 3447 .num_ports = 6, 3448 .base_baud = 921600, 3449 .uart_offset = 0x40, 3450 .reg_shift = 2, 3451 .first_offset = 0x200, 3452 }, 3453 [pbn_computone_8] = { 3454 .flags = FL_BASE0, 3455 .num_ports = 8, 3456 .base_baud = 921600, 3457 .uart_offset = 0x40, 3458 .reg_shift = 2, 3459 .first_offset = 0x200, 3460 }, 3461 [pbn_sbsxrsio] = { 3462 .flags = FL_BASE0, 3463 .num_ports = 8, 3464 .base_baud = 460800, 3465 .uart_offset = 256, 3466 .reg_shift = 4, 3467 }, 3468 /* 3469 * PA Semi PWRficient PA6T-1682M on-chip UART 3470 */ 3471 [pbn_pasemi_1682M] = { 3472 .flags = FL_BASE0, 3473 .num_ports = 1, 3474 .base_baud = 8333333, 3475 }, 3476 /* 3477 * National Instruments 843x 3478 */ 3479 [pbn_ni8430_16] = { 3480 .flags = FL_BASE0, 3481 .num_ports = 16, 3482 .base_baud = 3686400, 3483 .uart_offset = 0x10, 3484 .first_offset = 0x800, 3485 }, 3486 [pbn_ni8430_8] = { 3487 .flags = FL_BASE0, 3488 .num_ports = 8, 3489 .base_baud = 3686400, 3490 .uart_offset = 0x10, 3491 .first_offset = 0x800, 3492 }, 3493 [pbn_ni8430_4] = { 3494 .flags = FL_BASE0, 3495 .num_ports = 4, 3496 .base_baud = 3686400, 3497 .uart_offset = 0x10, 3498 .first_offset = 0x800, 3499 }, 3500 [pbn_ni8430_2] = { 3501 .flags = FL_BASE0, 3502 .num_ports = 2, 3503 .base_baud = 3686400, 3504 .uart_offset = 0x10, 3505 .first_offset = 0x800, 3506 }, 3507 /* 3508 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3509 */ 3510 [pbn_ADDIDATA_PCIe_1_3906250] = { 3511 .flags = FL_BASE0, 3512 .num_ports = 1, 3513 .base_baud = 3906250, 3514 .uart_offset = 0x200, 3515 .first_offset = 0x1000, 3516 }, 3517 [pbn_ADDIDATA_PCIe_2_3906250] = { 3518 .flags = FL_BASE0, 3519 .num_ports = 2, 3520 .base_baud = 3906250, 3521 .uart_offset = 0x200, 3522 .first_offset = 0x1000, 3523 }, 3524 [pbn_ADDIDATA_PCIe_4_3906250] = { 3525 .flags = FL_BASE0, 3526 .num_ports = 4, 3527 .base_baud = 3906250, 3528 .uart_offset = 0x200, 3529 .first_offset = 0x1000, 3530 }, 3531 [pbn_ADDIDATA_PCIe_8_3906250] = { 3532 .flags = FL_BASE0, 3533 .num_ports = 8, 3534 .base_baud = 3906250, 3535 .uart_offset = 0x200, 3536 .first_offset = 0x1000, 3537 }, 3538 [pbn_ce4100_1_115200] = { 3539 .flags = FL_BASE_BARS, 3540 .num_ports = 2, 3541 .base_baud = 921600, 3542 .reg_shift = 2, 3543 }, 3544 [pbn_omegapci] = { 3545 .flags = FL_BASE0, 3546 .num_ports = 8, 3547 .base_baud = 115200, 3548 .uart_offset = 0x200, 3549 }, 3550 [pbn_NETMOS9900_2s_115200] = { 3551 .flags = FL_BASE0, 3552 .num_ports = 2, 3553 .base_baud = 115200, 3554 }, 3555 [pbn_brcm_trumanage] = { 3556 .flags = FL_BASE0, 3557 .num_ports = 1, 3558 .reg_shift = 2, 3559 .base_baud = 115200, 3560 }, 3561 [pbn_fintek_4] = { 3562 .num_ports = 4, 3563 .uart_offset = 8, 3564 .base_baud = 115200, 3565 .first_offset = 0x40, 3566 }, 3567 [pbn_fintek_8] = { 3568 .num_ports = 8, 3569 .uart_offset = 8, 3570 .base_baud = 115200, 3571 .first_offset = 0x40, 3572 }, 3573 [pbn_fintek_12] = { 3574 .num_ports = 12, 3575 .uart_offset = 8, 3576 .base_baud = 115200, 3577 .first_offset = 0x40, 3578 }, 3579 [pbn_fintek_F81504A] = { 3580 .num_ports = 4, 3581 .uart_offset = 8, 3582 .base_baud = 115200, 3583 }, 3584 [pbn_fintek_F81508A] = { 3585 .num_ports = 8, 3586 .uart_offset = 8, 3587 .base_baud = 115200, 3588 }, 3589 [pbn_fintek_F81512A] = { 3590 .num_ports = 12, 3591 .uart_offset = 8, 3592 .base_baud = 115200, 3593 }, 3594 [pbn_wch382_2] = { 3595 .flags = FL_BASE0, 3596 .num_ports = 2, 3597 .base_baud = 115200, 3598 .uart_offset = 8, 3599 .first_offset = 0xC0, 3600 }, 3601 [pbn_wch384_4] = { 3602 .flags = FL_BASE0, 3603 .num_ports = 4, 3604 .base_baud = 115200, 3605 .uart_offset = 8, 3606 .first_offset = 0xC0, 3607 }, 3608 [pbn_wch384_8] = { 3609 .flags = FL_BASE0, 3610 .num_ports = 8, 3611 .base_baud = 115200, 3612 .uart_offset = 8, 3613 .first_offset = 0x00, 3614 }, 3615 [pbn_sunix_pci_1s] = { 3616 .num_ports = 1, 3617 .base_baud = 921600, 3618 .uart_offset = 0x8, 3619 }, 3620 [pbn_sunix_pci_2s] = { 3621 .num_ports = 2, 3622 .base_baud = 921600, 3623 .uart_offset = 0x8, 3624 }, 3625 [pbn_sunix_pci_4s] = { 3626 .num_ports = 4, 3627 .base_baud = 921600, 3628 .uart_offset = 0x8, 3629 }, 3630 [pbn_sunix_pci_8s] = { 3631 .num_ports = 8, 3632 .base_baud = 921600, 3633 .uart_offset = 0x8, 3634 }, 3635 [pbn_sunix_pci_16s] = { 3636 .num_ports = 16, 3637 .base_baud = 921600, 3638 .uart_offset = 0x8, 3639 }, 3640 [pbn_titan_1_4000000] = { 3641 .flags = FL_BASE0, 3642 .num_ports = 1, 3643 .base_baud = 4000000, 3644 .uart_offset = 0x200, 3645 .first_offset = 0x1000, 3646 }, 3647 [pbn_titan_2_4000000] = { 3648 .flags = FL_BASE0, 3649 .num_ports = 2, 3650 .base_baud = 4000000, 3651 .uart_offset = 0x200, 3652 .first_offset = 0x1000, 3653 }, 3654 [pbn_titan_4_4000000] = { 3655 .flags = FL_BASE0, 3656 .num_ports = 4, 3657 .base_baud = 4000000, 3658 .uart_offset = 0x200, 3659 .first_offset = 0x1000, 3660 }, 3661 [pbn_titan_8_4000000] = { 3662 .flags = FL_BASE0, 3663 .num_ports = 8, 3664 .base_baud = 4000000, 3665 .uart_offset = 0x200, 3666 .first_offset = 0x1000, 3667 }, 3668 [pbn_moxa8250_2p] = { 3669 .flags = FL_BASE1, 3670 .num_ports = 2, 3671 .base_baud = 921600, 3672 .uart_offset = 0x200, 3673 }, 3674 [pbn_moxa8250_4p] = { 3675 .flags = FL_BASE1, 3676 .num_ports = 4, 3677 .base_baud = 921600, 3678 .uart_offset = 0x200, 3679 }, 3680 [pbn_moxa8250_8p] = { 3681 .flags = FL_BASE1, 3682 .num_ports = 8, 3683 .base_baud = 921600, 3684 .uart_offset = 0x200, 3685 }, 3686 }; 3687 3688 #define REPORT_CONFIG(option) \ 3689 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3690 #define REPORT_8250_CONFIG(option) \ 3691 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3692 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3693 3694 static const struct pci_device_id blacklist[] = { 3695 /* softmodems */ 3696 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3697 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3698 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3699 3700 /* multi-io cards handled by parport_serial */ 3701 /* WCH CH353 2S1P */ 3702 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3703 /* WCH CH353 1S1P */ 3704 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3705 /* WCH CH382 2S1P */ 3706 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3707 3708 /* Intel platforms with MID UART */ 3709 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3710 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3711 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3712 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3713 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3714 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3715 3716 /* Intel platforms with DesignWare UART */ 3717 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3718 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3719 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3720 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3721 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3722 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3723 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3724 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3725 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3726 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3727 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3728 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3729 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3730 3731 /* Exar devices */ 3732 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3733 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3734 3735 /* Pericom devices */ 3736 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3737 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3738 3739 /* End of the black list */ 3740 { } 3741 }; 3742 3743 static int serial_pci_is_class_communication(struct pci_dev *dev) 3744 { 3745 /* 3746 * If it is not a communications device or the programming 3747 * interface is greater than 6, give up. 3748 */ 3749 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3750 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3751 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3752 (dev->class & 0xff) > 6) 3753 return -ENODEV; 3754 3755 return 0; 3756 } 3757 3758 /* 3759 * Given a complete unknown PCI device, try to use some heuristics to 3760 * guess what the configuration might be, based on the pitiful PCI 3761 * serial specs. Returns 0 on success, -ENODEV on failure. 3762 */ 3763 static int 3764 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3765 { 3766 int num_iomem, num_port, first_port = -1, i; 3767 int rc; 3768 3769 rc = serial_pci_is_class_communication(dev); 3770 if (rc) 3771 return rc; 3772 3773 /* 3774 * Should we try to make guesses for multiport serial devices later? 3775 */ 3776 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3777 return -ENODEV; 3778 3779 num_iomem = num_port = 0; 3780 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3781 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3782 num_port++; 3783 if (first_port == -1) 3784 first_port = i; 3785 } 3786 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3787 num_iomem++; 3788 } 3789 3790 /* 3791 * If there is 1 or 0 iomem regions, and exactly one port, 3792 * use it. We guess the number of ports based on the IO 3793 * region size. 3794 */ 3795 if (num_iomem <= 1 && num_port == 1) { 3796 board->flags = first_port; 3797 board->num_ports = pci_resource_len(dev, first_port) / 8; 3798 return 0; 3799 } 3800 3801 /* 3802 * Now guess if we've got a board which indexes by BARs. 3803 * Each IO BAR should be 8 bytes, and they should follow 3804 * consecutively. 3805 */ 3806 first_port = -1; 3807 num_port = 0; 3808 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3809 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3810 pci_resource_len(dev, i) == 8 && 3811 (first_port == -1 || (first_port + num_port) == i)) { 3812 num_port++; 3813 if (first_port == -1) 3814 first_port = i; 3815 } 3816 } 3817 3818 if (num_port > 1) { 3819 board->flags = first_port | FL_BASE_BARS; 3820 board->num_ports = num_port; 3821 return 0; 3822 } 3823 3824 return -ENODEV; 3825 } 3826 3827 static inline int 3828 serial_pci_matches(const struct pciserial_board *board, 3829 const struct pciserial_board *guessed) 3830 { 3831 return 3832 board->num_ports == guessed->num_ports && 3833 board->base_baud == guessed->base_baud && 3834 board->uart_offset == guessed->uart_offset && 3835 board->reg_shift == guessed->reg_shift && 3836 board->first_offset == guessed->first_offset; 3837 } 3838 3839 struct serial_private * 3840 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3841 { 3842 struct uart_8250_port uart; 3843 struct serial_private *priv; 3844 struct pci_serial_quirk *quirk; 3845 int rc, nr_ports, i; 3846 3847 nr_ports = board->num_ports; 3848 3849 /* 3850 * Find an init and setup quirks. 3851 */ 3852 quirk = find_quirk(dev); 3853 3854 /* 3855 * Run the new-style initialization function. 3856 * The initialization function returns: 3857 * <0 - error 3858 * 0 - use board->num_ports 3859 * >0 - number of ports 3860 */ 3861 if (quirk->init) { 3862 rc = quirk->init(dev); 3863 if (rc < 0) { 3864 priv = ERR_PTR(rc); 3865 goto err_out; 3866 } 3867 if (rc) 3868 nr_ports = rc; 3869 } 3870 3871 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3872 if (!priv) { 3873 priv = ERR_PTR(-ENOMEM); 3874 goto err_deinit; 3875 } 3876 3877 priv->dev = dev; 3878 priv->quirk = quirk; 3879 3880 memset(&uart, 0, sizeof(uart)); 3881 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3882 uart.port.uartclk = board->base_baud * 16; 3883 3884 if (board->flags & FL_NOIRQ) { 3885 uart.port.irq = 0; 3886 } else { 3887 if (pci_match_id(pci_use_msi, dev)) { 3888 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3889 pci_set_master(dev); 3890 uart.port.flags &= ~UPF_SHARE_IRQ; 3891 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3892 } else { 3893 pci_dbg(dev, "Using legacy interrupts\n"); 3894 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3895 } 3896 if (rc < 0) { 3897 kfree(priv); 3898 priv = ERR_PTR(rc); 3899 goto err_deinit; 3900 } 3901 3902 uart.port.irq = pci_irq_vector(dev, 0); 3903 } 3904 3905 uart.port.dev = &dev->dev; 3906 3907 for (i = 0; i < nr_ports; i++) { 3908 if (quirk->setup(priv, board, &uart, i)) 3909 break; 3910 3911 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3912 uart.port.iobase, uart.port.irq, uart.port.iotype); 3913 3914 priv->line[i] = serial8250_register_8250_port(&uart); 3915 if (priv->line[i] < 0) { 3916 pci_err(dev, 3917 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3918 uart.port.iobase, uart.port.irq, 3919 uart.port.iotype, priv->line[i]); 3920 break; 3921 } 3922 } 3923 priv->nr = i; 3924 priv->board = board; 3925 return priv; 3926 3927 err_deinit: 3928 if (quirk->exit) 3929 quirk->exit(dev); 3930 err_out: 3931 return priv; 3932 } 3933 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3934 3935 static void pciserial_detach_ports(struct serial_private *priv) 3936 { 3937 struct pci_serial_quirk *quirk; 3938 int i; 3939 3940 for (i = 0; i < priv->nr; i++) 3941 serial8250_unregister_port(priv->line[i]); 3942 3943 /* 3944 * Find the exit quirks. 3945 */ 3946 quirk = find_quirk(priv->dev); 3947 if (quirk->exit) 3948 quirk->exit(priv->dev); 3949 } 3950 3951 void pciserial_remove_ports(struct serial_private *priv) 3952 { 3953 pciserial_detach_ports(priv); 3954 kfree(priv); 3955 } 3956 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3957 3958 void pciserial_suspend_ports(struct serial_private *priv) 3959 { 3960 int i; 3961 3962 for (i = 0; i < priv->nr; i++) 3963 if (priv->line[i] >= 0) 3964 serial8250_suspend_port(priv->line[i]); 3965 3966 /* 3967 * Ensure that every init quirk is properly torn down 3968 */ 3969 if (priv->quirk->exit) 3970 priv->quirk->exit(priv->dev); 3971 } 3972 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3973 3974 void pciserial_resume_ports(struct serial_private *priv) 3975 { 3976 int i; 3977 3978 /* 3979 * Ensure that the board is correctly configured. 3980 */ 3981 if (priv->quirk->init) 3982 priv->quirk->init(priv->dev); 3983 3984 for (i = 0; i < priv->nr; i++) 3985 if (priv->line[i] >= 0) 3986 serial8250_resume_port(priv->line[i]); 3987 } 3988 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3989 3990 /* 3991 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3992 * to the arrangement of serial ports on a PCI card. 3993 */ 3994 static int 3995 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3996 { 3997 struct pci_serial_quirk *quirk; 3998 struct serial_private *priv; 3999 const struct pciserial_board *board; 4000 const struct pci_device_id *exclude; 4001 struct pciserial_board tmp; 4002 int rc; 4003 4004 quirk = find_quirk(dev); 4005 if (quirk->probe) { 4006 rc = quirk->probe(dev); 4007 if (rc) 4008 return rc; 4009 } 4010 4011 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4012 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4013 return -EINVAL; 4014 } 4015 4016 board = &pci_boards[ent->driver_data]; 4017 4018 exclude = pci_match_id(blacklist, dev); 4019 if (exclude) { 4020 if (exclude->driver_data) 4021 pci_warn(dev, "ignoring port, enable %s to handle\n", 4022 (const char *)exclude->driver_data); 4023 return -ENODEV; 4024 } 4025 4026 rc = pcim_enable_device(dev); 4027 pci_save_state(dev); 4028 if (rc) 4029 return rc; 4030 4031 if (ent->driver_data == pbn_default) { 4032 /* 4033 * Use a copy of the pci_board entry for this; 4034 * avoid changing entries in the table. 4035 */ 4036 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4037 board = &tmp; 4038 4039 /* 4040 * We matched one of our class entries. Try to 4041 * determine the parameters of this board. 4042 */ 4043 rc = serial_pci_guess_board(dev, &tmp); 4044 if (rc) 4045 return rc; 4046 } else { 4047 /* 4048 * We matched an explicit entry. If we are able to 4049 * detect this boards settings with our heuristic, 4050 * then we no longer need this entry. 4051 */ 4052 memcpy(&tmp, &pci_boards[pbn_default], 4053 sizeof(struct pciserial_board)); 4054 rc = serial_pci_guess_board(dev, &tmp); 4055 if (rc == 0 && serial_pci_matches(board, &tmp)) 4056 moan_device("Redundant entry in serial pci_table.", 4057 dev); 4058 } 4059 4060 priv = pciserial_init_ports(dev, board); 4061 if (IS_ERR(priv)) 4062 return PTR_ERR(priv); 4063 4064 pci_set_drvdata(dev, priv); 4065 return 0; 4066 } 4067 4068 static void pciserial_remove_one(struct pci_dev *dev) 4069 { 4070 struct serial_private *priv = pci_get_drvdata(dev); 4071 4072 pciserial_remove_ports(priv); 4073 } 4074 4075 #ifdef CONFIG_PM_SLEEP 4076 static int pciserial_suspend_one(struct device *dev) 4077 { 4078 struct serial_private *priv = dev_get_drvdata(dev); 4079 4080 if (priv) 4081 pciserial_suspend_ports(priv); 4082 4083 return 0; 4084 } 4085 4086 static int pciserial_resume_one(struct device *dev) 4087 { 4088 struct pci_dev *pdev = to_pci_dev(dev); 4089 struct serial_private *priv = pci_get_drvdata(pdev); 4090 int err; 4091 4092 if (priv) { 4093 /* 4094 * The device may have been disabled. Re-enable it. 4095 */ 4096 err = pci_enable_device(pdev); 4097 /* FIXME: We cannot simply error out here */ 4098 if (err) 4099 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4100 pciserial_resume_ports(priv); 4101 } 4102 return 0; 4103 } 4104 #endif 4105 4106 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4107 pciserial_resume_one); 4108 4109 static const struct pci_device_id serial_pci_tbl[] = { 4110 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4111 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4112 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4113 pbn_b2_8_921600 }, 4114 /* Advantech also use 0x3618 and 0xf618 */ 4115 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4116 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4117 pbn_b0_4_921600 }, 4118 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4119 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4120 pbn_b0_4_921600 }, 4121 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4122 PCI_SUBVENDOR_ID_CONNECT_TECH, 4123 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4124 pbn_b1_8_1382400 }, 4125 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4126 PCI_SUBVENDOR_ID_CONNECT_TECH, 4127 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4128 pbn_b1_4_1382400 }, 4129 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4130 PCI_SUBVENDOR_ID_CONNECT_TECH, 4131 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4132 pbn_b1_2_1382400 }, 4133 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4134 PCI_SUBVENDOR_ID_CONNECT_TECH, 4135 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4136 pbn_b1_8_1382400 }, 4137 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4138 PCI_SUBVENDOR_ID_CONNECT_TECH, 4139 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4140 pbn_b1_4_1382400 }, 4141 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4142 PCI_SUBVENDOR_ID_CONNECT_TECH, 4143 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4144 pbn_b1_2_1382400 }, 4145 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4146 PCI_SUBVENDOR_ID_CONNECT_TECH, 4147 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4148 pbn_b1_8_921600 }, 4149 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4150 PCI_SUBVENDOR_ID_CONNECT_TECH, 4151 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4152 pbn_b1_8_921600 }, 4153 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4154 PCI_SUBVENDOR_ID_CONNECT_TECH, 4155 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4156 pbn_b1_4_921600 }, 4157 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4158 PCI_SUBVENDOR_ID_CONNECT_TECH, 4159 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4160 pbn_b1_4_921600 }, 4161 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4162 PCI_SUBVENDOR_ID_CONNECT_TECH, 4163 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4164 pbn_b1_2_921600 }, 4165 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4166 PCI_SUBVENDOR_ID_CONNECT_TECH, 4167 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4168 pbn_b1_8_921600 }, 4169 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4170 PCI_SUBVENDOR_ID_CONNECT_TECH, 4171 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4172 pbn_b1_8_921600 }, 4173 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4174 PCI_SUBVENDOR_ID_CONNECT_TECH, 4175 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4176 pbn_b1_4_921600 }, 4177 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4178 PCI_SUBVENDOR_ID_CONNECT_TECH, 4179 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4180 pbn_b1_2_1250000 }, 4181 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4182 PCI_SUBVENDOR_ID_CONNECT_TECH, 4183 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4184 pbn_b0_2_1843200 }, 4185 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4186 PCI_SUBVENDOR_ID_CONNECT_TECH, 4187 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4188 pbn_b0_4_1843200 }, 4189 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4190 PCI_VENDOR_ID_AFAVLAB, 4191 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4192 pbn_b0_4_1152000 }, 4193 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4195 pbn_b2_bt_1_115200 }, 4196 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4198 pbn_b2_bt_2_115200 }, 4199 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4201 pbn_b2_bt_4_115200 }, 4202 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4204 pbn_b2_bt_2_115200 }, 4205 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4207 pbn_b2_bt_4_115200 }, 4208 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4210 pbn_b2_8_115200 }, 4211 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_b2_8_460800 }, 4214 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4216 pbn_b2_8_115200 }, 4217 4218 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4219 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4220 pbn_b2_bt_2_115200 }, 4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4223 pbn_b2_bt_2_921600 }, 4224 /* 4225 * VScom SPCOM800, from sl@s.pl 4226 */ 4227 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4229 pbn_b2_8_921600 }, 4230 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4232 pbn_b2_4_921600 }, 4233 /* Unknown card - subdevice 0x1584 */ 4234 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4235 PCI_VENDOR_ID_PLX, 4236 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4237 pbn_b2_4_115200 }, 4238 /* Unknown card - subdevice 0x1588 */ 4239 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4240 PCI_VENDOR_ID_PLX, 4241 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4242 pbn_b2_8_115200 }, 4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4244 PCI_SUBVENDOR_ID_KEYSPAN, 4245 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4246 pbn_panacom }, 4247 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4249 pbn_panacom4 }, 4250 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4252 pbn_panacom2 }, 4253 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4254 PCI_VENDOR_ID_ESDGMBH, 4255 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4256 pbn_b2_4_115200 }, 4257 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4258 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4259 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4260 pbn_b2_4_460800 }, 4261 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4262 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4263 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4264 pbn_b2_8_460800 }, 4265 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4266 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4267 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4268 pbn_b2_16_460800 }, 4269 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4270 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4271 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4272 pbn_b2_16_460800 }, 4273 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4274 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4275 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4276 pbn_b2_4_460800 }, 4277 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4278 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4279 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4280 pbn_b2_8_460800 }, 4281 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4282 PCI_SUBVENDOR_ID_EXSYS, 4283 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4284 pbn_b2_4_115200 }, 4285 /* 4286 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4287 * (Exoray@isys.ca) 4288 */ 4289 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4290 0x10b5, 0x106a, 0, 0, 4291 pbn_plx_romulus }, 4292 /* 4293 * Quatech cards. These actually have configurable clocks but for 4294 * now we just use the default. 4295 * 4296 * 100 series are RS232, 200 series RS422, 4297 */ 4298 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4300 pbn_b1_4_115200 }, 4301 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_b1_2_115200 }, 4304 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_b2_2_115200 }, 4307 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4309 pbn_b1_2_115200 }, 4310 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4312 pbn_b2_2_115200 }, 4313 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4315 pbn_b1_4_115200 }, 4316 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4318 pbn_b1_8_115200 }, 4319 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4321 pbn_b1_8_115200 }, 4322 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4324 pbn_b1_4_115200 }, 4325 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4327 pbn_b1_2_115200 }, 4328 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4330 pbn_b1_4_115200 }, 4331 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4333 pbn_b1_2_115200 }, 4334 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4336 pbn_b2_4_115200 }, 4337 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4339 pbn_b2_2_115200 }, 4340 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4342 pbn_b2_1_115200 }, 4343 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4345 pbn_b2_4_115200 }, 4346 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4348 pbn_b2_2_115200 }, 4349 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4351 pbn_b2_1_115200 }, 4352 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4354 pbn_b0_8_115200 }, 4355 4356 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4357 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4358 0, 0, 4359 pbn_b0_4_921600 }, 4360 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4361 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4362 0, 0, 4363 pbn_b0_4_1152000 }, 4364 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4366 pbn_b0_bt_2_921600 }, 4367 4368 /* 4369 * The below card is a little controversial since it is the 4370 * subject of a PCI vendor/device ID clash. (See 4371 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4372 * For now just used the hex ID 0x950a. 4373 */ 4374 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4375 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4376 0, 0, pbn_b0_2_115200 }, 4377 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4378 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4379 0, 0, pbn_b0_2_115200 }, 4380 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b0_2_1130000 }, 4383 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4384 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4385 pbn_b0_1_921600 }, 4386 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_b0_4_115200 }, 4389 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b0_bt_2_921600 }, 4392 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b2_8_1152000 }, 4395 4396 /* 4397 * Oxford Semiconductor Inc. Tornado PCI express device range. 4398 */ 4399 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4401 pbn_b0_1_15625000 }, 4402 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4404 pbn_b0_1_15625000 }, 4405 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_oxsemi_1_15625000 }, 4408 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4410 pbn_oxsemi_1_15625000 }, 4411 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4413 pbn_b0_1_15625000 }, 4414 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4416 pbn_b0_1_15625000 }, 4417 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4419 pbn_oxsemi_1_15625000 }, 4420 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4422 pbn_oxsemi_1_15625000 }, 4423 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4425 pbn_b0_1_15625000 }, 4426 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4428 pbn_b0_1_15625000 }, 4429 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4431 pbn_b0_1_15625000 }, 4432 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4434 pbn_b0_1_15625000 }, 4435 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4437 pbn_oxsemi_2_15625000 }, 4438 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4440 pbn_oxsemi_2_15625000 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_oxsemi_4_15625000 }, 4444 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4446 pbn_oxsemi_4_15625000 }, 4447 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_oxsemi_8_15625000 }, 4450 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_oxsemi_8_15625000 }, 4453 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_oxsemi_1_15625000 }, 4456 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4458 pbn_oxsemi_1_15625000 }, 4459 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4461 pbn_oxsemi_1_15625000 }, 4462 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4464 pbn_oxsemi_1_15625000 }, 4465 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4467 pbn_oxsemi_1_15625000 }, 4468 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4470 pbn_oxsemi_1_15625000 }, 4471 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4473 pbn_oxsemi_1_15625000 }, 4474 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4476 pbn_oxsemi_1_15625000 }, 4477 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4479 pbn_oxsemi_1_15625000 }, 4480 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4482 pbn_oxsemi_1_15625000 }, 4483 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4485 pbn_oxsemi_1_15625000 }, 4486 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4488 pbn_oxsemi_1_15625000 }, 4489 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_oxsemi_1_15625000 }, 4492 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_oxsemi_1_15625000 }, 4495 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_oxsemi_1_15625000 }, 4498 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_oxsemi_1_15625000 }, 4501 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_oxsemi_1_15625000 }, 4504 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_oxsemi_1_15625000 }, 4507 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_oxsemi_1_15625000 }, 4510 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_oxsemi_1_15625000 }, 4513 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4515 pbn_oxsemi_1_15625000 }, 4516 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4518 pbn_oxsemi_1_15625000 }, 4519 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4521 pbn_oxsemi_1_15625000 }, 4522 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4524 pbn_oxsemi_1_15625000 }, 4525 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4527 pbn_oxsemi_1_15625000 }, 4528 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4530 pbn_oxsemi_1_15625000 }, 4531 /* 4532 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4533 */ 4534 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4535 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4536 pbn_oxsemi_1_15625000 }, 4537 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4538 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4539 pbn_oxsemi_2_15625000 }, 4540 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4541 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4542 pbn_oxsemi_4_15625000 }, 4543 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4544 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4545 pbn_oxsemi_8_15625000 }, 4546 4547 /* 4548 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4549 */ 4550 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4551 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4552 pbn_oxsemi_2_15625000 }, 4553 /* 4554 * EndRun Technologies. PCI express device range. 4555 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4556 */ 4557 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4559 pbn_oxsemi_2_15625000 }, 4560 4561 /* 4562 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4563 * from skokodyn@yahoo.com 4564 */ 4565 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4566 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4567 pbn_sbsxrsio }, 4568 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4569 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4570 pbn_sbsxrsio }, 4571 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4572 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4573 pbn_sbsxrsio }, 4574 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4575 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4576 pbn_sbsxrsio }, 4577 4578 /* 4579 * Digitan DS560-558, from jimd@esoft.com 4580 */ 4581 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4583 pbn_b1_1_115200 }, 4584 4585 /* 4586 * Titan Electronic cards 4587 * The 400L and 800L have a custom setup quirk. 4588 */ 4589 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_b0_1_921600 }, 4592 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_b0_2_921600 }, 4595 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4597 pbn_b0_4_921600 }, 4598 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4600 pbn_b0_4_921600 }, 4601 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4603 pbn_b1_1_921600 }, 4604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4606 pbn_b1_bt_2_921600 }, 4607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4609 pbn_b0_bt_4_921600 }, 4610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4612 pbn_b0_bt_8_921600 }, 4613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4615 pbn_b4_bt_2_921600 }, 4616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4618 pbn_b4_bt_4_921600 }, 4619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4621 pbn_b4_bt_8_921600 }, 4622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4624 pbn_b0_4_921600 }, 4625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4627 pbn_b0_4_921600 }, 4628 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4630 pbn_b0_4_921600 }, 4631 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4633 pbn_titan_1_4000000 }, 4634 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4636 pbn_titan_2_4000000 }, 4637 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4639 pbn_titan_4_4000000 }, 4640 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4642 pbn_titan_8_4000000 }, 4643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_titan_2_4000000 }, 4646 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_titan_2_4000000 }, 4649 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_b0_bt_2_921600 }, 4652 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b0_4_921600 }, 4655 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_b0_4_921600 }, 4658 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_b0_4_921600 }, 4661 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_b0_4_921600 }, 4664 4665 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4667 pbn_b2_1_460800 }, 4668 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4669 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4670 pbn_b2_1_460800 }, 4671 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4672 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4673 pbn_b2_1_460800 }, 4674 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4675 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4676 pbn_b2_bt_2_921600 }, 4677 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4678 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4679 pbn_b2_bt_2_921600 }, 4680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4682 pbn_b2_bt_2_921600 }, 4683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b2_bt_4_921600 }, 4686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4687 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4688 pbn_b2_bt_4_921600 }, 4689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4691 pbn_b2_bt_4_921600 }, 4692 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4694 pbn_b0_1_921600 }, 4695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4697 pbn_b0_1_921600 }, 4698 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4700 pbn_b0_1_921600 }, 4701 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4703 pbn_b0_bt_2_921600 }, 4704 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4706 pbn_b0_bt_2_921600 }, 4707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4709 pbn_b0_bt_2_921600 }, 4710 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4712 pbn_b0_bt_4_921600 }, 4713 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4715 pbn_b0_bt_4_921600 }, 4716 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4718 pbn_b0_bt_4_921600 }, 4719 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_b0_bt_8_921600 }, 4722 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b0_bt_8_921600 }, 4725 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b0_bt_8_921600 }, 4728 4729 /* 4730 * Computone devices submitted by Doug McNash dmcnash@computone.com 4731 */ 4732 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4733 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4734 0, 0, pbn_computone_4 }, 4735 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4736 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4737 0, 0, pbn_computone_8 }, 4738 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4739 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4740 0, 0, pbn_computone_6 }, 4741 4742 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4744 pbn_oxsemi }, 4745 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4746 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4747 pbn_b0_bt_1_921600 }, 4748 4749 /* 4750 * Sunix PCI serial boards 4751 */ 4752 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4753 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4754 pbn_sunix_pci_1s }, 4755 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4756 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4757 pbn_sunix_pci_2s }, 4758 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4759 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4760 pbn_sunix_pci_4s }, 4761 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4762 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4763 pbn_sunix_pci_4s }, 4764 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4765 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4766 pbn_sunix_pci_8s }, 4767 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4768 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4769 pbn_sunix_pci_8s }, 4770 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4771 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4772 pbn_sunix_pci_16s }, 4773 4774 /* 4775 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4776 */ 4777 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b0_bt_8_115200 }, 4780 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_8_115200 }, 4783 4784 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4786 pbn_b0_bt_2_115200 }, 4787 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4789 pbn_b0_bt_2_115200 }, 4790 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4792 pbn_b0_bt_2_115200 }, 4793 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4795 pbn_b0_bt_2_115200 }, 4796 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_b0_bt_2_115200 }, 4799 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4801 pbn_b0_bt_4_460800 }, 4802 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4804 pbn_b0_bt_4_460800 }, 4805 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4807 pbn_b0_bt_2_460800 }, 4808 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4810 pbn_b0_bt_2_460800 }, 4811 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4813 pbn_b0_bt_2_460800 }, 4814 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4815 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4816 pbn_b0_bt_1_115200 }, 4817 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4819 pbn_b0_bt_1_460800 }, 4820 4821 /* 4822 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4823 * Cards are identified by their subsystem vendor IDs, which 4824 * (in hex) match the model number. 4825 * 4826 * Note that JC140x are RS422/485 cards which require ox950 4827 * ACR = 0x10, and as such are not currently fully supported. 4828 */ 4829 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4830 0x1204, 0x0004, 0, 0, 4831 pbn_b0_4_921600 }, 4832 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4833 0x1208, 0x0004, 0, 0, 4834 pbn_b0_4_921600 }, 4835 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4836 0x1402, 0x0002, 0, 0, 4837 pbn_b0_2_921600 }, */ 4838 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4839 0x1404, 0x0004, 0, 0, 4840 pbn_b0_4_921600 }, */ 4841 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4842 0x1208, 0x0004, 0, 0, 4843 pbn_b0_4_921600 }, 4844 4845 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4846 0x1204, 0x0004, 0, 0, 4847 pbn_b0_4_921600 }, 4848 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4849 0x1208, 0x0004, 0, 0, 4850 pbn_b0_4_921600 }, 4851 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4852 0x1208, 0x0004, 0, 0, 4853 pbn_b0_4_921600 }, 4854 /* 4855 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4856 */ 4857 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4859 pbn_b1_1_1382400 }, 4860 4861 /* 4862 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4863 */ 4864 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4866 pbn_b1_1_1382400 }, 4867 4868 /* 4869 * RAStel 2 port modem, gerg@moreton.com.au 4870 */ 4871 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4873 pbn_b2_bt_2_115200 }, 4874 4875 /* 4876 * EKF addition for i960 Boards form EKF with serial port 4877 */ 4878 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4879 0xE4BF, PCI_ANY_ID, 0, 0, 4880 pbn_intel_i960 }, 4881 4882 /* 4883 * Xircom Cardbus/Ethernet combos 4884 */ 4885 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4887 pbn_b0_1_115200 }, 4888 /* 4889 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4890 */ 4891 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4893 pbn_b0_1_115200 }, 4894 4895 /* 4896 * Untested PCI modems, sent in from various folks... 4897 */ 4898 4899 /* 4900 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4901 */ 4902 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4903 0x1048, 0x1500, 0, 0, 4904 pbn_b1_1_115200 }, 4905 4906 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4907 0xFF00, 0, 0, 0, 4908 pbn_sgi_ioc3 }, 4909 4910 /* 4911 * HP Diva card 4912 */ 4913 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4914 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4915 pbn_b1_1_115200 }, 4916 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4918 pbn_b0_5_115200 }, 4919 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4921 pbn_b2_1_115200 }, 4922 /* HPE PCI serial device */ 4923 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4925 pbn_b1_1_115200 }, 4926 4927 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4929 pbn_b3_2_115200 }, 4930 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4932 pbn_b3_4_115200 }, 4933 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4935 pbn_b3_8_115200 }, 4936 /* 4937 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4938 */ 4939 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4941 pbn_b0_1_115200 }, 4942 /* 4943 * ITE 4944 */ 4945 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4946 PCI_ANY_ID, PCI_ANY_ID, 4947 0, 0, 4948 pbn_b1_bt_1_115200 }, 4949 4950 /* 4951 * IntaShield IS-200 4952 */ 4953 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4955 pbn_b2_2_115200 }, 4956 /* 4957 * IntaShield IS-400 4958 */ 4959 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4961 pbn_b2_4_115200 }, 4962 /* Brainboxes Devices */ 4963 /* 4964 * Brainboxes UC-101 4965 */ 4966 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4967 PCI_ANY_ID, PCI_ANY_ID, 4968 0, 0, 4969 pbn_b2_2_115200 }, 4970 /* 4971 * Brainboxes UC-235/246 4972 */ 4973 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4974 PCI_ANY_ID, PCI_ANY_ID, 4975 0, 0, 4976 pbn_b2_1_115200 }, 4977 /* 4978 * Brainboxes UC-257 4979 */ 4980 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4981 PCI_ANY_ID, PCI_ANY_ID, 4982 0, 0, 4983 pbn_b2_2_115200 }, 4984 /* 4985 * Brainboxes UC-260/271/701/756 4986 */ 4987 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4988 PCI_ANY_ID, PCI_ANY_ID, 4989 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4990 pbn_b2_4_115200 }, 4991 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4992 PCI_ANY_ID, PCI_ANY_ID, 4993 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4994 pbn_b2_4_115200 }, 4995 /* 4996 * Brainboxes UC-268 4997 */ 4998 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4999 PCI_ANY_ID, PCI_ANY_ID, 5000 0, 0, 5001 pbn_b2_4_115200 }, 5002 /* 5003 * Brainboxes UC-275/279 5004 */ 5005 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 5006 PCI_ANY_ID, PCI_ANY_ID, 5007 0, 0, 5008 pbn_b2_8_115200 }, 5009 /* 5010 * Brainboxes UC-302 5011 */ 5012 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 5013 PCI_ANY_ID, PCI_ANY_ID, 5014 0, 0, 5015 pbn_b2_2_115200 }, 5016 /* 5017 * Brainboxes UC-310 5018 */ 5019 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 5020 PCI_ANY_ID, PCI_ANY_ID, 5021 0, 0, 5022 pbn_b2_2_115200 }, 5023 /* 5024 * Brainboxes UC-313 5025 */ 5026 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5027 PCI_ANY_ID, PCI_ANY_ID, 5028 0, 0, 5029 pbn_b2_2_115200 }, 5030 /* 5031 * Brainboxes UC-320/324 5032 */ 5033 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5034 PCI_ANY_ID, PCI_ANY_ID, 5035 0, 0, 5036 pbn_b2_1_115200 }, 5037 /* 5038 * Brainboxes UC-346 5039 */ 5040 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5041 PCI_ANY_ID, PCI_ANY_ID, 5042 0, 0, 5043 pbn_b2_4_115200 }, 5044 /* 5045 * Brainboxes UC-357 5046 */ 5047 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5048 PCI_ANY_ID, PCI_ANY_ID, 5049 0, 0, 5050 pbn_b2_2_115200 }, 5051 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5052 PCI_ANY_ID, PCI_ANY_ID, 5053 0, 0, 5054 pbn_b2_2_115200 }, 5055 /* 5056 * Brainboxes UC-368 5057 */ 5058 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5059 PCI_ANY_ID, PCI_ANY_ID, 5060 0, 0, 5061 pbn_b2_4_115200 }, 5062 /* 5063 * Brainboxes UC-420/431 5064 */ 5065 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5066 PCI_ANY_ID, PCI_ANY_ID, 5067 0, 0, 5068 pbn_b2_4_115200 }, 5069 /* 5070 * Brainboxes PX-101 5071 */ 5072 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5073 PCI_ANY_ID, PCI_ANY_ID, 5074 0, 0, 5075 pbn_b0_2_115200 }, 5076 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5077 PCI_ANY_ID, PCI_ANY_ID, 5078 0, 0, 5079 pbn_oxsemi_2_15625000 }, 5080 /* 5081 * Brainboxes PX-235/246 5082 */ 5083 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5084 PCI_ANY_ID, PCI_ANY_ID, 5085 0, 0, 5086 pbn_b0_1_115200 }, 5087 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5088 PCI_ANY_ID, PCI_ANY_ID, 5089 0, 0, 5090 pbn_oxsemi_1_15625000 }, 5091 /* 5092 * Brainboxes PX-203/PX-257 5093 */ 5094 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5095 PCI_ANY_ID, PCI_ANY_ID, 5096 0, 0, 5097 pbn_b0_2_115200 }, 5098 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5099 PCI_ANY_ID, PCI_ANY_ID, 5100 0, 0, 5101 pbn_oxsemi_4_15625000 }, 5102 /* 5103 * Brainboxes PX-260/PX-701 5104 */ 5105 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5106 PCI_ANY_ID, PCI_ANY_ID, 5107 0, 0, 5108 pbn_oxsemi_4_15625000 }, 5109 /* 5110 * Brainboxes PX-310 5111 */ 5112 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5113 PCI_ANY_ID, PCI_ANY_ID, 5114 0, 0, 5115 pbn_oxsemi_2_15625000 }, 5116 /* 5117 * Brainboxes PX-313 5118 */ 5119 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5120 PCI_ANY_ID, PCI_ANY_ID, 5121 0, 0, 5122 pbn_oxsemi_2_15625000 }, 5123 /* 5124 * Brainboxes PX-320/324/PX-376/PX-387 5125 */ 5126 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5127 PCI_ANY_ID, PCI_ANY_ID, 5128 0, 0, 5129 pbn_oxsemi_1_15625000 }, 5130 /* 5131 * Brainboxes PX-335/346 5132 */ 5133 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5134 PCI_ANY_ID, PCI_ANY_ID, 5135 0, 0, 5136 pbn_oxsemi_4_15625000 }, 5137 /* 5138 * Brainboxes PX-368 5139 */ 5140 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5141 PCI_ANY_ID, PCI_ANY_ID, 5142 0, 0, 5143 pbn_oxsemi_4_15625000 }, 5144 /* 5145 * Brainboxes PX-420 5146 */ 5147 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5148 PCI_ANY_ID, PCI_ANY_ID, 5149 0, 0, 5150 pbn_b0_4_115200 }, 5151 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5152 PCI_ANY_ID, PCI_ANY_ID, 5153 0, 0, 5154 pbn_oxsemi_4_15625000 }, 5155 /* 5156 * Brainboxes PX-803 5157 */ 5158 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5159 PCI_ANY_ID, PCI_ANY_ID, 5160 0, 0, 5161 pbn_b0_1_115200 }, 5162 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5163 PCI_ANY_ID, PCI_ANY_ID, 5164 0, 0, 5165 pbn_oxsemi_1_15625000 }, 5166 /* 5167 * Brainboxes PX-846 5168 */ 5169 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5170 PCI_ANY_ID, PCI_ANY_ID, 5171 0, 0, 5172 pbn_b0_1_115200 }, 5173 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5174 PCI_ANY_ID, PCI_ANY_ID, 5175 0, 0, 5176 pbn_oxsemi_1_15625000 }, 5177 5178 /* 5179 * Perle PCI-RAS cards 5180 */ 5181 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5182 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5183 0, 0, pbn_b2_4_921600 }, 5184 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5185 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5186 0, 0, pbn_b2_8_921600 }, 5187 5188 /* 5189 * Mainpine series cards: Fairly standard layout but fools 5190 * parts of the autodetect in some cases and uses otherwise 5191 * unmatched communications subclasses in the PCI Express case 5192 */ 5193 5194 { /* RockForceDUO */ 5195 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5196 PCI_VENDOR_ID_MAINPINE, 0x0200, 5197 0, 0, pbn_b0_2_115200 }, 5198 { /* RockForceQUATRO */ 5199 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5200 PCI_VENDOR_ID_MAINPINE, 0x0300, 5201 0, 0, pbn_b0_4_115200 }, 5202 { /* RockForceDUO+ */ 5203 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5204 PCI_VENDOR_ID_MAINPINE, 0x0400, 5205 0, 0, pbn_b0_2_115200 }, 5206 { /* RockForceQUATRO+ */ 5207 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5208 PCI_VENDOR_ID_MAINPINE, 0x0500, 5209 0, 0, pbn_b0_4_115200 }, 5210 { /* RockForce+ */ 5211 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5212 PCI_VENDOR_ID_MAINPINE, 0x0600, 5213 0, 0, pbn_b0_2_115200 }, 5214 { /* RockForce+ */ 5215 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5216 PCI_VENDOR_ID_MAINPINE, 0x0700, 5217 0, 0, pbn_b0_4_115200 }, 5218 { /* RockForceOCTO+ */ 5219 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5220 PCI_VENDOR_ID_MAINPINE, 0x0800, 5221 0, 0, pbn_b0_8_115200 }, 5222 { /* RockForceDUO+ */ 5223 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5224 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5225 0, 0, pbn_b0_2_115200 }, 5226 { /* RockForceQUARTRO+ */ 5227 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5228 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5229 0, 0, pbn_b0_4_115200 }, 5230 { /* RockForceOCTO+ */ 5231 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5232 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5233 0, 0, pbn_b0_8_115200 }, 5234 { /* RockForceD1 */ 5235 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5236 PCI_VENDOR_ID_MAINPINE, 0x2000, 5237 0, 0, pbn_b0_1_115200 }, 5238 { /* RockForceF1 */ 5239 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5240 PCI_VENDOR_ID_MAINPINE, 0x2100, 5241 0, 0, pbn_b0_1_115200 }, 5242 { /* RockForceD2 */ 5243 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5244 PCI_VENDOR_ID_MAINPINE, 0x2200, 5245 0, 0, pbn_b0_2_115200 }, 5246 { /* RockForceF2 */ 5247 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5248 PCI_VENDOR_ID_MAINPINE, 0x2300, 5249 0, 0, pbn_b0_2_115200 }, 5250 { /* RockForceD4 */ 5251 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5252 PCI_VENDOR_ID_MAINPINE, 0x2400, 5253 0, 0, pbn_b0_4_115200 }, 5254 { /* RockForceF4 */ 5255 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5256 PCI_VENDOR_ID_MAINPINE, 0x2500, 5257 0, 0, pbn_b0_4_115200 }, 5258 { /* RockForceD8 */ 5259 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5260 PCI_VENDOR_ID_MAINPINE, 0x2600, 5261 0, 0, pbn_b0_8_115200 }, 5262 { /* RockForceF8 */ 5263 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5264 PCI_VENDOR_ID_MAINPINE, 0x2700, 5265 0, 0, pbn_b0_8_115200 }, 5266 { /* IQ Express D1 */ 5267 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5268 PCI_VENDOR_ID_MAINPINE, 0x3000, 5269 0, 0, pbn_b0_1_115200 }, 5270 { /* IQ Express F1 */ 5271 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5272 PCI_VENDOR_ID_MAINPINE, 0x3100, 5273 0, 0, pbn_b0_1_115200 }, 5274 { /* IQ Express D2 */ 5275 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5276 PCI_VENDOR_ID_MAINPINE, 0x3200, 5277 0, 0, pbn_b0_2_115200 }, 5278 { /* IQ Express F2 */ 5279 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5280 PCI_VENDOR_ID_MAINPINE, 0x3300, 5281 0, 0, pbn_b0_2_115200 }, 5282 { /* IQ Express D4 */ 5283 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5284 PCI_VENDOR_ID_MAINPINE, 0x3400, 5285 0, 0, pbn_b0_4_115200 }, 5286 { /* IQ Express F4 */ 5287 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5288 PCI_VENDOR_ID_MAINPINE, 0x3500, 5289 0, 0, pbn_b0_4_115200 }, 5290 { /* IQ Express D8 */ 5291 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5292 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5293 0, 0, pbn_b0_8_115200 }, 5294 { /* IQ Express F8 */ 5295 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5296 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5297 0, 0, pbn_b0_8_115200 }, 5298 5299 5300 /* 5301 * PA Semi PA6T-1682M on-chip UART 5302 */ 5303 { PCI_VENDOR_ID_PASEMI, 0xa004, 5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5305 pbn_pasemi_1682M }, 5306 5307 /* 5308 * National Instruments 5309 */ 5310 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5311 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5312 pbn_b1_16_115200 }, 5313 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5315 pbn_b1_8_115200 }, 5316 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5317 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5318 pbn_b1_bt_4_115200 }, 5319 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5321 pbn_b1_bt_2_115200 }, 5322 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5323 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5324 pbn_b1_bt_4_115200 }, 5325 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5327 pbn_b1_bt_2_115200 }, 5328 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5329 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5330 pbn_b1_16_115200 }, 5331 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5333 pbn_b1_8_115200 }, 5334 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5336 pbn_b1_bt_4_115200 }, 5337 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5339 pbn_b1_bt_2_115200 }, 5340 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5341 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5342 pbn_b1_bt_4_115200 }, 5343 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5345 pbn_b1_bt_2_115200 }, 5346 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5348 pbn_ni8430_2 }, 5349 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5351 pbn_ni8430_2 }, 5352 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5354 pbn_ni8430_4 }, 5355 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5357 pbn_ni8430_4 }, 5358 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5360 pbn_ni8430_8 }, 5361 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5363 pbn_ni8430_8 }, 5364 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5366 pbn_ni8430_16 }, 5367 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5369 pbn_ni8430_16 }, 5370 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5372 pbn_ni8430_2 }, 5373 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5375 pbn_ni8430_2 }, 5376 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5378 pbn_ni8430_4 }, 5379 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5381 pbn_ni8430_4 }, 5382 5383 /* 5384 * MOXA 5385 */ 5386 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5388 pbn_moxa8250_2p }, 5389 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5391 pbn_moxa8250_2p }, 5392 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5394 pbn_moxa8250_4p }, 5395 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5397 pbn_moxa8250_4p }, 5398 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5400 pbn_moxa8250_8p }, 5401 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5403 pbn_moxa8250_8p }, 5404 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5406 pbn_moxa8250_8p }, 5407 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5409 pbn_moxa8250_8p }, 5410 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5412 pbn_moxa8250_2p }, 5413 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5415 pbn_moxa8250_4p }, 5416 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5418 pbn_moxa8250_8p }, 5419 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5421 pbn_moxa8250_8p }, 5422 5423 /* 5424 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5425 */ 5426 { PCI_VENDOR_ID_ADDIDATA, 5427 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5428 PCI_ANY_ID, 5429 PCI_ANY_ID, 5430 0, 5431 0, 5432 pbn_b0_4_115200 }, 5433 5434 { PCI_VENDOR_ID_ADDIDATA, 5435 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5436 PCI_ANY_ID, 5437 PCI_ANY_ID, 5438 0, 5439 0, 5440 pbn_b0_2_115200 }, 5441 5442 { PCI_VENDOR_ID_ADDIDATA, 5443 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5444 PCI_ANY_ID, 5445 PCI_ANY_ID, 5446 0, 5447 0, 5448 pbn_b0_1_115200 }, 5449 5450 { PCI_VENDOR_ID_AMCC, 5451 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5452 PCI_ANY_ID, 5453 PCI_ANY_ID, 5454 0, 5455 0, 5456 pbn_b1_8_115200 }, 5457 5458 { PCI_VENDOR_ID_ADDIDATA, 5459 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5460 PCI_ANY_ID, 5461 PCI_ANY_ID, 5462 0, 5463 0, 5464 pbn_b0_4_115200 }, 5465 5466 { PCI_VENDOR_ID_ADDIDATA, 5467 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5468 PCI_ANY_ID, 5469 PCI_ANY_ID, 5470 0, 5471 0, 5472 pbn_b0_2_115200 }, 5473 5474 { PCI_VENDOR_ID_ADDIDATA, 5475 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5476 PCI_ANY_ID, 5477 PCI_ANY_ID, 5478 0, 5479 0, 5480 pbn_b0_1_115200 }, 5481 5482 { PCI_VENDOR_ID_ADDIDATA, 5483 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5484 PCI_ANY_ID, 5485 PCI_ANY_ID, 5486 0, 5487 0, 5488 pbn_b0_4_115200 }, 5489 5490 { PCI_VENDOR_ID_ADDIDATA, 5491 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5492 PCI_ANY_ID, 5493 PCI_ANY_ID, 5494 0, 5495 0, 5496 pbn_b0_2_115200 }, 5497 5498 { PCI_VENDOR_ID_ADDIDATA, 5499 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5500 PCI_ANY_ID, 5501 PCI_ANY_ID, 5502 0, 5503 0, 5504 pbn_b0_1_115200 }, 5505 5506 { PCI_VENDOR_ID_ADDIDATA, 5507 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5508 PCI_ANY_ID, 5509 PCI_ANY_ID, 5510 0, 5511 0, 5512 pbn_b0_8_115200 }, 5513 5514 { PCI_VENDOR_ID_ADDIDATA, 5515 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5516 PCI_ANY_ID, 5517 PCI_ANY_ID, 5518 0, 5519 0, 5520 pbn_ADDIDATA_PCIe_4_3906250 }, 5521 5522 { PCI_VENDOR_ID_ADDIDATA, 5523 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5524 PCI_ANY_ID, 5525 PCI_ANY_ID, 5526 0, 5527 0, 5528 pbn_ADDIDATA_PCIe_2_3906250 }, 5529 5530 { PCI_VENDOR_ID_ADDIDATA, 5531 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5532 PCI_ANY_ID, 5533 PCI_ANY_ID, 5534 0, 5535 0, 5536 pbn_ADDIDATA_PCIe_1_3906250 }, 5537 5538 { PCI_VENDOR_ID_ADDIDATA, 5539 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5540 PCI_ANY_ID, 5541 PCI_ANY_ID, 5542 0, 5543 0, 5544 pbn_ADDIDATA_PCIe_8_3906250 }, 5545 5546 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5547 PCI_VENDOR_ID_IBM, 0x0299, 5548 0, 0, pbn_b0_bt_2_115200 }, 5549 5550 /* 5551 * other NetMos 9835 devices are most likely handled by the 5552 * parport_serial driver, check drivers/parport/parport_serial.c 5553 * before adding them here. 5554 */ 5555 5556 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5557 0xA000, 0x1000, 5558 0, 0, pbn_b0_1_115200 }, 5559 5560 /* the 9901 is a rebranded 9912 */ 5561 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5562 0xA000, 0x1000, 5563 0, 0, pbn_b0_1_115200 }, 5564 5565 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5566 0xA000, 0x1000, 5567 0, 0, pbn_b0_1_115200 }, 5568 5569 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5570 0xA000, 0x1000, 5571 0, 0, pbn_b0_1_115200 }, 5572 5573 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5574 0xA000, 0x1000, 5575 0, 0, pbn_b0_1_115200 }, 5576 5577 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5578 0xA000, 0x3002, 5579 0, 0, pbn_NETMOS9900_2s_115200 }, 5580 5581 /* 5582 * Best Connectivity and Rosewill PCI Multi I/O cards 5583 */ 5584 5585 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5586 0xA000, 0x1000, 5587 0, 0, pbn_b0_1_115200 }, 5588 5589 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5590 0xA000, 0x3002, 5591 0, 0, pbn_b0_bt_2_115200 }, 5592 5593 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5594 0xA000, 0x3004, 5595 0, 0, pbn_b0_bt_4_115200 }, 5596 /* Intel CE4100 */ 5597 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5599 pbn_ce4100_1_115200 }, 5600 5601 /* 5602 * Cronyx Omega PCI 5603 */ 5604 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5605 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5606 pbn_omegapci }, 5607 5608 /* 5609 * Broadcom TruManage 5610 */ 5611 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5613 pbn_brcm_trumanage }, 5614 5615 /* 5616 * AgeStar as-prs2-009 5617 */ 5618 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5619 PCI_ANY_ID, PCI_ANY_ID, 5620 0, 0, pbn_b0_bt_2_115200 }, 5621 5622 /* 5623 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5624 * so not listed here. 5625 */ 5626 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5627 PCI_ANY_ID, PCI_ANY_ID, 5628 0, 0, pbn_b0_bt_4_115200 }, 5629 5630 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5631 PCI_ANY_ID, PCI_ANY_ID, 5632 0, 0, pbn_b0_bt_2_115200 }, 5633 5634 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5635 PCI_ANY_ID, PCI_ANY_ID, 5636 0, 0, pbn_b0_bt_4_115200 }, 5637 5638 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5639 PCI_ANY_ID, PCI_ANY_ID, 5640 0, 0, pbn_wch382_2 }, 5641 5642 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5643 PCI_ANY_ID, PCI_ANY_ID, 5644 0, 0, pbn_wch384_4 }, 5645 5646 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5647 PCI_ANY_ID, PCI_ANY_ID, 5648 0, 0, pbn_wch384_8 }, 5649 /* 5650 * Realtek RealManage 5651 */ 5652 { PCI_VENDOR_ID_REALTEK, 0x816a, 5653 PCI_ANY_ID, PCI_ANY_ID, 5654 0, 0, pbn_b0_1_115200 }, 5655 5656 { PCI_VENDOR_ID_REALTEK, 0x816b, 5657 PCI_ANY_ID, PCI_ANY_ID, 5658 0, 0, pbn_b0_1_115200 }, 5659 5660 /* Fintek PCI serial cards */ 5661 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5662 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5663 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5664 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5665 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5666 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5667 5668 /* MKS Tenta SCOM-080x serial cards */ 5669 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5670 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5671 5672 /* Amazon PCI serial device */ 5673 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5674 5675 /* 5676 * These entries match devices with class COMMUNICATION_SERIAL, 5677 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5678 */ 5679 { PCI_ANY_ID, PCI_ANY_ID, 5680 PCI_ANY_ID, PCI_ANY_ID, 5681 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5682 0xffff00, pbn_default }, 5683 { PCI_ANY_ID, PCI_ANY_ID, 5684 PCI_ANY_ID, PCI_ANY_ID, 5685 PCI_CLASS_COMMUNICATION_MODEM << 8, 5686 0xffff00, pbn_default }, 5687 { PCI_ANY_ID, PCI_ANY_ID, 5688 PCI_ANY_ID, PCI_ANY_ID, 5689 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5690 0xffff00, pbn_default }, 5691 { 0, } 5692 }; 5693 5694 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5695 pci_channel_state_t state) 5696 { 5697 struct serial_private *priv = pci_get_drvdata(dev); 5698 5699 if (state == pci_channel_io_perm_failure) 5700 return PCI_ERS_RESULT_DISCONNECT; 5701 5702 if (priv) 5703 pciserial_detach_ports(priv); 5704 5705 pci_disable_device(dev); 5706 5707 return PCI_ERS_RESULT_NEED_RESET; 5708 } 5709 5710 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5711 { 5712 int rc; 5713 5714 rc = pci_enable_device(dev); 5715 5716 if (rc) 5717 return PCI_ERS_RESULT_DISCONNECT; 5718 5719 pci_restore_state(dev); 5720 pci_save_state(dev); 5721 5722 return PCI_ERS_RESULT_RECOVERED; 5723 } 5724 5725 static void serial8250_io_resume(struct pci_dev *dev) 5726 { 5727 struct serial_private *priv = pci_get_drvdata(dev); 5728 struct serial_private *new; 5729 5730 if (!priv) 5731 return; 5732 5733 new = pciserial_init_ports(dev, priv->board); 5734 if (!IS_ERR(new)) { 5735 pci_set_drvdata(dev, new); 5736 kfree(priv); 5737 } 5738 } 5739 5740 static const struct pci_error_handlers serial8250_err_handler = { 5741 .error_detected = serial8250_io_error_detected, 5742 .slot_reset = serial8250_io_slot_reset, 5743 .resume = serial8250_io_resume, 5744 }; 5745 5746 static struct pci_driver serial_pci_driver = { 5747 .name = "serial", 5748 .probe = pciserial_init_one, 5749 .remove = pciserial_remove_one, 5750 .driver = { 5751 .pm = &pciserial_pm_ops, 5752 }, 5753 .id_table = serial_pci_tbl, 5754 .err_handler = &serial8250_err_handler, 5755 }; 5756 5757 module_pci_driver(serial_pci_driver); 5758 5759 MODULE_LICENSE("GPL"); 5760 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5761 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5762