1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include <linux/dmaengine.h> 29 #include <linux/platform_data/dma-dw.h> 30 31 #include "8250.h" 32 33 /* 34 * init function returns: 35 * > 0 - number of ports 36 * = 0 - use board->num_ports 37 * < 0 - error 38 */ 39 struct pci_serial_quirk { 40 u32 vendor; 41 u32 device; 42 u32 subvendor; 43 u32 subdevice; 44 int (*probe)(struct pci_dev *dev); 45 int (*init)(struct pci_dev *dev); 46 int (*setup)(struct serial_private *, 47 const struct pciserial_board *, 48 struct uart_8250_port *, int); 49 void (*exit)(struct pci_dev *dev); 50 }; 51 52 #define PCI_NUM_BAR_RESOURCES 6 53 54 struct serial_private { 55 struct pci_dev *dev; 56 unsigned int nr; 57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 58 struct pci_serial_quirk *quirk; 59 int line[0]; 60 }; 61 62 static int pci_default_setup(struct serial_private*, 63 const struct pciserial_board*, struct uart_8250_port *, int); 64 65 static void moan_device(const char *str, struct pci_dev *dev) 66 { 67 dev_err(&dev->dev, 68 "%s: %s\n" 69 "Please send the output of lspci -vv, this\n" 70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 71 "manufacturer and name of serial board or\n" 72 "modem board to rmk+serial@arm.linux.org.uk.\n", 73 pci_name(dev), str, dev->vendor, dev->device, 74 dev->subsystem_vendor, dev->subsystem_device); 75 } 76 77 static int 78 setup_port(struct serial_private *priv, struct uart_8250_port *port, 79 int bar, int offset, int regshift) 80 { 81 struct pci_dev *dev = priv->dev; 82 83 if (bar >= PCI_NUM_BAR_RESOURCES) 84 return -EINVAL; 85 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 87 if (!priv->remapped_bar[bar]) 88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar); 89 if (!priv->remapped_bar[bar]) 90 return -ENOMEM; 91 92 port->port.iotype = UPIO_MEM; 93 port->port.iobase = 0; 94 port->port.mapbase = pci_resource_start(dev, bar) + offset; 95 port->port.membase = priv->remapped_bar[bar] + offset; 96 port->port.regshift = regshift; 97 } else { 98 port->port.iotype = UPIO_PORT; 99 port->port.iobase = pci_resource_start(dev, bar) + offset; 100 port->port.mapbase = 0; 101 port->port.membase = NULL; 102 port->port.regshift = 0; 103 } 104 return 0; 105 } 106 107 /* 108 * ADDI-DATA GmbH communication cards <info@addi-data.com> 109 */ 110 static int addidata_apci7800_setup(struct serial_private *priv, 111 const struct pciserial_board *board, 112 struct uart_8250_port *port, int idx) 113 { 114 unsigned int bar = 0, offset = board->first_offset; 115 bar = FL_GET_BASE(board->flags); 116 117 if (idx < 2) { 118 offset += idx * board->uart_offset; 119 } else if ((idx >= 2) && (idx < 4)) { 120 bar += 1; 121 offset += ((idx - 2) * board->uart_offset); 122 } else if ((idx >= 4) && (idx < 6)) { 123 bar += 2; 124 offset += ((idx - 4) * board->uart_offset); 125 } else if (idx >= 6) { 126 bar += 3; 127 offset += ((idx - 6) * board->uart_offset); 128 } 129 130 return setup_port(priv, port, bar, offset, board->reg_shift); 131 } 132 133 /* 134 * AFAVLAB uses a different mixture of BARs and offsets 135 * Not that ugly ;) -- HW 136 */ 137 static int 138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 139 struct uart_8250_port *port, int idx) 140 { 141 unsigned int bar, offset = board->first_offset; 142 143 bar = FL_GET_BASE(board->flags); 144 if (idx < 4) 145 bar += idx; 146 else { 147 bar = 4; 148 offset += (idx - 4) * board->uart_offset; 149 } 150 151 return setup_port(priv, port, bar, offset, board->reg_shift); 152 } 153 154 /* 155 * HP's Remote Management Console. The Diva chip came in several 156 * different versions. N-class, L2000 and A500 have two Diva chips, each 157 * with 3 UARTs (the third UART on the second chip is unused). Superdome 158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 159 * one Diva chip, but it has been expanded to 5 UARTs. 160 */ 161 static int pci_hp_diva_init(struct pci_dev *dev) 162 { 163 int rc = 0; 164 165 switch (dev->subsystem_device) { 166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 169 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 170 rc = 3; 171 break; 172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 173 rc = 2; 174 break; 175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 176 rc = 4; 177 break; 178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 180 rc = 1; 181 break; 182 } 183 184 return rc; 185 } 186 187 /* 188 * HP's Diva chip puts the 4th/5th serial port further out, and 189 * some serial ports are supposed to be hidden on certain models. 190 */ 191 static int 192 pci_hp_diva_setup(struct serial_private *priv, 193 const struct pciserial_board *board, 194 struct uart_8250_port *port, int idx) 195 { 196 unsigned int offset = board->first_offset; 197 unsigned int bar = FL_GET_BASE(board->flags); 198 199 switch (priv->dev->subsystem_device) { 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 201 if (idx == 3) 202 idx++; 203 break; 204 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 205 if (idx > 0) 206 idx++; 207 if (idx > 2) 208 idx++; 209 break; 210 } 211 if (idx > 2) 212 offset = 0x18; 213 214 offset += idx * board->uart_offset; 215 216 return setup_port(priv, port, bar, offset, board->reg_shift); 217 } 218 219 /* 220 * Added for EKF Intel i960 serial boards 221 */ 222 static int pci_inteli960ni_init(struct pci_dev *dev) 223 { 224 unsigned long oldval; 225 226 if (!(dev->subsystem_device & 0x1000)) 227 return -ENODEV; 228 229 /* is firmware started? */ 230 pci_read_config_dword(dev, 0x44, (void *)&oldval); 231 if (oldval == 0x00001000L) { /* RESET value */ 232 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 233 return -ENODEV; 234 } 235 return 0; 236 } 237 238 /* 239 * Some PCI serial cards using the PLX 9050 PCI interface chip require 240 * that the card interrupt be explicitly enabled or disabled. This 241 * seems to be mainly needed on card using the PLX which also use I/O 242 * mapped memory. 243 */ 244 static int pci_plx9050_init(struct pci_dev *dev) 245 { 246 u8 irq_config; 247 void __iomem *p; 248 249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 250 moan_device("no memory in bar 0", dev); 251 return 0; 252 } 253 254 irq_config = 0x41; 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 257 irq_config = 0x43; 258 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 261 /* 262 * As the megawolf cards have the int pins active 263 * high, and have 2 UART chips, both ints must be 264 * enabled on the 9050. Also, the UARTS are set in 265 * 16450 mode by default, so we have to enable the 266 * 16C950 'enhanced' mode so that we can use the 267 * deep FIFOs 268 */ 269 irq_config = 0x5b; 270 /* 271 * enable/disable interrupts 272 */ 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 274 if (p == NULL) 275 return -ENOMEM; 276 writel(irq_config, p + 0x4c); 277 278 /* 279 * Read the register back to ensure that it took effect. 280 */ 281 readl(p + 0x4c); 282 iounmap(p); 283 284 return 0; 285 } 286 287 static void pci_plx9050_exit(struct pci_dev *dev) 288 { 289 u8 __iomem *p; 290 291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 292 return; 293 294 /* 295 * disable interrupts 296 */ 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 298 if (p != NULL) { 299 writel(0, p + 0x4c); 300 301 /* 302 * Read the register back to ensure that it took effect. 303 */ 304 readl(p + 0x4c); 305 iounmap(p); 306 } 307 } 308 309 #define NI8420_INT_ENABLE_REG 0x38 310 #define NI8420_INT_ENABLE_BIT 0x2000 311 312 static void pci_ni8420_exit(struct pci_dev *dev) 313 { 314 void __iomem *p; 315 unsigned int bar = 0; 316 317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 318 moan_device("no memory in bar", dev); 319 return; 320 } 321 322 p = pci_ioremap_bar(dev, bar); 323 if (p == NULL) 324 return; 325 326 /* Disable the CPU Interrupt */ 327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 328 p + NI8420_INT_ENABLE_REG); 329 iounmap(p); 330 } 331 332 333 /* MITE registers */ 334 #define MITE_IOWBSR1 0xc4 335 #define MITE_IOWCR1 0xf4 336 #define MITE_LCIMR1 0x08 337 #define MITE_LCIMR2 0x10 338 339 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 340 341 static void pci_ni8430_exit(struct pci_dev *dev) 342 { 343 void __iomem *p; 344 unsigned int bar = 0; 345 346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 347 moan_device("no memory in bar", dev); 348 return; 349 } 350 351 p = pci_ioremap_bar(dev, bar); 352 if (p == NULL) 353 return; 354 355 /* Disable the CPU Interrupt */ 356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 357 iounmap(p); 358 } 359 360 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 361 static int 362 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 363 struct uart_8250_port *port, int idx) 364 { 365 unsigned int bar, offset = board->first_offset; 366 367 bar = 0; 368 369 if (idx < 4) { 370 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 371 offset += idx * board->uart_offset; 372 } else if (idx < 8) { 373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 374 offset += idx * board->uart_offset + 0xC00; 375 } else /* we have only 8 ports on PMC-OCTALPRO */ 376 return 1; 377 378 return setup_port(priv, port, bar, offset, board->reg_shift); 379 } 380 381 /* 382 * This does initialization for PMC OCTALPRO cards: 383 * maps the device memory, resets the UARTs (needed, bc 384 * if the module is removed and inserted again, the card 385 * is in the sleep mode) and enables global interrupt. 386 */ 387 388 /* global control register offset for SBS PMC-OctalPro */ 389 #define OCT_REG_CR_OFF 0x500 390 391 static int sbs_init(struct pci_dev *dev) 392 { 393 u8 __iomem *p; 394 395 p = pci_ioremap_bar(dev, 0); 396 397 if (p == NULL) 398 return -ENOMEM; 399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 400 writeb(0x10, p + OCT_REG_CR_OFF); 401 udelay(50); 402 writeb(0x0, p + OCT_REG_CR_OFF); 403 404 /* Set bit-2 (INTENABLE) of Control Register */ 405 writeb(0x4, p + OCT_REG_CR_OFF); 406 iounmap(p); 407 408 return 0; 409 } 410 411 /* 412 * Disables the global interrupt of PMC-OctalPro 413 */ 414 415 static void sbs_exit(struct pci_dev *dev) 416 { 417 u8 __iomem *p; 418 419 p = pci_ioremap_bar(dev, 0); 420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 421 if (p != NULL) 422 writeb(0, p + OCT_REG_CR_OFF); 423 iounmap(p); 424 } 425 426 /* 427 * SIIG serial cards have an PCI interface chip which also controls 428 * the UART clocking frequency. Each UART can be clocked independently 429 * (except cards equipped with 4 UARTs) and initial clocking settings 430 * are stored in the EEPROM chip. It can cause problems because this 431 * version of serial driver doesn't support differently clocked UART's 432 * on single PCI card. To prevent this, initialization functions set 433 * high frequency clocking for all UART's on given card. It is safe (I 434 * hope) because it doesn't touch EEPROM settings to prevent conflicts 435 * with other OSes (like M$ DOS). 436 * 437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 438 * 439 * There is two family of SIIG serial cards with different PCI 440 * interface chip and different configuration methods: 441 * - 10x cards have control registers in IO and/or memory space; 442 * - 20x cards have control registers in standard PCI configuration space. 443 * 444 * Note: all 10x cards have PCI device ids 0x10.. 445 * all 20x cards have PCI device ids 0x20.. 446 * 447 * There are also Quartet Serial cards which use Oxford Semiconductor 448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 449 * 450 * Note: some SIIG cards are probed by the parport_serial object. 451 */ 452 453 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 454 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 455 456 static int pci_siig10x_init(struct pci_dev *dev) 457 { 458 u16 data; 459 void __iomem *p; 460 461 switch (dev->device & 0xfff8) { 462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 463 data = 0xffdf; 464 break; 465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 466 data = 0xf7ff; 467 break; 468 default: /* 1S1P, 4S */ 469 data = 0xfffb; 470 break; 471 } 472 473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 474 if (p == NULL) 475 return -ENOMEM; 476 477 writew(readw(p + 0x28) & data, p + 0x28); 478 readw(p + 0x28); 479 iounmap(p); 480 return 0; 481 } 482 483 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 484 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 485 486 static int pci_siig20x_init(struct pci_dev *dev) 487 { 488 u8 data; 489 490 /* Change clock frequency for the first UART. */ 491 pci_read_config_byte(dev, 0x6f, &data); 492 pci_write_config_byte(dev, 0x6f, data & 0xef); 493 494 /* If this card has 2 UART, we have to do the same with second UART. */ 495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 497 pci_read_config_byte(dev, 0x73, &data); 498 pci_write_config_byte(dev, 0x73, data & 0xef); 499 } 500 return 0; 501 } 502 503 static int pci_siig_init(struct pci_dev *dev) 504 { 505 unsigned int type = dev->device & 0xff00; 506 507 if (type == 0x1000) 508 return pci_siig10x_init(dev); 509 else if (type == 0x2000) 510 return pci_siig20x_init(dev); 511 512 moan_device("Unknown SIIG card", dev); 513 return -ENODEV; 514 } 515 516 static int pci_siig_setup(struct serial_private *priv, 517 const struct pciserial_board *board, 518 struct uart_8250_port *port, int idx) 519 { 520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 521 522 if (idx > 3) { 523 bar = 4; 524 offset = (idx - 4) * 8; 525 } 526 527 return setup_port(priv, port, bar, offset, 0); 528 } 529 530 /* 531 * Timedia has an explosion of boards, and to avoid the PCI table from 532 * growing *huge*, we use this function to collapse some 70 entries 533 * in the PCI table into one, for sanity's and compactness's sake. 534 */ 535 static const unsigned short timedia_single_port[] = { 536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 537 }; 538 539 static const unsigned short timedia_dual_port[] = { 540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 544 0xD079, 0 545 }; 546 547 static const unsigned short timedia_quad_port[] = { 548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 551 0xB157, 0 552 }; 553 554 static const unsigned short timedia_eight_port[] = { 555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 557 }; 558 559 static const struct timedia_struct { 560 int num; 561 const unsigned short *ids; 562 } timedia_data[] = { 563 { 1, timedia_single_port }, 564 { 2, timedia_dual_port }, 565 { 4, timedia_quad_port }, 566 { 8, timedia_eight_port } 567 }; 568 569 /* 570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 571 * listing them individually, this driver merely grabs them all with 572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 573 * and should be left free to be claimed by parport_serial instead. 574 */ 575 static int pci_timedia_probe(struct pci_dev *dev) 576 { 577 /* 578 * Check the third digit of the subdevice ID 579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 580 */ 581 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 582 dev_info(&dev->dev, 583 "ignoring Timedia subdevice %04x for parport_serial\n", 584 dev->subsystem_device); 585 return -ENODEV; 586 } 587 588 return 0; 589 } 590 591 static int pci_timedia_init(struct pci_dev *dev) 592 { 593 const unsigned short *ids; 594 int i, j; 595 596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 597 ids = timedia_data[i].ids; 598 for (j = 0; ids[j]; j++) 599 if (dev->subsystem_device == ids[j]) 600 return timedia_data[i].num; 601 } 602 return 0; 603 } 604 605 /* 606 * Timedia/SUNIX uses a mixture of BARs and offsets 607 * Ugh, this is ugly as all hell --- TYT 608 */ 609 static int 610 pci_timedia_setup(struct serial_private *priv, 611 const struct pciserial_board *board, 612 struct uart_8250_port *port, int idx) 613 { 614 unsigned int bar = 0, offset = board->first_offset; 615 616 switch (idx) { 617 case 0: 618 bar = 0; 619 break; 620 case 1: 621 offset = board->uart_offset; 622 bar = 0; 623 break; 624 case 2: 625 bar = 1; 626 break; 627 case 3: 628 offset = board->uart_offset; 629 /* FALLTHROUGH */ 630 case 4: /* BAR 2 */ 631 case 5: /* BAR 3 */ 632 case 6: /* BAR 4 */ 633 case 7: /* BAR 5 */ 634 bar = idx - 2; 635 } 636 637 return setup_port(priv, port, bar, offset, board->reg_shift); 638 } 639 640 /* 641 * Some Titan cards are also a little weird 642 */ 643 static int 644 titan_400l_800l_setup(struct serial_private *priv, 645 const struct pciserial_board *board, 646 struct uart_8250_port *port, int idx) 647 { 648 unsigned int bar, offset = board->first_offset; 649 650 switch (idx) { 651 case 0: 652 bar = 1; 653 break; 654 case 1: 655 bar = 2; 656 break; 657 default: 658 bar = 4; 659 offset = (idx - 2) * board->uart_offset; 660 } 661 662 return setup_port(priv, port, bar, offset, board->reg_shift); 663 } 664 665 static int pci_xircom_init(struct pci_dev *dev) 666 { 667 msleep(100); 668 return 0; 669 } 670 671 static int pci_ni8420_init(struct pci_dev *dev) 672 { 673 void __iomem *p; 674 unsigned int bar = 0; 675 676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 677 moan_device("no memory in bar", dev); 678 return 0; 679 } 680 681 p = pci_ioremap_bar(dev, bar); 682 if (p == NULL) 683 return -ENOMEM; 684 685 /* Enable CPU Interrupt */ 686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 687 p + NI8420_INT_ENABLE_REG); 688 689 iounmap(p); 690 return 0; 691 } 692 693 #define MITE_IOWBSR1_WSIZE 0xa 694 #define MITE_IOWBSR1_WIN_OFFSET 0x800 695 #define MITE_IOWBSR1_WENAB (1 << 7) 696 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 697 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 698 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 699 700 static int pci_ni8430_init(struct pci_dev *dev) 701 { 702 void __iomem *p; 703 struct pci_bus_region region; 704 u32 device_window; 705 unsigned int bar = 0; 706 707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 708 moan_device("no memory in bar", dev); 709 return 0; 710 } 711 712 p = pci_ioremap_bar(dev, bar); 713 if (p == NULL) 714 return -ENOMEM; 715 716 /* 717 * Set device window address and size in BAR0, while acknowledging that 718 * the resource structure may contain a translated address that differs 719 * from the address the device responds to. 720 */ 721 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 724 writel(device_window, p + MITE_IOWBSR1); 725 726 /* Set window access to go to RAMSEL IO address space */ 727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 728 p + MITE_IOWCR1); 729 730 /* Enable IO Bus Interrupt 0 */ 731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 732 733 /* Enable CPU Interrupt */ 734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 735 736 iounmap(p); 737 return 0; 738 } 739 740 /* UART Port Control Register */ 741 #define NI8430_PORTCON 0x0f 742 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 743 744 static int 745 pci_ni8430_setup(struct serial_private *priv, 746 const struct pciserial_board *board, 747 struct uart_8250_port *port, int idx) 748 { 749 struct pci_dev *dev = priv->dev; 750 void __iomem *p; 751 unsigned int bar, offset = board->first_offset; 752 753 if (idx >= board->num_ports) 754 return 1; 755 756 bar = FL_GET_BASE(board->flags); 757 offset += idx * board->uart_offset; 758 759 p = pci_ioremap_bar(dev, bar); 760 if (!p) 761 return -ENOMEM; 762 763 /* enable the transceiver */ 764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 765 p + offset + NI8430_PORTCON); 766 767 iounmap(p); 768 769 return setup_port(priv, port, bar, offset, board->reg_shift); 770 } 771 772 static int pci_netmos_9900_setup(struct serial_private *priv, 773 const struct pciserial_board *board, 774 struct uart_8250_port *port, int idx) 775 { 776 unsigned int bar; 777 778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 779 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 780 /* netmos apparently orders BARs by datasheet layout, so serial 781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 782 */ 783 bar = 3 * idx; 784 785 return setup_port(priv, port, bar, 0, board->reg_shift); 786 } else { 787 return pci_default_setup(priv, board, port, idx); 788 } 789 } 790 791 /* the 99xx series comes with a range of device IDs and a variety 792 * of capabilities: 793 * 794 * 9900 has varying capabilities and can cascade to sub-controllers 795 * (cascading should be purely internal) 796 * 9904 is hardwired with 4 serial ports 797 * 9912 and 9922 are hardwired with 2 serial ports 798 */ 799 static int pci_netmos_9900_numports(struct pci_dev *dev) 800 { 801 unsigned int c = dev->class; 802 unsigned int pi; 803 unsigned short sub_serports; 804 805 pi = (c & 0xff); 806 807 if (pi == 2) { 808 return 1; 809 } else if ((pi == 0) && 810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 811 /* two possibilities: 0x30ps encodes number of parallel and 812 * serial ports, or 0x1000 indicates *something*. This is not 813 * immediately obvious, since the 2s1p+4s configuration seems 814 * to offer all functionality on functions 0..2, while still 815 * advertising the same function 3 as the 4s+2s1p config. 816 */ 817 sub_serports = dev->subsystem_device & 0xf; 818 if (sub_serports > 0) { 819 return sub_serports; 820 } else { 821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 822 return 0; 823 } 824 } 825 826 moan_device("unknown NetMos/Mostech program interface", dev); 827 return 0; 828 } 829 830 static int pci_netmos_init(struct pci_dev *dev) 831 { 832 /* subdevice 0x00PS means <P> parallel, <S> serial */ 833 unsigned int num_serial = dev->subsystem_device & 0xf; 834 835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 836 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 837 return 0; 838 839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 840 dev->subsystem_device == 0x0299) 841 return 0; 842 843 switch (dev->device) { /* FALLTHROUGH on all */ 844 case PCI_DEVICE_ID_NETMOS_9904: 845 case PCI_DEVICE_ID_NETMOS_9912: 846 case PCI_DEVICE_ID_NETMOS_9922: 847 case PCI_DEVICE_ID_NETMOS_9900: 848 num_serial = pci_netmos_9900_numports(dev); 849 break; 850 851 default: 852 if (num_serial == 0 ) { 853 moan_device("unknown NetMos/Mostech device", dev); 854 } 855 } 856 857 if (num_serial == 0) 858 return -ENODEV; 859 860 return num_serial; 861 } 862 863 /* 864 * These chips are available with optionally one parallel port and up to 865 * two serial ports. Unfortunately they all have the same product id. 866 * 867 * Basic configuration is done over a region of 32 I/O ports. The base 868 * ioport is called INTA or INTC, depending on docs/other drivers. 869 * 870 * The region of the 32 I/O ports is configured in POSIO0R... 871 */ 872 873 /* registers */ 874 #define ITE_887x_MISCR 0x9c 875 #define ITE_887x_INTCBAR 0x78 876 #define ITE_887x_UARTBAR 0x7c 877 #define ITE_887x_PS0BAR 0x10 878 #define ITE_887x_POSIO0 0x60 879 880 /* I/O space size */ 881 #define ITE_887x_IOSIZE 32 882 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 883 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 884 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 885 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 886 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 887 #define ITE_887x_POSIO_SPEED (3 << 29) 888 /* enable IO_Space bit */ 889 #define ITE_887x_POSIO_ENABLE (1 << 31) 890 891 static int pci_ite887x_init(struct pci_dev *dev) 892 { 893 /* inta_addr are the configuration addresses of the ITE */ 894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 895 0x200, 0x280, 0 }; 896 int ret, i, type; 897 struct resource *iobase = NULL; 898 u32 miscr, uartbar, ioport; 899 900 /* search for the base-ioport */ 901 i = 0; 902 while (inta_addr[i] && iobase == NULL) { 903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 904 "ite887x"); 905 if (iobase != NULL) { 906 /* write POSIO0R - speed | size | ioport */ 907 pci_write_config_dword(dev, ITE_887x_POSIO0, 908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 910 /* write INTCBAR - ioport */ 911 pci_write_config_dword(dev, ITE_887x_INTCBAR, 912 inta_addr[i]); 913 ret = inb(inta_addr[i]); 914 if (ret != 0xff) { 915 /* ioport connected */ 916 break; 917 } 918 release_region(iobase->start, ITE_887x_IOSIZE); 919 iobase = NULL; 920 } 921 i++; 922 } 923 924 if (!inta_addr[i]) { 925 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 926 return -ENODEV; 927 } 928 929 /* start of undocumented type checking (see parport_pc.c) */ 930 type = inb(iobase->start + 0x18) & 0x0f; 931 932 switch (type) { 933 case 0x2: /* ITE8871 (1P) */ 934 case 0xa: /* ITE8875 (1P) */ 935 ret = 0; 936 break; 937 case 0xe: /* ITE8872 (2S1P) */ 938 ret = 2; 939 break; 940 case 0x6: /* ITE8873 (1S) */ 941 ret = 1; 942 break; 943 case 0x8: /* ITE8874 (2S) */ 944 ret = 2; 945 break; 946 default: 947 moan_device("Unknown ITE887x", dev); 948 ret = -ENODEV; 949 } 950 951 /* configure all serial ports */ 952 for (i = 0; i < ret; i++) { 953 /* read the I/O port from the device */ 954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 955 &ioport); 956 ioport &= 0x0000FF00; /* the actual base address */ 957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 959 ITE_887x_POSIO_IOSIZE_8 | ioport); 960 961 /* write the ioport to the UARTBAR */ 962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 964 uartbar |= (ioport << (16 * i)); /* set the ioport */ 965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 966 967 /* get current config */ 968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 969 /* disable interrupts (UARTx_Routing[3:0]) */ 970 miscr &= ~(0xf << (12 - 4 * i)); 971 /* activate the UART (UARTx_En) */ 972 miscr |= 1 << (23 - i); 973 /* write new config with activated UART */ 974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 975 } 976 977 if (ret <= 0) { 978 /* the device has no UARTs if we get here */ 979 release_region(iobase->start, ITE_887x_IOSIZE); 980 } 981 982 return ret; 983 } 984 985 static void pci_ite887x_exit(struct pci_dev *dev) 986 { 987 u32 ioport; 988 /* the ioport is bit 0-15 in POSIO0R */ 989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 990 ioport &= 0xffff; 991 release_region(ioport, ITE_887x_IOSIZE); 992 } 993 994 /* 995 * EndRun Technologies. 996 * Determine the number of ports available on the device. 997 */ 998 #define PCI_VENDOR_ID_ENDRUN 0x7401 999 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1000 1001 static int pci_endrun_init(struct pci_dev *dev) 1002 { 1003 u8 __iomem *p; 1004 unsigned long deviceID; 1005 unsigned int number_uarts = 0; 1006 1007 /* EndRun device is all 0xexxx */ 1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1009 (dev->device & 0xf000) != 0xe000) 1010 return 0; 1011 1012 p = pci_iomap(dev, 0, 5); 1013 if (p == NULL) 1014 return -ENOMEM; 1015 1016 deviceID = ioread32(p); 1017 /* EndRun device */ 1018 if (deviceID == 0x07000200) { 1019 number_uarts = ioread8(p + 4); 1020 dev_dbg(&dev->dev, 1021 "%d ports detected on EndRun PCI Express device\n", 1022 number_uarts); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* 1029 * Oxford Semiconductor Inc. 1030 * Check that device is part of the Tornado range of devices, then determine 1031 * the number of ports available on the device. 1032 */ 1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1034 { 1035 u8 __iomem *p; 1036 unsigned long deviceID; 1037 unsigned int number_uarts = 0; 1038 1039 /* OxSemi Tornado devices are all 0xCxxx */ 1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1041 (dev->device & 0xF000) != 0xC000) 1042 return 0; 1043 1044 p = pci_iomap(dev, 0, 5); 1045 if (p == NULL) 1046 return -ENOMEM; 1047 1048 deviceID = ioread32(p); 1049 /* Tornado device */ 1050 if (deviceID == 0x07000200) { 1051 number_uarts = ioread8(p + 4); 1052 dev_dbg(&dev->dev, 1053 "%d ports detected on Oxford PCI Express device\n", 1054 number_uarts); 1055 } 1056 pci_iounmap(dev, p); 1057 return number_uarts; 1058 } 1059 1060 static int pci_asix_setup(struct serial_private *priv, 1061 const struct pciserial_board *board, 1062 struct uart_8250_port *port, int idx) 1063 { 1064 port->bugs |= UART_BUG_PARITY; 1065 return pci_default_setup(priv, board, port, idx); 1066 } 1067 1068 /* Quatech devices have their own extra interface features */ 1069 1070 struct quatech_feature { 1071 u16 devid; 1072 bool amcc; 1073 }; 1074 1075 #define QPCR_TEST_FOR1 0x3F 1076 #define QPCR_TEST_GET1 0x00 1077 #define QPCR_TEST_FOR2 0x40 1078 #define QPCR_TEST_GET2 0x40 1079 #define QPCR_TEST_FOR3 0x80 1080 #define QPCR_TEST_GET3 0x40 1081 #define QPCR_TEST_FOR4 0xC0 1082 #define QPCR_TEST_GET4 0x80 1083 1084 #define QOPR_CLOCK_X1 0x0000 1085 #define QOPR_CLOCK_X2 0x0001 1086 #define QOPR_CLOCK_X4 0x0002 1087 #define QOPR_CLOCK_X8 0x0003 1088 #define QOPR_CLOCK_RATE_MASK 0x0003 1089 1090 1091 static struct quatech_feature quatech_cards[] = { 1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1111 { 0, } 1112 }; 1113 1114 static int pci_quatech_amcc(u16 devid) 1115 { 1116 struct quatech_feature *qf = &quatech_cards[0]; 1117 while (qf->devid) { 1118 if (qf->devid == devid) 1119 return qf->amcc; 1120 qf++; 1121 } 1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1123 return 0; 1124 }; 1125 1126 static int pci_quatech_rqopr(struct uart_8250_port *port) 1127 { 1128 unsigned long base = port->port.iobase; 1129 u8 LCR, val; 1130 1131 LCR = inb(base + UART_LCR); 1132 outb(0xBF, base + UART_LCR); 1133 val = inb(base + UART_SCR); 1134 outb(LCR, base + UART_LCR); 1135 return val; 1136 } 1137 1138 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1139 { 1140 unsigned long base = port->port.iobase; 1141 u8 LCR, val; 1142 1143 LCR = inb(base + UART_LCR); 1144 outb(0xBF, base + UART_LCR); 1145 val = inb(base + UART_SCR); 1146 outb(qopr, base + UART_SCR); 1147 outb(LCR, base + UART_LCR); 1148 } 1149 1150 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1151 { 1152 unsigned long base = port->port.iobase; 1153 u8 LCR, val, qmcr; 1154 1155 LCR = inb(base + UART_LCR); 1156 outb(0xBF, base + UART_LCR); 1157 val = inb(base + UART_SCR); 1158 outb(val | 0x10, base + UART_SCR); 1159 qmcr = inb(base + UART_MCR); 1160 outb(val, base + UART_SCR); 1161 outb(LCR, base + UART_LCR); 1162 1163 return qmcr; 1164 } 1165 1166 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1167 { 1168 unsigned long base = port->port.iobase; 1169 u8 LCR, val; 1170 1171 LCR = inb(base + UART_LCR); 1172 outb(0xBF, base + UART_LCR); 1173 val = inb(base + UART_SCR); 1174 outb(val | 0x10, base + UART_SCR); 1175 outb(qmcr, base + UART_MCR); 1176 outb(val, base + UART_SCR); 1177 outb(LCR, base + UART_LCR); 1178 } 1179 1180 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1181 { 1182 unsigned long base = port->port.iobase; 1183 u8 LCR, val; 1184 1185 LCR = inb(base + UART_LCR); 1186 outb(0xBF, base + UART_LCR); 1187 val = inb(base + UART_SCR); 1188 if (val & 0x20) { 1189 outb(0x80, UART_LCR); 1190 if (!(inb(UART_SCR) & 0x20)) { 1191 outb(LCR, base + UART_LCR); 1192 return 1; 1193 } 1194 } 1195 return 0; 1196 } 1197 1198 static int pci_quatech_test(struct uart_8250_port *port) 1199 { 1200 u8 reg; 1201 u8 qopr = pci_quatech_rqopr(port); 1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1203 reg = pci_quatech_rqopr(port) & 0xC0; 1204 if (reg != QPCR_TEST_GET1) 1205 return -EINVAL; 1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1207 reg = pci_quatech_rqopr(port) & 0xC0; 1208 if (reg != QPCR_TEST_GET2) 1209 return -EINVAL; 1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1211 reg = pci_quatech_rqopr(port) & 0xC0; 1212 if (reg != QPCR_TEST_GET3) 1213 return -EINVAL; 1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1215 reg = pci_quatech_rqopr(port) & 0xC0; 1216 if (reg != QPCR_TEST_GET4) 1217 return -EINVAL; 1218 1219 pci_quatech_wqopr(port, qopr); 1220 return 0; 1221 } 1222 1223 static int pci_quatech_clock(struct uart_8250_port *port) 1224 { 1225 u8 qopr, reg, set; 1226 unsigned long clock; 1227 1228 if (pci_quatech_test(port) < 0) 1229 return 1843200; 1230 1231 qopr = pci_quatech_rqopr(port); 1232 1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1234 reg = pci_quatech_rqopr(port); 1235 if (reg & QOPR_CLOCK_X8) { 1236 clock = 1843200; 1237 goto out; 1238 } 1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1240 reg = pci_quatech_rqopr(port); 1241 if (!(reg & QOPR_CLOCK_X8)) { 1242 clock = 1843200; 1243 goto out; 1244 } 1245 reg &= QOPR_CLOCK_X8; 1246 if (reg == QOPR_CLOCK_X2) { 1247 clock = 3685400; 1248 set = QOPR_CLOCK_X2; 1249 } else if (reg == QOPR_CLOCK_X4) { 1250 clock = 7372800; 1251 set = QOPR_CLOCK_X4; 1252 } else if (reg == QOPR_CLOCK_X8) { 1253 clock = 14745600; 1254 set = QOPR_CLOCK_X8; 1255 } else { 1256 clock = 1843200; 1257 set = QOPR_CLOCK_X1; 1258 } 1259 qopr &= ~QOPR_CLOCK_RATE_MASK; 1260 qopr |= set; 1261 1262 out: 1263 pci_quatech_wqopr(port, qopr); 1264 return clock; 1265 } 1266 1267 static int pci_quatech_rs422(struct uart_8250_port *port) 1268 { 1269 u8 qmcr; 1270 int rs422 = 0; 1271 1272 if (!pci_quatech_has_qmcr(port)) 1273 return 0; 1274 qmcr = pci_quatech_rqmcr(port); 1275 pci_quatech_wqmcr(port, 0xFF); 1276 if (pci_quatech_rqmcr(port)) 1277 rs422 = 1; 1278 pci_quatech_wqmcr(port, qmcr); 1279 return rs422; 1280 } 1281 1282 static int pci_quatech_init(struct pci_dev *dev) 1283 { 1284 if (pci_quatech_amcc(dev->device)) { 1285 unsigned long base = pci_resource_start(dev, 0); 1286 if (base) { 1287 u32 tmp; 1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1289 tmp = inl(base + 0x3c); 1290 outl(tmp | 0x01000000, base + 0x3c); 1291 outl(tmp &= ~0x01000000, base + 0x3c); 1292 } 1293 } 1294 return 0; 1295 } 1296 1297 static int pci_quatech_setup(struct serial_private *priv, 1298 const struct pciserial_board *board, 1299 struct uart_8250_port *port, int idx) 1300 { 1301 /* Needed by pci_quatech calls below */ 1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1303 /* Set up the clocking */ 1304 port->port.uartclk = pci_quatech_clock(port); 1305 /* For now just warn about RS422 */ 1306 if (pci_quatech_rs422(port)) 1307 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1308 return pci_default_setup(priv, board, port, idx); 1309 } 1310 1311 static void pci_quatech_exit(struct pci_dev *dev) 1312 { 1313 } 1314 1315 static int pci_default_setup(struct serial_private *priv, 1316 const struct pciserial_board *board, 1317 struct uart_8250_port *port, int idx) 1318 { 1319 unsigned int bar, offset = board->first_offset, maxnr; 1320 1321 bar = FL_GET_BASE(board->flags); 1322 if (board->flags & FL_BASE_BARS) 1323 bar += idx; 1324 else 1325 offset += idx * board->uart_offset; 1326 1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1328 (board->reg_shift + 3); 1329 1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1331 return 1; 1332 1333 return setup_port(priv, port, bar, offset, board->reg_shift); 1334 } 1335 1336 static int pci_pericom_setup(struct serial_private *priv, 1337 const struct pciserial_board *board, 1338 struct uart_8250_port *port, int idx) 1339 { 1340 unsigned int bar, offset = board->first_offset, maxnr; 1341 1342 bar = FL_GET_BASE(board->flags); 1343 if (board->flags & FL_BASE_BARS) 1344 bar += idx; 1345 else 1346 offset += idx * board->uart_offset; 1347 1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1349 (board->reg_shift + 3); 1350 1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1352 return 1; 1353 1354 port->port.uartclk = 14745600; 1355 1356 return setup_port(priv, port, bar, offset, board->reg_shift); 1357 } 1358 1359 static int 1360 ce4100_serial_setup(struct serial_private *priv, 1361 const struct pciserial_board *board, 1362 struct uart_8250_port *port, int idx) 1363 { 1364 int ret; 1365 1366 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1367 port->port.iotype = UPIO_MEM32; 1368 port->port.type = PORT_XSCALE; 1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1370 port->port.regshift = 2; 1371 1372 return ret; 1373 } 1374 1375 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1376 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1377 1378 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a 1379 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c 1380 1381 #define BYT_PRV_CLK 0x800 1382 #define BYT_PRV_CLK_EN (1 << 0) 1383 #define BYT_PRV_CLK_M_VAL_SHIFT 1 1384 #define BYT_PRV_CLK_N_VAL_SHIFT 16 1385 #define BYT_PRV_CLK_UPDATE (1 << 31) 1386 1387 #define BYT_TX_OVF_INT 0x820 1388 #define BYT_TX_OVF_INT_MASK (1 << 1) 1389 1390 static void 1391 byt_set_termios(struct uart_port *p, struct ktermios *termios, 1392 struct ktermios *old) 1393 { 1394 unsigned int baud = tty_termios_baud_rate(termios); 1395 unsigned int m, n; 1396 u32 reg; 1397 1398 /* 1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1400 * dividers must be adjusted. 1401 * 1402 * uartclk = (m / n) * 100 MHz, where m <= n 1403 */ 1404 switch (baud) { 1405 case 500000: 1406 case 1000000: 1407 case 2000000: 1408 case 4000000: 1409 m = 64; 1410 n = 100; 1411 p->uartclk = 64000000; 1412 break; 1413 case 3500000: 1414 m = 56; 1415 n = 100; 1416 p->uartclk = 56000000; 1417 break; 1418 case 1500000: 1419 case 3000000: 1420 m = 48; 1421 n = 100; 1422 p->uartclk = 48000000; 1423 break; 1424 case 2500000: 1425 m = 40; 1426 n = 100; 1427 p->uartclk = 40000000; 1428 break; 1429 default: 1430 m = 2304; 1431 n = 3125; 1432 p->uartclk = 73728000; 1433 } 1434 1435 /* Reset the clock */ 1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1437 writel(reg, p->membase + BYT_PRV_CLK); 1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1439 writel(reg, p->membase + BYT_PRV_CLK); 1440 1441 serial8250_do_set_termios(p, termios, old); 1442 } 1443 1444 static bool byt_dma_filter(struct dma_chan *chan, void *param) 1445 { 1446 struct dw_dma_slave *dws = param; 1447 1448 if (dws->dma_dev != chan->device->dev) 1449 return false; 1450 1451 chan->private = dws; 1452 return true; 1453 } 1454 1455 static int 1456 byt_serial_setup(struct serial_private *priv, 1457 const struct pciserial_board *board, 1458 struct uart_8250_port *port, int idx) 1459 { 1460 struct pci_dev *pdev = priv->dev; 1461 struct device *dev = port->port.dev; 1462 struct uart_8250_dma *dma; 1463 struct dw_dma_slave *tx_param, *rx_param; 1464 struct pci_dev *dma_dev; 1465 int ret; 1466 1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 1468 if (!dma) 1469 return -ENOMEM; 1470 1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); 1472 if (!tx_param) 1473 return -ENOMEM; 1474 1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); 1476 if (!rx_param) 1477 return -ENOMEM; 1478 1479 switch (pdev->device) { 1480 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1481 case PCI_DEVICE_ID_INTEL_BSW_UART1: 1482 rx_param->src_id = 3; 1483 tx_param->dst_id = 2; 1484 break; 1485 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1486 case PCI_DEVICE_ID_INTEL_BSW_UART2: 1487 rx_param->src_id = 5; 1488 tx_param->dst_id = 4; 1489 break; 1490 default: 1491 return -EINVAL; 1492 } 1493 1494 rx_param->src_master = 1; 1495 rx_param->dst_master = 0; 1496 1497 dma->rxconf.src_maxburst = 16; 1498 1499 tx_param->src_master = 1; 1500 tx_param->dst_master = 0; 1501 1502 dma->txconf.dst_maxburst = 16; 1503 1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0)); 1505 rx_param->dma_dev = &dma_dev->dev; 1506 tx_param->dma_dev = &dma_dev->dev; 1507 1508 dma->fn = byt_dma_filter; 1509 dma->rx_param = rx_param; 1510 dma->tx_param = tx_param; 1511 1512 ret = pci_default_setup(priv, board, port, idx); 1513 port->port.iotype = UPIO_MEM; 1514 port->port.type = PORT_16550A; 1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1516 port->port.set_termios = byt_set_termios; 1517 port->port.fifosize = 64; 1518 port->tx_loadsz = 64; 1519 port->dma = dma; 1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1521 1522 /* Disable Tx counter interrupts */ 1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1524 1525 return ret; 1526 } 1527 1528 static int 1529 pci_omegapci_setup(struct serial_private *priv, 1530 const struct pciserial_board *board, 1531 struct uart_8250_port *port, int idx) 1532 { 1533 return setup_port(priv, port, 2, idx * 8, 0); 1534 } 1535 1536 static int 1537 pci_brcm_trumanage_setup(struct serial_private *priv, 1538 const struct pciserial_board *board, 1539 struct uart_8250_port *port, int idx) 1540 { 1541 int ret = pci_default_setup(priv, board, port, idx); 1542 1543 port->port.type = PORT_BRCM_TRUMANAGE; 1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1545 return ret; 1546 } 1547 1548 static int pci_fintek_setup(struct serial_private *priv, 1549 const struct pciserial_board *board, 1550 struct uart_8250_port *port, int idx) 1551 { 1552 struct pci_dev *pdev = priv->dev; 1553 unsigned long base; 1554 unsigned long iobase; 1555 unsigned long ciobase = 0; 1556 u8 config_base; 1557 u32 bar_data[3]; 1558 1559 /* 1560 * Find each UARTs offset in PCI configuraion space 1561 */ 1562 switch (idx) { 1563 case 0: 1564 config_base = 0x40; 1565 break; 1566 case 1: 1567 config_base = 0x48; 1568 break; 1569 case 2: 1570 config_base = 0x50; 1571 break; 1572 case 3: 1573 config_base = 0x58; 1574 break; 1575 case 4: 1576 config_base = 0x60; 1577 break; 1578 case 5: 1579 config_base = 0x68; 1580 break; 1581 case 6: 1582 config_base = 0x70; 1583 break; 1584 case 7: 1585 config_base = 0x78; 1586 break; 1587 case 8: 1588 config_base = 0x80; 1589 break; 1590 case 9: 1591 config_base = 0x88; 1592 break; 1593 case 10: 1594 config_base = 0x90; 1595 break; 1596 case 11: 1597 config_base = 0x98; 1598 break; 1599 default: 1600 /* Unknown number of ports, get out of here */ 1601 return -EINVAL; 1602 } 1603 1604 if (idx < 4) { 1605 base = pci_resource_start(priv->dev, 3); 1606 ciobase = (int)(base + (0x8 * idx)); 1607 } 1608 1609 /* Get the io address dispatch from the BIOS */ 1610 pci_read_config_dword(pdev, 0x24, &bar_data[0]); 1611 pci_read_config_dword(pdev, 0x20, &bar_data[1]); 1612 pci_read_config_dword(pdev, 0x1c, &bar_data[2]); 1613 1614 /* Calculate Real IO Port */ 1615 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8; 1616 1617 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n", 1618 __func__, idx, iobase, ciobase, config_base); 1619 1620 /* Enable UART I/O port */ 1621 pci_write_config_byte(pdev, config_base + 0x00, 0x01); 1622 1623 /* Select 128-byte FIFO and 8x FIFO threshold */ 1624 pci_write_config_byte(pdev, config_base + 0x01, 0x33); 1625 1626 /* LSB UART */ 1627 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff)); 1628 1629 /* MSB UART */ 1630 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8)); 1631 1632 /* irq number, this usually fails, but the spec says to do it anyway. */ 1633 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq); 1634 1635 port->port.iotype = UPIO_PORT; 1636 port->port.iobase = iobase; 1637 port->port.mapbase = 0; 1638 port->port.membase = NULL; 1639 port->port.regshift = 0; 1640 1641 return 0; 1642 } 1643 1644 static int skip_tx_en_setup(struct serial_private *priv, 1645 const struct pciserial_board *board, 1646 struct uart_8250_port *port, int idx) 1647 { 1648 port->port.flags |= UPF_NO_TXEN_TEST; 1649 dev_dbg(&priv->dev->dev, 1650 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1651 priv->dev->vendor, priv->dev->device, 1652 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1653 1654 return pci_default_setup(priv, board, port, idx); 1655 } 1656 1657 static void kt_handle_break(struct uart_port *p) 1658 { 1659 struct uart_8250_port *up = up_to_u8250p(p); 1660 /* 1661 * On receipt of a BI, serial device in Intel ME (Intel 1662 * management engine) needs to have its fifos cleared for sane 1663 * SOL (Serial Over Lan) output. 1664 */ 1665 serial8250_clear_and_reinit_fifos(up); 1666 } 1667 1668 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1669 { 1670 struct uart_8250_port *up = up_to_u8250p(p); 1671 unsigned int val; 1672 1673 /* 1674 * When the Intel ME (management engine) gets reset its serial 1675 * port registers could return 0 momentarily. Functions like 1676 * serial8250_console_write, read and save the IER, perform 1677 * some operation and then restore it. In order to avoid 1678 * setting IER register inadvertently to 0, if the value read 1679 * is 0, double check with ier value in uart_8250_port and use 1680 * that instead. up->ier should be the same value as what is 1681 * currently configured. 1682 */ 1683 val = inb(p->iobase + offset); 1684 if (offset == UART_IER) { 1685 if (val == 0) 1686 val = up->ier; 1687 } 1688 return val; 1689 } 1690 1691 static int kt_serial_setup(struct serial_private *priv, 1692 const struct pciserial_board *board, 1693 struct uart_8250_port *port, int idx) 1694 { 1695 port->port.flags |= UPF_BUG_THRE; 1696 port->port.serial_in = kt_serial_in; 1697 port->port.handle_break = kt_handle_break; 1698 return skip_tx_en_setup(priv, board, port, idx); 1699 } 1700 1701 static int pci_eg20t_init(struct pci_dev *dev) 1702 { 1703 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1704 return -ENODEV; 1705 #else 1706 return 0; 1707 #endif 1708 } 1709 1710 static int 1711 pci_xr17c154_setup(struct serial_private *priv, 1712 const struct pciserial_board *board, 1713 struct uart_8250_port *port, int idx) 1714 { 1715 port->port.flags |= UPF_EXAR_EFR; 1716 return pci_default_setup(priv, board, port, idx); 1717 } 1718 1719 static int 1720 pci_xr17v35x_setup(struct serial_private *priv, 1721 const struct pciserial_board *board, 1722 struct uart_8250_port *port, int idx) 1723 { 1724 u8 __iomem *p; 1725 1726 p = pci_ioremap_bar(priv->dev, 0); 1727 if (p == NULL) 1728 return -ENOMEM; 1729 1730 port->port.flags |= UPF_EXAR_EFR; 1731 1732 /* 1733 * Setup Multipurpose Input/Output pins. 1734 */ 1735 if (idx == 0) { 1736 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1737 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1738 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1739 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1740 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1741 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1742 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1743 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1744 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1745 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1746 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1747 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1748 } 1749 writeb(0x00, p + UART_EXAR_8XMODE); 1750 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1751 writeb(128, p + UART_EXAR_TXTRG); 1752 writeb(128, p + UART_EXAR_RXTRG); 1753 iounmap(p); 1754 1755 return pci_default_setup(priv, board, port, idx); 1756 } 1757 1758 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1759 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1760 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1761 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1762 1763 static int 1764 pci_fastcom335_setup(struct serial_private *priv, 1765 const struct pciserial_board *board, 1766 struct uart_8250_port *port, int idx) 1767 { 1768 u8 __iomem *p; 1769 1770 p = pci_ioremap_bar(priv->dev, 0); 1771 if (p == NULL) 1772 return -ENOMEM; 1773 1774 port->port.flags |= UPF_EXAR_EFR; 1775 1776 /* 1777 * Setup Multipurpose Input/Output pins. 1778 */ 1779 if (idx == 0) { 1780 switch (priv->dev->device) { 1781 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1782 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1783 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1784 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1785 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1786 break; 1787 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1788 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1789 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1790 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1791 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1792 break; 1793 } 1794 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1795 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1796 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1797 } 1798 writeb(0x00, p + UART_EXAR_8XMODE); 1799 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1800 writeb(32, p + UART_EXAR_TXTRG); 1801 writeb(32, p + UART_EXAR_RXTRG); 1802 iounmap(p); 1803 1804 return pci_default_setup(priv, board, port, idx); 1805 } 1806 1807 static int 1808 pci_wch_ch353_setup(struct serial_private *priv, 1809 const struct pciserial_board *board, 1810 struct uart_8250_port *port, int idx) 1811 { 1812 port->port.flags |= UPF_FIXED_TYPE; 1813 port->port.type = PORT_16550A; 1814 return pci_default_setup(priv, board, port, idx); 1815 } 1816 1817 static int 1818 pci_wch_ch38x_setup(struct serial_private *priv, 1819 const struct pciserial_board *board, 1820 struct uart_8250_port *port, int idx) 1821 { 1822 port->port.flags |= UPF_FIXED_TYPE; 1823 port->port.type = PORT_16850; 1824 return pci_default_setup(priv, board, port, idx); 1825 } 1826 1827 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1828 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1829 #define PCI_DEVICE_ID_OCTPRO 0x0001 1830 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1831 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1832 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1833 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1834 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1835 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1836 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1837 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1838 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1839 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1840 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1841 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1842 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1843 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1844 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1845 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1846 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1847 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1848 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1849 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1850 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1851 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1852 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1853 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1854 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1855 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1856 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1857 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1858 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1859 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1860 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1861 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1862 #define PCI_VENDOR_ID_WCH 0x4348 1863 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1864 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1865 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1866 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1867 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1868 #define PCI_VENDOR_ID_AGESTAR 0x5372 1869 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1870 #define PCI_VENDOR_ID_ASIX 0x9710 1871 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1872 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1873 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1874 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1875 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1876 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936 1877 1878 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1879 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1880 1881 #define PCIE_VENDOR_ID_WCH 0x1c00 1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1883 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1884 1885 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1886 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1887 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1888 1889 /* 1890 * Master list of serial port init/setup/exit quirks. 1891 * This does not describe the general nature of the port. 1892 * (ie, baud base, number and location of ports, etc) 1893 * 1894 * This list is ordered alphabetically by vendor then device. 1895 * Specific entries must come before more generic entries. 1896 */ 1897 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1898 /* 1899 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1900 */ 1901 { 1902 .vendor = PCI_VENDOR_ID_AMCC, 1903 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1904 .subvendor = PCI_ANY_ID, 1905 .subdevice = PCI_ANY_ID, 1906 .setup = addidata_apci7800_setup, 1907 }, 1908 /* 1909 * AFAVLAB cards - these may be called via parport_serial 1910 * It is not clear whether this applies to all products. 1911 */ 1912 { 1913 .vendor = PCI_VENDOR_ID_AFAVLAB, 1914 .device = PCI_ANY_ID, 1915 .subvendor = PCI_ANY_ID, 1916 .subdevice = PCI_ANY_ID, 1917 .setup = afavlab_setup, 1918 }, 1919 /* 1920 * HP Diva 1921 */ 1922 { 1923 .vendor = PCI_VENDOR_ID_HP, 1924 .device = PCI_DEVICE_ID_HP_DIVA, 1925 .subvendor = PCI_ANY_ID, 1926 .subdevice = PCI_ANY_ID, 1927 .init = pci_hp_diva_init, 1928 .setup = pci_hp_diva_setup, 1929 }, 1930 /* 1931 * Intel 1932 */ 1933 { 1934 .vendor = PCI_VENDOR_ID_INTEL, 1935 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1936 .subvendor = 0xe4bf, 1937 .subdevice = PCI_ANY_ID, 1938 .init = pci_inteli960ni_init, 1939 .setup = pci_default_setup, 1940 }, 1941 { 1942 .vendor = PCI_VENDOR_ID_INTEL, 1943 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1944 .subvendor = PCI_ANY_ID, 1945 .subdevice = PCI_ANY_ID, 1946 .setup = skip_tx_en_setup, 1947 }, 1948 { 1949 .vendor = PCI_VENDOR_ID_INTEL, 1950 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1951 .subvendor = PCI_ANY_ID, 1952 .subdevice = PCI_ANY_ID, 1953 .setup = skip_tx_en_setup, 1954 }, 1955 { 1956 .vendor = PCI_VENDOR_ID_INTEL, 1957 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1958 .subvendor = PCI_ANY_ID, 1959 .subdevice = PCI_ANY_ID, 1960 .setup = skip_tx_en_setup, 1961 }, 1962 { 1963 .vendor = PCI_VENDOR_ID_INTEL, 1964 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1965 .subvendor = PCI_ANY_ID, 1966 .subdevice = PCI_ANY_ID, 1967 .setup = ce4100_serial_setup, 1968 }, 1969 { 1970 .vendor = PCI_VENDOR_ID_INTEL, 1971 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1972 .subvendor = PCI_ANY_ID, 1973 .subdevice = PCI_ANY_ID, 1974 .setup = kt_serial_setup, 1975 }, 1976 { 1977 .vendor = PCI_VENDOR_ID_INTEL, 1978 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 1979 .subvendor = PCI_ANY_ID, 1980 .subdevice = PCI_ANY_ID, 1981 .setup = byt_serial_setup, 1982 }, 1983 { 1984 .vendor = PCI_VENDOR_ID_INTEL, 1985 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 1986 .subvendor = PCI_ANY_ID, 1987 .subdevice = PCI_ANY_ID, 1988 .setup = byt_serial_setup, 1989 }, 1990 { 1991 .vendor = PCI_VENDOR_ID_INTEL, 1992 .device = PCI_DEVICE_ID_INTEL_QRK_UART, 1993 .subvendor = PCI_ANY_ID, 1994 .subdevice = PCI_ANY_ID, 1995 .setup = pci_default_setup, 1996 }, 1997 { 1998 .vendor = PCI_VENDOR_ID_INTEL, 1999 .device = PCI_DEVICE_ID_INTEL_BSW_UART1, 2000 .subvendor = PCI_ANY_ID, 2001 .subdevice = PCI_ANY_ID, 2002 .setup = byt_serial_setup, 2003 }, 2004 { 2005 .vendor = PCI_VENDOR_ID_INTEL, 2006 .device = PCI_DEVICE_ID_INTEL_BSW_UART2, 2007 .subvendor = PCI_ANY_ID, 2008 .subdevice = PCI_ANY_ID, 2009 .setup = byt_serial_setup, 2010 }, 2011 /* 2012 * ITE 2013 */ 2014 { 2015 .vendor = PCI_VENDOR_ID_ITE, 2016 .device = PCI_DEVICE_ID_ITE_8872, 2017 .subvendor = PCI_ANY_ID, 2018 .subdevice = PCI_ANY_ID, 2019 .init = pci_ite887x_init, 2020 .setup = pci_default_setup, 2021 .exit = pci_ite887x_exit, 2022 }, 2023 /* 2024 * National Instruments 2025 */ 2026 { 2027 .vendor = PCI_VENDOR_ID_NI, 2028 .device = PCI_DEVICE_ID_NI_PCI23216, 2029 .subvendor = PCI_ANY_ID, 2030 .subdevice = PCI_ANY_ID, 2031 .init = pci_ni8420_init, 2032 .setup = pci_default_setup, 2033 .exit = pci_ni8420_exit, 2034 }, 2035 { 2036 .vendor = PCI_VENDOR_ID_NI, 2037 .device = PCI_DEVICE_ID_NI_PCI2328, 2038 .subvendor = PCI_ANY_ID, 2039 .subdevice = PCI_ANY_ID, 2040 .init = pci_ni8420_init, 2041 .setup = pci_default_setup, 2042 .exit = pci_ni8420_exit, 2043 }, 2044 { 2045 .vendor = PCI_VENDOR_ID_NI, 2046 .device = PCI_DEVICE_ID_NI_PCI2324, 2047 .subvendor = PCI_ANY_ID, 2048 .subdevice = PCI_ANY_ID, 2049 .init = pci_ni8420_init, 2050 .setup = pci_default_setup, 2051 .exit = pci_ni8420_exit, 2052 }, 2053 { 2054 .vendor = PCI_VENDOR_ID_NI, 2055 .device = PCI_DEVICE_ID_NI_PCI2322, 2056 .subvendor = PCI_ANY_ID, 2057 .subdevice = PCI_ANY_ID, 2058 .init = pci_ni8420_init, 2059 .setup = pci_default_setup, 2060 .exit = pci_ni8420_exit, 2061 }, 2062 { 2063 .vendor = PCI_VENDOR_ID_NI, 2064 .device = PCI_DEVICE_ID_NI_PCI2324I, 2065 .subvendor = PCI_ANY_ID, 2066 .subdevice = PCI_ANY_ID, 2067 .init = pci_ni8420_init, 2068 .setup = pci_default_setup, 2069 .exit = pci_ni8420_exit, 2070 }, 2071 { 2072 .vendor = PCI_VENDOR_ID_NI, 2073 .device = PCI_DEVICE_ID_NI_PCI2322I, 2074 .subvendor = PCI_ANY_ID, 2075 .subdevice = PCI_ANY_ID, 2076 .init = pci_ni8420_init, 2077 .setup = pci_default_setup, 2078 .exit = pci_ni8420_exit, 2079 }, 2080 { 2081 .vendor = PCI_VENDOR_ID_NI, 2082 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2083 .subvendor = PCI_ANY_ID, 2084 .subdevice = PCI_ANY_ID, 2085 .init = pci_ni8420_init, 2086 .setup = pci_default_setup, 2087 .exit = pci_ni8420_exit, 2088 }, 2089 { 2090 .vendor = PCI_VENDOR_ID_NI, 2091 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2092 .subvendor = PCI_ANY_ID, 2093 .subdevice = PCI_ANY_ID, 2094 .init = pci_ni8420_init, 2095 .setup = pci_default_setup, 2096 .exit = pci_ni8420_exit, 2097 }, 2098 { 2099 .vendor = PCI_VENDOR_ID_NI, 2100 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2101 .subvendor = PCI_ANY_ID, 2102 .subdevice = PCI_ANY_ID, 2103 .init = pci_ni8420_init, 2104 .setup = pci_default_setup, 2105 .exit = pci_ni8420_exit, 2106 }, 2107 { 2108 .vendor = PCI_VENDOR_ID_NI, 2109 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2110 .subvendor = PCI_ANY_ID, 2111 .subdevice = PCI_ANY_ID, 2112 .init = pci_ni8420_init, 2113 .setup = pci_default_setup, 2114 .exit = pci_ni8420_exit, 2115 }, 2116 { 2117 .vendor = PCI_VENDOR_ID_NI, 2118 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2119 .subvendor = PCI_ANY_ID, 2120 .subdevice = PCI_ANY_ID, 2121 .init = pci_ni8420_init, 2122 .setup = pci_default_setup, 2123 .exit = pci_ni8420_exit, 2124 }, 2125 { 2126 .vendor = PCI_VENDOR_ID_NI, 2127 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2128 .subvendor = PCI_ANY_ID, 2129 .subdevice = PCI_ANY_ID, 2130 .init = pci_ni8420_init, 2131 .setup = pci_default_setup, 2132 .exit = pci_ni8420_exit, 2133 }, 2134 { 2135 .vendor = PCI_VENDOR_ID_NI, 2136 .device = PCI_ANY_ID, 2137 .subvendor = PCI_ANY_ID, 2138 .subdevice = PCI_ANY_ID, 2139 .init = pci_ni8430_init, 2140 .setup = pci_ni8430_setup, 2141 .exit = pci_ni8430_exit, 2142 }, 2143 /* Quatech */ 2144 { 2145 .vendor = PCI_VENDOR_ID_QUATECH, 2146 .device = PCI_ANY_ID, 2147 .subvendor = PCI_ANY_ID, 2148 .subdevice = PCI_ANY_ID, 2149 .init = pci_quatech_init, 2150 .setup = pci_quatech_setup, 2151 .exit = pci_quatech_exit, 2152 }, 2153 /* 2154 * Panacom 2155 */ 2156 { 2157 .vendor = PCI_VENDOR_ID_PANACOM, 2158 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2159 .subvendor = PCI_ANY_ID, 2160 .subdevice = PCI_ANY_ID, 2161 .init = pci_plx9050_init, 2162 .setup = pci_default_setup, 2163 .exit = pci_plx9050_exit, 2164 }, 2165 { 2166 .vendor = PCI_VENDOR_ID_PANACOM, 2167 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2168 .subvendor = PCI_ANY_ID, 2169 .subdevice = PCI_ANY_ID, 2170 .init = pci_plx9050_init, 2171 .setup = pci_default_setup, 2172 .exit = pci_plx9050_exit, 2173 }, 2174 /* 2175 * Pericom 2176 */ 2177 { 2178 .vendor = 0x12d8, 2179 .device = 0x7952, 2180 .subvendor = PCI_ANY_ID, 2181 .subdevice = PCI_ANY_ID, 2182 .setup = pci_pericom_setup, 2183 }, 2184 { 2185 .vendor = 0x12d8, 2186 .device = 0x7954, 2187 .subvendor = PCI_ANY_ID, 2188 .subdevice = PCI_ANY_ID, 2189 .setup = pci_pericom_setup, 2190 }, 2191 { 2192 .vendor = 0x12d8, 2193 .device = 0x7958, 2194 .subvendor = PCI_ANY_ID, 2195 .subdevice = PCI_ANY_ID, 2196 .setup = pci_pericom_setup, 2197 }, 2198 2199 /* 2200 * PLX 2201 */ 2202 { 2203 .vendor = PCI_VENDOR_ID_PLX, 2204 .device = PCI_DEVICE_ID_PLX_9030, 2205 .subvendor = PCI_SUBVENDOR_ID_PERLE, 2206 .subdevice = PCI_ANY_ID, 2207 .setup = pci_default_setup, 2208 }, 2209 { 2210 .vendor = PCI_VENDOR_ID_PLX, 2211 .device = PCI_DEVICE_ID_PLX_9050, 2212 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2213 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2214 .init = pci_plx9050_init, 2215 .setup = pci_default_setup, 2216 .exit = pci_plx9050_exit, 2217 }, 2218 { 2219 .vendor = PCI_VENDOR_ID_PLX, 2220 .device = PCI_DEVICE_ID_PLX_9050, 2221 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2222 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2223 .init = pci_plx9050_init, 2224 .setup = pci_default_setup, 2225 .exit = pci_plx9050_exit, 2226 }, 2227 { 2228 .vendor = PCI_VENDOR_ID_PLX, 2229 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2230 .subvendor = PCI_VENDOR_ID_PLX, 2231 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2232 .init = pci_plx9050_init, 2233 .setup = pci_default_setup, 2234 .exit = pci_plx9050_exit, 2235 }, 2236 /* 2237 * SBS Technologies, Inc., PMC-OCTALPRO 232 2238 */ 2239 { 2240 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2241 .device = PCI_DEVICE_ID_OCTPRO, 2242 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2243 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2244 .init = sbs_init, 2245 .setup = sbs_setup, 2246 .exit = sbs_exit, 2247 }, 2248 /* 2249 * SBS Technologies, Inc., PMC-OCTALPRO 422 2250 */ 2251 { 2252 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2253 .device = PCI_DEVICE_ID_OCTPRO, 2254 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2255 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2256 .init = sbs_init, 2257 .setup = sbs_setup, 2258 .exit = sbs_exit, 2259 }, 2260 /* 2261 * SBS Technologies, Inc., P-Octal 232 2262 */ 2263 { 2264 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2265 .device = PCI_DEVICE_ID_OCTPRO, 2266 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2267 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2268 .init = sbs_init, 2269 .setup = sbs_setup, 2270 .exit = sbs_exit, 2271 }, 2272 /* 2273 * SBS Technologies, Inc., P-Octal 422 2274 */ 2275 { 2276 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2277 .device = PCI_DEVICE_ID_OCTPRO, 2278 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2279 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2280 .init = sbs_init, 2281 .setup = sbs_setup, 2282 .exit = sbs_exit, 2283 }, 2284 /* 2285 * SIIG cards - these may be called via parport_serial 2286 */ 2287 { 2288 .vendor = PCI_VENDOR_ID_SIIG, 2289 .device = PCI_ANY_ID, 2290 .subvendor = PCI_ANY_ID, 2291 .subdevice = PCI_ANY_ID, 2292 .init = pci_siig_init, 2293 .setup = pci_siig_setup, 2294 }, 2295 /* 2296 * Titan cards 2297 */ 2298 { 2299 .vendor = PCI_VENDOR_ID_TITAN, 2300 .device = PCI_DEVICE_ID_TITAN_400L, 2301 .subvendor = PCI_ANY_ID, 2302 .subdevice = PCI_ANY_ID, 2303 .setup = titan_400l_800l_setup, 2304 }, 2305 { 2306 .vendor = PCI_VENDOR_ID_TITAN, 2307 .device = PCI_DEVICE_ID_TITAN_800L, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .setup = titan_400l_800l_setup, 2311 }, 2312 /* 2313 * Timedia cards 2314 */ 2315 { 2316 .vendor = PCI_VENDOR_ID_TIMEDIA, 2317 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2318 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2319 .subdevice = PCI_ANY_ID, 2320 .probe = pci_timedia_probe, 2321 .init = pci_timedia_init, 2322 .setup = pci_timedia_setup, 2323 }, 2324 { 2325 .vendor = PCI_VENDOR_ID_TIMEDIA, 2326 .device = PCI_ANY_ID, 2327 .subvendor = PCI_ANY_ID, 2328 .subdevice = PCI_ANY_ID, 2329 .setup = pci_timedia_setup, 2330 }, 2331 /* 2332 * SUNIX (Timedia) cards 2333 * Do not "probe" for these cards as there is at least one combination 2334 * card that should be handled by parport_pc that doesn't match the 2335 * rule in pci_timedia_probe. 2336 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2337 * There are some boards with part number SER5037AL that report 2338 * subdevice ID 0x0002. 2339 */ 2340 { 2341 .vendor = PCI_VENDOR_ID_SUNIX, 2342 .device = PCI_DEVICE_ID_SUNIX_1999, 2343 .subvendor = PCI_VENDOR_ID_SUNIX, 2344 .subdevice = PCI_ANY_ID, 2345 .init = pci_timedia_init, 2346 .setup = pci_timedia_setup, 2347 }, 2348 /* 2349 * Exar cards 2350 */ 2351 { 2352 .vendor = PCI_VENDOR_ID_EXAR, 2353 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2354 .subvendor = PCI_ANY_ID, 2355 .subdevice = PCI_ANY_ID, 2356 .setup = pci_xr17c154_setup, 2357 }, 2358 { 2359 .vendor = PCI_VENDOR_ID_EXAR, 2360 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2361 .subvendor = PCI_ANY_ID, 2362 .subdevice = PCI_ANY_ID, 2363 .setup = pci_xr17c154_setup, 2364 }, 2365 { 2366 .vendor = PCI_VENDOR_ID_EXAR, 2367 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2368 .subvendor = PCI_ANY_ID, 2369 .subdevice = PCI_ANY_ID, 2370 .setup = pci_xr17c154_setup, 2371 }, 2372 { 2373 .vendor = PCI_VENDOR_ID_EXAR, 2374 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2375 .subvendor = PCI_ANY_ID, 2376 .subdevice = PCI_ANY_ID, 2377 .setup = pci_xr17v35x_setup, 2378 }, 2379 { 2380 .vendor = PCI_VENDOR_ID_EXAR, 2381 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2382 .subvendor = PCI_ANY_ID, 2383 .subdevice = PCI_ANY_ID, 2384 .setup = pci_xr17v35x_setup, 2385 }, 2386 { 2387 .vendor = PCI_VENDOR_ID_EXAR, 2388 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2389 .subvendor = PCI_ANY_ID, 2390 .subdevice = PCI_ANY_ID, 2391 .setup = pci_xr17v35x_setup, 2392 }, 2393 /* 2394 * Xircom cards 2395 */ 2396 { 2397 .vendor = PCI_VENDOR_ID_XIRCOM, 2398 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2399 .subvendor = PCI_ANY_ID, 2400 .subdevice = PCI_ANY_ID, 2401 .init = pci_xircom_init, 2402 .setup = pci_default_setup, 2403 }, 2404 /* 2405 * Netmos cards - these may be called via parport_serial 2406 */ 2407 { 2408 .vendor = PCI_VENDOR_ID_NETMOS, 2409 .device = PCI_ANY_ID, 2410 .subvendor = PCI_ANY_ID, 2411 .subdevice = PCI_ANY_ID, 2412 .init = pci_netmos_init, 2413 .setup = pci_netmos_9900_setup, 2414 }, 2415 /* 2416 * EndRun Technologies 2417 */ 2418 { 2419 .vendor = PCI_VENDOR_ID_ENDRUN, 2420 .device = PCI_ANY_ID, 2421 .subvendor = PCI_ANY_ID, 2422 .subdevice = PCI_ANY_ID, 2423 .init = pci_endrun_init, 2424 .setup = pci_default_setup, 2425 }, 2426 /* 2427 * For Oxford Semiconductor Tornado based devices 2428 */ 2429 { 2430 .vendor = PCI_VENDOR_ID_OXSEMI, 2431 .device = PCI_ANY_ID, 2432 .subvendor = PCI_ANY_ID, 2433 .subdevice = PCI_ANY_ID, 2434 .init = pci_oxsemi_tornado_init, 2435 .setup = pci_default_setup, 2436 }, 2437 { 2438 .vendor = PCI_VENDOR_ID_MAINPINE, 2439 .device = PCI_ANY_ID, 2440 .subvendor = PCI_ANY_ID, 2441 .subdevice = PCI_ANY_ID, 2442 .init = pci_oxsemi_tornado_init, 2443 .setup = pci_default_setup, 2444 }, 2445 { 2446 .vendor = PCI_VENDOR_ID_DIGI, 2447 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2448 .subvendor = PCI_SUBVENDOR_ID_IBM, 2449 .subdevice = PCI_ANY_ID, 2450 .init = pci_oxsemi_tornado_init, 2451 .setup = pci_default_setup, 2452 }, 2453 { 2454 .vendor = PCI_VENDOR_ID_INTEL, 2455 .device = 0x8811, 2456 .subvendor = PCI_ANY_ID, 2457 .subdevice = PCI_ANY_ID, 2458 .init = pci_eg20t_init, 2459 .setup = pci_default_setup, 2460 }, 2461 { 2462 .vendor = PCI_VENDOR_ID_INTEL, 2463 .device = 0x8812, 2464 .subvendor = PCI_ANY_ID, 2465 .subdevice = PCI_ANY_ID, 2466 .init = pci_eg20t_init, 2467 .setup = pci_default_setup, 2468 }, 2469 { 2470 .vendor = PCI_VENDOR_ID_INTEL, 2471 .device = 0x8813, 2472 .subvendor = PCI_ANY_ID, 2473 .subdevice = PCI_ANY_ID, 2474 .init = pci_eg20t_init, 2475 .setup = pci_default_setup, 2476 }, 2477 { 2478 .vendor = PCI_VENDOR_ID_INTEL, 2479 .device = 0x8814, 2480 .subvendor = PCI_ANY_ID, 2481 .subdevice = PCI_ANY_ID, 2482 .init = pci_eg20t_init, 2483 .setup = pci_default_setup, 2484 }, 2485 { 2486 .vendor = 0x10DB, 2487 .device = 0x8027, 2488 .subvendor = PCI_ANY_ID, 2489 .subdevice = PCI_ANY_ID, 2490 .init = pci_eg20t_init, 2491 .setup = pci_default_setup, 2492 }, 2493 { 2494 .vendor = 0x10DB, 2495 .device = 0x8028, 2496 .subvendor = PCI_ANY_ID, 2497 .subdevice = PCI_ANY_ID, 2498 .init = pci_eg20t_init, 2499 .setup = pci_default_setup, 2500 }, 2501 { 2502 .vendor = 0x10DB, 2503 .device = 0x8029, 2504 .subvendor = PCI_ANY_ID, 2505 .subdevice = PCI_ANY_ID, 2506 .init = pci_eg20t_init, 2507 .setup = pci_default_setup, 2508 }, 2509 { 2510 .vendor = 0x10DB, 2511 .device = 0x800C, 2512 .subvendor = PCI_ANY_ID, 2513 .subdevice = PCI_ANY_ID, 2514 .init = pci_eg20t_init, 2515 .setup = pci_default_setup, 2516 }, 2517 { 2518 .vendor = 0x10DB, 2519 .device = 0x800D, 2520 .subvendor = PCI_ANY_ID, 2521 .subdevice = PCI_ANY_ID, 2522 .init = pci_eg20t_init, 2523 .setup = pci_default_setup, 2524 }, 2525 /* 2526 * Cronyx Omega PCI (PLX-chip based) 2527 */ 2528 { 2529 .vendor = PCI_VENDOR_ID_PLX, 2530 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2531 .subvendor = PCI_ANY_ID, 2532 .subdevice = PCI_ANY_ID, 2533 .setup = pci_omegapci_setup, 2534 }, 2535 /* WCH CH353 1S1P card (16550 clone) */ 2536 { 2537 .vendor = PCI_VENDOR_ID_WCH, 2538 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2539 .subvendor = PCI_ANY_ID, 2540 .subdevice = PCI_ANY_ID, 2541 .setup = pci_wch_ch353_setup, 2542 }, 2543 /* WCH CH353 2S1P card (16550 clone) */ 2544 { 2545 .vendor = PCI_VENDOR_ID_WCH, 2546 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2547 .subvendor = PCI_ANY_ID, 2548 .subdevice = PCI_ANY_ID, 2549 .setup = pci_wch_ch353_setup, 2550 }, 2551 /* WCH CH353 4S card (16550 clone) */ 2552 { 2553 .vendor = PCI_VENDOR_ID_WCH, 2554 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2555 .subvendor = PCI_ANY_ID, 2556 .subdevice = PCI_ANY_ID, 2557 .setup = pci_wch_ch353_setup, 2558 }, 2559 /* WCH CH353 2S1PF card (16550 clone) */ 2560 { 2561 .vendor = PCI_VENDOR_ID_WCH, 2562 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2563 .subvendor = PCI_ANY_ID, 2564 .subdevice = PCI_ANY_ID, 2565 .setup = pci_wch_ch353_setup, 2566 }, 2567 /* WCH CH352 2S card (16550 clone) */ 2568 { 2569 .vendor = PCI_VENDOR_ID_WCH, 2570 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2571 .subvendor = PCI_ANY_ID, 2572 .subdevice = PCI_ANY_ID, 2573 .setup = pci_wch_ch353_setup, 2574 }, 2575 /* WCH CH382 2S1P card (16850 clone) */ 2576 { 2577 .vendor = PCIE_VENDOR_ID_WCH, 2578 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2579 .subvendor = PCI_ANY_ID, 2580 .subdevice = PCI_ANY_ID, 2581 .setup = pci_wch_ch38x_setup, 2582 }, 2583 /* WCH CH384 4S card (16850 clone) */ 2584 { 2585 .vendor = PCIE_VENDOR_ID_WCH, 2586 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2587 .subvendor = PCI_ANY_ID, 2588 .subdevice = PCI_ANY_ID, 2589 .setup = pci_wch_ch38x_setup, 2590 }, 2591 /* 2592 * ASIX devices with FIFO bug 2593 */ 2594 { 2595 .vendor = PCI_VENDOR_ID_ASIX, 2596 .device = PCI_ANY_ID, 2597 .subvendor = PCI_ANY_ID, 2598 .subdevice = PCI_ANY_ID, 2599 .setup = pci_asix_setup, 2600 }, 2601 /* 2602 * Commtech, Inc. Fastcom adapters 2603 * 2604 */ 2605 { 2606 .vendor = PCI_VENDOR_ID_COMMTECH, 2607 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2608 .subvendor = PCI_ANY_ID, 2609 .subdevice = PCI_ANY_ID, 2610 .setup = pci_fastcom335_setup, 2611 }, 2612 { 2613 .vendor = PCI_VENDOR_ID_COMMTECH, 2614 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2615 .subvendor = PCI_ANY_ID, 2616 .subdevice = PCI_ANY_ID, 2617 .setup = pci_fastcom335_setup, 2618 }, 2619 { 2620 .vendor = PCI_VENDOR_ID_COMMTECH, 2621 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2622 .subvendor = PCI_ANY_ID, 2623 .subdevice = PCI_ANY_ID, 2624 .setup = pci_fastcom335_setup, 2625 }, 2626 { 2627 .vendor = PCI_VENDOR_ID_COMMTECH, 2628 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2629 .subvendor = PCI_ANY_ID, 2630 .subdevice = PCI_ANY_ID, 2631 .setup = pci_fastcom335_setup, 2632 }, 2633 { 2634 .vendor = PCI_VENDOR_ID_COMMTECH, 2635 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2636 .subvendor = PCI_ANY_ID, 2637 .subdevice = PCI_ANY_ID, 2638 .setup = pci_xr17v35x_setup, 2639 }, 2640 { 2641 .vendor = PCI_VENDOR_ID_COMMTECH, 2642 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2643 .subvendor = PCI_ANY_ID, 2644 .subdevice = PCI_ANY_ID, 2645 .setup = pci_xr17v35x_setup, 2646 }, 2647 { 2648 .vendor = PCI_VENDOR_ID_COMMTECH, 2649 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2650 .subvendor = PCI_ANY_ID, 2651 .subdevice = PCI_ANY_ID, 2652 .setup = pci_xr17v35x_setup, 2653 }, 2654 /* 2655 * Broadcom TruManage (NetXtreme) 2656 */ 2657 { 2658 .vendor = PCI_VENDOR_ID_BROADCOM, 2659 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2660 .subvendor = PCI_ANY_ID, 2661 .subdevice = PCI_ANY_ID, 2662 .setup = pci_brcm_trumanage_setup, 2663 }, 2664 { 2665 .vendor = 0x1c29, 2666 .device = 0x1104, 2667 .subvendor = PCI_ANY_ID, 2668 .subdevice = PCI_ANY_ID, 2669 .setup = pci_fintek_setup, 2670 }, 2671 { 2672 .vendor = 0x1c29, 2673 .device = 0x1108, 2674 .subvendor = PCI_ANY_ID, 2675 .subdevice = PCI_ANY_ID, 2676 .setup = pci_fintek_setup, 2677 }, 2678 { 2679 .vendor = 0x1c29, 2680 .device = 0x1112, 2681 .subvendor = PCI_ANY_ID, 2682 .subdevice = PCI_ANY_ID, 2683 .setup = pci_fintek_setup, 2684 }, 2685 2686 /* 2687 * Default "match everything" terminator entry 2688 */ 2689 { 2690 .vendor = PCI_ANY_ID, 2691 .device = PCI_ANY_ID, 2692 .subvendor = PCI_ANY_ID, 2693 .subdevice = PCI_ANY_ID, 2694 .setup = pci_default_setup, 2695 } 2696 }; 2697 2698 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2699 { 2700 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2701 } 2702 2703 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2704 { 2705 struct pci_serial_quirk *quirk; 2706 2707 for (quirk = pci_serial_quirks; ; quirk++) 2708 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2709 quirk_id_matches(quirk->device, dev->device) && 2710 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2711 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2712 break; 2713 return quirk; 2714 } 2715 2716 static inline int get_pci_irq(struct pci_dev *dev, 2717 const struct pciserial_board *board) 2718 { 2719 if (board->flags & FL_NOIRQ) 2720 return 0; 2721 else 2722 return dev->irq; 2723 } 2724 2725 /* 2726 * This is the configuration table for all of the PCI serial boards 2727 * which we support. It is directly indexed by the pci_board_num_t enum 2728 * value, which is encoded in the pci_device_id PCI probe table's 2729 * driver_data member. 2730 * 2731 * The makeup of these names are: 2732 * pbn_bn{_bt}_n_baud{_offsetinhex} 2733 * 2734 * bn = PCI BAR number 2735 * bt = Index using PCI BARs 2736 * n = number of serial ports 2737 * baud = baud rate 2738 * offsetinhex = offset for each sequential port (in hex) 2739 * 2740 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2741 * 2742 * Please note: in theory if n = 1, _bt infix should make no difference. 2743 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2744 */ 2745 enum pci_board_num_t { 2746 pbn_default = 0, 2747 2748 pbn_b0_1_115200, 2749 pbn_b0_2_115200, 2750 pbn_b0_4_115200, 2751 pbn_b0_5_115200, 2752 pbn_b0_8_115200, 2753 2754 pbn_b0_1_921600, 2755 pbn_b0_2_921600, 2756 pbn_b0_4_921600, 2757 2758 pbn_b0_2_1130000, 2759 2760 pbn_b0_4_1152000, 2761 2762 pbn_b0_2_1152000_200, 2763 pbn_b0_4_1152000_200, 2764 pbn_b0_8_1152000_200, 2765 2766 pbn_b0_2_1843200, 2767 pbn_b0_4_1843200, 2768 2769 pbn_b0_2_1843200_200, 2770 pbn_b0_4_1843200_200, 2771 pbn_b0_8_1843200_200, 2772 2773 pbn_b0_1_4000000, 2774 2775 pbn_b0_bt_1_115200, 2776 pbn_b0_bt_2_115200, 2777 pbn_b0_bt_4_115200, 2778 pbn_b0_bt_8_115200, 2779 2780 pbn_b0_bt_1_460800, 2781 pbn_b0_bt_2_460800, 2782 pbn_b0_bt_4_460800, 2783 2784 pbn_b0_bt_1_921600, 2785 pbn_b0_bt_2_921600, 2786 pbn_b0_bt_4_921600, 2787 pbn_b0_bt_8_921600, 2788 2789 pbn_b1_1_115200, 2790 pbn_b1_2_115200, 2791 pbn_b1_4_115200, 2792 pbn_b1_8_115200, 2793 pbn_b1_16_115200, 2794 2795 pbn_b1_1_921600, 2796 pbn_b1_2_921600, 2797 pbn_b1_4_921600, 2798 pbn_b1_8_921600, 2799 2800 pbn_b1_2_1250000, 2801 2802 pbn_b1_bt_1_115200, 2803 pbn_b1_bt_2_115200, 2804 pbn_b1_bt_4_115200, 2805 2806 pbn_b1_bt_2_921600, 2807 2808 pbn_b1_1_1382400, 2809 pbn_b1_2_1382400, 2810 pbn_b1_4_1382400, 2811 pbn_b1_8_1382400, 2812 2813 pbn_b2_1_115200, 2814 pbn_b2_2_115200, 2815 pbn_b2_4_115200, 2816 pbn_b2_8_115200, 2817 2818 pbn_b2_1_460800, 2819 pbn_b2_4_460800, 2820 pbn_b2_8_460800, 2821 pbn_b2_16_460800, 2822 2823 pbn_b2_1_921600, 2824 pbn_b2_4_921600, 2825 pbn_b2_8_921600, 2826 2827 pbn_b2_8_1152000, 2828 2829 pbn_b2_bt_1_115200, 2830 pbn_b2_bt_2_115200, 2831 pbn_b2_bt_4_115200, 2832 2833 pbn_b2_bt_2_921600, 2834 pbn_b2_bt_4_921600, 2835 2836 pbn_b3_2_115200, 2837 pbn_b3_4_115200, 2838 pbn_b3_8_115200, 2839 2840 pbn_b4_bt_2_921600, 2841 pbn_b4_bt_4_921600, 2842 pbn_b4_bt_8_921600, 2843 2844 /* 2845 * Board-specific versions. 2846 */ 2847 pbn_panacom, 2848 pbn_panacom2, 2849 pbn_panacom4, 2850 pbn_plx_romulus, 2851 pbn_endrun_2_4000000, 2852 pbn_oxsemi, 2853 pbn_oxsemi_1_4000000, 2854 pbn_oxsemi_2_4000000, 2855 pbn_oxsemi_4_4000000, 2856 pbn_oxsemi_8_4000000, 2857 pbn_intel_i960, 2858 pbn_sgi_ioc3, 2859 pbn_computone_4, 2860 pbn_computone_6, 2861 pbn_computone_8, 2862 pbn_sbsxrsio, 2863 pbn_exar_XR17C152, 2864 pbn_exar_XR17C154, 2865 pbn_exar_XR17C158, 2866 pbn_exar_XR17V352, 2867 pbn_exar_XR17V354, 2868 pbn_exar_XR17V358, 2869 pbn_exar_ibm_saturn, 2870 pbn_pasemi_1682M, 2871 pbn_ni8430_2, 2872 pbn_ni8430_4, 2873 pbn_ni8430_8, 2874 pbn_ni8430_16, 2875 pbn_ADDIDATA_PCIe_1_3906250, 2876 pbn_ADDIDATA_PCIe_2_3906250, 2877 pbn_ADDIDATA_PCIe_4_3906250, 2878 pbn_ADDIDATA_PCIe_8_3906250, 2879 pbn_ce4100_1_115200, 2880 pbn_byt, 2881 pbn_qrk, 2882 pbn_omegapci, 2883 pbn_NETMOS9900_2s_115200, 2884 pbn_brcm_trumanage, 2885 pbn_fintek_4, 2886 pbn_fintek_8, 2887 pbn_fintek_12, 2888 pbn_wch384_4, 2889 }; 2890 2891 /* 2892 * uart_offset - the space between channels 2893 * reg_shift - describes how the UART registers are mapped 2894 * to PCI memory by the card. 2895 * For example IER register on SBS, Inc. PMC-OctPro is located at 2896 * offset 0x10 from the UART base, while UART_IER is defined as 1 2897 * in include/linux/serial_reg.h, 2898 * see first lines of serial_in() and serial_out() in 8250.c 2899 */ 2900 2901 static struct pciserial_board pci_boards[] = { 2902 [pbn_default] = { 2903 .flags = FL_BASE0, 2904 .num_ports = 1, 2905 .base_baud = 115200, 2906 .uart_offset = 8, 2907 }, 2908 [pbn_b0_1_115200] = { 2909 .flags = FL_BASE0, 2910 .num_ports = 1, 2911 .base_baud = 115200, 2912 .uart_offset = 8, 2913 }, 2914 [pbn_b0_2_115200] = { 2915 .flags = FL_BASE0, 2916 .num_ports = 2, 2917 .base_baud = 115200, 2918 .uart_offset = 8, 2919 }, 2920 [pbn_b0_4_115200] = { 2921 .flags = FL_BASE0, 2922 .num_ports = 4, 2923 .base_baud = 115200, 2924 .uart_offset = 8, 2925 }, 2926 [pbn_b0_5_115200] = { 2927 .flags = FL_BASE0, 2928 .num_ports = 5, 2929 .base_baud = 115200, 2930 .uart_offset = 8, 2931 }, 2932 [pbn_b0_8_115200] = { 2933 .flags = FL_BASE0, 2934 .num_ports = 8, 2935 .base_baud = 115200, 2936 .uart_offset = 8, 2937 }, 2938 [pbn_b0_1_921600] = { 2939 .flags = FL_BASE0, 2940 .num_ports = 1, 2941 .base_baud = 921600, 2942 .uart_offset = 8, 2943 }, 2944 [pbn_b0_2_921600] = { 2945 .flags = FL_BASE0, 2946 .num_ports = 2, 2947 .base_baud = 921600, 2948 .uart_offset = 8, 2949 }, 2950 [pbn_b0_4_921600] = { 2951 .flags = FL_BASE0, 2952 .num_ports = 4, 2953 .base_baud = 921600, 2954 .uart_offset = 8, 2955 }, 2956 2957 [pbn_b0_2_1130000] = { 2958 .flags = FL_BASE0, 2959 .num_ports = 2, 2960 .base_baud = 1130000, 2961 .uart_offset = 8, 2962 }, 2963 2964 [pbn_b0_4_1152000] = { 2965 .flags = FL_BASE0, 2966 .num_ports = 4, 2967 .base_baud = 1152000, 2968 .uart_offset = 8, 2969 }, 2970 2971 [pbn_b0_2_1152000_200] = { 2972 .flags = FL_BASE0, 2973 .num_ports = 2, 2974 .base_baud = 1152000, 2975 .uart_offset = 0x200, 2976 }, 2977 2978 [pbn_b0_4_1152000_200] = { 2979 .flags = FL_BASE0, 2980 .num_ports = 4, 2981 .base_baud = 1152000, 2982 .uart_offset = 0x200, 2983 }, 2984 2985 [pbn_b0_8_1152000_200] = { 2986 .flags = FL_BASE0, 2987 .num_ports = 8, 2988 .base_baud = 1152000, 2989 .uart_offset = 0x200, 2990 }, 2991 2992 [pbn_b0_2_1843200] = { 2993 .flags = FL_BASE0, 2994 .num_ports = 2, 2995 .base_baud = 1843200, 2996 .uart_offset = 8, 2997 }, 2998 [pbn_b0_4_1843200] = { 2999 .flags = FL_BASE0, 3000 .num_ports = 4, 3001 .base_baud = 1843200, 3002 .uart_offset = 8, 3003 }, 3004 3005 [pbn_b0_2_1843200_200] = { 3006 .flags = FL_BASE0, 3007 .num_ports = 2, 3008 .base_baud = 1843200, 3009 .uart_offset = 0x200, 3010 }, 3011 [pbn_b0_4_1843200_200] = { 3012 .flags = FL_BASE0, 3013 .num_ports = 4, 3014 .base_baud = 1843200, 3015 .uart_offset = 0x200, 3016 }, 3017 [pbn_b0_8_1843200_200] = { 3018 .flags = FL_BASE0, 3019 .num_ports = 8, 3020 .base_baud = 1843200, 3021 .uart_offset = 0x200, 3022 }, 3023 [pbn_b0_1_4000000] = { 3024 .flags = FL_BASE0, 3025 .num_ports = 1, 3026 .base_baud = 4000000, 3027 .uart_offset = 8, 3028 }, 3029 3030 [pbn_b0_bt_1_115200] = { 3031 .flags = FL_BASE0|FL_BASE_BARS, 3032 .num_ports = 1, 3033 .base_baud = 115200, 3034 .uart_offset = 8, 3035 }, 3036 [pbn_b0_bt_2_115200] = { 3037 .flags = FL_BASE0|FL_BASE_BARS, 3038 .num_ports = 2, 3039 .base_baud = 115200, 3040 .uart_offset = 8, 3041 }, 3042 [pbn_b0_bt_4_115200] = { 3043 .flags = FL_BASE0|FL_BASE_BARS, 3044 .num_ports = 4, 3045 .base_baud = 115200, 3046 .uart_offset = 8, 3047 }, 3048 [pbn_b0_bt_8_115200] = { 3049 .flags = FL_BASE0|FL_BASE_BARS, 3050 .num_ports = 8, 3051 .base_baud = 115200, 3052 .uart_offset = 8, 3053 }, 3054 3055 [pbn_b0_bt_1_460800] = { 3056 .flags = FL_BASE0|FL_BASE_BARS, 3057 .num_ports = 1, 3058 .base_baud = 460800, 3059 .uart_offset = 8, 3060 }, 3061 [pbn_b0_bt_2_460800] = { 3062 .flags = FL_BASE0|FL_BASE_BARS, 3063 .num_ports = 2, 3064 .base_baud = 460800, 3065 .uart_offset = 8, 3066 }, 3067 [pbn_b0_bt_4_460800] = { 3068 .flags = FL_BASE0|FL_BASE_BARS, 3069 .num_ports = 4, 3070 .base_baud = 460800, 3071 .uart_offset = 8, 3072 }, 3073 3074 [pbn_b0_bt_1_921600] = { 3075 .flags = FL_BASE0|FL_BASE_BARS, 3076 .num_ports = 1, 3077 .base_baud = 921600, 3078 .uart_offset = 8, 3079 }, 3080 [pbn_b0_bt_2_921600] = { 3081 .flags = FL_BASE0|FL_BASE_BARS, 3082 .num_ports = 2, 3083 .base_baud = 921600, 3084 .uart_offset = 8, 3085 }, 3086 [pbn_b0_bt_4_921600] = { 3087 .flags = FL_BASE0|FL_BASE_BARS, 3088 .num_ports = 4, 3089 .base_baud = 921600, 3090 .uart_offset = 8, 3091 }, 3092 [pbn_b0_bt_8_921600] = { 3093 .flags = FL_BASE0|FL_BASE_BARS, 3094 .num_ports = 8, 3095 .base_baud = 921600, 3096 .uart_offset = 8, 3097 }, 3098 3099 [pbn_b1_1_115200] = { 3100 .flags = FL_BASE1, 3101 .num_ports = 1, 3102 .base_baud = 115200, 3103 .uart_offset = 8, 3104 }, 3105 [pbn_b1_2_115200] = { 3106 .flags = FL_BASE1, 3107 .num_ports = 2, 3108 .base_baud = 115200, 3109 .uart_offset = 8, 3110 }, 3111 [pbn_b1_4_115200] = { 3112 .flags = FL_BASE1, 3113 .num_ports = 4, 3114 .base_baud = 115200, 3115 .uart_offset = 8, 3116 }, 3117 [pbn_b1_8_115200] = { 3118 .flags = FL_BASE1, 3119 .num_ports = 8, 3120 .base_baud = 115200, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b1_16_115200] = { 3124 .flags = FL_BASE1, 3125 .num_ports = 16, 3126 .base_baud = 115200, 3127 .uart_offset = 8, 3128 }, 3129 3130 [pbn_b1_1_921600] = { 3131 .flags = FL_BASE1, 3132 .num_ports = 1, 3133 .base_baud = 921600, 3134 .uart_offset = 8, 3135 }, 3136 [pbn_b1_2_921600] = { 3137 .flags = FL_BASE1, 3138 .num_ports = 2, 3139 .base_baud = 921600, 3140 .uart_offset = 8, 3141 }, 3142 [pbn_b1_4_921600] = { 3143 .flags = FL_BASE1, 3144 .num_ports = 4, 3145 .base_baud = 921600, 3146 .uart_offset = 8, 3147 }, 3148 [pbn_b1_8_921600] = { 3149 .flags = FL_BASE1, 3150 .num_ports = 8, 3151 .base_baud = 921600, 3152 .uart_offset = 8, 3153 }, 3154 [pbn_b1_2_1250000] = { 3155 .flags = FL_BASE1, 3156 .num_ports = 2, 3157 .base_baud = 1250000, 3158 .uart_offset = 8, 3159 }, 3160 3161 [pbn_b1_bt_1_115200] = { 3162 .flags = FL_BASE1|FL_BASE_BARS, 3163 .num_ports = 1, 3164 .base_baud = 115200, 3165 .uart_offset = 8, 3166 }, 3167 [pbn_b1_bt_2_115200] = { 3168 .flags = FL_BASE1|FL_BASE_BARS, 3169 .num_ports = 2, 3170 .base_baud = 115200, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b1_bt_4_115200] = { 3174 .flags = FL_BASE1|FL_BASE_BARS, 3175 .num_ports = 4, 3176 .base_baud = 115200, 3177 .uart_offset = 8, 3178 }, 3179 3180 [pbn_b1_bt_2_921600] = { 3181 .flags = FL_BASE1|FL_BASE_BARS, 3182 .num_ports = 2, 3183 .base_baud = 921600, 3184 .uart_offset = 8, 3185 }, 3186 3187 [pbn_b1_1_1382400] = { 3188 .flags = FL_BASE1, 3189 .num_ports = 1, 3190 .base_baud = 1382400, 3191 .uart_offset = 8, 3192 }, 3193 [pbn_b1_2_1382400] = { 3194 .flags = FL_BASE1, 3195 .num_ports = 2, 3196 .base_baud = 1382400, 3197 .uart_offset = 8, 3198 }, 3199 [pbn_b1_4_1382400] = { 3200 .flags = FL_BASE1, 3201 .num_ports = 4, 3202 .base_baud = 1382400, 3203 .uart_offset = 8, 3204 }, 3205 [pbn_b1_8_1382400] = { 3206 .flags = FL_BASE1, 3207 .num_ports = 8, 3208 .base_baud = 1382400, 3209 .uart_offset = 8, 3210 }, 3211 3212 [pbn_b2_1_115200] = { 3213 .flags = FL_BASE2, 3214 .num_ports = 1, 3215 .base_baud = 115200, 3216 .uart_offset = 8, 3217 }, 3218 [pbn_b2_2_115200] = { 3219 .flags = FL_BASE2, 3220 .num_ports = 2, 3221 .base_baud = 115200, 3222 .uart_offset = 8, 3223 }, 3224 [pbn_b2_4_115200] = { 3225 .flags = FL_BASE2, 3226 .num_ports = 4, 3227 .base_baud = 115200, 3228 .uart_offset = 8, 3229 }, 3230 [pbn_b2_8_115200] = { 3231 .flags = FL_BASE2, 3232 .num_ports = 8, 3233 .base_baud = 115200, 3234 .uart_offset = 8, 3235 }, 3236 3237 [pbn_b2_1_460800] = { 3238 .flags = FL_BASE2, 3239 .num_ports = 1, 3240 .base_baud = 460800, 3241 .uart_offset = 8, 3242 }, 3243 [pbn_b2_4_460800] = { 3244 .flags = FL_BASE2, 3245 .num_ports = 4, 3246 .base_baud = 460800, 3247 .uart_offset = 8, 3248 }, 3249 [pbn_b2_8_460800] = { 3250 .flags = FL_BASE2, 3251 .num_ports = 8, 3252 .base_baud = 460800, 3253 .uart_offset = 8, 3254 }, 3255 [pbn_b2_16_460800] = { 3256 .flags = FL_BASE2, 3257 .num_ports = 16, 3258 .base_baud = 460800, 3259 .uart_offset = 8, 3260 }, 3261 3262 [pbn_b2_1_921600] = { 3263 .flags = FL_BASE2, 3264 .num_ports = 1, 3265 .base_baud = 921600, 3266 .uart_offset = 8, 3267 }, 3268 [pbn_b2_4_921600] = { 3269 .flags = FL_BASE2, 3270 .num_ports = 4, 3271 .base_baud = 921600, 3272 .uart_offset = 8, 3273 }, 3274 [pbn_b2_8_921600] = { 3275 .flags = FL_BASE2, 3276 .num_ports = 8, 3277 .base_baud = 921600, 3278 .uart_offset = 8, 3279 }, 3280 3281 [pbn_b2_8_1152000] = { 3282 .flags = FL_BASE2, 3283 .num_ports = 8, 3284 .base_baud = 1152000, 3285 .uart_offset = 8, 3286 }, 3287 3288 [pbn_b2_bt_1_115200] = { 3289 .flags = FL_BASE2|FL_BASE_BARS, 3290 .num_ports = 1, 3291 .base_baud = 115200, 3292 .uart_offset = 8, 3293 }, 3294 [pbn_b2_bt_2_115200] = { 3295 .flags = FL_BASE2|FL_BASE_BARS, 3296 .num_ports = 2, 3297 .base_baud = 115200, 3298 .uart_offset = 8, 3299 }, 3300 [pbn_b2_bt_4_115200] = { 3301 .flags = FL_BASE2|FL_BASE_BARS, 3302 .num_ports = 4, 3303 .base_baud = 115200, 3304 .uart_offset = 8, 3305 }, 3306 3307 [pbn_b2_bt_2_921600] = { 3308 .flags = FL_BASE2|FL_BASE_BARS, 3309 .num_ports = 2, 3310 .base_baud = 921600, 3311 .uart_offset = 8, 3312 }, 3313 [pbn_b2_bt_4_921600] = { 3314 .flags = FL_BASE2|FL_BASE_BARS, 3315 .num_ports = 4, 3316 .base_baud = 921600, 3317 .uart_offset = 8, 3318 }, 3319 3320 [pbn_b3_2_115200] = { 3321 .flags = FL_BASE3, 3322 .num_ports = 2, 3323 .base_baud = 115200, 3324 .uart_offset = 8, 3325 }, 3326 [pbn_b3_4_115200] = { 3327 .flags = FL_BASE3, 3328 .num_ports = 4, 3329 .base_baud = 115200, 3330 .uart_offset = 8, 3331 }, 3332 [pbn_b3_8_115200] = { 3333 .flags = FL_BASE3, 3334 .num_ports = 8, 3335 .base_baud = 115200, 3336 .uart_offset = 8, 3337 }, 3338 3339 [pbn_b4_bt_2_921600] = { 3340 .flags = FL_BASE4, 3341 .num_ports = 2, 3342 .base_baud = 921600, 3343 .uart_offset = 8, 3344 }, 3345 [pbn_b4_bt_4_921600] = { 3346 .flags = FL_BASE4, 3347 .num_ports = 4, 3348 .base_baud = 921600, 3349 .uart_offset = 8, 3350 }, 3351 [pbn_b4_bt_8_921600] = { 3352 .flags = FL_BASE4, 3353 .num_ports = 8, 3354 .base_baud = 921600, 3355 .uart_offset = 8, 3356 }, 3357 3358 /* 3359 * Entries following this are board-specific. 3360 */ 3361 3362 /* 3363 * Panacom - IOMEM 3364 */ 3365 [pbn_panacom] = { 3366 .flags = FL_BASE2, 3367 .num_ports = 2, 3368 .base_baud = 921600, 3369 .uart_offset = 0x400, 3370 .reg_shift = 7, 3371 }, 3372 [pbn_panacom2] = { 3373 .flags = FL_BASE2|FL_BASE_BARS, 3374 .num_ports = 2, 3375 .base_baud = 921600, 3376 .uart_offset = 0x400, 3377 .reg_shift = 7, 3378 }, 3379 [pbn_panacom4] = { 3380 .flags = FL_BASE2|FL_BASE_BARS, 3381 .num_ports = 4, 3382 .base_baud = 921600, 3383 .uart_offset = 0x400, 3384 .reg_shift = 7, 3385 }, 3386 3387 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3388 [pbn_plx_romulus] = { 3389 .flags = FL_BASE2, 3390 .num_ports = 4, 3391 .base_baud = 921600, 3392 .uart_offset = 8 << 2, 3393 .reg_shift = 2, 3394 .first_offset = 0x03, 3395 }, 3396 3397 /* 3398 * EndRun Technologies 3399 * Uses the size of PCI Base region 0 to 3400 * signal now many ports are available 3401 * 2 port 952 Uart support 3402 */ 3403 [pbn_endrun_2_4000000] = { 3404 .flags = FL_BASE0, 3405 .num_ports = 2, 3406 .base_baud = 4000000, 3407 .uart_offset = 0x200, 3408 .first_offset = 0x1000, 3409 }, 3410 3411 /* 3412 * This board uses the size of PCI Base region 0 to 3413 * signal now many ports are available 3414 */ 3415 [pbn_oxsemi] = { 3416 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3417 .num_ports = 32, 3418 .base_baud = 115200, 3419 .uart_offset = 8, 3420 }, 3421 [pbn_oxsemi_1_4000000] = { 3422 .flags = FL_BASE0, 3423 .num_ports = 1, 3424 .base_baud = 4000000, 3425 .uart_offset = 0x200, 3426 .first_offset = 0x1000, 3427 }, 3428 [pbn_oxsemi_2_4000000] = { 3429 .flags = FL_BASE0, 3430 .num_ports = 2, 3431 .base_baud = 4000000, 3432 .uart_offset = 0x200, 3433 .first_offset = 0x1000, 3434 }, 3435 [pbn_oxsemi_4_4000000] = { 3436 .flags = FL_BASE0, 3437 .num_ports = 4, 3438 .base_baud = 4000000, 3439 .uart_offset = 0x200, 3440 .first_offset = 0x1000, 3441 }, 3442 [pbn_oxsemi_8_4000000] = { 3443 .flags = FL_BASE0, 3444 .num_ports = 8, 3445 .base_baud = 4000000, 3446 .uart_offset = 0x200, 3447 .first_offset = 0x1000, 3448 }, 3449 3450 3451 /* 3452 * EKF addition for i960 Boards form EKF with serial port. 3453 * Max 256 ports. 3454 */ 3455 [pbn_intel_i960] = { 3456 .flags = FL_BASE0, 3457 .num_ports = 32, 3458 .base_baud = 921600, 3459 .uart_offset = 8 << 2, 3460 .reg_shift = 2, 3461 .first_offset = 0x10000, 3462 }, 3463 [pbn_sgi_ioc3] = { 3464 .flags = FL_BASE0|FL_NOIRQ, 3465 .num_ports = 1, 3466 .base_baud = 458333, 3467 .uart_offset = 8, 3468 .reg_shift = 0, 3469 .first_offset = 0x20178, 3470 }, 3471 3472 /* 3473 * Computone - uses IOMEM. 3474 */ 3475 [pbn_computone_4] = { 3476 .flags = FL_BASE0, 3477 .num_ports = 4, 3478 .base_baud = 921600, 3479 .uart_offset = 0x40, 3480 .reg_shift = 2, 3481 .first_offset = 0x200, 3482 }, 3483 [pbn_computone_6] = { 3484 .flags = FL_BASE0, 3485 .num_ports = 6, 3486 .base_baud = 921600, 3487 .uart_offset = 0x40, 3488 .reg_shift = 2, 3489 .first_offset = 0x200, 3490 }, 3491 [pbn_computone_8] = { 3492 .flags = FL_BASE0, 3493 .num_ports = 8, 3494 .base_baud = 921600, 3495 .uart_offset = 0x40, 3496 .reg_shift = 2, 3497 .first_offset = 0x200, 3498 }, 3499 [pbn_sbsxrsio] = { 3500 .flags = FL_BASE0, 3501 .num_ports = 8, 3502 .base_baud = 460800, 3503 .uart_offset = 256, 3504 .reg_shift = 4, 3505 }, 3506 /* 3507 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3508 * Only basic 16550A support. 3509 * XR17C15[24] are not tested, but they should work. 3510 */ 3511 [pbn_exar_XR17C152] = { 3512 .flags = FL_BASE0, 3513 .num_ports = 2, 3514 .base_baud = 921600, 3515 .uart_offset = 0x200, 3516 }, 3517 [pbn_exar_XR17C154] = { 3518 .flags = FL_BASE0, 3519 .num_ports = 4, 3520 .base_baud = 921600, 3521 .uart_offset = 0x200, 3522 }, 3523 [pbn_exar_XR17C158] = { 3524 .flags = FL_BASE0, 3525 .num_ports = 8, 3526 .base_baud = 921600, 3527 .uart_offset = 0x200, 3528 }, 3529 [pbn_exar_XR17V352] = { 3530 .flags = FL_BASE0, 3531 .num_ports = 2, 3532 .base_baud = 7812500, 3533 .uart_offset = 0x400, 3534 .reg_shift = 0, 3535 .first_offset = 0, 3536 }, 3537 [pbn_exar_XR17V354] = { 3538 .flags = FL_BASE0, 3539 .num_ports = 4, 3540 .base_baud = 7812500, 3541 .uart_offset = 0x400, 3542 .reg_shift = 0, 3543 .first_offset = 0, 3544 }, 3545 [pbn_exar_XR17V358] = { 3546 .flags = FL_BASE0, 3547 .num_ports = 8, 3548 .base_baud = 7812500, 3549 .uart_offset = 0x400, 3550 .reg_shift = 0, 3551 .first_offset = 0, 3552 }, 3553 [pbn_exar_ibm_saturn] = { 3554 .flags = FL_BASE0, 3555 .num_ports = 1, 3556 .base_baud = 921600, 3557 .uart_offset = 0x200, 3558 }, 3559 3560 /* 3561 * PA Semi PWRficient PA6T-1682M on-chip UART 3562 */ 3563 [pbn_pasemi_1682M] = { 3564 .flags = FL_BASE0, 3565 .num_ports = 1, 3566 .base_baud = 8333333, 3567 }, 3568 /* 3569 * National Instruments 843x 3570 */ 3571 [pbn_ni8430_16] = { 3572 .flags = FL_BASE0, 3573 .num_ports = 16, 3574 .base_baud = 3686400, 3575 .uart_offset = 0x10, 3576 .first_offset = 0x800, 3577 }, 3578 [pbn_ni8430_8] = { 3579 .flags = FL_BASE0, 3580 .num_ports = 8, 3581 .base_baud = 3686400, 3582 .uart_offset = 0x10, 3583 .first_offset = 0x800, 3584 }, 3585 [pbn_ni8430_4] = { 3586 .flags = FL_BASE0, 3587 .num_ports = 4, 3588 .base_baud = 3686400, 3589 .uart_offset = 0x10, 3590 .first_offset = 0x800, 3591 }, 3592 [pbn_ni8430_2] = { 3593 .flags = FL_BASE0, 3594 .num_ports = 2, 3595 .base_baud = 3686400, 3596 .uart_offset = 0x10, 3597 .first_offset = 0x800, 3598 }, 3599 /* 3600 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3601 */ 3602 [pbn_ADDIDATA_PCIe_1_3906250] = { 3603 .flags = FL_BASE0, 3604 .num_ports = 1, 3605 .base_baud = 3906250, 3606 .uart_offset = 0x200, 3607 .first_offset = 0x1000, 3608 }, 3609 [pbn_ADDIDATA_PCIe_2_3906250] = { 3610 .flags = FL_BASE0, 3611 .num_ports = 2, 3612 .base_baud = 3906250, 3613 .uart_offset = 0x200, 3614 .first_offset = 0x1000, 3615 }, 3616 [pbn_ADDIDATA_PCIe_4_3906250] = { 3617 .flags = FL_BASE0, 3618 .num_ports = 4, 3619 .base_baud = 3906250, 3620 .uart_offset = 0x200, 3621 .first_offset = 0x1000, 3622 }, 3623 [pbn_ADDIDATA_PCIe_8_3906250] = { 3624 .flags = FL_BASE0, 3625 .num_ports = 8, 3626 .base_baud = 3906250, 3627 .uart_offset = 0x200, 3628 .first_offset = 0x1000, 3629 }, 3630 [pbn_ce4100_1_115200] = { 3631 .flags = FL_BASE_BARS, 3632 .num_ports = 2, 3633 .base_baud = 921600, 3634 .reg_shift = 2, 3635 }, 3636 /* 3637 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3638 * but is overridden by byt_set_termios. 3639 */ 3640 [pbn_byt] = { 3641 .flags = FL_BASE0, 3642 .num_ports = 1, 3643 .base_baud = 2764800, 3644 .uart_offset = 0x80, 3645 .reg_shift = 2, 3646 }, 3647 [pbn_qrk] = { 3648 .flags = FL_BASE0, 3649 .num_ports = 1, 3650 .base_baud = 2764800, 3651 .reg_shift = 2, 3652 }, 3653 [pbn_omegapci] = { 3654 .flags = FL_BASE0, 3655 .num_ports = 8, 3656 .base_baud = 115200, 3657 .uart_offset = 0x200, 3658 }, 3659 [pbn_NETMOS9900_2s_115200] = { 3660 .flags = FL_BASE0, 3661 .num_ports = 2, 3662 .base_baud = 115200, 3663 }, 3664 [pbn_brcm_trumanage] = { 3665 .flags = FL_BASE0, 3666 .num_ports = 1, 3667 .reg_shift = 2, 3668 .base_baud = 115200, 3669 }, 3670 [pbn_fintek_4] = { 3671 .num_ports = 4, 3672 .uart_offset = 8, 3673 .base_baud = 115200, 3674 .first_offset = 0x40, 3675 }, 3676 [pbn_fintek_8] = { 3677 .num_ports = 8, 3678 .uart_offset = 8, 3679 .base_baud = 115200, 3680 .first_offset = 0x40, 3681 }, 3682 [pbn_fintek_12] = { 3683 .num_ports = 12, 3684 .uart_offset = 8, 3685 .base_baud = 115200, 3686 .first_offset = 0x40, 3687 }, 3688 3689 [pbn_wch384_4] = { 3690 .flags = FL_BASE0, 3691 .num_ports = 4, 3692 .base_baud = 115200, 3693 .uart_offset = 8, 3694 .first_offset = 0xC0, 3695 }, 3696 }; 3697 3698 static const struct pci_device_id blacklist[] = { 3699 /* softmodems */ 3700 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3701 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3702 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3703 3704 /* multi-io cards handled by parport_serial */ 3705 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3706 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3707 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3708 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ 3709 }; 3710 3711 /* 3712 * Given a complete unknown PCI device, try to use some heuristics to 3713 * guess what the configuration might be, based on the pitiful PCI 3714 * serial specs. Returns 0 on success, 1 on failure. 3715 */ 3716 static int 3717 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3718 { 3719 const struct pci_device_id *bldev; 3720 int num_iomem, num_port, first_port = -1, i; 3721 3722 /* 3723 * If it is not a communications device or the programming 3724 * interface is greater than 6, give up. 3725 * 3726 * (Should we try to make guesses for multiport serial devices 3727 * later?) 3728 */ 3729 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3730 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3731 (dev->class & 0xff) > 6) 3732 return -ENODEV; 3733 3734 /* 3735 * Do not access blacklisted devices that are known not to 3736 * feature serial ports or are handled by other modules. 3737 */ 3738 for (bldev = blacklist; 3739 bldev < blacklist + ARRAY_SIZE(blacklist); 3740 bldev++) { 3741 if (dev->vendor == bldev->vendor && 3742 dev->device == bldev->device) 3743 return -ENODEV; 3744 } 3745 3746 num_iomem = num_port = 0; 3747 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3748 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3749 num_port++; 3750 if (first_port == -1) 3751 first_port = i; 3752 } 3753 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3754 num_iomem++; 3755 } 3756 3757 /* 3758 * If there is 1 or 0 iomem regions, and exactly one port, 3759 * use it. We guess the number of ports based on the IO 3760 * region size. 3761 */ 3762 if (num_iomem <= 1 && num_port == 1) { 3763 board->flags = first_port; 3764 board->num_ports = pci_resource_len(dev, first_port) / 8; 3765 return 0; 3766 } 3767 3768 /* 3769 * Now guess if we've got a board which indexes by BARs. 3770 * Each IO BAR should be 8 bytes, and they should follow 3771 * consecutively. 3772 */ 3773 first_port = -1; 3774 num_port = 0; 3775 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3776 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3777 pci_resource_len(dev, i) == 8 && 3778 (first_port == -1 || (first_port + num_port) == i)) { 3779 num_port++; 3780 if (first_port == -1) 3781 first_port = i; 3782 } 3783 } 3784 3785 if (num_port > 1) { 3786 board->flags = first_port | FL_BASE_BARS; 3787 board->num_ports = num_port; 3788 return 0; 3789 } 3790 3791 return -ENODEV; 3792 } 3793 3794 static inline int 3795 serial_pci_matches(const struct pciserial_board *board, 3796 const struct pciserial_board *guessed) 3797 { 3798 return 3799 board->num_ports == guessed->num_ports && 3800 board->base_baud == guessed->base_baud && 3801 board->uart_offset == guessed->uart_offset && 3802 board->reg_shift == guessed->reg_shift && 3803 board->first_offset == guessed->first_offset; 3804 } 3805 3806 struct serial_private * 3807 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3808 { 3809 struct uart_8250_port uart; 3810 struct serial_private *priv; 3811 struct pci_serial_quirk *quirk; 3812 int rc, nr_ports, i; 3813 3814 nr_ports = board->num_ports; 3815 3816 /* 3817 * Find an init and setup quirks. 3818 */ 3819 quirk = find_quirk(dev); 3820 3821 /* 3822 * Run the new-style initialization function. 3823 * The initialization function returns: 3824 * <0 - error 3825 * 0 - use board->num_ports 3826 * >0 - number of ports 3827 */ 3828 if (quirk->init) { 3829 rc = quirk->init(dev); 3830 if (rc < 0) { 3831 priv = ERR_PTR(rc); 3832 goto err_out; 3833 } 3834 if (rc) 3835 nr_ports = rc; 3836 } 3837 3838 priv = kzalloc(sizeof(struct serial_private) + 3839 sizeof(unsigned int) * nr_ports, 3840 GFP_KERNEL); 3841 if (!priv) { 3842 priv = ERR_PTR(-ENOMEM); 3843 goto err_deinit; 3844 } 3845 3846 priv->dev = dev; 3847 priv->quirk = quirk; 3848 3849 memset(&uart, 0, sizeof(uart)); 3850 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3851 uart.port.uartclk = board->base_baud * 16; 3852 uart.port.irq = get_pci_irq(dev, board); 3853 uart.port.dev = &dev->dev; 3854 3855 for (i = 0; i < nr_ports; i++) { 3856 if (quirk->setup(priv, board, &uart, i)) 3857 break; 3858 3859 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3860 uart.port.iobase, uart.port.irq, uart.port.iotype); 3861 3862 priv->line[i] = serial8250_register_8250_port(&uart); 3863 if (priv->line[i] < 0) { 3864 dev_err(&dev->dev, 3865 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3866 uart.port.iobase, uart.port.irq, 3867 uart.port.iotype, priv->line[i]); 3868 break; 3869 } 3870 } 3871 priv->nr = i; 3872 return priv; 3873 3874 err_deinit: 3875 if (quirk->exit) 3876 quirk->exit(dev); 3877 err_out: 3878 return priv; 3879 } 3880 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3881 3882 void pciserial_remove_ports(struct serial_private *priv) 3883 { 3884 struct pci_serial_quirk *quirk; 3885 int i; 3886 3887 for (i = 0; i < priv->nr; i++) 3888 serial8250_unregister_port(priv->line[i]); 3889 3890 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3891 if (priv->remapped_bar[i]) 3892 iounmap(priv->remapped_bar[i]); 3893 priv->remapped_bar[i] = NULL; 3894 } 3895 3896 /* 3897 * Find the exit quirks. 3898 */ 3899 quirk = find_quirk(priv->dev); 3900 if (quirk->exit) 3901 quirk->exit(priv->dev); 3902 3903 kfree(priv); 3904 } 3905 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3906 3907 void pciserial_suspend_ports(struct serial_private *priv) 3908 { 3909 int i; 3910 3911 for (i = 0; i < priv->nr; i++) 3912 if (priv->line[i] >= 0) 3913 serial8250_suspend_port(priv->line[i]); 3914 3915 /* 3916 * Ensure that every init quirk is properly torn down 3917 */ 3918 if (priv->quirk->exit) 3919 priv->quirk->exit(priv->dev); 3920 } 3921 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3922 3923 void pciserial_resume_ports(struct serial_private *priv) 3924 { 3925 int i; 3926 3927 /* 3928 * Ensure that the board is correctly configured. 3929 */ 3930 if (priv->quirk->init) 3931 priv->quirk->init(priv->dev); 3932 3933 for (i = 0; i < priv->nr; i++) 3934 if (priv->line[i] >= 0) 3935 serial8250_resume_port(priv->line[i]); 3936 } 3937 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3938 3939 /* 3940 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3941 * to the arrangement of serial ports on a PCI card. 3942 */ 3943 static int 3944 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3945 { 3946 struct pci_serial_quirk *quirk; 3947 struct serial_private *priv; 3948 const struct pciserial_board *board; 3949 struct pciserial_board tmp; 3950 int rc; 3951 3952 quirk = find_quirk(dev); 3953 if (quirk->probe) { 3954 rc = quirk->probe(dev); 3955 if (rc) 3956 return rc; 3957 } 3958 3959 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3960 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3961 ent->driver_data); 3962 return -EINVAL; 3963 } 3964 3965 board = &pci_boards[ent->driver_data]; 3966 3967 rc = pci_enable_device(dev); 3968 pci_save_state(dev); 3969 if (rc) 3970 return rc; 3971 3972 if (ent->driver_data == pbn_default) { 3973 /* 3974 * Use a copy of the pci_board entry for this; 3975 * avoid changing entries in the table. 3976 */ 3977 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3978 board = &tmp; 3979 3980 /* 3981 * We matched one of our class entries. Try to 3982 * determine the parameters of this board. 3983 */ 3984 rc = serial_pci_guess_board(dev, &tmp); 3985 if (rc) 3986 goto disable; 3987 } else { 3988 /* 3989 * We matched an explicit entry. If we are able to 3990 * detect this boards settings with our heuristic, 3991 * then we no longer need this entry. 3992 */ 3993 memcpy(&tmp, &pci_boards[pbn_default], 3994 sizeof(struct pciserial_board)); 3995 rc = serial_pci_guess_board(dev, &tmp); 3996 if (rc == 0 && serial_pci_matches(board, &tmp)) 3997 moan_device("Redundant entry in serial pci_table.", 3998 dev); 3999 } 4000 4001 priv = pciserial_init_ports(dev, board); 4002 if (!IS_ERR(priv)) { 4003 pci_set_drvdata(dev, priv); 4004 return 0; 4005 } 4006 4007 rc = PTR_ERR(priv); 4008 4009 disable: 4010 pci_disable_device(dev); 4011 return rc; 4012 } 4013 4014 static void pciserial_remove_one(struct pci_dev *dev) 4015 { 4016 struct serial_private *priv = pci_get_drvdata(dev); 4017 4018 pciserial_remove_ports(priv); 4019 4020 pci_disable_device(dev); 4021 } 4022 4023 #ifdef CONFIG_PM 4024 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) 4025 { 4026 struct serial_private *priv = pci_get_drvdata(dev); 4027 4028 if (priv) 4029 pciserial_suspend_ports(priv); 4030 4031 pci_save_state(dev); 4032 pci_set_power_state(dev, pci_choose_state(dev, state)); 4033 return 0; 4034 } 4035 4036 static int pciserial_resume_one(struct pci_dev *dev) 4037 { 4038 int err; 4039 struct serial_private *priv = pci_get_drvdata(dev); 4040 4041 pci_set_power_state(dev, PCI_D0); 4042 pci_restore_state(dev); 4043 4044 if (priv) { 4045 /* 4046 * The device may have been disabled. Re-enable it. 4047 */ 4048 err = pci_enable_device(dev); 4049 /* FIXME: We cannot simply error out here */ 4050 if (err) 4051 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n"); 4052 pciserial_resume_ports(priv); 4053 } 4054 return 0; 4055 } 4056 #endif 4057 4058 static struct pci_device_id serial_pci_tbl[] = { 4059 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4060 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4061 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4062 pbn_b2_8_921600 }, 4063 /* Advantech also use 0x3618 and 0xf618 */ 4064 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4065 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4066 pbn_b0_4_921600 }, 4067 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4068 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4069 pbn_b0_4_921600 }, 4070 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4071 PCI_SUBVENDOR_ID_CONNECT_TECH, 4072 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4073 pbn_b1_8_1382400 }, 4074 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4075 PCI_SUBVENDOR_ID_CONNECT_TECH, 4076 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4077 pbn_b1_4_1382400 }, 4078 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4079 PCI_SUBVENDOR_ID_CONNECT_TECH, 4080 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4081 pbn_b1_2_1382400 }, 4082 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4083 PCI_SUBVENDOR_ID_CONNECT_TECH, 4084 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4085 pbn_b1_8_1382400 }, 4086 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4087 PCI_SUBVENDOR_ID_CONNECT_TECH, 4088 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4089 pbn_b1_4_1382400 }, 4090 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4091 PCI_SUBVENDOR_ID_CONNECT_TECH, 4092 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4093 pbn_b1_2_1382400 }, 4094 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4095 PCI_SUBVENDOR_ID_CONNECT_TECH, 4096 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4097 pbn_b1_8_921600 }, 4098 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4099 PCI_SUBVENDOR_ID_CONNECT_TECH, 4100 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4101 pbn_b1_8_921600 }, 4102 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4103 PCI_SUBVENDOR_ID_CONNECT_TECH, 4104 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4105 pbn_b1_4_921600 }, 4106 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4107 PCI_SUBVENDOR_ID_CONNECT_TECH, 4108 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4109 pbn_b1_4_921600 }, 4110 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4111 PCI_SUBVENDOR_ID_CONNECT_TECH, 4112 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4113 pbn_b1_2_921600 }, 4114 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4115 PCI_SUBVENDOR_ID_CONNECT_TECH, 4116 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4117 pbn_b1_8_921600 }, 4118 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4119 PCI_SUBVENDOR_ID_CONNECT_TECH, 4120 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4121 pbn_b1_8_921600 }, 4122 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4123 PCI_SUBVENDOR_ID_CONNECT_TECH, 4124 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4125 pbn_b1_4_921600 }, 4126 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4127 PCI_SUBVENDOR_ID_CONNECT_TECH, 4128 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4129 pbn_b1_2_1250000 }, 4130 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4131 PCI_SUBVENDOR_ID_CONNECT_TECH, 4132 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4133 pbn_b0_2_1843200 }, 4134 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4135 PCI_SUBVENDOR_ID_CONNECT_TECH, 4136 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4137 pbn_b0_4_1843200 }, 4138 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4139 PCI_VENDOR_ID_AFAVLAB, 4140 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4141 pbn_b0_4_1152000 }, 4142 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4143 PCI_SUBVENDOR_ID_CONNECT_TECH, 4144 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 4145 pbn_b0_2_1843200_200 }, 4146 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4147 PCI_SUBVENDOR_ID_CONNECT_TECH, 4148 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 4149 pbn_b0_4_1843200_200 }, 4150 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4151 PCI_SUBVENDOR_ID_CONNECT_TECH, 4152 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 4153 pbn_b0_8_1843200_200 }, 4154 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4155 PCI_SUBVENDOR_ID_CONNECT_TECH, 4156 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 4157 pbn_b0_2_1843200_200 }, 4158 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4159 PCI_SUBVENDOR_ID_CONNECT_TECH, 4160 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 4161 pbn_b0_4_1843200_200 }, 4162 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4163 PCI_SUBVENDOR_ID_CONNECT_TECH, 4164 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 4165 pbn_b0_8_1843200_200 }, 4166 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4167 PCI_SUBVENDOR_ID_CONNECT_TECH, 4168 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 4169 pbn_b0_2_1843200_200 }, 4170 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4171 PCI_SUBVENDOR_ID_CONNECT_TECH, 4172 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4173 pbn_b0_4_1843200_200 }, 4174 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4175 PCI_SUBVENDOR_ID_CONNECT_TECH, 4176 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4177 pbn_b0_8_1843200_200 }, 4178 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4179 PCI_SUBVENDOR_ID_CONNECT_TECH, 4180 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4181 pbn_b0_2_1843200_200 }, 4182 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4183 PCI_SUBVENDOR_ID_CONNECT_TECH, 4184 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4185 pbn_b0_4_1843200_200 }, 4186 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4187 PCI_SUBVENDOR_ID_CONNECT_TECH, 4188 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4189 pbn_b0_8_1843200_200 }, 4190 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4191 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4192 0, 0, pbn_exar_ibm_saturn }, 4193 4194 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4196 pbn_b2_bt_1_115200 }, 4197 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4199 pbn_b2_bt_2_115200 }, 4200 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4202 pbn_b2_bt_4_115200 }, 4203 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4205 pbn_b2_bt_2_115200 }, 4206 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4208 pbn_b2_bt_4_115200 }, 4209 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4211 pbn_b2_8_115200 }, 4212 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4214 pbn_b2_8_460800 }, 4215 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4217 pbn_b2_8_115200 }, 4218 4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4221 pbn_b2_bt_2_115200 }, 4222 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4224 pbn_b2_bt_2_921600 }, 4225 /* 4226 * VScom SPCOM800, from sl@s.pl 4227 */ 4228 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_b2_8_921600 }, 4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4233 pbn_b2_4_921600 }, 4234 /* Unknown card - subdevice 0x1584 */ 4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4236 PCI_VENDOR_ID_PLX, 4237 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4238 pbn_b2_4_115200 }, 4239 /* Unknown card - subdevice 0x1588 */ 4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4241 PCI_VENDOR_ID_PLX, 4242 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4243 pbn_b2_8_115200 }, 4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4245 PCI_SUBVENDOR_ID_KEYSPAN, 4246 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4247 pbn_panacom }, 4248 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4250 pbn_panacom4 }, 4251 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4253 pbn_panacom2 }, 4254 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4255 PCI_VENDOR_ID_ESDGMBH, 4256 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4257 pbn_b2_4_115200 }, 4258 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4259 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4260 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4261 pbn_b2_4_460800 }, 4262 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4263 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4264 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4265 pbn_b2_8_460800 }, 4266 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4267 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4268 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4269 pbn_b2_16_460800 }, 4270 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4271 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4272 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4273 pbn_b2_16_460800 }, 4274 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4275 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4276 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4277 pbn_b2_4_460800 }, 4278 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4279 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4280 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4281 pbn_b2_8_460800 }, 4282 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4283 PCI_SUBVENDOR_ID_EXSYS, 4284 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4285 pbn_b2_4_115200 }, 4286 /* 4287 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4288 * (Exoray@isys.ca) 4289 */ 4290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4291 0x10b5, 0x106a, 0, 0, 4292 pbn_plx_romulus }, 4293 /* 4294 * EndRun Technologies. PCI express device range. 4295 * EndRun PTP/1588 has 2 Native UARTs. 4296 */ 4297 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4299 pbn_endrun_2_4000000 }, 4300 /* 4301 * Quatech cards. These actually have configurable clocks but for 4302 * now we just use the default. 4303 * 4304 * 100 series are RS232, 200 series RS422, 4305 */ 4306 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4308 pbn_b1_4_115200 }, 4309 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4311 pbn_b1_2_115200 }, 4312 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4314 pbn_b2_2_115200 }, 4315 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4317 pbn_b1_2_115200 }, 4318 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4320 pbn_b2_2_115200 }, 4321 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4323 pbn_b1_4_115200 }, 4324 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4326 pbn_b1_8_115200 }, 4327 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4329 pbn_b1_8_115200 }, 4330 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4332 pbn_b1_4_115200 }, 4333 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4335 pbn_b1_2_115200 }, 4336 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4338 pbn_b1_4_115200 }, 4339 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4341 pbn_b1_2_115200 }, 4342 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4344 pbn_b2_4_115200 }, 4345 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4347 pbn_b2_2_115200 }, 4348 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4350 pbn_b2_1_115200 }, 4351 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4353 pbn_b2_4_115200 }, 4354 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4356 pbn_b2_2_115200 }, 4357 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4359 pbn_b2_1_115200 }, 4360 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4362 pbn_b0_8_115200 }, 4363 4364 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4365 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4366 0, 0, 4367 pbn_b0_4_921600 }, 4368 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4369 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4370 0, 0, 4371 pbn_b0_4_1152000 }, 4372 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4374 pbn_b0_bt_2_921600 }, 4375 4376 /* 4377 * The below card is a little controversial since it is the 4378 * subject of a PCI vendor/device ID clash. (See 4379 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4380 * For now just used the hex ID 0x950a. 4381 */ 4382 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4383 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4384 0, 0, pbn_b0_2_115200 }, 4385 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4386 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4387 0, 0, pbn_b0_2_115200 }, 4388 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4390 pbn_b0_2_1130000 }, 4391 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4392 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4393 pbn_b0_1_921600 }, 4394 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4396 pbn_b0_4_115200 }, 4397 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4399 pbn_b0_bt_2_921600 }, 4400 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4401 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4402 pbn_b2_8_1152000 }, 4403 4404 /* 4405 * Oxford Semiconductor Inc. Tornado PCI express device range. 4406 */ 4407 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b0_1_4000000 }, 4410 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b0_1_4000000 }, 4413 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_oxsemi_1_4000000 }, 4416 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_oxsemi_1_4000000 }, 4419 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_b0_1_4000000 }, 4422 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_b0_1_4000000 }, 4425 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_oxsemi_1_4000000 }, 4428 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_oxsemi_1_4000000 }, 4431 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_b0_1_4000000 }, 4434 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b0_1_4000000 }, 4437 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_b0_1_4000000 }, 4440 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_b0_1_4000000 }, 4443 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_oxsemi_2_4000000 }, 4446 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_oxsemi_2_4000000 }, 4449 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_oxsemi_4_4000000 }, 4452 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4454 pbn_oxsemi_4_4000000 }, 4455 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4457 pbn_oxsemi_8_4000000 }, 4458 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4460 pbn_oxsemi_8_4000000 }, 4461 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_oxsemi_1_4000000 }, 4464 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_oxsemi_1_4000000 }, 4467 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_oxsemi_1_4000000 }, 4470 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_oxsemi_1_4000000 }, 4473 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_oxsemi_1_4000000 }, 4476 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_oxsemi_1_4000000 }, 4479 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_oxsemi_1_4000000 }, 4482 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_oxsemi_1_4000000 }, 4485 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_oxsemi_1_4000000 }, 4488 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_oxsemi_1_4000000 }, 4491 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_oxsemi_1_4000000 }, 4494 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_oxsemi_1_4000000 }, 4497 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_oxsemi_1_4000000 }, 4500 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_oxsemi_1_4000000 }, 4503 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_oxsemi_1_4000000 }, 4506 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_oxsemi_1_4000000 }, 4509 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4510 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4511 pbn_oxsemi_1_4000000 }, 4512 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4513 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4514 pbn_oxsemi_1_4000000 }, 4515 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4516 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4517 pbn_oxsemi_1_4000000 }, 4518 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4519 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4520 pbn_oxsemi_1_4000000 }, 4521 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4522 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4523 pbn_oxsemi_1_4000000 }, 4524 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4525 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4526 pbn_oxsemi_1_4000000 }, 4527 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4529 pbn_oxsemi_1_4000000 }, 4530 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4532 pbn_oxsemi_1_4000000 }, 4533 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4535 pbn_oxsemi_1_4000000 }, 4536 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4538 pbn_oxsemi_1_4000000 }, 4539 /* 4540 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4541 */ 4542 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4543 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4544 pbn_oxsemi_1_4000000 }, 4545 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4546 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4547 pbn_oxsemi_2_4000000 }, 4548 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4549 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4550 pbn_oxsemi_4_4000000 }, 4551 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4552 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4553 pbn_oxsemi_8_4000000 }, 4554 4555 /* 4556 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4557 */ 4558 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4559 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4560 pbn_oxsemi_2_4000000 }, 4561 4562 /* 4563 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4564 * from skokodyn@yahoo.com 4565 */ 4566 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4567 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4568 pbn_sbsxrsio }, 4569 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4570 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4571 pbn_sbsxrsio }, 4572 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4573 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4574 pbn_sbsxrsio }, 4575 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4576 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4577 pbn_sbsxrsio }, 4578 4579 /* 4580 * Digitan DS560-558, from jimd@esoft.com 4581 */ 4582 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_b1_1_115200 }, 4585 4586 /* 4587 * Titan Electronic cards 4588 * The 400L and 800L have a custom setup quirk. 4589 */ 4590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4592 pbn_b0_1_921600 }, 4593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4595 pbn_b0_2_921600 }, 4596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b0_4_921600 }, 4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b0_4_921600 }, 4602 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b1_1_921600 }, 4605 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b1_bt_2_921600 }, 4608 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b0_bt_4_921600 }, 4611 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b0_bt_8_921600 }, 4614 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b4_bt_2_921600 }, 4617 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b4_bt_4_921600 }, 4620 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_b4_bt_8_921600 }, 4623 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_b0_4_921600 }, 4626 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_b0_4_921600 }, 4629 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b0_4_921600 }, 4632 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4634 pbn_oxsemi_1_4000000 }, 4635 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_oxsemi_2_4000000 }, 4638 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4639 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4640 pbn_oxsemi_4_4000000 }, 4641 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4642 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4643 pbn_oxsemi_8_4000000 }, 4644 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4646 pbn_oxsemi_2_4000000 }, 4647 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4649 pbn_oxsemi_2_4000000 }, 4650 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4652 pbn_b0_bt_2_921600 }, 4653 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4654 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4655 pbn_b0_4_921600 }, 4656 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4657 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4658 pbn_b0_4_921600 }, 4659 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4661 pbn_b0_4_921600 }, 4662 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4664 pbn_b0_4_921600 }, 4665 4666 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4668 pbn_b2_1_460800 }, 4669 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_b2_1_460800 }, 4672 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4674 pbn_b2_1_460800 }, 4675 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4677 pbn_b2_bt_2_921600 }, 4678 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4680 pbn_b2_bt_2_921600 }, 4681 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4683 pbn_b2_bt_2_921600 }, 4684 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4686 pbn_b2_bt_4_921600 }, 4687 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4689 pbn_b2_bt_4_921600 }, 4690 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4692 pbn_b2_bt_4_921600 }, 4693 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4695 pbn_b0_1_921600 }, 4696 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4698 pbn_b0_1_921600 }, 4699 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4701 pbn_b0_1_921600 }, 4702 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4704 pbn_b0_bt_2_921600 }, 4705 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4707 pbn_b0_bt_2_921600 }, 4708 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4710 pbn_b0_bt_2_921600 }, 4711 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4713 pbn_b0_bt_4_921600 }, 4714 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4716 pbn_b0_bt_4_921600 }, 4717 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4719 pbn_b0_bt_4_921600 }, 4720 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_b0_bt_8_921600 }, 4723 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4725 pbn_b0_bt_8_921600 }, 4726 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4728 pbn_b0_bt_8_921600 }, 4729 4730 /* 4731 * Computone devices submitted by Doug McNash dmcnash@computone.com 4732 */ 4733 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4734 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4735 0, 0, pbn_computone_4 }, 4736 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4737 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4738 0, 0, pbn_computone_8 }, 4739 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4740 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4741 0, 0, pbn_computone_6 }, 4742 4743 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4745 pbn_oxsemi }, 4746 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4747 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4748 pbn_b0_bt_1_921600 }, 4749 4750 /* 4751 * SUNIX (TIMEDIA) 4752 */ 4753 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4754 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4755 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4756 pbn_b0_bt_1_921600 }, 4757 4758 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4759 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4760 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4761 pbn_b0_bt_1_921600 }, 4762 4763 /* 4764 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4765 */ 4766 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4768 pbn_b0_bt_8_115200 }, 4769 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4771 pbn_b0_bt_8_115200 }, 4772 4773 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4775 pbn_b0_bt_2_115200 }, 4776 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4778 pbn_b0_bt_2_115200 }, 4779 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4781 pbn_b0_bt_2_115200 }, 4782 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4784 pbn_b0_bt_2_115200 }, 4785 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4787 pbn_b0_bt_2_115200 }, 4788 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4790 pbn_b0_bt_4_460800 }, 4791 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4793 pbn_b0_bt_4_460800 }, 4794 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4796 pbn_b0_bt_2_460800 }, 4797 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4799 pbn_b0_bt_2_460800 }, 4800 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4802 pbn_b0_bt_2_460800 }, 4803 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4805 pbn_b0_bt_1_115200 }, 4806 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4808 pbn_b0_bt_1_460800 }, 4809 4810 /* 4811 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4812 * Cards are identified by their subsystem vendor IDs, which 4813 * (in hex) match the model number. 4814 * 4815 * Note that JC140x are RS422/485 cards which require ox950 4816 * ACR = 0x10, and as such are not currently fully supported. 4817 */ 4818 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4819 0x1204, 0x0004, 0, 0, 4820 pbn_b0_4_921600 }, 4821 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4822 0x1208, 0x0004, 0, 0, 4823 pbn_b0_4_921600 }, 4824 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4825 0x1402, 0x0002, 0, 0, 4826 pbn_b0_2_921600 }, */ 4827 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4828 0x1404, 0x0004, 0, 0, 4829 pbn_b0_4_921600 }, */ 4830 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4831 0x1208, 0x0004, 0, 0, 4832 pbn_b0_4_921600 }, 4833 4834 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4835 0x1204, 0x0004, 0, 0, 4836 pbn_b0_4_921600 }, 4837 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4838 0x1208, 0x0004, 0, 0, 4839 pbn_b0_4_921600 }, 4840 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4841 0x1208, 0x0004, 0, 0, 4842 pbn_b0_4_921600 }, 4843 /* 4844 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4845 */ 4846 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4848 pbn_b1_1_1382400 }, 4849 4850 /* 4851 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4852 */ 4853 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4855 pbn_b1_1_1382400 }, 4856 4857 /* 4858 * RAStel 2 port modem, gerg@moreton.com.au 4859 */ 4860 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4862 pbn_b2_bt_2_115200 }, 4863 4864 /* 4865 * EKF addition for i960 Boards form EKF with serial port 4866 */ 4867 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4868 0xE4BF, PCI_ANY_ID, 0, 0, 4869 pbn_intel_i960 }, 4870 4871 /* 4872 * Xircom Cardbus/Ethernet combos 4873 */ 4874 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4876 pbn_b0_1_115200 }, 4877 /* 4878 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4879 */ 4880 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4882 pbn_b0_1_115200 }, 4883 4884 /* 4885 * Untested PCI modems, sent in from various folks... 4886 */ 4887 4888 /* 4889 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4890 */ 4891 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4892 0x1048, 0x1500, 0, 0, 4893 pbn_b1_1_115200 }, 4894 4895 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4896 0xFF00, 0, 0, 0, 4897 pbn_sgi_ioc3 }, 4898 4899 /* 4900 * HP Diva card 4901 */ 4902 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4903 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4904 pbn_b1_1_115200 }, 4905 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_b0_5_115200 }, 4908 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_b2_1_115200 }, 4911 4912 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4914 pbn_b3_2_115200 }, 4915 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4917 pbn_b3_4_115200 }, 4918 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4920 pbn_b3_8_115200 }, 4921 4922 /* 4923 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4924 */ 4925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4926 PCI_ANY_ID, PCI_ANY_ID, 4927 0, 4928 0, pbn_exar_XR17C152 }, 4929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4930 PCI_ANY_ID, PCI_ANY_ID, 4931 0, 4932 0, pbn_exar_XR17C154 }, 4933 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4934 PCI_ANY_ID, PCI_ANY_ID, 4935 0, 4936 0, pbn_exar_XR17C158 }, 4937 /* 4938 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs 4939 */ 4940 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4941 PCI_ANY_ID, PCI_ANY_ID, 4942 0, 4943 0, pbn_exar_XR17V352 }, 4944 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4945 PCI_ANY_ID, PCI_ANY_ID, 4946 0, 4947 0, pbn_exar_XR17V354 }, 4948 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4949 PCI_ANY_ID, PCI_ANY_ID, 4950 0, 4951 0, pbn_exar_XR17V358 }, 4952 4953 /* 4954 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4955 */ 4956 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4958 pbn_b0_1_115200 }, 4959 /* 4960 * ITE 4961 */ 4962 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4963 PCI_ANY_ID, PCI_ANY_ID, 4964 0, 0, 4965 pbn_b1_bt_1_115200 }, 4966 4967 /* 4968 * IntaShield IS-200 4969 */ 4970 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4972 pbn_b2_2_115200 }, 4973 /* 4974 * IntaShield IS-400 4975 */ 4976 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4978 pbn_b2_4_115200 }, 4979 /* 4980 * Perle PCI-RAS cards 4981 */ 4982 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4983 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4984 0, 0, pbn_b2_4_921600 }, 4985 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4986 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4987 0, 0, pbn_b2_8_921600 }, 4988 4989 /* 4990 * Mainpine series cards: Fairly standard layout but fools 4991 * parts of the autodetect in some cases and uses otherwise 4992 * unmatched communications subclasses in the PCI Express case 4993 */ 4994 4995 { /* RockForceDUO */ 4996 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4997 PCI_VENDOR_ID_MAINPINE, 0x0200, 4998 0, 0, pbn_b0_2_115200 }, 4999 { /* RockForceQUATRO */ 5000 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5001 PCI_VENDOR_ID_MAINPINE, 0x0300, 5002 0, 0, pbn_b0_4_115200 }, 5003 { /* RockForceDUO+ */ 5004 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5005 PCI_VENDOR_ID_MAINPINE, 0x0400, 5006 0, 0, pbn_b0_2_115200 }, 5007 { /* RockForceQUATRO+ */ 5008 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5009 PCI_VENDOR_ID_MAINPINE, 0x0500, 5010 0, 0, pbn_b0_4_115200 }, 5011 { /* RockForce+ */ 5012 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5013 PCI_VENDOR_ID_MAINPINE, 0x0600, 5014 0, 0, pbn_b0_2_115200 }, 5015 { /* RockForce+ */ 5016 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5017 PCI_VENDOR_ID_MAINPINE, 0x0700, 5018 0, 0, pbn_b0_4_115200 }, 5019 { /* RockForceOCTO+ */ 5020 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5021 PCI_VENDOR_ID_MAINPINE, 0x0800, 5022 0, 0, pbn_b0_8_115200 }, 5023 { /* RockForceDUO+ */ 5024 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5025 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5026 0, 0, pbn_b0_2_115200 }, 5027 { /* RockForceQUARTRO+ */ 5028 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5029 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5030 0, 0, pbn_b0_4_115200 }, 5031 { /* RockForceOCTO+ */ 5032 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5033 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5034 0, 0, pbn_b0_8_115200 }, 5035 { /* RockForceD1 */ 5036 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5037 PCI_VENDOR_ID_MAINPINE, 0x2000, 5038 0, 0, pbn_b0_1_115200 }, 5039 { /* RockForceF1 */ 5040 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5041 PCI_VENDOR_ID_MAINPINE, 0x2100, 5042 0, 0, pbn_b0_1_115200 }, 5043 { /* RockForceD2 */ 5044 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5045 PCI_VENDOR_ID_MAINPINE, 0x2200, 5046 0, 0, pbn_b0_2_115200 }, 5047 { /* RockForceF2 */ 5048 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5049 PCI_VENDOR_ID_MAINPINE, 0x2300, 5050 0, 0, pbn_b0_2_115200 }, 5051 { /* RockForceD4 */ 5052 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5053 PCI_VENDOR_ID_MAINPINE, 0x2400, 5054 0, 0, pbn_b0_4_115200 }, 5055 { /* RockForceF4 */ 5056 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5057 PCI_VENDOR_ID_MAINPINE, 0x2500, 5058 0, 0, pbn_b0_4_115200 }, 5059 { /* RockForceD8 */ 5060 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5061 PCI_VENDOR_ID_MAINPINE, 0x2600, 5062 0, 0, pbn_b0_8_115200 }, 5063 { /* RockForceF8 */ 5064 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5065 PCI_VENDOR_ID_MAINPINE, 0x2700, 5066 0, 0, pbn_b0_8_115200 }, 5067 { /* IQ Express D1 */ 5068 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5069 PCI_VENDOR_ID_MAINPINE, 0x3000, 5070 0, 0, pbn_b0_1_115200 }, 5071 { /* IQ Express F1 */ 5072 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5073 PCI_VENDOR_ID_MAINPINE, 0x3100, 5074 0, 0, pbn_b0_1_115200 }, 5075 { /* IQ Express D2 */ 5076 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5077 PCI_VENDOR_ID_MAINPINE, 0x3200, 5078 0, 0, pbn_b0_2_115200 }, 5079 { /* IQ Express F2 */ 5080 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5081 PCI_VENDOR_ID_MAINPINE, 0x3300, 5082 0, 0, pbn_b0_2_115200 }, 5083 { /* IQ Express D4 */ 5084 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5085 PCI_VENDOR_ID_MAINPINE, 0x3400, 5086 0, 0, pbn_b0_4_115200 }, 5087 { /* IQ Express F4 */ 5088 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5089 PCI_VENDOR_ID_MAINPINE, 0x3500, 5090 0, 0, pbn_b0_4_115200 }, 5091 { /* IQ Express D8 */ 5092 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5093 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5094 0, 0, pbn_b0_8_115200 }, 5095 { /* IQ Express F8 */ 5096 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5097 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5098 0, 0, pbn_b0_8_115200 }, 5099 5100 5101 /* 5102 * PA Semi PA6T-1682M on-chip UART 5103 */ 5104 { PCI_VENDOR_ID_PASEMI, 0xa004, 5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5106 pbn_pasemi_1682M }, 5107 5108 /* 5109 * National Instruments 5110 */ 5111 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5113 pbn_b1_16_115200 }, 5114 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5116 pbn_b1_8_115200 }, 5117 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5119 pbn_b1_bt_4_115200 }, 5120 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5122 pbn_b1_bt_2_115200 }, 5123 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5125 pbn_b1_bt_4_115200 }, 5126 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5128 pbn_b1_bt_2_115200 }, 5129 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5131 pbn_b1_16_115200 }, 5132 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5134 pbn_b1_8_115200 }, 5135 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5137 pbn_b1_bt_4_115200 }, 5138 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5140 pbn_b1_bt_2_115200 }, 5141 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5143 pbn_b1_bt_4_115200 }, 5144 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5146 pbn_b1_bt_2_115200 }, 5147 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5149 pbn_ni8430_2 }, 5150 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5152 pbn_ni8430_2 }, 5153 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5155 pbn_ni8430_4 }, 5156 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5158 pbn_ni8430_4 }, 5159 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5161 pbn_ni8430_8 }, 5162 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5164 pbn_ni8430_8 }, 5165 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5167 pbn_ni8430_16 }, 5168 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5170 pbn_ni8430_16 }, 5171 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5173 pbn_ni8430_2 }, 5174 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5176 pbn_ni8430_2 }, 5177 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5179 pbn_ni8430_4 }, 5180 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5182 pbn_ni8430_4 }, 5183 5184 /* 5185 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5186 */ 5187 { PCI_VENDOR_ID_ADDIDATA, 5188 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5189 PCI_ANY_ID, 5190 PCI_ANY_ID, 5191 0, 5192 0, 5193 pbn_b0_4_115200 }, 5194 5195 { PCI_VENDOR_ID_ADDIDATA, 5196 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5197 PCI_ANY_ID, 5198 PCI_ANY_ID, 5199 0, 5200 0, 5201 pbn_b0_2_115200 }, 5202 5203 { PCI_VENDOR_ID_ADDIDATA, 5204 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5205 PCI_ANY_ID, 5206 PCI_ANY_ID, 5207 0, 5208 0, 5209 pbn_b0_1_115200 }, 5210 5211 { PCI_VENDOR_ID_AMCC, 5212 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5213 PCI_ANY_ID, 5214 PCI_ANY_ID, 5215 0, 5216 0, 5217 pbn_b1_8_115200 }, 5218 5219 { PCI_VENDOR_ID_ADDIDATA, 5220 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5221 PCI_ANY_ID, 5222 PCI_ANY_ID, 5223 0, 5224 0, 5225 pbn_b0_4_115200 }, 5226 5227 { PCI_VENDOR_ID_ADDIDATA, 5228 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5229 PCI_ANY_ID, 5230 PCI_ANY_ID, 5231 0, 5232 0, 5233 pbn_b0_2_115200 }, 5234 5235 { PCI_VENDOR_ID_ADDIDATA, 5236 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5237 PCI_ANY_ID, 5238 PCI_ANY_ID, 5239 0, 5240 0, 5241 pbn_b0_1_115200 }, 5242 5243 { PCI_VENDOR_ID_ADDIDATA, 5244 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5245 PCI_ANY_ID, 5246 PCI_ANY_ID, 5247 0, 5248 0, 5249 pbn_b0_4_115200 }, 5250 5251 { PCI_VENDOR_ID_ADDIDATA, 5252 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5253 PCI_ANY_ID, 5254 PCI_ANY_ID, 5255 0, 5256 0, 5257 pbn_b0_2_115200 }, 5258 5259 { PCI_VENDOR_ID_ADDIDATA, 5260 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5261 PCI_ANY_ID, 5262 PCI_ANY_ID, 5263 0, 5264 0, 5265 pbn_b0_1_115200 }, 5266 5267 { PCI_VENDOR_ID_ADDIDATA, 5268 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5269 PCI_ANY_ID, 5270 PCI_ANY_ID, 5271 0, 5272 0, 5273 pbn_b0_8_115200 }, 5274 5275 { PCI_VENDOR_ID_ADDIDATA, 5276 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5277 PCI_ANY_ID, 5278 PCI_ANY_ID, 5279 0, 5280 0, 5281 pbn_ADDIDATA_PCIe_4_3906250 }, 5282 5283 { PCI_VENDOR_ID_ADDIDATA, 5284 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5285 PCI_ANY_ID, 5286 PCI_ANY_ID, 5287 0, 5288 0, 5289 pbn_ADDIDATA_PCIe_2_3906250 }, 5290 5291 { PCI_VENDOR_ID_ADDIDATA, 5292 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5293 PCI_ANY_ID, 5294 PCI_ANY_ID, 5295 0, 5296 0, 5297 pbn_ADDIDATA_PCIe_1_3906250 }, 5298 5299 { PCI_VENDOR_ID_ADDIDATA, 5300 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5301 PCI_ANY_ID, 5302 PCI_ANY_ID, 5303 0, 5304 0, 5305 pbn_ADDIDATA_PCIe_8_3906250 }, 5306 5307 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5308 PCI_VENDOR_ID_IBM, 0x0299, 5309 0, 0, pbn_b0_bt_2_115200 }, 5310 5311 /* 5312 * other NetMos 9835 devices are most likely handled by the 5313 * parport_serial driver, check drivers/parport/parport_serial.c 5314 * before adding them here. 5315 */ 5316 5317 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5318 0xA000, 0x1000, 5319 0, 0, pbn_b0_1_115200 }, 5320 5321 /* the 9901 is a rebranded 9912 */ 5322 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5323 0xA000, 0x1000, 5324 0, 0, pbn_b0_1_115200 }, 5325 5326 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5327 0xA000, 0x1000, 5328 0, 0, pbn_b0_1_115200 }, 5329 5330 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5331 0xA000, 0x1000, 5332 0, 0, pbn_b0_1_115200 }, 5333 5334 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5335 0xA000, 0x1000, 5336 0, 0, pbn_b0_1_115200 }, 5337 5338 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5339 0xA000, 0x3002, 5340 0, 0, pbn_NETMOS9900_2s_115200 }, 5341 5342 /* 5343 * Best Connectivity and Rosewill PCI Multi I/O cards 5344 */ 5345 5346 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5347 0xA000, 0x1000, 5348 0, 0, pbn_b0_1_115200 }, 5349 5350 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5351 0xA000, 0x3002, 5352 0, 0, pbn_b0_bt_2_115200 }, 5353 5354 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5355 0xA000, 0x3004, 5356 0, 0, pbn_b0_bt_4_115200 }, 5357 /* Intel CE4100 */ 5358 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5360 pbn_ce4100_1_115200 }, 5361 /* Intel BayTrail */ 5362 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5363 PCI_ANY_ID, PCI_ANY_ID, 5364 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5365 pbn_byt }, 5366 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5367 PCI_ANY_ID, PCI_ANY_ID, 5368 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5369 pbn_byt }, 5370 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1, 5371 PCI_ANY_ID, PCI_ANY_ID, 5372 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5373 pbn_byt }, 5374 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2, 5375 PCI_ANY_ID, PCI_ANY_ID, 5376 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5377 pbn_byt }, 5378 5379 /* 5380 * Intel Quark x1000 5381 */ 5382 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART, 5383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5384 pbn_qrk }, 5385 /* 5386 * Cronyx Omega PCI 5387 */ 5388 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5390 pbn_omegapci }, 5391 5392 /* 5393 * Broadcom TruManage 5394 */ 5395 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5397 pbn_brcm_trumanage }, 5398 5399 /* 5400 * AgeStar as-prs2-009 5401 */ 5402 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5403 PCI_ANY_ID, PCI_ANY_ID, 5404 0, 0, pbn_b0_bt_2_115200 }, 5405 5406 /* 5407 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5408 * so not listed here. 5409 */ 5410 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5411 PCI_ANY_ID, PCI_ANY_ID, 5412 0, 0, pbn_b0_bt_4_115200 }, 5413 5414 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5415 PCI_ANY_ID, PCI_ANY_ID, 5416 0, 0, pbn_b0_bt_2_115200 }, 5417 5418 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S, 5419 PCI_ANY_ID, PCI_ANY_ID, 5420 0, 0, pbn_b0_bt_2_115200 }, 5421 5422 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5423 PCI_ANY_ID, PCI_ANY_ID, 5424 0, 0, pbn_wch384_4 }, 5425 5426 /* 5427 * Commtech, Inc. Fastcom adapters 5428 */ 5429 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5430 PCI_ANY_ID, PCI_ANY_ID, 5431 0, 5432 0, pbn_b0_2_1152000_200 }, 5433 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5434 PCI_ANY_ID, PCI_ANY_ID, 5435 0, 5436 0, pbn_b0_4_1152000_200 }, 5437 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5438 PCI_ANY_ID, PCI_ANY_ID, 5439 0, 5440 0, pbn_b0_4_1152000_200 }, 5441 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5442 PCI_ANY_ID, PCI_ANY_ID, 5443 0, 5444 0, pbn_b0_8_1152000_200 }, 5445 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5446 PCI_ANY_ID, PCI_ANY_ID, 5447 0, 5448 0, pbn_exar_XR17V352 }, 5449 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5450 PCI_ANY_ID, PCI_ANY_ID, 5451 0, 5452 0, pbn_exar_XR17V354 }, 5453 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5454 PCI_ANY_ID, PCI_ANY_ID, 5455 0, 5456 0, pbn_exar_XR17V358 }, 5457 5458 /* Fintek PCI serial cards */ 5459 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5460 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5461 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5462 5463 /* 5464 * These entries match devices with class COMMUNICATION_SERIAL, 5465 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5466 */ 5467 { PCI_ANY_ID, PCI_ANY_ID, 5468 PCI_ANY_ID, PCI_ANY_ID, 5469 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5470 0xffff00, pbn_default }, 5471 { PCI_ANY_ID, PCI_ANY_ID, 5472 PCI_ANY_ID, PCI_ANY_ID, 5473 PCI_CLASS_COMMUNICATION_MODEM << 8, 5474 0xffff00, pbn_default }, 5475 { PCI_ANY_ID, PCI_ANY_ID, 5476 PCI_ANY_ID, PCI_ANY_ID, 5477 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5478 0xffff00, pbn_default }, 5479 { 0, } 5480 }; 5481 5482 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5483 pci_channel_state_t state) 5484 { 5485 struct serial_private *priv = pci_get_drvdata(dev); 5486 5487 if (state == pci_channel_io_perm_failure) 5488 return PCI_ERS_RESULT_DISCONNECT; 5489 5490 if (priv) 5491 pciserial_suspend_ports(priv); 5492 5493 pci_disable_device(dev); 5494 5495 return PCI_ERS_RESULT_NEED_RESET; 5496 } 5497 5498 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5499 { 5500 int rc; 5501 5502 rc = pci_enable_device(dev); 5503 5504 if (rc) 5505 return PCI_ERS_RESULT_DISCONNECT; 5506 5507 pci_restore_state(dev); 5508 pci_save_state(dev); 5509 5510 return PCI_ERS_RESULT_RECOVERED; 5511 } 5512 5513 static void serial8250_io_resume(struct pci_dev *dev) 5514 { 5515 struct serial_private *priv = pci_get_drvdata(dev); 5516 5517 if (priv) 5518 pciserial_resume_ports(priv); 5519 } 5520 5521 static const struct pci_error_handlers serial8250_err_handler = { 5522 .error_detected = serial8250_io_error_detected, 5523 .slot_reset = serial8250_io_slot_reset, 5524 .resume = serial8250_io_resume, 5525 }; 5526 5527 static struct pci_driver serial_pci_driver = { 5528 .name = "serial", 5529 .probe = pciserial_init_one, 5530 .remove = pciserial_remove_one, 5531 #ifdef CONFIG_PM 5532 .suspend = pciserial_suspend_one, 5533 .resume = pciserial_resume_one, 5534 #endif 5535 .id_table = serial_pci_tbl, 5536 .err_handler = &serial8250_err_handler, 5537 }; 5538 5539 module_pci_driver(serial_pci_driver); 5540 5541 MODULE_LICENSE("GPL"); 5542 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5543 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5544