1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 23 #include <asm/byteorder.h> 24 #include <asm/io.h> 25 26 #include "8250.h" 27 #include "8250_pcilib.h" 28 29 /* 30 * init function returns: 31 * > 0 - number of ports 32 * = 0 - use board->num_ports 33 * < 0 - error 34 */ 35 struct pci_serial_quirk { 36 u32 vendor; 37 u32 device; 38 u32 subvendor; 39 u32 subdevice; 40 int (*probe)(struct pci_dev *dev); 41 int (*init)(struct pci_dev *dev); 42 int (*setup)(struct serial_private *, 43 const struct pciserial_board *, 44 struct uart_8250_port *, int); 45 void (*exit)(struct pci_dev *dev); 46 }; 47 48 struct f815xxa_data { 49 spinlock_t lock; 50 int idx; 51 }; 52 53 struct serial_private { 54 struct pci_dev *dev; 55 unsigned int nr; 56 struct pci_serial_quirk *quirk; 57 const struct pciserial_board *board; 58 int line[]; 59 }; 60 61 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 62 63 static const struct pci_device_id pci_use_msi[] = { 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 65 0xA000, 0x1000) }, 66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 67 0xA000, 0x1000) }, 68 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 69 0xA000, 0x1000) }, 70 { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 71 PCI_ANY_ID, PCI_ANY_ID) }, 72 { } 73 }; 74 75 static int pci_default_setup(struct serial_private*, 76 const struct pciserial_board*, struct uart_8250_port *, int); 77 78 static void moan_device(const char *str, struct pci_dev *dev) 79 { 80 pci_err(dev, "%s\n" 81 "Please send the output of lspci -vv, this\n" 82 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 83 "manufacturer and name of serial board or\n" 84 "modem board to <linux-serial@vger.kernel.org>.\n", 85 str, dev->vendor, dev->device, 86 dev->subsystem_vendor, dev->subsystem_device); 87 } 88 89 static int 90 setup_port(struct serial_private *priv, struct uart_8250_port *port, 91 u8 bar, unsigned int offset, int regshift) 92 { 93 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift); 94 } 95 96 /* 97 * ADDI-DATA GmbH communication cards <info@addi-data.com> 98 */ 99 static int addidata_apci7800_setup(struct serial_private *priv, 100 const struct pciserial_board *board, 101 struct uart_8250_port *port, int idx) 102 { 103 unsigned int bar = 0, offset = board->first_offset; 104 bar = FL_GET_BASE(board->flags); 105 106 if (idx < 2) { 107 offset += idx * board->uart_offset; 108 } else if ((idx >= 2) && (idx < 4)) { 109 bar += 1; 110 offset += ((idx - 2) * board->uart_offset); 111 } else if ((idx >= 4) && (idx < 6)) { 112 bar += 2; 113 offset += ((idx - 4) * board->uart_offset); 114 } else if (idx >= 6) { 115 bar += 3; 116 offset += ((idx - 6) * board->uart_offset); 117 } 118 119 return setup_port(priv, port, bar, offset, board->reg_shift); 120 } 121 122 /* 123 * AFAVLAB uses a different mixture of BARs and offsets 124 * Not that ugly ;) -- HW 125 */ 126 static int 127 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 128 struct uart_8250_port *port, int idx) 129 { 130 unsigned int bar, offset = board->first_offset; 131 132 bar = FL_GET_BASE(board->flags); 133 if (idx < 4) 134 bar += idx; 135 else { 136 bar = 4; 137 offset += (idx - 4) * board->uart_offset; 138 } 139 140 return setup_port(priv, port, bar, offset, board->reg_shift); 141 } 142 143 /* 144 * HP's Remote Management Console. The Diva chip came in several 145 * different versions. N-class, L2000 and A500 have two Diva chips, each 146 * with 3 UARTs (the third UART on the second chip is unused). Superdome 147 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 148 * one Diva chip, but it has been expanded to 5 UARTs. 149 */ 150 static int pci_hp_diva_init(struct pci_dev *dev) 151 { 152 int rc = 0; 153 154 switch (dev->subsystem_device) { 155 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 156 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 157 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 158 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 159 rc = 3; 160 break; 161 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 162 rc = 2; 163 break; 164 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 165 rc = 4; 166 break; 167 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 168 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 169 rc = 1; 170 break; 171 } 172 173 return rc; 174 } 175 176 /* 177 * HP's Diva chip puts the 4th/5th serial port further out, and 178 * some serial ports are supposed to be hidden on certain models. 179 */ 180 static int 181 pci_hp_diva_setup(struct serial_private *priv, 182 const struct pciserial_board *board, 183 struct uart_8250_port *port, int idx) 184 { 185 unsigned int offset = board->first_offset; 186 unsigned int bar = FL_GET_BASE(board->flags); 187 188 switch (priv->dev->subsystem_device) { 189 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 190 if (idx == 3) 191 idx++; 192 break; 193 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 194 if (idx > 0) 195 idx++; 196 if (idx > 2) 197 idx++; 198 break; 199 } 200 if (idx > 2) 201 offset = 0x18; 202 203 offset += idx * board->uart_offset; 204 205 return setup_port(priv, port, bar, offset, board->reg_shift); 206 } 207 208 /* 209 * Added for EKF Intel i960 serial boards 210 */ 211 static int pci_inteli960ni_init(struct pci_dev *dev) 212 { 213 u32 oldval; 214 215 if (!(dev->subsystem_device & 0x1000)) 216 return -ENODEV; 217 218 /* is firmware started? */ 219 pci_read_config_dword(dev, 0x44, &oldval); 220 if (oldval == 0x00001000L) { /* RESET value */ 221 pci_dbg(dev, "Local i960 firmware missing\n"); 222 return -ENODEV; 223 } 224 return 0; 225 } 226 227 /* 228 * Some PCI serial cards using the PLX 9050 PCI interface chip require 229 * that the card interrupt be explicitly enabled or disabled. This 230 * seems to be mainly needed on card using the PLX which also use I/O 231 * mapped memory. 232 */ 233 static int pci_plx9050_init(struct pci_dev *dev) 234 { 235 u8 irq_config; 236 void __iomem *p; 237 238 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 239 moan_device("no memory in bar 0", dev); 240 return 0; 241 } 242 243 irq_config = 0x41; 244 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 245 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 246 irq_config = 0x43; 247 248 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 249 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 250 /* 251 * As the megawolf cards have the int pins active 252 * high, and have 2 UART chips, both ints must be 253 * enabled on the 9050. Also, the UARTS are set in 254 * 16450 mode by default, so we have to enable the 255 * 16C950 'enhanced' mode so that we can use the 256 * deep FIFOs 257 */ 258 irq_config = 0x5b; 259 /* 260 * enable/disable interrupts 261 */ 262 p = ioremap(pci_resource_start(dev, 0), 0x80); 263 if (p == NULL) 264 return -ENOMEM; 265 writel(irq_config, p + 0x4c); 266 267 /* 268 * Read the register back to ensure that it took effect. 269 */ 270 readl(p + 0x4c); 271 iounmap(p); 272 273 return 0; 274 } 275 276 static void pci_plx9050_exit(struct pci_dev *dev) 277 { 278 u8 __iomem *p; 279 280 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 281 return; 282 283 /* 284 * disable interrupts 285 */ 286 p = ioremap(pci_resource_start(dev, 0), 0x80); 287 if (p != NULL) { 288 writel(0, p + 0x4c); 289 290 /* 291 * Read the register back to ensure that it took effect. 292 */ 293 readl(p + 0x4c); 294 iounmap(p); 295 } 296 } 297 298 #define NI8420_INT_ENABLE_REG 0x38 299 #define NI8420_INT_ENABLE_BIT 0x2000 300 301 static void pci_ni8420_exit(struct pci_dev *dev) 302 { 303 void __iomem *p; 304 unsigned int bar = 0; 305 306 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 307 moan_device("no memory in bar", dev); 308 return; 309 } 310 311 p = pci_ioremap_bar(dev, bar); 312 if (p == NULL) 313 return; 314 315 /* Disable the CPU Interrupt */ 316 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 317 p + NI8420_INT_ENABLE_REG); 318 iounmap(p); 319 } 320 321 322 /* MITE registers */ 323 #define MITE_IOWBSR1 0xc4 324 #define MITE_IOWCR1 0xf4 325 #define MITE_LCIMR1 0x08 326 #define MITE_LCIMR2 0x10 327 328 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 329 330 static void pci_ni8430_exit(struct pci_dev *dev) 331 { 332 void __iomem *p; 333 unsigned int bar = 0; 334 335 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 336 moan_device("no memory in bar", dev); 337 return; 338 } 339 340 p = pci_ioremap_bar(dev, bar); 341 if (p == NULL) 342 return; 343 344 /* Disable the CPU Interrupt */ 345 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 346 iounmap(p); 347 } 348 349 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 350 static int 351 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 352 struct uart_8250_port *port, int idx) 353 { 354 unsigned int bar, offset = board->first_offset; 355 356 bar = 0; 357 358 if (idx < 4) { 359 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 360 offset += idx * board->uart_offset; 361 } else if (idx < 8) { 362 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 363 offset += idx * board->uart_offset + 0xC00; 364 } else /* we have only 8 ports on PMC-OCTALPRO */ 365 return 1; 366 367 return setup_port(priv, port, bar, offset, board->reg_shift); 368 } 369 370 /* 371 * This does initialization for PMC OCTALPRO cards: 372 * maps the device memory, resets the UARTs (needed, bc 373 * if the module is removed and inserted again, the card 374 * is in the sleep mode) and enables global interrupt. 375 */ 376 377 /* global control register offset for SBS PMC-OctalPro */ 378 #define OCT_REG_CR_OFF 0x500 379 380 static int sbs_init(struct pci_dev *dev) 381 { 382 u8 __iomem *p; 383 384 p = pci_ioremap_bar(dev, 0); 385 386 if (p == NULL) 387 return -ENOMEM; 388 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 389 writeb(0x10, p + OCT_REG_CR_OFF); 390 udelay(50); 391 writeb(0x0, p + OCT_REG_CR_OFF); 392 393 /* Set bit-2 (INTENABLE) of Control Register */ 394 writeb(0x4, p + OCT_REG_CR_OFF); 395 iounmap(p); 396 397 return 0; 398 } 399 400 /* 401 * Disables the global interrupt of PMC-OctalPro 402 */ 403 404 static void sbs_exit(struct pci_dev *dev) 405 { 406 u8 __iomem *p; 407 408 p = pci_ioremap_bar(dev, 0); 409 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 410 if (p != NULL) 411 writeb(0, p + OCT_REG_CR_OFF); 412 iounmap(p); 413 } 414 415 /* 416 * SIIG serial cards have an PCI interface chip which also controls 417 * the UART clocking frequency. Each UART can be clocked independently 418 * (except cards equipped with 4 UARTs) and initial clocking settings 419 * are stored in the EEPROM chip. It can cause problems because this 420 * version of serial driver doesn't support differently clocked UART's 421 * on single PCI card. To prevent this, initialization functions set 422 * high frequency clocking for all UART's on given card. It is safe (I 423 * hope) because it doesn't touch EEPROM settings to prevent conflicts 424 * with other OSes (like M$ DOS). 425 * 426 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 427 * 428 * There is two family of SIIG serial cards with different PCI 429 * interface chip and different configuration methods: 430 * - 10x cards have control registers in IO and/or memory space; 431 * - 20x cards have control registers in standard PCI configuration space. 432 * 433 * Note: all 10x cards have PCI device ids 0x10.. 434 * all 20x cards have PCI device ids 0x20.. 435 * 436 * There are also Quartet Serial cards which use Oxford Semiconductor 437 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 438 * 439 * Note: some SIIG cards are probed by the parport_serial object. 440 */ 441 442 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 443 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 444 445 static int pci_siig10x_init(struct pci_dev *dev) 446 { 447 u16 data; 448 void __iomem *p; 449 450 switch (dev->device & 0xfff8) { 451 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 452 data = 0xffdf; 453 break; 454 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 455 data = 0xf7ff; 456 break; 457 default: /* 1S1P, 4S */ 458 data = 0xfffb; 459 break; 460 } 461 462 p = ioremap(pci_resource_start(dev, 0), 0x80); 463 if (p == NULL) 464 return -ENOMEM; 465 466 writew(readw(p + 0x28) & data, p + 0x28); 467 readw(p + 0x28); 468 iounmap(p); 469 return 0; 470 } 471 472 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 473 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 474 475 static int pci_siig20x_init(struct pci_dev *dev) 476 { 477 u8 data; 478 479 /* Change clock frequency for the first UART. */ 480 pci_read_config_byte(dev, 0x6f, &data); 481 pci_write_config_byte(dev, 0x6f, data & 0xef); 482 483 /* If this card has 2 UART, we have to do the same with second UART. */ 484 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 485 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 486 pci_read_config_byte(dev, 0x73, &data); 487 pci_write_config_byte(dev, 0x73, data & 0xef); 488 } 489 return 0; 490 } 491 492 static int pci_siig_init(struct pci_dev *dev) 493 { 494 unsigned int type = dev->device & 0xff00; 495 496 if (type == 0x1000) 497 return pci_siig10x_init(dev); 498 if (type == 0x2000) 499 return pci_siig20x_init(dev); 500 501 moan_device("Unknown SIIG card", dev); 502 return -ENODEV; 503 } 504 505 static int pci_siig_setup(struct serial_private *priv, 506 const struct pciserial_board *board, 507 struct uart_8250_port *port, int idx) 508 { 509 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 510 511 if (idx > 3) { 512 bar = 4; 513 offset = (idx - 4) * 8; 514 } 515 516 return setup_port(priv, port, bar, offset, 0); 517 } 518 519 /* 520 * Timedia has an explosion of boards, and to avoid the PCI table from 521 * growing *huge*, we use this function to collapse some 70 entries 522 * in the PCI table into one, for sanity's and compactness's sake. 523 */ 524 static const unsigned short timedia_single_port[] = { 525 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 526 }; 527 528 static const unsigned short timedia_dual_port[] = { 529 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 530 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 531 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 532 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 533 0xD079, 0 534 }; 535 536 static const unsigned short timedia_quad_port[] = { 537 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 538 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 539 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 540 0xB157, 0 541 }; 542 543 static const unsigned short timedia_eight_port[] = { 544 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 545 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 546 }; 547 548 static const struct timedia_struct { 549 int num; 550 const unsigned short *ids; 551 } timedia_data[] = { 552 { 1, timedia_single_port }, 553 { 2, timedia_dual_port }, 554 { 4, timedia_quad_port }, 555 { 8, timedia_eight_port } 556 }; 557 558 /* 559 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 560 * listing them individually, this driver merely grabs them all with 561 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 562 * and should be left free to be claimed by parport_serial instead. 563 */ 564 static int pci_timedia_probe(struct pci_dev *dev) 565 { 566 /* 567 * Check the third digit of the subdevice ID 568 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 569 */ 570 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 571 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 572 dev->subsystem_device); 573 return -ENODEV; 574 } 575 576 return 0; 577 } 578 579 static int pci_timedia_init(struct pci_dev *dev) 580 { 581 const unsigned short *ids; 582 int i, j; 583 584 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 585 ids = timedia_data[i].ids; 586 for (j = 0; ids[j]; j++) 587 if (dev->subsystem_device == ids[j]) 588 return timedia_data[i].num; 589 } 590 return 0; 591 } 592 593 /* 594 * Timedia/SUNIX uses a mixture of BARs and offsets 595 * Ugh, this is ugly as all hell --- TYT 596 */ 597 static int 598 pci_timedia_setup(struct serial_private *priv, 599 const struct pciserial_board *board, 600 struct uart_8250_port *port, int idx) 601 { 602 unsigned int bar = 0, offset = board->first_offset; 603 604 switch (idx) { 605 case 0: 606 bar = 0; 607 break; 608 case 1: 609 offset = board->uart_offset; 610 bar = 0; 611 break; 612 case 2: 613 bar = 1; 614 break; 615 case 3: 616 offset = board->uart_offset; 617 fallthrough; 618 case 4: /* BAR 2 */ 619 case 5: /* BAR 3 */ 620 case 6: /* BAR 4 */ 621 case 7: /* BAR 5 */ 622 bar = idx - 2; 623 } 624 625 return setup_port(priv, port, bar, offset, board->reg_shift); 626 } 627 628 /* 629 * Some Titan cards are also a little weird 630 */ 631 static int 632 titan_400l_800l_setup(struct serial_private *priv, 633 const struct pciserial_board *board, 634 struct uart_8250_port *port, int idx) 635 { 636 unsigned int bar, offset = board->first_offset; 637 638 switch (idx) { 639 case 0: 640 bar = 1; 641 break; 642 case 1: 643 bar = 2; 644 break; 645 default: 646 bar = 4; 647 offset = (idx - 2) * board->uart_offset; 648 } 649 650 return setup_port(priv, port, bar, offset, board->reg_shift); 651 } 652 653 static int pci_xircom_init(struct pci_dev *dev) 654 { 655 msleep(100); 656 return 0; 657 } 658 659 static int pci_ni8420_init(struct pci_dev *dev) 660 { 661 void __iomem *p; 662 unsigned int bar = 0; 663 664 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 665 moan_device("no memory in bar", dev); 666 return 0; 667 } 668 669 p = pci_ioremap_bar(dev, bar); 670 if (p == NULL) 671 return -ENOMEM; 672 673 /* Enable CPU Interrupt */ 674 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 675 p + NI8420_INT_ENABLE_REG); 676 677 iounmap(p); 678 return 0; 679 } 680 681 #define MITE_IOWBSR1_WSIZE 0xa 682 #define MITE_IOWBSR1_WIN_OFFSET 0x800 683 #define MITE_IOWBSR1_WENAB (1 << 7) 684 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 685 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 686 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 687 688 static int pci_ni8430_init(struct pci_dev *dev) 689 { 690 void __iomem *p; 691 struct pci_bus_region region; 692 u32 device_window; 693 unsigned int bar = 0; 694 695 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 696 moan_device("no memory in bar", dev); 697 return 0; 698 } 699 700 p = pci_ioremap_bar(dev, bar); 701 if (p == NULL) 702 return -ENOMEM; 703 704 /* 705 * Set device window address and size in BAR0, while acknowledging that 706 * the resource structure may contain a translated address that differs 707 * from the address the device responds to. 708 */ 709 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 710 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 711 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 712 writel(device_window, p + MITE_IOWBSR1); 713 714 /* Set window access to go to RAMSEL IO address space */ 715 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 716 p + MITE_IOWCR1); 717 718 /* Enable IO Bus Interrupt 0 */ 719 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 720 721 /* Enable CPU Interrupt */ 722 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 723 724 iounmap(p); 725 return 0; 726 } 727 728 /* UART Port Control Register */ 729 #define NI8430_PORTCON 0x0f 730 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 731 732 static int 733 pci_ni8430_setup(struct serial_private *priv, 734 const struct pciserial_board *board, 735 struct uart_8250_port *port, int idx) 736 { 737 struct pci_dev *dev = priv->dev; 738 void __iomem *p; 739 unsigned int bar, offset = board->first_offset; 740 741 if (idx >= board->num_ports) 742 return 1; 743 744 bar = FL_GET_BASE(board->flags); 745 offset += idx * board->uart_offset; 746 747 p = pci_ioremap_bar(dev, bar); 748 if (!p) 749 return -ENOMEM; 750 751 /* enable the transceiver */ 752 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 753 p + offset + NI8430_PORTCON); 754 755 iounmap(p); 756 757 return setup_port(priv, port, bar, offset, board->reg_shift); 758 } 759 760 static int pci_netmos_9900_setup(struct serial_private *priv, 761 const struct pciserial_board *board, 762 struct uart_8250_port *port, int idx) 763 { 764 unsigned int bar; 765 766 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 767 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 768 /* netmos apparently orders BARs by datasheet layout, so serial 769 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 770 */ 771 bar = 3 * idx; 772 773 return setup_port(priv, port, bar, 0, board->reg_shift); 774 } 775 776 return pci_default_setup(priv, board, port, idx); 777 } 778 779 /* the 99xx series comes with a range of device IDs and a variety 780 * of capabilities: 781 * 782 * 9900 has varying capabilities and can cascade to sub-controllers 783 * (cascading should be purely internal) 784 * 9904 is hardwired with 4 serial ports 785 * 9912 and 9922 are hardwired with 2 serial ports 786 */ 787 static int pci_netmos_9900_numports(struct pci_dev *dev) 788 { 789 unsigned int c = dev->class; 790 unsigned int pi; 791 unsigned short sub_serports; 792 793 pi = c & 0xff; 794 795 if (pi == 2) 796 return 1; 797 798 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 799 /* two possibilities: 0x30ps encodes number of parallel and 800 * serial ports, or 0x1000 indicates *something*. This is not 801 * immediately obvious, since the 2s1p+4s configuration seems 802 * to offer all functionality on functions 0..2, while still 803 * advertising the same function 3 as the 4s+2s1p config. 804 */ 805 sub_serports = dev->subsystem_device & 0xf; 806 if (sub_serports > 0) 807 return sub_serports; 808 809 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 810 return 0; 811 } 812 813 moan_device("unknown NetMos/Mostech program interface", dev); 814 return 0; 815 } 816 817 static int pci_netmos_init(struct pci_dev *dev) 818 { 819 /* subdevice 0x00PS means <P> parallel, <S> serial */ 820 unsigned int num_serial = dev->subsystem_device & 0xf; 821 822 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 823 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 824 return 0; 825 826 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 827 dev->subsystem_device == 0x0299) 828 return 0; 829 830 switch (dev->device) { /* FALLTHROUGH on all */ 831 case PCI_DEVICE_ID_NETMOS_9904: 832 case PCI_DEVICE_ID_NETMOS_9912: 833 case PCI_DEVICE_ID_NETMOS_9922: 834 case PCI_DEVICE_ID_NETMOS_9900: 835 num_serial = pci_netmos_9900_numports(dev); 836 break; 837 838 default: 839 break; 840 } 841 842 if (num_serial == 0) { 843 moan_device("unknown NetMos/Mostech device", dev); 844 return -ENODEV; 845 } 846 847 return num_serial; 848 } 849 850 /* 851 * These chips are available with optionally one parallel port and up to 852 * two serial ports. Unfortunately they all have the same product id. 853 * 854 * Basic configuration is done over a region of 32 I/O ports. The base 855 * ioport is called INTA or INTC, depending on docs/other drivers. 856 * 857 * The region of the 32 I/O ports is configured in POSIO0R... 858 */ 859 860 /* registers */ 861 #define ITE_887x_MISCR 0x9c 862 #define ITE_887x_INTCBAR 0x78 863 #define ITE_887x_UARTBAR 0x7c 864 #define ITE_887x_PS0BAR 0x10 865 #define ITE_887x_POSIO0 0x60 866 867 /* I/O space size */ 868 #define ITE_887x_IOSIZE 32 869 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 870 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 871 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 872 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 873 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 874 #define ITE_887x_POSIO_SPEED (3 << 29) 875 /* enable IO_Space bit */ 876 #define ITE_887x_POSIO_ENABLE (1 << 31) 877 878 /* inta_addr are the configuration addresses of the ITE */ 879 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 880 static int pci_ite887x_init(struct pci_dev *dev) 881 { 882 int ret, i, type; 883 struct resource *iobase = NULL; 884 u32 miscr, uartbar, ioport; 885 886 /* search for the base-ioport */ 887 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 888 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 889 "ite887x"); 890 if (iobase != NULL) { 891 /* write POSIO0R - speed | size | ioport */ 892 pci_write_config_dword(dev, ITE_887x_POSIO0, 893 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 894 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 895 /* write INTCBAR - ioport */ 896 pci_write_config_dword(dev, ITE_887x_INTCBAR, 897 inta_addr[i]); 898 ret = inb(inta_addr[i]); 899 if (ret != 0xff) { 900 /* ioport connected */ 901 break; 902 } 903 release_region(iobase->start, ITE_887x_IOSIZE); 904 } 905 } 906 907 if (i == ARRAY_SIZE(inta_addr)) { 908 pci_err(dev, "could not find iobase\n"); 909 return -ENODEV; 910 } 911 912 /* start of undocumented type checking (see parport_pc.c) */ 913 type = inb(iobase->start + 0x18) & 0x0f; 914 915 switch (type) { 916 case 0x2: /* ITE8871 (1P) */ 917 case 0xa: /* ITE8875 (1P) */ 918 ret = 0; 919 break; 920 case 0xe: /* ITE8872 (2S1P) */ 921 ret = 2; 922 break; 923 case 0x6: /* ITE8873 (1S) */ 924 ret = 1; 925 break; 926 case 0x8: /* ITE8874 (2S) */ 927 ret = 2; 928 break; 929 default: 930 moan_device("Unknown ITE887x", dev); 931 ret = -ENODEV; 932 } 933 934 /* configure all serial ports */ 935 for (i = 0; i < ret; i++) { 936 /* read the I/O port from the device */ 937 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 938 &ioport); 939 ioport &= 0x0000FF00; /* the actual base address */ 940 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 941 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 942 ITE_887x_POSIO_IOSIZE_8 | ioport); 943 944 /* write the ioport to the UARTBAR */ 945 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 946 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 947 uartbar |= (ioport << (16 * i)); /* set the ioport */ 948 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 949 950 /* get current config */ 951 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 952 /* disable interrupts (UARTx_Routing[3:0]) */ 953 miscr &= ~(0xf << (12 - 4 * i)); 954 /* activate the UART (UARTx_En) */ 955 miscr |= 1 << (23 - i); 956 /* write new config with activated UART */ 957 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 958 } 959 960 if (ret <= 0) { 961 /* the device has no UARTs if we get here */ 962 release_region(iobase->start, ITE_887x_IOSIZE); 963 } 964 965 return ret; 966 } 967 968 static void pci_ite887x_exit(struct pci_dev *dev) 969 { 970 u32 ioport; 971 /* the ioport is bit 0-15 in POSIO0R */ 972 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 973 ioport &= 0xffff; 974 release_region(ioport, ITE_887x_IOSIZE); 975 } 976 977 /* 978 * Oxford Semiconductor Inc. 979 * Check if an OxSemi device is part of the Tornado range of devices. 980 */ 981 #define PCI_VENDOR_ID_ENDRUN 0x7401 982 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 983 984 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 985 { 986 /* OxSemi Tornado devices are all 0xCxxx */ 987 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 988 (dev->device & 0xf000) != 0xc000) 989 return false; 990 991 /* EndRun devices are all 0xExxx */ 992 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 993 (dev->device & 0xf000) != 0xe000) 994 return false; 995 996 return true; 997 } 998 999 /* 1000 * Determine the number of ports available on a Tornado device. 1001 */ 1002 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1003 { 1004 u8 __iomem *p; 1005 unsigned long deviceID; 1006 unsigned int number_uarts = 0; 1007 1008 if (!pci_oxsemi_tornado_p(dev)) 1009 return 0; 1010 1011 p = pci_iomap(dev, 0, 5); 1012 if (p == NULL) 1013 return -ENOMEM; 1014 1015 deviceID = ioread32(p); 1016 /* Tornado device */ 1017 if (deviceID == 0x07000200) { 1018 number_uarts = ioread8(p + 4); 1019 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1020 number_uarts, 1021 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1022 "EndRun" : "Oxford"); 1023 } 1024 pci_iounmap(dev, p); 1025 return number_uarts; 1026 } 1027 1028 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1029 #define OXSEMI_TORNADO_TCR_MASK 0xf 1030 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1031 #define OXSEMI_TORNADO_CPR_MIN 0x008 1032 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1033 1034 /* 1035 * Determine the oversampling rate, the clock prescaler, and the clock 1036 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1037 * which is four times the baud base, and the prescaler increments in 1038 * steps of 1/8. Therefore to make calculations on integers we need 1039 * to use a scaled clock rate, which is the baud base multiplied by 32 1040 * (or our assumed UART clock rate multiplied by 2). 1041 * 1042 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1043 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1044 * values between 1.000 and 63.875 inclusive (operation for values from 1045 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1046 * unsigned 16-bit integer. 1047 * 1048 * For the most accurate baud rate we use a table of predetermined 1049 * oversampling rates and clock prescalers that records all possible 1050 * products of the two parameters in the range from 4 up to 255 inclusive, 1051 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1052 * by 8. The table is sorted by the decreasing value of the oversampling 1053 * rate and ties are resolved by sorting by the decreasing value of the 1054 * product. This way preference is given to higher oversampling rates. 1055 * 1056 * We iterate over the table and choose the product of an oversampling 1057 * rate and a clock prescaler that gives the lowest integer division 1058 * result deviation, or if an exact integer divider is found we stop 1059 * looking for it right away. We do some fixup if the resulting clock 1060 * divisor required would be out of its unsigned 16-bit integer range. 1061 * 1062 * Finally we abuse the supposed fractional part returned to encode the 1063 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1064 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1065 */ 1066 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1067 unsigned int baud, 1068 unsigned int *frac) 1069 { 1070 static u8 p[][2] = { 1071 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1072 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1073 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1074 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1075 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1076 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1077 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1078 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1079 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1080 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1081 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1082 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1083 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1084 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1085 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1086 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1087 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1088 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1089 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1090 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1091 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1092 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1093 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1094 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1095 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1096 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1097 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1098 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1099 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1100 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1101 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1102 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1103 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1104 { 4, 9, }, { 4, 8, }, 1105 }; 1106 /* Scale the quotient for comparison to get the fractional part. */ 1107 const unsigned int quot_scale = 65536; 1108 unsigned int sclk = port->uartclk * 2; 1109 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1110 unsigned int best_squot; 1111 unsigned int squot; 1112 unsigned int quot; 1113 u16 cpr; 1114 u8 tcr; 1115 int i; 1116 1117 /* Old custom speed handling. */ 1118 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 1119 unsigned int cust_div = port->custom_divisor; 1120 1121 quot = cust_div & UART_DIV_MAX; 1122 tcr = (cust_div >> 16) & OXSEMI_TORNADO_TCR_MASK; 1123 cpr = (cust_div >> 20) & OXSEMI_TORNADO_CPR_MASK; 1124 if (cpr < OXSEMI_TORNADO_CPR_MIN) 1125 cpr = OXSEMI_TORNADO_CPR_DEF; 1126 } else { 1127 best_squot = quot_scale; 1128 for (i = 0; i < ARRAY_SIZE(p); i++) { 1129 unsigned int spre; 1130 unsigned int srem; 1131 u8 cp; 1132 u8 tc; 1133 1134 tc = p[i][0]; 1135 cp = p[i][1]; 1136 spre = tc * cp; 1137 1138 srem = sdiv % spre; 1139 if (srem > spre / 2) 1140 srem = spre - srem; 1141 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1142 1143 if (srem == 0) { 1144 tcr = tc; 1145 cpr = cp; 1146 quot = sdiv / spre; 1147 break; 1148 } else if (squot < best_squot) { 1149 best_squot = squot; 1150 tcr = tc; 1151 cpr = cp; 1152 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1153 } 1154 } 1155 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1156 quot % 2 == 0) { 1157 quot >>= 1; 1158 tcr <<= 1; 1159 } 1160 while (quot > UART_DIV_MAX) { 1161 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1162 quot >>= 1; 1163 tcr <<= 1; 1164 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1165 quot >>= 1; 1166 cpr <<= 1; 1167 } else { 1168 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1169 cpr = OXSEMI_TORNADO_CPR_MASK; 1170 } 1171 } 1172 } 1173 1174 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1175 return quot; 1176 } 1177 1178 /* 1179 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1180 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1181 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1182 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1183 * has to be written first, followed by CPR2, which occupies the location 1184 * of CKS used with earlier UART designs. 1185 */ 1186 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1187 unsigned int baud, 1188 unsigned int quot, 1189 unsigned int quot_frac) 1190 { 1191 struct uart_8250_port *up = up_to_u8250p(port); 1192 u8 cpr2 = quot_frac >> 16; 1193 u8 cpr = quot_frac >> 8; 1194 u8 tcr = quot_frac; 1195 1196 serial_icr_write(up, UART_TCR, tcr); 1197 serial_icr_write(up, UART_CPR, cpr); 1198 serial_icr_write(up, UART_CKS, cpr2); 1199 serial8250_do_set_divisor(port, baud, quot, 0); 1200 } 1201 1202 /* 1203 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1204 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1205 */ 1206 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1207 unsigned int mctrl) 1208 { 1209 struct uart_8250_port *up = up_to_u8250p(port); 1210 1211 up->mcr |= UART_MCR_CLKSEL; 1212 serial8250_do_set_mctrl(port, mctrl); 1213 } 1214 1215 /* 1216 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1217 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1218 */ 1219 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1220 const struct pciserial_board *board, 1221 struct uart_8250_port *up, int idx) 1222 { 1223 struct pci_dev *dev = priv->dev; 1224 1225 if (pci_oxsemi_tornado_p(dev)) { 1226 up->port.flags |= UPF_FULL_PROBE; 1227 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1228 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1229 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1230 } 1231 1232 return pci_default_setup(priv, board, up, idx); 1233 } 1234 1235 static int pci_asix_setup(struct serial_private *priv, 1236 const struct pciserial_board *board, 1237 struct uart_8250_port *port, int idx) 1238 { 1239 port->bugs |= UART_BUG_PARITY; 1240 return pci_default_setup(priv, board, port, idx); 1241 } 1242 1243 #define QPCR_TEST_FOR1 0x3F 1244 #define QPCR_TEST_GET1 0x00 1245 #define QPCR_TEST_FOR2 0x40 1246 #define QPCR_TEST_GET2 0x40 1247 #define QPCR_TEST_FOR3 0x80 1248 #define QPCR_TEST_GET3 0x40 1249 #define QPCR_TEST_FOR4 0xC0 1250 #define QPCR_TEST_GET4 0x80 1251 1252 #define QOPR_CLOCK_X1 0x0000 1253 #define QOPR_CLOCK_X2 0x0001 1254 #define QOPR_CLOCK_X4 0x0002 1255 #define QOPR_CLOCK_X8 0x0003 1256 #define QOPR_CLOCK_RATE_MASK 0x0003 1257 1258 /* Quatech devices have their own extra interface features */ 1259 static struct pci_device_id quatech_cards[] = { 1260 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1261 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1262 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1263 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1264 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1265 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1266 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1267 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1268 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1269 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1270 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1271 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1272 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1273 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1274 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1275 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1276 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1277 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1278 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1279 { 0, } 1280 }; 1281 1282 static int pci_quatech_rqopr(struct uart_8250_port *port) 1283 { 1284 unsigned long base = port->port.iobase; 1285 u8 LCR, val; 1286 1287 LCR = inb(base + UART_LCR); 1288 outb(0xBF, base + UART_LCR); 1289 val = inb(base + UART_SCR); 1290 outb(LCR, base + UART_LCR); 1291 return val; 1292 } 1293 1294 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1295 { 1296 unsigned long base = port->port.iobase; 1297 u8 LCR; 1298 1299 LCR = inb(base + UART_LCR); 1300 outb(0xBF, base + UART_LCR); 1301 inb(base + UART_SCR); 1302 outb(qopr, base + UART_SCR); 1303 outb(LCR, base + UART_LCR); 1304 } 1305 1306 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1307 { 1308 unsigned long base = port->port.iobase; 1309 u8 LCR, val, qmcr; 1310 1311 LCR = inb(base + UART_LCR); 1312 outb(0xBF, base + UART_LCR); 1313 val = inb(base + UART_SCR); 1314 outb(val | 0x10, base + UART_SCR); 1315 qmcr = inb(base + UART_MCR); 1316 outb(val, base + UART_SCR); 1317 outb(LCR, base + UART_LCR); 1318 1319 return qmcr; 1320 } 1321 1322 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1323 { 1324 unsigned long base = port->port.iobase; 1325 u8 LCR, val; 1326 1327 LCR = inb(base + UART_LCR); 1328 outb(0xBF, base + UART_LCR); 1329 val = inb(base + UART_SCR); 1330 outb(val | 0x10, base + UART_SCR); 1331 outb(qmcr, base + UART_MCR); 1332 outb(val, base + UART_SCR); 1333 outb(LCR, base + UART_LCR); 1334 } 1335 1336 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1337 { 1338 unsigned long base = port->port.iobase; 1339 u8 LCR, val; 1340 1341 LCR = inb(base + UART_LCR); 1342 outb(0xBF, base + UART_LCR); 1343 val = inb(base + UART_SCR); 1344 if (val & 0x20) { 1345 outb(0x80, UART_LCR); 1346 if (!(inb(UART_SCR) & 0x20)) { 1347 outb(LCR, base + UART_LCR); 1348 return 1; 1349 } 1350 } 1351 return 0; 1352 } 1353 1354 static int pci_quatech_test(struct uart_8250_port *port) 1355 { 1356 u8 reg, qopr; 1357 1358 qopr = pci_quatech_rqopr(port); 1359 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1360 reg = pci_quatech_rqopr(port) & 0xC0; 1361 if (reg != QPCR_TEST_GET1) 1362 return -EINVAL; 1363 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1364 reg = pci_quatech_rqopr(port) & 0xC0; 1365 if (reg != QPCR_TEST_GET2) 1366 return -EINVAL; 1367 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1368 reg = pci_quatech_rqopr(port) & 0xC0; 1369 if (reg != QPCR_TEST_GET3) 1370 return -EINVAL; 1371 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1372 reg = pci_quatech_rqopr(port) & 0xC0; 1373 if (reg != QPCR_TEST_GET4) 1374 return -EINVAL; 1375 1376 pci_quatech_wqopr(port, qopr); 1377 return 0; 1378 } 1379 1380 static int pci_quatech_clock(struct uart_8250_port *port) 1381 { 1382 u8 qopr, reg, set; 1383 unsigned long clock; 1384 1385 if (pci_quatech_test(port) < 0) 1386 return 1843200; 1387 1388 qopr = pci_quatech_rqopr(port); 1389 1390 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1391 reg = pci_quatech_rqopr(port); 1392 if (reg & QOPR_CLOCK_X8) { 1393 clock = 1843200; 1394 goto out; 1395 } 1396 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1397 reg = pci_quatech_rqopr(port); 1398 if (!(reg & QOPR_CLOCK_X8)) { 1399 clock = 1843200; 1400 goto out; 1401 } 1402 reg &= QOPR_CLOCK_X8; 1403 if (reg == QOPR_CLOCK_X2) { 1404 clock = 3685400; 1405 set = QOPR_CLOCK_X2; 1406 } else if (reg == QOPR_CLOCK_X4) { 1407 clock = 7372800; 1408 set = QOPR_CLOCK_X4; 1409 } else if (reg == QOPR_CLOCK_X8) { 1410 clock = 14745600; 1411 set = QOPR_CLOCK_X8; 1412 } else { 1413 clock = 1843200; 1414 set = QOPR_CLOCK_X1; 1415 } 1416 qopr &= ~QOPR_CLOCK_RATE_MASK; 1417 qopr |= set; 1418 1419 out: 1420 pci_quatech_wqopr(port, qopr); 1421 return clock; 1422 } 1423 1424 static int pci_quatech_rs422(struct uart_8250_port *port) 1425 { 1426 u8 qmcr; 1427 int rs422 = 0; 1428 1429 if (!pci_quatech_has_qmcr(port)) 1430 return 0; 1431 qmcr = pci_quatech_rqmcr(port); 1432 pci_quatech_wqmcr(port, 0xFF); 1433 if (pci_quatech_rqmcr(port)) 1434 rs422 = 1; 1435 pci_quatech_wqmcr(port, qmcr); 1436 return rs422; 1437 } 1438 1439 static int pci_quatech_init(struct pci_dev *dev) 1440 { 1441 const struct pci_device_id *match; 1442 bool amcc = false; 1443 1444 match = pci_match_id(quatech_cards, dev); 1445 if (match) 1446 amcc = match->driver_data; 1447 else 1448 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1449 1450 if (amcc) { 1451 unsigned long base = pci_resource_start(dev, 0); 1452 if (base) { 1453 u32 tmp; 1454 1455 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1456 tmp = inl(base + 0x3c); 1457 outl(tmp | 0x01000000, base + 0x3c); 1458 outl(tmp & ~0x01000000, base + 0x3c); 1459 } 1460 } 1461 return 0; 1462 } 1463 1464 static int pci_quatech_setup(struct serial_private *priv, 1465 const struct pciserial_board *board, 1466 struct uart_8250_port *port, int idx) 1467 { 1468 /* Needed by pci_quatech calls below */ 1469 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1470 /* Set up the clocking */ 1471 port->port.uartclk = pci_quatech_clock(port); 1472 /* For now just warn about RS422 */ 1473 if (pci_quatech_rs422(port)) 1474 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1475 return pci_default_setup(priv, board, port, idx); 1476 } 1477 1478 static int pci_default_setup(struct serial_private *priv, 1479 const struct pciserial_board *board, 1480 struct uart_8250_port *port, int idx) 1481 { 1482 unsigned int bar, offset = board->first_offset, maxnr; 1483 1484 bar = FL_GET_BASE(board->flags); 1485 if (board->flags & FL_BASE_BARS) 1486 bar += idx; 1487 else 1488 offset += idx * board->uart_offset; 1489 1490 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1491 (board->reg_shift + 3); 1492 1493 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1494 return 1; 1495 1496 return setup_port(priv, port, bar, offset, board->reg_shift); 1497 } 1498 1499 static int 1500 ce4100_serial_setup(struct serial_private *priv, 1501 const struct pciserial_board *board, 1502 struct uart_8250_port *port, int idx) 1503 { 1504 int ret; 1505 1506 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1507 port->port.iotype = UPIO_MEM32; 1508 port->port.type = PORT_XSCALE; 1509 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1510 port->port.regshift = 2; 1511 1512 return ret; 1513 } 1514 1515 static int 1516 pci_omegapci_setup(struct serial_private *priv, 1517 const struct pciserial_board *board, 1518 struct uart_8250_port *port, int idx) 1519 { 1520 return setup_port(priv, port, 2, idx * 8, 0); 1521 } 1522 1523 static int 1524 pci_brcm_trumanage_setup(struct serial_private *priv, 1525 const struct pciserial_board *board, 1526 struct uart_8250_port *port, int idx) 1527 { 1528 int ret = pci_default_setup(priv, board, port, idx); 1529 1530 port->port.type = PORT_BRCM_TRUMANAGE; 1531 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1532 return ret; 1533 } 1534 1535 /* RTS will control by MCR if this bit is 0 */ 1536 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1537 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1538 #define FINTEK_RTS_INVERT BIT(5) 1539 1540 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1541 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1542 struct serial_rs485 *rs485) 1543 { 1544 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1545 u8 setting; 1546 u8 *index = (u8 *) port->private_data; 1547 1548 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1549 1550 if (rs485->flags & SER_RS485_ENABLED) { 1551 /* Enable RTS H/W control mode */ 1552 setting |= FINTEK_RTS_CONTROL_BY_HW; 1553 1554 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1555 /* RTS driving high on TX */ 1556 setting &= ~FINTEK_RTS_INVERT; 1557 } else { 1558 /* RTS driving low on TX */ 1559 setting |= FINTEK_RTS_INVERT; 1560 } 1561 } else { 1562 /* Disable RTS H/W control mode */ 1563 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1564 } 1565 1566 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1567 1568 return 0; 1569 } 1570 1571 static const struct serial_rs485 pci_fintek_rs485_supported = { 1572 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND, 1573 /* F81504/508/512 does not support RTS delay before or after send */ 1574 }; 1575 1576 static int pci_fintek_setup(struct serial_private *priv, 1577 const struct pciserial_board *board, 1578 struct uart_8250_port *port, int idx) 1579 { 1580 struct pci_dev *pdev = priv->dev; 1581 u8 *data; 1582 u8 config_base; 1583 u16 iobase; 1584 1585 config_base = 0x40 + 0x08 * idx; 1586 1587 /* Get the io address from configuration space */ 1588 pci_read_config_word(pdev, config_base + 4, &iobase); 1589 1590 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1591 1592 port->port.iotype = UPIO_PORT; 1593 port->port.iobase = iobase; 1594 port->port.rs485_config = pci_fintek_rs485_config; 1595 port->port.rs485_supported = pci_fintek_rs485_supported; 1596 1597 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1598 if (!data) 1599 return -ENOMEM; 1600 1601 /* preserve index in PCI configuration space */ 1602 *data = idx; 1603 port->port.private_data = data; 1604 1605 return 0; 1606 } 1607 1608 static int pci_fintek_init(struct pci_dev *dev) 1609 { 1610 unsigned long iobase; 1611 u32 max_port, i; 1612 resource_size_t bar_data[3]; 1613 u8 config_base; 1614 struct serial_private *priv = pci_get_drvdata(dev); 1615 1616 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1617 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1618 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1619 return -ENODEV; 1620 1621 switch (dev->device) { 1622 case 0x1104: /* 4 ports */ 1623 case 0x1108: /* 8 ports */ 1624 max_port = dev->device & 0xff; 1625 break; 1626 case 0x1112: /* 12 ports */ 1627 max_port = 12; 1628 break; 1629 default: 1630 return -EINVAL; 1631 } 1632 1633 /* Get the io address dispatch from the BIOS */ 1634 bar_data[0] = pci_resource_start(dev, 5); 1635 bar_data[1] = pci_resource_start(dev, 4); 1636 bar_data[2] = pci_resource_start(dev, 3); 1637 1638 for (i = 0; i < max_port; ++i) { 1639 /* UART0 configuration offset start from 0x40 */ 1640 config_base = 0x40 + 0x08 * i; 1641 1642 /* Calculate Real IO Port */ 1643 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1644 1645 /* Enable UART I/O port */ 1646 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1647 1648 /* Select 128-byte FIFO and 8x FIFO threshold */ 1649 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1650 1651 /* LSB UART */ 1652 pci_write_config_byte(dev, config_base + 0x04, 1653 (u8)(iobase & 0xff)); 1654 1655 /* MSB UART */ 1656 pci_write_config_byte(dev, config_base + 0x05, 1657 (u8)((iobase & 0xff00) >> 8)); 1658 1659 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1660 1661 if (!priv) { 1662 /* First init without port data 1663 * force init to RS232 Mode 1664 */ 1665 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1666 } 1667 } 1668 1669 return max_port; 1670 } 1671 1672 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1673 { 1674 struct f815xxa_data *data = p->private_data; 1675 unsigned long flags; 1676 1677 spin_lock_irqsave(&data->lock, flags); 1678 writeb(value, p->membase + offset); 1679 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1680 spin_unlock_irqrestore(&data->lock, flags); 1681 } 1682 1683 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1684 const struct pciserial_board *board, 1685 struct uart_8250_port *port, int idx) 1686 { 1687 struct pci_dev *pdev = priv->dev; 1688 struct f815xxa_data *data; 1689 1690 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1691 if (!data) 1692 return -ENOMEM; 1693 1694 data->idx = idx; 1695 spin_lock_init(&data->lock); 1696 1697 port->port.private_data = data; 1698 port->port.iotype = UPIO_MEM; 1699 port->port.flags |= UPF_IOREMAP; 1700 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1701 port->port.serial_out = f815xxa_mem_serial_out; 1702 1703 return 0; 1704 } 1705 1706 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1707 { 1708 u32 max_port, i; 1709 int config_base; 1710 1711 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1712 return -ENODEV; 1713 1714 switch (dev->device) { 1715 case 0x1204: /* 4 ports */ 1716 case 0x1208: /* 8 ports */ 1717 max_port = dev->device & 0xff; 1718 break; 1719 case 0x1212: /* 12 ports */ 1720 max_port = 12; 1721 break; 1722 default: 1723 return -EINVAL; 1724 } 1725 1726 /* Set to mmio decode */ 1727 pci_write_config_byte(dev, 0x209, 0x40); 1728 1729 for (i = 0; i < max_port; ++i) { 1730 /* UART0 configuration offset start from 0x2A0 */ 1731 config_base = 0x2A0 + 0x08 * i; 1732 1733 /* Select 128-byte FIFO and 8x FIFO threshold */ 1734 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1735 1736 /* Enable UART I/O port */ 1737 pci_write_config_byte(dev, config_base + 0, 0x01); 1738 } 1739 1740 return max_port; 1741 } 1742 1743 static int skip_tx_en_setup(struct serial_private *priv, 1744 const struct pciserial_board *board, 1745 struct uart_8250_port *port, int idx) 1746 { 1747 port->port.quirks |= UPQ_NO_TXEN_TEST; 1748 pci_dbg(priv->dev, 1749 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1750 priv->dev->vendor, priv->dev->device, 1751 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1752 1753 return pci_default_setup(priv, board, port, idx); 1754 } 1755 1756 static void kt_handle_break(struct uart_port *p) 1757 { 1758 struct uart_8250_port *up = up_to_u8250p(p); 1759 /* 1760 * On receipt of a BI, serial device in Intel ME (Intel 1761 * management engine) needs to have its fifos cleared for sane 1762 * SOL (Serial Over Lan) output. 1763 */ 1764 serial8250_clear_and_reinit_fifos(up); 1765 } 1766 1767 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1768 { 1769 struct uart_8250_port *up = up_to_u8250p(p); 1770 unsigned int val; 1771 1772 /* 1773 * When the Intel ME (management engine) gets reset its serial 1774 * port registers could return 0 momentarily. Functions like 1775 * serial8250_console_write, read and save the IER, perform 1776 * some operation and then restore it. In order to avoid 1777 * setting IER register inadvertently to 0, if the value read 1778 * is 0, double check with ier value in uart_8250_port and use 1779 * that instead. up->ier should be the same value as what is 1780 * currently configured. 1781 */ 1782 val = inb(p->iobase + offset); 1783 if (offset == UART_IER) { 1784 if (val == 0) 1785 val = up->ier; 1786 } 1787 return val; 1788 } 1789 1790 static int kt_serial_setup(struct serial_private *priv, 1791 const struct pciserial_board *board, 1792 struct uart_8250_port *port, int idx) 1793 { 1794 port->port.flags |= UPF_BUG_THRE; 1795 port->port.serial_in = kt_serial_in; 1796 port->port.handle_break = kt_handle_break; 1797 return skip_tx_en_setup(priv, board, port, idx); 1798 } 1799 1800 static int pci_eg20t_init(struct pci_dev *dev) 1801 { 1802 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1803 return -ENODEV; 1804 #else 1805 return 0; 1806 #endif 1807 } 1808 1809 static int 1810 pci_wch_ch353_setup(struct serial_private *priv, 1811 const struct pciserial_board *board, 1812 struct uart_8250_port *port, int idx) 1813 { 1814 port->port.flags |= UPF_FIXED_TYPE; 1815 port->port.type = PORT_16550A; 1816 return pci_default_setup(priv, board, port, idx); 1817 } 1818 1819 static int 1820 pci_wch_ch355_setup(struct serial_private *priv, 1821 const struct pciserial_board *board, 1822 struct uart_8250_port *port, int idx) 1823 { 1824 port->port.flags |= UPF_FIXED_TYPE; 1825 port->port.type = PORT_16550A; 1826 return pci_default_setup(priv, board, port, idx); 1827 } 1828 1829 static int 1830 pci_wch_ch38x_setup(struct serial_private *priv, 1831 const struct pciserial_board *board, 1832 struct uart_8250_port *port, int idx) 1833 { 1834 port->port.flags |= UPF_FIXED_TYPE; 1835 port->port.type = PORT_16850; 1836 return pci_default_setup(priv, board, port, idx); 1837 } 1838 1839 1840 #define CH384_XINT_ENABLE_REG 0xEB 1841 #define CH384_XINT_ENABLE_BIT 0x02 1842 1843 static int pci_wch_ch38x_init(struct pci_dev *dev) 1844 { 1845 int max_port; 1846 unsigned long iobase; 1847 1848 1849 switch (dev->device) { 1850 case 0x3853: /* 8 ports */ 1851 max_port = 8; 1852 break; 1853 default: 1854 return -EINVAL; 1855 } 1856 1857 iobase = pci_resource_start(dev, 0); 1858 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1859 1860 return max_port; 1861 } 1862 1863 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1864 { 1865 unsigned long iobase; 1866 1867 iobase = pci_resource_start(dev, 0); 1868 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1869 } 1870 1871 1872 static int 1873 pci_sunix_setup(struct serial_private *priv, 1874 const struct pciserial_board *board, 1875 struct uart_8250_port *port, int idx) 1876 { 1877 int bar; 1878 int offset; 1879 1880 port->port.flags |= UPF_FIXED_TYPE; 1881 port->port.type = PORT_SUNIX; 1882 1883 if (idx < 4) { 1884 bar = 0; 1885 offset = idx * board->uart_offset; 1886 } else { 1887 bar = 1; 1888 idx -= 4; 1889 idx = div_s64_rem(idx, 4, &offset); 1890 offset = idx * 64 + offset * board->uart_offset; 1891 } 1892 1893 return setup_port(priv, port, bar, offset, 0); 1894 } 1895 1896 static int 1897 pci_moxa_setup(struct serial_private *priv, 1898 const struct pciserial_board *board, 1899 struct uart_8250_port *port, int idx) 1900 { 1901 unsigned int bar = FL_GET_BASE(board->flags); 1902 int offset; 1903 1904 if (board->num_ports == 4 && idx == 3) 1905 offset = 7 * board->uart_offset; 1906 else 1907 offset = idx * board->uart_offset; 1908 1909 return setup_port(priv, port, bar, offset, 0); 1910 } 1911 1912 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1913 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1914 #define PCI_DEVICE_ID_OCTPRO 0x0001 1915 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1916 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1917 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1918 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1919 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1920 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1921 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1922 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1923 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1924 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1925 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1926 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1927 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1928 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1929 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1930 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1931 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1932 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1933 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1934 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1935 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1936 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1937 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1938 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1939 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1940 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1941 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1942 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1943 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1944 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1945 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1946 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1947 #define PCI_VENDOR_ID_WCH 0x4348 1948 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1949 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1950 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1951 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1952 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1953 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1954 #define PCI_VENDOR_ID_AGESTAR 0x5372 1955 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1956 #define PCI_VENDOR_ID_ASIX 0x9710 1957 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1958 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1959 1960 #define PCIE_VENDOR_ID_WCH 0x1c00 1961 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1962 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1963 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1964 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1965 1966 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1967 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1968 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1969 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1970 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1971 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1972 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1973 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1974 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1975 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1976 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1977 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1978 1979 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1980 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1981 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1982 1983 /* 1984 * Master list of serial port init/setup/exit quirks. 1985 * This does not describe the general nature of the port. 1986 * (ie, baud base, number and location of ports, etc) 1987 * 1988 * This list is ordered alphabetically by vendor then device. 1989 * Specific entries must come before more generic entries. 1990 */ 1991 static struct pci_serial_quirk pci_serial_quirks[] = { 1992 /* 1993 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1994 */ 1995 { 1996 .vendor = PCI_VENDOR_ID_AMCC, 1997 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1998 .subvendor = PCI_ANY_ID, 1999 .subdevice = PCI_ANY_ID, 2000 .setup = addidata_apci7800_setup, 2001 }, 2002 /* 2003 * AFAVLAB cards - these may be called via parport_serial 2004 * It is not clear whether this applies to all products. 2005 */ 2006 { 2007 .vendor = PCI_VENDOR_ID_AFAVLAB, 2008 .device = PCI_ANY_ID, 2009 .subvendor = PCI_ANY_ID, 2010 .subdevice = PCI_ANY_ID, 2011 .setup = afavlab_setup, 2012 }, 2013 /* 2014 * HP Diva 2015 */ 2016 { 2017 .vendor = PCI_VENDOR_ID_HP, 2018 .device = PCI_DEVICE_ID_HP_DIVA, 2019 .subvendor = PCI_ANY_ID, 2020 .subdevice = PCI_ANY_ID, 2021 .init = pci_hp_diva_init, 2022 .setup = pci_hp_diva_setup, 2023 }, 2024 /* 2025 * HPE PCI serial device 2026 */ 2027 { 2028 .vendor = PCI_VENDOR_ID_HP_3PAR, 2029 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2030 .subvendor = PCI_ANY_ID, 2031 .subdevice = PCI_ANY_ID, 2032 .setup = pci_hp_diva_setup, 2033 }, 2034 /* 2035 * Intel 2036 */ 2037 { 2038 .vendor = PCI_VENDOR_ID_INTEL, 2039 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2040 .subvendor = 0xe4bf, 2041 .subdevice = PCI_ANY_ID, 2042 .init = pci_inteli960ni_init, 2043 .setup = pci_default_setup, 2044 }, 2045 { 2046 .vendor = PCI_VENDOR_ID_INTEL, 2047 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2048 .subvendor = PCI_ANY_ID, 2049 .subdevice = PCI_ANY_ID, 2050 .setup = skip_tx_en_setup, 2051 }, 2052 { 2053 .vendor = PCI_VENDOR_ID_INTEL, 2054 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2055 .subvendor = PCI_ANY_ID, 2056 .subdevice = PCI_ANY_ID, 2057 .setup = skip_tx_en_setup, 2058 }, 2059 { 2060 .vendor = PCI_VENDOR_ID_INTEL, 2061 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2062 .subvendor = PCI_ANY_ID, 2063 .subdevice = PCI_ANY_ID, 2064 .setup = skip_tx_en_setup, 2065 }, 2066 { 2067 .vendor = PCI_VENDOR_ID_INTEL, 2068 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2069 .subvendor = PCI_ANY_ID, 2070 .subdevice = PCI_ANY_ID, 2071 .setup = ce4100_serial_setup, 2072 }, 2073 { 2074 .vendor = PCI_VENDOR_ID_INTEL, 2075 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2076 .subvendor = PCI_ANY_ID, 2077 .subdevice = PCI_ANY_ID, 2078 .setup = kt_serial_setup, 2079 }, 2080 /* 2081 * ITE 2082 */ 2083 { 2084 .vendor = PCI_VENDOR_ID_ITE, 2085 .device = PCI_DEVICE_ID_ITE_8872, 2086 .subvendor = PCI_ANY_ID, 2087 .subdevice = PCI_ANY_ID, 2088 .init = pci_ite887x_init, 2089 .setup = pci_default_setup, 2090 .exit = pci_ite887x_exit, 2091 }, 2092 /* 2093 * National Instruments 2094 */ 2095 { 2096 .vendor = PCI_VENDOR_ID_NI, 2097 .device = PCI_DEVICE_ID_NI_PCI23216, 2098 .subvendor = PCI_ANY_ID, 2099 .subdevice = PCI_ANY_ID, 2100 .init = pci_ni8420_init, 2101 .setup = pci_default_setup, 2102 .exit = pci_ni8420_exit, 2103 }, 2104 { 2105 .vendor = PCI_VENDOR_ID_NI, 2106 .device = PCI_DEVICE_ID_NI_PCI2328, 2107 .subvendor = PCI_ANY_ID, 2108 .subdevice = PCI_ANY_ID, 2109 .init = pci_ni8420_init, 2110 .setup = pci_default_setup, 2111 .exit = pci_ni8420_exit, 2112 }, 2113 { 2114 .vendor = PCI_VENDOR_ID_NI, 2115 .device = PCI_DEVICE_ID_NI_PCI2324, 2116 .subvendor = PCI_ANY_ID, 2117 .subdevice = PCI_ANY_ID, 2118 .init = pci_ni8420_init, 2119 .setup = pci_default_setup, 2120 .exit = pci_ni8420_exit, 2121 }, 2122 { 2123 .vendor = PCI_VENDOR_ID_NI, 2124 .device = PCI_DEVICE_ID_NI_PCI2322, 2125 .subvendor = PCI_ANY_ID, 2126 .subdevice = PCI_ANY_ID, 2127 .init = pci_ni8420_init, 2128 .setup = pci_default_setup, 2129 .exit = pci_ni8420_exit, 2130 }, 2131 { 2132 .vendor = PCI_VENDOR_ID_NI, 2133 .device = PCI_DEVICE_ID_NI_PCI2324I, 2134 .subvendor = PCI_ANY_ID, 2135 .subdevice = PCI_ANY_ID, 2136 .init = pci_ni8420_init, 2137 .setup = pci_default_setup, 2138 .exit = pci_ni8420_exit, 2139 }, 2140 { 2141 .vendor = PCI_VENDOR_ID_NI, 2142 .device = PCI_DEVICE_ID_NI_PCI2322I, 2143 .subvendor = PCI_ANY_ID, 2144 .subdevice = PCI_ANY_ID, 2145 .init = pci_ni8420_init, 2146 .setup = pci_default_setup, 2147 .exit = pci_ni8420_exit, 2148 }, 2149 { 2150 .vendor = PCI_VENDOR_ID_NI, 2151 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2152 .subvendor = PCI_ANY_ID, 2153 .subdevice = PCI_ANY_ID, 2154 .init = pci_ni8420_init, 2155 .setup = pci_default_setup, 2156 .exit = pci_ni8420_exit, 2157 }, 2158 { 2159 .vendor = PCI_VENDOR_ID_NI, 2160 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2161 .subvendor = PCI_ANY_ID, 2162 .subdevice = PCI_ANY_ID, 2163 .init = pci_ni8420_init, 2164 .setup = pci_default_setup, 2165 .exit = pci_ni8420_exit, 2166 }, 2167 { 2168 .vendor = PCI_VENDOR_ID_NI, 2169 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2170 .subvendor = PCI_ANY_ID, 2171 .subdevice = PCI_ANY_ID, 2172 .init = pci_ni8420_init, 2173 .setup = pci_default_setup, 2174 .exit = pci_ni8420_exit, 2175 }, 2176 { 2177 .vendor = PCI_VENDOR_ID_NI, 2178 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2179 .subvendor = PCI_ANY_ID, 2180 .subdevice = PCI_ANY_ID, 2181 .init = pci_ni8420_init, 2182 .setup = pci_default_setup, 2183 .exit = pci_ni8420_exit, 2184 }, 2185 { 2186 .vendor = PCI_VENDOR_ID_NI, 2187 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2188 .subvendor = PCI_ANY_ID, 2189 .subdevice = PCI_ANY_ID, 2190 .init = pci_ni8420_init, 2191 .setup = pci_default_setup, 2192 .exit = pci_ni8420_exit, 2193 }, 2194 { 2195 .vendor = PCI_VENDOR_ID_NI, 2196 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2197 .subvendor = PCI_ANY_ID, 2198 .subdevice = PCI_ANY_ID, 2199 .init = pci_ni8420_init, 2200 .setup = pci_default_setup, 2201 .exit = pci_ni8420_exit, 2202 }, 2203 { 2204 .vendor = PCI_VENDOR_ID_NI, 2205 .device = PCI_ANY_ID, 2206 .subvendor = PCI_ANY_ID, 2207 .subdevice = PCI_ANY_ID, 2208 .init = pci_ni8430_init, 2209 .setup = pci_ni8430_setup, 2210 .exit = pci_ni8430_exit, 2211 }, 2212 /* Quatech */ 2213 { 2214 .vendor = PCI_VENDOR_ID_QUATECH, 2215 .device = PCI_ANY_ID, 2216 .subvendor = PCI_ANY_ID, 2217 .subdevice = PCI_ANY_ID, 2218 .init = pci_quatech_init, 2219 .setup = pci_quatech_setup, 2220 }, 2221 /* 2222 * Panacom 2223 */ 2224 { 2225 .vendor = PCI_VENDOR_ID_PANACOM, 2226 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2227 .subvendor = PCI_ANY_ID, 2228 .subdevice = PCI_ANY_ID, 2229 .init = pci_plx9050_init, 2230 .setup = pci_default_setup, 2231 .exit = pci_plx9050_exit, 2232 }, 2233 { 2234 .vendor = PCI_VENDOR_ID_PANACOM, 2235 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2236 .subvendor = PCI_ANY_ID, 2237 .subdevice = PCI_ANY_ID, 2238 .init = pci_plx9050_init, 2239 .setup = pci_default_setup, 2240 .exit = pci_plx9050_exit, 2241 }, 2242 /* 2243 * PLX 2244 */ 2245 { 2246 .vendor = PCI_VENDOR_ID_PLX, 2247 .device = PCI_DEVICE_ID_PLX_9050, 2248 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2249 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2250 .init = pci_plx9050_init, 2251 .setup = pci_default_setup, 2252 .exit = pci_plx9050_exit, 2253 }, 2254 { 2255 .vendor = PCI_VENDOR_ID_PLX, 2256 .device = PCI_DEVICE_ID_PLX_9050, 2257 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2258 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2259 .init = pci_plx9050_init, 2260 .setup = pci_default_setup, 2261 .exit = pci_plx9050_exit, 2262 }, 2263 { 2264 .vendor = PCI_VENDOR_ID_PLX, 2265 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2266 .subvendor = PCI_VENDOR_ID_PLX, 2267 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2268 .init = pci_plx9050_init, 2269 .setup = pci_default_setup, 2270 .exit = pci_plx9050_exit, 2271 }, 2272 /* 2273 * SBS Technologies, Inc., PMC-OCTALPRO 232 2274 */ 2275 { 2276 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2277 .device = PCI_DEVICE_ID_OCTPRO, 2278 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2279 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2280 .init = sbs_init, 2281 .setup = sbs_setup, 2282 .exit = sbs_exit, 2283 }, 2284 /* 2285 * SBS Technologies, Inc., PMC-OCTALPRO 422 2286 */ 2287 { 2288 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2289 .device = PCI_DEVICE_ID_OCTPRO, 2290 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2291 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2292 .init = sbs_init, 2293 .setup = sbs_setup, 2294 .exit = sbs_exit, 2295 }, 2296 /* 2297 * SBS Technologies, Inc., P-Octal 232 2298 */ 2299 { 2300 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2301 .device = PCI_DEVICE_ID_OCTPRO, 2302 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2303 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2304 .init = sbs_init, 2305 .setup = sbs_setup, 2306 .exit = sbs_exit, 2307 }, 2308 /* 2309 * SBS Technologies, Inc., P-Octal 422 2310 */ 2311 { 2312 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2313 .device = PCI_DEVICE_ID_OCTPRO, 2314 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2315 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2316 .init = sbs_init, 2317 .setup = sbs_setup, 2318 .exit = sbs_exit, 2319 }, 2320 /* 2321 * SIIG cards - these may be called via parport_serial 2322 */ 2323 { 2324 .vendor = PCI_VENDOR_ID_SIIG, 2325 .device = PCI_ANY_ID, 2326 .subvendor = PCI_ANY_ID, 2327 .subdevice = PCI_ANY_ID, 2328 .init = pci_siig_init, 2329 .setup = pci_siig_setup, 2330 }, 2331 /* 2332 * Titan cards 2333 */ 2334 { 2335 .vendor = PCI_VENDOR_ID_TITAN, 2336 .device = PCI_DEVICE_ID_TITAN_400L, 2337 .subvendor = PCI_ANY_ID, 2338 .subdevice = PCI_ANY_ID, 2339 .setup = titan_400l_800l_setup, 2340 }, 2341 { 2342 .vendor = PCI_VENDOR_ID_TITAN, 2343 .device = PCI_DEVICE_ID_TITAN_800L, 2344 .subvendor = PCI_ANY_ID, 2345 .subdevice = PCI_ANY_ID, 2346 .setup = titan_400l_800l_setup, 2347 }, 2348 /* 2349 * Timedia cards 2350 */ 2351 { 2352 .vendor = PCI_VENDOR_ID_TIMEDIA, 2353 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2354 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2355 .subdevice = PCI_ANY_ID, 2356 .probe = pci_timedia_probe, 2357 .init = pci_timedia_init, 2358 .setup = pci_timedia_setup, 2359 }, 2360 { 2361 .vendor = PCI_VENDOR_ID_TIMEDIA, 2362 .device = PCI_ANY_ID, 2363 .subvendor = PCI_ANY_ID, 2364 .subdevice = PCI_ANY_ID, 2365 .setup = pci_timedia_setup, 2366 }, 2367 /* 2368 * Sunix PCI serial boards 2369 */ 2370 { 2371 .vendor = PCI_VENDOR_ID_SUNIX, 2372 .device = PCI_DEVICE_ID_SUNIX_1999, 2373 .subvendor = PCI_VENDOR_ID_SUNIX, 2374 .subdevice = PCI_ANY_ID, 2375 .setup = pci_sunix_setup, 2376 }, 2377 /* 2378 * Xircom cards 2379 */ 2380 { 2381 .vendor = PCI_VENDOR_ID_XIRCOM, 2382 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2383 .subvendor = PCI_ANY_ID, 2384 .subdevice = PCI_ANY_ID, 2385 .init = pci_xircom_init, 2386 .setup = pci_default_setup, 2387 }, 2388 /* 2389 * Netmos cards - these may be called via parport_serial 2390 */ 2391 { 2392 .vendor = PCI_VENDOR_ID_NETMOS, 2393 .device = PCI_ANY_ID, 2394 .subvendor = PCI_ANY_ID, 2395 .subdevice = PCI_ANY_ID, 2396 .init = pci_netmos_init, 2397 .setup = pci_netmos_9900_setup, 2398 }, 2399 /* 2400 * EndRun Technologies 2401 */ 2402 { 2403 .vendor = PCI_VENDOR_ID_ENDRUN, 2404 .device = PCI_ANY_ID, 2405 .subvendor = PCI_ANY_ID, 2406 .subdevice = PCI_ANY_ID, 2407 .init = pci_oxsemi_tornado_init, 2408 .setup = pci_default_setup, 2409 }, 2410 /* 2411 * For Oxford Semiconductor Tornado based devices 2412 */ 2413 { 2414 .vendor = PCI_VENDOR_ID_OXSEMI, 2415 .device = PCI_ANY_ID, 2416 .subvendor = PCI_ANY_ID, 2417 .subdevice = PCI_ANY_ID, 2418 .init = pci_oxsemi_tornado_init, 2419 .setup = pci_oxsemi_tornado_setup, 2420 }, 2421 { 2422 .vendor = PCI_VENDOR_ID_MAINPINE, 2423 .device = PCI_ANY_ID, 2424 .subvendor = PCI_ANY_ID, 2425 .subdevice = PCI_ANY_ID, 2426 .init = pci_oxsemi_tornado_init, 2427 .setup = pci_oxsemi_tornado_setup, 2428 }, 2429 { 2430 .vendor = PCI_VENDOR_ID_DIGI, 2431 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2432 .subvendor = PCI_SUBVENDOR_ID_IBM, 2433 .subdevice = PCI_ANY_ID, 2434 .init = pci_oxsemi_tornado_init, 2435 .setup = pci_oxsemi_tornado_setup, 2436 }, 2437 { 2438 .vendor = PCI_VENDOR_ID_INTEL, 2439 .device = 0x8811, 2440 .subvendor = PCI_ANY_ID, 2441 .subdevice = PCI_ANY_ID, 2442 .init = pci_eg20t_init, 2443 .setup = pci_default_setup, 2444 }, 2445 { 2446 .vendor = PCI_VENDOR_ID_INTEL, 2447 .device = 0x8812, 2448 .subvendor = PCI_ANY_ID, 2449 .subdevice = PCI_ANY_ID, 2450 .init = pci_eg20t_init, 2451 .setup = pci_default_setup, 2452 }, 2453 { 2454 .vendor = PCI_VENDOR_ID_INTEL, 2455 .device = 0x8813, 2456 .subvendor = PCI_ANY_ID, 2457 .subdevice = PCI_ANY_ID, 2458 .init = pci_eg20t_init, 2459 .setup = pci_default_setup, 2460 }, 2461 { 2462 .vendor = PCI_VENDOR_ID_INTEL, 2463 .device = 0x8814, 2464 .subvendor = PCI_ANY_ID, 2465 .subdevice = PCI_ANY_ID, 2466 .init = pci_eg20t_init, 2467 .setup = pci_default_setup, 2468 }, 2469 { 2470 .vendor = 0x10DB, 2471 .device = 0x8027, 2472 .subvendor = PCI_ANY_ID, 2473 .subdevice = PCI_ANY_ID, 2474 .init = pci_eg20t_init, 2475 .setup = pci_default_setup, 2476 }, 2477 { 2478 .vendor = 0x10DB, 2479 .device = 0x8028, 2480 .subvendor = PCI_ANY_ID, 2481 .subdevice = PCI_ANY_ID, 2482 .init = pci_eg20t_init, 2483 .setup = pci_default_setup, 2484 }, 2485 { 2486 .vendor = 0x10DB, 2487 .device = 0x8029, 2488 .subvendor = PCI_ANY_ID, 2489 .subdevice = PCI_ANY_ID, 2490 .init = pci_eg20t_init, 2491 .setup = pci_default_setup, 2492 }, 2493 { 2494 .vendor = 0x10DB, 2495 .device = 0x800C, 2496 .subvendor = PCI_ANY_ID, 2497 .subdevice = PCI_ANY_ID, 2498 .init = pci_eg20t_init, 2499 .setup = pci_default_setup, 2500 }, 2501 { 2502 .vendor = 0x10DB, 2503 .device = 0x800D, 2504 .subvendor = PCI_ANY_ID, 2505 .subdevice = PCI_ANY_ID, 2506 .init = pci_eg20t_init, 2507 .setup = pci_default_setup, 2508 }, 2509 /* 2510 * Cronyx Omega PCI (PLX-chip based) 2511 */ 2512 { 2513 .vendor = PCI_VENDOR_ID_PLX, 2514 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2515 .subvendor = PCI_ANY_ID, 2516 .subdevice = PCI_ANY_ID, 2517 .setup = pci_omegapci_setup, 2518 }, 2519 /* WCH CH353 1S1P card (16550 clone) */ 2520 { 2521 .vendor = PCI_VENDOR_ID_WCH, 2522 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2523 .subvendor = PCI_ANY_ID, 2524 .subdevice = PCI_ANY_ID, 2525 .setup = pci_wch_ch353_setup, 2526 }, 2527 /* WCH CH353 2S1P card (16550 clone) */ 2528 { 2529 .vendor = PCI_VENDOR_ID_WCH, 2530 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2531 .subvendor = PCI_ANY_ID, 2532 .subdevice = PCI_ANY_ID, 2533 .setup = pci_wch_ch353_setup, 2534 }, 2535 /* WCH CH353 4S card (16550 clone) */ 2536 { 2537 .vendor = PCI_VENDOR_ID_WCH, 2538 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2539 .subvendor = PCI_ANY_ID, 2540 .subdevice = PCI_ANY_ID, 2541 .setup = pci_wch_ch353_setup, 2542 }, 2543 /* WCH CH353 2S1PF card (16550 clone) */ 2544 { 2545 .vendor = PCI_VENDOR_ID_WCH, 2546 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2547 .subvendor = PCI_ANY_ID, 2548 .subdevice = PCI_ANY_ID, 2549 .setup = pci_wch_ch353_setup, 2550 }, 2551 /* WCH CH352 2S card (16550 clone) */ 2552 { 2553 .vendor = PCI_VENDOR_ID_WCH, 2554 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2555 .subvendor = PCI_ANY_ID, 2556 .subdevice = PCI_ANY_ID, 2557 .setup = pci_wch_ch353_setup, 2558 }, 2559 /* WCH CH355 4S card (16550 clone) */ 2560 { 2561 .vendor = PCI_VENDOR_ID_WCH, 2562 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2563 .subvendor = PCI_ANY_ID, 2564 .subdevice = PCI_ANY_ID, 2565 .setup = pci_wch_ch355_setup, 2566 }, 2567 /* WCH CH382 2S card (16850 clone) */ 2568 { 2569 .vendor = PCIE_VENDOR_ID_WCH, 2570 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2571 .subvendor = PCI_ANY_ID, 2572 .subdevice = PCI_ANY_ID, 2573 .setup = pci_wch_ch38x_setup, 2574 }, 2575 /* WCH CH382 2S1P card (16850 clone) */ 2576 { 2577 .vendor = PCIE_VENDOR_ID_WCH, 2578 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2579 .subvendor = PCI_ANY_ID, 2580 .subdevice = PCI_ANY_ID, 2581 .setup = pci_wch_ch38x_setup, 2582 }, 2583 /* WCH CH384 4S card (16850 clone) */ 2584 { 2585 .vendor = PCIE_VENDOR_ID_WCH, 2586 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2587 .subvendor = PCI_ANY_ID, 2588 .subdevice = PCI_ANY_ID, 2589 .setup = pci_wch_ch38x_setup, 2590 }, 2591 /* WCH CH384 8S card (16850 clone) */ 2592 { 2593 .vendor = PCIE_VENDOR_ID_WCH, 2594 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2595 .subvendor = PCI_ANY_ID, 2596 .subdevice = PCI_ANY_ID, 2597 .init = pci_wch_ch38x_init, 2598 .exit = pci_wch_ch38x_exit, 2599 .setup = pci_wch_ch38x_setup, 2600 }, 2601 /* 2602 * ASIX devices with FIFO bug 2603 */ 2604 { 2605 .vendor = PCI_VENDOR_ID_ASIX, 2606 .device = PCI_ANY_ID, 2607 .subvendor = PCI_ANY_ID, 2608 .subdevice = PCI_ANY_ID, 2609 .setup = pci_asix_setup, 2610 }, 2611 /* 2612 * Broadcom TruManage (NetXtreme) 2613 */ 2614 { 2615 .vendor = PCI_VENDOR_ID_BROADCOM, 2616 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .setup = pci_brcm_trumanage_setup, 2620 }, 2621 { 2622 .vendor = 0x1c29, 2623 .device = 0x1104, 2624 .subvendor = PCI_ANY_ID, 2625 .subdevice = PCI_ANY_ID, 2626 .setup = pci_fintek_setup, 2627 .init = pci_fintek_init, 2628 }, 2629 { 2630 .vendor = 0x1c29, 2631 .device = 0x1108, 2632 .subvendor = PCI_ANY_ID, 2633 .subdevice = PCI_ANY_ID, 2634 .setup = pci_fintek_setup, 2635 .init = pci_fintek_init, 2636 }, 2637 { 2638 .vendor = 0x1c29, 2639 .device = 0x1112, 2640 .subvendor = PCI_ANY_ID, 2641 .subdevice = PCI_ANY_ID, 2642 .setup = pci_fintek_setup, 2643 .init = pci_fintek_init, 2644 }, 2645 /* 2646 * MOXA 2647 */ 2648 { 2649 .vendor = PCI_VENDOR_ID_MOXA, 2650 .device = PCI_ANY_ID, 2651 .subvendor = PCI_ANY_ID, 2652 .subdevice = PCI_ANY_ID, 2653 .setup = pci_moxa_setup, 2654 }, 2655 { 2656 .vendor = 0x1c29, 2657 .device = 0x1204, 2658 .subvendor = PCI_ANY_ID, 2659 .subdevice = PCI_ANY_ID, 2660 .setup = pci_fintek_f815xxa_setup, 2661 .init = pci_fintek_f815xxa_init, 2662 }, 2663 { 2664 .vendor = 0x1c29, 2665 .device = 0x1208, 2666 .subvendor = PCI_ANY_ID, 2667 .subdevice = PCI_ANY_ID, 2668 .setup = pci_fintek_f815xxa_setup, 2669 .init = pci_fintek_f815xxa_init, 2670 }, 2671 { 2672 .vendor = 0x1c29, 2673 .device = 0x1212, 2674 .subvendor = PCI_ANY_ID, 2675 .subdevice = PCI_ANY_ID, 2676 .setup = pci_fintek_f815xxa_setup, 2677 .init = pci_fintek_f815xxa_init, 2678 }, 2679 2680 /* 2681 * Default "match everything" terminator entry 2682 */ 2683 { 2684 .vendor = PCI_ANY_ID, 2685 .device = PCI_ANY_ID, 2686 .subvendor = PCI_ANY_ID, 2687 .subdevice = PCI_ANY_ID, 2688 .setup = pci_default_setup, 2689 } 2690 }; 2691 2692 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2693 { 2694 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2695 } 2696 2697 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2698 { 2699 struct pci_serial_quirk *quirk; 2700 2701 for (quirk = pci_serial_quirks; ; quirk++) 2702 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2703 quirk_id_matches(quirk->device, dev->device) && 2704 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2705 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2706 break; 2707 return quirk; 2708 } 2709 2710 /* 2711 * This is the configuration table for all of the PCI serial boards 2712 * which we support. It is directly indexed by the pci_board_num_t enum 2713 * value, which is encoded in the pci_device_id PCI probe table's 2714 * driver_data member. 2715 * 2716 * The makeup of these names are: 2717 * pbn_bn{_bt}_n_baud{_offsetinhex} 2718 * 2719 * bn = PCI BAR number 2720 * bt = Index using PCI BARs 2721 * n = number of serial ports 2722 * baud = baud rate 2723 * offsetinhex = offset for each sequential port (in hex) 2724 * 2725 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2726 * 2727 * Please note: in theory if n = 1, _bt infix should make no difference. 2728 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2729 */ 2730 enum pci_board_num_t { 2731 pbn_default = 0, 2732 2733 pbn_b0_1_115200, 2734 pbn_b0_2_115200, 2735 pbn_b0_4_115200, 2736 pbn_b0_5_115200, 2737 pbn_b0_8_115200, 2738 2739 pbn_b0_1_921600, 2740 pbn_b0_2_921600, 2741 pbn_b0_4_921600, 2742 2743 pbn_b0_2_1130000, 2744 2745 pbn_b0_4_1152000, 2746 2747 pbn_b0_4_1250000, 2748 2749 pbn_b0_2_1843200, 2750 pbn_b0_4_1843200, 2751 2752 pbn_b0_1_15625000, 2753 2754 pbn_b0_bt_1_115200, 2755 pbn_b0_bt_2_115200, 2756 pbn_b0_bt_4_115200, 2757 pbn_b0_bt_8_115200, 2758 2759 pbn_b0_bt_1_460800, 2760 pbn_b0_bt_2_460800, 2761 pbn_b0_bt_4_460800, 2762 2763 pbn_b0_bt_1_921600, 2764 pbn_b0_bt_2_921600, 2765 pbn_b0_bt_4_921600, 2766 pbn_b0_bt_8_921600, 2767 2768 pbn_b1_1_115200, 2769 pbn_b1_2_115200, 2770 pbn_b1_4_115200, 2771 pbn_b1_8_115200, 2772 pbn_b1_16_115200, 2773 2774 pbn_b1_1_921600, 2775 pbn_b1_2_921600, 2776 pbn_b1_4_921600, 2777 pbn_b1_8_921600, 2778 2779 pbn_b1_2_1250000, 2780 2781 pbn_b1_bt_1_115200, 2782 pbn_b1_bt_2_115200, 2783 pbn_b1_bt_4_115200, 2784 2785 pbn_b1_bt_2_921600, 2786 2787 pbn_b1_1_1382400, 2788 pbn_b1_2_1382400, 2789 pbn_b1_4_1382400, 2790 pbn_b1_8_1382400, 2791 2792 pbn_b2_1_115200, 2793 pbn_b2_2_115200, 2794 pbn_b2_4_115200, 2795 pbn_b2_8_115200, 2796 2797 pbn_b2_1_460800, 2798 pbn_b2_4_460800, 2799 pbn_b2_8_460800, 2800 pbn_b2_16_460800, 2801 2802 pbn_b2_1_921600, 2803 pbn_b2_4_921600, 2804 pbn_b2_8_921600, 2805 2806 pbn_b2_8_1152000, 2807 2808 pbn_b2_bt_1_115200, 2809 pbn_b2_bt_2_115200, 2810 pbn_b2_bt_4_115200, 2811 2812 pbn_b2_bt_2_921600, 2813 pbn_b2_bt_4_921600, 2814 2815 pbn_b3_2_115200, 2816 pbn_b3_4_115200, 2817 pbn_b3_8_115200, 2818 2819 pbn_b4_bt_2_921600, 2820 pbn_b4_bt_4_921600, 2821 pbn_b4_bt_8_921600, 2822 2823 /* 2824 * Board-specific versions. 2825 */ 2826 pbn_panacom, 2827 pbn_panacom2, 2828 pbn_panacom4, 2829 pbn_plx_romulus, 2830 pbn_oxsemi, 2831 pbn_oxsemi_1_15625000, 2832 pbn_oxsemi_2_15625000, 2833 pbn_oxsemi_4_15625000, 2834 pbn_oxsemi_8_15625000, 2835 pbn_intel_i960, 2836 pbn_sgi_ioc3, 2837 pbn_computone_4, 2838 pbn_computone_6, 2839 pbn_computone_8, 2840 pbn_sbsxrsio, 2841 pbn_pasemi_1682M, 2842 pbn_ni8430_2, 2843 pbn_ni8430_4, 2844 pbn_ni8430_8, 2845 pbn_ni8430_16, 2846 pbn_ADDIDATA_PCIe_1_3906250, 2847 pbn_ADDIDATA_PCIe_2_3906250, 2848 pbn_ADDIDATA_PCIe_4_3906250, 2849 pbn_ADDIDATA_PCIe_8_3906250, 2850 pbn_ce4100_1_115200, 2851 pbn_omegapci, 2852 pbn_NETMOS9900_2s_115200, 2853 pbn_brcm_trumanage, 2854 pbn_fintek_4, 2855 pbn_fintek_8, 2856 pbn_fintek_12, 2857 pbn_fintek_F81504A, 2858 pbn_fintek_F81508A, 2859 pbn_fintek_F81512A, 2860 pbn_wch382_2, 2861 pbn_wch384_4, 2862 pbn_wch384_8, 2863 pbn_sunix_pci_1s, 2864 pbn_sunix_pci_2s, 2865 pbn_sunix_pci_4s, 2866 pbn_sunix_pci_8s, 2867 pbn_sunix_pci_16s, 2868 pbn_titan_1_4000000, 2869 pbn_titan_2_4000000, 2870 pbn_titan_4_4000000, 2871 pbn_titan_8_4000000, 2872 pbn_moxa8250_2p, 2873 pbn_moxa8250_4p, 2874 pbn_moxa8250_8p, 2875 }; 2876 2877 /* 2878 * uart_offset - the space between channels 2879 * reg_shift - describes how the UART registers are mapped 2880 * to PCI memory by the card. 2881 * For example IER register on SBS, Inc. PMC-OctPro is located at 2882 * offset 0x10 from the UART base, while UART_IER is defined as 1 2883 * in include/linux/serial_reg.h, 2884 * see first lines of serial_in() and serial_out() in 8250.c 2885 */ 2886 2887 static struct pciserial_board pci_boards[] = { 2888 [pbn_default] = { 2889 .flags = FL_BASE0, 2890 .num_ports = 1, 2891 .base_baud = 115200, 2892 .uart_offset = 8, 2893 }, 2894 [pbn_b0_1_115200] = { 2895 .flags = FL_BASE0, 2896 .num_ports = 1, 2897 .base_baud = 115200, 2898 .uart_offset = 8, 2899 }, 2900 [pbn_b0_2_115200] = { 2901 .flags = FL_BASE0, 2902 .num_ports = 2, 2903 .base_baud = 115200, 2904 .uart_offset = 8, 2905 }, 2906 [pbn_b0_4_115200] = { 2907 .flags = FL_BASE0, 2908 .num_ports = 4, 2909 .base_baud = 115200, 2910 .uart_offset = 8, 2911 }, 2912 [pbn_b0_5_115200] = { 2913 .flags = FL_BASE0, 2914 .num_ports = 5, 2915 .base_baud = 115200, 2916 .uart_offset = 8, 2917 }, 2918 [pbn_b0_8_115200] = { 2919 .flags = FL_BASE0, 2920 .num_ports = 8, 2921 .base_baud = 115200, 2922 .uart_offset = 8, 2923 }, 2924 [pbn_b0_1_921600] = { 2925 .flags = FL_BASE0, 2926 .num_ports = 1, 2927 .base_baud = 921600, 2928 .uart_offset = 8, 2929 }, 2930 [pbn_b0_2_921600] = { 2931 .flags = FL_BASE0, 2932 .num_ports = 2, 2933 .base_baud = 921600, 2934 .uart_offset = 8, 2935 }, 2936 [pbn_b0_4_921600] = { 2937 .flags = FL_BASE0, 2938 .num_ports = 4, 2939 .base_baud = 921600, 2940 .uart_offset = 8, 2941 }, 2942 2943 [pbn_b0_2_1130000] = { 2944 .flags = FL_BASE0, 2945 .num_ports = 2, 2946 .base_baud = 1130000, 2947 .uart_offset = 8, 2948 }, 2949 2950 [pbn_b0_4_1152000] = { 2951 .flags = FL_BASE0, 2952 .num_ports = 4, 2953 .base_baud = 1152000, 2954 .uart_offset = 8, 2955 }, 2956 2957 [pbn_b0_4_1250000] = { 2958 .flags = FL_BASE0, 2959 .num_ports = 4, 2960 .base_baud = 1250000, 2961 .uart_offset = 8, 2962 }, 2963 2964 [pbn_b0_2_1843200] = { 2965 .flags = FL_BASE0, 2966 .num_ports = 2, 2967 .base_baud = 1843200, 2968 .uart_offset = 8, 2969 }, 2970 [pbn_b0_4_1843200] = { 2971 .flags = FL_BASE0, 2972 .num_ports = 4, 2973 .base_baud = 1843200, 2974 .uart_offset = 8, 2975 }, 2976 2977 [pbn_b0_1_15625000] = { 2978 .flags = FL_BASE0, 2979 .num_ports = 1, 2980 .base_baud = 15625000, 2981 .uart_offset = 8, 2982 }, 2983 2984 [pbn_b0_bt_1_115200] = { 2985 .flags = FL_BASE0|FL_BASE_BARS, 2986 .num_ports = 1, 2987 .base_baud = 115200, 2988 .uart_offset = 8, 2989 }, 2990 [pbn_b0_bt_2_115200] = { 2991 .flags = FL_BASE0|FL_BASE_BARS, 2992 .num_ports = 2, 2993 .base_baud = 115200, 2994 .uart_offset = 8, 2995 }, 2996 [pbn_b0_bt_4_115200] = { 2997 .flags = FL_BASE0|FL_BASE_BARS, 2998 .num_ports = 4, 2999 .base_baud = 115200, 3000 .uart_offset = 8, 3001 }, 3002 [pbn_b0_bt_8_115200] = { 3003 .flags = FL_BASE0|FL_BASE_BARS, 3004 .num_ports = 8, 3005 .base_baud = 115200, 3006 .uart_offset = 8, 3007 }, 3008 3009 [pbn_b0_bt_1_460800] = { 3010 .flags = FL_BASE0|FL_BASE_BARS, 3011 .num_ports = 1, 3012 .base_baud = 460800, 3013 .uart_offset = 8, 3014 }, 3015 [pbn_b0_bt_2_460800] = { 3016 .flags = FL_BASE0|FL_BASE_BARS, 3017 .num_ports = 2, 3018 .base_baud = 460800, 3019 .uart_offset = 8, 3020 }, 3021 [pbn_b0_bt_4_460800] = { 3022 .flags = FL_BASE0|FL_BASE_BARS, 3023 .num_ports = 4, 3024 .base_baud = 460800, 3025 .uart_offset = 8, 3026 }, 3027 3028 [pbn_b0_bt_1_921600] = { 3029 .flags = FL_BASE0|FL_BASE_BARS, 3030 .num_ports = 1, 3031 .base_baud = 921600, 3032 .uart_offset = 8, 3033 }, 3034 [pbn_b0_bt_2_921600] = { 3035 .flags = FL_BASE0|FL_BASE_BARS, 3036 .num_ports = 2, 3037 .base_baud = 921600, 3038 .uart_offset = 8, 3039 }, 3040 [pbn_b0_bt_4_921600] = { 3041 .flags = FL_BASE0|FL_BASE_BARS, 3042 .num_ports = 4, 3043 .base_baud = 921600, 3044 .uart_offset = 8, 3045 }, 3046 [pbn_b0_bt_8_921600] = { 3047 .flags = FL_BASE0|FL_BASE_BARS, 3048 .num_ports = 8, 3049 .base_baud = 921600, 3050 .uart_offset = 8, 3051 }, 3052 3053 [pbn_b1_1_115200] = { 3054 .flags = FL_BASE1, 3055 .num_ports = 1, 3056 .base_baud = 115200, 3057 .uart_offset = 8, 3058 }, 3059 [pbn_b1_2_115200] = { 3060 .flags = FL_BASE1, 3061 .num_ports = 2, 3062 .base_baud = 115200, 3063 .uart_offset = 8, 3064 }, 3065 [pbn_b1_4_115200] = { 3066 .flags = FL_BASE1, 3067 .num_ports = 4, 3068 .base_baud = 115200, 3069 .uart_offset = 8, 3070 }, 3071 [pbn_b1_8_115200] = { 3072 .flags = FL_BASE1, 3073 .num_ports = 8, 3074 .base_baud = 115200, 3075 .uart_offset = 8, 3076 }, 3077 [pbn_b1_16_115200] = { 3078 .flags = FL_BASE1, 3079 .num_ports = 16, 3080 .base_baud = 115200, 3081 .uart_offset = 8, 3082 }, 3083 3084 [pbn_b1_1_921600] = { 3085 .flags = FL_BASE1, 3086 .num_ports = 1, 3087 .base_baud = 921600, 3088 .uart_offset = 8, 3089 }, 3090 [pbn_b1_2_921600] = { 3091 .flags = FL_BASE1, 3092 .num_ports = 2, 3093 .base_baud = 921600, 3094 .uart_offset = 8, 3095 }, 3096 [pbn_b1_4_921600] = { 3097 .flags = FL_BASE1, 3098 .num_ports = 4, 3099 .base_baud = 921600, 3100 .uart_offset = 8, 3101 }, 3102 [pbn_b1_8_921600] = { 3103 .flags = FL_BASE1, 3104 .num_ports = 8, 3105 .base_baud = 921600, 3106 .uart_offset = 8, 3107 }, 3108 [pbn_b1_2_1250000] = { 3109 .flags = FL_BASE1, 3110 .num_ports = 2, 3111 .base_baud = 1250000, 3112 .uart_offset = 8, 3113 }, 3114 3115 [pbn_b1_bt_1_115200] = { 3116 .flags = FL_BASE1|FL_BASE_BARS, 3117 .num_ports = 1, 3118 .base_baud = 115200, 3119 .uart_offset = 8, 3120 }, 3121 [pbn_b1_bt_2_115200] = { 3122 .flags = FL_BASE1|FL_BASE_BARS, 3123 .num_ports = 2, 3124 .base_baud = 115200, 3125 .uart_offset = 8, 3126 }, 3127 [pbn_b1_bt_4_115200] = { 3128 .flags = FL_BASE1|FL_BASE_BARS, 3129 .num_ports = 4, 3130 .base_baud = 115200, 3131 .uart_offset = 8, 3132 }, 3133 3134 [pbn_b1_bt_2_921600] = { 3135 .flags = FL_BASE1|FL_BASE_BARS, 3136 .num_ports = 2, 3137 .base_baud = 921600, 3138 .uart_offset = 8, 3139 }, 3140 3141 [pbn_b1_1_1382400] = { 3142 .flags = FL_BASE1, 3143 .num_ports = 1, 3144 .base_baud = 1382400, 3145 .uart_offset = 8, 3146 }, 3147 [pbn_b1_2_1382400] = { 3148 .flags = FL_BASE1, 3149 .num_ports = 2, 3150 .base_baud = 1382400, 3151 .uart_offset = 8, 3152 }, 3153 [pbn_b1_4_1382400] = { 3154 .flags = FL_BASE1, 3155 .num_ports = 4, 3156 .base_baud = 1382400, 3157 .uart_offset = 8, 3158 }, 3159 [pbn_b1_8_1382400] = { 3160 .flags = FL_BASE1, 3161 .num_ports = 8, 3162 .base_baud = 1382400, 3163 .uart_offset = 8, 3164 }, 3165 3166 [pbn_b2_1_115200] = { 3167 .flags = FL_BASE2, 3168 .num_ports = 1, 3169 .base_baud = 115200, 3170 .uart_offset = 8, 3171 }, 3172 [pbn_b2_2_115200] = { 3173 .flags = FL_BASE2, 3174 .num_ports = 2, 3175 .base_baud = 115200, 3176 .uart_offset = 8, 3177 }, 3178 [pbn_b2_4_115200] = { 3179 .flags = FL_BASE2, 3180 .num_ports = 4, 3181 .base_baud = 115200, 3182 .uart_offset = 8, 3183 }, 3184 [pbn_b2_8_115200] = { 3185 .flags = FL_BASE2, 3186 .num_ports = 8, 3187 .base_baud = 115200, 3188 .uart_offset = 8, 3189 }, 3190 3191 [pbn_b2_1_460800] = { 3192 .flags = FL_BASE2, 3193 .num_ports = 1, 3194 .base_baud = 460800, 3195 .uart_offset = 8, 3196 }, 3197 [pbn_b2_4_460800] = { 3198 .flags = FL_BASE2, 3199 .num_ports = 4, 3200 .base_baud = 460800, 3201 .uart_offset = 8, 3202 }, 3203 [pbn_b2_8_460800] = { 3204 .flags = FL_BASE2, 3205 .num_ports = 8, 3206 .base_baud = 460800, 3207 .uart_offset = 8, 3208 }, 3209 [pbn_b2_16_460800] = { 3210 .flags = FL_BASE2, 3211 .num_ports = 16, 3212 .base_baud = 460800, 3213 .uart_offset = 8, 3214 }, 3215 3216 [pbn_b2_1_921600] = { 3217 .flags = FL_BASE2, 3218 .num_ports = 1, 3219 .base_baud = 921600, 3220 .uart_offset = 8, 3221 }, 3222 [pbn_b2_4_921600] = { 3223 .flags = FL_BASE2, 3224 .num_ports = 4, 3225 .base_baud = 921600, 3226 .uart_offset = 8, 3227 }, 3228 [pbn_b2_8_921600] = { 3229 .flags = FL_BASE2, 3230 .num_ports = 8, 3231 .base_baud = 921600, 3232 .uart_offset = 8, 3233 }, 3234 3235 [pbn_b2_8_1152000] = { 3236 .flags = FL_BASE2, 3237 .num_ports = 8, 3238 .base_baud = 1152000, 3239 .uart_offset = 8, 3240 }, 3241 3242 [pbn_b2_bt_1_115200] = { 3243 .flags = FL_BASE2|FL_BASE_BARS, 3244 .num_ports = 1, 3245 .base_baud = 115200, 3246 .uart_offset = 8, 3247 }, 3248 [pbn_b2_bt_2_115200] = { 3249 .flags = FL_BASE2|FL_BASE_BARS, 3250 .num_ports = 2, 3251 .base_baud = 115200, 3252 .uart_offset = 8, 3253 }, 3254 [pbn_b2_bt_4_115200] = { 3255 .flags = FL_BASE2|FL_BASE_BARS, 3256 .num_ports = 4, 3257 .base_baud = 115200, 3258 .uart_offset = 8, 3259 }, 3260 3261 [pbn_b2_bt_2_921600] = { 3262 .flags = FL_BASE2|FL_BASE_BARS, 3263 .num_ports = 2, 3264 .base_baud = 921600, 3265 .uart_offset = 8, 3266 }, 3267 [pbn_b2_bt_4_921600] = { 3268 .flags = FL_BASE2|FL_BASE_BARS, 3269 .num_ports = 4, 3270 .base_baud = 921600, 3271 .uart_offset = 8, 3272 }, 3273 3274 [pbn_b3_2_115200] = { 3275 .flags = FL_BASE3, 3276 .num_ports = 2, 3277 .base_baud = 115200, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b3_4_115200] = { 3281 .flags = FL_BASE3, 3282 .num_ports = 4, 3283 .base_baud = 115200, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b3_8_115200] = { 3287 .flags = FL_BASE3, 3288 .num_ports = 8, 3289 .base_baud = 115200, 3290 .uart_offset = 8, 3291 }, 3292 3293 [pbn_b4_bt_2_921600] = { 3294 .flags = FL_BASE4, 3295 .num_ports = 2, 3296 .base_baud = 921600, 3297 .uart_offset = 8, 3298 }, 3299 [pbn_b4_bt_4_921600] = { 3300 .flags = FL_BASE4, 3301 .num_ports = 4, 3302 .base_baud = 921600, 3303 .uart_offset = 8, 3304 }, 3305 [pbn_b4_bt_8_921600] = { 3306 .flags = FL_BASE4, 3307 .num_ports = 8, 3308 .base_baud = 921600, 3309 .uart_offset = 8, 3310 }, 3311 3312 /* 3313 * Entries following this are board-specific. 3314 */ 3315 3316 /* 3317 * Panacom - IOMEM 3318 */ 3319 [pbn_panacom] = { 3320 .flags = FL_BASE2, 3321 .num_ports = 2, 3322 .base_baud = 921600, 3323 .uart_offset = 0x400, 3324 .reg_shift = 7, 3325 }, 3326 [pbn_panacom2] = { 3327 .flags = FL_BASE2|FL_BASE_BARS, 3328 .num_ports = 2, 3329 .base_baud = 921600, 3330 .uart_offset = 0x400, 3331 .reg_shift = 7, 3332 }, 3333 [pbn_panacom4] = { 3334 .flags = FL_BASE2|FL_BASE_BARS, 3335 .num_ports = 4, 3336 .base_baud = 921600, 3337 .uart_offset = 0x400, 3338 .reg_shift = 7, 3339 }, 3340 3341 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3342 [pbn_plx_romulus] = { 3343 .flags = FL_BASE2, 3344 .num_ports = 4, 3345 .base_baud = 921600, 3346 .uart_offset = 8 << 2, 3347 .reg_shift = 2, 3348 .first_offset = 0x03, 3349 }, 3350 3351 /* 3352 * This board uses the size of PCI Base region 0 to 3353 * signal now many ports are available 3354 */ 3355 [pbn_oxsemi] = { 3356 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3357 .num_ports = 32, 3358 .base_baud = 115200, 3359 .uart_offset = 8, 3360 }, 3361 [pbn_oxsemi_1_15625000] = { 3362 .flags = FL_BASE0, 3363 .num_ports = 1, 3364 .base_baud = 15625000, 3365 .uart_offset = 0x200, 3366 .first_offset = 0x1000, 3367 }, 3368 [pbn_oxsemi_2_15625000] = { 3369 .flags = FL_BASE0, 3370 .num_ports = 2, 3371 .base_baud = 15625000, 3372 .uart_offset = 0x200, 3373 .first_offset = 0x1000, 3374 }, 3375 [pbn_oxsemi_4_15625000] = { 3376 .flags = FL_BASE0, 3377 .num_ports = 4, 3378 .base_baud = 15625000, 3379 .uart_offset = 0x200, 3380 .first_offset = 0x1000, 3381 }, 3382 [pbn_oxsemi_8_15625000] = { 3383 .flags = FL_BASE0, 3384 .num_ports = 8, 3385 .base_baud = 15625000, 3386 .uart_offset = 0x200, 3387 .first_offset = 0x1000, 3388 }, 3389 3390 3391 /* 3392 * EKF addition for i960 Boards form EKF with serial port. 3393 * Max 256 ports. 3394 */ 3395 [pbn_intel_i960] = { 3396 .flags = FL_BASE0, 3397 .num_ports = 32, 3398 .base_baud = 921600, 3399 .uart_offset = 8 << 2, 3400 .reg_shift = 2, 3401 .first_offset = 0x10000, 3402 }, 3403 [pbn_sgi_ioc3] = { 3404 .flags = FL_BASE0|FL_NOIRQ, 3405 .num_ports = 1, 3406 .base_baud = 458333, 3407 .uart_offset = 8, 3408 .reg_shift = 0, 3409 .first_offset = 0x20178, 3410 }, 3411 3412 /* 3413 * Computone - uses IOMEM. 3414 */ 3415 [pbn_computone_4] = { 3416 .flags = FL_BASE0, 3417 .num_ports = 4, 3418 .base_baud = 921600, 3419 .uart_offset = 0x40, 3420 .reg_shift = 2, 3421 .first_offset = 0x200, 3422 }, 3423 [pbn_computone_6] = { 3424 .flags = FL_BASE0, 3425 .num_ports = 6, 3426 .base_baud = 921600, 3427 .uart_offset = 0x40, 3428 .reg_shift = 2, 3429 .first_offset = 0x200, 3430 }, 3431 [pbn_computone_8] = { 3432 .flags = FL_BASE0, 3433 .num_ports = 8, 3434 .base_baud = 921600, 3435 .uart_offset = 0x40, 3436 .reg_shift = 2, 3437 .first_offset = 0x200, 3438 }, 3439 [pbn_sbsxrsio] = { 3440 .flags = FL_BASE0, 3441 .num_ports = 8, 3442 .base_baud = 460800, 3443 .uart_offset = 256, 3444 .reg_shift = 4, 3445 }, 3446 /* 3447 * PA Semi PWRficient PA6T-1682M on-chip UART 3448 */ 3449 [pbn_pasemi_1682M] = { 3450 .flags = FL_BASE0, 3451 .num_ports = 1, 3452 .base_baud = 8333333, 3453 }, 3454 /* 3455 * National Instruments 843x 3456 */ 3457 [pbn_ni8430_16] = { 3458 .flags = FL_BASE0, 3459 .num_ports = 16, 3460 .base_baud = 3686400, 3461 .uart_offset = 0x10, 3462 .first_offset = 0x800, 3463 }, 3464 [pbn_ni8430_8] = { 3465 .flags = FL_BASE0, 3466 .num_ports = 8, 3467 .base_baud = 3686400, 3468 .uart_offset = 0x10, 3469 .first_offset = 0x800, 3470 }, 3471 [pbn_ni8430_4] = { 3472 .flags = FL_BASE0, 3473 .num_ports = 4, 3474 .base_baud = 3686400, 3475 .uart_offset = 0x10, 3476 .first_offset = 0x800, 3477 }, 3478 [pbn_ni8430_2] = { 3479 .flags = FL_BASE0, 3480 .num_ports = 2, 3481 .base_baud = 3686400, 3482 .uart_offset = 0x10, 3483 .first_offset = 0x800, 3484 }, 3485 /* 3486 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3487 */ 3488 [pbn_ADDIDATA_PCIe_1_3906250] = { 3489 .flags = FL_BASE0, 3490 .num_ports = 1, 3491 .base_baud = 3906250, 3492 .uart_offset = 0x200, 3493 .first_offset = 0x1000, 3494 }, 3495 [pbn_ADDIDATA_PCIe_2_3906250] = { 3496 .flags = FL_BASE0, 3497 .num_ports = 2, 3498 .base_baud = 3906250, 3499 .uart_offset = 0x200, 3500 .first_offset = 0x1000, 3501 }, 3502 [pbn_ADDIDATA_PCIe_4_3906250] = { 3503 .flags = FL_BASE0, 3504 .num_ports = 4, 3505 .base_baud = 3906250, 3506 .uart_offset = 0x200, 3507 .first_offset = 0x1000, 3508 }, 3509 [pbn_ADDIDATA_PCIe_8_3906250] = { 3510 .flags = FL_BASE0, 3511 .num_ports = 8, 3512 .base_baud = 3906250, 3513 .uart_offset = 0x200, 3514 .first_offset = 0x1000, 3515 }, 3516 [pbn_ce4100_1_115200] = { 3517 .flags = FL_BASE_BARS, 3518 .num_ports = 2, 3519 .base_baud = 921600, 3520 .reg_shift = 2, 3521 }, 3522 [pbn_omegapci] = { 3523 .flags = FL_BASE0, 3524 .num_ports = 8, 3525 .base_baud = 115200, 3526 .uart_offset = 0x200, 3527 }, 3528 [pbn_NETMOS9900_2s_115200] = { 3529 .flags = FL_BASE0, 3530 .num_ports = 2, 3531 .base_baud = 115200, 3532 }, 3533 [pbn_brcm_trumanage] = { 3534 .flags = FL_BASE0, 3535 .num_ports = 1, 3536 .reg_shift = 2, 3537 .base_baud = 115200, 3538 }, 3539 [pbn_fintek_4] = { 3540 .num_ports = 4, 3541 .uart_offset = 8, 3542 .base_baud = 115200, 3543 .first_offset = 0x40, 3544 }, 3545 [pbn_fintek_8] = { 3546 .num_ports = 8, 3547 .uart_offset = 8, 3548 .base_baud = 115200, 3549 .first_offset = 0x40, 3550 }, 3551 [pbn_fintek_12] = { 3552 .num_ports = 12, 3553 .uart_offset = 8, 3554 .base_baud = 115200, 3555 .first_offset = 0x40, 3556 }, 3557 [pbn_fintek_F81504A] = { 3558 .num_ports = 4, 3559 .uart_offset = 8, 3560 .base_baud = 115200, 3561 }, 3562 [pbn_fintek_F81508A] = { 3563 .num_ports = 8, 3564 .uart_offset = 8, 3565 .base_baud = 115200, 3566 }, 3567 [pbn_fintek_F81512A] = { 3568 .num_ports = 12, 3569 .uart_offset = 8, 3570 .base_baud = 115200, 3571 }, 3572 [pbn_wch382_2] = { 3573 .flags = FL_BASE0, 3574 .num_ports = 2, 3575 .base_baud = 115200, 3576 .uart_offset = 8, 3577 .first_offset = 0xC0, 3578 }, 3579 [pbn_wch384_4] = { 3580 .flags = FL_BASE0, 3581 .num_ports = 4, 3582 .base_baud = 115200, 3583 .uart_offset = 8, 3584 .first_offset = 0xC0, 3585 }, 3586 [pbn_wch384_8] = { 3587 .flags = FL_BASE0, 3588 .num_ports = 8, 3589 .base_baud = 115200, 3590 .uart_offset = 8, 3591 .first_offset = 0x00, 3592 }, 3593 [pbn_sunix_pci_1s] = { 3594 .num_ports = 1, 3595 .base_baud = 921600, 3596 .uart_offset = 0x8, 3597 }, 3598 [pbn_sunix_pci_2s] = { 3599 .num_ports = 2, 3600 .base_baud = 921600, 3601 .uart_offset = 0x8, 3602 }, 3603 [pbn_sunix_pci_4s] = { 3604 .num_ports = 4, 3605 .base_baud = 921600, 3606 .uart_offset = 0x8, 3607 }, 3608 [pbn_sunix_pci_8s] = { 3609 .num_ports = 8, 3610 .base_baud = 921600, 3611 .uart_offset = 0x8, 3612 }, 3613 [pbn_sunix_pci_16s] = { 3614 .num_ports = 16, 3615 .base_baud = 921600, 3616 .uart_offset = 0x8, 3617 }, 3618 [pbn_titan_1_4000000] = { 3619 .flags = FL_BASE0, 3620 .num_ports = 1, 3621 .base_baud = 4000000, 3622 .uart_offset = 0x200, 3623 .first_offset = 0x1000, 3624 }, 3625 [pbn_titan_2_4000000] = { 3626 .flags = FL_BASE0, 3627 .num_ports = 2, 3628 .base_baud = 4000000, 3629 .uart_offset = 0x200, 3630 .first_offset = 0x1000, 3631 }, 3632 [pbn_titan_4_4000000] = { 3633 .flags = FL_BASE0, 3634 .num_ports = 4, 3635 .base_baud = 4000000, 3636 .uart_offset = 0x200, 3637 .first_offset = 0x1000, 3638 }, 3639 [pbn_titan_8_4000000] = { 3640 .flags = FL_BASE0, 3641 .num_ports = 8, 3642 .base_baud = 4000000, 3643 .uart_offset = 0x200, 3644 .first_offset = 0x1000, 3645 }, 3646 [pbn_moxa8250_2p] = { 3647 .flags = FL_BASE1, 3648 .num_ports = 2, 3649 .base_baud = 921600, 3650 .uart_offset = 0x200, 3651 }, 3652 [pbn_moxa8250_4p] = { 3653 .flags = FL_BASE1, 3654 .num_ports = 4, 3655 .base_baud = 921600, 3656 .uart_offset = 0x200, 3657 }, 3658 [pbn_moxa8250_8p] = { 3659 .flags = FL_BASE1, 3660 .num_ports = 8, 3661 .base_baud = 921600, 3662 .uart_offset = 0x200, 3663 }, 3664 }; 3665 3666 #define REPORT_CONFIG(option) \ 3667 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 3668 #define REPORT_8250_CONFIG(option) \ 3669 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 3670 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 3671 3672 static const struct pci_device_id blacklist[] = { 3673 /* softmodems */ 3674 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3675 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3676 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3677 3678 /* multi-io cards handled by parport_serial */ 3679 /* WCH CH353 2S1P */ 3680 { PCI_DEVICE(0x4348, 0x7053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3681 /* WCH CH353 1S1P */ 3682 { PCI_DEVICE(0x4348, 0x5053), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3683 /* WCH CH382 2S1P */ 3684 { PCI_DEVICE(0x1c00, 0x3250), 0, 0, REPORT_CONFIG(PARPORT_SERIAL), }, 3685 3686 /* Intel platforms with MID UART */ 3687 { PCI_VDEVICE(INTEL, 0x081b), REPORT_8250_CONFIG(MID), }, 3688 { PCI_VDEVICE(INTEL, 0x081c), REPORT_8250_CONFIG(MID), }, 3689 { PCI_VDEVICE(INTEL, 0x081d), REPORT_8250_CONFIG(MID), }, 3690 { PCI_VDEVICE(INTEL, 0x1191), REPORT_8250_CONFIG(MID), }, 3691 { PCI_VDEVICE(INTEL, 0x18d8), REPORT_8250_CONFIG(MID), }, 3692 { PCI_VDEVICE(INTEL, 0x19d8), REPORT_8250_CONFIG(MID), }, 3693 3694 /* Intel platforms with DesignWare UART */ 3695 { PCI_VDEVICE(INTEL, 0x0936), REPORT_8250_CONFIG(LPSS), }, 3696 { PCI_VDEVICE(INTEL, 0x0f0a), REPORT_8250_CONFIG(LPSS), }, 3697 { PCI_VDEVICE(INTEL, 0x0f0c), REPORT_8250_CONFIG(LPSS), }, 3698 { PCI_VDEVICE(INTEL, 0x228a), REPORT_8250_CONFIG(LPSS), }, 3699 { PCI_VDEVICE(INTEL, 0x228c), REPORT_8250_CONFIG(LPSS), }, 3700 { PCI_VDEVICE(INTEL, 0x4b96), REPORT_8250_CONFIG(LPSS), }, 3701 { PCI_VDEVICE(INTEL, 0x4b97), REPORT_8250_CONFIG(LPSS), }, 3702 { PCI_VDEVICE(INTEL, 0x4b98), REPORT_8250_CONFIG(LPSS), }, 3703 { PCI_VDEVICE(INTEL, 0x4b99), REPORT_8250_CONFIG(LPSS), }, 3704 { PCI_VDEVICE(INTEL, 0x4b9a), REPORT_8250_CONFIG(LPSS), }, 3705 { PCI_VDEVICE(INTEL, 0x4b9b), REPORT_8250_CONFIG(LPSS), }, 3706 { PCI_VDEVICE(INTEL, 0x9ce3), REPORT_8250_CONFIG(LPSS), }, 3707 { PCI_VDEVICE(INTEL, 0x9ce4), REPORT_8250_CONFIG(LPSS), }, 3708 3709 /* Exar devices */ 3710 { PCI_VDEVICE(EXAR, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3711 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), REPORT_8250_CONFIG(EXAR), }, 3712 3713 /* Pericom devices */ 3714 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3715 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), REPORT_8250_CONFIG(PERICOM), }, 3716 3717 /* End of the black list */ 3718 { } 3719 }; 3720 3721 static int serial_pci_is_class_communication(struct pci_dev *dev) 3722 { 3723 /* 3724 * If it is not a communications device or the programming 3725 * interface is greater than 6, give up. 3726 */ 3727 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3728 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3729 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3730 (dev->class & 0xff) > 6) 3731 return -ENODEV; 3732 3733 return 0; 3734 } 3735 3736 /* 3737 * Given a complete unknown PCI device, try to use some heuristics to 3738 * guess what the configuration might be, based on the pitiful PCI 3739 * serial specs. Returns 0 on success, -ENODEV on failure. 3740 */ 3741 static int 3742 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3743 { 3744 int num_iomem, num_port, first_port = -1, i; 3745 int rc; 3746 3747 rc = serial_pci_is_class_communication(dev); 3748 if (rc) 3749 return rc; 3750 3751 /* 3752 * Should we try to make guesses for multiport serial devices later? 3753 */ 3754 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3755 return -ENODEV; 3756 3757 num_iomem = num_port = 0; 3758 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3759 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3760 num_port++; 3761 if (first_port == -1) 3762 first_port = i; 3763 } 3764 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3765 num_iomem++; 3766 } 3767 3768 /* 3769 * If there is 1 or 0 iomem regions, and exactly one port, 3770 * use it. We guess the number of ports based on the IO 3771 * region size. 3772 */ 3773 if (num_iomem <= 1 && num_port == 1) { 3774 board->flags = first_port; 3775 board->num_ports = pci_resource_len(dev, first_port) / 8; 3776 return 0; 3777 } 3778 3779 /* 3780 * Now guess if we've got a board which indexes by BARs. 3781 * Each IO BAR should be 8 bytes, and they should follow 3782 * consecutively. 3783 */ 3784 first_port = -1; 3785 num_port = 0; 3786 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3787 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3788 pci_resource_len(dev, i) == 8 && 3789 (first_port == -1 || (first_port + num_port) == i)) { 3790 num_port++; 3791 if (first_port == -1) 3792 first_port = i; 3793 } 3794 } 3795 3796 if (num_port > 1) { 3797 board->flags = first_port | FL_BASE_BARS; 3798 board->num_ports = num_port; 3799 return 0; 3800 } 3801 3802 return -ENODEV; 3803 } 3804 3805 static inline int 3806 serial_pci_matches(const struct pciserial_board *board, 3807 const struct pciserial_board *guessed) 3808 { 3809 return 3810 board->num_ports == guessed->num_ports && 3811 board->base_baud == guessed->base_baud && 3812 board->uart_offset == guessed->uart_offset && 3813 board->reg_shift == guessed->reg_shift && 3814 board->first_offset == guessed->first_offset; 3815 } 3816 3817 struct serial_private * 3818 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3819 { 3820 struct uart_8250_port uart; 3821 struct serial_private *priv; 3822 struct pci_serial_quirk *quirk; 3823 int rc, nr_ports, i; 3824 3825 nr_ports = board->num_ports; 3826 3827 /* 3828 * Find an init and setup quirks. 3829 */ 3830 quirk = find_quirk(dev); 3831 3832 /* 3833 * Run the new-style initialization function. 3834 * The initialization function returns: 3835 * <0 - error 3836 * 0 - use board->num_ports 3837 * >0 - number of ports 3838 */ 3839 if (quirk->init) { 3840 rc = quirk->init(dev); 3841 if (rc < 0) { 3842 priv = ERR_PTR(rc); 3843 goto err_out; 3844 } 3845 if (rc) 3846 nr_ports = rc; 3847 } 3848 3849 priv = kzalloc(struct_size(priv, line, nr_ports), GFP_KERNEL); 3850 if (!priv) { 3851 priv = ERR_PTR(-ENOMEM); 3852 goto err_deinit; 3853 } 3854 3855 priv->dev = dev; 3856 priv->quirk = quirk; 3857 3858 memset(&uart, 0, sizeof(uart)); 3859 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3860 uart.port.uartclk = board->base_baud * 16; 3861 3862 if (board->flags & FL_NOIRQ) { 3863 uart.port.irq = 0; 3864 } else { 3865 if (pci_match_id(pci_use_msi, dev)) { 3866 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 3867 pci_set_master(dev); 3868 uart.port.flags &= ~UPF_SHARE_IRQ; 3869 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3870 } else { 3871 pci_dbg(dev, "Using legacy interrupts\n"); 3872 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3873 } 3874 if (rc < 0) { 3875 kfree(priv); 3876 priv = ERR_PTR(rc); 3877 goto err_deinit; 3878 } 3879 3880 uart.port.irq = pci_irq_vector(dev, 0); 3881 } 3882 3883 uart.port.dev = &dev->dev; 3884 3885 for (i = 0; i < nr_ports; i++) { 3886 if (quirk->setup(priv, board, &uart, i)) 3887 break; 3888 3889 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3890 uart.port.iobase, uart.port.irq, uart.port.iotype); 3891 3892 priv->line[i] = serial8250_register_8250_port(&uart); 3893 if (priv->line[i] < 0) { 3894 pci_err(dev, 3895 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3896 uart.port.iobase, uart.port.irq, 3897 uart.port.iotype, priv->line[i]); 3898 break; 3899 } 3900 } 3901 priv->nr = i; 3902 priv->board = board; 3903 return priv; 3904 3905 err_deinit: 3906 if (quirk->exit) 3907 quirk->exit(dev); 3908 err_out: 3909 return priv; 3910 } 3911 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3912 3913 static void pciserial_detach_ports(struct serial_private *priv) 3914 { 3915 struct pci_serial_quirk *quirk; 3916 int i; 3917 3918 for (i = 0; i < priv->nr; i++) 3919 serial8250_unregister_port(priv->line[i]); 3920 3921 /* 3922 * Find the exit quirks. 3923 */ 3924 quirk = find_quirk(priv->dev); 3925 if (quirk->exit) 3926 quirk->exit(priv->dev); 3927 } 3928 3929 void pciserial_remove_ports(struct serial_private *priv) 3930 { 3931 pciserial_detach_ports(priv); 3932 kfree(priv); 3933 } 3934 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3935 3936 void pciserial_suspend_ports(struct serial_private *priv) 3937 { 3938 int i; 3939 3940 for (i = 0; i < priv->nr; i++) 3941 if (priv->line[i] >= 0) 3942 serial8250_suspend_port(priv->line[i]); 3943 3944 /* 3945 * Ensure that every init quirk is properly torn down 3946 */ 3947 if (priv->quirk->exit) 3948 priv->quirk->exit(priv->dev); 3949 } 3950 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3951 3952 void pciserial_resume_ports(struct serial_private *priv) 3953 { 3954 int i; 3955 3956 /* 3957 * Ensure that the board is correctly configured. 3958 */ 3959 if (priv->quirk->init) 3960 priv->quirk->init(priv->dev); 3961 3962 for (i = 0; i < priv->nr; i++) 3963 if (priv->line[i] >= 0) 3964 serial8250_resume_port(priv->line[i]); 3965 } 3966 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3967 3968 /* 3969 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3970 * to the arrangement of serial ports on a PCI card. 3971 */ 3972 static int 3973 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3974 { 3975 struct pci_serial_quirk *quirk; 3976 struct serial_private *priv; 3977 const struct pciserial_board *board; 3978 const struct pci_device_id *exclude; 3979 struct pciserial_board tmp; 3980 int rc; 3981 3982 quirk = find_quirk(dev); 3983 if (quirk->probe) { 3984 rc = quirk->probe(dev); 3985 if (rc) 3986 return rc; 3987 } 3988 3989 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3990 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 3991 return -EINVAL; 3992 } 3993 3994 board = &pci_boards[ent->driver_data]; 3995 3996 exclude = pci_match_id(blacklist, dev); 3997 if (exclude) { 3998 if (exclude->driver_data) 3999 pci_warn(dev, "ignoring port, enable %s to handle\n", 4000 (const char *)exclude->driver_data); 4001 return -ENODEV; 4002 } 4003 4004 rc = pcim_enable_device(dev); 4005 pci_save_state(dev); 4006 if (rc) 4007 return rc; 4008 4009 if (ent->driver_data == pbn_default) { 4010 /* 4011 * Use a copy of the pci_board entry for this; 4012 * avoid changing entries in the table. 4013 */ 4014 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4015 board = &tmp; 4016 4017 /* 4018 * We matched one of our class entries. Try to 4019 * determine the parameters of this board. 4020 */ 4021 rc = serial_pci_guess_board(dev, &tmp); 4022 if (rc) 4023 return rc; 4024 } else { 4025 /* 4026 * We matched an explicit entry. If we are able to 4027 * detect this boards settings with our heuristic, 4028 * then we no longer need this entry. 4029 */ 4030 memcpy(&tmp, &pci_boards[pbn_default], 4031 sizeof(struct pciserial_board)); 4032 rc = serial_pci_guess_board(dev, &tmp); 4033 if (rc == 0 && serial_pci_matches(board, &tmp)) 4034 moan_device("Redundant entry in serial pci_table.", 4035 dev); 4036 } 4037 4038 priv = pciserial_init_ports(dev, board); 4039 if (IS_ERR(priv)) 4040 return PTR_ERR(priv); 4041 4042 pci_set_drvdata(dev, priv); 4043 return 0; 4044 } 4045 4046 static void pciserial_remove_one(struct pci_dev *dev) 4047 { 4048 struct serial_private *priv = pci_get_drvdata(dev); 4049 4050 pciserial_remove_ports(priv); 4051 } 4052 4053 #ifdef CONFIG_PM_SLEEP 4054 static int pciserial_suspend_one(struct device *dev) 4055 { 4056 struct serial_private *priv = dev_get_drvdata(dev); 4057 4058 if (priv) 4059 pciserial_suspend_ports(priv); 4060 4061 return 0; 4062 } 4063 4064 static int pciserial_resume_one(struct device *dev) 4065 { 4066 struct pci_dev *pdev = to_pci_dev(dev); 4067 struct serial_private *priv = pci_get_drvdata(pdev); 4068 int err; 4069 4070 if (priv) { 4071 /* 4072 * The device may have been disabled. Re-enable it. 4073 */ 4074 err = pci_enable_device(pdev); 4075 /* FIXME: We cannot simply error out here */ 4076 if (err) 4077 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4078 pciserial_resume_ports(priv); 4079 } 4080 return 0; 4081 } 4082 #endif 4083 4084 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4085 pciserial_resume_one); 4086 4087 static const struct pci_device_id serial_pci_tbl[] = { 4088 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4089 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4090 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4091 pbn_b2_8_921600 }, 4092 /* Advantech also use 0x3618 and 0xf618 */ 4093 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4094 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4095 pbn_b0_4_921600 }, 4096 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4097 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4098 pbn_b0_4_921600 }, 4099 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4100 PCI_SUBVENDOR_ID_CONNECT_TECH, 4101 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4102 pbn_b1_8_1382400 }, 4103 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4104 PCI_SUBVENDOR_ID_CONNECT_TECH, 4105 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4106 pbn_b1_4_1382400 }, 4107 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4108 PCI_SUBVENDOR_ID_CONNECT_TECH, 4109 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4110 pbn_b1_2_1382400 }, 4111 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4112 PCI_SUBVENDOR_ID_CONNECT_TECH, 4113 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4114 pbn_b1_8_1382400 }, 4115 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4116 PCI_SUBVENDOR_ID_CONNECT_TECH, 4117 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4118 pbn_b1_4_1382400 }, 4119 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4120 PCI_SUBVENDOR_ID_CONNECT_TECH, 4121 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4122 pbn_b1_2_1382400 }, 4123 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4124 PCI_SUBVENDOR_ID_CONNECT_TECH, 4125 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4126 pbn_b1_8_921600 }, 4127 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4128 PCI_SUBVENDOR_ID_CONNECT_TECH, 4129 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4130 pbn_b1_8_921600 }, 4131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4132 PCI_SUBVENDOR_ID_CONNECT_TECH, 4133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4134 pbn_b1_4_921600 }, 4135 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4136 PCI_SUBVENDOR_ID_CONNECT_TECH, 4137 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4138 pbn_b1_4_921600 }, 4139 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4140 PCI_SUBVENDOR_ID_CONNECT_TECH, 4141 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4142 pbn_b1_2_921600 }, 4143 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4144 PCI_SUBVENDOR_ID_CONNECT_TECH, 4145 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4146 pbn_b1_8_921600 }, 4147 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4148 PCI_SUBVENDOR_ID_CONNECT_TECH, 4149 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4150 pbn_b1_8_921600 }, 4151 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4152 PCI_SUBVENDOR_ID_CONNECT_TECH, 4153 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4154 pbn_b1_4_921600 }, 4155 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4156 PCI_SUBVENDOR_ID_CONNECT_TECH, 4157 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4158 pbn_b1_2_1250000 }, 4159 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4160 PCI_SUBVENDOR_ID_CONNECT_TECH, 4161 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4162 pbn_b0_2_1843200 }, 4163 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4164 PCI_SUBVENDOR_ID_CONNECT_TECH, 4165 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4166 pbn_b0_4_1843200 }, 4167 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4168 PCI_VENDOR_ID_AFAVLAB, 4169 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4170 pbn_b0_4_1152000 }, 4171 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4173 pbn_b2_bt_1_115200 }, 4174 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4176 pbn_b2_bt_2_115200 }, 4177 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4179 pbn_b2_bt_4_115200 }, 4180 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4182 pbn_b2_bt_2_115200 }, 4183 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4185 pbn_b2_bt_4_115200 }, 4186 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4188 pbn_b2_8_115200 }, 4189 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4191 pbn_b2_8_460800 }, 4192 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4194 pbn_b2_8_115200 }, 4195 4196 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4198 pbn_b2_bt_2_115200 }, 4199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4201 pbn_b2_bt_2_921600 }, 4202 /* 4203 * VScom SPCOM800, from sl@s.pl 4204 */ 4205 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4207 pbn_b2_8_921600 }, 4208 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4210 pbn_b2_4_921600 }, 4211 /* Unknown card - subdevice 0x1584 */ 4212 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4213 PCI_VENDOR_ID_PLX, 4214 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4215 pbn_b2_4_115200 }, 4216 /* Unknown card - subdevice 0x1588 */ 4217 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4218 PCI_VENDOR_ID_PLX, 4219 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4220 pbn_b2_8_115200 }, 4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4222 PCI_SUBVENDOR_ID_KEYSPAN, 4223 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4224 pbn_panacom }, 4225 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4227 pbn_panacom4 }, 4228 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4230 pbn_panacom2 }, 4231 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4232 PCI_VENDOR_ID_ESDGMBH, 4233 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4234 pbn_b2_4_115200 }, 4235 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4236 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4237 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4238 pbn_b2_4_460800 }, 4239 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4240 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4241 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4242 pbn_b2_8_460800 }, 4243 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4244 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4245 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4246 pbn_b2_16_460800 }, 4247 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4248 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4249 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4250 pbn_b2_16_460800 }, 4251 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4252 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4253 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4254 pbn_b2_4_460800 }, 4255 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4256 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4257 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4258 pbn_b2_8_460800 }, 4259 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4260 PCI_SUBVENDOR_ID_EXSYS, 4261 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4262 pbn_b2_4_115200 }, 4263 /* 4264 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4265 * (Exoray@isys.ca) 4266 */ 4267 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4268 0x10b5, 0x106a, 0, 0, 4269 pbn_plx_romulus }, 4270 /* 4271 * Quatech cards. These actually have configurable clocks but for 4272 * now we just use the default. 4273 * 4274 * 100 series are RS232, 200 series RS422, 4275 */ 4276 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4278 pbn_b1_4_115200 }, 4279 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4281 pbn_b1_2_115200 }, 4282 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4284 pbn_b2_2_115200 }, 4285 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4287 pbn_b1_2_115200 }, 4288 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4290 pbn_b2_2_115200 }, 4291 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4293 pbn_b1_4_115200 }, 4294 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4296 pbn_b1_8_115200 }, 4297 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4299 pbn_b1_8_115200 }, 4300 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4302 pbn_b1_4_115200 }, 4303 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4305 pbn_b1_2_115200 }, 4306 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4308 pbn_b1_4_115200 }, 4309 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4311 pbn_b1_2_115200 }, 4312 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4314 pbn_b2_4_115200 }, 4315 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4317 pbn_b2_2_115200 }, 4318 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4320 pbn_b2_1_115200 }, 4321 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4323 pbn_b2_4_115200 }, 4324 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4326 pbn_b2_2_115200 }, 4327 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4329 pbn_b2_1_115200 }, 4330 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4332 pbn_b0_8_115200 }, 4333 4334 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4335 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4336 0, 0, 4337 pbn_b0_4_921600 }, 4338 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4339 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4340 0, 0, 4341 pbn_b0_4_1152000 }, 4342 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4344 pbn_b0_bt_2_921600 }, 4345 4346 /* 4347 * The below card is a little controversial since it is the 4348 * subject of a PCI vendor/device ID clash. (See 4349 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4350 * For now just used the hex ID 0x950a. 4351 */ 4352 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4353 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4354 0, 0, pbn_b0_2_115200 }, 4355 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4356 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4357 0, 0, pbn_b0_2_115200 }, 4358 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4360 pbn_b0_2_1130000 }, 4361 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4362 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4363 pbn_b0_1_921600 }, 4364 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4366 pbn_b0_4_115200 }, 4367 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4369 pbn_b0_bt_2_921600 }, 4370 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4372 pbn_b2_8_1152000 }, 4373 4374 /* 4375 * Oxford Semiconductor Inc. Tornado PCI express device range. 4376 */ 4377 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b0_1_15625000 }, 4380 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b0_1_15625000 }, 4383 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4385 pbn_oxsemi_1_15625000 }, 4386 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_oxsemi_1_15625000 }, 4389 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b0_1_15625000 }, 4392 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b0_1_15625000 }, 4395 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4397 pbn_oxsemi_1_15625000 }, 4398 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4400 pbn_oxsemi_1_15625000 }, 4401 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b0_1_15625000 }, 4404 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b0_1_15625000 }, 4407 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b0_1_15625000 }, 4410 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b0_1_15625000 }, 4413 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_oxsemi_2_15625000 }, 4416 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_oxsemi_2_15625000 }, 4419 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_oxsemi_4_15625000 }, 4422 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_oxsemi_4_15625000 }, 4425 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_oxsemi_8_15625000 }, 4428 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_oxsemi_8_15625000 }, 4431 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_oxsemi_1_15625000 }, 4434 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_oxsemi_1_15625000 }, 4437 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_oxsemi_1_15625000 }, 4440 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_oxsemi_1_15625000 }, 4443 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_oxsemi_1_15625000 }, 4446 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_oxsemi_1_15625000 }, 4449 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_oxsemi_1_15625000 }, 4452 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4454 pbn_oxsemi_1_15625000 }, 4455 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4457 pbn_oxsemi_1_15625000 }, 4458 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4460 pbn_oxsemi_1_15625000 }, 4461 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_oxsemi_1_15625000 }, 4464 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_oxsemi_1_15625000 }, 4467 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_oxsemi_1_15625000 }, 4470 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_oxsemi_1_15625000 }, 4473 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_oxsemi_1_15625000 }, 4476 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_oxsemi_1_15625000 }, 4479 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_oxsemi_1_15625000 }, 4482 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_oxsemi_1_15625000 }, 4485 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_oxsemi_1_15625000 }, 4488 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4490 pbn_oxsemi_1_15625000 }, 4491 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4493 pbn_oxsemi_1_15625000 }, 4494 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4496 pbn_oxsemi_1_15625000 }, 4497 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4499 pbn_oxsemi_1_15625000 }, 4500 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4502 pbn_oxsemi_1_15625000 }, 4503 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4505 pbn_oxsemi_1_15625000 }, 4506 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4508 pbn_oxsemi_1_15625000 }, 4509 /* 4510 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4511 */ 4512 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4513 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4514 pbn_oxsemi_1_15625000 }, 4515 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4516 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4517 pbn_oxsemi_2_15625000 }, 4518 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4519 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4520 pbn_oxsemi_4_15625000 }, 4521 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4522 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4523 pbn_oxsemi_8_15625000 }, 4524 4525 /* 4526 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4527 */ 4528 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4529 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4530 pbn_oxsemi_2_15625000 }, 4531 /* 4532 * EndRun Technologies. PCI express device range. 4533 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4534 */ 4535 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4537 pbn_oxsemi_2_15625000 }, 4538 4539 /* 4540 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4541 * from skokodyn@yahoo.com 4542 */ 4543 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4544 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4545 pbn_sbsxrsio }, 4546 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4547 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4548 pbn_sbsxrsio }, 4549 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4550 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4551 pbn_sbsxrsio }, 4552 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4553 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4554 pbn_sbsxrsio }, 4555 4556 /* 4557 * Digitan DS560-558, from jimd@esoft.com 4558 */ 4559 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4561 pbn_b1_1_115200 }, 4562 4563 /* 4564 * Titan Electronic cards 4565 * The 400L and 800L have a custom setup quirk. 4566 */ 4567 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4569 pbn_b0_1_921600 }, 4570 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4572 pbn_b0_2_921600 }, 4573 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4575 pbn_b0_4_921600 }, 4576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4578 pbn_b0_4_921600 }, 4579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4581 pbn_b1_1_921600 }, 4582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4584 pbn_b1_bt_2_921600 }, 4585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4587 pbn_b0_bt_4_921600 }, 4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4590 pbn_b0_bt_8_921600 }, 4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4593 pbn_b4_bt_2_921600 }, 4594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4596 pbn_b4_bt_4_921600 }, 4597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4599 pbn_b4_bt_8_921600 }, 4600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4602 pbn_b0_4_921600 }, 4603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4605 pbn_b0_4_921600 }, 4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4608 pbn_b0_4_921600 }, 4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4611 pbn_titan_1_4000000 }, 4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4614 pbn_titan_2_4000000 }, 4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4617 pbn_titan_4_4000000 }, 4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4620 pbn_titan_8_4000000 }, 4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4623 pbn_titan_2_4000000 }, 4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4626 pbn_titan_2_4000000 }, 4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4629 pbn_b0_bt_2_921600 }, 4630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4632 pbn_b0_4_921600 }, 4633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4635 pbn_b0_4_921600 }, 4636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4638 pbn_b0_4_921600 }, 4639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4641 pbn_b0_4_921600 }, 4642 4643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_b2_1_460800 }, 4646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_b2_1_460800 }, 4649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_b2_1_460800 }, 4652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b2_bt_2_921600 }, 4655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_b2_bt_2_921600 }, 4658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_b2_bt_2_921600 }, 4661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_b2_bt_4_921600 }, 4664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b2_bt_4_921600 }, 4667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_b2_bt_4_921600 }, 4670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_b0_1_921600 }, 4673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_b0_1_921600 }, 4676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b0_1_921600 }, 4679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_b0_bt_2_921600 }, 4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_b0_bt_2_921600 }, 4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_b0_bt_2_921600 }, 4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_b0_bt_4_921600 }, 4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_b0_bt_4_921600 }, 4694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_b0_bt_4_921600 }, 4697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_b0_bt_8_921600 }, 4700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_b0_bt_8_921600 }, 4703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_b0_bt_8_921600 }, 4706 4707 /* 4708 * Computone devices submitted by Doug McNash dmcnash@computone.com 4709 */ 4710 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4711 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4712 0, 0, pbn_computone_4 }, 4713 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4714 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4715 0, 0, pbn_computone_8 }, 4716 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4717 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4718 0, 0, pbn_computone_6 }, 4719 4720 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4722 pbn_oxsemi }, 4723 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4724 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4725 pbn_b0_bt_1_921600 }, 4726 4727 /* 4728 * Sunix PCI serial boards 4729 */ 4730 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4731 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4732 pbn_sunix_pci_1s }, 4733 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4734 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4735 pbn_sunix_pci_2s }, 4736 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4737 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4738 pbn_sunix_pci_4s }, 4739 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4740 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4741 pbn_sunix_pci_4s }, 4742 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4743 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4744 pbn_sunix_pci_8s }, 4745 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4746 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4747 pbn_sunix_pci_8s }, 4748 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4749 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4750 pbn_sunix_pci_16s }, 4751 4752 /* 4753 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4754 */ 4755 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4757 pbn_b0_bt_8_115200 }, 4758 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4760 pbn_b0_bt_8_115200 }, 4761 4762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4764 pbn_b0_bt_2_115200 }, 4765 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4767 pbn_b0_bt_2_115200 }, 4768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4770 pbn_b0_bt_2_115200 }, 4771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4773 pbn_b0_bt_2_115200 }, 4774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4776 pbn_b0_bt_2_115200 }, 4777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4779 pbn_b0_bt_4_460800 }, 4780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4782 pbn_b0_bt_4_460800 }, 4783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4785 pbn_b0_bt_2_460800 }, 4786 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4788 pbn_b0_bt_2_460800 }, 4789 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4791 pbn_b0_bt_2_460800 }, 4792 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4794 pbn_b0_bt_1_115200 }, 4795 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4796 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4797 pbn_b0_bt_1_460800 }, 4798 4799 /* 4800 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4801 * Cards are identified by their subsystem vendor IDs, which 4802 * (in hex) match the model number. 4803 * 4804 * Note that JC140x are RS422/485 cards which require ox950 4805 * ACR = 0x10, and as such are not currently fully supported. 4806 */ 4807 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4808 0x1204, 0x0004, 0, 0, 4809 pbn_b0_4_921600 }, 4810 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4811 0x1208, 0x0004, 0, 0, 4812 pbn_b0_4_921600 }, 4813 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4814 0x1402, 0x0002, 0, 0, 4815 pbn_b0_2_921600 }, */ 4816 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4817 0x1404, 0x0004, 0, 0, 4818 pbn_b0_4_921600 }, */ 4819 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4820 0x1208, 0x0004, 0, 0, 4821 pbn_b0_4_921600 }, 4822 4823 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4824 0x1204, 0x0004, 0, 0, 4825 pbn_b0_4_921600 }, 4826 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4827 0x1208, 0x0004, 0, 0, 4828 pbn_b0_4_921600 }, 4829 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4830 0x1208, 0x0004, 0, 0, 4831 pbn_b0_4_921600 }, 4832 /* 4833 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4834 */ 4835 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4837 pbn_b1_1_1382400 }, 4838 4839 /* 4840 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4841 */ 4842 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4844 pbn_b1_1_1382400 }, 4845 4846 /* 4847 * RAStel 2 port modem, gerg@moreton.com.au 4848 */ 4849 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4851 pbn_b2_bt_2_115200 }, 4852 4853 /* 4854 * EKF addition for i960 Boards form EKF with serial port 4855 */ 4856 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4857 0xE4BF, PCI_ANY_ID, 0, 0, 4858 pbn_intel_i960 }, 4859 4860 /* 4861 * Xircom Cardbus/Ethernet combos 4862 */ 4863 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4864 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4865 pbn_b0_1_115200 }, 4866 /* 4867 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4868 */ 4869 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4870 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4871 pbn_b0_1_115200 }, 4872 4873 /* 4874 * Untested PCI modems, sent in from various folks... 4875 */ 4876 4877 /* 4878 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4879 */ 4880 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4881 0x1048, 0x1500, 0, 0, 4882 pbn_b1_1_115200 }, 4883 4884 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4885 0xFF00, 0, 0, 0, 4886 pbn_sgi_ioc3 }, 4887 4888 /* 4889 * HP Diva card 4890 */ 4891 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4892 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4893 pbn_b1_1_115200 }, 4894 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4896 pbn_b0_5_115200 }, 4897 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4899 pbn_b2_1_115200 }, 4900 /* HPE PCI serial device */ 4901 { PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL, 4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4903 pbn_b1_1_115200 }, 4904 4905 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4907 pbn_b3_2_115200 }, 4908 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4910 pbn_b3_4_115200 }, 4911 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4913 pbn_b3_8_115200 }, 4914 /* 4915 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4916 */ 4917 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4919 pbn_b0_1_115200 }, 4920 /* 4921 * ITE 4922 */ 4923 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4924 PCI_ANY_ID, PCI_ANY_ID, 4925 0, 0, 4926 pbn_b1_bt_1_115200 }, 4927 4928 /* 4929 * IntaShield IS-200 4930 */ 4931 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4933 pbn_b2_2_115200 }, 4934 /* 4935 * IntaShield IS-400 4936 */ 4937 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4939 pbn_b2_4_115200 }, 4940 /* Brainboxes Devices */ 4941 /* 4942 * Brainboxes UC-101 4943 */ 4944 { PCI_VENDOR_ID_INTASHIELD, 0x0BA1, 4945 PCI_ANY_ID, PCI_ANY_ID, 4946 0, 0, 4947 pbn_b2_2_115200 }, 4948 /* 4949 * Brainboxes UC-235/246 4950 */ 4951 { PCI_VENDOR_ID_INTASHIELD, 0x0AA1, 4952 PCI_ANY_ID, PCI_ANY_ID, 4953 0, 0, 4954 pbn_b2_1_115200 }, 4955 /* 4956 * Brainboxes UC-257 4957 */ 4958 { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4959 PCI_ANY_ID, PCI_ANY_ID, 4960 0, 0, 4961 pbn_b2_2_115200 }, 4962 /* 4963 * Brainboxes UC-260/271/701/756 4964 */ 4965 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 4966 PCI_ANY_ID, PCI_ANY_ID, 4967 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4968 pbn_b2_4_115200 }, 4969 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 4970 PCI_ANY_ID, PCI_ANY_ID, 4971 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4972 pbn_b2_4_115200 }, 4973 /* 4974 * Brainboxes UC-268 4975 */ 4976 { PCI_VENDOR_ID_INTASHIELD, 0x0841, 4977 PCI_ANY_ID, PCI_ANY_ID, 4978 0, 0, 4979 pbn_b2_4_115200 }, 4980 /* 4981 * Brainboxes UC-275/279 4982 */ 4983 { PCI_VENDOR_ID_INTASHIELD, 0x0881, 4984 PCI_ANY_ID, PCI_ANY_ID, 4985 0, 0, 4986 pbn_b2_8_115200 }, 4987 /* 4988 * Brainboxes UC-302 4989 */ 4990 { PCI_VENDOR_ID_INTASHIELD, 0x08E1, 4991 PCI_ANY_ID, PCI_ANY_ID, 4992 0, 0, 4993 pbn_b2_2_115200 }, 4994 /* 4995 * Brainboxes UC-310 4996 */ 4997 { PCI_VENDOR_ID_INTASHIELD, 0x08C1, 4998 PCI_ANY_ID, PCI_ANY_ID, 4999 0, 0, 5000 pbn_b2_2_115200 }, 5001 /* 5002 * Brainboxes UC-313 5003 */ 5004 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5005 PCI_ANY_ID, PCI_ANY_ID, 5006 0, 0, 5007 pbn_b2_2_115200 }, 5008 /* 5009 * Brainboxes UC-320/324 5010 */ 5011 { PCI_VENDOR_ID_INTASHIELD, 0x0A61, 5012 PCI_ANY_ID, PCI_ANY_ID, 5013 0, 0, 5014 pbn_b2_1_115200 }, 5015 /* 5016 * Brainboxes UC-346 5017 */ 5018 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5019 PCI_ANY_ID, PCI_ANY_ID, 5020 0, 0, 5021 pbn_b2_4_115200 }, 5022 /* 5023 * Brainboxes UC-357 5024 */ 5025 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5026 PCI_ANY_ID, PCI_ANY_ID, 5027 0, 0, 5028 pbn_b2_2_115200 }, 5029 { PCI_VENDOR_ID_INTASHIELD, 0x0A83, 5030 PCI_ANY_ID, PCI_ANY_ID, 5031 0, 0, 5032 pbn_b2_2_115200 }, 5033 /* 5034 * Brainboxes UC-368 5035 */ 5036 { PCI_VENDOR_ID_INTASHIELD, 0x0C41, 5037 PCI_ANY_ID, PCI_ANY_ID, 5038 0, 0, 5039 pbn_b2_4_115200 }, 5040 /* 5041 * Brainboxes UC-420/431 5042 */ 5043 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5044 PCI_ANY_ID, PCI_ANY_ID, 5045 0, 0, 5046 pbn_b2_4_115200 }, 5047 /* 5048 * Brainboxes PX-101 5049 */ 5050 { PCI_VENDOR_ID_INTASHIELD, 0x4005, 5051 PCI_ANY_ID, PCI_ANY_ID, 5052 0, 0, 5053 pbn_b0_2_115200 }, 5054 { PCI_VENDOR_ID_INTASHIELD, 0x4019, 5055 PCI_ANY_ID, PCI_ANY_ID, 5056 0, 0, 5057 pbn_oxsemi_2_15625000 }, 5058 /* 5059 * Brainboxes PX-235/246 5060 */ 5061 { PCI_VENDOR_ID_INTASHIELD, 0x4004, 5062 PCI_ANY_ID, PCI_ANY_ID, 5063 0, 0, 5064 pbn_b0_1_115200 }, 5065 { PCI_VENDOR_ID_INTASHIELD, 0x4016, 5066 PCI_ANY_ID, PCI_ANY_ID, 5067 0, 0, 5068 pbn_oxsemi_1_15625000 }, 5069 /* 5070 * Brainboxes PX-203/PX-257 5071 */ 5072 { PCI_VENDOR_ID_INTASHIELD, 0x4006, 5073 PCI_ANY_ID, PCI_ANY_ID, 5074 0, 0, 5075 pbn_b0_2_115200 }, 5076 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5077 PCI_ANY_ID, PCI_ANY_ID, 5078 0, 0, 5079 pbn_oxsemi_4_15625000 }, 5080 /* 5081 * Brainboxes PX-260/PX-701 5082 */ 5083 { PCI_VENDOR_ID_INTASHIELD, 0x400A, 5084 PCI_ANY_ID, PCI_ANY_ID, 5085 0, 0, 5086 pbn_oxsemi_4_15625000 }, 5087 /* 5088 * Brainboxes PX-310 5089 */ 5090 { PCI_VENDOR_ID_INTASHIELD, 0x400E, 5091 PCI_ANY_ID, PCI_ANY_ID, 5092 0, 0, 5093 pbn_oxsemi_2_15625000 }, 5094 /* 5095 * Brainboxes PX-313 5096 */ 5097 { PCI_VENDOR_ID_INTASHIELD, 0x400C, 5098 PCI_ANY_ID, PCI_ANY_ID, 5099 0, 0, 5100 pbn_oxsemi_2_15625000 }, 5101 /* 5102 * Brainboxes PX-320/324/PX-376/PX-387 5103 */ 5104 { PCI_VENDOR_ID_INTASHIELD, 0x400B, 5105 PCI_ANY_ID, PCI_ANY_ID, 5106 0, 0, 5107 pbn_oxsemi_1_15625000 }, 5108 /* 5109 * Brainboxes PX-335/346 5110 */ 5111 { PCI_VENDOR_ID_INTASHIELD, 0x400F, 5112 PCI_ANY_ID, PCI_ANY_ID, 5113 0, 0, 5114 pbn_oxsemi_4_15625000 }, 5115 /* 5116 * Brainboxes PX-368 5117 */ 5118 { PCI_VENDOR_ID_INTASHIELD, 0x4010, 5119 PCI_ANY_ID, PCI_ANY_ID, 5120 0, 0, 5121 pbn_oxsemi_4_15625000 }, 5122 /* 5123 * Brainboxes PX-420 5124 */ 5125 { PCI_VENDOR_ID_INTASHIELD, 0x4000, 5126 PCI_ANY_ID, PCI_ANY_ID, 5127 0, 0, 5128 pbn_b0_4_115200 }, 5129 { PCI_VENDOR_ID_INTASHIELD, 0x4011, 5130 PCI_ANY_ID, PCI_ANY_ID, 5131 0, 0, 5132 pbn_oxsemi_4_15625000 }, 5133 /* 5134 * Brainboxes PX-803 5135 */ 5136 { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5137 PCI_ANY_ID, PCI_ANY_ID, 5138 0, 0, 5139 pbn_b0_1_115200 }, 5140 { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5141 PCI_ANY_ID, PCI_ANY_ID, 5142 0, 0, 5143 pbn_oxsemi_1_15625000 }, 5144 /* 5145 * Brainboxes PX-846 5146 */ 5147 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5148 PCI_ANY_ID, PCI_ANY_ID, 5149 0, 0, 5150 pbn_b0_1_115200 }, 5151 { PCI_VENDOR_ID_INTASHIELD, 0x4017, 5152 PCI_ANY_ID, PCI_ANY_ID, 5153 0, 0, 5154 pbn_oxsemi_1_15625000 }, 5155 5156 /* 5157 * Perle PCI-RAS cards 5158 */ 5159 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5160 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5161 0, 0, pbn_b2_4_921600 }, 5162 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5163 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5164 0, 0, pbn_b2_8_921600 }, 5165 5166 /* 5167 * Mainpine series cards: Fairly standard layout but fools 5168 * parts of the autodetect in some cases and uses otherwise 5169 * unmatched communications subclasses in the PCI Express case 5170 */ 5171 5172 { /* RockForceDUO */ 5173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5174 PCI_VENDOR_ID_MAINPINE, 0x0200, 5175 0, 0, pbn_b0_2_115200 }, 5176 { /* RockForceQUATRO */ 5177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5178 PCI_VENDOR_ID_MAINPINE, 0x0300, 5179 0, 0, pbn_b0_4_115200 }, 5180 { /* RockForceDUO+ */ 5181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5182 PCI_VENDOR_ID_MAINPINE, 0x0400, 5183 0, 0, pbn_b0_2_115200 }, 5184 { /* RockForceQUATRO+ */ 5185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5186 PCI_VENDOR_ID_MAINPINE, 0x0500, 5187 0, 0, pbn_b0_4_115200 }, 5188 { /* RockForce+ */ 5189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5190 PCI_VENDOR_ID_MAINPINE, 0x0600, 5191 0, 0, pbn_b0_2_115200 }, 5192 { /* RockForce+ */ 5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5194 PCI_VENDOR_ID_MAINPINE, 0x0700, 5195 0, 0, pbn_b0_4_115200 }, 5196 { /* RockForceOCTO+ */ 5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5198 PCI_VENDOR_ID_MAINPINE, 0x0800, 5199 0, 0, pbn_b0_8_115200 }, 5200 { /* RockForceDUO+ */ 5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5202 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5203 0, 0, pbn_b0_2_115200 }, 5204 { /* RockForceQUARTRO+ */ 5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5206 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5207 0, 0, pbn_b0_4_115200 }, 5208 { /* RockForceOCTO+ */ 5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5210 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5211 0, 0, pbn_b0_8_115200 }, 5212 { /* RockForceD1 */ 5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5214 PCI_VENDOR_ID_MAINPINE, 0x2000, 5215 0, 0, pbn_b0_1_115200 }, 5216 { /* RockForceF1 */ 5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5218 PCI_VENDOR_ID_MAINPINE, 0x2100, 5219 0, 0, pbn_b0_1_115200 }, 5220 { /* RockForceD2 */ 5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5222 PCI_VENDOR_ID_MAINPINE, 0x2200, 5223 0, 0, pbn_b0_2_115200 }, 5224 { /* RockForceF2 */ 5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5226 PCI_VENDOR_ID_MAINPINE, 0x2300, 5227 0, 0, pbn_b0_2_115200 }, 5228 { /* RockForceD4 */ 5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5230 PCI_VENDOR_ID_MAINPINE, 0x2400, 5231 0, 0, pbn_b0_4_115200 }, 5232 { /* RockForceF4 */ 5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5234 PCI_VENDOR_ID_MAINPINE, 0x2500, 5235 0, 0, pbn_b0_4_115200 }, 5236 { /* RockForceD8 */ 5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5238 PCI_VENDOR_ID_MAINPINE, 0x2600, 5239 0, 0, pbn_b0_8_115200 }, 5240 { /* RockForceF8 */ 5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5242 PCI_VENDOR_ID_MAINPINE, 0x2700, 5243 0, 0, pbn_b0_8_115200 }, 5244 { /* IQ Express D1 */ 5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5246 PCI_VENDOR_ID_MAINPINE, 0x3000, 5247 0, 0, pbn_b0_1_115200 }, 5248 { /* IQ Express F1 */ 5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5250 PCI_VENDOR_ID_MAINPINE, 0x3100, 5251 0, 0, pbn_b0_1_115200 }, 5252 { /* IQ Express D2 */ 5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5254 PCI_VENDOR_ID_MAINPINE, 0x3200, 5255 0, 0, pbn_b0_2_115200 }, 5256 { /* IQ Express F2 */ 5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5258 PCI_VENDOR_ID_MAINPINE, 0x3300, 5259 0, 0, pbn_b0_2_115200 }, 5260 { /* IQ Express D4 */ 5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5262 PCI_VENDOR_ID_MAINPINE, 0x3400, 5263 0, 0, pbn_b0_4_115200 }, 5264 { /* IQ Express F4 */ 5265 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5266 PCI_VENDOR_ID_MAINPINE, 0x3500, 5267 0, 0, pbn_b0_4_115200 }, 5268 { /* IQ Express D8 */ 5269 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5270 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5271 0, 0, pbn_b0_8_115200 }, 5272 { /* IQ Express F8 */ 5273 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5274 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5275 0, 0, pbn_b0_8_115200 }, 5276 5277 5278 /* 5279 * PA Semi PA6T-1682M on-chip UART 5280 */ 5281 { PCI_VENDOR_ID_PASEMI, 0xa004, 5282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5283 pbn_pasemi_1682M }, 5284 5285 /* 5286 * National Instruments 5287 */ 5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5290 pbn_b1_16_115200 }, 5291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5293 pbn_b1_8_115200 }, 5294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5296 pbn_b1_bt_4_115200 }, 5297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5299 pbn_b1_bt_2_115200 }, 5300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5302 pbn_b1_bt_4_115200 }, 5303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5305 pbn_b1_bt_2_115200 }, 5306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5308 pbn_b1_16_115200 }, 5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5311 pbn_b1_8_115200 }, 5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5314 pbn_b1_bt_4_115200 }, 5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5317 pbn_b1_bt_2_115200 }, 5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5320 pbn_b1_bt_4_115200 }, 5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5323 pbn_b1_bt_2_115200 }, 5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5326 pbn_ni8430_2 }, 5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5329 pbn_ni8430_2 }, 5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5332 pbn_ni8430_4 }, 5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5335 pbn_ni8430_4 }, 5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5338 pbn_ni8430_8 }, 5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5341 pbn_ni8430_8 }, 5342 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5344 pbn_ni8430_16 }, 5345 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5347 pbn_ni8430_16 }, 5348 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5349 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5350 pbn_ni8430_2 }, 5351 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5353 pbn_ni8430_2 }, 5354 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5356 pbn_ni8430_4 }, 5357 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5359 pbn_ni8430_4 }, 5360 5361 /* 5362 * MOXA 5363 */ 5364 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5366 pbn_moxa8250_2p }, 5367 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5369 pbn_moxa8250_2p }, 5370 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5372 pbn_moxa8250_4p }, 5373 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5375 pbn_moxa8250_4p }, 5376 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5378 pbn_moxa8250_8p }, 5379 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5381 pbn_moxa8250_8p }, 5382 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5384 pbn_moxa8250_8p }, 5385 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5387 pbn_moxa8250_8p }, 5388 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5389 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5390 pbn_moxa8250_2p }, 5391 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5393 pbn_moxa8250_4p }, 5394 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5395 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5396 pbn_moxa8250_8p }, 5397 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5399 pbn_moxa8250_8p }, 5400 5401 /* 5402 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5403 */ 5404 { PCI_VENDOR_ID_ADDIDATA, 5405 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5406 PCI_ANY_ID, 5407 PCI_ANY_ID, 5408 0, 5409 0, 5410 pbn_b0_4_115200 }, 5411 5412 { PCI_VENDOR_ID_ADDIDATA, 5413 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5414 PCI_ANY_ID, 5415 PCI_ANY_ID, 5416 0, 5417 0, 5418 pbn_b0_2_115200 }, 5419 5420 { PCI_VENDOR_ID_ADDIDATA, 5421 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5422 PCI_ANY_ID, 5423 PCI_ANY_ID, 5424 0, 5425 0, 5426 pbn_b0_1_115200 }, 5427 5428 { PCI_VENDOR_ID_AMCC, 5429 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5430 PCI_ANY_ID, 5431 PCI_ANY_ID, 5432 0, 5433 0, 5434 pbn_b1_8_115200 }, 5435 5436 { PCI_VENDOR_ID_ADDIDATA, 5437 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5438 PCI_ANY_ID, 5439 PCI_ANY_ID, 5440 0, 5441 0, 5442 pbn_b0_4_115200 }, 5443 5444 { PCI_VENDOR_ID_ADDIDATA, 5445 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5446 PCI_ANY_ID, 5447 PCI_ANY_ID, 5448 0, 5449 0, 5450 pbn_b0_2_115200 }, 5451 5452 { PCI_VENDOR_ID_ADDIDATA, 5453 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5454 PCI_ANY_ID, 5455 PCI_ANY_ID, 5456 0, 5457 0, 5458 pbn_b0_1_115200 }, 5459 5460 { PCI_VENDOR_ID_ADDIDATA, 5461 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5462 PCI_ANY_ID, 5463 PCI_ANY_ID, 5464 0, 5465 0, 5466 pbn_b0_4_115200 }, 5467 5468 { PCI_VENDOR_ID_ADDIDATA, 5469 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5470 PCI_ANY_ID, 5471 PCI_ANY_ID, 5472 0, 5473 0, 5474 pbn_b0_2_115200 }, 5475 5476 { PCI_VENDOR_ID_ADDIDATA, 5477 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5478 PCI_ANY_ID, 5479 PCI_ANY_ID, 5480 0, 5481 0, 5482 pbn_b0_1_115200 }, 5483 5484 { PCI_VENDOR_ID_ADDIDATA, 5485 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5486 PCI_ANY_ID, 5487 PCI_ANY_ID, 5488 0, 5489 0, 5490 pbn_b0_8_115200 }, 5491 5492 { PCI_VENDOR_ID_ADDIDATA, 5493 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5494 PCI_ANY_ID, 5495 PCI_ANY_ID, 5496 0, 5497 0, 5498 pbn_ADDIDATA_PCIe_4_3906250 }, 5499 5500 { PCI_VENDOR_ID_ADDIDATA, 5501 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5502 PCI_ANY_ID, 5503 PCI_ANY_ID, 5504 0, 5505 0, 5506 pbn_ADDIDATA_PCIe_2_3906250 }, 5507 5508 { PCI_VENDOR_ID_ADDIDATA, 5509 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5510 PCI_ANY_ID, 5511 PCI_ANY_ID, 5512 0, 5513 0, 5514 pbn_ADDIDATA_PCIe_1_3906250 }, 5515 5516 { PCI_VENDOR_ID_ADDIDATA, 5517 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5518 PCI_ANY_ID, 5519 PCI_ANY_ID, 5520 0, 5521 0, 5522 pbn_ADDIDATA_PCIe_8_3906250 }, 5523 5524 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5525 PCI_VENDOR_ID_IBM, 0x0299, 5526 0, 0, pbn_b0_bt_2_115200 }, 5527 5528 /* 5529 * other NetMos 9835 devices are most likely handled by the 5530 * parport_serial driver, check drivers/parport/parport_serial.c 5531 * before adding them here. 5532 */ 5533 5534 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5535 0xA000, 0x1000, 5536 0, 0, pbn_b0_1_115200 }, 5537 5538 /* the 9901 is a rebranded 9912 */ 5539 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5540 0xA000, 0x1000, 5541 0, 0, pbn_b0_1_115200 }, 5542 5543 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5544 0xA000, 0x1000, 5545 0, 0, pbn_b0_1_115200 }, 5546 5547 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5548 0xA000, 0x1000, 5549 0, 0, pbn_b0_1_115200 }, 5550 5551 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5552 0xA000, 0x1000, 5553 0, 0, pbn_b0_1_115200 }, 5554 5555 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5556 0xA000, 0x3002, 5557 0, 0, pbn_NETMOS9900_2s_115200 }, 5558 5559 /* 5560 * Best Connectivity and Rosewill PCI Multi I/O cards 5561 */ 5562 5563 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5564 0xA000, 0x1000, 5565 0, 0, pbn_b0_1_115200 }, 5566 5567 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5568 0xA000, 0x3002, 5569 0, 0, pbn_b0_bt_2_115200 }, 5570 5571 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5572 0xA000, 0x3004, 5573 0, 0, pbn_b0_bt_4_115200 }, 5574 /* Intel CE4100 */ 5575 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5576 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5577 pbn_ce4100_1_115200 }, 5578 5579 /* 5580 * Cronyx Omega PCI 5581 */ 5582 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5583 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5584 pbn_omegapci }, 5585 5586 /* 5587 * Broadcom TruManage 5588 */ 5589 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5591 pbn_brcm_trumanage }, 5592 5593 /* 5594 * AgeStar as-prs2-009 5595 */ 5596 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5597 PCI_ANY_ID, PCI_ANY_ID, 5598 0, 0, pbn_b0_bt_2_115200 }, 5599 5600 /* 5601 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5602 * so not listed here. 5603 */ 5604 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5605 PCI_ANY_ID, PCI_ANY_ID, 5606 0, 0, pbn_b0_bt_4_115200 }, 5607 5608 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5609 PCI_ANY_ID, PCI_ANY_ID, 5610 0, 0, pbn_b0_bt_2_115200 }, 5611 5612 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5613 PCI_ANY_ID, PCI_ANY_ID, 5614 0, 0, pbn_b0_bt_4_115200 }, 5615 5616 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5617 PCI_ANY_ID, PCI_ANY_ID, 5618 0, 0, pbn_wch382_2 }, 5619 5620 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5621 PCI_ANY_ID, PCI_ANY_ID, 5622 0, 0, pbn_wch384_4 }, 5623 5624 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5625 PCI_ANY_ID, PCI_ANY_ID, 5626 0, 0, pbn_wch384_8 }, 5627 /* 5628 * Realtek RealManage 5629 */ 5630 { PCI_VENDOR_ID_REALTEK, 0x816a, 5631 PCI_ANY_ID, PCI_ANY_ID, 5632 0, 0, pbn_b0_1_115200 }, 5633 5634 { PCI_VENDOR_ID_REALTEK, 0x816b, 5635 PCI_ANY_ID, PCI_ANY_ID, 5636 0, 0, pbn_b0_1_115200 }, 5637 5638 /* Fintek PCI serial cards */ 5639 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5640 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5641 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5642 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5643 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5644 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5645 5646 /* MKS Tenta SCOM-080x serial cards */ 5647 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5648 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5649 5650 /* Amazon PCI serial device */ 5651 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5652 5653 /* 5654 * These entries match devices with class COMMUNICATION_SERIAL, 5655 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5656 */ 5657 { PCI_ANY_ID, PCI_ANY_ID, 5658 PCI_ANY_ID, PCI_ANY_ID, 5659 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5660 0xffff00, pbn_default }, 5661 { PCI_ANY_ID, PCI_ANY_ID, 5662 PCI_ANY_ID, PCI_ANY_ID, 5663 PCI_CLASS_COMMUNICATION_MODEM << 8, 5664 0xffff00, pbn_default }, 5665 { PCI_ANY_ID, PCI_ANY_ID, 5666 PCI_ANY_ID, PCI_ANY_ID, 5667 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5668 0xffff00, pbn_default }, 5669 { 0, } 5670 }; 5671 5672 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5673 pci_channel_state_t state) 5674 { 5675 struct serial_private *priv = pci_get_drvdata(dev); 5676 5677 if (state == pci_channel_io_perm_failure) 5678 return PCI_ERS_RESULT_DISCONNECT; 5679 5680 if (priv) 5681 pciserial_detach_ports(priv); 5682 5683 pci_disable_device(dev); 5684 5685 return PCI_ERS_RESULT_NEED_RESET; 5686 } 5687 5688 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5689 { 5690 int rc; 5691 5692 rc = pci_enable_device(dev); 5693 5694 if (rc) 5695 return PCI_ERS_RESULT_DISCONNECT; 5696 5697 pci_restore_state(dev); 5698 pci_save_state(dev); 5699 5700 return PCI_ERS_RESULT_RECOVERED; 5701 } 5702 5703 static void serial8250_io_resume(struct pci_dev *dev) 5704 { 5705 struct serial_private *priv = pci_get_drvdata(dev); 5706 struct serial_private *new; 5707 5708 if (!priv) 5709 return; 5710 5711 new = pciserial_init_ports(dev, priv->board); 5712 if (!IS_ERR(new)) { 5713 pci_set_drvdata(dev, new); 5714 kfree(priv); 5715 } 5716 } 5717 5718 static const struct pci_error_handlers serial8250_err_handler = { 5719 .error_detected = serial8250_io_error_detected, 5720 .slot_reset = serial8250_io_slot_reset, 5721 .resume = serial8250_io_resume, 5722 }; 5723 5724 static struct pci_driver serial_pci_driver = { 5725 .name = "serial", 5726 .probe = pciserial_init_one, 5727 .remove = pciserial_remove_one, 5728 .driver = { 5729 .pm = &pciserial_pm_ops, 5730 }, 5731 .id_table = serial_pci_tbl, 5732 .err_handler = &serial8250_err_handler, 5733 }; 5734 5735 module_pci_driver(serial_pci_driver); 5736 5737 MODULE_LICENSE("GPL"); 5738 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5739 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5740 MODULE_IMPORT_NS(SERIAL_8250_PCI); 5741