1 /* 2 * Probe module for 8250/16550-type PCI serial ports. 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King, All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License. 11 */ 12 #undef DEBUG 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/string.h> 16 #include <linux/kernel.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 #include <linux/tty.h> 20 #include <linux/serial_reg.h> 21 #include <linux/serial_core.h> 22 #include <linux/8250_pci.h> 23 #include <linux/bitops.h> 24 25 #include <asm/byteorder.h> 26 #include <asm/io.h> 27 28 #include "8250.h" 29 30 /* 31 * init function returns: 32 * > 0 - number of ports 33 * = 0 - use board->num_ports 34 * < 0 - error 35 */ 36 struct pci_serial_quirk { 37 u32 vendor; 38 u32 device; 39 u32 subvendor; 40 u32 subdevice; 41 int (*probe)(struct pci_dev *dev); 42 int (*init)(struct pci_dev *dev); 43 int (*setup)(struct serial_private *, 44 const struct pciserial_board *, 45 struct uart_8250_port *, int); 46 void (*exit)(struct pci_dev *dev); 47 }; 48 49 #define PCI_NUM_BAR_RESOURCES 6 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES]; 55 struct pci_serial_quirk *quirk; 56 int line[0]; 57 }; 58 59 static int pci_default_setup(struct serial_private*, 60 const struct pciserial_board*, struct uart_8250_port *, int); 61 62 static void moan_device(const char *str, struct pci_dev *dev) 63 { 64 dev_err(&dev->dev, 65 "%s: %s\n" 66 "Please send the output of lspci -vv, this\n" 67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 68 "manufacturer and name of serial board or\n" 69 "modem board to rmk+serial@arm.linux.org.uk.\n", 70 pci_name(dev), str, dev->vendor, dev->device, 71 dev->subsystem_vendor, dev->subsystem_device); 72 } 73 74 static int 75 setup_port(struct serial_private *priv, struct uart_8250_port *port, 76 int bar, int offset, int regshift) 77 { 78 struct pci_dev *dev = priv->dev; 79 unsigned long base, len; 80 81 if (bar >= PCI_NUM_BAR_RESOURCES) 82 return -EINVAL; 83 84 base = pci_resource_start(dev, bar); 85 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 87 len = pci_resource_len(dev, bar); 88 89 if (!priv->remapped_bar[bar]) 90 priv->remapped_bar[bar] = ioremap_nocache(base, len); 91 if (!priv->remapped_bar[bar]) 92 return -ENOMEM; 93 94 port->port.iotype = UPIO_MEM; 95 port->port.iobase = 0; 96 port->port.mapbase = base + offset; 97 port->port.membase = priv->remapped_bar[bar] + offset; 98 port->port.regshift = regshift; 99 } else { 100 port->port.iotype = UPIO_PORT; 101 port->port.iobase = base + offset; 102 port->port.mapbase = 0; 103 port->port.membase = NULL; 104 port->port.regshift = 0; 105 } 106 return 0; 107 } 108 109 /* 110 * ADDI-DATA GmbH communication cards <info@addi-data.com> 111 */ 112 static int addidata_apci7800_setup(struct serial_private *priv, 113 const struct pciserial_board *board, 114 struct uart_8250_port *port, int idx) 115 { 116 unsigned int bar = 0, offset = board->first_offset; 117 bar = FL_GET_BASE(board->flags); 118 119 if (idx < 2) { 120 offset += idx * board->uart_offset; 121 } else if ((idx >= 2) && (idx < 4)) { 122 bar += 1; 123 offset += ((idx - 2) * board->uart_offset); 124 } else if ((idx >= 4) && (idx < 6)) { 125 bar += 2; 126 offset += ((idx - 4) * board->uart_offset); 127 } else if (idx >= 6) { 128 bar += 3; 129 offset += ((idx - 6) * board->uart_offset); 130 } 131 132 return setup_port(priv, port, bar, offset, board->reg_shift); 133 } 134 135 /* 136 * AFAVLAB uses a different mixture of BARs and offsets 137 * Not that ugly ;) -- HW 138 */ 139 static int 140 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 141 struct uart_8250_port *port, int idx) 142 { 143 unsigned int bar, offset = board->first_offset; 144 145 bar = FL_GET_BASE(board->flags); 146 if (idx < 4) 147 bar += idx; 148 else { 149 bar = 4; 150 offset += (idx - 4) * board->uart_offset; 151 } 152 153 return setup_port(priv, port, bar, offset, board->reg_shift); 154 } 155 156 /* 157 * HP's Remote Management Console. The Diva chip came in several 158 * different versions. N-class, L2000 and A500 have two Diva chips, each 159 * with 3 UARTs (the third UART on the second chip is unused). Superdome 160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 161 * one Diva chip, but it has been expanded to 5 UARTs. 162 */ 163 static int pci_hp_diva_init(struct pci_dev *dev) 164 { 165 int rc = 0; 166 167 switch (dev->subsystem_device) { 168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 171 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 172 rc = 3; 173 break; 174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 175 rc = 2; 176 break; 177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 178 rc = 4; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 182 rc = 1; 183 break; 184 } 185 186 return rc; 187 } 188 189 /* 190 * HP's Diva chip puts the 4th/5th serial port further out, and 191 * some serial ports are supposed to be hidden on certain models. 192 */ 193 static int 194 pci_hp_diva_setup(struct serial_private *priv, 195 const struct pciserial_board *board, 196 struct uart_8250_port *port, int idx) 197 { 198 unsigned int offset = board->first_offset; 199 unsigned int bar = FL_GET_BASE(board->flags); 200 201 switch (priv->dev->subsystem_device) { 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 203 if (idx == 3) 204 idx++; 205 break; 206 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 207 if (idx > 0) 208 idx++; 209 if (idx > 2) 210 idx++; 211 break; 212 } 213 if (idx > 2) 214 offset = 0x18; 215 216 offset += idx * board->uart_offset; 217 218 return setup_port(priv, port, bar, offset, board->reg_shift); 219 } 220 221 /* 222 * Added for EKF Intel i960 serial boards 223 */ 224 static int pci_inteli960ni_init(struct pci_dev *dev) 225 { 226 unsigned long oldval; 227 228 if (!(dev->subsystem_device & 0x1000)) 229 return -ENODEV; 230 231 /* is firmware started? */ 232 pci_read_config_dword(dev, 0x44, (void *)&oldval); 233 if (oldval == 0x00001000L) { /* RESET value */ 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 235 return -ENODEV; 236 } 237 return 0; 238 } 239 240 /* 241 * Some PCI serial cards using the PLX 9050 PCI interface chip require 242 * that the card interrupt be explicitly enabled or disabled. This 243 * seems to be mainly needed on card using the PLX which also use I/O 244 * mapped memory. 245 */ 246 static int pci_plx9050_init(struct pci_dev *dev) 247 { 248 u8 irq_config; 249 void __iomem *p; 250 251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 252 moan_device("no memory in bar 0", dev); 253 return 0; 254 } 255 256 irq_config = 0x41; 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 259 irq_config = 0x43; 260 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 263 /* 264 * As the megawolf cards have the int pins active 265 * high, and have 2 UART chips, both ints must be 266 * enabled on the 9050. Also, the UARTS are set in 267 * 16450 mode by default, so we have to enable the 268 * 16C950 'enhanced' mode so that we can use the 269 * deep FIFOs 270 */ 271 irq_config = 0x5b; 272 /* 273 * enable/disable interrupts 274 */ 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 276 if (p == NULL) 277 return -ENOMEM; 278 writel(irq_config, p + 0x4c); 279 280 /* 281 * Read the register back to ensure that it took effect. 282 */ 283 readl(p + 0x4c); 284 iounmap(p); 285 286 return 0; 287 } 288 289 static void pci_plx9050_exit(struct pci_dev *dev) 290 { 291 u8 __iomem *p; 292 293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 294 return; 295 296 /* 297 * disable interrupts 298 */ 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 300 if (p != NULL) { 301 writel(0, p + 0x4c); 302 303 /* 304 * Read the register back to ensure that it took effect. 305 */ 306 readl(p + 0x4c); 307 iounmap(p); 308 } 309 } 310 311 #define NI8420_INT_ENABLE_REG 0x38 312 #define NI8420_INT_ENABLE_BIT 0x2000 313 314 static void pci_ni8420_exit(struct pci_dev *dev) 315 { 316 void __iomem *p; 317 unsigned long base, len; 318 unsigned int bar = 0; 319 320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 321 moan_device("no memory in bar", dev); 322 return; 323 } 324 325 base = pci_resource_start(dev, bar); 326 len = pci_resource_len(dev, bar); 327 p = ioremap_nocache(base, len); 328 if (p == NULL) 329 return; 330 331 /* Disable the CPU Interrupt */ 332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 333 p + NI8420_INT_ENABLE_REG); 334 iounmap(p); 335 } 336 337 338 /* MITE registers */ 339 #define MITE_IOWBSR1 0xc4 340 #define MITE_IOWCR1 0xf4 341 #define MITE_LCIMR1 0x08 342 #define MITE_LCIMR2 0x10 343 344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 345 346 static void pci_ni8430_exit(struct pci_dev *dev) 347 { 348 void __iomem *p; 349 unsigned long base, len; 350 unsigned int bar = 0; 351 352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 353 moan_device("no memory in bar", dev); 354 return; 355 } 356 357 base = pci_resource_start(dev, bar); 358 len = pci_resource_len(dev, bar); 359 p = ioremap_nocache(base, len); 360 if (p == NULL) 361 return; 362 363 /* Disable the CPU Interrupt */ 364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 365 iounmap(p); 366 } 367 368 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 369 static int 370 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 371 struct uart_8250_port *port, int idx) 372 { 373 unsigned int bar, offset = board->first_offset; 374 375 bar = 0; 376 377 if (idx < 4) { 378 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 379 offset += idx * board->uart_offset; 380 } else if (idx < 8) { 381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 382 offset += idx * board->uart_offset + 0xC00; 383 } else /* we have only 8 ports on PMC-OCTALPRO */ 384 return 1; 385 386 return setup_port(priv, port, bar, offset, board->reg_shift); 387 } 388 389 /* 390 * This does initialization for PMC OCTALPRO cards: 391 * maps the device memory, resets the UARTs (needed, bc 392 * if the module is removed and inserted again, the card 393 * is in the sleep mode) and enables global interrupt. 394 */ 395 396 /* global control register offset for SBS PMC-OctalPro */ 397 #define OCT_REG_CR_OFF 0x500 398 399 static int sbs_init(struct pci_dev *dev) 400 { 401 u8 __iomem *p; 402 403 p = pci_ioremap_bar(dev, 0); 404 405 if (p == NULL) 406 return -ENOMEM; 407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 408 writeb(0x10, p + OCT_REG_CR_OFF); 409 udelay(50); 410 writeb(0x0, p + OCT_REG_CR_OFF); 411 412 /* Set bit-2 (INTENABLE) of Control Register */ 413 writeb(0x4, p + OCT_REG_CR_OFF); 414 iounmap(p); 415 416 return 0; 417 } 418 419 /* 420 * Disables the global interrupt of PMC-OctalPro 421 */ 422 423 static void sbs_exit(struct pci_dev *dev) 424 { 425 u8 __iomem *p; 426 427 p = pci_ioremap_bar(dev, 0); 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 429 if (p != NULL) 430 writeb(0, p + OCT_REG_CR_OFF); 431 iounmap(p); 432 } 433 434 /* 435 * SIIG serial cards have an PCI interface chip which also controls 436 * the UART clocking frequency. Each UART can be clocked independently 437 * (except cards equipped with 4 UARTs) and initial clocking settings 438 * are stored in the EEPROM chip. It can cause problems because this 439 * version of serial driver doesn't support differently clocked UART's 440 * on single PCI card. To prevent this, initialization functions set 441 * high frequency clocking for all UART's on given card. It is safe (I 442 * hope) because it doesn't touch EEPROM settings to prevent conflicts 443 * with other OSes (like M$ DOS). 444 * 445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 446 * 447 * There is two family of SIIG serial cards with different PCI 448 * interface chip and different configuration methods: 449 * - 10x cards have control registers in IO and/or memory space; 450 * - 20x cards have control registers in standard PCI configuration space. 451 * 452 * Note: all 10x cards have PCI device ids 0x10.. 453 * all 20x cards have PCI device ids 0x20.. 454 * 455 * There are also Quartet Serial cards which use Oxford Semiconductor 456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 457 * 458 * Note: some SIIG cards are probed by the parport_serial object. 459 */ 460 461 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 462 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 463 464 static int pci_siig10x_init(struct pci_dev *dev) 465 { 466 u16 data; 467 void __iomem *p; 468 469 switch (dev->device & 0xfff8) { 470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 471 data = 0xffdf; 472 break; 473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 474 data = 0xf7ff; 475 break; 476 default: /* 1S1P, 4S */ 477 data = 0xfffb; 478 break; 479 } 480 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); 482 if (p == NULL) 483 return -ENOMEM; 484 485 writew(readw(p + 0x28) & data, p + 0x28); 486 readw(p + 0x28); 487 iounmap(p); 488 return 0; 489 } 490 491 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 492 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 493 494 static int pci_siig20x_init(struct pci_dev *dev) 495 { 496 u8 data; 497 498 /* Change clock frequency for the first UART. */ 499 pci_read_config_byte(dev, 0x6f, &data); 500 pci_write_config_byte(dev, 0x6f, data & 0xef); 501 502 /* If this card has 2 UART, we have to do the same with second UART. */ 503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 505 pci_read_config_byte(dev, 0x73, &data); 506 pci_write_config_byte(dev, 0x73, data & 0xef); 507 } 508 return 0; 509 } 510 511 static int pci_siig_init(struct pci_dev *dev) 512 { 513 unsigned int type = dev->device & 0xff00; 514 515 if (type == 0x1000) 516 return pci_siig10x_init(dev); 517 else if (type == 0x2000) 518 return pci_siig20x_init(dev); 519 520 moan_device("Unknown SIIG card", dev); 521 return -ENODEV; 522 } 523 524 static int pci_siig_setup(struct serial_private *priv, 525 const struct pciserial_board *board, 526 struct uart_8250_port *port, int idx) 527 { 528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 529 530 if (idx > 3) { 531 bar = 4; 532 offset = (idx - 4) * 8; 533 } 534 535 return setup_port(priv, port, bar, offset, 0); 536 } 537 538 /* 539 * Timedia has an explosion of boards, and to avoid the PCI table from 540 * growing *huge*, we use this function to collapse some 70 entries 541 * in the PCI table into one, for sanity's and compactness's sake. 542 */ 543 static const unsigned short timedia_single_port[] = { 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 545 }; 546 547 static const unsigned short timedia_dual_port[] = { 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 552 0xD079, 0 553 }; 554 555 static const unsigned short timedia_quad_port[] = { 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 559 0xB157, 0 560 }; 561 562 static const unsigned short timedia_eight_port[] = { 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 565 }; 566 567 static const struct timedia_struct { 568 int num; 569 const unsigned short *ids; 570 } timedia_data[] = { 571 { 1, timedia_single_port }, 572 { 2, timedia_dual_port }, 573 { 4, timedia_quad_port }, 574 { 8, timedia_eight_port } 575 }; 576 577 /* 578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 579 * listing them individually, this driver merely grabs them all with 580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 581 * and should be left free to be claimed by parport_serial instead. 582 */ 583 static int pci_timedia_probe(struct pci_dev *dev) 584 { 585 /* 586 * Check the third digit of the subdevice ID 587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 588 */ 589 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 590 dev_info(&dev->dev, 591 "ignoring Timedia subdevice %04x for parport_serial\n", 592 dev->subsystem_device); 593 return -ENODEV; 594 } 595 596 return 0; 597 } 598 599 static int pci_timedia_init(struct pci_dev *dev) 600 { 601 const unsigned short *ids; 602 int i, j; 603 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 605 ids = timedia_data[i].ids; 606 for (j = 0; ids[j]; j++) 607 if (dev->subsystem_device == ids[j]) 608 return timedia_data[i].num; 609 } 610 return 0; 611 } 612 613 /* 614 * Timedia/SUNIX uses a mixture of BARs and offsets 615 * Ugh, this is ugly as all hell --- TYT 616 */ 617 static int 618 pci_timedia_setup(struct serial_private *priv, 619 const struct pciserial_board *board, 620 struct uart_8250_port *port, int idx) 621 { 622 unsigned int bar = 0, offset = board->first_offset; 623 624 switch (idx) { 625 case 0: 626 bar = 0; 627 break; 628 case 1: 629 offset = board->uart_offset; 630 bar = 0; 631 break; 632 case 2: 633 bar = 1; 634 break; 635 case 3: 636 offset = board->uart_offset; 637 /* FALLTHROUGH */ 638 case 4: /* BAR 2 */ 639 case 5: /* BAR 3 */ 640 case 6: /* BAR 4 */ 641 case 7: /* BAR 5 */ 642 bar = idx - 2; 643 } 644 645 return setup_port(priv, port, bar, offset, board->reg_shift); 646 } 647 648 /* 649 * Some Titan cards are also a little weird 650 */ 651 static int 652 titan_400l_800l_setup(struct serial_private *priv, 653 const struct pciserial_board *board, 654 struct uart_8250_port *port, int idx) 655 { 656 unsigned int bar, offset = board->first_offset; 657 658 switch (idx) { 659 case 0: 660 bar = 1; 661 break; 662 case 1: 663 bar = 2; 664 break; 665 default: 666 bar = 4; 667 offset = (idx - 2) * board->uart_offset; 668 } 669 670 return setup_port(priv, port, bar, offset, board->reg_shift); 671 } 672 673 static int pci_xircom_init(struct pci_dev *dev) 674 { 675 msleep(100); 676 return 0; 677 } 678 679 static int pci_ni8420_init(struct pci_dev *dev) 680 { 681 void __iomem *p; 682 unsigned long base, len; 683 unsigned int bar = 0; 684 685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 686 moan_device("no memory in bar", dev); 687 return 0; 688 } 689 690 base = pci_resource_start(dev, bar); 691 len = pci_resource_len(dev, bar); 692 p = ioremap_nocache(base, len); 693 if (p == NULL) 694 return -ENOMEM; 695 696 /* Enable CPU Interrupt */ 697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 698 p + NI8420_INT_ENABLE_REG); 699 700 iounmap(p); 701 return 0; 702 } 703 704 #define MITE_IOWBSR1_WSIZE 0xa 705 #define MITE_IOWBSR1_WIN_OFFSET 0x800 706 #define MITE_IOWBSR1_WENAB (1 << 7) 707 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 708 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 709 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 710 711 static int pci_ni8430_init(struct pci_dev *dev) 712 { 713 void __iomem *p; 714 unsigned long base, len; 715 u32 device_window; 716 unsigned int bar = 0; 717 718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 719 moan_device("no memory in bar", dev); 720 return 0; 721 } 722 723 base = pci_resource_start(dev, bar); 724 len = pci_resource_len(dev, bar); 725 p = ioremap_nocache(base, len); 726 if (p == NULL) 727 return -ENOMEM; 728 729 /* Set device window address and size in BAR0 */ 730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 732 writel(device_window, p + MITE_IOWBSR1); 733 734 /* Set window access to go to RAMSEL IO address space */ 735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 736 p + MITE_IOWCR1); 737 738 /* Enable IO Bus Interrupt 0 */ 739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 740 741 /* Enable CPU Interrupt */ 742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 743 744 iounmap(p); 745 return 0; 746 } 747 748 /* UART Port Control Register */ 749 #define NI8430_PORTCON 0x0f 750 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 751 752 static int 753 pci_ni8430_setup(struct serial_private *priv, 754 const struct pciserial_board *board, 755 struct uart_8250_port *port, int idx) 756 { 757 void __iomem *p; 758 unsigned long base, len; 759 unsigned int bar, offset = board->first_offset; 760 761 if (idx >= board->num_ports) 762 return 1; 763 764 bar = FL_GET_BASE(board->flags); 765 offset += idx * board->uart_offset; 766 767 base = pci_resource_start(priv->dev, bar); 768 len = pci_resource_len(priv->dev, bar); 769 p = ioremap_nocache(base, len); 770 771 /* enable the transceiver */ 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 773 p + offset + NI8430_PORTCON); 774 775 iounmap(p); 776 777 return setup_port(priv, port, bar, offset, board->reg_shift); 778 } 779 780 static int pci_netmos_9900_setup(struct serial_private *priv, 781 const struct pciserial_board *board, 782 struct uart_8250_port *port, int idx) 783 { 784 unsigned int bar; 785 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 787 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 788 /* netmos apparently orders BARs by datasheet layout, so serial 789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 790 */ 791 bar = 3 * idx; 792 793 return setup_port(priv, port, bar, 0, board->reg_shift); 794 } else { 795 return pci_default_setup(priv, board, port, idx); 796 } 797 } 798 799 /* the 99xx series comes with a range of device IDs and a variety 800 * of capabilities: 801 * 802 * 9900 has varying capabilities and can cascade to sub-controllers 803 * (cascading should be purely internal) 804 * 9904 is hardwired with 4 serial ports 805 * 9912 and 9922 are hardwired with 2 serial ports 806 */ 807 static int pci_netmos_9900_numports(struct pci_dev *dev) 808 { 809 unsigned int c = dev->class; 810 unsigned int pi; 811 unsigned short sub_serports; 812 813 pi = (c & 0xff); 814 815 if (pi == 2) { 816 return 1; 817 } else if ((pi == 0) && 818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 819 /* two possibilities: 0x30ps encodes number of parallel and 820 * serial ports, or 0x1000 indicates *something*. This is not 821 * immediately obvious, since the 2s1p+4s configuration seems 822 * to offer all functionality on functions 0..2, while still 823 * advertising the same function 3 as the 4s+2s1p config. 824 */ 825 sub_serports = dev->subsystem_device & 0xf; 826 if (sub_serports > 0) { 827 return sub_serports; 828 } else { 829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 830 return 0; 831 } 832 } 833 834 moan_device("unknown NetMos/Mostech program interface", dev); 835 return 0; 836 } 837 838 static int pci_netmos_init(struct pci_dev *dev) 839 { 840 /* subdevice 0x00PS means <P> parallel, <S> serial */ 841 unsigned int num_serial = dev->subsystem_device & 0xf; 842 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 844 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 845 return 0; 846 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 848 dev->subsystem_device == 0x0299) 849 return 0; 850 851 switch (dev->device) { /* FALLTHROUGH on all */ 852 case PCI_DEVICE_ID_NETMOS_9904: 853 case PCI_DEVICE_ID_NETMOS_9912: 854 case PCI_DEVICE_ID_NETMOS_9922: 855 case PCI_DEVICE_ID_NETMOS_9900: 856 num_serial = pci_netmos_9900_numports(dev); 857 break; 858 859 default: 860 if (num_serial == 0 ) { 861 moan_device("unknown NetMos/Mostech device", dev); 862 } 863 } 864 865 if (num_serial == 0) 866 return -ENODEV; 867 868 return num_serial; 869 } 870 871 /* 872 * These chips are available with optionally one parallel port and up to 873 * two serial ports. Unfortunately they all have the same product id. 874 * 875 * Basic configuration is done over a region of 32 I/O ports. The base 876 * ioport is called INTA or INTC, depending on docs/other drivers. 877 * 878 * The region of the 32 I/O ports is configured in POSIO0R... 879 */ 880 881 /* registers */ 882 #define ITE_887x_MISCR 0x9c 883 #define ITE_887x_INTCBAR 0x78 884 #define ITE_887x_UARTBAR 0x7c 885 #define ITE_887x_PS0BAR 0x10 886 #define ITE_887x_POSIO0 0x60 887 888 /* I/O space size */ 889 #define ITE_887x_IOSIZE 32 890 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 891 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 892 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 893 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 895 #define ITE_887x_POSIO_SPEED (3 << 29) 896 /* enable IO_Space bit */ 897 #define ITE_887x_POSIO_ENABLE (1 << 31) 898 899 static int pci_ite887x_init(struct pci_dev *dev) 900 { 901 /* inta_addr are the configuration addresses of the ITE */ 902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 903 0x200, 0x280, 0 }; 904 int ret, i, type; 905 struct resource *iobase = NULL; 906 u32 miscr, uartbar, ioport; 907 908 /* search for the base-ioport */ 909 i = 0; 910 while (inta_addr[i] && iobase == NULL) { 911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 912 "ite887x"); 913 if (iobase != NULL) { 914 /* write POSIO0R - speed | size | ioport */ 915 pci_write_config_dword(dev, ITE_887x_POSIO0, 916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 918 /* write INTCBAR - ioport */ 919 pci_write_config_dword(dev, ITE_887x_INTCBAR, 920 inta_addr[i]); 921 ret = inb(inta_addr[i]); 922 if (ret != 0xff) { 923 /* ioport connected */ 924 break; 925 } 926 release_region(iobase->start, ITE_887x_IOSIZE); 927 iobase = NULL; 928 } 929 i++; 930 } 931 932 if (!inta_addr[i]) { 933 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 934 return -ENODEV; 935 } 936 937 /* start of undocumented type checking (see parport_pc.c) */ 938 type = inb(iobase->start + 0x18) & 0x0f; 939 940 switch (type) { 941 case 0x2: /* ITE8871 (1P) */ 942 case 0xa: /* ITE8875 (1P) */ 943 ret = 0; 944 break; 945 case 0xe: /* ITE8872 (2S1P) */ 946 ret = 2; 947 break; 948 case 0x6: /* ITE8873 (1S) */ 949 ret = 1; 950 break; 951 case 0x8: /* ITE8874 (2S) */ 952 ret = 2; 953 break; 954 default: 955 moan_device("Unknown ITE887x", dev); 956 ret = -ENODEV; 957 } 958 959 /* configure all serial ports */ 960 for (i = 0; i < ret; i++) { 961 /* read the I/O port from the device */ 962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 963 &ioport); 964 ioport &= 0x0000FF00; /* the actual base address */ 965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 967 ITE_887x_POSIO_IOSIZE_8 | ioport); 968 969 /* write the ioport to the UARTBAR */ 970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 972 uartbar |= (ioport << (16 * i)); /* set the ioport */ 973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 974 975 /* get current config */ 976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 977 /* disable interrupts (UARTx_Routing[3:0]) */ 978 miscr &= ~(0xf << (12 - 4 * i)); 979 /* activate the UART (UARTx_En) */ 980 miscr |= 1 << (23 - i); 981 /* write new config with activated UART */ 982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 983 } 984 985 if (ret <= 0) { 986 /* the device has no UARTs if we get here */ 987 release_region(iobase->start, ITE_887x_IOSIZE); 988 } 989 990 return ret; 991 } 992 993 static void pci_ite887x_exit(struct pci_dev *dev) 994 { 995 u32 ioport; 996 /* the ioport is bit 0-15 in POSIO0R */ 997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 998 ioport &= 0xffff; 999 release_region(ioport, ITE_887x_IOSIZE); 1000 } 1001 1002 /* 1003 * Oxford Semiconductor Inc. 1004 * Check that device is part of the Tornado range of devices, then determine 1005 * the number of ports available on the device. 1006 */ 1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1008 { 1009 u8 __iomem *p; 1010 unsigned long deviceID; 1011 unsigned int number_uarts = 0; 1012 1013 /* OxSemi Tornado devices are all 0xCxxx */ 1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1015 (dev->device & 0xF000) != 0xC000) 1016 return 0; 1017 1018 p = pci_iomap(dev, 0, 5); 1019 if (p == NULL) 1020 return -ENOMEM; 1021 1022 deviceID = ioread32(p); 1023 /* Tornado device */ 1024 if (deviceID == 0x07000200) { 1025 number_uarts = ioread8(p + 4); 1026 dev_dbg(&dev->dev, 1027 "%d ports detected on Oxford PCI Express device\n", 1028 number_uarts); 1029 } 1030 pci_iounmap(dev, p); 1031 return number_uarts; 1032 } 1033 1034 static int pci_asix_setup(struct serial_private *priv, 1035 const struct pciserial_board *board, 1036 struct uart_8250_port *port, int idx) 1037 { 1038 port->bugs |= UART_BUG_PARITY; 1039 return pci_default_setup(priv, board, port, idx); 1040 } 1041 1042 /* Quatech devices have their own extra interface features */ 1043 1044 struct quatech_feature { 1045 u16 devid; 1046 bool amcc; 1047 }; 1048 1049 #define QPCR_TEST_FOR1 0x3F 1050 #define QPCR_TEST_GET1 0x00 1051 #define QPCR_TEST_FOR2 0x40 1052 #define QPCR_TEST_GET2 0x40 1053 #define QPCR_TEST_FOR3 0x80 1054 #define QPCR_TEST_GET3 0x40 1055 #define QPCR_TEST_FOR4 0xC0 1056 #define QPCR_TEST_GET4 0x80 1057 1058 #define QOPR_CLOCK_X1 0x0000 1059 #define QOPR_CLOCK_X2 0x0001 1060 #define QOPR_CLOCK_X4 0x0002 1061 #define QOPR_CLOCK_X8 0x0003 1062 #define QOPR_CLOCK_RATE_MASK 0x0003 1063 1064 1065 static struct quatech_feature quatech_cards[] = { 1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1085 { 0, } 1086 }; 1087 1088 static int pci_quatech_amcc(u16 devid) 1089 { 1090 struct quatech_feature *qf = &quatech_cards[0]; 1091 while (qf->devid) { 1092 if (qf->devid == devid) 1093 return qf->amcc; 1094 qf++; 1095 } 1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1097 return 0; 1098 }; 1099 1100 static int pci_quatech_rqopr(struct uart_8250_port *port) 1101 { 1102 unsigned long base = port->port.iobase; 1103 u8 LCR, val; 1104 1105 LCR = inb(base + UART_LCR); 1106 outb(0xBF, base + UART_LCR); 1107 val = inb(base + UART_SCR); 1108 outb(LCR, base + UART_LCR); 1109 return val; 1110 } 1111 1112 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1113 { 1114 unsigned long base = port->port.iobase; 1115 u8 LCR, val; 1116 1117 LCR = inb(base + UART_LCR); 1118 outb(0xBF, base + UART_LCR); 1119 val = inb(base + UART_SCR); 1120 outb(qopr, base + UART_SCR); 1121 outb(LCR, base + UART_LCR); 1122 } 1123 1124 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1125 { 1126 unsigned long base = port->port.iobase; 1127 u8 LCR, val, qmcr; 1128 1129 LCR = inb(base + UART_LCR); 1130 outb(0xBF, base + UART_LCR); 1131 val = inb(base + UART_SCR); 1132 outb(val | 0x10, base + UART_SCR); 1133 qmcr = inb(base + UART_MCR); 1134 outb(val, base + UART_SCR); 1135 outb(LCR, base + UART_LCR); 1136 1137 return qmcr; 1138 } 1139 1140 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1141 { 1142 unsigned long base = port->port.iobase; 1143 u8 LCR, val; 1144 1145 LCR = inb(base + UART_LCR); 1146 outb(0xBF, base + UART_LCR); 1147 val = inb(base + UART_SCR); 1148 outb(val | 0x10, base + UART_SCR); 1149 outb(qmcr, base + UART_MCR); 1150 outb(val, base + UART_SCR); 1151 outb(LCR, base + UART_LCR); 1152 } 1153 1154 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1155 { 1156 unsigned long base = port->port.iobase; 1157 u8 LCR, val; 1158 1159 LCR = inb(base + UART_LCR); 1160 outb(0xBF, base + UART_LCR); 1161 val = inb(base + UART_SCR); 1162 if (val & 0x20) { 1163 outb(0x80, UART_LCR); 1164 if (!(inb(UART_SCR) & 0x20)) { 1165 outb(LCR, base + UART_LCR); 1166 return 1; 1167 } 1168 } 1169 return 0; 1170 } 1171 1172 static int pci_quatech_test(struct uart_8250_port *port) 1173 { 1174 u8 reg; 1175 u8 qopr = pci_quatech_rqopr(port); 1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1177 reg = pci_quatech_rqopr(port) & 0xC0; 1178 if (reg != QPCR_TEST_GET1) 1179 return -EINVAL; 1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1181 reg = pci_quatech_rqopr(port) & 0xC0; 1182 if (reg != QPCR_TEST_GET2) 1183 return -EINVAL; 1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1185 reg = pci_quatech_rqopr(port) & 0xC0; 1186 if (reg != QPCR_TEST_GET3) 1187 return -EINVAL; 1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1189 reg = pci_quatech_rqopr(port) & 0xC0; 1190 if (reg != QPCR_TEST_GET4) 1191 return -EINVAL; 1192 1193 pci_quatech_wqopr(port, qopr); 1194 return 0; 1195 } 1196 1197 static int pci_quatech_clock(struct uart_8250_port *port) 1198 { 1199 u8 qopr, reg, set; 1200 unsigned long clock; 1201 1202 if (pci_quatech_test(port) < 0) 1203 return 1843200; 1204 1205 qopr = pci_quatech_rqopr(port); 1206 1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1208 reg = pci_quatech_rqopr(port); 1209 if (reg & QOPR_CLOCK_X8) { 1210 clock = 1843200; 1211 goto out; 1212 } 1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1214 reg = pci_quatech_rqopr(port); 1215 if (!(reg & QOPR_CLOCK_X8)) { 1216 clock = 1843200; 1217 goto out; 1218 } 1219 reg &= QOPR_CLOCK_X8; 1220 if (reg == QOPR_CLOCK_X2) { 1221 clock = 3685400; 1222 set = QOPR_CLOCK_X2; 1223 } else if (reg == QOPR_CLOCK_X4) { 1224 clock = 7372800; 1225 set = QOPR_CLOCK_X4; 1226 } else if (reg == QOPR_CLOCK_X8) { 1227 clock = 14745600; 1228 set = QOPR_CLOCK_X8; 1229 } else { 1230 clock = 1843200; 1231 set = QOPR_CLOCK_X1; 1232 } 1233 qopr &= ~QOPR_CLOCK_RATE_MASK; 1234 qopr |= set; 1235 1236 out: 1237 pci_quatech_wqopr(port, qopr); 1238 return clock; 1239 } 1240 1241 static int pci_quatech_rs422(struct uart_8250_port *port) 1242 { 1243 u8 qmcr; 1244 int rs422 = 0; 1245 1246 if (!pci_quatech_has_qmcr(port)) 1247 return 0; 1248 qmcr = pci_quatech_rqmcr(port); 1249 pci_quatech_wqmcr(port, 0xFF); 1250 if (pci_quatech_rqmcr(port)) 1251 rs422 = 1; 1252 pci_quatech_wqmcr(port, qmcr); 1253 return rs422; 1254 } 1255 1256 static int pci_quatech_init(struct pci_dev *dev) 1257 { 1258 if (pci_quatech_amcc(dev->device)) { 1259 unsigned long base = pci_resource_start(dev, 0); 1260 if (base) { 1261 u32 tmp; 1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1263 tmp = inl(base + 0x3c); 1264 outl(tmp | 0x01000000, base + 0x3c); 1265 outl(tmp &= ~0x01000000, base + 0x3c); 1266 } 1267 } 1268 return 0; 1269 } 1270 1271 static int pci_quatech_setup(struct serial_private *priv, 1272 const struct pciserial_board *board, 1273 struct uart_8250_port *port, int idx) 1274 { 1275 /* Needed by pci_quatech calls below */ 1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1277 /* Set up the clocking */ 1278 port->port.uartclk = pci_quatech_clock(port); 1279 /* For now just warn about RS422 */ 1280 if (pci_quatech_rs422(port)) 1281 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1282 return pci_default_setup(priv, board, port, idx); 1283 } 1284 1285 static void pci_quatech_exit(struct pci_dev *dev) 1286 { 1287 } 1288 1289 static int pci_default_setup(struct serial_private *priv, 1290 const struct pciserial_board *board, 1291 struct uart_8250_port *port, int idx) 1292 { 1293 unsigned int bar, offset = board->first_offset, maxnr; 1294 1295 bar = FL_GET_BASE(board->flags); 1296 if (board->flags & FL_BASE_BARS) 1297 bar += idx; 1298 else 1299 offset += idx * board->uart_offset; 1300 1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1302 (board->reg_shift + 3); 1303 1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1305 return 1; 1306 1307 return setup_port(priv, port, bar, offset, board->reg_shift); 1308 } 1309 1310 static int pci_pericom_setup(struct serial_private *priv, 1311 const struct pciserial_board *board, 1312 struct uart_8250_port *port, int idx) 1313 { 1314 unsigned int bar, offset = board->first_offset, maxnr; 1315 1316 bar = FL_GET_BASE(board->flags); 1317 if (board->flags & FL_BASE_BARS) 1318 bar += idx; 1319 else 1320 offset += idx * board->uart_offset; 1321 1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1323 (board->reg_shift + 3); 1324 1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1326 return 1; 1327 1328 port->port.uartclk = 14745600; 1329 1330 return setup_port(priv, port, bar, offset, board->reg_shift); 1331 } 1332 1333 static int 1334 ce4100_serial_setup(struct serial_private *priv, 1335 const struct pciserial_board *board, 1336 struct uart_8250_port *port, int idx) 1337 { 1338 int ret; 1339 1340 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1341 port->port.iotype = UPIO_MEM32; 1342 port->port.type = PORT_XSCALE; 1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1344 port->port.regshift = 2; 1345 1346 return ret; 1347 } 1348 1349 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a 1350 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c 1351 1352 #define BYT_PRV_CLK 0x800 1353 #define BYT_PRV_CLK_EN (1 << 0) 1354 #define BYT_PRV_CLK_M_VAL_SHIFT 1 1355 #define BYT_PRV_CLK_N_VAL_SHIFT 16 1356 #define BYT_PRV_CLK_UPDATE (1 << 31) 1357 1358 #define BYT_GENERAL_REG 0x808 1359 #define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3) 1360 1361 #define BYT_TX_OVF_INT 0x820 1362 #define BYT_TX_OVF_INT_MASK (1 << 1) 1363 1364 static void 1365 byt_set_termios(struct uart_port *p, struct ktermios *termios, 1366 struct ktermios *old) 1367 { 1368 unsigned int baud = tty_termios_baud_rate(termios); 1369 unsigned int m, n; 1370 u32 reg; 1371 1372 /* 1373 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 1374 * dividers must be adjusted. 1375 * 1376 * uartclk = (m / n) * 100 MHz, where m <= n 1377 */ 1378 switch (baud) { 1379 case 500000: 1380 case 1000000: 1381 case 2000000: 1382 case 4000000: 1383 m = 64; 1384 n = 100; 1385 p->uartclk = 64000000; 1386 break; 1387 case 3500000: 1388 m = 56; 1389 n = 100; 1390 p->uartclk = 56000000; 1391 break; 1392 case 1500000: 1393 case 3000000: 1394 m = 48; 1395 n = 100; 1396 p->uartclk = 48000000; 1397 break; 1398 case 2500000: 1399 m = 40; 1400 n = 100; 1401 p->uartclk = 40000000; 1402 break; 1403 default: 1404 m = 2304; 1405 n = 3125; 1406 p->uartclk = 73728000; 1407 } 1408 1409 /* Reset the clock */ 1410 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 1411 writel(reg, p->membase + BYT_PRV_CLK); 1412 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 1413 writel(reg, p->membase + BYT_PRV_CLK); 1414 1415 /* 1416 * If auto-handshake mechanism is not enabled, 1417 * disable rts_n override 1418 */ 1419 reg = readl(p->membase + BYT_GENERAL_REG); 1420 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE; 1421 if (termios->c_cflag & CRTSCTS) 1422 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE; 1423 writel(reg, p->membase + BYT_GENERAL_REG); 1424 1425 serial8250_do_set_termios(p, termios, old); 1426 } 1427 1428 static bool byt_dma_filter(struct dma_chan *chan, void *param) 1429 { 1430 return chan->chan_id == *(int *)param; 1431 } 1432 1433 static int 1434 byt_serial_setup(struct serial_private *priv, 1435 const struct pciserial_board *board, 1436 struct uart_8250_port *port, int idx) 1437 { 1438 struct uart_8250_dma *dma; 1439 int ret; 1440 1441 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL); 1442 if (!dma) 1443 return -ENOMEM; 1444 1445 switch (priv->dev->device) { 1446 case PCI_DEVICE_ID_INTEL_BYT_UART1: 1447 dma->rx_chan_id = 3; 1448 dma->tx_chan_id = 2; 1449 break; 1450 case PCI_DEVICE_ID_INTEL_BYT_UART2: 1451 dma->rx_chan_id = 5; 1452 dma->tx_chan_id = 4; 1453 break; 1454 default: 1455 return -EINVAL; 1456 } 1457 1458 dma->rxconf.slave_id = dma->rx_chan_id; 1459 dma->rxconf.src_maxburst = 16; 1460 1461 dma->txconf.slave_id = dma->tx_chan_id; 1462 dma->txconf.dst_maxburst = 16; 1463 1464 dma->fn = byt_dma_filter; 1465 dma->rx_param = &dma->rx_chan_id; 1466 dma->tx_param = &dma->tx_chan_id; 1467 1468 ret = pci_default_setup(priv, board, port, idx); 1469 port->port.iotype = UPIO_MEM; 1470 port->port.type = PORT_16550A; 1471 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1472 port->port.set_termios = byt_set_termios; 1473 port->port.fifosize = 64; 1474 port->tx_loadsz = 64; 1475 port->dma = dma; 1476 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE; 1477 1478 /* Disable Tx counter interrupts */ 1479 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT); 1480 1481 return ret; 1482 } 1483 1484 static int 1485 pci_omegapci_setup(struct serial_private *priv, 1486 const struct pciserial_board *board, 1487 struct uart_8250_port *port, int idx) 1488 { 1489 return setup_port(priv, port, 2, idx * 8, 0); 1490 } 1491 1492 static int 1493 pci_brcm_trumanage_setup(struct serial_private *priv, 1494 const struct pciserial_board *board, 1495 struct uart_8250_port *port, int idx) 1496 { 1497 int ret = pci_default_setup(priv, board, port, idx); 1498 1499 port->port.type = PORT_BRCM_TRUMANAGE; 1500 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1501 return ret; 1502 } 1503 1504 static int pci_fintek_setup(struct serial_private *priv, 1505 const struct pciserial_board *board, 1506 struct uart_8250_port *port, int idx) 1507 { 1508 struct pci_dev *pdev = priv->dev; 1509 unsigned long base; 1510 unsigned long iobase; 1511 unsigned long ciobase = 0; 1512 u8 config_base; 1513 1514 /* 1515 * We are supposed to be able to read these from the PCI config space, 1516 * but the values there don't seem to match what we need to use, so 1517 * just use these hard-coded values for now, as they are correct. 1518 */ 1519 switch (idx) { 1520 case 0: iobase = 0xe000; config_base = 0x40; break; 1521 case 1: iobase = 0xe008; config_base = 0x48; break; 1522 case 2: iobase = 0xe010; config_base = 0x50; break; 1523 case 3: iobase = 0xe018; config_base = 0x58; break; 1524 case 4: iobase = 0xe020; config_base = 0x60; break; 1525 case 5: iobase = 0xe028; config_base = 0x68; break; 1526 case 6: iobase = 0xe030; config_base = 0x70; break; 1527 case 7: iobase = 0xe038; config_base = 0x78; break; 1528 case 8: iobase = 0xe040; config_base = 0x80; break; 1529 case 9: iobase = 0xe048; config_base = 0x88; break; 1530 case 10: iobase = 0xe050; config_base = 0x90; break; 1531 case 11: iobase = 0xe058; config_base = 0x98; break; 1532 default: 1533 /* Unknown number of ports, get out of here */ 1534 return -EINVAL; 1535 } 1536 1537 if (idx < 4) { 1538 base = pci_resource_start(priv->dev, 3); 1539 ciobase = (int)(base + (0x8 * idx)); 1540 } 1541 1542 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n", 1543 __func__, idx, iobase, ciobase, config_base); 1544 1545 /* Enable UART I/O port */ 1546 pci_write_config_byte(pdev, config_base + 0x00, 0x01); 1547 1548 /* Select 128-byte FIFO and 8x FIFO threshold */ 1549 pci_write_config_byte(pdev, config_base + 0x01, 0x33); 1550 1551 /* LSB UART */ 1552 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff)); 1553 1554 /* MSB UART */ 1555 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8)); 1556 1557 /* irq number, this usually fails, but the spec says to do it anyway. */ 1558 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq); 1559 1560 port->port.iotype = UPIO_PORT; 1561 port->port.iobase = iobase; 1562 port->port.mapbase = 0; 1563 port->port.membase = NULL; 1564 port->port.regshift = 0; 1565 1566 return 0; 1567 } 1568 1569 static int skip_tx_en_setup(struct serial_private *priv, 1570 const struct pciserial_board *board, 1571 struct uart_8250_port *port, int idx) 1572 { 1573 port->port.flags |= UPF_NO_TXEN_TEST; 1574 dev_dbg(&priv->dev->dev, 1575 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1576 priv->dev->vendor, priv->dev->device, 1577 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1578 1579 return pci_default_setup(priv, board, port, idx); 1580 } 1581 1582 static void kt_handle_break(struct uart_port *p) 1583 { 1584 struct uart_8250_port *up = up_to_u8250p(p); 1585 /* 1586 * On receipt of a BI, serial device in Intel ME (Intel 1587 * management engine) needs to have its fifos cleared for sane 1588 * SOL (Serial Over Lan) output. 1589 */ 1590 serial8250_clear_and_reinit_fifos(up); 1591 } 1592 1593 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1594 { 1595 struct uart_8250_port *up = up_to_u8250p(p); 1596 unsigned int val; 1597 1598 /* 1599 * When the Intel ME (management engine) gets reset its serial 1600 * port registers could return 0 momentarily. Functions like 1601 * serial8250_console_write, read and save the IER, perform 1602 * some operation and then restore it. In order to avoid 1603 * setting IER register inadvertently to 0, if the value read 1604 * is 0, double check with ier value in uart_8250_port and use 1605 * that instead. up->ier should be the same value as what is 1606 * currently configured. 1607 */ 1608 val = inb(p->iobase + offset); 1609 if (offset == UART_IER) { 1610 if (val == 0) 1611 val = up->ier; 1612 } 1613 return val; 1614 } 1615 1616 static int kt_serial_setup(struct serial_private *priv, 1617 const struct pciserial_board *board, 1618 struct uart_8250_port *port, int idx) 1619 { 1620 port->port.flags |= UPF_BUG_THRE; 1621 port->port.serial_in = kt_serial_in; 1622 port->port.handle_break = kt_handle_break; 1623 return skip_tx_en_setup(priv, board, port, idx); 1624 } 1625 1626 static int pci_eg20t_init(struct pci_dev *dev) 1627 { 1628 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1629 return -ENODEV; 1630 #else 1631 return 0; 1632 #endif 1633 } 1634 1635 static int 1636 pci_xr17c154_setup(struct serial_private *priv, 1637 const struct pciserial_board *board, 1638 struct uart_8250_port *port, int idx) 1639 { 1640 port->port.flags |= UPF_EXAR_EFR; 1641 return pci_default_setup(priv, board, port, idx); 1642 } 1643 1644 static int 1645 pci_xr17v35x_setup(struct serial_private *priv, 1646 const struct pciserial_board *board, 1647 struct uart_8250_port *port, int idx) 1648 { 1649 u8 __iomem *p; 1650 1651 p = pci_ioremap_bar(priv->dev, 0); 1652 if (p == NULL) 1653 return -ENOMEM; 1654 1655 port->port.flags |= UPF_EXAR_EFR; 1656 1657 /* 1658 * Setup Multipurpose Input/Output pins. 1659 */ 1660 if (idx == 0) { 1661 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/ 1662 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/ 1663 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/ 1664 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/ 1665 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/ 1666 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/ 1667 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/ 1668 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/ 1669 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/ 1670 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/ 1671 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/ 1672 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/ 1673 } 1674 writeb(0x00, p + UART_EXAR_8XMODE); 1675 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1676 writeb(128, p + UART_EXAR_TXTRG); 1677 writeb(128, p + UART_EXAR_RXTRG); 1678 iounmap(p); 1679 1680 return pci_default_setup(priv, board, port, idx); 1681 } 1682 1683 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 1684 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 1685 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 1686 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 1687 1688 static int 1689 pci_fastcom335_setup(struct serial_private *priv, 1690 const struct pciserial_board *board, 1691 struct uart_8250_port *port, int idx) 1692 { 1693 u8 __iomem *p; 1694 1695 p = pci_ioremap_bar(priv->dev, 0); 1696 if (p == NULL) 1697 return -ENOMEM; 1698 1699 port->port.flags |= UPF_EXAR_EFR; 1700 1701 /* 1702 * Setup Multipurpose Input/Output pins. 1703 */ 1704 if (idx == 0) { 1705 switch (priv->dev->device) { 1706 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 1707 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 1708 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */ 1709 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */ 1710 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */ 1711 break; 1712 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 1713 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 1714 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */ 1715 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */ 1716 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */ 1717 break; 1718 } 1719 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */ 1720 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */ 1721 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */ 1722 } 1723 writeb(0x00, p + UART_EXAR_8XMODE); 1724 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 1725 writeb(32, p + UART_EXAR_TXTRG); 1726 writeb(32, p + UART_EXAR_RXTRG); 1727 iounmap(p); 1728 1729 return pci_default_setup(priv, board, port, idx); 1730 } 1731 1732 static int 1733 pci_wch_ch353_setup(struct serial_private *priv, 1734 const struct pciserial_board *board, 1735 struct uart_8250_port *port, int idx) 1736 { 1737 port->port.flags |= UPF_FIXED_TYPE; 1738 port->port.type = PORT_16550A; 1739 return pci_default_setup(priv, board, port, idx); 1740 } 1741 1742 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1743 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1744 #define PCI_DEVICE_ID_OCTPRO 0x0001 1745 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1746 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1747 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1748 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1749 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1750 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1751 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1752 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1753 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1754 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1755 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1756 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1757 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1758 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1759 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1760 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1761 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1762 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1763 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1764 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1765 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1766 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1767 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1768 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1769 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1770 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1771 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1772 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1773 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1774 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1775 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1776 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1777 #define PCI_VENDOR_ID_WCH 0x4348 1778 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1779 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1780 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1781 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1782 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1783 #define PCI_VENDOR_ID_AGESTAR 0x5372 1784 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1785 #define PCI_VENDOR_ID_ASIX 0x9710 1786 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 1787 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 1788 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 1789 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1790 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1791 1792 #define PCI_VENDOR_ID_SUNIX 0x1fd4 1793 #define PCI_DEVICE_ID_SUNIX_1999 0x1999 1794 1795 1796 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1797 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1798 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1799 1800 /* 1801 * Master list of serial port init/setup/exit quirks. 1802 * This does not describe the general nature of the port. 1803 * (ie, baud base, number and location of ports, etc) 1804 * 1805 * This list is ordered alphabetically by vendor then device. 1806 * Specific entries must come before more generic entries. 1807 */ 1808 static struct pci_serial_quirk pci_serial_quirks[] __refdata = { 1809 /* 1810 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1811 */ 1812 { 1813 .vendor = PCI_VENDOR_ID_AMCC, 1814 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1815 .subvendor = PCI_ANY_ID, 1816 .subdevice = PCI_ANY_ID, 1817 .setup = addidata_apci7800_setup, 1818 }, 1819 /* 1820 * AFAVLAB cards - these may be called via parport_serial 1821 * It is not clear whether this applies to all products. 1822 */ 1823 { 1824 .vendor = PCI_VENDOR_ID_AFAVLAB, 1825 .device = PCI_ANY_ID, 1826 .subvendor = PCI_ANY_ID, 1827 .subdevice = PCI_ANY_ID, 1828 .setup = afavlab_setup, 1829 }, 1830 /* 1831 * HP Diva 1832 */ 1833 { 1834 .vendor = PCI_VENDOR_ID_HP, 1835 .device = PCI_DEVICE_ID_HP_DIVA, 1836 .subvendor = PCI_ANY_ID, 1837 .subdevice = PCI_ANY_ID, 1838 .init = pci_hp_diva_init, 1839 .setup = pci_hp_diva_setup, 1840 }, 1841 /* 1842 * Intel 1843 */ 1844 { 1845 .vendor = PCI_VENDOR_ID_INTEL, 1846 .device = PCI_DEVICE_ID_INTEL_80960_RP, 1847 .subvendor = 0xe4bf, 1848 .subdevice = PCI_ANY_ID, 1849 .init = pci_inteli960ni_init, 1850 .setup = pci_default_setup, 1851 }, 1852 { 1853 .vendor = PCI_VENDOR_ID_INTEL, 1854 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 1855 .subvendor = PCI_ANY_ID, 1856 .subdevice = PCI_ANY_ID, 1857 .setup = skip_tx_en_setup, 1858 }, 1859 { 1860 .vendor = PCI_VENDOR_ID_INTEL, 1861 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 1862 .subvendor = PCI_ANY_ID, 1863 .subdevice = PCI_ANY_ID, 1864 .setup = skip_tx_en_setup, 1865 }, 1866 { 1867 .vendor = PCI_VENDOR_ID_INTEL, 1868 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 1869 .subvendor = PCI_ANY_ID, 1870 .subdevice = PCI_ANY_ID, 1871 .setup = skip_tx_en_setup, 1872 }, 1873 { 1874 .vendor = PCI_VENDOR_ID_INTEL, 1875 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 1876 .subvendor = PCI_ANY_ID, 1877 .subdevice = PCI_ANY_ID, 1878 .setup = ce4100_serial_setup, 1879 }, 1880 { 1881 .vendor = PCI_VENDOR_ID_INTEL, 1882 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 1883 .subvendor = PCI_ANY_ID, 1884 .subdevice = PCI_ANY_ID, 1885 .setup = kt_serial_setup, 1886 }, 1887 { 1888 .vendor = PCI_VENDOR_ID_INTEL, 1889 .device = PCI_DEVICE_ID_INTEL_BYT_UART1, 1890 .subvendor = PCI_ANY_ID, 1891 .subdevice = PCI_ANY_ID, 1892 .setup = byt_serial_setup, 1893 }, 1894 { 1895 .vendor = PCI_VENDOR_ID_INTEL, 1896 .device = PCI_DEVICE_ID_INTEL_BYT_UART2, 1897 .subvendor = PCI_ANY_ID, 1898 .subdevice = PCI_ANY_ID, 1899 .setup = byt_serial_setup, 1900 }, 1901 /* 1902 * ITE 1903 */ 1904 { 1905 .vendor = PCI_VENDOR_ID_ITE, 1906 .device = PCI_DEVICE_ID_ITE_8872, 1907 .subvendor = PCI_ANY_ID, 1908 .subdevice = PCI_ANY_ID, 1909 .init = pci_ite887x_init, 1910 .setup = pci_default_setup, 1911 .exit = pci_ite887x_exit, 1912 }, 1913 /* 1914 * National Instruments 1915 */ 1916 { 1917 .vendor = PCI_VENDOR_ID_NI, 1918 .device = PCI_DEVICE_ID_NI_PCI23216, 1919 .subvendor = PCI_ANY_ID, 1920 .subdevice = PCI_ANY_ID, 1921 .init = pci_ni8420_init, 1922 .setup = pci_default_setup, 1923 .exit = pci_ni8420_exit, 1924 }, 1925 { 1926 .vendor = PCI_VENDOR_ID_NI, 1927 .device = PCI_DEVICE_ID_NI_PCI2328, 1928 .subvendor = PCI_ANY_ID, 1929 .subdevice = PCI_ANY_ID, 1930 .init = pci_ni8420_init, 1931 .setup = pci_default_setup, 1932 .exit = pci_ni8420_exit, 1933 }, 1934 { 1935 .vendor = PCI_VENDOR_ID_NI, 1936 .device = PCI_DEVICE_ID_NI_PCI2324, 1937 .subvendor = PCI_ANY_ID, 1938 .subdevice = PCI_ANY_ID, 1939 .init = pci_ni8420_init, 1940 .setup = pci_default_setup, 1941 .exit = pci_ni8420_exit, 1942 }, 1943 { 1944 .vendor = PCI_VENDOR_ID_NI, 1945 .device = PCI_DEVICE_ID_NI_PCI2322, 1946 .subvendor = PCI_ANY_ID, 1947 .subdevice = PCI_ANY_ID, 1948 .init = pci_ni8420_init, 1949 .setup = pci_default_setup, 1950 .exit = pci_ni8420_exit, 1951 }, 1952 { 1953 .vendor = PCI_VENDOR_ID_NI, 1954 .device = PCI_DEVICE_ID_NI_PCI2324I, 1955 .subvendor = PCI_ANY_ID, 1956 .subdevice = PCI_ANY_ID, 1957 .init = pci_ni8420_init, 1958 .setup = pci_default_setup, 1959 .exit = pci_ni8420_exit, 1960 }, 1961 { 1962 .vendor = PCI_VENDOR_ID_NI, 1963 .device = PCI_DEVICE_ID_NI_PCI2322I, 1964 .subvendor = PCI_ANY_ID, 1965 .subdevice = PCI_ANY_ID, 1966 .init = pci_ni8420_init, 1967 .setup = pci_default_setup, 1968 .exit = pci_ni8420_exit, 1969 }, 1970 { 1971 .vendor = PCI_VENDOR_ID_NI, 1972 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 1973 .subvendor = PCI_ANY_ID, 1974 .subdevice = PCI_ANY_ID, 1975 .init = pci_ni8420_init, 1976 .setup = pci_default_setup, 1977 .exit = pci_ni8420_exit, 1978 }, 1979 { 1980 .vendor = PCI_VENDOR_ID_NI, 1981 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 1982 .subvendor = PCI_ANY_ID, 1983 .subdevice = PCI_ANY_ID, 1984 .init = pci_ni8420_init, 1985 .setup = pci_default_setup, 1986 .exit = pci_ni8420_exit, 1987 }, 1988 { 1989 .vendor = PCI_VENDOR_ID_NI, 1990 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 1991 .subvendor = PCI_ANY_ID, 1992 .subdevice = PCI_ANY_ID, 1993 .init = pci_ni8420_init, 1994 .setup = pci_default_setup, 1995 .exit = pci_ni8420_exit, 1996 }, 1997 { 1998 .vendor = PCI_VENDOR_ID_NI, 1999 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2000 .subvendor = PCI_ANY_ID, 2001 .subdevice = PCI_ANY_ID, 2002 .init = pci_ni8420_init, 2003 .setup = pci_default_setup, 2004 .exit = pci_ni8420_exit, 2005 }, 2006 { 2007 .vendor = PCI_VENDOR_ID_NI, 2008 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2009 .subvendor = PCI_ANY_ID, 2010 .subdevice = PCI_ANY_ID, 2011 .init = pci_ni8420_init, 2012 .setup = pci_default_setup, 2013 .exit = pci_ni8420_exit, 2014 }, 2015 { 2016 .vendor = PCI_VENDOR_ID_NI, 2017 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2018 .subvendor = PCI_ANY_ID, 2019 .subdevice = PCI_ANY_ID, 2020 .init = pci_ni8420_init, 2021 .setup = pci_default_setup, 2022 .exit = pci_ni8420_exit, 2023 }, 2024 { 2025 .vendor = PCI_VENDOR_ID_NI, 2026 .device = PCI_ANY_ID, 2027 .subvendor = PCI_ANY_ID, 2028 .subdevice = PCI_ANY_ID, 2029 .init = pci_ni8430_init, 2030 .setup = pci_ni8430_setup, 2031 .exit = pci_ni8430_exit, 2032 }, 2033 /* Quatech */ 2034 { 2035 .vendor = PCI_VENDOR_ID_QUATECH, 2036 .device = PCI_ANY_ID, 2037 .subvendor = PCI_ANY_ID, 2038 .subdevice = PCI_ANY_ID, 2039 .init = pci_quatech_init, 2040 .setup = pci_quatech_setup, 2041 .exit = pci_quatech_exit, 2042 }, 2043 /* 2044 * Panacom 2045 */ 2046 { 2047 .vendor = PCI_VENDOR_ID_PANACOM, 2048 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2049 .subvendor = PCI_ANY_ID, 2050 .subdevice = PCI_ANY_ID, 2051 .init = pci_plx9050_init, 2052 .setup = pci_default_setup, 2053 .exit = pci_plx9050_exit, 2054 }, 2055 { 2056 .vendor = PCI_VENDOR_ID_PANACOM, 2057 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2058 .subvendor = PCI_ANY_ID, 2059 .subdevice = PCI_ANY_ID, 2060 .init = pci_plx9050_init, 2061 .setup = pci_default_setup, 2062 .exit = pci_plx9050_exit, 2063 }, 2064 /* 2065 * Pericom 2066 */ 2067 { 2068 .vendor = 0x12d8, 2069 .device = 0x7952, 2070 .subvendor = PCI_ANY_ID, 2071 .subdevice = PCI_ANY_ID, 2072 .setup = pci_pericom_setup, 2073 }, 2074 { 2075 .vendor = 0x12d8, 2076 .device = 0x7954, 2077 .subvendor = PCI_ANY_ID, 2078 .subdevice = PCI_ANY_ID, 2079 .setup = pci_pericom_setup, 2080 }, 2081 { 2082 .vendor = 0x12d8, 2083 .device = 0x7958, 2084 .subvendor = PCI_ANY_ID, 2085 .subdevice = PCI_ANY_ID, 2086 .setup = pci_pericom_setup, 2087 }, 2088 2089 /* 2090 * PLX 2091 */ 2092 { 2093 .vendor = PCI_VENDOR_ID_PLX, 2094 .device = PCI_DEVICE_ID_PLX_9030, 2095 .subvendor = PCI_SUBVENDOR_ID_PERLE, 2096 .subdevice = PCI_ANY_ID, 2097 .setup = pci_default_setup, 2098 }, 2099 { 2100 .vendor = PCI_VENDOR_ID_PLX, 2101 .device = PCI_DEVICE_ID_PLX_9050, 2102 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2103 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2104 .init = pci_plx9050_init, 2105 .setup = pci_default_setup, 2106 .exit = pci_plx9050_exit, 2107 }, 2108 { 2109 .vendor = PCI_VENDOR_ID_PLX, 2110 .device = PCI_DEVICE_ID_PLX_9050, 2111 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2112 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2113 .init = pci_plx9050_init, 2114 .setup = pci_default_setup, 2115 .exit = pci_plx9050_exit, 2116 }, 2117 { 2118 .vendor = PCI_VENDOR_ID_PLX, 2119 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2120 .subvendor = PCI_VENDOR_ID_PLX, 2121 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2122 .init = pci_plx9050_init, 2123 .setup = pci_default_setup, 2124 .exit = pci_plx9050_exit, 2125 }, 2126 /* 2127 * SBS Technologies, Inc., PMC-OCTALPRO 232 2128 */ 2129 { 2130 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2131 .device = PCI_DEVICE_ID_OCTPRO, 2132 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2133 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2134 .init = sbs_init, 2135 .setup = sbs_setup, 2136 .exit = sbs_exit, 2137 }, 2138 /* 2139 * SBS Technologies, Inc., PMC-OCTALPRO 422 2140 */ 2141 { 2142 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2143 .device = PCI_DEVICE_ID_OCTPRO, 2144 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2145 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2146 .init = sbs_init, 2147 .setup = sbs_setup, 2148 .exit = sbs_exit, 2149 }, 2150 /* 2151 * SBS Technologies, Inc., P-Octal 232 2152 */ 2153 { 2154 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2155 .device = PCI_DEVICE_ID_OCTPRO, 2156 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2157 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2158 .init = sbs_init, 2159 .setup = sbs_setup, 2160 .exit = sbs_exit, 2161 }, 2162 /* 2163 * SBS Technologies, Inc., P-Octal 422 2164 */ 2165 { 2166 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2167 .device = PCI_DEVICE_ID_OCTPRO, 2168 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2169 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2170 .init = sbs_init, 2171 .setup = sbs_setup, 2172 .exit = sbs_exit, 2173 }, 2174 /* 2175 * SIIG cards - these may be called via parport_serial 2176 */ 2177 { 2178 .vendor = PCI_VENDOR_ID_SIIG, 2179 .device = PCI_ANY_ID, 2180 .subvendor = PCI_ANY_ID, 2181 .subdevice = PCI_ANY_ID, 2182 .init = pci_siig_init, 2183 .setup = pci_siig_setup, 2184 }, 2185 /* 2186 * Titan cards 2187 */ 2188 { 2189 .vendor = PCI_VENDOR_ID_TITAN, 2190 .device = PCI_DEVICE_ID_TITAN_400L, 2191 .subvendor = PCI_ANY_ID, 2192 .subdevice = PCI_ANY_ID, 2193 .setup = titan_400l_800l_setup, 2194 }, 2195 { 2196 .vendor = PCI_VENDOR_ID_TITAN, 2197 .device = PCI_DEVICE_ID_TITAN_800L, 2198 .subvendor = PCI_ANY_ID, 2199 .subdevice = PCI_ANY_ID, 2200 .setup = titan_400l_800l_setup, 2201 }, 2202 /* 2203 * Timedia cards 2204 */ 2205 { 2206 .vendor = PCI_VENDOR_ID_TIMEDIA, 2207 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2208 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2209 .subdevice = PCI_ANY_ID, 2210 .probe = pci_timedia_probe, 2211 .init = pci_timedia_init, 2212 .setup = pci_timedia_setup, 2213 }, 2214 { 2215 .vendor = PCI_VENDOR_ID_TIMEDIA, 2216 .device = PCI_ANY_ID, 2217 .subvendor = PCI_ANY_ID, 2218 .subdevice = PCI_ANY_ID, 2219 .setup = pci_timedia_setup, 2220 }, 2221 /* 2222 * SUNIX (Timedia) cards 2223 * Do not "probe" for these cards as there is at least one combination 2224 * card that should be handled by parport_pc that doesn't match the 2225 * rule in pci_timedia_probe. 2226 * It is part number is MIO5079A but its subdevice ID is 0x0102. 2227 * There are some boards with part number SER5037AL that report 2228 * subdevice ID 0x0002. 2229 */ 2230 { 2231 .vendor = PCI_VENDOR_ID_SUNIX, 2232 .device = PCI_DEVICE_ID_SUNIX_1999, 2233 .subvendor = PCI_VENDOR_ID_SUNIX, 2234 .subdevice = PCI_ANY_ID, 2235 .init = pci_timedia_init, 2236 .setup = pci_timedia_setup, 2237 }, 2238 /* 2239 * Exar cards 2240 */ 2241 { 2242 .vendor = PCI_VENDOR_ID_EXAR, 2243 .device = PCI_DEVICE_ID_EXAR_XR17C152, 2244 .subvendor = PCI_ANY_ID, 2245 .subdevice = PCI_ANY_ID, 2246 .setup = pci_xr17c154_setup, 2247 }, 2248 { 2249 .vendor = PCI_VENDOR_ID_EXAR, 2250 .device = PCI_DEVICE_ID_EXAR_XR17C154, 2251 .subvendor = PCI_ANY_ID, 2252 .subdevice = PCI_ANY_ID, 2253 .setup = pci_xr17c154_setup, 2254 }, 2255 { 2256 .vendor = PCI_VENDOR_ID_EXAR, 2257 .device = PCI_DEVICE_ID_EXAR_XR17C158, 2258 .subvendor = PCI_ANY_ID, 2259 .subdevice = PCI_ANY_ID, 2260 .setup = pci_xr17c154_setup, 2261 }, 2262 { 2263 .vendor = PCI_VENDOR_ID_EXAR, 2264 .device = PCI_DEVICE_ID_EXAR_XR17V352, 2265 .subvendor = PCI_ANY_ID, 2266 .subdevice = PCI_ANY_ID, 2267 .setup = pci_xr17v35x_setup, 2268 }, 2269 { 2270 .vendor = PCI_VENDOR_ID_EXAR, 2271 .device = PCI_DEVICE_ID_EXAR_XR17V354, 2272 .subvendor = PCI_ANY_ID, 2273 .subdevice = PCI_ANY_ID, 2274 .setup = pci_xr17v35x_setup, 2275 }, 2276 { 2277 .vendor = PCI_VENDOR_ID_EXAR, 2278 .device = PCI_DEVICE_ID_EXAR_XR17V358, 2279 .subvendor = PCI_ANY_ID, 2280 .subdevice = PCI_ANY_ID, 2281 .setup = pci_xr17v35x_setup, 2282 }, 2283 /* 2284 * Xircom cards 2285 */ 2286 { 2287 .vendor = PCI_VENDOR_ID_XIRCOM, 2288 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2289 .subvendor = PCI_ANY_ID, 2290 .subdevice = PCI_ANY_ID, 2291 .init = pci_xircom_init, 2292 .setup = pci_default_setup, 2293 }, 2294 /* 2295 * Netmos cards - these may be called via parport_serial 2296 */ 2297 { 2298 .vendor = PCI_VENDOR_ID_NETMOS, 2299 .device = PCI_ANY_ID, 2300 .subvendor = PCI_ANY_ID, 2301 .subdevice = PCI_ANY_ID, 2302 .init = pci_netmos_init, 2303 .setup = pci_netmos_9900_setup, 2304 }, 2305 /* 2306 * For Oxford Semiconductor Tornado based devices 2307 */ 2308 { 2309 .vendor = PCI_VENDOR_ID_OXSEMI, 2310 .device = PCI_ANY_ID, 2311 .subvendor = PCI_ANY_ID, 2312 .subdevice = PCI_ANY_ID, 2313 .init = pci_oxsemi_tornado_init, 2314 .setup = pci_default_setup, 2315 }, 2316 { 2317 .vendor = PCI_VENDOR_ID_MAINPINE, 2318 .device = PCI_ANY_ID, 2319 .subvendor = PCI_ANY_ID, 2320 .subdevice = PCI_ANY_ID, 2321 .init = pci_oxsemi_tornado_init, 2322 .setup = pci_default_setup, 2323 }, 2324 { 2325 .vendor = PCI_VENDOR_ID_DIGI, 2326 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2327 .subvendor = PCI_SUBVENDOR_ID_IBM, 2328 .subdevice = PCI_ANY_ID, 2329 .init = pci_oxsemi_tornado_init, 2330 .setup = pci_default_setup, 2331 }, 2332 { 2333 .vendor = PCI_VENDOR_ID_INTEL, 2334 .device = 0x8811, 2335 .subvendor = PCI_ANY_ID, 2336 .subdevice = PCI_ANY_ID, 2337 .init = pci_eg20t_init, 2338 .setup = pci_default_setup, 2339 }, 2340 { 2341 .vendor = PCI_VENDOR_ID_INTEL, 2342 .device = 0x8812, 2343 .subvendor = PCI_ANY_ID, 2344 .subdevice = PCI_ANY_ID, 2345 .init = pci_eg20t_init, 2346 .setup = pci_default_setup, 2347 }, 2348 { 2349 .vendor = PCI_VENDOR_ID_INTEL, 2350 .device = 0x8813, 2351 .subvendor = PCI_ANY_ID, 2352 .subdevice = PCI_ANY_ID, 2353 .init = pci_eg20t_init, 2354 .setup = pci_default_setup, 2355 }, 2356 { 2357 .vendor = PCI_VENDOR_ID_INTEL, 2358 .device = 0x8814, 2359 .subvendor = PCI_ANY_ID, 2360 .subdevice = PCI_ANY_ID, 2361 .init = pci_eg20t_init, 2362 .setup = pci_default_setup, 2363 }, 2364 { 2365 .vendor = 0x10DB, 2366 .device = 0x8027, 2367 .subvendor = PCI_ANY_ID, 2368 .subdevice = PCI_ANY_ID, 2369 .init = pci_eg20t_init, 2370 .setup = pci_default_setup, 2371 }, 2372 { 2373 .vendor = 0x10DB, 2374 .device = 0x8028, 2375 .subvendor = PCI_ANY_ID, 2376 .subdevice = PCI_ANY_ID, 2377 .init = pci_eg20t_init, 2378 .setup = pci_default_setup, 2379 }, 2380 { 2381 .vendor = 0x10DB, 2382 .device = 0x8029, 2383 .subvendor = PCI_ANY_ID, 2384 .subdevice = PCI_ANY_ID, 2385 .init = pci_eg20t_init, 2386 .setup = pci_default_setup, 2387 }, 2388 { 2389 .vendor = 0x10DB, 2390 .device = 0x800C, 2391 .subvendor = PCI_ANY_ID, 2392 .subdevice = PCI_ANY_ID, 2393 .init = pci_eg20t_init, 2394 .setup = pci_default_setup, 2395 }, 2396 { 2397 .vendor = 0x10DB, 2398 .device = 0x800D, 2399 .subvendor = PCI_ANY_ID, 2400 .subdevice = PCI_ANY_ID, 2401 .init = pci_eg20t_init, 2402 .setup = pci_default_setup, 2403 }, 2404 /* 2405 * Cronyx Omega PCI (PLX-chip based) 2406 */ 2407 { 2408 .vendor = PCI_VENDOR_ID_PLX, 2409 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2410 .subvendor = PCI_ANY_ID, 2411 .subdevice = PCI_ANY_ID, 2412 .setup = pci_omegapci_setup, 2413 }, 2414 /* WCH CH353 1S1P card (16550 clone) */ 2415 { 2416 .vendor = PCI_VENDOR_ID_WCH, 2417 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2418 .subvendor = PCI_ANY_ID, 2419 .subdevice = PCI_ANY_ID, 2420 .setup = pci_wch_ch353_setup, 2421 }, 2422 /* WCH CH353 2S1P card (16550 clone) */ 2423 { 2424 .vendor = PCI_VENDOR_ID_WCH, 2425 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2426 .subvendor = PCI_ANY_ID, 2427 .subdevice = PCI_ANY_ID, 2428 .setup = pci_wch_ch353_setup, 2429 }, 2430 /* WCH CH353 4S card (16550 clone) */ 2431 { 2432 .vendor = PCI_VENDOR_ID_WCH, 2433 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2434 .subvendor = PCI_ANY_ID, 2435 .subdevice = PCI_ANY_ID, 2436 .setup = pci_wch_ch353_setup, 2437 }, 2438 /* WCH CH353 2S1PF card (16550 clone) */ 2439 { 2440 .vendor = PCI_VENDOR_ID_WCH, 2441 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2442 .subvendor = PCI_ANY_ID, 2443 .subdevice = PCI_ANY_ID, 2444 .setup = pci_wch_ch353_setup, 2445 }, 2446 /* WCH CH352 2S card (16550 clone) */ 2447 { 2448 .vendor = PCI_VENDOR_ID_WCH, 2449 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2450 .subvendor = PCI_ANY_ID, 2451 .subdevice = PCI_ANY_ID, 2452 .setup = pci_wch_ch353_setup, 2453 }, 2454 /* 2455 * ASIX devices with FIFO bug 2456 */ 2457 { 2458 .vendor = PCI_VENDOR_ID_ASIX, 2459 .device = PCI_ANY_ID, 2460 .subvendor = PCI_ANY_ID, 2461 .subdevice = PCI_ANY_ID, 2462 .setup = pci_asix_setup, 2463 }, 2464 /* 2465 * Commtech, Inc. Fastcom adapters 2466 * 2467 */ 2468 { 2469 .vendor = PCI_VENDOR_ID_COMMTECH, 2470 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335, 2471 .subvendor = PCI_ANY_ID, 2472 .subdevice = PCI_ANY_ID, 2473 .setup = pci_fastcom335_setup, 2474 }, 2475 { 2476 .vendor = PCI_VENDOR_ID_COMMTECH, 2477 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335, 2478 .subvendor = PCI_ANY_ID, 2479 .subdevice = PCI_ANY_ID, 2480 .setup = pci_fastcom335_setup, 2481 }, 2482 { 2483 .vendor = PCI_VENDOR_ID_COMMTECH, 2484 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335, 2485 .subvendor = PCI_ANY_ID, 2486 .subdevice = PCI_ANY_ID, 2487 .setup = pci_fastcom335_setup, 2488 }, 2489 { 2490 .vendor = PCI_VENDOR_ID_COMMTECH, 2491 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335, 2492 .subvendor = PCI_ANY_ID, 2493 .subdevice = PCI_ANY_ID, 2494 .setup = pci_fastcom335_setup, 2495 }, 2496 { 2497 .vendor = PCI_VENDOR_ID_COMMTECH, 2498 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE, 2499 .subvendor = PCI_ANY_ID, 2500 .subdevice = PCI_ANY_ID, 2501 .setup = pci_xr17v35x_setup, 2502 }, 2503 { 2504 .vendor = PCI_VENDOR_ID_COMMTECH, 2505 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE, 2506 .subvendor = PCI_ANY_ID, 2507 .subdevice = PCI_ANY_ID, 2508 .setup = pci_xr17v35x_setup, 2509 }, 2510 { 2511 .vendor = PCI_VENDOR_ID_COMMTECH, 2512 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE, 2513 .subvendor = PCI_ANY_ID, 2514 .subdevice = PCI_ANY_ID, 2515 .setup = pci_xr17v35x_setup, 2516 }, 2517 /* 2518 * Broadcom TruManage (NetXtreme) 2519 */ 2520 { 2521 .vendor = PCI_VENDOR_ID_BROADCOM, 2522 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2523 .subvendor = PCI_ANY_ID, 2524 .subdevice = PCI_ANY_ID, 2525 .setup = pci_brcm_trumanage_setup, 2526 }, 2527 { 2528 .vendor = 0x1c29, 2529 .device = 0x1104, 2530 .subvendor = PCI_ANY_ID, 2531 .subdevice = PCI_ANY_ID, 2532 .setup = pci_fintek_setup, 2533 }, 2534 { 2535 .vendor = 0x1c29, 2536 .device = 0x1108, 2537 .subvendor = PCI_ANY_ID, 2538 .subdevice = PCI_ANY_ID, 2539 .setup = pci_fintek_setup, 2540 }, 2541 { 2542 .vendor = 0x1c29, 2543 .device = 0x1112, 2544 .subvendor = PCI_ANY_ID, 2545 .subdevice = PCI_ANY_ID, 2546 .setup = pci_fintek_setup, 2547 }, 2548 2549 /* 2550 * Default "match everything" terminator entry 2551 */ 2552 { 2553 .vendor = PCI_ANY_ID, 2554 .device = PCI_ANY_ID, 2555 .subvendor = PCI_ANY_ID, 2556 .subdevice = PCI_ANY_ID, 2557 .setup = pci_default_setup, 2558 } 2559 }; 2560 2561 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2562 { 2563 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2564 } 2565 2566 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2567 { 2568 struct pci_serial_quirk *quirk; 2569 2570 for (quirk = pci_serial_quirks; ; quirk++) 2571 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2572 quirk_id_matches(quirk->device, dev->device) && 2573 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2574 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2575 break; 2576 return quirk; 2577 } 2578 2579 static inline int get_pci_irq(struct pci_dev *dev, 2580 const struct pciserial_board *board) 2581 { 2582 if (board->flags & FL_NOIRQ) 2583 return 0; 2584 else 2585 return dev->irq; 2586 } 2587 2588 /* 2589 * This is the configuration table for all of the PCI serial boards 2590 * which we support. It is directly indexed by the pci_board_num_t enum 2591 * value, which is encoded in the pci_device_id PCI probe table's 2592 * driver_data member. 2593 * 2594 * The makeup of these names are: 2595 * pbn_bn{_bt}_n_baud{_offsetinhex} 2596 * 2597 * bn = PCI BAR number 2598 * bt = Index using PCI BARs 2599 * n = number of serial ports 2600 * baud = baud rate 2601 * offsetinhex = offset for each sequential port (in hex) 2602 * 2603 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2604 * 2605 * Please note: in theory if n = 1, _bt infix should make no difference. 2606 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2607 */ 2608 enum pci_board_num_t { 2609 pbn_default = 0, 2610 2611 pbn_b0_1_115200, 2612 pbn_b0_2_115200, 2613 pbn_b0_4_115200, 2614 pbn_b0_5_115200, 2615 pbn_b0_8_115200, 2616 2617 pbn_b0_1_921600, 2618 pbn_b0_2_921600, 2619 pbn_b0_4_921600, 2620 2621 pbn_b0_2_1130000, 2622 2623 pbn_b0_4_1152000, 2624 2625 pbn_b0_2_1152000_200, 2626 pbn_b0_4_1152000_200, 2627 pbn_b0_8_1152000_200, 2628 2629 pbn_b0_2_1843200, 2630 pbn_b0_4_1843200, 2631 2632 pbn_b0_2_1843200_200, 2633 pbn_b0_4_1843200_200, 2634 pbn_b0_8_1843200_200, 2635 2636 pbn_b0_1_4000000, 2637 2638 pbn_b0_bt_1_115200, 2639 pbn_b0_bt_2_115200, 2640 pbn_b0_bt_4_115200, 2641 pbn_b0_bt_8_115200, 2642 2643 pbn_b0_bt_1_460800, 2644 pbn_b0_bt_2_460800, 2645 pbn_b0_bt_4_460800, 2646 2647 pbn_b0_bt_1_921600, 2648 pbn_b0_bt_2_921600, 2649 pbn_b0_bt_4_921600, 2650 pbn_b0_bt_8_921600, 2651 2652 pbn_b1_1_115200, 2653 pbn_b1_2_115200, 2654 pbn_b1_4_115200, 2655 pbn_b1_8_115200, 2656 pbn_b1_16_115200, 2657 2658 pbn_b1_1_921600, 2659 pbn_b1_2_921600, 2660 pbn_b1_4_921600, 2661 pbn_b1_8_921600, 2662 2663 pbn_b1_2_1250000, 2664 2665 pbn_b1_bt_1_115200, 2666 pbn_b1_bt_2_115200, 2667 pbn_b1_bt_4_115200, 2668 2669 pbn_b1_bt_2_921600, 2670 2671 pbn_b1_1_1382400, 2672 pbn_b1_2_1382400, 2673 pbn_b1_4_1382400, 2674 pbn_b1_8_1382400, 2675 2676 pbn_b2_1_115200, 2677 pbn_b2_2_115200, 2678 pbn_b2_4_115200, 2679 pbn_b2_8_115200, 2680 2681 pbn_b2_1_460800, 2682 pbn_b2_4_460800, 2683 pbn_b2_8_460800, 2684 pbn_b2_16_460800, 2685 2686 pbn_b2_1_921600, 2687 pbn_b2_4_921600, 2688 pbn_b2_8_921600, 2689 2690 pbn_b2_8_1152000, 2691 2692 pbn_b2_bt_1_115200, 2693 pbn_b2_bt_2_115200, 2694 pbn_b2_bt_4_115200, 2695 2696 pbn_b2_bt_2_921600, 2697 pbn_b2_bt_4_921600, 2698 2699 pbn_b3_2_115200, 2700 pbn_b3_4_115200, 2701 pbn_b3_8_115200, 2702 2703 pbn_b4_bt_2_921600, 2704 pbn_b4_bt_4_921600, 2705 pbn_b4_bt_8_921600, 2706 2707 /* 2708 * Board-specific versions. 2709 */ 2710 pbn_panacom, 2711 pbn_panacom2, 2712 pbn_panacom4, 2713 pbn_plx_romulus, 2714 pbn_oxsemi, 2715 pbn_oxsemi_1_4000000, 2716 pbn_oxsemi_2_4000000, 2717 pbn_oxsemi_4_4000000, 2718 pbn_oxsemi_8_4000000, 2719 pbn_intel_i960, 2720 pbn_sgi_ioc3, 2721 pbn_computone_4, 2722 pbn_computone_6, 2723 pbn_computone_8, 2724 pbn_sbsxrsio, 2725 pbn_exar_XR17C152, 2726 pbn_exar_XR17C154, 2727 pbn_exar_XR17C158, 2728 pbn_exar_XR17V352, 2729 pbn_exar_XR17V354, 2730 pbn_exar_XR17V358, 2731 pbn_exar_ibm_saturn, 2732 pbn_pasemi_1682M, 2733 pbn_ni8430_2, 2734 pbn_ni8430_4, 2735 pbn_ni8430_8, 2736 pbn_ni8430_16, 2737 pbn_ADDIDATA_PCIe_1_3906250, 2738 pbn_ADDIDATA_PCIe_2_3906250, 2739 pbn_ADDIDATA_PCIe_4_3906250, 2740 pbn_ADDIDATA_PCIe_8_3906250, 2741 pbn_ce4100_1_115200, 2742 pbn_byt, 2743 pbn_omegapci, 2744 pbn_NETMOS9900_2s_115200, 2745 pbn_brcm_trumanage, 2746 pbn_fintek_4, 2747 pbn_fintek_8, 2748 pbn_fintek_12, 2749 }; 2750 2751 /* 2752 * uart_offset - the space between channels 2753 * reg_shift - describes how the UART registers are mapped 2754 * to PCI memory by the card. 2755 * For example IER register on SBS, Inc. PMC-OctPro is located at 2756 * offset 0x10 from the UART base, while UART_IER is defined as 1 2757 * in include/linux/serial_reg.h, 2758 * see first lines of serial_in() and serial_out() in 8250.c 2759 */ 2760 2761 static struct pciserial_board pci_boards[] = { 2762 [pbn_default] = { 2763 .flags = FL_BASE0, 2764 .num_ports = 1, 2765 .base_baud = 115200, 2766 .uart_offset = 8, 2767 }, 2768 [pbn_b0_1_115200] = { 2769 .flags = FL_BASE0, 2770 .num_ports = 1, 2771 .base_baud = 115200, 2772 .uart_offset = 8, 2773 }, 2774 [pbn_b0_2_115200] = { 2775 .flags = FL_BASE0, 2776 .num_ports = 2, 2777 .base_baud = 115200, 2778 .uart_offset = 8, 2779 }, 2780 [pbn_b0_4_115200] = { 2781 .flags = FL_BASE0, 2782 .num_ports = 4, 2783 .base_baud = 115200, 2784 .uart_offset = 8, 2785 }, 2786 [pbn_b0_5_115200] = { 2787 .flags = FL_BASE0, 2788 .num_ports = 5, 2789 .base_baud = 115200, 2790 .uart_offset = 8, 2791 }, 2792 [pbn_b0_8_115200] = { 2793 .flags = FL_BASE0, 2794 .num_ports = 8, 2795 .base_baud = 115200, 2796 .uart_offset = 8, 2797 }, 2798 [pbn_b0_1_921600] = { 2799 .flags = FL_BASE0, 2800 .num_ports = 1, 2801 .base_baud = 921600, 2802 .uart_offset = 8, 2803 }, 2804 [pbn_b0_2_921600] = { 2805 .flags = FL_BASE0, 2806 .num_ports = 2, 2807 .base_baud = 921600, 2808 .uart_offset = 8, 2809 }, 2810 [pbn_b0_4_921600] = { 2811 .flags = FL_BASE0, 2812 .num_ports = 4, 2813 .base_baud = 921600, 2814 .uart_offset = 8, 2815 }, 2816 2817 [pbn_b0_2_1130000] = { 2818 .flags = FL_BASE0, 2819 .num_ports = 2, 2820 .base_baud = 1130000, 2821 .uart_offset = 8, 2822 }, 2823 2824 [pbn_b0_4_1152000] = { 2825 .flags = FL_BASE0, 2826 .num_ports = 4, 2827 .base_baud = 1152000, 2828 .uart_offset = 8, 2829 }, 2830 2831 [pbn_b0_2_1152000_200] = { 2832 .flags = FL_BASE0, 2833 .num_ports = 2, 2834 .base_baud = 1152000, 2835 .uart_offset = 0x200, 2836 }, 2837 2838 [pbn_b0_4_1152000_200] = { 2839 .flags = FL_BASE0, 2840 .num_ports = 4, 2841 .base_baud = 1152000, 2842 .uart_offset = 0x200, 2843 }, 2844 2845 [pbn_b0_8_1152000_200] = { 2846 .flags = FL_BASE0, 2847 .num_ports = 8, 2848 .base_baud = 1152000, 2849 .uart_offset = 0x200, 2850 }, 2851 2852 [pbn_b0_2_1843200] = { 2853 .flags = FL_BASE0, 2854 .num_ports = 2, 2855 .base_baud = 1843200, 2856 .uart_offset = 8, 2857 }, 2858 [pbn_b0_4_1843200] = { 2859 .flags = FL_BASE0, 2860 .num_ports = 4, 2861 .base_baud = 1843200, 2862 .uart_offset = 8, 2863 }, 2864 2865 [pbn_b0_2_1843200_200] = { 2866 .flags = FL_BASE0, 2867 .num_ports = 2, 2868 .base_baud = 1843200, 2869 .uart_offset = 0x200, 2870 }, 2871 [pbn_b0_4_1843200_200] = { 2872 .flags = FL_BASE0, 2873 .num_ports = 4, 2874 .base_baud = 1843200, 2875 .uart_offset = 0x200, 2876 }, 2877 [pbn_b0_8_1843200_200] = { 2878 .flags = FL_BASE0, 2879 .num_ports = 8, 2880 .base_baud = 1843200, 2881 .uart_offset = 0x200, 2882 }, 2883 [pbn_b0_1_4000000] = { 2884 .flags = FL_BASE0, 2885 .num_ports = 1, 2886 .base_baud = 4000000, 2887 .uart_offset = 8, 2888 }, 2889 2890 [pbn_b0_bt_1_115200] = { 2891 .flags = FL_BASE0|FL_BASE_BARS, 2892 .num_ports = 1, 2893 .base_baud = 115200, 2894 .uart_offset = 8, 2895 }, 2896 [pbn_b0_bt_2_115200] = { 2897 .flags = FL_BASE0|FL_BASE_BARS, 2898 .num_ports = 2, 2899 .base_baud = 115200, 2900 .uart_offset = 8, 2901 }, 2902 [pbn_b0_bt_4_115200] = { 2903 .flags = FL_BASE0|FL_BASE_BARS, 2904 .num_ports = 4, 2905 .base_baud = 115200, 2906 .uart_offset = 8, 2907 }, 2908 [pbn_b0_bt_8_115200] = { 2909 .flags = FL_BASE0|FL_BASE_BARS, 2910 .num_ports = 8, 2911 .base_baud = 115200, 2912 .uart_offset = 8, 2913 }, 2914 2915 [pbn_b0_bt_1_460800] = { 2916 .flags = FL_BASE0|FL_BASE_BARS, 2917 .num_ports = 1, 2918 .base_baud = 460800, 2919 .uart_offset = 8, 2920 }, 2921 [pbn_b0_bt_2_460800] = { 2922 .flags = FL_BASE0|FL_BASE_BARS, 2923 .num_ports = 2, 2924 .base_baud = 460800, 2925 .uart_offset = 8, 2926 }, 2927 [pbn_b0_bt_4_460800] = { 2928 .flags = FL_BASE0|FL_BASE_BARS, 2929 .num_ports = 4, 2930 .base_baud = 460800, 2931 .uart_offset = 8, 2932 }, 2933 2934 [pbn_b0_bt_1_921600] = { 2935 .flags = FL_BASE0|FL_BASE_BARS, 2936 .num_ports = 1, 2937 .base_baud = 921600, 2938 .uart_offset = 8, 2939 }, 2940 [pbn_b0_bt_2_921600] = { 2941 .flags = FL_BASE0|FL_BASE_BARS, 2942 .num_ports = 2, 2943 .base_baud = 921600, 2944 .uart_offset = 8, 2945 }, 2946 [pbn_b0_bt_4_921600] = { 2947 .flags = FL_BASE0|FL_BASE_BARS, 2948 .num_ports = 4, 2949 .base_baud = 921600, 2950 .uart_offset = 8, 2951 }, 2952 [pbn_b0_bt_8_921600] = { 2953 .flags = FL_BASE0|FL_BASE_BARS, 2954 .num_ports = 8, 2955 .base_baud = 921600, 2956 .uart_offset = 8, 2957 }, 2958 2959 [pbn_b1_1_115200] = { 2960 .flags = FL_BASE1, 2961 .num_ports = 1, 2962 .base_baud = 115200, 2963 .uart_offset = 8, 2964 }, 2965 [pbn_b1_2_115200] = { 2966 .flags = FL_BASE1, 2967 .num_ports = 2, 2968 .base_baud = 115200, 2969 .uart_offset = 8, 2970 }, 2971 [pbn_b1_4_115200] = { 2972 .flags = FL_BASE1, 2973 .num_ports = 4, 2974 .base_baud = 115200, 2975 .uart_offset = 8, 2976 }, 2977 [pbn_b1_8_115200] = { 2978 .flags = FL_BASE1, 2979 .num_ports = 8, 2980 .base_baud = 115200, 2981 .uart_offset = 8, 2982 }, 2983 [pbn_b1_16_115200] = { 2984 .flags = FL_BASE1, 2985 .num_ports = 16, 2986 .base_baud = 115200, 2987 .uart_offset = 8, 2988 }, 2989 2990 [pbn_b1_1_921600] = { 2991 .flags = FL_BASE1, 2992 .num_ports = 1, 2993 .base_baud = 921600, 2994 .uart_offset = 8, 2995 }, 2996 [pbn_b1_2_921600] = { 2997 .flags = FL_BASE1, 2998 .num_ports = 2, 2999 .base_baud = 921600, 3000 .uart_offset = 8, 3001 }, 3002 [pbn_b1_4_921600] = { 3003 .flags = FL_BASE1, 3004 .num_ports = 4, 3005 .base_baud = 921600, 3006 .uart_offset = 8, 3007 }, 3008 [pbn_b1_8_921600] = { 3009 .flags = FL_BASE1, 3010 .num_ports = 8, 3011 .base_baud = 921600, 3012 .uart_offset = 8, 3013 }, 3014 [pbn_b1_2_1250000] = { 3015 .flags = FL_BASE1, 3016 .num_ports = 2, 3017 .base_baud = 1250000, 3018 .uart_offset = 8, 3019 }, 3020 3021 [pbn_b1_bt_1_115200] = { 3022 .flags = FL_BASE1|FL_BASE_BARS, 3023 .num_ports = 1, 3024 .base_baud = 115200, 3025 .uart_offset = 8, 3026 }, 3027 [pbn_b1_bt_2_115200] = { 3028 .flags = FL_BASE1|FL_BASE_BARS, 3029 .num_ports = 2, 3030 .base_baud = 115200, 3031 .uart_offset = 8, 3032 }, 3033 [pbn_b1_bt_4_115200] = { 3034 .flags = FL_BASE1|FL_BASE_BARS, 3035 .num_ports = 4, 3036 .base_baud = 115200, 3037 .uart_offset = 8, 3038 }, 3039 3040 [pbn_b1_bt_2_921600] = { 3041 .flags = FL_BASE1|FL_BASE_BARS, 3042 .num_ports = 2, 3043 .base_baud = 921600, 3044 .uart_offset = 8, 3045 }, 3046 3047 [pbn_b1_1_1382400] = { 3048 .flags = FL_BASE1, 3049 .num_ports = 1, 3050 .base_baud = 1382400, 3051 .uart_offset = 8, 3052 }, 3053 [pbn_b1_2_1382400] = { 3054 .flags = FL_BASE1, 3055 .num_ports = 2, 3056 .base_baud = 1382400, 3057 .uart_offset = 8, 3058 }, 3059 [pbn_b1_4_1382400] = { 3060 .flags = FL_BASE1, 3061 .num_ports = 4, 3062 .base_baud = 1382400, 3063 .uart_offset = 8, 3064 }, 3065 [pbn_b1_8_1382400] = { 3066 .flags = FL_BASE1, 3067 .num_ports = 8, 3068 .base_baud = 1382400, 3069 .uart_offset = 8, 3070 }, 3071 3072 [pbn_b2_1_115200] = { 3073 .flags = FL_BASE2, 3074 .num_ports = 1, 3075 .base_baud = 115200, 3076 .uart_offset = 8, 3077 }, 3078 [pbn_b2_2_115200] = { 3079 .flags = FL_BASE2, 3080 .num_ports = 2, 3081 .base_baud = 115200, 3082 .uart_offset = 8, 3083 }, 3084 [pbn_b2_4_115200] = { 3085 .flags = FL_BASE2, 3086 .num_ports = 4, 3087 .base_baud = 115200, 3088 .uart_offset = 8, 3089 }, 3090 [pbn_b2_8_115200] = { 3091 .flags = FL_BASE2, 3092 .num_ports = 8, 3093 .base_baud = 115200, 3094 .uart_offset = 8, 3095 }, 3096 3097 [pbn_b2_1_460800] = { 3098 .flags = FL_BASE2, 3099 .num_ports = 1, 3100 .base_baud = 460800, 3101 .uart_offset = 8, 3102 }, 3103 [pbn_b2_4_460800] = { 3104 .flags = FL_BASE2, 3105 .num_ports = 4, 3106 .base_baud = 460800, 3107 .uart_offset = 8, 3108 }, 3109 [pbn_b2_8_460800] = { 3110 .flags = FL_BASE2, 3111 .num_ports = 8, 3112 .base_baud = 460800, 3113 .uart_offset = 8, 3114 }, 3115 [pbn_b2_16_460800] = { 3116 .flags = FL_BASE2, 3117 .num_ports = 16, 3118 .base_baud = 460800, 3119 .uart_offset = 8, 3120 }, 3121 3122 [pbn_b2_1_921600] = { 3123 .flags = FL_BASE2, 3124 .num_ports = 1, 3125 .base_baud = 921600, 3126 .uart_offset = 8, 3127 }, 3128 [pbn_b2_4_921600] = { 3129 .flags = FL_BASE2, 3130 .num_ports = 4, 3131 .base_baud = 921600, 3132 .uart_offset = 8, 3133 }, 3134 [pbn_b2_8_921600] = { 3135 .flags = FL_BASE2, 3136 .num_ports = 8, 3137 .base_baud = 921600, 3138 .uart_offset = 8, 3139 }, 3140 3141 [pbn_b2_8_1152000] = { 3142 .flags = FL_BASE2, 3143 .num_ports = 8, 3144 .base_baud = 1152000, 3145 .uart_offset = 8, 3146 }, 3147 3148 [pbn_b2_bt_1_115200] = { 3149 .flags = FL_BASE2|FL_BASE_BARS, 3150 .num_ports = 1, 3151 .base_baud = 115200, 3152 .uart_offset = 8, 3153 }, 3154 [pbn_b2_bt_2_115200] = { 3155 .flags = FL_BASE2|FL_BASE_BARS, 3156 .num_ports = 2, 3157 .base_baud = 115200, 3158 .uart_offset = 8, 3159 }, 3160 [pbn_b2_bt_4_115200] = { 3161 .flags = FL_BASE2|FL_BASE_BARS, 3162 .num_ports = 4, 3163 .base_baud = 115200, 3164 .uart_offset = 8, 3165 }, 3166 3167 [pbn_b2_bt_2_921600] = { 3168 .flags = FL_BASE2|FL_BASE_BARS, 3169 .num_ports = 2, 3170 .base_baud = 921600, 3171 .uart_offset = 8, 3172 }, 3173 [pbn_b2_bt_4_921600] = { 3174 .flags = FL_BASE2|FL_BASE_BARS, 3175 .num_ports = 4, 3176 .base_baud = 921600, 3177 .uart_offset = 8, 3178 }, 3179 3180 [pbn_b3_2_115200] = { 3181 .flags = FL_BASE3, 3182 .num_ports = 2, 3183 .base_baud = 115200, 3184 .uart_offset = 8, 3185 }, 3186 [pbn_b3_4_115200] = { 3187 .flags = FL_BASE3, 3188 .num_ports = 4, 3189 .base_baud = 115200, 3190 .uart_offset = 8, 3191 }, 3192 [pbn_b3_8_115200] = { 3193 .flags = FL_BASE3, 3194 .num_ports = 8, 3195 .base_baud = 115200, 3196 .uart_offset = 8, 3197 }, 3198 3199 [pbn_b4_bt_2_921600] = { 3200 .flags = FL_BASE4, 3201 .num_ports = 2, 3202 .base_baud = 921600, 3203 .uart_offset = 8, 3204 }, 3205 [pbn_b4_bt_4_921600] = { 3206 .flags = FL_BASE4, 3207 .num_ports = 4, 3208 .base_baud = 921600, 3209 .uart_offset = 8, 3210 }, 3211 [pbn_b4_bt_8_921600] = { 3212 .flags = FL_BASE4, 3213 .num_ports = 8, 3214 .base_baud = 921600, 3215 .uart_offset = 8, 3216 }, 3217 3218 /* 3219 * Entries following this are board-specific. 3220 */ 3221 3222 /* 3223 * Panacom - IOMEM 3224 */ 3225 [pbn_panacom] = { 3226 .flags = FL_BASE2, 3227 .num_ports = 2, 3228 .base_baud = 921600, 3229 .uart_offset = 0x400, 3230 .reg_shift = 7, 3231 }, 3232 [pbn_panacom2] = { 3233 .flags = FL_BASE2|FL_BASE_BARS, 3234 .num_ports = 2, 3235 .base_baud = 921600, 3236 .uart_offset = 0x400, 3237 .reg_shift = 7, 3238 }, 3239 [pbn_panacom4] = { 3240 .flags = FL_BASE2|FL_BASE_BARS, 3241 .num_ports = 4, 3242 .base_baud = 921600, 3243 .uart_offset = 0x400, 3244 .reg_shift = 7, 3245 }, 3246 3247 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3248 [pbn_plx_romulus] = { 3249 .flags = FL_BASE2, 3250 .num_ports = 4, 3251 .base_baud = 921600, 3252 .uart_offset = 8 << 2, 3253 .reg_shift = 2, 3254 .first_offset = 0x03, 3255 }, 3256 3257 /* 3258 * This board uses the size of PCI Base region 0 to 3259 * signal now many ports are available 3260 */ 3261 [pbn_oxsemi] = { 3262 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3263 .num_ports = 32, 3264 .base_baud = 115200, 3265 .uart_offset = 8, 3266 }, 3267 [pbn_oxsemi_1_4000000] = { 3268 .flags = FL_BASE0, 3269 .num_ports = 1, 3270 .base_baud = 4000000, 3271 .uart_offset = 0x200, 3272 .first_offset = 0x1000, 3273 }, 3274 [pbn_oxsemi_2_4000000] = { 3275 .flags = FL_BASE0, 3276 .num_ports = 2, 3277 .base_baud = 4000000, 3278 .uart_offset = 0x200, 3279 .first_offset = 0x1000, 3280 }, 3281 [pbn_oxsemi_4_4000000] = { 3282 .flags = FL_BASE0, 3283 .num_ports = 4, 3284 .base_baud = 4000000, 3285 .uart_offset = 0x200, 3286 .first_offset = 0x1000, 3287 }, 3288 [pbn_oxsemi_8_4000000] = { 3289 .flags = FL_BASE0, 3290 .num_ports = 8, 3291 .base_baud = 4000000, 3292 .uart_offset = 0x200, 3293 .first_offset = 0x1000, 3294 }, 3295 3296 3297 /* 3298 * EKF addition for i960 Boards form EKF with serial port. 3299 * Max 256 ports. 3300 */ 3301 [pbn_intel_i960] = { 3302 .flags = FL_BASE0, 3303 .num_ports = 32, 3304 .base_baud = 921600, 3305 .uart_offset = 8 << 2, 3306 .reg_shift = 2, 3307 .first_offset = 0x10000, 3308 }, 3309 [pbn_sgi_ioc3] = { 3310 .flags = FL_BASE0|FL_NOIRQ, 3311 .num_ports = 1, 3312 .base_baud = 458333, 3313 .uart_offset = 8, 3314 .reg_shift = 0, 3315 .first_offset = 0x20178, 3316 }, 3317 3318 /* 3319 * Computone - uses IOMEM. 3320 */ 3321 [pbn_computone_4] = { 3322 .flags = FL_BASE0, 3323 .num_ports = 4, 3324 .base_baud = 921600, 3325 .uart_offset = 0x40, 3326 .reg_shift = 2, 3327 .first_offset = 0x200, 3328 }, 3329 [pbn_computone_6] = { 3330 .flags = FL_BASE0, 3331 .num_ports = 6, 3332 .base_baud = 921600, 3333 .uart_offset = 0x40, 3334 .reg_shift = 2, 3335 .first_offset = 0x200, 3336 }, 3337 [pbn_computone_8] = { 3338 .flags = FL_BASE0, 3339 .num_ports = 8, 3340 .base_baud = 921600, 3341 .uart_offset = 0x40, 3342 .reg_shift = 2, 3343 .first_offset = 0x200, 3344 }, 3345 [pbn_sbsxrsio] = { 3346 .flags = FL_BASE0, 3347 .num_ports = 8, 3348 .base_baud = 460800, 3349 .uart_offset = 256, 3350 .reg_shift = 4, 3351 }, 3352 /* 3353 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 3354 * Only basic 16550A support. 3355 * XR17C15[24] are not tested, but they should work. 3356 */ 3357 [pbn_exar_XR17C152] = { 3358 .flags = FL_BASE0, 3359 .num_ports = 2, 3360 .base_baud = 921600, 3361 .uart_offset = 0x200, 3362 }, 3363 [pbn_exar_XR17C154] = { 3364 .flags = FL_BASE0, 3365 .num_ports = 4, 3366 .base_baud = 921600, 3367 .uart_offset = 0x200, 3368 }, 3369 [pbn_exar_XR17C158] = { 3370 .flags = FL_BASE0, 3371 .num_ports = 8, 3372 .base_baud = 921600, 3373 .uart_offset = 0x200, 3374 }, 3375 [pbn_exar_XR17V352] = { 3376 .flags = FL_BASE0, 3377 .num_ports = 2, 3378 .base_baud = 7812500, 3379 .uart_offset = 0x400, 3380 .reg_shift = 0, 3381 .first_offset = 0, 3382 }, 3383 [pbn_exar_XR17V354] = { 3384 .flags = FL_BASE0, 3385 .num_ports = 4, 3386 .base_baud = 7812500, 3387 .uart_offset = 0x400, 3388 .reg_shift = 0, 3389 .first_offset = 0, 3390 }, 3391 [pbn_exar_XR17V358] = { 3392 .flags = FL_BASE0, 3393 .num_ports = 8, 3394 .base_baud = 7812500, 3395 .uart_offset = 0x400, 3396 .reg_shift = 0, 3397 .first_offset = 0, 3398 }, 3399 [pbn_exar_ibm_saturn] = { 3400 .flags = FL_BASE0, 3401 .num_ports = 1, 3402 .base_baud = 921600, 3403 .uart_offset = 0x200, 3404 }, 3405 3406 /* 3407 * PA Semi PWRficient PA6T-1682M on-chip UART 3408 */ 3409 [pbn_pasemi_1682M] = { 3410 .flags = FL_BASE0, 3411 .num_ports = 1, 3412 .base_baud = 8333333, 3413 }, 3414 /* 3415 * National Instruments 843x 3416 */ 3417 [pbn_ni8430_16] = { 3418 .flags = FL_BASE0, 3419 .num_ports = 16, 3420 .base_baud = 3686400, 3421 .uart_offset = 0x10, 3422 .first_offset = 0x800, 3423 }, 3424 [pbn_ni8430_8] = { 3425 .flags = FL_BASE0, 3426 .num_ports = 8, 3427 .base_baud = 3686400, 3428 .uart_offset = 0x10, 3429 .first_offset = 0x800, 3430 }, 3431 [pbn_ni8430_4] = { 3432 .flags = FL_BASE0, 3433 .num_ports = 4, 3434 .base_baud = 3686400, 3435 .uart_offset = 0x10, 3436 .first_offset = 0x800, 3437 }, 3438 [pbn_ni8430_2] = { 3439 .flags = FL_BASE0, 3440 .num_ports = 2, 3441 .base_baud = 3686400, 3442 .uart_offset = 0x10, 3443 .first_offset = 0x800, 3444 }, 3445 /* 3446 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3447 */ 3448 [pbn_ADDIDATA_PCIe_1_3906250] = { 3449 .flags = FL_BASE0, 3450 .num_ports = 1, 3451 .base_baud = 3906250, 3452 .uart_offset = 0x200, 3453 .first_offset = 0x1000, 3454 }, 3455 [pbn_ADDIDATA_PCIe_2_3906250] = { 3456 .flags = FL_BASE0, 3457 .num_ports = 2, 3458 .base_baud = 3906250, 3459 .uart_offset = 0x200, 3460 .first_offset = 0x1000, 3461 }, 3462 [pbn_ADDIDATA_PCIe_4_3906250] = { 3463 .flags = FL_BASE0, 3464 .num_ports = 4, 3465 .base_baud = 3906250, 3466 .uart_offset = 0x200, 3467 .first_offset = 0x1000, 3468 }, 3469 [pbn_ADDIDATA_PCIe_8_3906250] = { 3470 .flags = FL_BASE0, 3471 .num_ports = 8, 3472 .base_baud = 3906250, 3473 .uart_offset = 0x200, 3474 .first_offset = 0x1000, 3475 }, 3476 [pbn_ce4100_1_115200] = { 3477 .flags = FL_BASE_BARS, 3478 .num_ports = 2, 3479 .base_baud = 921600, 3480 .reg_shift = 2, 3481 }, 3482 /* 3483 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on, 3484 * but is overridden by byt_set_termios. 3485 */ 3486 [pbn_byt] = { 3487 .flags = FL_BASE0, 3488 .num_ports = 1, 3489 .base_baud = 2764800, 3490 .uart_offset = 0x80, 3491 .reg_shift = 2, 3492 }, 3493 [pbn_omegapci] = { 3494 .flags = FL_BASE0, 3495 .num_ports = 8, 3496 .base_baud = 115200, 3497 .uart_offset = 0x200, 3498 }, 3499 [pbn_NETMOS9900_2s_115200] = { 3500 .flags = FL_BASE0, 3501 .num_ports = 2, 3502 .base_baud = 115200, 3503 }, 3504 [pbn_brcm_trumanage] = { 3505 .flags = FL_BASE0, 3506 .num_ports = 1, 3507 .reg_shift = 2, 3508 .base_baud = 115200, 3509 }, 3510 [pbn_fintek_4] = { 3511 .num_ports = 4, 3512 .uart_offset = 8, 3513 .base_baud = 115200, 3514 .first_offset = 0x40, 3515 }, 3516 [pbn_fintek_8] = { 3517 .num_ports = 8, 3518 .uart_offset = 8, 3519 .base_baud = 115200, 3520 .first_offset = 0x40, 3521 }, 3522 [pbn_fintek_12] = { 3523 .num_ports = 12, 3524 .uart_offset = 8, 3525 .base_baud = 115200, 3526 .first_offset = 0x40, 3527 }, 3528 }; 3529 3530 static const struct pci_device_id blacklist[] = { 3531 /* softmodems */ 3532 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3533 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3534 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3535 3536 /* multi-io cards handled by parport_serial */ 3537 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3538 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3539 }; 3540 3541 /* 3542 * Given a complete unknown PCI device, try to use some heuristics to 3543 * guess what the configuration might be, based on the pitiful PCI 3544 * serial specs. Returns 0 on success, 1 on failure. 3545 */ 3546 static int 3547 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3548 { 3549 const struct pci_device_id *bldev; 3550 int num_iomem, num_port, first_port = -1, i; 3551 3552 /* 3553 * If it is not a communications device or the programming 3554 * interface is greater than 6, give up. 3555 * 3556 * (Should we try to make guesses for multiport serial devices 3557 * later?) 3558 */ 3559 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3560 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3561 (dev->class & 0xff) > 6) 3562 return -ENODEV; 3563 3564 /* 3565 * Do not access blacklisted devices that are known not to 3566 * feature serial ports or are handled by other modules. 3567 */ 3568 for (bldev = blacklist; 3569 bldev < blacklist + ARRAY_SIZE(blacklist); 3570 bldev++) { 3571 if (dev->vendor == bldev->vendor && 3572 dev->device == bldev->device) 3573 return -ENODEV; 3574 } 3575 3576 num_iomem = num_port = 0; 3577 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3578 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3579 num_port++; 3580 if (first_port == -1) 3581 first_port = i; 3582 } 3583 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3584 num_iomem++; 3585 } 3586 3587 /* 3588 * If there is 1 or 0 iomem regions, and exactly one port, 3589 * use it. We guess the number of ports based on the IO 3590 * region size. 3591 */ 3592 if (num_iomem <= 1 && num_port == 1) { 3593 board->flags = first_port; 3594 board->num_ports = pci_resource_len(dev, first_port) / 8; 3595 return 0; 3596 } 3597 3598 /* 3599 * Now guess if we've got a board which indexes by BARs. 3600 * Each IO BAR should be 8 bytes, and they should follow 3601 * consecutively. 3602 */ 3603 first_port = -1; 3604 num_port = 0; 3605 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3606 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3607 pci_resource_len(dev, i) == 8 && 3608 (first_port == -1 || (first_port + num_port) == i)) { 3609 num_port++; 3610 if (first_port == -1) 3611 first_port = i; 3612 } 3613 } 3614 3615 if (num_port > 1) { 3616 board->flags = first_port | FL_BASE_BARS; 3617 board->num_ports = num_port; 3618 return 0; 3619 } 3620 3621 return -ENODEV; 3622 } 3623 3624 static inline int 3625 serial_pci_matches(const struct pciserial_board *board, 3626 const struct pciserial_board *guessed) 3627 { 3628 return 3629 board->num_ports == guessed->num_ports && 3630 board->base_baud == guessed->base_baud && 3631 board->uart_offset == guessed->uart_offset && 3632 board->reg_shift == guessed->reg_shift && 3633 board->first_offset == guessed->first_offset; 3634 } 3635 3636 struct serial_private * 3637 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3638 { 3639 struct uart_8250_port uart; 3640 struct serial_private *priv; 3641 struct pci_serial_quirk *quirk; 3642 int rc, nr_ports, i; 3643 3644 nr_ports = board->num_ports; 3645 3646 /* 3647 * Find an init and setup quirks. 3648 */ 3649 quirk = find_quirk(dev); 3650 3651 /* 3652 * Run the new-style initialization function. 3653 * The initialization function returns: 3654 * <0 - error 3655 * 0 - use board->num_ports 3656 * >0 - number of ports 3657 */ 3658 if (quirk->init) { 3659 rc = quirk->init(dev); 3660 if (rc < 0) { 3661 priv = ERR_PTR(rc); 3662 goto err_out; 3663 } 3664 if (rc) 3665 nr_ports = rc; 3666 } 3667 3668 priv = kzalloc(sizeof(struct serial_private) + 3669 sizeof(unsigned int) * nr_ports, 3670 GFP_KERNEL); 3671 if (!priv) { 3672 priv = ERR_PTR(-ENOMEM); 3673 goto err_deinit; 3674 } 3675 3676 priv->dev = dev; 3677 priv->quirk = quirk; 3678 3679 memset(&uart, 0, sizeof(uart)); 3680 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3681 uart.port.uartclk = board->base_baud * 16; 3682 uart.port.irq = get_pci_irq(dev, board); 3683 uart.port.dev = &dev->dev; 3684 3685 for (i = 0; i < nr_ports; i++) { 3686 if (quirk->setup(priv, board, &uart, i)) 3687 break; 3688 3689 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3690 uart.port.iobase, uart.port.irq, uart.port.iotype); 3691 3692 priv->line[i] = serial8250_register_8250_port(&uart); 3693 if (priv->line[i] < 0) { 3694 dev_err(&dev->dev, 3695 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3696 uart.port.iobase, uart.port.irq, 3697 uart.port.iotype, priv->line[i]); 3698 break; 3699 } 3700 } 3701 priv->nr = i; 3702 return priv; 3703 3704 err_deinit: 3705 if (quirk->exit) 3706 quirk->exit(dev); 3707 err_out: 3708 return priv; 3709 } 3710 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3711 3712 void pciserial_remove_ports(struct serial_private *priv) 3713 { 3714 struct pci_serial_quirk *quirk; 3715 int i; 3716 3717 for (i = 0; i < priv->nr; i++) 3718 serial8250_unregister_port(priv->line[i]); 3719 3720 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { 3721 if (priv->remapped_bar[i]) 3722 iounmap(priv->remapped_bar[i]); 3723 priv->remapped_bar[i] = NULL; 3724 } 3725 3726 /* 3727 * Find the exit quirks. 3728 */ 3729 quirk = find_quirk(priv->dev); 3730 if (quirk->exit) 3731 quirk->exit(priv->dev); 3732 3733 kfree(priv); 3734 } 3735 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 3736 3737 void pciserial_suspend_ports(struct serial_private *priv) 3738 { 3739 int i; 3740 3741 for (i = 0; i < priv->nr; i++) 3742 if (priv->line[i] >= 0) 3743 serial8250_suspend_port(priv->line[i]); 3744 3745 /* 3746 * Ensure that every init quirk is properly torn down 3747 */ 3748 if (priv->quirk->exit) 3749 priv->quirk->exit(priv->dev); 3750 } 3751 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 3752 3753 void pciserial_resume_ports(struct serial_private *priv) 3754 { 3755 int i; 3756 3757 /* 3758 * Ensure that the board is correctly configured. 3759 */ 3760 if (priv->quirk->init) 3761 priv->quirk->init(priv->dev); 3762 3763 for (i = 0; i < priv->nr; i++) 3764 if (priv->line[i] >= 0) 3765 serial8250_resume_port(priv->line[i]); 3766 } 3767 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 3768 3769 /* 3770 * Probe one serial board. Unfortunately, there is no rhyme nor reason 3771 * to the arrangement of serial ports on a PCI card. 3772 */ 3773 static int 3774 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 3775 { 3776 struct pci_serial_quirk *quirk; 3777 struct serial_private *priv; 3778 const struct pciserial_board *board; 3779 struct pciserial_board tmp; 3780 int rc; 3781 3782 quirk = find_quirk(dev); 3783 if (quirk->probe) { 3784 rc = quirk->probe(dev); 3785 if (rc) 3786 return rc; 3787 } 3788 3789 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 3790 dev_err(&dev->dev, "invalid driver_data: %ld\n", 3791 ent->driver_data); 3792 return -EINVAL; 3793 } 3794 3795 board = &pci_boards[ent->driver_data]; 3796 3797 rc = pci_enable_device(dev); 3798 pci_save_state(dev); 3799 if (rc) 3800 return rc; 3801 3802 if (ent->driver_data == pbn_default) { 3803 /* 3804 * Use a copy of the pci_board entry for this; 3805 * avoid changing entries in the table. 3806 */ 3807 memcpy(&tmp, board, sizeof(struct pciserial_board)); 3808 board = &tmp; 3809 3810 /* 3811 * We matched one of our class entries. Try to 3812 * determine the parameters of this board. 3813 */ 3814 rc = serial_pci_guess_board(dev, &tmp); 3815 if (rc) 3816 goto disable; 3817 } else { 3818 /* 3819 * We matched an explicit entry. If we are able to 3820 * detect this boards settings with our heuristic, 3821 * then we no longer need this entry. 3822 */ 3823 memcpy(&tmp, &pci_boards[pbn_default], 3824 sizeof(struct pciserial_board)); 3825 rc = serial_pci_guess_board(dev, &tmp); 3826 if (rc == 0 && serial_pci_matches(board, &tmp)) 3827 moan_device("Redundant entry in serial pci_table.", 3828 dev); 3829 } 3830 3831 priv = pciserial_init_ports(dev, board); 3832 if (!IS_ERR(priv)) { 3833 pci_set_drvdata(dev, priv); 3834 return 0; 3835 } 3836 3837 rc = PTR_ERR(priv); 3838 3839 disable: 3840 pci_disable_device(dev); 3841 return rc; 3842 } 3843 3844 static void pciserial_remove_one(struct pci_dev *dev) 3845 { 3846 struct serial_private *priv = pci_get_drvdata(dev); 3847 3848 pciserial_remove_ports(priv); 3849 3850 pci_disable_device(dev); 3851 } 3852 3853 #ifdef CONFIG_PM 3854 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state) 3855 { 3856 struct serial_private *priv = pci_get_drvdata(dev); 3857 3858 if (priv) 3859 pciserial_suspend_ports(priv); 3860 3861 pci_save_state(dev); 3862 pci_set_power_state(dev, pci_choose_state(dev, state)); 3863 return 0; 3864 } 3865 3866 static int pciserial_resume_one(struct pci_dev *dev) 3867 { 3868 int err; 3869 struct serial_private *priv = pci_get_drvdata(dev); 3870 3871 pci_set_power_state(dev, PCI_D0); 3872 pci_restore_state(dev); 3873 3874 if (priv) { 3875 /* 3876 * The device may have been disabled. Re-enable it. 3877 */ 3878 err = pci_enable_device(dev); 3879 /* FIXME: We cannot simply error out here */ 3880 if (err) 3881 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n"); 3882 pciserial_resume_ports(priv); 3883 } 3884 return 0; 3885 } 3886 #endif 3887 3888 static struct pci_device_id serial_pci_tbl[] = { 3889 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 3890 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 3891 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 3892 pbn_b2_8_921600 }, 3893 /* Advantech also use 0x3618 and 0xf618 */ 3894 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 3895 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3896 pbn_b0_4_921600 }, 3897 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 3898 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 3899 pbn_b0_4_921600 }, 3900 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3901 PCI_SUBVENDOR_ID_CONNECT_TECH, 3902 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3903 pbn_b1_8_1382400 }, 3904 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3905 PCI_SUBVENDOR_ID_CONNECT_TECH, 3906 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3907 pbn_b1_4_1382400 }, 3908 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 3909 PCI_SUBVENDOR_ID_CONNECT_TECH, 3910 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3911 pbn_b1_2_1382400 }, 3912 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3913 PCI_SUBVENDOR_ID_CONNECT_TECH, 3914 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 3915 pbn_b1_8_1382400 }, 3916 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3917 PCI_SUBVENDOR_ID_CONNECT_TECH, 3918 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 3919 pbn_b1_4_1382400 }, 3920 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3921 PCI_SUBVENDOR_ID_CONNECT_TECH, 3922 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 3923 pbn_b1_2_1382400 }, 3924 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3925 PCI_SUBVENDOR_ID_CONNECT_TECH, 3926 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 3927 pbn_b1_8_921600 }, 3928 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3929 PCI_SUBVENDOR_ID_CONNECT_TECH, 3930 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 3931 pbn_b1_8_921600 }, 3932 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3933 PCI_SUBVENDOR_ID_CONNECT_TECH, 3934 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 3935 pbn_b1_4_921600 }, 3936 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3937 PCI_SUBVENDOR_ID_CONNECT_TECH, 3938 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 3939 pbn_b1_4_921600 }, 3940 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3941 PCI_SUBVENDOR_ID_CONNECT_TECH, 3942 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 3943 pbn_b1_2_921600 }, 3944 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3945 PCI_SUBVENDOR_ID_CONNECT_TECH, 3946 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 3947 pbn_b1_8_921600 }, 3948 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3949 PCI_SUBVENDOR_ID_CONNECT_TECH, 3950 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 3951 pbn_b1_8_921600 }, 3952 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3953 PCI_SUBVENDOR_ID_CONNECT_TECH, 3954 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 3955 pbn_b1_4_921600 }, 3956 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 3957 PCI_SUBVENDOR_ID_CONNECT_TECH, 3958 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 3959 pbn_b1_2_1250000 }, 3960 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3961 PCI_SUBVENDOR_ID_CONNECT_TECH, 3962 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 3963 pbn_b0_2_1843200 }, 3964 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3965 PCI_SUBVENDOR_ID_CONNECT_TECH, 3966 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 3967 pbn_b0_4_1843200 }, 3968 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 3969 PCI_VENDOR_ID_AFAVLAB, 3970 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 3971 pbn_b0_4_1152000 }, 3972 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3973 PCI_SUBVENDOR_ID_CONNECT_TECH, 3974 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0, 3975 pbn_b0_2_1843200_200 }, 3976 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3977 PCI_SUBVENDOR_ID_CONNECT_TECH, 3978 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0, 3979 pbn_b0_4_1843200_200 }, 3980 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3981 PCI_SUBVENDOR_ID_CONNECT_TECH, 3982 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0, 3983 pbn_b0_8_1843200_200 }, 3984 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3985 PCI_SUBVENDOR_ID_CONNECT_TECH, 3986 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0, 3987 pbn_b0_2_1843200_200 }, 3988 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 3989 PCI_SUBVENDOR_ID_CONNECT_TECH, 3990 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0, 3991 pbn_b0_4_1843200_200 }, 3992 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 3993 PCI_SUBVENDOR_ID_CONNECT_TECH, 3994 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0, 3995 pbn_b0_8_1843200_200 }, 3996 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 3997 PCI_SUBVENDOR_ID_CONNECT_TECH, 3998 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0, 3999 pbn_b0_2_1843200_200 }, 4000 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4001 PCI_SUBVENDOR_ID_CONNECT_TECH, 4002 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0, 4003 pbn_b0_4_1843200_200 }, 4004 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4005 PCI_SUBVENDOR_ID_CONNECT_TECH, 4006 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0, 4007 pbn_b0_8_1843200_200 }, 4008 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4009 PCI_SUBVENDOR_ID_CONNECT_TECH, 4010 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0, 4011 pbn_b0_2_1843200_200 }, 4012 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4013 PCI_SUBVENDOR_ID_CONNECT_TECH, 4014 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0, 4015 pbn_b0_4_1843200_200 }, 4016 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4017 PCI_SUBVENDOR_ID_CONNECT_TECH, 4018 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0, 4019 pbn_b0_8_1843200_200 }, 4020 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4021 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT, 4022 0, 0, pbn_exar_ibm_saturn }, 4023 4024 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4025 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4026 pbn_b2_bt_1_115200 }, 4027 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4028 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4029 pbn_b2_bt_2_115200 }, 4030 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4031 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4032 pbn_b2_bt_4_115200 }, 4033 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4034 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4035 pbn_b2_bt_2_115200 }, 4036 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4037 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4038 pbn_b2_bt_4_115200 }, 4039 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4040 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4041 pbn_b2_8_115200 }, 4042 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4043 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4044 pbn_b2_8_460800 }, 4045 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4046 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4047 pbn_b2_8_115200 }, 4048 4049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4050 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4051 pbn_b2_bt_2_115200 }, 4052 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4053 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4054 pbn_b2_bt_2_921600 }, 4055 /* 4056 * VScom SPCOM800, from sl@s.pl 4057 */ 4058 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4059 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4060 pbn_b2_8_921600 }, 4061 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4062 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4063 pbn_b2_4_921600 }, 4064 /* Unknown card - subdevice 0x1584 */ 4065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4066 PCI_VENDOR_ID_PLX, 4067 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4068 pbn_b2_4_115200 }, 4069 /* Unknown card - subdevice 0x1588 */ 4070 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4071 PCI_VENDOR_ID_PLX, 4072 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4073 pbn_b2_8_115200 }, 4074 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4075 PCI_SUBVENDOR_ID_KEYSPAN, 4076 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4077 pbn_panacom }, 4078 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4079 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4080 pbn_panacom4 }, 4081 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4083 pbn_panacom2 }, 4084 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4085 PCI_VENDOR_ID_ESDGMBH, 4086 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4087 pbn_b2_4_115200 }, 4088 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4089 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4090 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4091 pbn_b2_4_460800 }, 4092 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4093 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4094 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4095 pbn_b2_8_460800 }, 4096 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4097 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4098 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4099 pbn_b2_16_460800 }, 4100 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4101 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4102 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4103 pbn_b2_16_460800 }, 4104 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4105 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4106 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4107 pbn_b2_4_460800 }, 4108 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4109 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4110 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4111 pbn_b2_8_460800 }, 4112 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4113 PCI_SUBVENDOR_ID_EXSYS, 4114 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4115 pbn_b2_4_115200 }, 4116 /* 4117 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4118 * (Exoray@isys.ca) 4119 */ 4120 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4121 0x10b5, 0x106a, 0, 0, 4122 pbn_plx_romulus }, 4123 /* 4124 * Quatech cards. These actually have configurable clocks but for 4125 * now we just use the default. 4126 * 4127 * 100 series are RS232, 200 series RS422, 4128 */ 4129 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4131 pbn_b1_4_115200 }, 4132 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4134 pbn_b1_2_115200 }, 4135 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4137 pbn_b2_2_115200 }, 4138 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4140 pbn_b1_2_115200 }, 4141 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4143 pbn_b2_2_115200 }, 4144 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4146 pbn_b1_4_115200 }, 4147 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4149 pbn_b1_8_115200 }, 4150 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4152 pbn_b1_8_115200 }, 4153 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4155 pbn_b1_4_115200 }, 4156 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4158 pbn_b1_2_115200 }, 4159 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4161 pbn_b1_4_115200 }, 4162 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4164 pbn_b1_2_115200 }, 4165 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4167 pbn_b2_4_115200 }, 4168 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4170 pbn_b2_2_115200 }, 4171 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4173 pbn_b2_1_115200 }, 4174 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4176 pbn_b2_4_115200 }, 4177 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4179 pbn_b2_2_115200 }, 4180 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4182 pbn_b2_1_115200 }, 4183 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4185 pbn_b0_8_115200 }, 4186 4187 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4188 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4189 0, 0, 4190 pbn_b0_4_921600 }, 4191 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4192 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4193 0, 0, 4194 pbn_b0_4_1152000 }, 4195 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4197 pbn_b0_bt_2_921600 }, 4198 4199 /* 4200 * The below card is a little controversial since it is the 4201 * subject of a PCI vendor/device ID clash. (See 4202 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4203 * For now just used the hex ID 0x950a. 4204 */ 4205 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4206 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4207 0, 0, pbn_b0_2_115200 }, 4208 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4209 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4210 0, 0, pbn_b0_2_115200 }, 4211 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4213 pbn_b0_2_1130000 }, 4214 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4215 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4216 pbn_b0_1_921600 }, 4217 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4219 pbn_b0_4_115200 }, 4220 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4222 pbn_b0_bt_2_921600 }, 4223 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4224 PCI_ANY_ID , PCI_ANY_ID, 0, 0, 4225 pbn_b2_8_1152000 }, 4226 4227 /* 4228 * Oxford Semiconductor Inc. Tornado PCI express device range. 4229 */ 4230 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4232 pbn_b0_1_4000000 }, 4233 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4235 pbn_b0_1_4000000 }, 4236 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4238 pbn_oxsemi_1_4000000 }, 4239 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4241 pbn_oxsemi_1_4000000 }, 4242 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4244 pbn_b0_1_4000000 }, 4245 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4247 pbn_b0_1_4000000 }, 4248 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4250 pbn_oxsemi_1_4000000 }, 4251 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4253 pbn_oxsemi_1_4000000 }, 4254 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4255 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4256 pbn_b0_1_4000000 }, 4257 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4259 pbn_b0_1_4000000 }, 4260 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4262 pbn_b0_1_4000000 }, 4263 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4265 pbn_b0_1_4000000 }, 4266 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4268 pbn_oxsemi_2_4000000 }, 4269 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4271 pbn_oxsemi_2_4000000 }, 4272 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4274 pbn_oxsemi_4_4000000 }, 4275 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4277 pbn_oxsemi_4_4000000 }, 4278 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4280 pbn_oxsemi_8_4000000 }, 4281 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4283 pbn_oxsemi_8_4000000 }, 4284 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4286 pbn_oxsemi_1_4000000 }, 4287 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4289 pbn_oxsemi_1_4000000 }, 4290 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4292 pbn_oxsemi_1_4000000 }, 4293 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4295 pbn_oxsemi_1_4000000 }, 4296 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4298 pbn_oxsemi_1_4000000 }, 4299 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4301 pbn_oxsemi_1_4000000 }, 4302 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4304 pbn_oxsemi_1_4000000 }, 4305 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4307 pbn_oxsemi_1_4000000 }, 4308 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4310 pbn_oxsemi_1_4000000 }, 4311 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4313 pbn_oxsemi_1_4000000 }, 4314 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4316 pbn_oxsemi_1_4000000 }, 4317 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4319 pbn_oxsemi_1_4000000 }, 4320 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4322 pbn_oxsemi_1_4000000 }, 4323 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4325 pbn_oxsemi_1_4000000 }, 4326 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4328 pbn_oxsemi_1_4000000 }, 4329 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4331 pbn_oxsemi_1_4000000 }, 4332 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4334 pbn_oxsemi_1_4000000 }, 4335 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4337 pbn_oxsemi_1_4000000 }, 4338 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4340 pbn_oxsemi_1_4000000 }, 4341 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4343 pbn_oxsemi_1_4000000 }, 4344 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4346 pbn_oxsemi_1_4000000 }, 4347 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4349 pbn_oxsemi_1_4000000 }, 4350 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_oxsemi_1_4000000 }, 4353 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4355 pbn_oxsemi_1_4000000 }, 4356 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4358 pbn_oxsemi_1_4000000 }, 4359 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4361 pbn_oxsemi_1_4000000 }, 4362 /* 4363 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4364 */ 4365 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4366 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4367 pbn_oxsemi_1_4000000 }, 4368 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4369 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4370 pbn_oxsemi_2_4000000 }, 4371 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4372 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4373 pbn_oxsemi_4_4000000 }, 4374 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4375 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4376 pbn_oxsemi_8_4000000 }, 4377 4378 /* 4379 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4380 */ 4381 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4382 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4383 pbn_oxsemi_2_4000000 }, 4384 4385 /* 4386 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4387 * from skokodyn@yahoo.com 4388 */ 4389 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4390 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4391 pbn_sbsxrsio }, 4392 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4393 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4394 pbn_sbsxrsio }, 4395 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4396 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4397 pbn_sbsxrsio }, 4398 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4399 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4400 pbn_sbsxrsio }, 4401 4402 /* 4403 * Digitan DS560-558, from jimd@esoft.com 4404 */ 4405 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4407 pbn_b1_1_115200 }, 4408 4409 /* 4410 * Titan Electronic cards 4411 * The 400L and 800L have a custom setup quirk. 4412 */ 4413 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b0_1_921600 }, 4416 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4418 pbn_b0_2_921600 }, 4419 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4421 pbn_b0_4_921600 }, 4422 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4424 pbn_b0_4_921600 }, 4425 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_b1_1_921600 }, 4428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4430 pbn_b1_bt_2_921600 }, 4431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4433 pbn_b0_bt_4_921600 }, 4434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4436 pbn_b0_bt_8_921600 }, 4437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4439 pbn_b4_bt_2_921600 }, 4440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4442 pbn_b4_bt_4_921600 }, 4443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4445 pbn_b4_bt_8_921600 }, 4446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4448 pbn_b0_4_921600 }, 4449 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4451 pbn_b0_4_921600 }, 4452 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4454 pbn_b0_4_921600 }, 4455 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4457 pbn_oxsemi_1_4000000 }, 4458 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4460 pbn_oxsemi_2_4000000 }, 4461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4463 pbn_oxsemi_4_4000000 }, 4464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4466 pbn_oxsemi_8_4000000 }, 4467 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4469 pbn_oxsemi_2_4000000 }, 4470 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4472 pbn_oxsemi_2_4000000 }, 4473 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4475 pbn_b0_bt_2_921600 }, 4476 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4478 pbn_b0_4_921600 }, 4479 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4481 pbn_b0_4_921600 }, 4482 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4484 pbn_b0_4_921600 }, 4485 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4487 pbn_b0_4_921600 }, 4488 4489 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4491 pbn_b2_1_460800 }, 4492 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4494 pbn_b2_1_460800 }, 4495 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4497 pbn_b2_1_460800 }, 4498 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4500 pbn_b2_bt_2_921600 }, 4501 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4503 pbn_b2_bt_2_921600 }, 4504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4506 pbn_b2_bt_2_921600 }, 4507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4509 pbn_b2_bt_4_921600 }, 4510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4512 pbn_b2_bt_4_921600 }, 4513 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4515 pbn_b2_bt_4_921600 }, 4516 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4518 pbn_b0_1_921600 }, 4519 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4521 pbn_b0_1_921600 }, 4522 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4524 pbn_b0_1_921600 }, 4525 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4527 pbn_b0_bt_2_921600 }, 4528 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4530 pbn_b0_bt_2_921600 }, 4531 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4533 pbn_b0_bt_2_921600 }, 4534 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4536 pbn_b0_bt_4_921600 }, 4537 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4539 pbn_b0_bt_4_921600 }, 4540 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4542 pbn_b0_bt_4_921600 }, 4543 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4545 pbn_b0_bt_8_921600 }, 4546 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4548 pbn_b0_bt_8_921600 }, 4549 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4551 pbn_b0_bt_8_921600 }, 4552 4553 /* 4554 * Computone devices submitted by Doug McNash dmcnash@computone.com 4555 */ 4556 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4557 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4558 0, 0, pbn_computone_4 }, 4559 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4560 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4561 0, 0, pbn_computone_8 }, 4562 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4563 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4564 0, 0, pbn_computone_6 }, 4565 4566 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4568 pbn_oxsemi }, 4569 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4570 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4571 pbn_b0_bt_1_921600 }, 4572 4573 /* 4574 * SUNIX (TIMEDIA) 4575 */ 4576 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4577 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4578 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, 4579 pbn_b0_bt_1_921600 }, 4580 4581 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4582 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, 4583 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 4584 pbn_b0_bt_1_921600 }, 4585 4586 /* 4587 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4588 */ 4589 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_b0_bt_8_115200 }, 4592 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4594 pbn_b0_bt_8_115200 }, 4595 4596 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4598 pbn_b0_bt_2_115200 }, 4599 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4601 pbn_b0_bt_2_115200 }, 4602 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4604 pbn_b0_bt_2_115200 }, 4605 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4607 pbn_b0_bt_2_115200 }, 4608 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4610 pbn_b0_bt_2_115200 }, 4611 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4613 pbn_b0_bt_4_460800 }, 4614 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4616 pbn_b0_bt_4_460800 }, 4617 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4619 pbn_b0_bt_2_460800 }, 4620 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4622 pbn_b0_bt_2_460800 }, 4623 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4625 pbn_b0_bt_2_460800 }, 4626 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4628 pbn_b0_bt_1_115200 }, 4629 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4631 pbn_b0_bt_1_460800 }, 4632 4633 /* 4634 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4635 * Cards are identified by their subsystem vendor IDs, which 4636 * (in hex) match the model number. 4637 * 4638 * Note that JC140x are RS422/485 cards which require ox950 4639 * ACR = 0x10, and as such are not currently fully supported. 4640 */ 4641 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4642 0x1204, 0x0004, 0, 0, 4643 pbn_b0_4_921600 }, 4644 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4645 0x1208, 0x0004, 0, 0, 4646 pbn_b0_4_921600 }, 4647 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4648 0x1402, 0x0002, 0, 0, 4649 pbn_b0_2_921600 }, */ 4650 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4651 0x1404, 0x0004, 0, 0, 4652 pbn_b0_4_921600 }, */ 4653 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4654 0x1208, 0x0004, 0, 0, 4655 pbn_b0_4_921600 }, 4656 4657 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4658 0x1204, 0x0004, 0, 0, 4659 pbn_b0_4_921600 }, 4660 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4661 0x1208, 0x0004, 0, 0, 4662 pbn_b0_4_921600 }, 4663 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4664 0x1208, 0x0004, 0, 0, 4665 pbn_b0_4_921600 }, 4666 /* 4667 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4668 */ 4669 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4671 pbn_b1_1_1382400 }, 4672 4673 /* 4674 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4675 */ 4676 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b1_1_1382400 }, 4679 4680 /* 4681 * RAStel 2 port modem, gerg@moreton.com.au 4682 */ 4683 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4684 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4685 pbn_b2_bt_2_115200 }, 4686 4687 /* 4688 * EKF addition for i960 Boards form EKF with serial port 4689 */ 4690 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4691 0xE4BF, PCI_ANY_ID, 0, 0, 4692 pbn_intel_i960 }, 4693 4694 /* 4695 * Xircom Cardbus/Ethernet combos 4696 */ 4697 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_b0_1_115200 }, 4700 /* 4701 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4702 */ 4703 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_b0_1_115200 }, 4706 4707 /* 4708 * Untested PCI modems, sent in from various folks... 4709 */ 4710 4711 /* 4712 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4713 */ 4714 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4715 0x1048, 0x1500, 0, 0, 4716 pbn_b1_1_115200 }, 4717 4718 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4719 0xFF00, 0, 0, 0, 4720 pbn_sgi_ioc3 }, 4721 4722 /* 4723 * HP Diva card 4724 */ 4725 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4726 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4727 pbn_b1_1_115200 }, 4728 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_b0_5_115200 }, 4731 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_b2_1_115200 }, 4734 4735 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4737 pbn_b3_2_115200 }, 4738 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4740 pbn_b3_4_115200 }, 4741 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4743 pbn_b3_8_115200 }, 4744 4745 /* 4746 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART 4747 */ 4748 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152, 4749 PCI_ANY_ID, PCI_ANY_ID, 4750 0, 4751 0, pbn_exar_XR17C152 }, 4752 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154, 4753 PCI_ANY_ID, PCI_ANY_ID, 4754 0, 4755 0, pbn_exar_XR17C154 }, 4756 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158, 4757 PCI_ANY_ID, PCI_ANY_ID, 4758 0, 4759 0, pbn_exar_XR17C158 }, 4760 /* 4761 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs 4762 */ 4763 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352, 4764 PCI_ANY_ID, PCI_ANY_ID, 4765 0, 4766 0, pbn_exar_XR17V352 }, 4767 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354, 4768 PCI_ANY_ID, PCI_ANY_ID, 4769 0, 4770 0, pbn_exar_XR17V354 }, 4771 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358, 4772 PCI_ANY_ID, PCI_ANY_ID, 4773 0, 4774 0, pbn_exar_XR17V358 }, 4775 4776 /* 4777 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 4778 */ 4779 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4781 pbn_b0_1_115200 }, 4782 /* 4783 * ITE 4784 */ 4785 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 4786 PCI_ANY_ID, PCI_ANY_ID, 4787 0, 0, 4788 pbn_b1_bt_1_115200 }, 4789 4790 /* 4791 * IntaShield IS-200 4792 */ 4793 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4795 pbn_b2_2_115200 }, 4796 /* 4797 * IntaShield IS-400 4798 */ 4799 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 4801 pbn_b2_4_115200 }, 4802 /* 4803 * Perle PCI-RAS cards 4804 */ 4805 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4806 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 4807 0, 0, pbn_b2_4_921600 }, 4808 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4809 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 4810 0, 0, pbn_b2_8_921600 }, 4811 4812 /* 4813 * Mainpine series cards: Fairly standard layout but fools 4814 * parts of the autodetect in some cases and uses otherwise 4815 * unmatched communications subclasses in the PCI Express case 4816 */ 4817 4818 { /* RockForceDUO */ 4819 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4820 PCI_VENDOR_ID_MAINPINE, 0x0200, 4821 0, 0, pbn_b0_2_115200 }, 4822 { /* RockForceQUATRO */ 4823 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4824 PCI_VENDOR_ID_MAINPINE, 0x0300, 4825 0, 0, pbn_b0_4_115200 }, 4826 { /* RockForceDUO+ */ 4827 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4828 PCI_VENDOR_ID_MAINPINE, 0x0400, 4829 0, 0, pbn_b0_2_115200 }, 4830 { /* RockForceQUATRO+ */ 4831 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4832 PCI_VENDOR_ID_MAINPINE, 0x0500, 4833 0, 0, pbn_b0_4_115200 }, 4834 { /* RockForce+ */ 4835 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4836 PCI_VENDOR_ID_MAINPINE, 0x0600, 4837 0, 0, pbn_b0_2_115200 }, 4838 { /* RockForce+ */ 4839 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4840 PCI_VENDOR_ID_MAINPINE, 0x0700, 4841 0, 0, pbn_b0_4_115200 }, 4842 { /* RockForceOCTO+ */ 4843 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4844 PCI_VENDOR_ID_MAINPINE, 0x0800, 4845 0, 0, pbn_b0_8_115200 }, 4846 { /* RockForceDUO+ */ 4847 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4848 PCI_VENDOR_ID_MAINPINE, 0x0C00, 4849 0, 0, pbn_b0_2_115200 }, 4850 { /* RockForceQUARTRO+ */ 4851 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4852 PCI_VENDOR_ID_MAINPINE, 0x0D00, 4853 0, 0, pbn_b0_4_115200 }, 4854 { /* RockForceOCTO+ */ 4855 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4856 PCI_VENDOR_ID_MAINPINE, 0x1D00, 4857 0, 0, pbn_b0_8_115200 }, 4858 { /* RockForceD1 */ 4859 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4860 PCI_VENDOR_ID_MAINPINE, 0x2000, 4861 0, 0, pbn_b0_1_115200 }, 4862 { /* RockForceF1 */ 4863 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4864 PCI_VENDOR_ID_MAINPINE, 0x2100, 4865 0, 0, pbn_b0_1_115200 }, 4866 { /* RockForceD2 */ 4867 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4868 PCI_VENDOR_ID_MAINPINE, 0x2200, 4869 0, 0, pbn_b0_2_115200 }, 4870 { /* RockForceF2 */ 4871 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4872 PCI_VENDOR_ID_MAINPINE, 0x2300, 4873 0, 0, pbn_b0_2_115200 }, 4874 { /* RockForceD4 */ 4875 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4876 PCI_VENDOR_ID_MAINPINE, 0x2400, 4877 0, 0, pbn_b0_4_115200 }, 4878 { /* RockForceF4 */ 4879 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4880 PCI_VENDOR_ID_MAINPINE, 0x2500, 4881 0, 0, pbn_b0_4_115200 }, 4882 { /* RockForceD8 */ 4883 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4884 PCI_VENDOR_ID_MAINPINE, 0x2600, 4885 0, 0, pbn_b0_8_115200 }, 4886 { /* RockForceF8 */ 4887 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4888 PCI_VENDOR_ID_MAINPINE, 0x2700, 4889 0, 0, pbn_b0_8_115200 }, 4890 { /* IQ Express D1 */ 4891 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4892 PCI_VENDOR_ID_MAINPINE, 0x3000, 4893 0, 0, pbn_b0_1_115200 }, 4894 { /* IQ Express F1 */ 4895 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4896 PCI_VENDOR_ID_MAINPINE, 0x3100, 4897 0, 0, pbn_b0_1_115200 }, 4898 { /* IQ Express D2 */ 4899 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4900 PCI_VENDOR_ID_MAINPINE, 0x3200, 4901 0, 0, pbn_b0_2_115200 }, 4902 { /* IQ Express F2 */ 4903 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4904 PCI_VENDOR_ID_MAINPINE, 0x3300, 4905 0, 0, pbn_b0_2_115200 }, 4906 { /* IQ Express D4 */ 4907 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4908 PCI_VENDOR_ID_MAINPINE, 0x3400, 4909 0, 0, pbn_b0_4_115200 }, 4910 { /* IQ Express F4 */ 4911 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4912 PCI_VENDOR_ID_MAINPINE, 0x3500, 4913 0, 0, pbn_b0_4_115200 }, 4914 { /* IQ Express D8 */ 4915 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4916 PCI_VENDOR_ID_MAINPINE, 0x3C00, 4917 0, 0, pbn_b0_8_115200 }, 4918 { /* IQ Express F8 */ 4919 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 4920 PCI_VENDOR_ID_MAINPINE, 0x3D00, 4921 0, 0, pbn_b0_8_115200 }, 4922 4923 4924 /* 4925 * PA Semi PA6T-1682M on-chip UART 4926 */ 4927 { PCI_VENDOR_ID_PASEMI, 0xa004, 4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4929 pbn_pasemi_1682M }, 4930 4931 /* 4932 * National Instruments 4933 */ 4934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4936 pbn_b1_16_115200 }, 4937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4939 pbn_b1_8_115200 }, 4940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4942 pbn_b1_bt_4_115200 }, 4943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4945 pbn_b1_bt_2_115200 }, 4946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4948 pbn_b1_bt_4_115200 }, 4949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4951 pbn_b1_bt_2_115200 }, 4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4954 pbn_b1_16_115200 }, 4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4957 pbn_b1_8_115200 }, 4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4960 pbn_b1_bt_4_115200 }, 4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4963 pbn_b1_bt_2_115200 }, 4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4966 pbn_b1_bt_4_115200 }, 4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4969 pbn_b1_bt_2_115200 }, 4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4972 pbn_ni8430_2 }, 4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4975 pbn_ni8430_2 }, 4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4978 pbn_ni8430_4 }, 4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4981 pbn_ni8430_4 }, 4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4984 pbn_ni8430_8 }, 4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4987 pbn_ni8430_8 }, 4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4990 pbn_ni8430_16 }, 4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4993 pbn_ni8430_16 }, 4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4996 pbn_ni8430_2 }, 4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4999 pbn_ni8430_2 }, 5000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5002 pbn_ni8430_4 }, 5003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5005 pbn_ni8430_4 }, 5006 5007 /* 5008 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5009 */ 5010 { PCI_VENDOR_ID_ADDIDATA, 5011 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5012 PCI_ANY_ID, 5013 PCI_ANY_ID, 5014 0, 5015 0, 5016 pbn_b0_4_115200 }, 5017 5018 { PCI_VENDOR_ID_ADDIDATA, 5019 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5020 PCI_ANY_ID, 5021 PCI_ANY_ID, 5022 0, 5023 0, 5024 pbn_b0_2_115200 }, 5025 5026 { PCI_VENDOR_ID_ADDIDATA, 5027 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5028 PCI_ANY_ID, 5029 PCI_ANY_ID, 5030 0, 5031 0, 5032 pbn_b0_1_115200 }, 5033 5034 { PCI_VENDOR_ID_AMCC, 5035 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5036 PCI_ANY_ID, 5037 PCI_ANY_ID, 5038 0, 5039 0, 5040 pbn_b1_8_115200 }, 5041 5042 { PCI_VENDOR_ID_ADDIDATA, 5043 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5044 PCI_ANY_ID, 5045 PCI_ANY_ID, 5046 0, 5047 0, 5048 pbn_b0_4_115200 }, 5049 5050 { PCI_VENDOR_ID_ADDIDATA, 5051 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5052 PCI_ANY_ID, 5053 PCI_ANY_ID, 5054 0, 5055 0, 5056 pbn_b0_2_115200 }, 5057 5058 { PCI_VENDOR_ID_ADDIDATA, 5059 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5060 PCI_ANY_ID, 5061 PCI_ANY_ID, 5062 0, 5063 0, 5064 pbn_b0_1_115200 }, 5065 5066 { PCI_VENDOR_ID_ADDIDATA, 5067 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5068 PCI_ANY_ID, 5069 PCI_ANY_ID, 5070 0, 5071 0, 5072 pbn_b0_4_115200 }, 5073 5074 { PCI_VENDOR_ID_ADDIDATA, 5075 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5076 PCI_ANY_ID, 5077 PCI_ANY_ID, 5078 0, 5079 0, 5080 pbn_b0_2_115200 }, 5081 5082 { PCI_VENDOR_ID_ADDIDATA, 5083 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5084 PCI_ANY_ID, 5085 PCI_ANY_ID, 5086 0, 5087 0, 5088 pbn_b0_1_115200 }, 5089 5090 { PCI_VENDOR_ID_ADDIDATA, 5091 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5092 PCI_ANY_ID, 5093 PCI_ANY_ID, 5094 0, 5095 0, 5096 pbn_b0_8_115200 }, 5097 5098 { PCI_VENDOR_ID_ADDIDATA, 5099 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5100 PCI_ANY_ID, 5101 PCI_ANY_ID, 5102 0, 5103 0, 5104 pbn_ADDIDATA_PCIe_4_3906250 }, 5105 5106 { PCI_VENDOR_ID_ADDIDATA, 5107 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5108 PCI_ANY_ID, 5109 PCI_ANY_ID, 5110 0, 5111 0, 5112 pbn_ADDIDATA_PCIe_2_3906250 }, 5113 5114 { PCI_VENDOR_ID_ADDIDATA, 5115 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5116 PCI_ANY_ID, 5117 PCI_ANY_ID, 5118 0, 5119 0, 5120 pbn_ADDIDATA_PCIe_1_3906250 }, 5121 5122 { PCI_VENDOR_ID_ADDIDATA, 5123 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5124 PCI_ANY_ID, 5125 PCI_ANY_ID, 5126 0, 5127 0, 5128 pbn_ADDIDATA_PCIe_8_3906250 }, 5129 5130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5131 PCI_VENDOR_ID_IBM, 0x0299, 5132 0, 0, pbn_b0_bt_2_115200 }, 5133 5134 /* 5135 * other NetMos 9835 devices are most likely handled by the 5136 * parport_serial driver, check drivers/parport/parport_serial.c 5137 * before adding them here. 5138 */ 5139 5140 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5141 0xA000, 0x1000, 5142 0, 0, pbn_b0_1_115200 }, 5143 5144 /* the 9901 is a rebranded 9912 */ 5145 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5146 0xA000, 0x1000, 5147 0, 0, pbn_b0_1_115200 }, 5148 5149 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5150 0xA000, 0x1000, 5151 0, 0, pbn_b0_1_115200 }, 5152 5153 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5154 0xA000, 0x1000, 5155 0, 0, pbn_b0_1_115200 }, 5156 5157 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5158 0xA000, 0x1000, 5159 0, 0, pbn_b0_1_115200 }, 5160 5161 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5162 0xA000, 0x3002, 5163 0, 0, pbn_NETMOS9900_2s_115200 }, 5164 5165 /* 5166 * Best Connectivity and Rosewill PCI Multi I/O cards 5167 */ 5168 5169 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5170 0xA000, 0x1000, 5171 0, 0, pbn_b0_1_115200 }, 5172 5173 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5174 0xA000, 0x3002, 5175 0, 0, pbn_b0_bt_2_115200 }, 5176 5177 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5178 0xA000, 0x3004, 5179 0, 0, pbn_b0_bt_4_115200 }, 5180 /* Intel CE4100 */ 5181 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5183 pbn_ce4100_1_115200 }, 5184 /* Intel BayTrail */ 5185 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1, 5186 PCI_ANY_ID, PCI_ANY_ID, 5187 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5188 pbn_byt }, 5189 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2, 5190 PCI_ANY_ID, PCI_ANY_ID, 5191 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000, 5192 pbn_byt }, 5193 5194 /* 5195 * Cronyx Omega PCI 5196 */ 5197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5199 pbn_omegapci }, 5200 5201 /* 5202 * Broadcom TruManage 5203 */ 5204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5206 pbn_brcm_trumanage }, 5207 5208 /* 5209 * AgeStar as-prs2-009 5210 */ 5211 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5212 PCI_ANY_ID, PCI_ANY_ID, 5213 0, 0, pbn_b0_bt_2_115200 }, 5214 5215 /* 5216 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5217 * so not listed here. 5218 */ 5219 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5220 PCI_ANY_ID, PCI_ANY_ID, 5221 0, 0, pbn_b0_bt_4_115200 }, 5222 5223 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5224 PCI_ANY_ID, PCI_ANY_ID, 5225 0, 0, pbn_b0_bt_2_115200 }, 5226 5227 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S, 5228 PCI_ANY_ID, PCI_ANY_ID, 5229 0, 0, pbn_b0_bt_2_115200 }, 5230 5231 /* 5232 * Commtech, Inc. Fastcom adapters 5233 */ 5234 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335, 5235 PCI_ANY_ID, PCI_ANY_ID, 5236 0, 5237 0, pbn_b0_2_1152000_200 }, 5238 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335, 5239 PCI_ANY_ID, PCI_ANY_ID, 5240 0, 5241 0, pbn_b0_4_1152000_200 }, 5242 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335, 5243 PCI_ANY_ID, PCI_ANY_ID, 5244 0, 5245 0, pbn_b0_4_1152000_200 }, 5246 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335, 5247 PCI_ANY_ID, PCI_ANY_ID, 5248 0, 5249 0, pbn_b0_8_1152000_200 }, 5250 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE, 5251 PCI_ANY_ID, PCI_ANY_ID, 5252 0, 5253 0, pbn_exar_XR17V352 }, 5254 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE, 5255 PCI_ANY_ID, PCI_ANY_ID, 5256 0, 5257 0, pbn_exar_XR17V354 }, 5258 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE, 5259 PCI_ANY_ID, PCI_ANY_ID, 5260 0, 5261 0, pbn_exar_XR17V358 }, 5262 5263 /* Fintek PCI serial cards */ 5264 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5265 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5266 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5267 5268 /* 5269 * These entries match devices with class COMMUNICATION_SERIAL, 5270 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5271 */ 5272 { PCI_ANY_ID, PCI_ANY_ID, 5273 PCI_ANY_ID, PCI_ANY_ID, 5274 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5275 0xffff00, pbn_default }, 5276 { PCI_ANY_ID, PCI_ANY_ID, 5277 PCI_ANY_ID, PCI_ANY_ID, 5278 PCI_CLASS_COMMUNICATION_MODEM << 8, 5279 0xffff00, pbn_default }, 5280 { PCI_ANY_ID, PCI_ANY_ID, 5281 PCI_ANY_ID, PCI_ANY_ID, 5282 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5283 0xffff00, pbn_default }, 5284 { 0, } 5285 }; 5286 5287 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5288 pci_channel_state_t state) 5289 { 5290 struct serial_private *priv = pci_get_drvdata(dev); 5291 5292 if (state == pci_channel_io_perm_failure) 5293 return PCI_ERS_RESULT_DISCONNECT; 5294 5295 if (priv) 5296 pciserial_suspend_ports(priv); 5297 5298 pci_disable_device(dev); 5299 5300 return PCI_ERS_RESULT_NEED_RESET; 5301 } 5302 5303 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5304 { 5305 int rc; 5306 5307 rc = pci_enable_device(dev); 5308 5309 if (rc) 5310 return PCI_ERS_RESULT_DISCONNECT; 5311 5312 pci_restore_state(dev); 5313 pci_save_state(dev); 5314 5315 return PCI_ERS_RESULT_RECOVERED; 5316 } 5317 5318 static void serial8250_io_resume(struct pci_dev *dev) 5319 { 5320 struct serial_private *priv = pci_get_drvdata(dev); 5321 5322 if (priv) 5323 pciserial_resume_ports(priv); 5324 } 5325 5326 static const struct pci_error_handlers serial8250_err_handler = { 5327 .error_detected = serial8250_io_error_detected, 5328 .slot_reset = serial8250_io_slot_reset, 5329 .resume = serial8250_io_resume, 5330 }; 5331 5332 static struct pci_driver serial_pci_driver = { 5333 .name = "serial", 5334 .probe = pciserial_init_one, 5335 .remove = pciserial_remove_one, 5336 #ifdef CONFIG_PM 5337 .suspend = pciserial_suspend_one, 5338 .resume = pciserial_resume_one, 5339 #endif 5340 .id_table = serial_pci_tbl, 5341 .err_handler = &serial8250_err_handler, 5342 }; 5343 5344 module_pci_driver(serial_pci_driver); 5345 5346 MODULE_LICENSE("GPL"); 5347 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5348 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5349