1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/tty.h> 17 #include <linux/serial_reg.h> 18 #include <linux/serial_core.h> 19 #include <linux/8250_pci.h> 20 #include <linux/bitops.h> 21 22 #include <asm/byteorder.h> 23 #include <asm/io.h> 24 25 #include "8250.h" 26 27 /* 28 * init function returns: 29 * > 0 - number of ports 30 * = 0 - use board->num_ports 31 * < 0 - error 32 */ 33 struct pci_serial_quirk { 34 u32 vendor; 35 u32 device; 36 u32 subvendor; 37 u32 subdevice; 38 int (*probe)(struct pci_dev *dev); 39 int (*init)(struct pci_dev *dev); 40 int (*setup)(struct serial_private *, 41 const struct pciserial_board *, 42 struct uart_8250_port *, int); 43 void (*exit)(struct pci_dev *dev); 44 }; 45 46 struct f815xxa_data { 47 spinlock_t lock; 48 int idx; 49 }; 50 51 struct serial_private { 52 struct pci_dev *dev; 53 unsigned int nr; 54 struct pci_serial_quirk *quirk; 55 const struct pciserial_board *board; 56 int line[]; 57 }; 58 59 static const struct pci_device_id pci_use_msi[] = { 60 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 61 0xA000, 0x1000) }, 62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 63 0xA000, 0x1000) }, 64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 65 0xA000, 0x1000) }, 66 { } 67 }; 68 69 static int pci_default_setup(struct serial_private*, 70 const struct pciserial_board*, struct uart_8250_port *, int); 71 72 static void moan_device(const char *str, struct pci_dev *dev) 73 { 74 dev_err(&dev->dev, 75 "%s: %s\n" 76 "Please send the output of lspci -vv, this\n" 77 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 78 "manufacturer and name of serial board or\n" 79 "modem board to <linux-serial@vger.kernel.org>.\n", 80 pci_name(dev), str, dev->vendor, dev->device, 81 dev->subsystem_vendor, dev->subsystem_device); 82 } 83 84 static int 85 setup_port(struct serial_private *priv, struct uart_8250_port *port, 86 int bar, int offset, int regshift) 87 { 88 struct pci_dev *dev = priv->dev; 89 90 if (bar >= PCI_STD_NUM_BARS) 91 return -EINVAL; 92 93 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { 94 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) 95 return -ENOMEM; 96 97 port->port.iotype = UPIO_MEM; 98 port->port.iobase = 0; 99 port->port.mapbase = pci_resource_start(dev, bar) + offset; 100 port->port.membase = pcim_iomap_table(dev)[bar] + offset; 101 port->port.regshift = regshift; 102 } else { 103 port->port.iotype = UPIO_PORT; 104 port->port.iobase = pci_resource_start(dev, bar) + offset; 105 port->port.mapbase = 0; 106 port->port.membase = NULL; 107 port->port.regshift = 0; 108 } 109 return 0; 110 } 111 112 /* 113 * ADDI-DATA GmbH communication cards <info@addi-data.com> 114 */ 115 static int addidata_apci7800_setup(struct serial_private *priv, 116 const struct pciserial_board *board, 117 struct uart_8250_port *port, int idx) 118 { 119 unsigned int bar = 0, offset = board->first_offset; 120 bar = FL_GET_BASE(board->flags); 121 122 if (idx < 2) { 123 offset += idx * board->uart_offset; 124 } else if ((idx >= 2) && (idx < 4)) { 125 bar += 1; 126 offset += ((idx - 2) * board->uart_offset); 127 } else if ((idx >= 4) && (idx < 6)) { 128 bar += 2; 129 offset += ((idx - 4) * board->uart_offset); 130 } else if (idx >= 6) { 131 bar += 3; 132 offset += ((idx - 6) * board->uart_offset); 133 } 134 135 return setup_port(priv, port, bar, offset, board->reg_shift); 136 } 137 138 /* 139 * AFAVLAB uses a different mixture of BARs and offsets 140 * Not that ugly ;) -- HW 141 */ 142 static int 143 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 144 struct uart_8250_port *port, int idx) 145 { 146 unsigned int bar, offset = board->first_offset; 147 148 bar = FL_GET_BASE(board->flags); 149 if (idx < 4) 150 bar += idx; 151 else { 152 bar = 4; 153 offset += (idx - 4) * board->uart_offset; 154 } 155 156 return setup_port(priv, port, bar, offset, board->reg_shift); 157 } 158 159 /* 160 * HP's Remote Management Console. The Diva chip came in several 161 * different versions. N-class, L2000 and A500 have two Diva chips, each 162 * with 3 UARTs (the third UART on the second chip is unused). Superdome 163 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 164 * one Diva chip, but it has been expanded to 5 UARTs. 165 */ 166 static int pci_hp_diva_init(struct pci_dev *dev) 167 { 168 int rc = 0; 169 170 switch (dev->subsystem_device) { 171 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 172 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 173 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 174 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 175 rc = 3; 176 break; 177 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 178 rc = 2; 179 break; 180 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 181 rc = 4; 182 break; 183 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 184 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 185 rc = 1; 186 break; 187 } 188 189 return rc; 190 } 191 192 /* 193 * HP's Diva chip puts the 4th/5th serial port further out, and 194 * some serial ports are supposed to be hidden on certain models. 195 */ 196 static int 197 pci_hp_diva_setup(struct serial_private *priv, 198 const struct pciserial_board *board, 199 struct uart_8250_port *port, int idx) 200 { 201 unsigned int offset = board->first_offset; 202 unsigned int bar = FL_GET_BASE(board->flags); 203 204 switch (priv->dev->subsystem_device) { 205 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 206 if (idx == 3) 207 idx++; 208 break; 209 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 210 if (idx > 0) 211 idx++; 212 if (idx > 2) 213 idx++; 214 break; 215 } 216 if (idx > 2) 217 offset = 0x18; 218 219 offset += idx * board->uart_offset; 220 221 return setup_port(priv, port, bar, offset, board->reg_shift); 222 } 223 224 /* 225 * Added for EKF Intel i960 serial boards 226 */ 227 static int pci_inteli960ni_init(struct pci_dev *dev) 228 { 229 u32 oldval; 230 231 if (!(dev->subsystem_device & 0x1000)) 232 return -ENODEV; 233 234 /* is firmware started? */ 235 pci_read_config_dword(dev, 0x44, &oldval); 236 if (oldval == 0x00001000L) { /* RESET value */ 237 dev_dbg(&dev->dev, "Local i960 firmware missing\n"); 238 return -ENODEV; 239 } 240 return 0; 241 } 242 243 /* 244 * Some PCI serial cards using the PLX 9050 PCI interface chip require 245 * that the card interrupt be explicitly enabled or disabled. This 246 * seems to be mainly needed on card using the PLX which also use I/O 247 * mapped memory. 248 */ 249 static int pci_plx9050_init(struct pci_dev *dev) 250 { 251 u8 irq_config; 252 void __iomem *p; 253 254 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 255 moan_device("no memory in bar 0", dev); 256 return 0; 257 } 258 259 irq_config = 0x41; 260 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 261 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 262 irq_config = 0x43; 263 264 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 265 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 266 /* 267 * As the megawolf cards have the int pins active 268 * high, and have 2 UART chips, both ints must be 269 * enabled on the 9050. Also, the UARTS are set in 270 * 16450 mode by default, so we have to enable the 271 * 16C950 'enhanced' mode so that we can use the 272 * deep FIFOs 273 */ 274 irq_config = 0x5b; 275 /* 276 * enable/disable interrupts 277 */ 278 p = ioremap(pci_resource_start(dev, 0), 0x80); 279 if (p == NULL) 280 return -ENOMEM; 281 writel(irq_config, p + 0x4c); 282 283 /* 284 * Read the register back to ensure that it took effect. 285 */ 286 readl(p + 0x4c); 287 iounmap(p); 288 289 return 0; 290 } 291 292 static void pci_plx9050_exit(struct pci_dev *dev) 293 { 294 u8 __iomem *p; 295 296 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 297 return; 298 299 /* 300 * disable interrupts 301 */ 302 p = ioremap(pci_resource_start(dev, 0), 0x80); 303 if (p != NULL) { 304 writel(0, p + 0x4c); 305 306 /* 307 * Read the register back to ensure that it took effect. 308 */ 309 readl(p + 0x4c); 310 iounmap(p); 311 } 312 } 313 314 #define NI8420_INT_ENABLE_REG 0x38 315 #define NI8420_INT_ENABLE_BIT 0x2000 316 317 static void pci_ni8420_exit(struct pci_dev *dev) 318 { 319 void __iomem *p; 320 unsigned int bar = 0; 321 322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 323 moan_device("no memory in bar", dev); 324 return; 325 } 326 327 p = pci_ioremap_bar(dev, bar); 328 if (p == NULL) 329 return; 330 331 /* Disable the CPU Interrupt */ 332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 333 p + NI8420_INT_ENABLE_REG); 334 iounmap(p); 335 } 336 337 338 /* MITE registers */ 339 #define MITE_IOWBSR1 0xc4 340 #define MITE_IOWCR1 0xf4 341 #define MITE_LCIMR1 0x08 342 #define MITE_LCIMR2 0x10 343 344 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 345 346 static void pci_ni8430_exit(struct pci_dev *dev) 347 { 348 void __iomem *p; 349 unsigned int bar = 0; 350 351 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 352 moan_device("no memory in bar", dev); 353 return; 354 } 355 356 p = pci_ioremap_bar(dev, bar); 357 if (p == NULL) 358 return; 359 360 /* Disable the CPU Interrupt */ 361 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 362 iounmap(p); 363 } 364 365 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 366 static int 367 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 368 struct uart_8250_port *port, int idx) 369 { 370 unsigned int bar, offset = board->first_offset; 371 372 bar = 0; 373 374 if (idx < 4) { 375 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 376 offset += idx * board->uart_offset; 377 } else if (idx < 8) { 378 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 379 offset += idx * board->uart_offset + 0xC00; 380 } else /* we have only 8 ports on PMC-OCTALPRO */ 381 return 1; 382 383 return setup_port(priv, port, bar, offset, board->reg_shift); 384 } 385 386 /* 387 * This does initialization for PMC OCTALPRO cards: 388 * maps the device memory, resets the UARTs (needed, bc 389 * if the module is removed and inserted again, the card 390 * is in the sleep mode) and enables global interrupt. 391 */ 392 393 /* global control register offset for SBS PMC-OctalPro */ 394 #define OCT_REG_CR_OFF 0x500 395 396 static int sbs_init(struct pci_dev *dev) 397 { 398 u8 __iomem *p; 399 400 p = pci_ioremap_bar(dev, 0); 401 402 if (p == NULL) 403 return -ENOMEM; 404 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 405 writeb(0x10, p + OCT_REG_CR_OFF); 406 udelay(50); 407 writeb(0x0, p + OCT_REG_CR_OFF); 408 409 /* Set bit-2 (INTENABLE) of Control Register */ 410 writeb(0x4, p + OCT_REG_CR_OFF); 411 iounmap(p); 412 413 return 0; 414 } 415 416 /* 417 * Disables the global interrupt of PMC-OctalPro 418 */ 419 420 static void sbs_exit(struct pci_dev *dev) 421 { 422 u8 __iomem *p; 423 424 p = pci_ioremap_bar(dev, 0); 425 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 426 if (p != NULL) 427 writeb(0, p + OCT_REG_CR_OFF); 428 iounmap(p); 429 } 430 431 /* 432 * SIIG serial cards have an PCI interface chip which also controls 433 * the UART clocking frequency. Each UART can be clocked independently 434 * (except cards equipped with 4 UARTs) and initial clocking settings 435 * are stored in the EEPROM chip. It can cause problems because this 436 * version of serial driver doesn't support differently clocked UART's 437 * on single PCI card. To prevent this, initialization functions set 438 * high frequency clocking for all UART's on given card. It is safe (I 439 * hope) because it doesn't touch EEPROM settings to prevent conflicts 440 * with other OSes (like M$ DOS). 441 * 442 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 443 * 444 * There is two family of SIIG serial cards with different PCI 445 * interface chip and different configuration methods: 446 * - 10x cards have control registers in IO and/or memory space; 447 * - 20x cards have control registers in standard PCI configuration space. 448 * 449 * Note: all 10x cards have PCI device ids 0x10.. 450 * all 20x cards have PCI device ids 0x20.. 451 * 452 * There are also Quartet Serial cards which use Oxford Semiconductor 453 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 454 * 455 * Note: some SIIG cards are probed by the parport_serial object. 456 */ 457 458 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 459 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 460 461 static int pci_siig10x_init(struct pci_dev *dev) 462 { 463 u16 data; 464 void __iomem *p; 465 466 switch (dev->device & 0xfff8) { 467 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 468 data = 0xffdf; 469 break; 470 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 471 data = 0xf7ff; 472 break; 473 default: /* 1S1P, 4S */ 474 data = 0xfffb; 475 break; 476 } 477 478 p = ioremap(pci_resource_start(dev, 0), 0x80); 479 if (p == NULL) 480 return -ENOMEM; 481 482 writew(readw(p + 0x28) & data, p + 0x28); 483 readw(p + 0x28); 484 iounmap(p); 485 return 0; 486 } 487 488 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 489 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 490 491 static int pci_siig20x_init(struct pci_dev *dev) 492 { 493 u8 data; 494 495 /* Change clock frequency for the first UART. */ 496 pci_read_config_byte(dev, 0x6f, &data); 497 pci_write_config_byte(dev, 0x6f, data & 0xef); 498 499 /* If this card has 2 UART, we have to do the same with second UART. */ 500 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 501 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 502 pci_read_config_byte(dev, 0x73, &data); 503 pci_write_config_byte(dev, 0x73, data & 0xef); 504 } 505 return 0; 506 } 507 508 static int pci_siig_init(struct pci_dev *dev) 509 { 510 unsigned int type = dev->device & 0xff00; 511 512 if (type == 0x1000) 513 return pci_siig10x_init(dev); 514 else if (type == 0x2000) 515 return pci_siig20x_init(dev); 516 517 moan_device("Unknown SIIG card", dev); 518 return -ENODEV; 519 } 520 521 static int pci_siig_setup(struct serial_private *priv, 522 const struct pciserial_board *board, 523 struct uart_8250_port *port, int idx) 524 { 525 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 526 527 if (idx > 3) { 528 bar = 4; 529 offset = (idx - 4) * 8; 530 } 531 532 return setup_port(priv, port, bar, offset, 0); 533 } 534 535 /* 536 * Timedia has an explosion of boards, and to avoid the PCI table from 537 * growing *huge*, we use this function to collapse some 70 entries 538 * in the PCI table into one, for sanity's and compactness's sake. 539 */ 540 static const unsigned short timedia_single_port[] = { 541 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 542 }; 543 544 static const unsigned short timedia_dual_port[] = { 545 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 546 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 547 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 548 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 549 0xD079, 0 550 }; 551 552 static const unsigned short timedia_quad_port[] = { 553 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 554 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 555 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 556 0xB157, 0 557 }; 558 559 static const unsigned short timedia_eight_port[] = { 560 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 561 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 562 }; 563 564 static const struct timedia_struct { 565 int num; 566 const unsigned short *ids; 567 } timedia_data[] = { 568 { 1, timedia_single_port }, 569 { 2, timedia_dual_port }, 570 { 4, timedia_quad_port }, 571 { 8, timedia_eight_port } 572 }; 573 574 /* 575 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 576 * listing them individually, this driver merely grabs them all with 577 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 578 * and should be left free to be claimed by parport_serial instead. 579 */ 580 static int pci_timedia_probe(struct pci_dev *dev) 581 { 582 /* 583 * Check the third digit of the subdevice ID 584 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 585 */ 586 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 587 dev_info(&dev->dev, 588 "ignoring Timedia subdevice %04x for parport_serial\n", 589 dev->subsystem_device); 590 return -ENODEV; 591 } 592 593 return 0; 594 } 595 596 static int pci_timedia_init(struct pci_dev *dev) 597 { 598 const unsigned short *ids; 599 int i, j; 600 601 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 602 ids = timedia_data[i].ids; 603 for (j = 0; ids[j]; j++) 604 if (dev->subsystem_device == ids[j]) 605 return timedia_data[i].num; 606 } 607 return 0; 608 } 609 610 /* 611 * Timedia/SUNIX uses a mixture of BARs and offsets 612 * Ugh, this is ugly as all hell --- TYT 613 */ 614 static int 615 pci_timedia_setup(struct serial_private *priv, 616 const struct pciserial_board *board, 617 struct uart_8250_port *port, int idx) 618 { 619 unsigned int bar = 0, offset = board->first_offset; 620 621 switch (idx) { 622 case 0: 623 bar = 0; 624 break; 625 case 1: 626 offset = board->uart_offset; 627 bar = 0; 628 break; 629 case 2: 630 bar = 1; 631 break; 632 case 3: 633 offset = board->uart_offset; 634 fallthrough; 635 case 4: /* BAR 2 */ 636 case 5: /* BAR 3 */ 637 case 6: /* BAR 4 */ 638 case 7: /* BAR 5 */ 639 bar = idx - 2; 640 } 641 642 return setup_port(priv, port, bar, offset, board->reg_shift); 643 } 644 645 /* 646 * Some Titan cards are also a little weird 647 */ 648 static int 649 titan_400l_800l_setup(struct serial_private *priv, 650 const struct pciserial_board *board, 651 struct uart_8250_port *port, int idx) 652 { 653 unsigned int bar, offset = board->first_offset; 654 655 switch (idx) { 656 case 0: 657 bar = 1; 658 break; 659 case 1: 660 bar = 2; 661 break; 662 default: 663 bar = 4; 664 offset = (idx - 2) * board->uart_offset; 665 } 666 667 return setup_port(priv, port, bar, offset, board->reg_shift); 668 } 669 670 static int pci_xircom_init(struct pci_dev *dev) 671 { 672 msleep(100); 673 return 0; 674 } 675 676 static int pci_ni8420_init(struct pci_dev *dev) 677 { 678 void __iomem *p; 679 unsigned int bar = 0; 680 681 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 682 moan_device("no memory in bar", dev); 683 return 0; 684 } 685 686 p = pci_ioremap_bar(dev, bar); 687 if (p == NULL) 688 return -ENOMEM; 689 690 /* Enable CPU Interrupt */ 691 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 692 p + NI8420_INT_ENABLE_REG); 693 694 iounmap(p); 695 return 0; 696 } 697 698 #define MITE_IOWBSR1_WSIZE 0xa 699 #define MITE_IOWBSR1_WIN_OFFSET 0x800 700 #define MITE_IOWBSR1_WENAB (1 << 7) 701 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 702 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 703 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 704 705 static int pci_ni8430_init(struct pci_dev *dev) 706 { 707 void __iomem *p; 708 struct pci_bus_region region; 709 u32 device_window; 710 unsigned int bar = 0; 711 712 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 713 moan_device("no memory in bar", dev); 714 return 0; 715 } 716 717 p = pci_ioremap_bar(dev, bar); 718 if (p == NULL) 719 return -ENOMEM; 720 721 /* 722 * Set device window address and size in BAR0, while acknowledging that 723 * the resource structure may contain a translated address that differs 724 * from the address the device responds to. 725 */ 726 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 727 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 728 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 729 writel(device_window, p + MITE_IOWBSR1); 730 731 /* Set window access to go to RAMSEL IO address space */ 732 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 733 p + MITE_IOWCR1); 734 735 /* Enable IO Bus Interrupt 0 */ 736 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 737 738 /* Enable CPU Interrupt */ 739 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 740 741 iounmap(p); 742 return 0; 743 } 744 745 /* UART Port Control Register */ 746 #define NI8430_PORTCON 0x0f 747 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 748 749 static int 750 pci_ni8430_setup(struct serial_private *priv, 751 const struct pciserial_board *board, 752 struct uart_8250_port *port, int idx) 753 { 754 struct pci_dev *dev = priv->dev; 755 void __iomem *p; 756 unsigned int bar, offset = board->first_offset; 757 758 if (idx >= board->num_ports) 759 return 1; 760 761 bar = FL_GET_BASE(board->flags); 762 offset += idx * board->uart_offset; 763 764 p = pci_ioremap_bar(dev, bar); 765 if (!p) 766 return -ENOMEM; 767 768 /* enable the transceiver */ 769 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 770 p + offset + NI8430_PORTCON); 771 772 iounmap(p); 773 774 return setup_port(priv, port, bar, offset, board->reg_shift); 775 } 776 777 static int pci_netmos_9900_setup(struct serial_private *priv, 778 const struct pciserial_board *board, 779 struct uart_8250_port *port, int idx) 780 { 781 unsigned int bar; 782 783 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 784 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 785 /* netmos apparently orders BARs by datasheet layout, so serial 786 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 787 */ 788 bar = 3 * idx; 789 790 return setup_port(priv, port, bar, 0, board->reg_shift); 791 } else { 792 return pci_default_setup(priv, board, port, idx); 793 } 794 } 795 796 /* the 99xx series comes with a range of device IDs and a variety 797 * of capabilities: 798 * 799 * 9900 has varying capabilities and can cascade to sub-controllers 800 * (cascading should be purely internal) 801 * 9904 is hardwired with 4 serial ports 802 * 9912 and 9922 are hardwired with 2 serial ports 803 */ 804 static int pci_netmos_9900_numports(struct pci_dev *dev) 805 { 806 unsigned int c = dev->class; 807 unsigned int pi; 808 unsigned short sub_serports; 809 810 pi = c & 0xff; 811 812 if (pi == 2) 813 return 1; 814 815 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 816 /* two possibilities: 0x30ps encodes number of parallel and 817 * serial ports, or 0x1000 indicates *something*. This is not 818 * immediately obvious, since the 2s1p+4s configuration seems 819 * to offer all functionality on functions 0..2, while still 820 * advertising the same function 3 as the 4s+2s1p config. 821 */ 822 sub_serports = dev->subsystem_device & 0xf; 823 if (sub_serports > 0) 824 return sub_serports; 825 826 dev_err(&dev->dev, 827 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 828 return 0; 829 } 830 831 moan_device("unknown NetMos/Mostech program interface", dev); 832 return 0; 833 } 834 835 static int pci_netmos_init(struct pci_dev *dev) 836 { 837 /* subdevice 0x00PS means <P> parallel, <S> serial */ 838 unsigned int num_serial = dev->subsystem_device & 0xf; 839 840 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 841 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 842 return 0; 843 844 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 845 dev->subsystem_device == 0x0299) 846 return 0; 847 848 switch (dev->device) { /* FALLTHROUGH on all */ 849 case PCI_DEVICE_ID_NETMOS_9904: 850 case PCI_DEVICE_ID_NETMOS_9912: 851 case PCI_DEVICE_ID_NETMOS_9922: 852 case PCI_DEVICE_ID_NETMOS_9900: 853 num_serial = pci_netmos_9900_numports(dev); 854 break; 855 856 default: 857 break; 858 } 859 860 if (num_serial == 0) { 861 moan_device("unknown NetMos/Mostech device", dev); 862 return -ENODEV; 863 } 864 865 return num_serial; 866 } 867 868 /* 869 * These chips are available with optionally one parallel port and up to 870 * two serial ports. Unfortunately they all have the same product id. 871 * 872 * Basic configuration is done over a region of 32 I/O ports. The base 873 * ioport is called INTA or INTC, depending on docs/other drivers. 874 * 875 * The region of the 32 I/O ports is configured in POSIO0R... 876 */ 877 878 /* registers */ 879 #define ITE_887x_MISCR 0x9c 880 #define ITE_887x_INTCBAR 0x78 881 #define ITE_887x_UARTBAR 0x7c 882 #define ITE_887x_PS0BAR 0x10 883 #define ITE_887x_POSIO0 0x60 884 885 /* I/O space size */ 886 #define ITE_887x_IOSIZE 32 887 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 888 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 889 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 890 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 891 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 892 #define ITE_887x_POSIO_SPEED (3 << 29) 893 /* enable IO_Space bit */ 894 #define ITE_887x_POSIO_ENABLE (1 << 31) 895 896 static int pci_ite887x_init(struct pci_dev *dev) 897 { 898 /* inta_addr are the configuration addresses of the ITE */ 899 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 900 0x200, 0x280, 0 }; 901 int ret, i, type; 902 struct resource *iobase = NULL; 903 u32 miscr, uartbar, ioport; 904 905 /* search for the base-ioport */ 906 i = 0; 907 while (inta_addr[i] && iobase == NULL) { 908 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 909 "ite887x"); 910 if (iobase != NULL) { 911 /* write POSIO0R - speed | size | ioport */ 912 pci_write_config_dword(dev, ITE_887x_POSIO0, 913 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 914 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 915 /* write INTCBAR - ioport */ 916 pci_write_config_dword(dev, ITE_887x_INTCBAR, 917 inta_addr[i]); 918 ret = inb(inta_addr[i]); 919 if (ret != 0xff) { 920 /* ioport connected */ 921 break; 922 } 923 release_region(iobase->start, ITE_887x_IOSIZE); 924 iobase = NULL; 925 } 926 i++; 927 } 928 929 if (!inta_addr[i]) { 930 dev_err(&dev->dev, "ite887x: could not find iobase\n"); 931 return -ENODEV; 932 } 933 934 /* start of undocumented type checking (see parport_pc.c) */ 935 type = inb(iobase->start + 0x18) & 0x0f; 936 937 switch (type) { 938 case 0x2: /* ITE8871 (1P) */ 939 case 0xa: /* ITE8875 (1P) */ 940 ret = 0; 941 break; 942 case 0xe: /* ITE8872 (2S1P) */ 943 ret = 2; 944 break; 945 case 0x6: /* ITE8873 (1S) */ 946 ret = 1; 947 break; 948 case 0x8: /* ITE8874 (2S) */ 949 ret = 2; 950 break; 951 default: 952 moan_device("Unknown ITE887x", dev); 953 ret = -ENODEV; 954 } 955 956 /* configure all serial ports */ 957 for (i = 0; i < ret; i++) { 958 /* read the I/O port from the device */ 959 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 960 &ioport); 961 ioport &= 0x0000FF00; /* the actual base address */ 962 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 963 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 964 ITE_887x_POSIO_IOSIZE_8 | ioport); 965 966 /* write the ioport to the UARTBAR */ 967 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 968 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 969 uartbar |= (ioport << (16 * i)); /* set the ioport */ 970 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 971 972 /* get current config */ 973 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 974 /* disable interrupts (UARTx_Routing[3:0]) */ 975 miscr &= ~(0xf << (12 - 4 * i)); 976 /* activate the UART (UARTx_En) */ 977 miscr |= 1 << (23 - i); 978 /* write new config with activated UART */ 979 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 980 } 981 982 if (ret <= 0) { 983 /* the device has no UARTs if we get here */ 984 release_region(iobase->start, ITE_887x_IOSIZE); 985 } 986 987 return ret; 988 } 989 990 static void pci_ite887x_exit(struct pci_dev *dev) 991 { 992 u32 ioport; 993 /* the ioport is bit 0-15 in POSIO0R */ 994 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 995 ioport &= 0xffff; 996 release_region(ioport, ITE_887x_IOSIZE); 997 } 998 999 /* 1000 * EndRun Technologies. 1001 * Determine the number of ports available on the device. 1002 */ 1003 #define PCI_VENDOR_ID_ENDRUN 0x7401 1004 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1005 1006 static int pci_endrun_init(struct pci_dev *dev) 1007 { 1008 u8 __iomem *p; 1009 unsigned long deviceID; 1010 unsigned int number_uarts = 0; 1011 1012 /* EndRun device is all 0xexxx */ 1013 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1014 (dev->device & 0xf000) != 0xe000) 1015 return 0; 1016 1017 p = pci_iomap(dev, 0, 5); 1018 if (p == NULL) 1019 return -ENOMEM; 1020 1021 deviceID = ioread32(p); 1022 /* EndRun device */ 1023 if (deviceID == 0x07000200) { 1024 number_uarts = ioread8(p + 4); 1025 dev_dbg(&dev->dev, 1026 "%d ports detected on EndRun PCI Express device\n", 1027 number_uarts); 1028 } 1029 pci_iounmap(dev, p); 1030 return number_uarts; 1031 } 1032 1033 /* 1034 * Oxford Semiconductor Inc. 1035 * Check that device is part of the Tornado range of devices, then determine 1036 * the number of ports available on the device. 1037 */ 1038 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1039 { 1040 u8 __iomem *p; 1041 unsigned long deviceID; 1042 unsigned int number_uarts = 0; 1043 1044 /* OxSemi Tornado devices are all 0xCxxx */ 1045 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1046 (dev->device & 0xF000) != 0xC000) 1047 return 0; 1048 1049 p = pci_iomap(dev, 0, 5); 1050 if (p == NULL) 1051 return -ENOMEM; 1052 1053 deviceID = ioread32(p); 1054 /* Tornado device */ 1055 if (deviceID == 0x07000200) { 1056 number_uarts = ioread8(p + 4); 1057 dev_dbg(&dev->dev, 1058 "%d ports detected on Oxford PCI Express device\n", 1059 number_uarts); 1060 } 1061 pci_iounmap(dev, p); 1062 return number_uarts; 1063 } 1064 1065 static int pci_asix_setup(struct serial_private *priv, 1066 const struct pciserial_board *board, 1067 struct uart_8250_port *port, int idx) 1068 { 1069 port->bugs |= UART_BUG_PARITY; 1070 return pci_default_setup(priv, board, port, idx); 1071 } 1072 1073 /* Quatech devices have their own extra interface features */ 1074 1075 struct quatech_feature { 1076 u16 devid; 1077 bool amcc; 1078 }; 1079 1080 #define QPCR_TEST_FOR1 0x3F 1081 #define QPCR_TEST_GET1 0x00 1082 #define QPCR_TEST_FOR2 0x40 1083 #define QPCR_TEST_GET2 0x40 1084 #define QPCR_TEST_FOR3 0x80 1085 #define QPCR_TEST_GET3 0x40 1086 #define QPCR_TEST_FOR4 0xC0 1087 #define QPCR_TEST_GET4 0x80 1088 1089 #define QOPR_CLOCK_X1 0x0000 1090 #define QOPR_CLOCK_X2 0x0001 1091 #define QOPR_CLOCK_X4 0x0002 1092 #define QOPR_CLOCK_X8 0x0003 1093 #define QOPR_CLOCK_RATE_MASK 0x0003 1094 1095 1096 static struct quatech_feature quatech_cards[] = { 1097 { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, 1098 { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, 1099 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, 1100 { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, 1101 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, 1102 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, 1103 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, 1104 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, 1105 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, 1106 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, 1107 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, 1108 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, 1109 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, 1110 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, 1111 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, 1112 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, 1113 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, 1114 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, 1115 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, 1116 { 0, } 1117 }; 1118 1119 static int pci_quatech_amcc(u16 devid) 1120 { 1121 struct quatech_feature *qf = &quatech_cards[0]; 1122 while (qf->devid) { 1123 if (qf->devid == devid) 1124 return qf->amcc; 1125 qf++; 1126 } 1127 pr_err("quatech: unknown port type '0x%04X'.\n", devid); 1128 return 0; 1129 }; 1130 1131 static int pci_quatech_rqopr(struct uart_8250_port *port) 1132 { 1133 unsigned long base = port->port.iobase; 1134 u8 LCR, val; 1135 1136 LCR = inb(base + UART_LCR); 1137 outb(0xBF, base + UART_LCR); 1138 val = inb(base + UART_SCR); 1139 outb(LCR, base + UART_LCR); 1140 return val; 1141 } 1142 1143 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1144 { 1145 unsigned long base = port->port.iobase; 1146 u8 LCR; 1147 1148 LCR = inb(base + UART_LCR); 1149 outb(0xBF, base + UART_LCR); 1150 inb(base + UART_SCR); 1151 outb(qopr, base + UART_SCR); 1152 outb(LCR, base + UART_LCR); 1153 } 1154 1155 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1156 { 1157 unsigned long base = port->port.iobase; 1158 u8 LCR, val, qmcr; 1159 1160 LCR = inb(base + UART_LCR); 1161 outb(0xBF, base + UART_LCR); 1162 val = inb(base + UART_SCR); 1163 outb(val | 0x10, base + UART_SCR); 1164 qmcr = inb(base + UART_MCR); 1165 outb(val, base + UART_SCR); 1166 outb(LCR, base + UART_LCR); 1167 1168 return qmcr; 1169 } 1170 1171 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1172 { 1173 unsigned long base = port->port.iobase; 1174 u8 LCR, val; 1175 1176 LCR = inb(base + UART_LCR); 1177 outb(0xBF, base + UART_LCR); 1178 val = inb(base + UART_SCR); 1179 outb(val | 0x10, base + UART_SCR); 1180 outb(qmcr, base + UART_MCR); 1181 outb(val, base + UART_SCR); 1182 outb(LCR, base + UART_LCR); 1183 } 1184 1185 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1186 { 1187 unsigned long base = port->port.iobase; 1188 u8 LCR, val; 1189 1190 LCR = inb(base + UART_LCR); 1191 outb(0xBF, base + UART_LCR); 1192 val = inb(base + UART_SCR); 1193 if (val & 0x20) { 1194 outb(0x80, UART_LCR); 1195 if (!(inb(UART_SCR) & 0x20)) { 1196 outb(LCR, base + UART_LCR); 1197 return 1; 1198 } 1199 } 1200 return 0; 1201 } 1202 1203 static int pci_quatech_test(struct uart_8250_port *port) 1204 { 1205 u8 reg, qopr; 1206 1207 qopr = pci_quatech_rqopr(port); 1208 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1209 reg = pci_quatech_rqopr(port) & 0xC0; 1210 if (reg != QPCR_TEST_GET1) 1211 return -EINVAL; 1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1213 reg = pci_quatech_rqopr(port) & 0xC0; 1214 if (reg != QPCR_TEST_GET2) 1215 return -EINVAL; 1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1217 reg = pci_quatech_rqopr(port) & 0xC0; 1218 if (reg != QPCR_TEST_GET3) 1219 return -EINVAL; 1220 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1221 reg = pci_quatech_rqopr(port) & 0xC0; 1222 if (reg != QPCR_TEST_GET4) 1223 return -EINVAL; 1224 1225 pci_quatech_wqopr(port, qopr); 1226 return 0; 1227 } 1228 1229 static int pci_quatech_clock(struct uart_8250_port *port) 1230 { 1231 u8 qopr, reg, set; 1232 unsigned long clock; 1233 1234 if (pci_quatech_test(port) < 0) 1235 return 1843200; 1236 1237 qopr = pci_quatech_rqopr(port); 1238 1239 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1240 reg = pci_quatech_rqopr(port); 1241 if (reg & QOPR_CLOCK_X8) { 1242 clock = 1843200; 1243 goto out; 1244 } 1245 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1246 reg = pci_quatech_rqopr(port); 1247 if (!(reg & QOPR_CLOCK_X8)) { 1248 clock = 1843200; 1249 goto out; 1250 } 1251 reg &= QOPR_CLOCK_X8; 1252 if (reg == QOPR_CLOCK_X2) { 1253 clock = 3685400; 1254 set = QOPR_CLOCK_X2; 1255 } else if (reg == QOPR_CLOCK_X4) { 1256 clock = 7372800; 1257 set = QOPR_CLOCK_X4; 1258 } else if (reg == QOPR_CLOCK_X8) { 1259 clock = 14745600; 1260 set = QOPR_CLOCK_X8; 1261 } else { 1262 clock = 1843200; 1263 set = QOPR_CLOCK_X1; 1264 } 1265 qopr &= ~QOPR_CLOCK_RATE_MASK; 1266 qopr |= set; 1267 1268 out: 1269 pci_quatech_wqopr(port, qopr); 1270 return clock; 1271 } 1272 1273 static int pci_quatech_rs422(struct uart_8250_port *port) 1274 { 1275 u8 qmcr; 1276 int rs422 = 0; 1277 1278 if (!pci_quatech_has_qmcr(port)) 1279 return 0; 1280 qmcr = pci_quatech_rqmcr(port); 1281 pci_quatech_wqmcr(port, 0xFF); 1282 if (pci_quatech_rqmcr(port)) 1283 rs422 = 1; 1284 pci_quatech_wqmcr(port, qmcr); 1285 return rs422; 1286 } 1287 1288 static int pci_quatech_init(struct pci_dev *dev) 1289 { 1290 if (pci_quatech_amcc(dev->device)) { 1291 unsigned long base = pci_resource_start(dev, 0); 1292 if (base) { 1293 u32 tmp; 1294 1295 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1296 tmp = inl(base + 0x3c); 1297 outl(tmp | 0x01000000, base + 0x3c); 1298 outl(tmp &= ~0x01000000, base + 0x3c); 1299 } 1300 } 1301 return 0; 1302 } 1303 1304 static int pci_quatech_setup(struct serial_private *priv, 1305 const struct pciserial_board *board, 1306 struct uart_8250_port *port, int idx) 1307 { 1308 /* Needed by pci_quatech calls below */ 1309 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1310 /* Set up the clocking */ 1311 port->port.uartclk = pci_quatech_clock(port); 1312 /* For now just warn about RS422 */ 1313 if (pci_quatech_rs422(port)) 1314 pr_warn("quatech: software control of RS422 features not currently supported.\n"); 1315 return pci_default_setup(priv, board, port, idx); 1316 } 1317 1318 static void pci_quatech_exit(struct pci_dev *dev) 1319 { 1320 } 1321 1322 static int pci_default_setup(struct serial_private *priv, 1323 const struct pciserial_board *board, 1324 struct uart_8250_port *port, int idx) 1325 { 1326 unsigned int bar, offset = board->first_offset, maxnr; 1327 1328 bar = FL_GET_BASE(board->flags); 1329 if (board->flags & FL_BASE_BARS) 1330 bar += idx; 1331 else 1332 offset += idx * board->uart_offset; 1333 1334 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1335 (board->reg_shift + 3); 1336 1337 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1338 return 1; 1339 1340 return setup_port(priv, port, bar, offset, board->reg_shift); 1341 } 1342 static void 1343 pericom_do_set_divisor(struct uart_port *port, unsigned int baud, 1344 unsigned int quot, unsigned int quot_frac) 1345 { 1346 int scr; 1347 int lcr; 1348 int actual_baud; 1349 int tolerance; 1350 1351 for (scr = 5 ; scr <= 15 ; scr++) { 1352 actual_baud = 921600 * 16 / scr; 1353 tolerance = actual_baud / 50; 1354 1355 if ((baud < actual_baud + tolerance) && 1356 (baud > actual_baud - tolerance)) { 1357 1358 lcr = serial_port_in(port, UART_LCR); 1359 serial_port_out(port, UART_LCR, lcr | 0x80); 1360 1361 serial_port_out(port, UART_DLL, 1); 1362 serial_port_out(port, UART_DLM, 0); 1363 serial_port_out(port, 2, 16 - scr); 1364 serial_port_out(port, UART_LCR, lcr); 1365 return; 1366 } else if (baud > actual_baud) { 1367 break; 1368 } 1369 } 1370 serial8250_do_set_divisor(port, baud, quot, quot_frac); 1371 } 1372 static int pci_pericom_setup(struct serial_private *priv, 1373 const struct pciserial_board *board, 1374 struct uart_8250_port *port, int idx) 1375 { 1376 unsigned int bar, offset = board->first_offset, maxnr; 1377 1378 bar = FL_GET_BASE(board->flags); 1379 if (board->flags & FL_BASE_BARS) 1380 bar += idx; 1381 else 1382 offset += idx * board->uart_offset; 1383 1384 1385 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1386 (board->reg_shift + 3); 1387 1388 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1389 return 1; 1390 1391 port->port.set_divisor = pericom_do_set_divisor; 1392 1393 return setup_port(priv, port, bar, offset, board->reg_shift); 1394 } 1395 1396 static int pci_pericom_setup_four_at_eight(struct serial_private *priv, 1397 const struct pciserial_board *board, 1398 struct uart_8250_port *port, int idx) 1399 { 1400 unsigned int bar, offset = board->first_offset, maxnr; 1401 1402 bar = FL_GET_BASE(board->flags); 1403 if (board->flags & FL_BASE_BARS) 1404 bar += idx; 1405 else 1406 offset += idx * board->uart_offset; 1407 1408 if (idx==3) 1409 offset = 0x38; 1410 1411 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1412 (board->reg_shift + 3); 1413 1414 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1415 return 1; 1416 1417 port->port.set_divisor = pericom_do_set_divisor; 1418 1419 return setup_port(priv, port, bar, offset, board->reg_shift); 1420 } 1421 1422 static int 1423 ce4100_serial_setup(struct serial_private *priv, 1424 const struct pciserial_board *board, 1425 struct uart_8250_port *port, int idx) 1426 { 1427 int ret; 1428 1429 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1430 port->port.iotype = UPIO_MEM32; 1431 port->port.type = PORT_XSCALE; 1432 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1433 port->port.regshift = 2; 1434 1435 return ret; 1436 } 1437 1438 static int 1439 pci_omegapci_setup(struct serial_private *priv, 1440 const struct pciserial_board *board, 1441 struct uart_8250_port *port, int idx) 1442 { 1443 return setup_port(priv, port, 2, idx * 8, 0); 1444 } 1445 1446 static int 1447 pci_brcm_trumanage_setup(struct serial_private *priv, 1448 const struct pciserial_board *board, 1449 struct uart_8250_port *port, int idx) 1450 { 1451 int ret = pci_default_setup(priv, board, port, idx); 1452 1453 port->port.type = PORT_BRCM_TRUMANAGE; 1454 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1455 return ret; 1456 } 1457 1458 /* RTS will control by MCR if this bit is 0 */ 1459 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1460 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1461 #define FINTEK_RTS_INVERT BIT(5) 1462 1463 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1464 static int pci_fintek_rs485_config(struct uart_port *port, 1465 struct serial_rs485 *rs485) 1466 { 1467 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1468 u8 setting; 1469 u8 *index = (u8 *) port->private_data; 1470 1471 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1472 1473 if (!rs485) 1474 rs485 = &port->rs485; 1475 else if (rs485->flags & SER_RS485_ENABLED) 1476 memset(rs485->padding, 0, sizeof(rs485->padding)); 1477 else 1478 memset(rs485, 0, sizeof(*rs485)); 1479 1480 /* F81504/508/512 not support RTS delay before or after send */ 1481 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; 1482 1483 if (rs485->flags & SER_RS485_ENABLED) { 1484 /* Enable RTS H/W control mode */ 1485 setting |= FINTEK_RTS_CONTROL_BY_HW; 1486 1487 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1488 /* RTS driving high on TX */ 1489 setting &= ~FINTEK_RTS_INVERT; 1490 } else { 1491 /* RTS driving low on TX */ 1492 setting |= FINTEK_RTS_INVERT; 1493 } 1494 1495 rs485->delay_rts_after_send = 0; 1496 rs485->delay_rts_before_send = 0; 1497 } else { 1498 /* Disable RTS H/W control mode */ 1499 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1500 } 1501 1502 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1503 1504 if (rs485 != &port->rs485) 1505 port->rs485 = *rs485; 1506 1507 return 0; 1508 } 1509 1510 static int pci_fintek_setup(struct serial_private *priv, 1511 const struct pciserial_board *board, 1512 struct uart_8250_port *port, int idx) 1513 { 1514 struct pci_dev *pdev = priv->dev; 1515 u8 *data; 1516 u8 config_base; 1517 u16 iobase; 1518 1519 config_base = 0x40 + 0x08 * idx; 1520 1521 /* Get the io address from configuration space */ 1522 pci_read_config_word(pdev, config_base + 4, &iobase); 1523 1524 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); 1525 1526 port->port.iotype = UPIO_PORT; 1527 port->port.iobase = iobase; 1528 port->port.rs485_config = pci_fintek_rs485_config; 1529 1530 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1531 if (!data) 1532 return -ENOMEM; 1533 1534 /* preserve index in PCI configuration space */ 1535 *data = idx; 1536 port->port.private_data = data; 1537 1538 return 0; 1539 } 1540 1541 static int pci_fintek_init(struct pci_dev *dev) 1542 { 1543 unsigned long iobase; 1544 u32 max_port, i; 1545 resource_size_t bar_data[3]; 1546 u8 config_base; 1547 struct serial_private *priv = pci_get_drvdata(dev); 1548 struct uart_8250_port *port; 1549 1550 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1551 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1552 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1553 return -ENODEV; 1554 1555 switch (dev->device) { 1556 case 0x1104: /* 4 ports */ 1557 case 0x1108: /* 8 ports */ 1558 max_port = dev->device & 0xff; 1559 break; 1560 case 0x1112: /* 12 ports */ 1561 max_port = 12; 1562 break; 1563 default: 1564 return -EINVAL; 1565 } 1566 1567 /* Get the io address dispatch from the BIOS */ 1568 bar_data[0] = pci_resource_start(dev, 5); 1569 bar_data[1] = pci_resource_start(dev, 4); 1570 bar_data[2] = pci_resource_start(dev, 3); 1571 1572 for (i = 0; i < max_port; ++i) { 1573 /* UART0 configuration offset start from 0x40 */ 1574 config_base = 0x40 + 0x08 * i; 1575 1576 /* Calculate Real IO Port */ 1577 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1578 1579 /* Enable UART I/O port */ 1580 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1581 1582 /* Select 128-byte FIFO and 8x FIFO threshold */ 1583 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1584 1585 /* LSB UART */ 1586 pci_write_config_byte(dev, config_base + 0x04, 1587 (u8)(iobase & 0xff)); 1588 1589 /* MSB UART */ 1590 pci_write_config_byte(dev, config_base + 0x05, 1591 (u8)((iobase & 0xff00) >> 8)); 1592 1593 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1594 1595 if (priv) { 1596 /* re-apply RS232/485 mode when 1597 * pciserial_resume_ports() 1598 */ 1599 port = serial8250_get_port(priv->line[i]); 1600 pci_fintek_rs485_config(&port->port, NULL); 1601 } else { 1602 /* First init without port data 1603 * force init to RS232 Mode 1604 */ 1605 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1606 } 1607 } 1608 1609 return max_port; 1610 } 1611 1612 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value) 1613 { 1614 struct f815xxa_data *data = p->private_data; 1615 unsigned long flags; 1616 1617 spin_lock_irqsave(&data->lock, flags); 1618 writeb(value, p->membase + offset); 1619 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1620 spin_unlock_irqrestore(&data->lock, flags); 1621 } 1622 1623 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1624 const struct pciserial_board *board, 1625 struct uart_8250_port *port, int idx) 1626 { 1627 struct pci_dev *pdev = priv->dev; 1628 struct f815xxa_data *data; 1629 1630 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1631 if (!data) 1632 return -ENOMEM; 1633 1634 data->idx = idx; 1635 spin_lock_init(&data->lock); 1636 1637 port->port.private_data = data; 1638 port->port.iotype = UPIO_MEM; 1639 port->port.flags |= UPF_IOREMAP; 1640 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1641 port->port.serial_out = f815xxa_mem_serial_out; 1642 1643 return 0; 1644 } 1645 1646 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1647 { 1648 u32 max_port, i; 1649 int config_base; 1650 1651 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1652 return -ENODEV; 1653 1654 switch (dev->device) { 1655 case 0x1204: /* 4 ports */ 1656 case 0x1208: /* 8 ports */ 1657 max_port = dev->device & 0xff; 1658 break; 1659 case 0x1212: /* 12 ports */ 1660 max_port = 12; 1661 break; 1662 default: 1663 return -EINVAL; 1664 } 1665 1666 /* Set to mmio decode */ 1667 pci_write_config_byte(dev, 0x209, 0x40); 1668 1669 for (i = 0; i < max_port; ++i) { 1670 /* UART0 configuration offset start from 0x2A0 */ 1671 config_base = 0x2A0 + 0x08 * i; 1672 1673 /* Select 128-byte FIFO and 8x FIFO threshold */ 1674 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1675 1676 /* Enable UART I/O port */ 1677 pci_write_config_byte(dev, config_base + 0, 0x01); 1678 } 1679 1680 return max_port; 1681 } 1682 1683 static int skip_tx_en_setup(struct serial_private *priv, 1684 const struct pciserial_board *board, 1685 struct uart_8250_port *port, int idx) 1686 { 1687 port->port.quirks |= UPQ_NO_TXEN_TEST; 1688 dev_dbg(&priv->dev->dev, 1689 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1690 priv->dev->vendor, priv->dev->device, 1691 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1692 1693 return pci_default_setup(priv, board, port, idx); 1694 } 1695 1696 static void kt_handle_break(struct uart_port *p) 1697 { 1698 struct uart_8250_port *up = up_to_u8250p(p); 1699 /* 1700 * On receipt of a BI, serial device in Intel ME (Intel 1701 * management engine) needs to have its fifos cleared for sane 1702 * SOL (Serial Over Lan) output. 1703 */ 1704 serial8250_clear_and_reinit_fifos(up); 1705 } 1706 1707 static unsigned int kt_serial_in(struct uart_port *p, int offset) 1708 { 1709 struct uart_8250_port *up = up_to_u8250p(p); 1710 unsigned int val; 1711 1712 /* 1713 * When the Intel ME (management engine) gets reset its serial 1714 * port registers could return 0 momentarily. Functions like 1715 * serial8250_console_write, read and save the IER, perform 1716 * some operation and then restore it. In order to avoid 1717 * setting IER register inadvertently to 0, if the value read 1718 * is 0, double check with ier value in uart_8250_port and use 1719 * that instead. up->ier should be the same value as what is 1720 * currently configured. 1721 */ 1722 val = inb(p->iobase + offset); 1723 if (offset == UART_IER) { 1724 if (val == 0) 1725 val = up->ier; 1726 } 1727 return val; 1728 } 1729 1730 static int kt_serial_setup(struct serial_private *priv, 1731 const struct pciserial_board *board, 1732 struct uart_8250_port *port, int idx) 1733 { 1734 port->port.flags |= UPF_BUG_THRE; 1735 port->port.serial_in = kt_serial_in; 1736 port->port.handle_break = kt_handle_break; 1737 return skip_tx_en_setup(priv, board, port, idx); 1738 } 1739 1740 static int pci_eg20t_init(struct pci_dev *dev) 1741 { 1742 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1743 return -ENODEV; 1744 #else 1745 return 0; 1746 #endif 1747 } 1748 1749 static int 1750 pci_wch_ch353_setup(struct serial_private *priv, 1751 const struct pciserial_board *board, 1752 struct uart_8250_port *port, int idx) 1753 { 1754 port->port.flags |= UPF_FIXED_TYPE; 1755 port->port.type = PORT_16550A; 1756 return pci_default_setup(priv, board, port, idx); 1757 } 1758 1759 static int 1760 pci_wch_ch355_setup(struct serial_private *priv, 1761 const struct pciserial_board *board, 1762 struct uart_8250_port *port, int idx) 1763 { 1764 port->port.flags |= UPF_FIXED_TYPE; 1765 port->port.type = PORT_16550A; 1766 return pci_default_setup(priv, board, port, idx); 1767 } 1768 1769 static int 1770 pci_wch_ch38x_setup(struct serial_private *priv, 1771 const struct pciserial_board *board, 1772 struct uart_8250_port *port, int idx) 1773 { 1774 port->port.flags |= UPF_FIXED_TYPE; 1775 port->port.type = PORT_16850; 1776 return pci_default_setup(priv, board, port, idx); 1777 } 1778 1779 1780 #define CH384_XINT_ENABLE_REG 0xEB 1781 #define CH384_XINT_ENABLE_BIT 0x02 1782 1783 static int pci_wch_ch38x_init(struct pci_dev *dev) 1784 { 1785 int max_port; 1786 unsigned long iobase; 1787 1788 1789 switch (dev->device) { 1790 case 0x3853: /* 8 ports */ 1791 max_port = 8; 1792 break; 1793 default: 1794 return -EINVAL; 1795 } 1796 1797 iobase = pci_resource_start(dev, 0); 1798 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1799 1800 return max_port; 1801 } 1802 1803 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1804 { 1805 unsigned long iobase; 1806 1807 iobase = pci_resource_start(dev, 0); 1808 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1809 } 1810 1811 1812 static int 1813 pci_sunix_setup(struct serial_private *priv, 1814 const struct pciserial_board *board, 1815 struct uart_8250_port *port, int idx) 1816 { 1817 int bar; 1818 int offset; 1819 1820 port->port.flags |= UPF_FIXED_TYPE; 1821 port->port.type = PORT_SUNIX; 1822 1823 if (idx < 4) { 1824 bar = 0; 1825 offset = idx * board->uart_offset; 1826 } else { 1827 bar = 1; 1828 idx -= 4; 1829 idx = div_s64_rem(idx, 4, &offset); 1830 offset = idx * 64 + offset * board->uart_offset; 1831 } 1832 1833 return setup_port(priv, port, bar, offset, 0); 1834 } 1835 1836 static int 1837 pci_moxa_setup(struct serial_private *priv, 1838 const struct pciserial_board *board, 1839 struct uart_8250_port *port, int idx) 1840 { 1841 unsigned int bar = FL_GET_BASE(board->flags); 1842 int offset; 1843 1844 if (board->num_ports == 4 && idx == 3) 1845 offset = 7 * board->uart_offset; 1846 else 1847 offset = idx * board->uart_offset; 1848 1849 return setup_port(priv, port, bar, offset, 0); 1850 } 1851 1852 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 1853 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 1854 #define PCI_DEVICE_ID_OCTPRO 0x0001 1855 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 1856 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 1857 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 1858 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 1859 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 1860 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 1861 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 1862 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 1863 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 1864 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 1865 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 1866 #define PCI_DEVICE_ID_TITAN_200I 0x8028 1867 #define PCI_DEVICE_ID_TITAN_400I 0x8048 1868 #define PCI_DEVICE_ID_TITAN_800I 0x8088 1869 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 1870 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 1871 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 1872 #define PCI_DEVICE_ID_TITAN_100E 0xA010 1873 #define PCI_DEVICE_ID_TITAN_200E 0xA012 1874 #define PCI_DEVICE_ID_TITAN_400E 0xA013 1875 #define PCI_DEVICE_ID_TITAN_800E 0xA014 1876 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 1877 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 1878 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 1879 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 1880 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 1881 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 1882 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 1883 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 1884 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 1885 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 1886 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 1887 #define PCI_VENDOR_ID_WCH 0x4348 1888 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 1889 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 1890 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 1891 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 1892 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 1893 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 1894 #define PCI_VENDOR_ID_AGESTAR 0x5372 1895 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 1896 #define PCI_VENDOR_ID_ASIX 0x9710 1897 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 1898 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 1899 1900 #define PCIE_VENDOR_ID_WCH 0x1c00 1901 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 1902 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 1903 #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 1904 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 1905 1906 #define PCI_VENDOR_ID_ACCESIO 0x494f 1907 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 1908 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 1909 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C 1910 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E 1911 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 1912 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 1913 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 1914 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B 1915 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 1916 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 1917 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA 1918 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC 1919 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 1920 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 1921 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 1922 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 1923 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 1924 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 1925 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A 1926 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 1927 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 1928 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 1929 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 1930 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 1931 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A 1932 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B 1933 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A 1934 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B 1935 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 1936 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 1937 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 1938 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 1939 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 1940 1941 1942 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 1943 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 1944 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 1945 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 1946 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 1947 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 1948 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 1949 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 1950 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 1951 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 1952 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 1953 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 1954 1955 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 1956 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 1957 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 1958 1959 /* 1960 * Master list of serial port init/setup/exit quirks. 1961 * This does not describe the general nature of the port. 1962 * (ie, baud base, number and location of ports, etc) 1963 * 1964 * This list is ordered alphabetically by vendor then device. 1965 * Specific entries must come before more generic entries. 1966 */ 1967 static struct pci_serial_quirk pci_serial_quirks[] = { 1968 /* 1969 * ADDI-DATA GmbH communication cards <info@addi-data.com> 1970 */ 1971 { 1972 .vendor = PCI_VENDOR_ID_AMCC, 1973 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 1974 .subvendor = PCI_ANY_ID, 1975 .subdevice = PCI_ANY_ID, 1976 .setup = addidata_apci7800_setup, 1977 }, 1978 /* 1979 * AFAVLAB cards - these may be called via parport_serial 1980 * It is not clear whether this applies to all products. 1981 */ 1982 { 1983 .vendor = PCI_VENDOR_ID_AFAVLAB, 1984 .device = PCI_ANY_ID, 1985 .subvendor = PCI_ANY_ID, 1986 .subdevice = PCI_ANY_ID, 1987 .setup = afavlab_setup, 1988 }, 1989 /* 1990 * HP Diva 1991 */ 1992 { 1993 .vendor = PCI_VENDOR_ID_HP, 1994 .device = PCI_DEVICE_ID_HP_DIVA, 1995 .subvendor = PCI_ANY_ID, 1996 .subdevice = PCI_ANY_ID, 1997 .init = pci_hp_diva_init, 1998 .setup = pci_hp_diva_setup, 1999 }, 2000 /* 2001 * Intel 2002 */ 2003 { 2004 .vendor = PCI_VENDOR_ID_INTEL, 2005 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2006 .subvendor = 0xe4bf, 2007 .subdevice = PCI_ANY_ID, 2008 .init = pci_inteli960ni_init, 2009 .setup = pci_default_setup, 2010 }, 2011 { 2012 .vendor = PCI_VENDOR_ID_INTEL, 2013 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2014 .subvendor = PCI_ANY_ID, 2015 .subdevice = PCI_ANY_ID, 2016 .setup = skip_tx_en_setup, 2017 }, 2018 { 2019 .vendor = PCI_VENDOR_ID_INTEL, 2020 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2021 .subvendor = PCI_ANY_ID, 2022 .subdevice = PCI_ANY_ID, 2023 .setup = skip_tx_en_setup, 2024 }, 2025 { 2026 .vendor = PCI_VENDOR_ID_INTEL, 2027 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2028 .subvendor = PCI_ANY_ID, 2029 .subdevice = PCI_ANY_ID, 2030 .setup = skip_tx_en_setup, 2031 }, 2032 { 2033 .vendor = PCI_VENDOR_ID_INTEL, 2034 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2035 .subvendor = PCI_ANY_ID, 2036 .subdevice = PCI_ANY_ID, 2037 .setup = ce4100_serial_setup, 2038 }, 2039 { 2040 .vendor = PCI_VENDOR_ID_INTEL, 2041 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2042 .subvendor = PCI_ANY_ID, 2043 .subdevice = PCI_ANY_ID, 2044 .setup = kt_serial_setup, 2045 }, 2046 /* 2047 * ITE 2048 */ 2049 { 2050 .vendor = PCI_VENDOR_ID_ITE, 2051 .device = PCI_DEVICE_ID_ITE_8872, 2052 .subvendor = PCI_ANY_ID, 2053 .subdevice = PCI_ANY_ID, 2054 .init = pci_ite887x_init, 2055 .setup = pci_default_setup, 2056 .exit = pci_ite887x_exit, 2057 }, 2058 /* 2059 * National Instruments 2060 */ 2061 { 2062 .vendor = PCI_VENDOR_ID_NI, 2063 .device = PCI_DEVICE_ID_NI_PCI23216, 2064 .subvendor = PCI_ANY_ID, 2065 .subdevice = PCI_ANY_ID, 2066 .init = pci_ni8420_init, 2067 .setup = pci_default_setup, 2068 .exit = pci_ni8420_exit, 2069 }, 2070 { 2071 .vendor = PCI_VENDOR_ID_NI, 2072 .device = PCI_DEVICE_ID_NI_PCI2328, 2073 .subvendor = PCI_ANY_ID, 2074 .subdevice = PCI_ANY_ID, 2075 .init = pci_ni8420_init, 2076 .setup = pci_default_setup, 2077 .exit = pci_ni8420_exit, 2078 }, 2079 { 2080 .vendor = PCI_VENDOR_ID_NI, 2081 .device = PCI_DEVICE_ID_NI_PCI2324, 2082 .subvendor = PCI_ANY_ID, 2083 .subdevice = PCI_ANY_ID, 2084 .init = pci_ni8420_init, 2085 .setup = pci_default_setup, 2086 .exit = pci_ni8420_exit, 2087 }, 2088 { 2089 .vendor = PCI_VENDOR_ID_NI, 2090 .device = PCI_DEVICE_ID_NI_PCI2322, 2091 .subvendor = PCI_ANY_ID, 2092 .subdevice = PCI_ANY_ID, 2093 .init = pci_ni8420_init, 2094 .setup = pci_default_setup, 2095 .exit = pci_ni8420_exit, 2096 }, 2097 { 2098 .vendor = PCI_VENDOR_ID_NI, 2099 .device = PCI_DEVICE_ID_NI_PCI2324I, 2100 .subvendor = PCI_ANY_ID, 2101 .subdevice = PCI_ANY_ID, 2102 .init = pci_ni8420_init, 2103 .setup = pci_default_setup, 2104 .exit = pci_ni8420_exit, 2105 }, 2106 { 2107 .vendor = PCI_VENDOR_ID_NI, 2108 .device = PCI_DEVICE_ID_NI_PCI2322I, 2109 .subvendor = PCI_ANY_ID, 2110 .subdevice = PCI_ANY_ID, 2111 .init = pci_ni8420_init, 2112 .setup = pci_default_setup, 2113 .exit = pci_ni8420_exit, 2114 }, 2115 { 2116 .vendor = PCI_VENDOR_ID_NI, 2117 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2118 .subvendor = PCI_ANY_ID, 2119 .subdevice = PCI_ANY_ID, 2120 .init = pci_ni8420_init, 2121 .setup = pci_default_setup, 2122 .exit = pci_ni8420_exit, 2123 }, 2124 { 2125 .vendor = PCI_VENDOR_ID_NI, 2126 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2127 .subvendor = PCI_ANY_ID, 2128 .subdevice = PCI_ANY_ID, 2129 .init = pci_ni8420_init, 2130 .setup = pci_default_setup, 2131 .exit = pci_ni8420_exit, 2132 }, 2133 { 2134 .vendor = PCI_VENDOR_ID_NI, 2135 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2136 .subvendor = PCI_ANY_ID, 2137 .subdevice = PCI_ANY_ID, 2138 .init = pci_ni8420_init, 2139 .setup = pci_default_setup, 2140 .exit = pci_ni8420_exit, 2141 }, 2142 { 2143 .vendor = PCI_VENDOR_ID_NI, 2144 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2145 .subvendor = PCI_ANY_ID, 2146 .subdevice = PCI_ANY_ID, 2147 .init = pci_ni8420_init, 2148 .setup = pci_default_setup, 2149 .exit = pci_ni8420_exit, 2150 }, 2151 { 2152 .vendor = PCI_VENDOR_ID_NI, 2153 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2154 .subvendor = PCI_ANY_ID, 2155 .subdevice = PCI_ANY_ID, 2156 .init = pci_ni8420_init, 2157 .setup = pci_default_setup, 2158 .exit = pci_ni8420_exit, 2159 }, 2160 { 2161 .vendor = PCI_VENDOR_ID_NI, 2162 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2163 .subvendor = PCI_ANY_ID, 2164 .subdevice = PCI_ANY_ID, 2165 .init = pci_ni8420_init, 2166 .setup = pci_default_setup, 2167 .exit = pci_ni8420_exit, 2168 }, 2169 { 2170 .vendor = PCI_VENDOR_ID_NI, 2171 .device = PCI_ANY_ID, 2172 .subvendor = PCI_ANY_ID, 2173 .subdevice = PCI_ANY_ID, 2174 .init = pci_ni8430_init, 2175 .setup = pci_ni8430_setup, 2176 .exit = pci_ni8430_exit, 2177 }, 2178 /* Quatech */ 2179 { 2180 .vendor = PCI_VENDOR_ID_QUATECH, 2181 .device = PCI_ANY_ID, 2182 .subvendor = PCI_ANY_ID, 2183 .subdevice = PCI_ANY_ID, 2184 .init = pci_quatech_init, 2185 .setup = pci_quatech_setup, 2186 .exit = pci_quatech_exit, 2187 }, 2188 /* 2189 * Panacom 2190 */ 2191 { 2192 .vendor = PCI_VENDOR_ID_PANACOM, 2193 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2194 .subvendor = PCI_ANY_ID, 2195 .subdevice = PCI_ANY_ID, 2196 .init = pci_plx9050_init, 2197 .setup = pci_default_setup, 2198 .exit = pci_plx9050_exit, 2199 }, 2200 { 2201 .vendor = PCI_VENDOR_ID_PANACOM, 2202 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2203 .subvendor = PCI_ANY_ID, 2204 .subdevice = PCI_ANY_ID, 2205 .init = pci_plx9050_init, 2206 .setup = pci_default_setup, 2207 .exit = pci_plx9050_exit, 2208 }, 2209 /* 2210 * Pericom (Only 7954 - It have a offset jump for port 4) 2211 */ 2212 { 2213 .vendor = PCI_VENDOR_ID_PERICOM, 2214 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, 2215 .subvendor = PCI_ANY_ID, 2216 .subdevice = PCI_ANY_ID, 2217 .setup = pci_pericom_setup_four_at_eight, 2218 }, 2219 /* 2220 * PLX 2221 */ 2222 { 2223 .vendor = PCI_VENDOR_ID_PLX, 2224 .device = PCI_DEVICE_ID_PLX_9050, 2225 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2226 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2227 .init = pci_plx9050_init, 2228 .setup = pci_default_setup, 2229 .exit = pci_plx9050_exit, 2230 }, 2231 { 2232 .vendor = PCI_VENDOR_ID_PLX, 2233 .device = PCI_DEVICE_ID_PLX_9050, 2234 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2235 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2236 .init = pci_plx9050_init, 2237 .setup = pci_default_setup, 2238 .exit = pci_plx9050_exit, 2239 }, 2240 { 2241 .vendor = PCI_VENDOR_ID_PLX, 2242 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2243 .subvendor = PCI_VENDOR_ID_PLX, 2244 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2245 .init = pci_plx9050_init, 2246 .setup = pci_default_setup, 2247 .exit = pci_plx9050_exit, 2248 }, 2249 { 2250 .vendor = PCI_VENDOR_ID_ACCESIO, 2251 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 2252 .subvendor = PCI_ANY_ID, 2253 .subdevice = PCI_ANY_ID, 2254 .setup = pci_pericom_setup_four_at_eight, 2255 }, 2256 { 2257 .vendor = PCI_VENDOR_ID_ACCESIO, 2258 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 2259 .subvendor = PCI_ANY_ID, 2260 .subdevice = PCI_ANY_ID, 2261 .setup = pci_pericom_setup_four_at_eight, 2262 }, 2263 { 2264 .vendor = PCI_VENDOR_ID_ACCESIO, 2265 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 2266 .subvendor = PCI_ANY_ID, 2267 .subdevice = PCI_ANY_ID, 2268 .setup = pci_pericom_setup_four_at_eight, 2269 }, 2270 { 2271 .vendor = PCI_VENDOR_ID_ACCESIO, 2272 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 2273 .subvendor = PCI_ANY_ID, 2274 .subdevice = PCI_ANY_ID, 2275 .setup = pci_pericom_setup_four_at_eight, 2276 }, 2277 { 2278 .vendor = PCI_VENDOR_ID_ACCESIO, 2279 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 2280 .subvendor = PCI_ANY_ID, 2281 .subdevice = PCI_ANY_ID, 2282 .setup = pci_pericom_setup_four_at_eight, 2283 }, 2284 { 2285 .vendor = PCI_VENDOR_ID_ACCESIO, 2286 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 2287 .subvendor = PCI_ANY_ID, 2288 .subdevice = PCI_ANY_ID, 2289 .setup = pci_pericom_setup_four_at_eight, 2290 }, 2291 { 2292 .vendor = PCI_VENDOR_ID_ACCESIO, 2293 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 2294 .subvendor = PCI_ANY_ID, 2295 .subdevice = PCI_ANY_ID, 2296 .setup = pci_pericom_setup_four_at_eight, 2297 }, 2298 { 2299 .vendor = PCI_VENDOR_ID_ACCESIO, 2300 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 2301 .subvendor = PCI_ANY_ID, 2302 .subdevice = PCI_ANY_ID, 2303 .setup = pci_pericom_setup_four_at_eight, 2304 }, 2305 { 2306 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 2307 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .setup = pci_pericom_setup_four_at_eight, 2311 }, 2312 { 2313 .vendor = PCI_VENDOR_ID_ACCESIO, 2314 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 2315 .subvendor = PCI_ANY_ID, 2316 .subdevice = PCI_ANY_ID, 2317 .setup = pci_pericom_setup_four_at_eight, 2318 }, 2319 { 2320 .vendor = PCI_VENDOR_ID_ACCESIO, 2321 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 2322 .subvendor = PCI_ANY_ID, 2323 .subdevice = PCI_ANY_ID, 2324 .setup = pci_pericom_setup_four_at_eight, 2325 }, 2326 { 2327 .vendor = PCI_VENDOR_ID_ACCESIO, 2328 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 2329 .subvendor = PCI_ANY_ID, 2330 .subdevice = PCI_ANY_ID, 2331 .setup = pci_pericom_setup_four_at_eight, 2332 }, 2333 { 2334 .vendor = PCI_VENDOR_ID_ACCESIO, 2335 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 2336 .subvendor = PCI_ANY_ID, 2337 .subdevice = PCI_ANY_ID, 2338 .setup = pci_pericom_setup_four_at_eight, 2339 }, 2340 { 2341 .vendor = PCI_VENDOR_ID_ACCESIO, 2342 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 2343 .subvendor = PCI_ANY_ID, 2344 .subdevice = PCI_ANY_ID, 2345 .setup = pci_pericom_setup_four_at_eight, 2346 }, 2347 { 2348 .vendor = PCI_VENDOR_ID_ACCESIO, 2349 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 2350 .subvendor = PCI_ANY_ID, 2351 .subdevice = PCI_ANY_ID, 2352 .setup = pci_pericom_setup_four_at_eight, 2353 }, 2354 { 2355 .vendor = PCI_VENDOR_ID_ACCESIO, 2356 .device = PCI_ANY_ID, 2357 .subvendor = PCI_ANY_ID, 2358 .subdevice = PCI_ANY_ID, 2359 .setup = pci_pericom_setup, 2360 }, /* 2361 * SBS Technologies, Inc., PMC-OCTALPRO 232 2362 */ 2363 { 2364 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2365 .device = PCI_DEVICE_ID_OCTPRO, 2366 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2367 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2368 .init = sbs_init, 2369 .setup = sbs_setup, 2370 .exit = sbs_exit, 2371 }, 2372 /* 2373 * SBS Technologies, Inc., PMC-OCTALPRO 422 2374 */ 2375 { 2376 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2377 .device = PCI_DEVICE_ID_OCTPRO, 2378 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2379 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2380 .init = sbs_init, 2381 .setup = sbs_setup, 2382 .exit = sbs_exit, 2383 }, 2384 /* 2385 * SBS Technologies, Inc., P-Octal 232 2386 */ 2387 { 2388 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2389 .device = PCI_DEVICE_ID_OCTPRO, 2390 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2391 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2392 .init = sbs_init, 2393 .setup = sbs_setup, 2394 .exit = sbs_exit, 2395 }, 2396 /* 2397 * SBS Technologies, Inc., P-Octal 422 2398 */ 2399 { 2400 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2401 .device = PCI_DEVICE_ID_OCTPRO, 2402 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2403 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2404 .init = sbs_init, 2405 .setup = sbs_setup, 2406 .exit = sbs_exit, 2407 }, 2408 /* 2409 * SIIG cards - these may be called via parport_serial 2410 */ 2411 { 2412 .vendor = PCI_VENDOR_ID_SIIG, 2413 .device = PCI_ANY_ID, 2414 .subvendor = PCI_ANY_ID, 2415 .subdevice = PCI_ANY_ID, 2416 .init = pci_siig_init, 2417 .setup = pci_siig_setup, 2418 }, 2419 /* 2420 * Titan cards 2421 */ 2422 { 2423 .vendor = PCI_VENDOR_ID_TITAN, 2424 .device = PCI_DEVICE_ID_TITAN_400L, 2425 .subvendor = PCI_ANY_ID, 2426 .subdevice = PCI_ANY_ID, 2427 .setup = titan_400l_800l_setup, 2428 }, 2429 { 2430 .vendor = PCI_VENDOR_ID_TITAN, 2431 .device = PCI_DEVICE_ID_TITAN_800L, 2432 .subvendor = PCI_ANY_ID, 2433 .subdevice = PCI_ANY_ID, 2434 .setup = titan_400l_800l_setup, 2435 }, 2436 /* 2437 * Timedia cards 2438 */ 2439 { 2440 .vendor = PCI_VENDOR_ID_TIMEDIA, 2441 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2442 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2443 .subdevice = PCI_ANY_ID, 2444 .probe = pci_timedia_probe, 2445 .init = pci_timedia_init, 2446 .setup = pci_timedia_setup, 2447 }, 2448 { 2449 .vendor = PCI_VENDOR_ID_TIMEDIA, 2450 .device = PCI_ANY_ID, 2451 .subvendor = PCI_ANY_ID, 2452 .subdevice = PCI_ANY_ID, 2453 .setup = pci_timedia_setup, 2454 }, 2455 /* 2456 * Sunix PCI serial boards 2457 */ 2458 { 2459 .vendor = PCI_VENDOR_ID_SUNIX, 2460 .device = PCI_DEVICE_ID_SUNIX_1999, 2461 .subvendor = PCI_VENDOR_ID_SUNIX, 2462 .subdevice = PCI_ANY_ID, 2463 .setup = pci_sunix_setup, 2464 }, 2465 /* 2466 * Xircom cards 2467 */ 2468 { 2469 .vendor = PCI_VENDOR_ID_XIRCOM, 2470 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2471 .subvendor = PCI_ANY_ID, 2472 .subdevice = PCI_ANY_ID, 2473 .init = pci_xircom_init, 2474 .setup = pci_default_setup, 2475 }, 2476 /* 2477 * Netmos cards - these may be called via parport_serial 2478 */ 2479 { 2480 .vendor = PCI_VENDOR_ID_NETMOS, 2481 .device = PCI_ANY_ID, 2482 .subvendor = PCI_ANY_ID, 2483 .subdevice = PCI_ANY_ID, 2484 .init = pci_netmos_init, 2485 .setup = pci_netmos_9900_setup, 2486 }, 2487 /* 2488 * EndRun Technologies 2489 */ 2490 { 2491 .vendor = PCI_VENDOR_ID_ENDRUN, 2492 .device = PCI_ANY_ID, 2493 .subvendor = PCI_ANY_ID, 2494 .subdevice = PCI_ANY_ID, 2495 .init = pci_endrun_init, 2496 .setup = pci_default_setup, 2497 }, 2498 /* 2499 * For Oxford Semiconductor Tornado based devices 2500 */ 2501 { 2502 .vendor = PCI_VENDOR_ID_OXSEMI, 2503 .device = PCI_ANY_ID, 2504 .subvendor = PCI_ANY_ID, 2505 .subdevice = PCI_ANY_ID, 2506 .init = pci_oxsemi_tornado_init, 2507 .setup = pci_default_setup, 2508 }, 2509 { 2510 .vendor = PCI_VENDOR_ID_MAINPINE, 2511 .device = PCI_ANY_ID, 2512 .subvendor = PCI_ANY_ID, 2513 .subdevice = PCI_ANY_ID, 2514 .init = pci_oxsemi_tornado_init, 2515 .setup = pci_default_setup, 2516 }, 2517 { 2518 .vendor = PCI_VENDOR_ID_DIGI, 2519 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2520 .subvendor = PCI_SUBVENDOR_ID_IBM, 2521 .subdevice = PCI_ANY_ID, 2522 .init = pci_oxsemi_tornado_init, 2523 .setup = pci_default_setup, 2524 }, 2525 { 2526 .vendor = PCI_VENDOR_ID_INTEL, 2527 .device = 0x8811, 2528 .subvendor = PCI_ANY_ID, 2529 .subdevice = PCI_ANY_ID, 2530 .init = pci_eg20t_init, 2531 .setup = pci_default_setup, 2532 }, 2533 { 2534 .vendor = PCI_VENDOR_ID_INTEL, 2535 .device = 0x8812, 2536 .subvendor = PCI_ANY_ID, 2537 .subdevice = PCI_ANY_ID, 2538 .init = pci_eg20t_init, 2539 .setup = pci_default_setup, 2540 }, 2541 { 2542 .vendor = PCI_VENDOR_ID_INTEL, 2543 .device = 0x8813, 2544 .subvendor = PCI_ANY_ID, 2545 .subdevice = PCI_ANY_ID, 2546 .init = pci_eg20t_init, 2547 .setup = pci_default_setup, 2548 }, 2549 { 2550 .vendor = PCI_VENDOR_ID_INTEL, 2551 .device = 0x8814, 2552 .subvendor = PCI_ANY_ID, 2553 .subdevice = PCI_ANY_ID, 2554 .init = pci_eg20t_init, 2555 .setup = pci_default_setup, 2556 }, 2557 { 2558 .vendor = 0x10DB, 2559 .device = 0x8027, 2560 .subvendor = PCI_ANY_ID, 2561 .subdevice = PCI_ANY_ID, 2562 .init = pci_eg20t_init, 2563 .setup = pci_default_setup, 2564 }, 2565 { 2566 .vendor = 0x10DB, 2567 .device = 0x8028, 2568 .subvendor = PCI_ANY_ID, 2569 .subdevice = PCI_ANY_ID, 2570 .init = pci_eg20t_init, 2571 .setup = pci_default_setup, 2572 }, 2573 { 2574 .vendor = 0x10DB, 2575 .device = 0x8029, 2576 .subvendor = PCI_ANY_ID, 2577 .subdevice = PCI_ANY_ID, 2578 .init = pci_eg20t_init, 2579 .setup = pci_default_setup, 2580 }, 2581 { 2582 .vendor = 0x10DB, 2583 .device = 0x800C, 2584 .subvendor = PCI_ANY_ID, 2585 .subdevice = PCI_ANY_ID, 2586 .init = pci_eg20t_init, 2587 .setup = pci_default_setup, 2588 }, 2589 { 2590 .vendor = 0x10DB, 2591 .device = 0x800D, 2592 .subvendor = PCI_ANY_ID, 2593 .subdevice = PCI_ANY_ID, 2594 .init = pci_eg20t_init, 2595 .setup = pci_default_setup, 2596 }, 2597 /* 2598 * Cronyx Omega PCI (PLX-chip based) 2599 */ 2600 { 2601 .vendor = PCI_VENDOR_ID_PLX, 2602 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2603 .subvendor = PCI_ANY_ID, 2604 .subdevice = PCI_ANY_ID, 2605 .setup = pci_omegapci_setup, 2606 }, 2607 /* WCH CH353 1S1P card (16550 clone) */ 2608 { 2609 .vendor = PCI_VENDOR_ID_WCH, 2610 .device = PCI_DEVICE_ID_WCH_CH353_1S1P, 2611 .subvendor = PCI_ANY_ID, 2612 .subdevice = PCI_ANY_ID, 2613 .setup = pci_wch_ch353_setup, 2614 }, 2615 /* WCH CH353 2S1P card (16550 clone) */ 2616 { 2617 .vendor = PCI_VENDOR_ID_WCH, 2618 .device = PCI_DEVICE_ID_WCH_CH353_2S1P, 2619 .subvendor = PCI_ANY_ID, 2620 .subdevice = PCI_ANY_ID, 2621 .setup = pci_wch_ch353_setup, 2622 }, 2623 /* WCH CH353 4S card (16550 clone) */ 2624 { 2625 .vendor = PCI_VENDOR_ID_WCH, 2626 .device = PCI_DEVICE_ID_WCH_CH353_4S, 2627 .subvendor = PCI_ANY_ID, 2628 .subdevice = PCI_ANY_ID, 2629 .setup = pci_wch_ch353_setup, 2630 }, 2631 /* WCH CH353 2S1PF card (16550 clone) */ 2632 { 2633 .vendor = PCI_VENDOR_ID_WCH, 2634 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, 2635 .subvendor = PCI_ANY_ID, 2636 .subdevice = PCI_ANY_ID, 2637 .setup = pci_wch_ch353_setup, 2638 }, 2639 /* WCH CH352 2S card (16550 clone) */ 2640 { 2641 .vendor = PCI_VENDOR_ID_WCH, 2642 .device = PCI_DEVICE_ID_WCH_CH352_2S, 2643 .subvendor = PCI_ANY_ID, 2644 .subdevice = PCI_ANY_ID, 2645 .setup = pci_wch_ch353_setup, 2646 }, 2647 /* WCH CH355 4S card (16550 clone) */ 2648 { 2649 .vendor = PCI_VENDOR_ID_WCH, 2650 .device = PCI_DEVICE_ID_WCH_CH355_4S, 2651 .subvendor = PCI_ANY_ID, 2652 .subdevice = PCI_ANY_ID, 2653 .setup = pci_wch_ch355_setup, 2654 }, 2655 /* WCH CH382 2S card (16850 clone) */ 2656 { 2657 .vendor = PCIE_VENDOR_ID_WCH, 2658 .device = PCIE_DEVICE_ID_WCH_CH382_2S, 2659 .subvendor = PCI_ANY_ID, 2660 .subdevice = PCI_ANY_ID, 2661 .setup = pci_wch_ch38x_setup, 2662 }, 2663 /* WCH CH382 2S1P card (16850 clone) */ 2664 { 2665 .vendor = PCIE_VENDOR_ID_WCH, 2666 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, 2667 .subvendor = PCI_ANY_ID, 2668 .subdevice = PCI_ANY_ID, 2669 .setup = pci_wch_ch38x_setup, 2670 }, 2671 /* WCH CH384 4S card (16850 clone) */ 2672 { 2673 .vendor = PCIE_VENDOR_ID_WCH, 2674 .device = PCIE_DEVICE_ID_WCH_CH384_4S, 2675 .subvendor = PCI_ANY_ID, 2676 .subdevice = PCI_ANY_ID, 2677 .setup = pci_wch_ch38x_setup, 2678 }, 2679 /* WCH CH384 8S card (16850 clone) */ 2680 { 2681 .vendor = PCIE_VENDOR_ID_WCH, 2682 .device = PCIE_DEVICE_ID_WCH_CH384_8S, 2683 .subvendor = PCI_ANY_ID, 2684 .subdevice = PCI_ANY_ID, 2685 .init = pci_wch_ch38x_init, 2686 .exit = pci_wch_ch38x_exit, 2687 .setup = pci_wch_ch38x_setup, 2688 }, 2689 /* 2690 * ASIX devices with FIFO bug 2691 */ 2692 { 2693 .vendor = PCI_VENDOR_ID_ASIX, 2694 .device = PCI_ANY_ID, 2695 .subvendor = PCI_ANY_ID, 2696 .subdevice = PCI_ANY_ID, 2697 .setup = pci_asix_setup, 2698 }, 2699 /* 2700 * Broadcom TruManage (NetXtreme) 2701 */ 2702 { 2703 .vendor = PCI_VENDOR_ID_BROADCOM, 2704 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2705 .subvendor = PCI_ANY_ID, 2706 .subdevice = PCI_ANY_ID, 2707 .setup = pci_brcm_trumanage_setup, 2708 }, 2709 { 2710 .vendor = 0x1c29, 2711 .device = 0x1104, 2712 .subvendor = PCI_ANY_ID, 2713 .subdevice = PCI_ANY_ID, 2714 .setup = pci_fintek_setup, 2715 .init = pci_fintek_init, 2716 }, 2717 { 2718 .vendor = 0x1c29, 2719 .device = 0x1108, 2720 .subvendor = PCI_ANY_ID, 2721 .subdevice = PCI_ANY_ID, 2722 .setup = pci_fintek_setup, 2723 .init = pci_fintek_init, 2724 }, 2725 { 2726 .vendor = 0x1c29, 2727 .device = 0x1112, 2728 .subvendor = PCI_ANY_ID, 2729 .subdevice = PCI_ANY_ID, 2730 .setup = pci_fintek_setup, 2731 .init = pci_fintek_init, 2732 }, 2733 /* 2734 * MOXA 2735 */ 2736 { 2737 .vendor = PCI_VENDOR_ID_MOXA, 2738 .device = PCI_ANY_ID, 2739 .subvendor = PCI_ANY_ID, 2740 .subdevice = PCI_ANY_ID, 2741 .setup = pci_moxa_setup, 2742 }, 2743 { 2744 .vendor = 0x1c29, 2745 .device = 0x1204, 2746 .subvendor = PCI_ANY_ID, 2747 .subdevice = PCI_ANY_ID, 2748 .setup = pci_fintek_f815xxa_setup, 2749 .init = pci_fintek_f815xxa_init, 2750 }, 2751 { 2752 .vendor = 0x1c29, 2753 .device = 0x1208, 2754 .subvendor = PCI_ANY_ID, 2755 .subdevice = PCI_ANY_ID, 2756 .setup = pci_fintek_f815xxa_setup, 2757 .init = pci_fintek_f815xxa_init, 2758 }, 2759 { 2760 .vendor = 0x1c29, 2761 .device = 0x1212, 2762 .subvendor = PCI_ANY_ID, 2763 .subdevice = PCI_ANY_ID, 2764 .setup = pci_fintek_f815xxa_setup, 2765 .init = pci_fintek_f815xxa_init, 2766 }, 2767 2768 /* 2769 * Default "match everything" terminator entry 2770 */ 2771 { 2772 .vendor = PCI_ANY_ID, 2773 .device = PCI_ANY_ID, 2774 .subvendor = PCI_ANY_ID, 2775 .subdevice = PCI_ANY_ID, 2776 .setup = pci_default_setup, 2777 } 2778 }; 2779 2780 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 2781 { 2782 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 2783 } 2784 2785 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 2786 { 2787 struct pci_serial_quirk *quirk; 2788 2789 for (quirk = pci_serial_quirks; ; quirk++) 2790 if (quirk_id_matches(quirk->vendor, dev->vendor) && 2791 quirk_id_matches(quirk->device, dev->device) && 2792 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 2793 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 2794 break; 2795 return quirk; 2796 } 2797 2798 /* 2799 * This is the configuration table for all of the PCI serial boards 2800 * which we support. It is directly indexed by the pci_board_num_t enum 2801 * value, which is encoded in the pci_device_id PCI probe table's 2802 * driver_data member. 2803 * 2804 * The makeup of these names are: 2805 * pbn_bn{_bt}_n_baud{_offsetinhex} 2806 * 2807 * bn = PCI BAR number 2808 * bt = Index using PCI BARs 2809 * n = number of serial ports 2810 * baud = baud rate 2811 * offsetinhex = offset for each sequential port (in hex) 2812 * 2813 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 2814 * 2815 * Please note: in theory if n = 1, _bt infix should make no difference. 2816 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 2817 */ 2818 enum pci_board_num_t { 2819 pbn_default = 0, 2820 2821 pbn_b0_1_115200, 2822 pbn_b0_2_115200, 2823 pbn_b0_4_115200, 2824 pbn_b0_5_115200, 2825 pbn_b0_8_115200, 2826 2827 pbn_b0_1_921600, 2828 pbn_b0_2_921600, 2829 pbn_b0_4_921600, 2830 2831 pbn_b0_2_1130000, 2832 2833 pbn_b0_4_1152000, 2834 2835 pbn_b0_4_1250000, 2836 2837 pbn_b0_2_1843200, 2838 pbn_b0_4_1843200, 2839 2840 pbn_b0_1_4000000, 2841 2842 pbn_b0_bt_1_115200, 2843 pbn_b0_bt_2_115200, 2844 pbn_b0_bt_4_115200, 2845 pbn_b0_bt_8_115200, 2846 2847 pbn_b0_bt_1_460800, 2848 pbn_b0_bt_2_460800, 2849 pbn_b0_bt_4_460800, 2850 2851 pbn_b0_bt_1_921600, 2852 pbn_b0_bt_2_921600, 2853 pbn_b0_bt_4_921600, 2854 pbn_b0_bt_8_921600, 2855 2856 pbn_b1_1_115200, 2857 pbn_b1_2_115200, 2858 pbn_b1_4_115200, 2859 pbn_b1_8_115200, 2860 pbn_b1_16_115200, 2861 2862 pbn_b1_1_921600, 2863 pbn_b1_2_921600, 2864 pbn_b1_4_921600, 2865 pbn_b1_8_921600, 2866 2867 pbn_b1_2_1250000, 2868 2869 pbn_b1_bt_1_115200, 2870 pbn_b1_bt_2_115200, 2871 pbn_b1_bt_4_115200, 2872 2873 pbn_b1_bt_2_921600, 2874 2875 pbn_b1_1_1382400, 2876 pbn_b1_2_1382400, 2877 pbn_b1_4_1382400, 2878 pbn_b1_8_1382400, 2879 2880 pbn_b2_1_115200, 2881 pbn_b2_2_115200, 2882 pbn_b2_4_115200, 2883 pbn_b2_8_115200, 2884 2885 pbn_b2_1_460800, 2886 pbn_b2_4_460800, 2887 pbn_b2_8_460800, 2888 pbn_b2_16_460800, 2889 2890 pbn_b2_1_921600, 2891 pbn_b2_4_921600, 2892 pbn_b2_8_921600, 2893 2894 pbn_b2_8_1152000, 2895 2896 pbn_b2_bt_1_115200, 2897 pbn_b2_bt_2_115200, 2898 pbn_b2_bt_4_115200, 2899 2900 pbn_b2_bt_2_921600, 2901 pbn_b2_bt_4_921600, 2902 2903 pbn_b3_2_115200, 2904 pbn_b3_4_115200, 2905 pbn_b3_8_115200, 2906 2907 pbn_b4_bt_2_921600, 2908 pbn_b4_bt_4_921600, 2909 pbn_b4_bt_8_921600, 2910 2911 /* 2912 * Board-specific versions. 2913 */ 2914 pbn_panacom, 2915 pbn_panacom2, 2916 pbn_panacom4, 2917 pbn_plx_romulus, 2918 pbn_endrun_2_4000000, 2919 pbn_oxsemi, 2920 pbn_oxsemi_1_4000000, 2921 pbn_oxsemi_2_4000000, 2922 pbn_oxsemi_4_4000000, 2923 pbn_oxsemi_8_4000000, 2924 pbn_intel_i960, 2925 pbn_sgi_ioc3, 2926 pbn_computone_4, 2927 pbn_computone_6, 2928 pbn_computone_8, 2929 pbn_sbsxrsio, 2930 pbn_pasemi_1682M, 2931 pbn_ni8430_2, 2932 pbn_ni8430_4, 2933 pbn_ni8430_8, 2934 pbn_ni8430_16, 2935 pbn_ADDIDATA_PCIe_1_3906250, 2936 pbn_ADDIDATA_PCIe_2_3906250, 2937 pbn_ADDIDATA_PCIe_4_3906250, 2938 pbn_ADDIDATA_PCIe_8_3906250, 2939 pbn_ce4100_1_115200, 2940 pbn_omegapci, 2941 pbn_NETMOS9900_2s_115200, 2942 pbn_brcm_trumanage, 2943 pbn_fintek_4, 2944 pbn_fintek_8, 2945 pbn_fintek_12, 2946 pbn_fintek_F81504A, 2947 pbn_fintek_F81508A, 2948 pbn_fintek_F81512A, 2949 pbn_wch382_2, 2950 pbn_wch384_4, 2951 pbn_wch384_8, 2952 pbn_pericom_PI7C9X7951, 2953 pbn_pericom_PI7C9X7952, 2954 pbn_pericom_PI7C9X7954, 2955 pbn_pericom_PI7C9X7958, 2956 pbn_sunix_pci_1s, 2957 pbn_sunix_pci_2s, 2958 pbn_sunix_pci_4s, 2959 pbn_sunix_pci_8s, 2960 pbn_sunix_pci_16s, 2961 pbn_moxa8250_2p, 2962 pbn_moxa8250_4p, 2963 pbn_moxa8250_8p, 2964 }; 2965 2966 /* 2967 * uart_offset - the space between channels 2968 * reg_shift - describes how the UART registers are mapped 2969 * to PCI memory by the card. 2970 * For example IER register on SBS, Inc. PMC-OctPro is located at 2971 * offset 0x10 from the UART base, while UART_IER is defined as 1 2972 * in include/linux/serial_reg.h, 2973 * see first lines of serial_in() and serial_out() in 8250.c 2974 */ 2975 2976 static struct pciserial_board pci_boards[] = { 2977 [pbn_default] = { 2978 .flags = FL_BASE0, 2979 .num_ports = 1, 2980 .base_baud = 115200, 2981 .uart_offset = 8, 2982 }, 2983 [pbn_b0_1_115200] = { 2984 .flags = FL_BASE0, 2985 .num_ports = 1, 2986 .base_baud = 115200, 2987 .uart_offset = 8, 2988 }, 2989 [pbn_b0_2_115200] = { 2990 .flags = FL_BASE0, 2991 .num_ports = 2, 2992 .base_baud = 115200, 2993 .uart_offset = 8, 2994 }, 2995 [pbn_b0_4_115200] = { 2996 .flags = FL_BASE0, 2997 .num_ports = 4, 2998 .base_baud = 115200, 2999 .uart_offset = 8, 3000 }, 3001 [pbn_b0_5_115200] = { 3002 .flags = FL_BASE0, 3003 .num_ports = 5, 3004 .base_baud = 115200, 3005 .uart_offset = 8, 3006 }, 3007 [pbn_b0_8_115200] = { 3008 .flags = FL_BASE0, 3009 .num_ports = 8, 3010 .base_baud = 115200, 3011 .uart_offset = 8, 3012 }, 3013 [pbn_b0_1_921600] = { 3014 .flags = FL_BASE0, 3015 .num_ports = 1, 3016 .base_baud = 921600, 3017 .uart_offset = 8, 3018 }, 3019 [pbn_b0_2_921600] = { 3020 .flags = FL_BASE0, 3021 .num_ports = 2, 3022 .base_baud = 921600, 3023 .uart_offset = 8, 3024 }, 3025 [pbn_b0_4_921600] = { 3026 .flags = FL_BASE0, 3027 .num_ports = 4, 3028 .base_baud = 921600, 3029 .uart_offset = 8, 3030 }, 3031 3032 [pbn_b0_2_1130000] = { 3033 .flags = FL_BASE0, 3034 .num_ports = 2, 3035 .base_baud = 1130000, 3036 .uart_offset = 8, 3037 }, 3038 3039 [pbn_b0_4_1152000] = { 3040 .flags = FL_BASE0, 3041 .num_ports = 4, 3042 .base_baud = 1152000, 3043 .uart_offset = 8, 3044 }, 3045 3046 [pbn_b0_4_1250000] = { 3047 .flags = FL_BASE0, 3048 .num_ports = 4, 3049 .base_baud = 1250000, 3050 .uart_offset = 8, 3051 }, 3052 3053 [pbn_b0_2_1843200] = { 3054 .flags = FL_BASE0, 3055 .num_ports = 2, 3056 .base_baud = 1843200, 3057 .uart_offset = 8, 3058 }, 3059 [pbn_b0_4_1843200] = { 3060 .flags = FL_BASE0, 3061 .num_ports = 4, 3062 .base_baud = 1843200, 3063 .uart_offset = 8, 3064 }, 3065 3066 [pbn_b0_1_4000000] = { 3067 .flags = FL_BASE0, 3068 .num_ports = 1, 3069 .base_baud = 4000000, 3070 .uart_offset = 8, 3071 }, 3072 3073 [pbn_b0_bt_1_115200] = { 3074 .flags = FL_BASE0|FL_BASE_BARS, 3075 .num_ports = 1, 3076 .base_baud = 115200, 3077 .uart_offset = 8, 3078 }, 3079 [pbn_b0_bt_2_115200] = { 3080 .flags = FL_BASE0|FL_BASE_BARS, 3081 .num_ports = 2, 3082 .base_baud = 115200, 3083 .uart_offset = 8, 3084 }, 3085 [pbn_b0_bt_4_115200] = { 3086 .flags = FL_BASE0|FL_BASE_BARS, 3087 .num_ports = 4, 3088 .base_baud = 115200, 3089 .uart_offset = 8, 3090 }, 3091 [pbn_b0_bt_8_115200] = { 3092 .flags = FL_BASE0|FL_BASE_BARS, 3093 .num_ports = 8, 3094 .base_baud = 115200, 3095 .uart_offset = 8, 3096 }, 3097 3098 [pbn_b0_bt_1_460800] = { 3099 .flags = FL_BASE0|FL_BASE_BARS, 3100 .num_ports = 1, 3101 .base_baud = 460800, 3102 .uart_offset = 8, 3103 }, 3104 [pbn_b0_bt_2_460800] = { 3105 .flags = FL_BASE0|FL_BASE_BARS, 3106 .num_ports = 2, 3107 .base_baud = 460800, 3108 .uart_offset = 8, 3109 }, 3110 [pbn_b0_bt_4_460800] = { 3111 .flags = FL_BASE0|FL_BASE_BARS, 3112 .num_ports = 4, 3113 .base_baud = 460800, 3114 .uart_offset = 8, 3115 }, 3116 3117 [pbn_b0_bt_1_921600] = { 3118 .flags = FL_BASE0|FL_BASE_BARS, 3119 .num_ports = 1, 3120 .base_baud = 921600, 3121 .uart_offset = 8, 3122 }, 3123 [pbn_b0_bt_2_921600] = { 3124 .flags = FL_BASE0|FL_BASE_BARS, 3125 .num_ports = 2, 3126 .base_baud = 921600, 3127 .uart_offset = 8, 3128 }, 3129 [pbn_b0_bt_4_921600] = { 3130 .flags = FL_BASE0|FL_BASE_BARS, 3131 .num_ports = 4, 3132 .base_baud = 921600, 3133 .uart_offset = 8, 3134 }, 3135 [pbn_b0_bt_8_921600] = { 3136 .flags = FL_BASE0|FL_BASE_BARS, 3137 .num_ports = 8, 3138 .base_baud = 921600, 3139 .uart_offset = 8, 3140 }, 3141 3142 [pbn_b1_1_115200] = { 3143 .flags = FL_BASE1, 3144 .num_ports = 1, 3145 .base_baud = 115200, 3146 .uart_offset = 8, 3147 }, 3148 [pbn_b1_2_115200] = { 3149 .flags = FL_BASE1, 3150 .num_ports = 2, 3151 .base_baud = 115200, 3152 .uart_offset = 8, 3153 }, 3154 [pbn_b1_4_115200] = { 3155 .flags = FL_BASE1, 3156 .num_ports = 4, 3157 .base_baud = 115200, 3158 .uart_offset = 8, 3159 }, 3160 [pbn_b1_8_115200] = { 3161 .flags = FL_BASE1, 3162 .num_ports = 8, 3163 .base_baud = 115200, 3164 .uart_offset = 8, 3165 }, 3166 [pbn_b1_16_115200] = { 3167 .flags = FL_BASE1, 3168 .num_ports = 16, 3169 .base_baud = 115200, 3170 .uart_offset = 8, 3171 }, 3172 3173 [pbn_b1_1_921600] = { 3174 .flags = FL_BASE1, 3175 .num_ports = 1, 3176 .base_baud = 921600, 3177 .uart_offset = 8, 3178 }, 3179 [pbn_b1_2_921600] = { 3180 .flags = FL_BASE1, 3181 .num_ports = 2, 3182 .base_baud = 921600, 3183 .uart_offset = 8, 3184 }, 3185 [pbn_b1_4_921600] = { 3186 .flags = FL_BASE1, 3187 .num_ports = 4, 3188 .base_baud = 921600, 3189 .uart_offset = 8, 3190 }, 3191 [pbn_b1_8_921600] = { 3192 .flags = FL_BASE1, 3193 .num_ports = 8, 3194 .base_baud = 921600, 3195 .uart_offset = 8, 3196 }, 3197 [pbn_b1_2_1250000] = { 3198 .flags = FL_BASE1, 3199 .num_ports = 2, 3200 .base_baud = 1250000, 3201 .uart_offset = 8, 3202 }, 3203 3204 [pbn_b1_bt_1_115200] = { 3205 .flags = FL_BASE1|FL_BASE_BARS, 3206 .num_ports = 1, 3207 .base_baud = 115200, 3208 .uart_offset = 8, 3209 }, 3210 [pbn_b1_bt_2_115200] = { 3211 .flags = FL_BASE1|FL_BASE_BARS, 3212 .num_ports = 2, 3213 .base_baud = 115200, 3214 .uart_offset = 8, 3215 }, 3216 [pbn_b1_bt_4_115200] = { 3217 .flags = FL_BASE1|FL_BASE_BARS, 3218 .num_ports = 4, 3219 .base_baud = 115200, 3220 .uart_offset = 8, 3221 }, 3222 3223 [pbn_b1_bt_2_921600] = { 3224 .flags = FL_BASE1|FL_BASE_BARS, 3225 .num_ports = 2, 3226 .base_baud = 921600, 3227 .uart_offset = 8, 3228 }, 3229 3230 [pbn_b1_1_1382400] = { 3231 .flags = FL_BASE1, 3232 .num_ports = 1, 3233 .base_baud = 1382400, 3234 .uart_offset = 8, 3235 }, 3236 [pbn_b1_2_1382400] = { 3237 .flags = FL_BASE1, 3238 .num_ports = 2, 3239 .base_baud = 1382400, 3240 .uart_offset = 8, 3241 }, 3242 [pbn_b1_4_1382400] = { 3243 .flags = FL_BASE1, 3244 .num_ports = 4, 3245 .base_baud = 1382400, 3246 .uart_offset = 8, 3247 }, 3248 [pbn_b1_8_1382400] = { 3249 .flags = FL_BASE1, 3250 .num_ports = 8, 3251 .base_baud = 1382400, 3252 .uart_offset = 8, 3253 }, 3254 3255 [pbn_b2_1_115200] = { 3256 .flags = FL_BASE2, 3257 .num_ports = 1, 3258 .base_baud = 115200, 3259 .uart_offset = 8, 3260 }, 3261 [pbn_b2_2_115200] = { 3262 .flags = FL_BASE2, 3263 .num_ports = 2, 3264 .base_baud = 115200, 3265 .uart_offset = 8, 3266 }, 3267 [pbn_b2_4_115200] = { 3268 .flags = FL_BASE2, 3269 .num_ports = 4, 3270 .base_baud = 115200, 3271 .uart_offset = 8, 3272 }, 3273 [pbn_b2_8_115200] = { 3274 .flags = FL_BASE2, 3275 .num_ports = 8, 3276 .base_baud = 115200, 3277 .uart_offset = 8, 3278 }, 3279 3280 [pbn_b2_1_460800] = { 3281 .flags = FL_BASE2, 3282 .num_ports = 1, 3283 .base_baud = 460800, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b2_4_460800] = { 3287 .flags = FL_BASE2, 3288 .num_ports = 4, 3289 .base_baud = 460800, 3290 .uart_offset = 8, 3291 }, 3292 [pbn_b2_8_460800] = { 3293 .flags = FL_BASE2, 3294 .num_ports = 8, 3295 .base_baud = 460800, 3296 .uart_offset = 8, 3297 }, 3298 [pbn_b2_16_460800] = { 3299 .flags = FL_BASE2, 3300 .num_ports = 16, 3301 .base_baud = 460800, 3302 .uart_offset = 8, 3303 }, 3304 3305 [pbn_b2_1_921600] = { 3306 .flags = FL_BASE2, 3307 .num_ports = 1, 3308 .base_baud = 921600, 3309 .uart_offset = 8, 3310 }, 3311 [pbn_b2_4_921600] = { 3312 .flags = FL_BASE2, 3313 .num_ports = 4, 3314 .base_baud = 921600, 3315 .uart_offset = 8, 3316 }, 3317 [pbn_b2_8_921600] = { 3318 .flags = FL_BASE2, 3319 .num_ports = 8, 3320 .base_baud = 921600, 3321 .uart_offset = 8, 3322 }, 3323 3324 [pbn_b2_8_1152000] = { 3325 .flags = FL_BASE2, 3326 .num_ports = 8, 3327 .base_baud = 1152000, 3328 .uart_offset = 8, 3329 }, 3330 3331 [pbn_b2_bt_1_115200] = { 3332 .flags = FL_BASE2|FL_BASE_BARS, 3333 .num_ports = 1, 3334 .base_baud = 115200, 3335 .uart_offset = 8, 3336 }, 3337 [pbn_b2_bt_2_115200] = { 3338 .flags = FL_BASE2|FL_BASE_BARS, 3339 .num_ports = 2, 3340 .base_baud = 115200, 3341 .uart_offset = 8, 3342 }, 3343 [pbn_b2_bt_4_115200] = { 3344 .flags = FL_BASE2|FL_BASE_BARS, 3345 .num_ports = 4, 3346 .base_baud = 115200, 3347 .uart_offset = 8, 3348 }, 3349 3350 [pbn_b2_bt_2_921600] = { 3351 .flags = FL_BASE2|FL_BASE_BARS, 3352 .num_ports = 2, 3353 .base_baud = 921600, 3354 .uart_offset = 8, 3355 }, 3356 [pbn_b2_bt_4_921600] = { 3357 .flags = FL_BASE2|FL_BASE_BARS, 3358 .num_ports = 4, 3359 .base_baud = 921600, 3360 .uart_offset = 8, 3361 }, 3362 3363 [pbn_b3_2_115200] = { 3364 .flags = FL_BASE3, 3365 .num_ports = 2, 3366 .base_baud = 115200, 3367 .uart_offset = 8, 3368 }, 3369 [pbn_b3_4_115200] = { 3370 .flags = FL_BASE3, 3371 .num_ports = 4, 3372 .base_baud = 115200, 3373 .uart_offset = 8, 3374 }, 3375 [pbn_b3_8_115200] = { 3376 .flags = FL_BASE3, 3377 .num_ports = 8, 3378 .base_baud = 115200, 3379 .uart_offset = 8, 3380 }, 3381 3382 [pbn_b4_bt_2_921600] = { 3383 .flags = FL_BASE4, 3384 .num_ports = 2, 3385 .base_baud = 921600, 3386 .uart_offset = 8, 3387 }, 3388 [pbn_b4_bt_4_921600] = { 3389 .flags = FL_BASE4, 3390 .num_ports = 4, 3391 .base_baud = 921600, 3392 .uart_offset = 8, 3393 }, 3394 [pbn_b4_bt_8_921600] = { 3395 .flags = FL_BASE4, 3396 .num_ports = 8, 3397 .base_baud = 921600, 3398 .uart_offset = 8, 3399 }, 3400 3401 /* 3402 * Entries following this are board-specific. 3403 */ 3404 3405 /* 3406 * Panacom - IOMEM 3407 */ 3408 [pbn_panacom] = { 3409 .flags = FL_BASE2, 3410 .num_ports = 2, 3411 .base_baud = 921600, 3412 .uart_offset = 0x400, 3413 .reg_shift = 7, 3414 }, 3415 [pbn_panacom2] = { 3416 .flags = FL_BASE2|FL_BASE_BARS, 3417 .num_ports = 2, 3418 .base_baud = 921600, 3419 .uart_offset = 0x400, 3420 .reg_shift = 7, 3421 }, 3422 [pbn_panacom4] = { 3423 .flags = FL_BASE2|FL_BASE_BARS, 3424 .num_ports = 4, 3425 .base_baud = 921600, 3426 .uart_offset = 0x400, 3427 .reg_shift = 7, 3428 }, 3429 3430 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3431 [pbn_plx_romulus] = { 3432 .flags = FL_BASE2, 3433 .num_ports = 4, 3434 .base_baud = 921600, 3435 .uart_offset = 8 << 2, 3436 .reg_shift = 2, 3437 .first_offset = 0x03, 3438 }, 3439 3440 /* 3441 * EndRun Technologies 3442 * Uses the size of PCI Base region 0 to 3443 * signal now many ports are available 3444 * 2 port 952 Uart support 3445 */ 3446 [pbn_endrun_2_4000000] = { 3447 .flags = FL_BASE0, 3448 .num_ports = 2, 3449 .base_baud = 4000000, 3450 .uart_offset = 0x200, 3451 .first_offset = 0x1000, 3452 }, 3453 3454 /* 3455 * This board uses the size of PCI Base region 0 to 3456 * signal now many ports are available 3457 */ 3458 [pbn_oxsemi] = { 3459 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3460 .num_ports = 32, 3461 .base_baud = 115200, 3462 .uart_offset = 8, 3463 }, 3464 [pbn_oxsemi_1_4000000] = { 3465 .flags = FL_BASE0, 3466 .num_ports = 1, 3467 .base_baud = 4000000, 3468 .uart_offset = 0x200, 3469 .first_offset = 0x1000, 3470 }, 3471 [pbn_oxsemi_2_4000000] = { 3472 .flags = FL_BASE0, 3473 .num_ports = 2, 3474 .base_baud = 4000000, 3475 .uart_offset = 0x200, 3476 .first_offset = 0x1000, 3477 }, 3478 [pbn_oxsemi_4_4000000] = { 3479 .flags = FL_BASE0, 3480 .num_ports = 4, 3481 .base_baud = 4000000, 3482 .uart_offset = 0x200, 3483 .first_offset = 0x1000, 3484 }, 3485 [pbn_oxsemi_8_4000000] = { 3486 .flags = FL_BASE0, 3487 .num_ports = 8, 3488 .base_baud = 4000000, 3489 .uart_offset = 0x200, 3490 .first_offset = 0x1000, 3491 }, 3492 3493 3494 /* 3495 * EKF addition for i960 Boards form EKF with serial port. 3496 * Max 256 ports. 3497 */ 3498 [pbn_intel_i960] = { 3499 .flags = FL_BASE0, 3500 .num_ports = 32, 3501 .base_baud = 921600, 3502 .uart_offset = 8 << 2, 3503 .reg_shift = 2, 3504 .first_offset = 0x10000, 3505 }, 3506 [pbn_sgi_ioc3] = { 3507 .flags = FL_BASE0|FL_NOIRQ, 3508 .num_ports = 1, 3509 .base_baud = 458333, 3510 .uart_offset = 8, 3511 .reg_shift = 0, 3512 .first_offset = 0x20178, 3513 }, 3514 3515 /* 3516 * Computone - uses IOMEM. 3517 */ 3518 [pbn_computone_4] = { 3519 .flags = FL_BASE0, 3520 .num_ports = 4, 3521 .base_baud = 921600, 3522 .uart_offset = 0x40, 3523 .reg_shift = 2, 3524 .first_offset = 0x200, 3525 }, 3526 [pbn_computone_6] = { 3527 .flags = FL_BASE0, 3528 .num_ports = 6, 3529 .base_baud = 921600, 3530 .uart_offset = 0x40, 3531 .reg_shift = 2, 3532 .first_offset = 0x200, 3533 }, 3534 [pbn_computone_8] = { 3535 .flags = FL_BASE0, 3536 .num_ports = 8, 3537 .base_baud = 921600, 3538 .uart_offset = 0x40, 3539 .reg_shift = 2, 3540 .first_offset = 0x200, 3541 }, 3542 [pbn_sbsxrsio] = { 3543 .flags = FL_BASE0, 3544 .num_ports = 8, 3545 .base_baud = 460800, 3546 .uart_offset = 256, 3547 .reg_shift = 4, 3548 }, 3549 /* 3550 * PA Semi PWRficient PA6T-1682M on-chip UART 3551 */ 3552 [pbn_pasemi_1682M] = { 3553 .flags = FL_BASE0, 3554 .num_ports = 1, 3555 .base_baud = 8333333, 3556 }, 3557 /* 3558 * National Instruments 843x 3559 */ 3560 [pbn_ni8430_16] = { 3561 .flags = FL_BASE0, 3562 .num_ports = 16, 3563 .base_baud = 3686400, 3564 .uart_offset = 0x10, 3565 .first_offset = 0x800, 3566 }, 3567 [pbn_ni8430_8] = { 3568 .flags = FL_BASE0, 3569 .num_ports = 8, 3570 .base_baud = 3686400, 3571 .uart_offset = 0x10, 3572 .first_offset = 0x800, 3573 }, 3574 [pbn_ni8430_4] = { 3575 .flags = FL_BASE0, 3576 .num_ports = 4, 3577 .base_baud = 3686400, 3578 .uart_offset = 0x10, 3579 .first_offset = 0x800, 3580 }, 3581 [pbn_ni8430_2] = { 3582 .flags = FL_BASE0, 3583 .num_ports = 2, 3584 .base_baud = 3686400, 3585 .uart_offset = 0x10, 3586 .first_offset = 0x800, 3587 }, 3588 /* 3589 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3590 */ 3591 [pbn_ADDIDATA_PCIe_1_3906250] = { 3592 .flags = FL_BASE0, 3593 .num_ports = 1, 3594 .base_baud = 3906250, 3595 .uart_offset = 0x200, 3596 .first_offset = 0x1000, 3597 }, 3598 [pbn_ADDIDATA_PCIe_2_3906250] = { 3599 .flags = FL_BASE0, 3600 .num_ports = 2, 3601 .base_baud = 3906250, 3602 .uart_offset = 0x200, 3603 .first_offset = 0x1000, 3604 }, 3605 [pbn_ADDIDATA_PCIe_4_3906250] = { 3606 .flags = FL_BASE0, 3607 .num_ports = 4, 3608 .base_baud = 3906250, 3609 .uart_offset = 0x200, 3610 .first_offset = 0x1000, 3611 }, 3612 [pbn_ADDIDATA_PCIe_8_3906250] = { 3613 .flags = FL_BASE0, 3614 .num_ports = 8, 3615 .base_baud = 3906250, 3616 .uart_offset = 0x200, 3617 .first_offset = 0x1000, 3618 }, 3619 [pbn_ce4100_1_115200] = { 3620 .flags = FL_BASE_BARS, 3621 .num_ports = 2, 3622 .base_baud = 921600, 3623 .reg_shift = 2, 3624 }, 3625 [pbn_omegapci] = { 3626 .flags = FL_BASE0, 3627 .num_ports = 8, 3628 .base_baud = 115200, 3629 .uart_offset = 0x200, 3630 }, 3631 [pbn_NETMOS9900_2s_115200] = { 3632 .flags = FL_BASE0, 3633 .num_ports = 2, 3634 .base_baud = 115200, 3635 }, 3636 [pbn_brcm_trumanage] = { 3637 .flags = FL_BASE0, 3638 .num_ports = 1, 3639 .reg_shift = 2, 3640 .base_baud = 115200, 3641 }, 3642 [pbn_fintek_4] = { 3643 .num_ports = 4, 3644 .uart_offset = 8, 3645 .base_baud = 115200, 3646 .first_offset = 0x40, 3647 }, 3648 [pbn_fintek_8] = { 3649 .num_ports = 8, 3650 .uart_offset = 8, 3651 .base_baud = 115200, 3652 .first_offset = 0x40, 3653 }, 3654 [pbn_fintek_12] = { 3655 .num_ports = 12, 3656 .uart_offset = 8, 3657 .base_baud = 115200, 3658 .first_offset = 0x40, 3659 }, 3660 [pbn_fintek_F81504A] = { 3661 .num_ports = 4, 3662 .uart_offset = 8, 3663 .base_baud = 115200, 3664 }, 3665 [pbn_fintek_F81508A] = { 3666 .num_ports = 8, 3667 .uart_offset = 8, 3668 .base_baud = 115200, 3669 }, 3670 [pbn_fintek_F81512A] = { 3671 .num_ports = 12, 3672 .uart_offset = 8, 3673 .base_baud = 115200, 3674 }, 3675 [pbn_wch382_2] = { 3676 .flags = FL_BASE0, 3677 .num_ports = 2, 3678 .base_baud = 115200, 3679 .uart_offset = 8, 3680 .first_offset = 0xC0, 3681 }, 3682 [pbn_wch384_4] = { 3683 .flags = FL_BASE0, 3684 .num_ports = 4, 3685 .base_baud = 115200, 3686 .uart_offset = 8, 3687 .first_offset = 0xC0, 3688 }, 3689 [pbn_wch384_8] = { 3690 .flags = FL_BASE0, 3691 .num_ports = 8, 3692 .base_baud = 115200, 3693 .uart_offset = 8, 3694 .first_offset = 0x00, 3695 }, 3696 /* 3697 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 3698 */ 3699 [pbn_pericom_PI7C9X7951] = { 3700 .flags = FL_BASE0, 3701 .num_ports = 1, 3702 .base_baud = 921600, 3703 .uart_offset = 0x8, 3704 }, 3705 [pbn_pericom_PI7C9X7952] = { 3706 .flags = FL_BASE0, 3707 .num_ports = 2, 3708 .base_baud = 921600, 3709 .uart_offset = 0x8, 3710 }, 3711 [pbn_pericom_PI7C9X7954] = { 3712 .flags = FL_BASE0, 3713 .num_ports = 4, 3714 .base_baud = 921600, 3715 .uart_offset = 0x8, 3716 }, 3717 [pbn_pericom_PI7C9X7958] = { 3718 .flags = FL_BASE0, 3719 .num_ports = 8, 3720 .base_baud = 921600, 3721 .uart_offset = 0x8, 3722 }, 3723 [pbn_sunix_pci_1s] = { 3724 .num_ports = 1, 3725 .base_baud = 921600, 3726 .uart_offset = 0x8, 3727 }, 3728 [pbn_sunix_pci_2s] = { 3729 .num_ports = 2, 3730 .base_baud = 921600, 3731 .uart_offset = 0x8, 3732 }, 3733 [pbn_sunix_pci_4s] = { 3734 .num_ports = 4, 3735 .base_baud = 921600, 3736 .uart_offset = 0x8, 3737 }, 3738 [pbn_sunix_pci_8s] = { 3739 .num_ports = 8, 3740 .base_baud = 921600, 3741 .uart_offset = 0x8, 3742 }, 3743 [pbn_sunix_pci_16s] = { 3744 .num_ports = 16, 3745 .base_baud = 921600, 3746 .uart_offset = 0x8, 3747 }, 3748 [pbn_moxa8250_2p] = { 3749 .flags = FL_BASE1, 3750 .num_ports = 2, 3751 .base_baud = 921600, 3752 .uart_offset = 0x200, 3753 }, 3754 [pbn_moxa8250_4p] = { 3755 .flags = FL_BASE1, 3756 .num_ports = 4, 3757 .base_baud = 921600, 3758 .uart_offset = 0x200, 3759 }, 3760 [pbn_moxa8250_8p] = { 3761 .flags = FL_BASE1, 3762 .num_ports = 8, 3763 .base_baud = 921600, 3764 .uart_offset = 0x200, 3765 }, 3766 }; 3767 3768 static const struct pci_device_id blacklist[] = { 3769 /* softmodems */ 3770 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 3771 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 3772 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 3773 3774 /* multi-io cards handled by parport_serial */ 3775 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ 3776 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ 3777 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ 3778 3779 /* Intel platforms with MID UART */ 3780 { PCI_VDEVICE(INTEL, 0x081b), }, 3781 { PCI_VDEVICE(INTEL, 0x081c), }, 3782 { PCI_VDEVICE(INTEL, 0x081d), }, 3783 { PCI_VDEVICE(INTEL, 0x1191), }, 3784 { PCI_VDEVICE(INTEL, 0x18d8), }, 3785 { PCI_VDEVICE(INTEL, 0x19d8), }, 3786 3787 /* Intel platforms with DesignWare UART */ 3788 { PCI_VDEVICE(INTEL, 0x0936), }, 3789 { PCI_VDEVICE(INTEL, 0x0f0a), }, 3790 { PCI_VDEVICE(INTEL, 0x0f0c), }, 3791 { PCI_VDEVICE(INTEL, 0x228a), }, 3792 { PCI_VDEVICE(INTEL, 0x228c), }, 3793 { PCI_VDEVICE(INTEL, 0x9ce3), }, 3794 { PCI_VDEVICE(INTEL, 0x9ce4), }, 3795 3796 /* Exar devices */ 3797 { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, 3798 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, 3799 3800 /* End of the black list */ 3801 { } 3802 }; 3803 3804 static int serial_pci_is_class_communication(struct pci_dev *dev) 3805 { 3806 /* 3807 * If it is not a communications device or the programming 3808 * interface is greater than 6, give up. 3809 */ 3810 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 3811 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 3812 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 3813 (dev->class & 0xff) > 6) 3814 return -ENODEV; 3815 3816 return 0; 3817 } 3818 3819 /* 3820 * Given a complete unknown PCI device, try to use some heuristics to 3821 * guess what the configuration might be, based on the pitiful PCI 3822 * serial specs. Returns 0 on success, -ENODEV on failure. 3823 */ 3824 static int 3825 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 3826 { 3827 int num_iomem, num_port, first_port = -1, i; 3828 int rc; 3829 3830 rc = serial_pci_is_class_communication(dev); 3831 if (rc) 3832 return rc; 3833 3834 /* 3835 * Should we try to make guesses for multiport serial devices later? 3836 */ 3837 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 3838 return -ENODEV; 3839 3840 num_iomem = num_port = 0; 3841 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3842 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 3843 num_port++; 3844 if (first_port == -1) 3845 first_port = i; 3846 } 3847 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 3848 num_iomem++; 3849 } 3850 3851 /* 3852 * If there is 1 or 0 iomem regions, and exactly one port, 3853 * use it. We guess the number of ports based on the IO 3854 * region size. 3855 */ 3856 if (num_iomem <= 1 && num_port == 1) { 3857 board->flags = first_port; 3858 board->num_ports = pci_resource_len(dev, first_port) / 8; 3859 return 0; 3860 } 3861 3862 /* 3863 * Now guess if we've got a board which indexes by BARs. 3864 * Each IO BAR should be 8 bytes, and they should follow 3865 * consecutively. 3866 */ 3867 first_port = -1; 3868 num_port = 0; 3869 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 3870 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 3871 pci_resource_len(dev, i) == 8 && 3872 (first_port == -1 || (first_port + num_port) == i)) { 3873 num_port++; 3874 if (first_port == -1) 3875 first_port = i; 3876 } 3877 } 3878 3879 if (num_port > 1) { 3880 board->flags = first_port | FL_BASE_BARS; 3881 board->num_ports = num_port; 3882 return 0; 3883 } 3884 3885 return -ENODEV; 3886 } 3887 3888 static inline int 3889 serial_pci_matches(const struct pciserial_board *board, 3890 const struct pciserial_board *guessed) 3891 { 3892 return 3893 board->num_ports == guessed->num_ports && 3894 board->base_baud == guessed->base_baud && 3895 board->uart_offset == guessed->uart_offset && 3896 board->reg_shift == guessed->reg_shift && 3897 board->first_offset == guessed->first_offset; 3898 } 3899 3900 struct serial_private * 3901 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 3902 { 3903 struct uart_8250_port uart; 3904 struct serial_private *priv; 3905 struct pci_serial_quirk *quirk; 3906 int rc, nr_ports, i; 3907 3908 nr_ports = board->num_ports; 3909 3910 /* 3911 * Find an init and setup quirks. 3912 */ 3913 quirk = find_quirk(dev); 3914 3915 /* 3916 * Run the new-style initialization function. 3917 * The initialization function returns: 3918 * <0 - error 3919 * 0 - use board->num_ports 3920 * >0 - number of ports 3921 */ 3922 if (quirk->init) { 3923 rc = quirk->init(dev); 3924 if (rc < 0) { 3925 priv = ERR_PTR(rc); 3926 goto err_out; 3927 } 3928 if (rc) 3929 nr_ports = rc; 3930 } 3931 3932 priv = kzalloc(sizeof(struct serial_private) + 3933 sizeof(unsigned int) * nr_ports, 3934 GFP_KERNEL); 3935 if (!priv) { 3936 priv = ERR_PTR(-ENOMEM); 3937 goto err_deinit; 3938 } 3939 3940 priv->dev = dev; 3941 priv->quirk = quirk; 3942 3943 memset(&uart, 0, sizeof(uart)); 3944 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 3945 uart.port.uartclk = board->base_baud * 16; 3946 3947 if (pci_match_id(pci_use_msi, dev)) { 3948 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n"); 3949 pci_set_master(dev); 3950 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 3951 } else { 3952 dev_dbg(&dev->dev, "Using legacy interrupts\n"); 3953 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY); 3954 } 3955 if (rc < 0) { 3956 kfree(priv); 3957 priv = ERR_PTR(rc); 3958 goto err_deinit; 3959 } 3960 3961 uart.port.irq = pci_irq_vector(dev, 0); 3962 uart.port.dev = &dev->dev; 3963 3964 for (i = 0; i < nr_ports; i++) { 3965 if (quirk->setup(priv, board, &uart, i)) 3966 break; 3967 3968 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 3969 uart.port.iobase, uart.port.irq, uart.port.iotype); 3970 3971 priv->line[i] = serial8250_register_8250_port(&uart); 3972 if (priv->line[i] < 0) { 3973 dev_err(&dev->dev, 3974 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 3975 uart.port.iobase, uart.port.irq, 3976 uart.port.iotype, priv->line[i]); 3977 break; 3978 } 3979 } 3980 priv->nr = i; 3981 priv->board = board; 3982 return priv; 3983 3984 err_deinit: 3985 if (quirk->exit) 3986 quirk->exit(dev); 3987 err_out: 3988 return priv; 3989 } 3990 EXPORT_SYMBOL_GPL(pciserial_init_ports); 3991 3992 static void pciserial_detach_ports(struct serial_private *priv) 3993 { 3994 struct pci_serial_quirk *quirk; 3995 int i; 3996 3997 for (i = 0; i < priv->nr; i++) 3998 serial8250_unregister_port(priv->line[i]); 3999 4000 /* 4001 * Find the exit quirks. 4002 */ 4003 quirk = find_quirk(priv->dev); 4004 if (quirk->exit) 4005 quirk->exit(priv->dev); 4006 } 4007 4008 void pciserial_remove_ports(struct serial_private *priv) 4009 { 4010 pciserial_detach_ports(priv); 4011 kfree(priv); 4012 } 4013 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4014 4015 void pciserial_suspend_ports(struct serial_private *priv) 4016 { 4017 int i; 4018 4019 for (i = 0; i < priv->nr; i++) 4020 if (priv->line[i] >= 0) 4021 serial8250_suspend_port(priv->line[i]); 4022 4023 /* 4024 * Ensure that every init quirk is properly torn down 4025 */ 4026 if (priv->quirk->exit) 4027 priv->quirk->exit(priv->dev); 4028 } 4029 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4030 4031 void pciserial_resume_ports(struct serial_private *priv) 4032 { 4033 int i; 4034 4035 /* 4036 * Ensure that the board is correctly configured. 4037 */ 4038 if (priv->quirk->init) 4039 priv->quirk->init(priv->dev); 4040 4041 for (i = 0; i < priv->nr; i++) 4042 if (priv->line[i] >= 0) 4043 serial8250_resume_port(priv->line[i]); 4044 } 4045 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4046 4047 /* 4048 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4049 * to the arrangement of serial ports on a PCI card. 4050 */ 4051 static int 4052 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4053 { 4054 struct pci_serial_quirk *quirk; 4055 struct serial_private *priv; 4056 const struct pciserial_board *board; 4057 const struct pci_device_id *exclude; 4058 struct pciserial_board tmp; 4059 int rc; 4060 4061 quirk = find_quirk(dev); 4062 if (quirk->probe) { 4063 rc = quirk->probe(dev); 4064 if (rc) 4065 return rc; 4066 } 4067 4068 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4069 dev_err(&dev->dev, "invalid driver_data: %ld\n", 4070 ent->driver_data); 4071 return -EINVAL; 4072 } 4073 4074 board = &pci_boards[ent->driver_data]; 4075 4076 exclude = pci_match_id(blacklist, dev); 4077 if (exclude) 4078 return -ENODEV; 4079 4080 rc = pcim_enable_device(dev); 4081 pci_save_state(dev); 4082 if (rc) 4083 return rc; 4084 4085 if (ent->driver_data == pbn_default) { 4086 /* 4087 * Use a copy of the pci_board entry for this; 4088 * avoid changing entries in the table. 4089 */ 4090 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4091 board = &tmp; 4092 4093 /* 4094 * We matched one of our class entries. Try to 4095 * determine the parameters of this board. 4096 */ 4097 rc = serial_pci_guess_board(dev, &tmp); 4098 if (rc) 4099 return rc; 4100 } else { 4101 /* 4102 * We matched an explicit entry. If we are able to 4103 * detect this boards settings with our heuristic, 4104 * then we no longer need this entry. 4105 */ 4106 memcpy(&tmp, &pci_boards[pbn_default], 4107 sizeof(struct pciserial_board)); 4108 rc = serial_pci_guess_board(dev, &tmp); 4109 if (rc == 0 && serial_pci_matches(board, &tmp)) 4110 moan_device("Redundant entry in serial pci_table.", 4111 dev); 4112 } 4113 4114 priv = pciserial_init_ports(dev, board); 4115 if (IS_ERR(priv)) 4116 return PTR_ERR(priv); 4117 4118 pci_set_drvdata(dev, priv); 4119 return 0; 4120 } 4121 4122 static void pciserial_remove_one(struct pci_dev *dev) 4123 { 4124 struct serial_private *priv = pci_get_drvdata(dev); 4125 4126 pciserial_remove_ports(priv); 4127 } 4128 4129 #ifdef CONFIG_PM_SLEEP 4130 static int pciserial_suspend_one(struct device *dev) 4131 { 4132 struct serial_private *priv = dev_get_drvdata(dev); 4133 4134 if (priv) 4135 pciserial_suspend_ports(priv); 4136 4137 return 0; 4138 } 4139 4140 static int pciserial_resume_one(struct device *dev) 4141 { 4142 struct pci_dev *pdev = to_pci_dev(dev); 4143 struct serial_private *priv = pci_get_drvdata(pdev); 4144 int err; 4145 4146 if (priv) { 4147 /* 4148 * The device may have been disabled. Re-enable it. 4149 */ 4150 err = pci_enable_device(pdev); 4151 /* FIXME: We cannot simply error out here */ 4152 if (err) 4153 dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); 4154 pciserial_resume_ports(priv); 4155 } 4156 return 0; 4157 } 4158 #endif 4159 4160 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4161 pciserial_resume_one); 4162 4163 static const struct pci_device_id serial_pci_tbl[] = { 4164 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4165 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4166 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, 4167 pbn_b2_8_921600 }, 4168 /* Advantech also use 0x3618 and 0xf618 */ 4169 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4170 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4171 pbn_b0_4_921600 }, 4172 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4173 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, 4174 pbn_b0_4_921600 }, 4175 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4176 PCI_SUBVENDOR_ID_CONNECT_TECH, 4177 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4178 pbn_b1_8_1382400 }, 4179 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4180 PCI_SUBVENDOR_ID_CONNECT_TECH, 4181 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4182 pbn_b1_4_1382400 }, 4183 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, 4184 PCI_SUBVENDOR_ID_CONNECT_TECH, 4185 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4186 pbn_b1_2_1382400 }, 4187 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4188 PCI_SUBVENDOR_ID_CONNECT_TECH, 4189 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, 4190 pbn_b1_8_1382400 }, 4191 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4192 PCI_SUBVENDOR_ID_CONNECT_TECH, 4193 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, 4194 pbn_b1_4_1382400 }, 4195 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4196 PCI_SUBVENDOR_ID_CONNECT_TECH, 4197 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, 4198 pbn_b1_2_1382400 }, 4199 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4200 PCI_SUBVENDOR_ID_CONNECT_TECH, 4201 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, 4202 pbn_b1_8_921600 }, 4203 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4204 PCI_SUBVENDOR_ID_CONNECT_TECH, 4205 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, 4206 pbn_b1_8_921600 }, 4207 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4208 PCI_SUBVENDOR_ID_CONNECT_TECH, 4209 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, 4210 pbn_b1_4_921600 }, 4211 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4212 PCI_SUBVENDOR_ID_CONNECT_TECH, 4213 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, 4214 pbn_b1_4_921600 }, 4215 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4216 PCI_SUBVENDOR_ID_CONNECT_TECH, 4217 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, 4218 pbn_b1_2_921600 }, 4219 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4220 PCI_SUBVENDOR_ID_CONNECT_TECH, 4221 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, 4222 pbn_b1_8_921600 }, 4223 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4224 PCI_SUBVENDOR_ID_CONNECT_TECH, 4225 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, 4226 pbn_b1_8_921600 }, 4227 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4228 PCI_SUBVENDOR_ID_CONNECT_TECH, 4229 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, 4230 pbn_b1_4_921600 }, 4231 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, 4232 PCI_SUBVENDOR_ID_CONNECT_TECH, 4233 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, 4234 pbn_b1_2_1250000 }, 4235 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4236 PCI_SUBVENDOR_ID_CONNECT_TECH, 4237 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, 4238 pbn_b0_2_1843200 }, 4239 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4240 PCI_SUBVENDOR_ID_CONNECT_TECH, 4241 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, 4242 pbn_b0_4_1843200 }, 4243 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4244 PCI_VENDOR_ID_AFAVLAB, 4245 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, 4246 pbn_b0_4_1152000 }, 4247 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, 4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4249 pbn_b2_bt_1_115200 }, 4250 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, 4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4252 pbn_b2_bt_2_115200 }, 4253 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, 4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4255 pbn_b2_bt_4_115200 }, 4256 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, 4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4258 pbn_b2_bt_2_115200 }, 4259 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, 4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4261 pbn_b2_bt_4_115200 }, 4262 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, 4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4264 pbn_b2_8_115200 }, 4265 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, 4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4267 pbn_b2_8_460800 }, 4268 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, 4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4270 pbn_b2_8_115200 }, 4271 4272 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, 4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4274 pbn_b2_bt_2_115200 }, 4275 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, 4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4277 pbn_b2_bt_2_921600 }, 4278 /* 4279 * VScom SPCOM800, from sl@s.pl 4280 */ 4281 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, 4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4283 pbn_b2_8_921600 }, 4284 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, 4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4286 pbn_b2_4_921600 }, 4287 /* Unknown card - subdevice 0x1584 */ 4288 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4289 PCI_VENDOR_ID_PLX, 4290 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, 4291 pbn_b2_4_115200 }, 4292 /* Unknown card - subdevice 0x1588 */ 4293 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4294 PCI_VENDOR_ID_PLX, 4295 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, 4296 pbn_b2_8_115200 }, 4297 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4298 PCI_SUBVENDOR_ID_KEYSPAN, 4299 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, 4300 pbn_panacom }, 4301 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, 4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4303 pbn_panacom4 }, 4304 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, 4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4306 pbn_panacom2 }, 4307 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 4308 PCI_VENDOR_ID_ESDGMBH, 4309 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, 4310 pbn_b2_4_115200 }, 4311 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4312 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4313 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, 4314 pbn_b2_4_460800 }, 4315 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4316 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4317 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, 4318 pbn_b2_8_460800 }, 4319 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4320 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4321 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, 4322 pbn_b2_16_460800 }, 4323 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4324 PCI_SUBVENDOR_ID_CHASE_PCIFAST, 4325 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, 4326 pbn_b2_16_460800 }, 4327 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4328 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4329 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, 4330 pbn_b2_4_460800 }, 4331 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4332 PCI_SUBVENDOR_ID_CHASE_PCIRAS, 4333 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, 4334 pbn_b2_8_460800 }, 4335 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 4336 PCI_SUBVENDOR_ID_EXSYS, 4337 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, 4338 pbn_b2_4_115200 }, 4339 /* 4340 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4341 * (Exoray@isys.ca) 4342 */ 4343 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4344 0x10b5, 0x106a, 0, 0, 4345 pbn_plx_romulus }, 4346 /* 4347 * EndRun Technologies. PCI express device range. 4348 * EndRun PTP/1588 has 2 Native UARTs. 4349 */ 4350 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, 4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4352 pbn_endrun_2_4000000 }, 4353 /* 4354 * Quatech cards. These actually have configurable clocks but for 4355 * now we just use the default. 4356 * 4357 * 100 series are RS232, 200 series RS422, 4358 */ 4359 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, 4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4361 pbn_b1_4_115200 }, 4362 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4364 pbn_b1_2_115200 }, 4365 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, 4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4367 pbn_b2_2_115200 }, 4368 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, 4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4370 pbn_b1_2_115200 }, 4371 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, 4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4373 pbn_b2_2_115200 }, 4374 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, 4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4376 pbn_b1_4_115200 }, 4377 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, 4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4379 pbn_b1_8_115200 }, 4380 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, 4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4382 pbn_b1_8_115200 }, 4383 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, 4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4385 pbn_b1_4_115200 }, 4386 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, 4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4388 pbn_b1_2_115200 }, 4389 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, 4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4391 pbn_b1_4_115200 }, 4392 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4394 pbn_b1_2_115200 }, 4395 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4397 pbn_b2_4_115200 }, 4398 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4400 pbn_b2_2_115200 }, 4401 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4403 pbn_b2_1_115200 }, 4404 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, 4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4406 pbn_b2_4_115200 }, 4407 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, 4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4409 pbn_b2_2_115200 }, 4410 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, 4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4412 pbn_b2_1_115200 }, 4413 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, 4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4415 pbn_b0_8_115200 }, 4416 4417 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4418 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 4419 0, 0, 4420 pbn_b0_4_921600 }, 4421 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4422 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 4423 0, 0, 4424 pbn_b0_4_1152000 }, 4425 { PCI_VENDOR_ID_OXSEMI, 0x9505, 4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4427 pbn_b0_bt_2_921600 }, 4428 4429 /* 4430 * The below card is a little controversial since it is the 4431 * subject of a PCI vendor/device ID clash. (See 4432 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4433 * For now just used the hex ID 0x950a. 4434 */ 4435 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4436 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, 4437 0, 0, pbn_b0_2_115200 }, 4438 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4439 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, 4440 0, 0, pbn_b0_2_115200 }, 4441 { PCI_VENDOR_ID_OXSEMI, 0x950a, 4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4443 pbn_b0_2_1130000 }, 4444 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4445 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, 4446 pbn_b0_1_921600 }, 4447 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4449 pbn_b0_4_115200 }, 4450 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, 4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4452 pbn_b0_bt_2_921600 }, 4453 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, 4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4455 pbn_b2_8_1152000 }, 4456 4457 /* 4458 * Oxford Semiconductor Inc. Tornado PCI express device range. 4459 */ 4460 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ 4461 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4462 pbn_b0_1_4000000 }, 4463 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ 4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4465 pbn_b0_1_4000000 }, 4466 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ 4467 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4468 pbn_oxsemi_1_4000000 }, 4469 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ 4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4471 pbn_oxsemi_1_4000000 }, 4472 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ 4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4474 pbn_b0_1_4000000 }, 4475 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ 4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4477 pbn_b0_1_4000000 }, 4478 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ 4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4480 pbn_oxsemi_1_4000000 }, 4481 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ 4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4483 pbn_oxsemi_1_4000000 }, 4484 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ 4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4486 pbn_b0_1_4000000 }, 4487 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ 4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4489 pbn_b0_1_4000000 }, 4490 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ 4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4492 pbn_b0_1_4000000 }, 4493 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ 4494 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4495 pbn_b0_1_4000000 }, 4496 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ 4497 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4498 pbn_oxsemi_2_4000000 }, 4499 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ 4500 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4501 pbn_oxsemi_2_4000000 }, 4502 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ 4503 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4504 pbn_oxsemi_4_4000000 }, 4505 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ 4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4507 pbn_oxsemi_4_4000000 }, 4508 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ 4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4510 pbn_oxsemi_8_4000000 }, 4511 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4513 pbn_oxsemi_8_4000000 }, 4514 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ 4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4516 pbn_oxsemi_1_4000000 }, 4517 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ 4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4519 pbn_oxsemi_1_4000000 }, 4520 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ 4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4522 pbn_oxsemi_1_4000000 }, 4523 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ 4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4525 pbn_oxsemi_1_4000000 }, 4526 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ 4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4528 pbn_oxsemi_1_4000000 }, 4529 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ 4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4531 pbn_oxsemi_1_4000000 }, 4532 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ 4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4534 pbn_oxsemi_1_4000000 }, 4535 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ 4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4537 pbn_oxsemi_1_4000000 }, 4538 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ 4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4540 pbn_oxsemi_1_4000000 }, 4541 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ 4542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4543 pbn_oxsemi_1_4000000 }, 4544 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ 4545 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4546 pbn_oxsemi_1_4000000 }, 4547 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ 4548 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4549 pbn_oxsemi_1_4000000 }, 4550 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ 4551 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4552 pbn_oxsemi_1_4000000 }, 4553 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ 4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4555 pbn_oxsemi_1_4000000 }, 4556 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ 4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4558 pbn_oxsemi_1_4000000 }, 4559 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ 4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4561 pbn_oxsemi_1_4000000 }, 4562 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ 4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4564 pbn_oxsemi_1_4000000 }, 4565 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ 4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4567 pbn_oxsemi_1_4000000 }, 4568 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ 4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4570 pbn_oxsemi_1_4000000 }, 4571 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ 4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4573 pbn_oxsemi_1_4000000 }, 4574 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ 4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4576 pbn_oxsemi_1_4000000 }, 4577 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ 4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4579 pbn_oxsemi_1_4000000 }, 4580 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ 4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4582 pbn_oxsemi_1_4000000 }, 4583 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ 4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4585 pbn_oxsemi_1_4000000 }, 4586 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ 4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4588 pbn_oxsemi_1_4000000 }, 4589 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ 4590 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4591 pbn_oxsemi_1_4000000 }, 4592 /* 4593 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4594 */ 4595 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ 4596 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, 4597 pbn_oxsemi_1_4000000 }, 4598 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ 4599 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, 4600 pbn_oxsemi_2_4000000 }, 4601 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ 4602 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, 4603 pbn_oxsemi_4_4000000 }, 4604 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ 4605 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, 4606 pbn_oxsemi_8_4000000 }, 4607 4608 /* 4609 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4610 */ 4611 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4612 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, 4613 pbn_oxsemi_2_4000000 }, 4614 4615 /* 4616 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4617 * from skokodyn@yahoo.com 4618 */ 4619 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4620 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, 4621 pbn_sbsxrsio }, 4622 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4623 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, 4624 pbn_sbsxrsio }, 4625 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4626 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, 4627 pbn_sbsxrsio }, 4628 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4629 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, 4630 pbn_sbsxrsio }, 4631 4632 /* 4633 * Digitan DS560-558, from jimd@esoft.com 4634 */ 4635 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, 4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4637 pbn_b1_1_115200 }, 4638 4639 /* 4640 * Titan Electronic cards 4641 * The 400L and 800L have a custom setup quirk. 4642 */ 4643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, 4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4645 pbn_b0_1_921600 }, 4646 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, 4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4648 pbn_b0_2_921600 }, 4649 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, 4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4651 pbn_b0_4_921600 }, 4652 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, 4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4654 pbn_b0_4_921600 }, 4655 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, 4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4657 pbn_b1_1_921600 }, 4658 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, 4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4660 pbn_b1_bt_2_921600 }, 4661 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, 4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4663 pbn_b0_bt_4_921600 }, 4664 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, 4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4666 pbn_b0_bt_8_921600 }, 4667 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, 4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4669 pbn_b4_bt_2_921600 }, 4670 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, 4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4672 pbn_b4_bt_4_921600 }, 4673 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, 4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4675 pbn_b4_bt_8_921600 }, 4676 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, 4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4678 pbn_b0_4_921600 }, 4679 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, 4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4681 pbn_b0_4_921600 }, 4682 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, 4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4684 pbn_b0_4_921600 }, 4685 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, 4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4687 pbn_oxsemi_1_4000000 }, 4688 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, 4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4690 pbn_oxsemi_2_4000000 }, 4691 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, 4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4693 pbn_oxsemi_4_4000000 }, 4694 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, 4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4696 pbn_oxsemi_8_4000000 }, 4697 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, 4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4699 pbn_oxsemi_2_4000000 }, 4700 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, 4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4702 pbn_oxsemi_2_4000000 }, 4703 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, 4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4705 pbn_b0_bt_2_921600 }, 4706 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, 4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4708 pbn_b0_4_921600 }, 4709 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, 4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4711 pbn_b0_4_921600 }, 4712 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, 4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4714 pbn_b0_4_921600 }, 4715 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, 4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4717 pbn_b0_4_921600 }, 4718 4719 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, 4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4721 pbn_b2_1_460800 }, 4722 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, 4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4724 pbn_b2_1_460800 }, 4725 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, 4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4727 pbn_b2_1_460800 }, 4728 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, 4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4730 pbn_b2_bt_2_921600 }, 4731 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, 4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4733 pbn_b2_bt_2_921600 }, 4734 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, 4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4736 pbn_b2_bt_2_921600 }, 4737 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, 4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4739 pbn_b2_bt_4_921600 }, 4740 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, 4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4742 pbn_b2_bt_4_921600 }, 4743 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, 4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4745 pbn_b2_bt_4_921600 }, 4746 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, 4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4748 pbn_b0_1_921600 }, 4749 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, 4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4751 pbn_b0_1_921600 }, 4752 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, 4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4754 pbn_b0_1_921600 }, 4755 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, 4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4757 pbn_b0_bt_2_921600 }, 4758 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, 4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4760 pbn_b0_bt_2_921600 }, 4761 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, 4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4763 pbn_b0_bt_2_921600 }, 4764 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, 4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4766 pbn_b0_bt_4_921600 }, 4767 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, 4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4769 pbn_b0_bt_4_921600 }, 4770 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, 4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4772 pbn_b0_bt_4_921600 }, 4773 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, 4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4775 pbn_b0_bt_8_921600 }, 4776 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, 4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4778 pbn_b0_bt_8_921600 }, 4779 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, 4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4781 pbn_b0_bt_8_921600 }, 4782 4783 /* 4784 * Computone devices submitted by Doug McNash dmcnash@computone.com 4785 */ 4786 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4787 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, 4788 0, 0, pbn_computone_4 }, 4789 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4790 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, 4791 0, 0, pbn_computone_8 }, 4792 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 4793 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, 4794 0, 0, pbn_computone_6 }, 4795 4796 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, 4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4798 pbn_oxsemi }, 4799 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 4800 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, 4801 pbn_b0_bt_1_921600 }, 4802 4803 /* 4804 * Sunix PCI serial boards 4805 */ 4806 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4807 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0, 4808 pbn_sunix_pci_1s }, 4809 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4810 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0, 4811 pbn_sunix_pci_2s }, 4812 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4813 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0, 4814 pbn_sunix_pci_4s }, 4815 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4816 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0, 4817 pbn_sunix_pci_4s }, 4818 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4819 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0, 4820 pbn_sunix_pci_8s }, 4821 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4822 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0, 4823 pbn_sunix_pci_8s }, 4824 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, 4825 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0, 4826 pbn_sunix_pci_16s }, 4827 4828 /* 4829 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 4830 */ 4831 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, 4832 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4833 pbn_b0_bt_8_115200 }, 4834 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, 4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4836 pbn_b0_bt_8_115200 }, 4837 4838 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, 4839 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4840 pbn_b0_bt_2_115200 }, 4841 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, 4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4843 pbn_b0_bt_2_115200 }, 4844 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, 4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4846 pbn_b0_bt_2_115200 }, 4847 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, 4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4849 pbn_b0_bt_2_115200 }, 4850 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, 4851 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4852 pbn_b0_bt_2_115200 }, 4853 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, 4854 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4855 pbn_b0_bt_4_460800 }, 4856 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, 4857 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4858 pbn_b0_bt_4_460800 }, 4859 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, 4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4861 pbn_b0_bt_2_460800 }, 4862 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, 4863 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4864 pbn_b0_bt_2_460800 }, 4865 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, 4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4867 pbn_b0_bt_2_460800 }, 4868 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, 4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4870 pbn_b0_bt_1_115200 }, 4871 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, 4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4873 pbn_b0_bt_1_460800 }, 4874 4875 /* 4876 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 4877 * Cards are identified by their subsystem vendor IDs, which 4878 * (in hex) match the model number. 4879 * 4880 * Note that JC140x are RS422/485 cards which require ox950 4881 * ACR = 0x10, and as such are not currently fully supported. 4882 */ 4883 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4884 0x1204, 0x0004, 0, 0, 4885 pbn_b0_4_921600 }, 4886 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4887 0x1208, 0x0004, 0, 0, 4888 pbn_b0_4_921600 }, 4889 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4890 0x1402, 0x0002, 0, 0, 4891 pbn_b0_2_921600 }, */ 4892 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 4893 0x1404, 0x0004, 0, 0, 4894 pbn_b0_4_921600 }, */ 4895 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 4896 0x1208, 0x0004, 0, 0, 4897 pbn_b0_4_921600 }, 4898 4899 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4900 0x1204, 0x0004, 0, 0, 4901 pbn_b0_4_921600 }, 4902 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 4903 0x1208, 0x0004, 0, 0, 4904 pbn_b0_4_921600 }, 4905 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 4906 0x1208, 0x0004, 0, 0, 4907 pbn_b0_4_921600 }, 4908 /* 4909 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 4910 */ 4911 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, 4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4913 pbn_b1_1_1382400 }, 4914 4915 /* 4916 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 4917 */ 4918 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, 4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4920 pbn_b1_1_1382400 }, 4921 4922 /* 4923 * RAStel 2 port modem, gerg@moreton.com.au 4924 */ 4925 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, 4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4927 pbn_b2_bt_2_115200 }, 4928 4929 /* 4930 * EKF addition for i960 Boards form EKF with serial port 4931 */ 4932 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 4933 0xE4BF, PCI_ANY_ID, 0, 0, 4934 pbn_intel_i960 }, 4935 4936 /* 4937 * Xircom Cardbus/Ethernet combos 4938 */ 4939 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, 4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4941 pbn_b0_1_115200 }, 4942 /* 4943 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 4944 */ 4945 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, 4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4947 pbn_b0_1_115200 }, 4948 4949 /* 4950 * Untested PCI modems, sent in from various folks... 4951 */ 4952 4953 /* 4954 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> 4955 */ 4956 { PCI_VENDOR_ID_ROCKWELL, 0x1004, 4957 0x1048, 0x1500, 0, 0, 4958 pbn_b1_1_115200 }, 4959 4960 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, 4961 0xFF00, 0, 0, 0, 4962 pbn_sgi_ioc3 }, 4963 4964 /* 4965 * HP Diva card 4966 */ 4967 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4968 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, 4969 pbn_b1_1_115200 }, 4970 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, 4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4972 pbn_b0_5_115200 }, 4973 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, 4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4975 pbn_b2_1_115200 }, 4976 4977 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, 4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4979 pbn_b3_2_115200 }, 4980 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, 4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4982 pbn_b3_4_115200 }, 4983 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, 4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4985 pbn_b3_8_115200 }, 4986 /* 4987 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART 4988 */ 4989 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, 4990 PCI_ANY_ID, PCI_ANY_ID, 4991 0, 4992 0, pbn_pericom_PI7C9X7951 }, 4993 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, 4994 PCI_ANY_ID, PCI_ANY_ID, 4995 0, 4996 0, pbn_pericom_PI7C9X7952 }, 4997 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, 4998 PCI_ANY_ID, PCI_ANY_ID, 4999 0, 5000 0, pbn_pericom_PI7C9X7954 }, 5001 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, 5002 PCI_ANY_ID, PCI_ANY_ID, 5003 0, 5004 0, pbn_pericom_PI7C9X7958 }, 5005 /* 5006 * ACCES I/O Products quad 5007 */ 5008 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, 5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5010 pbn_pericom_PI7C9X7952 }, 5011 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, 5012 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5013 pbn_pericom_PI7C9X7952 }, 5014 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, 5015 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5016 pbn_pericom_PI7C9X7954 }, 5017 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, 5018 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5019 pbn_pericom_PI7C9X7954 }, 5020 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, 5021 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5022 pbn_pericom_PI7C9X7952 }, 5023 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, 5024 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5025 pbn_pericom_PI7C9X7952 }, 5026 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, 5027 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5028 pbn_pericom_PI7C9X7954 }, 5029 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, 5030 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5031 pbn_pericom_PI7C9X7954 }, 5032 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, 5033 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5034 pbn_pericom_PI7C9X7952 }, 5035 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, 5036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5037 pbn_pericom_PI7C9X7952 }, 5038 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, 5039 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5040 pbn_pericom_PI7C9X7954 }, 5041 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, 5042 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5043 pbn_pericom_PI7C9X7954 }, 5044 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, 5045 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5046 pbn_pericom_PI7C9X7951 }, 5047 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, 5048 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5049 pbn_pericom_PI7C9X7952 }, 5050 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, 5051 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5052 pbn_pericom_PI7C9X7952 }, 5053 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, 5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5055 pbn_pericom_PI7C9X7954 }, 5056 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, 5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5058 pbn_pericom_PI7C9X7954 }, 5059 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, 5060 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5061 pbn_pericom_PI7C9X7952 }, 5062 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, 5063 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5064 pbn_pericom_PI7C9X7954 }, 5065 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, 5066 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5067 pbn_pericom_PI7C9X7952 }, 5068 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, 5069 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5070 pbn_pericom_PI7C9X7952 }, 5071 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, 5072 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5073 pbn_pericom_PI7C9X7954 }, 5074 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, 5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5076 pbn_pericom_PI7C9X7954 }, 5077 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, 5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5079 pbn_pericom_PI7C9X7952 }, 5080 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, 5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5082 pbn_pericom_PI7C9X7954 }, 5083 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, 5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5085 pbn_pericom_PI7C9X7954 }, 5086 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, 5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5088 pbn_pericom_PI7C9X7958 }, 5089 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, 5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5091 pbn_pericom_PI7C9X7958 }, 5092 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, 5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5094 pbn_pericom_PI7C9X7954 }, 5095 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, 5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5097 pbn_pericom_PI7C9X7958 }, 5098 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, 5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5100 pbn_pericom_PI7C9X7954 }, 5101 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, 5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5103 pbn_pericom_PI7C9X7958 }, 5104 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, 5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5106 pbn_pericom_PI7C9X7954 }, 5107 /* 5108 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) 5109 */ 5110 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, 5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5112 pbn_b0_1_115200 }, 5113 /* 5114 * ITE 5115 */ 5116 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, 5117 PCI_ANY_ID, PCI_ANY_ID, 5118 0, 0, 5119 pbn_b1_bt_1_115200 }, 5120 5121 /* 5122 * IntaShield IS-200 5123 */ 5124 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 5126 pbn_b2_2_115200 }, 5127 /* 5128 * IntaShield IS-400 5129 */ 5130 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5132 pbn_b2_4_115200 }, 5133 /* 5134 * BrainBoxes UC-260 5135 */ 5136 { PCI_VENDOR_ID_INTASHIELD, 0x0D21, 5137 PCI_ANY_ID, PCI_ANY_ID, 5138 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5139 pbn_b2_4_115200 }, 5140 { PCI_VENDOR_ID_INTASHIELD, 0x0E34, 5141 PCI_ANY_ID, PCI_ANY_ID, 5142 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, 5143 pbn_b2_4_115200 }, 5144 /* 5145 * Perle PCI-RAS cards 5146 */ 5147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5148 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, 5149 0, 0, pbn_b2_4_921600 }, 5150 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, 5151 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, 5152 0, 0, pbn_b2_8_921600 }, 5153 5154 /* 5155 * Mainpine series cards: Fairly standard layout but fools 5156 * parts of the autodetect in some cases and uses otherwise 5157 * unmatched communications subclasses in the PCI Express case 5158 */ 5159 5160 { /* RockForceDUO */ 5161 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5162 PCI_VENDOR_ID_MAINPINE, 0x0200, 5163 0, 0, pbn_b0_2_115200 }, 5164 { /* RockForceQUATRO */ 5165 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5166 PCI_VENDOR_ID_MAINPINE, 0x0300, 5167 0, 0, pbn_b0_4_115200 }, 5168 { /* RockForceDUO+ */ 5169 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5170 PCI_VENDOR_ID_MAINPINE, 0x0400, 5171 0, 0, pbn_b0_2_115200 }, 5172 { /* RockForceQUATRO+ */ 5173 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5174 PCI_VENDOR_ID_MAINPINE, 0x0500, 5175 0, 0, pbn_b0_4_115200 }, 5176 { /* RockForce+ */ 5177 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5178 PCI_VENDOR_ID_MAINPINE, 0x0600, 5179 0, 0, pbn_b0_2_115200 }, 5180 { /* RockForce+ */ 5181 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5182 PCI_VENDOR_ID_MAINPINE, 0x0700, 5183 0, 0, pbn_b0_4_115200 }, 5184 { /* RockForceOCTO+ */ 5185 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5186 PCI_VENDOR_ID_MAINPINE, 0x0800, 5187 0, 0, pbn_b0_8_115200 }, 5188 { /* RockForceDUO+ */ 5189 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5190 PCI_VENDOR_ID_MAINPINE, 0x0C00, 5191 0, 0, pbn_b0_2_115200 }, 5192 { /* RockForceQUARTRO+ */ 5193 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5194 PCI_VENDOR_ID_MAINPINE, 0x0D00, 5195 0, 0, pbn_b0_4_115200 }, 5196 { /* RockForceOCTO+ */ 5197 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5198 PCI_VENDOR_ID_MAINPINE, 0x1D00, 5199 0, 0, pbn_b0_8_115200 }, 5200 { /* RockForceD1 */ 5201 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5202 PCI_VENDOR_ID_MAINPINE, 0x2000, 5203 0, 0, pbn_b0_1_115200 }, 5204 { /* RockForceF1 */ 5205 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5206 PCI_VENDOR_ID_MAINPINE, 0x2100, 5207 0, 0, pbn_b0_1_115200 }, 5208 { /* RockForceD2 */ 5209 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5210 PCI_VENDOR_ID_MAINPINE, 0x2200, 5211 0, 0, pbn_b0_2_115200 }, 5212 { /* RockForceF2 */ 5213 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5214 PCI_VENDOR_ID_MAINPINE, 0x2300, 5215 0, 0, pbn_b0_2_115200 }, 5216 { /* RockForceD4 */ 5217 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5218 PCI_VENDOR_ID_MAINPINE, 0x2400, 5219 0, 0, pbn_b0_4_115200 }, 5220 { /* RockForceF4 */ 5221 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5222 PCI_VENDOR_ID_MAINPINE, 0x2500, 5223 0, 0, pbn_b0_4_115200 }, 5224 { /* RockForceD8 */ 5225 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5226 PCI_VENDOR_ID_MAINPINE, 0x2600, 5227 0, 0, pbn_b0_8_115200 }, 5228 { /* RockForceF8 */ 5229 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5230 PCI_VENDOR_ID_MAINPINE, 0x2700, 5231 0, 0, pbn_b0_8_115200 }, 5232 { /* IQ Express D1 */ 5233 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5234 PCI_VENDOR_ID_MAINPINE, 0x3000, 5235 0, 0, pbn_b0_1_115200 }, 5236 { /* IQ Express F1 */ 5237 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5238 PCI_VENDOR_ID_MAINPINE, 0x3100, 5239 0, 0, pbn_b0_1_115200 }, 5240 { /* IQ Express D2 */ 5241 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5242 PCI_VENDOR_ID_MAINPINE, 0x3200, 5243 0, 0, pbn_b0_2_115200 }, 5244 { /* IQ Express F2 */ 5245 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5246 PCI_VENDOR_ID_MAINPINE, 0x3300, 5247 0, 0, pbn_b0_2_115200 }, 5248 { /* IQ Express D4 */ 5249 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5250 PCI_VENDOR_ID_MAINPINE, 0x3400, 5251 0, 0, pbn_b0_4_115200 }, 5252 { /* IQ Express F4 */ 5253 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5254 PCI_VENDOR_ID_MAINPINE, 0x3500, 5255 0, 0, pbn_b0_4_115200 }, 5256 { /* IQ Express D8 */ 5257 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5258 PCI_VENDOR_ID_MAINPINE, 0x3C00, 5259 0, 0, pbn_b0_8_115200 }, 5260 { /* IQ Express F8 */ 5261 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5262 PCI_VENDOR_ID_MAINPINE, 0x3D00, 5263 0, 0, pbn_b0_8_115200 }, 5264 5265 5266 /* 5267 * PA Semi PA6T-1682M on-chip UART 5268 */ 5269 { PCI_VENDOR_ID_PASEMI, 0xa004, 5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5271 pbn_pasemi_1682M }, 5272 5273 /* 5274 * National Instruments 5275 */ 5276 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, 5277 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5278 pbn_b1_16_115200 }, 5279 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, 5280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5281 pbn_b1_8_115200 }, 5282 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, 5283 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5284 pbn_b1_bt_4_115200 }, 5285 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, 5286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5287 pbn_b1_bt_2_115200 }, 5288 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, 5289 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5290 pbn_b1_bt_4_115200 }, 5291 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, 5292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5293 pbn_b1_bt_2_115200 }, 5294 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, 5295 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5296 pbn_b1_16_115200 }, 5297 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, 5298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5299 pbn_b1_8_115200 }, 5300 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, 5301 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5302 pbn_b1_bt_4_115200 }, 5303 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, 5304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5305 pbn_b1_bt_2_115200 }, 5306 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, 5307 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5308 pbn_b1_bt_4_115200 }, 5309 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, 5310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5311 pbn_b1_bt_2_115200 }, 5312 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, 5313 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5314 pbn_ni8430_2 }, 5315 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, 5316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5317 pbn_ni8430_2 }, 5318 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, 5319 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5320 pbn_ni8430_4 }, 5321 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, 5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5323 pbn_ni8430_4 }, 5324 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, 5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5326 pbn_ni8430_8 }, 5327 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, 5328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5329 pbn_ni8430_8 }, 5330 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, 5331 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5332 pbn_ni8430_16 }, 5333 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, 5334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5335 pbn_ni8430_16 }, 5336 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, 5337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5338 pbn_ni8430_2 }, 5339 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, 5340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5341 pbn_ni8430_2 }, 5342 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, 5343 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5344 pbn_ni8430_4 }, 5345 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, 5346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5347 pbn_ni8430_4 }, 5348 5349 /* 5350 * MOXA 5351 */ 5352 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5354 pbn_moxa8250_2p }, 5355 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5357 pbn_moxa8250_2p }, 5358 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5360 pbn_moxa8250_4p }, 5361 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5363 pbn_moxa8250_4p }, 5364 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5365 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5366 pbn_moxa8250_8p }, 5367 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5369 pbn_moxa8250_8p }, 5370 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5371 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5372 pbn_moxa8250_8p }, 5373 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5375 pbn_moxa8250_8p }, 5376 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5377 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5378 pbn_moxa8250_2p }, 5379 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5381 pbn_moxa8250_4p }, 5382 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5383 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5384 pbn_moxa8250_8p }, 5385 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5387 pbn_moxa8250_8p }, 5388 5389 /* 5390 * ADDI-DATA GmbH communication cards <info@addi-data.com> 5391 */ 5392 { PCI_VENDOR_ID_ADDIDATA, 5393 PCI_DEVICE_ID_ADDIDATA_APCI7500, 5394 PCI_ANY_ID, 5395 PCI_ANY_ID, 5396 0, 5397 0, 5398 pbn_b0_4_115200 }, 5399 5400 { PCI_VENDOR_ID_ADDIDATA, 5401 PCI_DEVICE_ID_ADDIDATA_APCI7420, 5402 PCI_ANY_ID, 5403 PCI_ANY_ID, 5404 0, 5405 0, 5406 pbn_b0_2_115200 }, 5407 5408 { PCI_VENDOR_ID_ADDIDATA, 5409 PCI_DEVICE_ID_ADDIDATA_APCI7300, 5410 PCI_ANY_ID, 5411 PCI_ANY_ID, 5412 0, 5413 0, 5414 pbn_b0_1_115200 }, 5415 5416 { PCI_VENDOR_ID_AMCC, 5417 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 5418 PCI_ANY_ID, 5419 PCI_ANY_ID, 5420 0, 5421 0, 5422 pbn_b1_8_115200 }, 5423 5424 { PCI_VENDOR_ID_ADDIDATA, 5425 PCI_DEVICE_ID_ADDIDATA_APCI7500_2, 5426 PCI_ANY_ID, 5427 PCI_ANY_ID, 5428 0, 5429 0, 5430 pbn_b0_4_115200 }, 5431 5432 { PCI_VENDOR_ID_ADDIDATA, 5433 PCI_DEVICE_ID_ADDIDATA_APCI7420_2, 5434 PCI_ANY_ID, 5435 PCI_ANY_ID, 5436 0, 5437 0, 5438 pbn_b0_2_115200 }, 5439 5440 { PCI_VENDOR_ID_ADDIDATA, 5441 PCI_DEVICE_ID_ADDIDATA_APCI7300_2, 5442 PCI_ANY_ID, 5443 PCI_ANY_ID, 5444 0, 5445 0, 5446 pbn_b0_1_115200 }, 5447 5448 { PCI_VENDOR_ID_ADDIDATA, 5449 PCI_DEVICE_ID_ADDIDATA_APCI7500_3, 5450 PCI_ANY_ID, 5451 PCI_ANY_ID, 5452 0, 5453 0, 5454 pbn_b0_4_115200 }, 5455 5456 { PCI_VENDOR_ID_ADDIDATA, 5457 PCI_DEVICE_ID_ADDIDATA_APCI7420_3, 5458 PCI_ANY_ID, 5459 PCI_ANY_ID, 5460 0, 5461 0, 5462 pbn_b0_2_115200 }, 5463 5464 { PCI_VENDOR_ID_ADDIDATA, 5465 PCI_DEVICE_ID_ADDIDATA_APCI7300_3, 5466 PCI_ANY_ID, 5467 PCI_ANY_ID, 5468 0, 5469 0, 5470 pbn_b0_1_115200 }, 5471 5472 { PCI_VENDOR_ID_ADDIDATA, 5473 PCI_DEVICE_ID_ADDIDATA_APCI7800_3, 5474 PCI_ANY_ID, 5475 PCI_ANY_ID, 5476 0, 5477 0, 5478 pbn_b0_8_115200 }, 5479 5480 { PCI_VENDOR_ID_ADDIDATA, 5481 PCI_DEVICE_ID_ADDIDATA_APCIe7500, 5482 PCI_ANY_ID, 5483 PCI_ANY_ID, 5484 0, 5485 0, 5486 pbn_ADDIDATA_PCIe_4_3906250 }, 5487 5488 { PCI_VENDOR_ID_ADDIDATA, 5489 PCI_DEVICE_ID_ADDIDATA_APCIe7420, 5490 PCI_ANY_ID, 5491 PCI_ANY_ID, 5492 0, 5493 0, 5494 pbn_ADDIDATA_PCIe_2_3906250 }, 5495 5496 { PCI_VENDOR_ID_ADDIDATA, 5497 PCI_DEVICE_ID_ADDIDATA_APCIe7300, 5498 PCI_ANY_ID, 5499 PCI_ANY_ID, 5500 0, 5501 0, 5502 pbn_ADDIDATA_PCIe_1_3906250 }, 5503 5504 { PCI_VENDOR_ID_ADDIDATA, 5505 PCI_DEVICE_ID_ADDIDATA_APCIe7800, 5506 PCI_ANY_ID, 5507 PCI_ANY_ID, 5508 0, 5509 0, 5510 pbn_ADDIDATA_PCIe_8_3906250 }, 5511 5512 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, 5513 PCI_VENDOR_ID_IBM, 0x0299, 5514 0, 0, pbn_b0_bt_2_115200 }, 5515 5516 /* 5517 * other NetMos 9835 devices are most likely handled by the 5518 * parport_serial driver, check drivers/parport/parport_serial.c 5519 * before adding them here. 5520 */ 5521 5522 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, 5523 0xA000, 0x1000, 5524 0, 0, pbn_b0_1_115200 }, 5525 5526 /* the 9901 is a rebranded 9912 */ 5527 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, 5528 0xA000, 0x1000, 5529 0, 0, pbn_b0_1_115200 }, 5530 5531 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, 5532 0xA000, 0x1000, 5533 0, 0, pbn_b0_1_115200 }, 5534 5535 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, 5536 0xA000, 0x1000, 5537 0, 0, pbn_b0_1_115200 }, 5538 5539 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5540 0xA000, 0x1000, 5541 0, 0, pbn_b0_1_115200 }, 5542 5543 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, 5544 0xA000, 0x3002, 5545 0, 0, pbn_NETMOS9900_2s_115200 }, 5546 5547 /* 5548 * Best Connectivity and Rosewill PCI Multi I/O cards 5549 */ 5550 5551 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5552 0xA000, 0x1000, 5553 0, 0, pbn_b0_1_115200 }, 5554 5555 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5556 0xA000, 0x3002, 5557 0, 0, pbn_b0_bt_2_115200 }, 5558 5559 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, 5560 0xA000, 0x3004, 5561 0, 0, pbn_b0_bt_4_115200 }, 5562 /* Intel CE4100 */ 5563 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, 5564 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5565 pbn_ce4100_1_115200 }, 5566 5567 /* 5568 * Cronyx Omega PCI 5569 */ 5570 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 5571 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5572 pbn_omegapci }, 5573 5574 /* 5575 * Broadcom TruManage 5576 */ 5577 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 5578 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5579 pbn_brcm_trumanage }, 5580 5581 /* 5582 * AgeStar as-prs2-009 5583 */ 5584 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, 5585 PCI_ANY_ID, PCI_ANY_ID, 5586 0, 0, pbn_b0_bt_2_115200 }, 5587 5588 /* 5589 * WCH CH353 series devices: The 2S1P is handled by parport_serial 5590 * so not listed here. 5591 */ 5592 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, 5593 PCI_ANY_ID, PCI_ANY_ID, 5594 0, 0, pbn_b0_bt_4_115200 }, 5595 5596 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, 5597 PCI_ANY_ID, PCI_ANY_ID, 5598 0, 0, pbn_b0_bt_2_115200 }, 5599 5600 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, 5601 PCI_ANY_ID, PCI_ANY_ID, 5602 0, 0, pbn_b0_bt_4_115200 }, 5603 5604 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, 5605 PCI_ANY_ID, PCI_ANY_ID, 5606 0, 0, pbn_wch382_2 }, 5607 5608 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, 5609 PCI_ANY_ID, PCI_ANY_ID, 5610 0, 0, pbn_wch384_4 }, 5611 5612 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_8S, 5613 PCI_ANY_ID, PCI_ANY_ID, 5614 0, 0, pbn_wch384_8 }, 5615 /* 5616 * Realtek RealManage 5617 */ 5618 { PCI_VENDOR_ID_REALTEK, 0x816a, 5619 PCI_ANY_ID, PCI_ANY_ID, 5620 0, 0, pbn_b0_1_115200 }, 5621 5622 { PCI_VENDOR_ID_REALTEK, 0x816b, 5623 PCI_ANY_ID, PCI_ANY_ID, 5624 0, 0, pbn_b0_1_115200 }, 5625 5626 /* Fintek PCI serial cards */ 5627 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, 5628 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, 5629 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, 5630 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A }, 5631 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A }, 5632 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A }, 5633 5634 /* MKS Tenta SCOM-080x serial cards */ 5635 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, 5636 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, 5637 5638 /* Amazon PCI serial device */ 5639 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 }, 5640 5641 /* 5642 * These entries match devices with class COMMUNICATION_SERIAL, 5643 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 5644 */ 5645 { PCI_ANY_ID, PCI_ANY_ID, 5646 PCI_ANY_ID, PCI_ANY_ID, 5647 PCI_CLASS_COMMUNICATION_SERIAL << 8, 5648 0xffff00, pbn_default }, 5649 { PCI_ANY_ID, PCI_ANY_ID, 5650 PCI_ANY_ID, PCI_ANY_ID, 5651 PCI_CLASS_COMMUNICATION_MODEM << 8, 5652 0xffff00, pbn_default }, 5653 { PCI_ANY_ID, PCI_ANY_ID, 5654 PCI_ANY_ID, PCI_ANY_ID, 5655 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5656 0xffff00, pbn_default }, 5657 { 0, } 5658 }; 5659 5660 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 5661 pci_channel_state_t state) 5662 { 5663 struct serial_private *priv = pci_get_drvdata(dev); 5664 5665 if (state == pci_channel_io_perm_failure) 5666 return PCI_ERS_RESULT_DISCONNECT; 5667 5668 if (priv) 5669 pciserial_detach_ports(priv); 5670 5671 pci_disable_device(dev); 5672 5673 return PCI_ERS_RESULT_NEED_RESET; 5674 } 5675 5676 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 5677 { 5678 int rc; 5679 5680 rc = pci_enable_device(dev); 5681 5682 if (rc) 5683 return PCI_ERS_RESULT_DISCONNECT; 5684 5685 pci_restore_state(dev); 5686 pci_save_state(dev); 5687 5688 return PCI_ERS_RESULT_RECOVERED; 5689 } 5690 5691 static void serial8250_io_resume(struct pci_dev *dev) 5692 { 5693 struct serial_private *priv = pci_get_drvdata(dev); 5694 struct serial_private *new; 5695 5696 if (!priv) 5697 return; 5698 5699 new = pciserial_init_ports(dev, priv->board); 5700 if (!IS_ERR(new)) { 5701 pci_set_drvdata(dev, new); 5702 kfree(priv); 5703 } 5704 } 5705 5706 static const struct pci_error_handlers serial8250_err_handler = { 5707 .error_detected = serial8250_io_error_detected, 5708 .slot_reset = serial8250_io_slot_reset, 5709 .resume = serial8250_io_resume, 5710 }; 5711 5712 static struct pci_driver serial_pci_driver = { 5713 .name = "serial", 5714 .probe = pciserial_init_one, 5715 .remove = pciserial_remove_one, 5716 .driver = { 5717 .pm = &pciserial_pm_ops, 5718 }, 5719 .id_table = serial_pci_tbl, 5720 .err_handler = &serial8250_err_handler, 5721 }; 5722 5723 module_pci_driver(serial_pci_driver); 5724 5725 MODULE_LICENSE("GPL"); 5726 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 5727 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 5728