1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/serial_8250.h> 16 #include <linux/serial_reg.h> 17 #include <linux/tty_flip.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/delay.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/console.h> 27 #include <linux/pm_qos.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sys_soc.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 #define OMAP_UART_REGSHIFT 2 36 37 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 38 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 39 #define OMAP_DMA_TX_KICK (1 << 2) 40 /* 41 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 42 * The same errata is applicable to AM335x and DRA7x processors too. 43 */ 44 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 45 #define UART_HAS_EFR2 BIT(4) 46 #define UART_HAS_RHR_IT_DIS BIT(5) 47 #define UART_RX_TIMEOUT_QUIRK BIT(6) 48 #define UART_HAS_NATIVE_RS485 BIT(7) 49 50 #define OMAP_UART_FCR_RX_TRIG 6 51 #define OMAP_UART_FCR_TX_TRIG 4 52 53 /* SCR register bitmasks */ 54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 56 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 57 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 58 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 59 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 60 61 /* MVR register bitmasks */ 62 #define OMAP_UART_MVR_SCHEME_SHIFT 30 63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 65 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 66 #define OMAP_UART_MVR_MAJ_MASK 0x700 67 #define OMAP_UART_MVR_MAJ_SHIFT 8 68 #define OMAP_UART_MVR_MIN_MASK 0x3f 69 70 /* SYSC register bitmasks */ 71 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 72 73 /* SYSS register bitmasks */ 74 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 75 76 #define UART_TI752_TLR_TX 0 77 #define UART_TI752_TLR_RX 4 78 79 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 80 #define TRIGGER_FCR_MASK(x) (x & 3) 81 82 /* Enable XON/XOFF flow control on output */ 83 #define OMAP_UART_SW_TX 0x08 84 /* Enable XON/XOFF flow control on input */ 85 #define OMAP_UART_SW_RX 0x02 86 87 #define OMAP_UART_WER_MOD_WKUP 0x7f 88 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 89 90 #define TX_TRIGGER 1 91 #define RX_TRIGGER 48 92 93 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 94 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 95 96 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 97 98 #define OMAP_UART_REV_46 0x0406 99 #define OMAP_UART_REV_52 0x0502 100 #define OMAP_UART_REV_63 0x0603 101 102 /* Interrupt Enable Register 2 */ 103 #define UART_OMAP_IER2 0x1B 104 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 105 106 /* Mode Definition Register 3 */ 107 #define UART_OMAP_MDR3 0x20 108 #define UART_OMAP_MDR3_DIR_POL BIT(3) 109 #define UART_OMAP_MDR3_DIR_EN BIT(4) 110 111 /* Enhanced features register 2 */ 112 #define UART_OMAP_EFR2 0x23 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 114 115 /* RX FIFO occupancy indicator */ 116 #define UART_OMAP_RX_LVL 0x19 117 118 struct omap8250_priv { 119 void __iomem *membase; 120 int line; 121 u8 habit; 122 u8 mdr1; 123 u8 mdr3; 124 u8 efr; 125 u8 scr; 126 u8 wer; 127 u8 xon; 128 u8 xoff; 129 u8 delayed_restore; 130 u16 quot; 131 132 u8 tx_trigger; 133 u8 rx_trigger; 134 bool is_suspending; 135 int wakeirq; 136 int wakeups_enabled; 137 u32 latency; 138 u32 calc_latency; 139 struct pm_qos_request pm_qos_request; 140 struct work_struct qos_work; 141 struct uart_8250_dma omap8250_dma; 142 spinlock_t rx_dma_lock; 143 bool rx_dma_broken; 144 bool throttled; 145 }; 146 147 struct omap8250_dma_params { 148 u32 rx_size; 149 u8 rx_trigger; 150 u8 tx_trigger; 151 }; 152 153 struct omap8250_platdata { 154 struct omap8250_dma_params *dma_params; 155 u8 habit; 156 }; 157 158 #ifdef CONFIG_SERIAL_8250_DMA 159 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 160 #else 161 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 162 #endif 163 164 static u32 uart_read(struct omap8250_priv *priv, u32 reg) 165 { 166 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT)); 167 } 168 169 /* 170 * Called on runtime PM resume path from omap8250_restore_regs(), and 171 * omap8250_set_mctrl(). 172 */ 173 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 174 { 175 struct uart_8250_port *up = up_to_u8250p(port); 176 struct omap8250_priv *priv = up->port.private_data; 177 u8 lcr; 178 179 serial8250_do_set_mctrl(port, mctrl); 180 181 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 182 /* 183 * Turn off autoRTS if RTS is lowered and restore autoRTS 184 * setting if RTS is raised 185 */ 186 lcr = serial_in(up, UART_LCR); 187 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 188 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 189 priv->efr |= UART_EFR_RTS; 190 else 191 priv->efr &= ~UART_EFR_RTS; 192 serial_out(up, UART_EFR, priv->efr); 193 serial_out(up, UART_LCR, lcr); 194 } 195 } 196 197 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 198 { 199 int err; 200 201 err = pm_runtime_resume_and_get(port->dev); 202 if (err) 203 return; 204 205 __omap8250_set_mctrl(port, mctrl); 206 207 pm_runtime_mark_last_busy(port->dev); 208 pm_runtime_put_autosuspend(port->dev); 209 } 210 211 /* 212 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 213 * The access to uart register after MDR1 Access 214 * causes UART to corrupt data. 215 * 216 * Need a delay = 217 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 218 * give 10 times as much 219 */ 220 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 221 struct omap8250_priv *priv) 222 { 223 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 224 udelay(2); 225 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 226 UART_FCR_CLEAR_RCVR); 227 } 228 229 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 230 struct omap8250_priv *priv) 231 { 232 unsigned int uartclk = port->uartclk; 233 unsigned int div_13, div_16; 234 unsigned int abs_d13, abs_d16; 235 236 /* 237 * Old custom speed handling. 238 */ 239 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 240 priv->quot = port->custom_divisor & UART_DIV_MAX; 241 /* 242 * I assume that nobody is using this. But hey, if somebody 243 * would like to specify the divisor _and_ the mode then the 244 * driver is ready and waiting for it. 245 */ 246 if (port->custom_divisor & (1 << 16)) 247 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 248 else 249 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 250 return; 251 } 252 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 253 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 254 255 if (!div_13) 256 div_13 = 1; 257 if (!div_16) 258 div_16 = 1; 259 260 abs_d13 = abs(baud - uartclk / 13 / div_13); 261 abs_d16 = abs(baud - uartclk / 16 / div_16); 262 263 if (abs_d13 >= abs_d16) { 264 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 265 priv->quot = div_16; 266 } else { 267 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 268 priv->quot = div_13; 269 } 270 } 271 272 static void omap8250_update_scr(struct uart_8250_port *up, 273 struct omap8250_priv *priv) 274 { 275 u8 old_scr; 276 277 old_scr = serial_in(up, UART_OMAP_SCR); 278 if (old_scr == priv->scr) 279 return; 280 281 /* 282 * The manual recommends not to enable the DMA mode selector in the SCR 283 * (instead of the FCR) register _and_ selecting the DMA mode as one 284 * register write because this may lead to malfunction. 285 */ 286 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 287 serial_out(up, UART_OMAP_SCR, 288 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 289 serial_out(up, UART_OMAP_SCR, priv->scr); 290 } 291 292 static void omap8250_update_mdr1(struct uart_8250_port *up, 293 struct omap8250_priv *priv) 294 { 295 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 296 omap_8250_mdr1_errataset(up, priv); 297 else 298 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 299 } 300 301 static void omap8250_restore_regs(struct uart_8250_port *up) 302 { 303 struct omap8250_priv *priv = up->port.private_data; 304 struct uart_8250_dma *dma = up->dma; 305 u8 mcr = serial8250_in_MCR(up); 306 307 /* Port locked to synchronize UART_IER access against the console. */ 308 lockdep_assert_held_once(&up->port.lock); 309 310 if (dma && dma->tx_running) { 311 /* 312 * TCSANOW requests the change to occur immediately however if 313 * we have a TX-DMA operation in progress then it has been 314 * observed that it might stall and never complete. Therefore we 315 * delay DMA completes to prevent this hang from happen. 316 */ 317 priv->delayed_restore = 1; 318 return; 319 } 320 321 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 322 serial_out(up, UART_EFR, UART_EFR_ECB); 323 324 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 325 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 326 serial_out(up, UART_FCR, up->fcr); 327 328 omap8250_update_scr(up, priv); 329 330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 331 332 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 333 OMAP_UART_TCR_HALT(52)); 334 serial_out(up, UART_TI752_TLR, 335 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 336 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 337 338 serial_out(up, UART_LCR, 0); 339 340 /* drop TCR + TLR access, we setup XON/XOFF later */ 341 serial8250_out_MCR(up, mcr); 342 343 serial_out(up, UART_IER, up->ier); 344 345 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 346 serial_dl_write(up, priv->quot); 347 348 serial_out(up, UART_EFR, priv->efr); 349 350 /* Configure flow control */ 351 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 352 serial_out(up, UART_XON1, priv->xon); 353 serial_out(up, UART_XOFF1, priv->xoff); 354 355 serial_out(up, UART_LCR, up->lcr); 356 357 omap8250_update_mdr1(up, priv); 358 359 __omap8250_set_mctrl(&up->port, up->port.mctrl); 360 361 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 362 363 if (up->port.rs485.flags & SER_RS485_ENABLED && 364 up->port.rs485_config == serial8250_em485_config) 365 serial8250_em485_stop_tx(up); 366 } 367 368 /* 369 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 370 * some differences in how we want to handle flow control. 371 */ 372 static void omap_8250_set_termios(struct uart_port *port, 373 struct ktermios *termios, 374 const struct ktermios *old) 375 { 376 struct uart_8250_port *up = up_to_u8250p(port); 377 struct omap8250_priv *priv = up->port.private_data; 378 unsigned char cval = 0; 379 unsigned int baud; 380 381 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 382 383 if (termios->c_cflag & CSTOPB) 384 cval |= UART_LCR_STOP; 385 if (termios->c_cflag & PARENB) 386 cval |= UART_LCR_PARITY; 387 if (!(termios->c_cflag & PARODD)) 388 cval |= UART_LCR_EPAR; 389 if (termios->c_cflag & CMSPAR) 390 cval |= UART_LCR_SPAR; 391 392 /* 393 * Ask the core to calculate the divisor for us. 394 */ 395 baud = uart_get_baud_rate(port, termios, old, 396 port->uartclk / 16 / UART_DIV_MAX, 397 port->uartclk / 13); 398 omap_8250_get_divisor(port, baud, priv); 399 400 /* 401 * Ok, we're now changing the port state. Do it with 402 * interrupts disabled. 403 */ 404 pm_runtime_get_sync(port->dev); 405 spin_lock_irq(&port->lock); 406 407 /* 408 * Update the per-port timeout. 409 */ 410 uart_update_timeout(port, termios->c_cflag, baud); 411 412 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 413 if (termios->c_iflag & INPCK) 414 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 415 if (termios->c_iflag & (IGNBRK | PARMRK)) 416 up->port.read_status_mask |= UART_LSR_BI; 417 418 /* 419 * Characters to ignore 420 */ 421 up->port.ignore_status_mask = 0; 422 if (termios->c_iflag & IGNPAR) 423 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 424 if (termios->c_iflag & IGNBRK) { 425 up->port.ignore_status_mask |= UART_LSR_BI; 426 /* 427 * If we're ignoring parity and break indicators, 428 * ignore overruns too (for real raw support). 429 */ 430 if (termios->c_iflag & IGNPAR) 431 up->port.ignore_status_mask |= UART_LSR_OE; 432 } 433 434 /* 435 * ignore all characters if CREAD is not set 436 */ 437 if ((termios->c_cflag & CREAD) == 0) 438 up->port.ignore_status_mask |= UART_LSR_DR; 439 440 /* 441 * Modem status interrupts 442 */ 443 up->ier &= ~UART_IER_MSI; 444 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 445 up->ier |= UART_IER_MSI; 446 447 up->lcr = cval; 448 /* Up to here it was mostly serial8250_do_set_termios() */ 449 450 /* 451 * We enable TRIG_GRANU for RX and TX and additionally we set 452 * SCR_TX_EMPTY bit. The result is the following: 453 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 454 * - less than RX_TRIGGER number of bytes will also cause an interrupt 455 * once the UART decides that there no new bytes arriving. 456 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 457 * empty - the trigger level is ignored here. 458 * 459 * Once DMA is enabled: 460 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 461 * bytes in the TX FIFO. On each assert the DMA engine will move 462 * TX_TRIGGER bytes into the FIFO. 463 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 464 * the FIFO and move RX_TRIGGER bytes. 465 * This is because threshold and trigger values are the same. 466 */ 467 up->fcr = UART_FCR_ENABLE_FIFO; 468 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 469 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 470 471 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 472 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 473 474 if (up->dma) 475 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 476 OMAP_UART_SCR_DMAMODE_CTL; 477 478 priv->xon = termios->c_cc[VSTART]; 479 priv->xoff = termios->c_cc[VSTOP]; 480 481 priv->efr = 0; 482 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 483 484 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 485 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 486 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 487 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 488 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 489 priv->efr |= UART_EFR_CTS; 490 } else if (up->port.flags & UPF_SOFT_FLOW) { 491 /* 492 * OMAP rx s/w flow control is borked; the transmitter remains 493 * stuck off even if rx flow control is subsequently disabled 494 */ 495 496 /* 497 * IXOFF Flag: 498 * Enable XON/XOFF flow control on output. 499 * Transmit XON1, XOFF1 500 */ 501 if (termios->c_iflag & IXOFF) { 502 up->port.status |= UPSTAT_AUTOXOFF; 503 priv->efr |= OMAP_UART_SW_TX; 504 } 505 } 506 omap8250_restore_regs(up); 507 508 spin_unlock_irq(&up->port.lock); 509 pm_runtime_mark_last_busy(port->dev); 510 pm_runtime_put_autosuspend(port->dev); 511 512 /* calculate wakeup latency constraint */ 513 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 514 priv->latency = priv->calc_latency; 515 516 schedule_work(&priv->qos_work); 517 518 /* Don't rewrite B0 */ 519 if (tty_termios_baud_rate(termios)) 520 tty_termios_encode_baud_rate(termios, baud, baud); 521 } 522 523 /* same as 8250 except that we may have extra flow bits set in EFR */ 524 static void omap_8250_pm(struct uart_port *port, unsigned int state, 525 unsigned int oldstate) 526 { 527 struct uart_8250_port *up = up_to_u8250p(port); 528 u8 efr; 529 530 pm_runtime_get_sync(port->dev); 531 532 /* Synchronize UART_IER access against the console. */ 533 spin_lock_irq(&port->lock); 534 535 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 536 efr = serial_in(up, UART_EFR); 537 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 538 serial_out(up, UART_LCR, 0); 539 540 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 541 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 542 serial_out(up, UART_EFR, efr); 543 serial_out(up, UART_LCR, 0); 544 545 spin_unlock_irq(&port->lock); 546 547 pm_runtime_mark_last_busy(port->dev); 548 pm_runtime_put_autosuspend(port->dev); 549 } 550 551 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 552 struct omap8250_priv *priv) 553 { 554 static const struct soc_device_attribute k3_soc_devices[] = { 555 { .family = "AM65X", }, 556 { .family = "J721E", .revision = "SR1.0" }, 557 { /* sentinel */ } 558 }; 559 u32 mvr, scheme; 560 u16 revision, major, minor; 561 562 mvr = uart_read(priv, UART_OMAP_MVER); 563 564 /* Check revision register scheme */ 565 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 566 567 switch (scheme) { 568 case 0: /* Legacy Scheme: OMAP2/3 */ 569 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 570 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 571 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 572 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 573 break; 574 case 1: 575 /* New Scheme: OMAP4+ */ 576 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 577 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 578 OMAP_UART_MVR_MAJ_SHIFT; 579 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 580 break; 581 default: 582 dev_warn(up->port.dev, 583 "Unknown revision, defaulting to highest\n"); 584 /* highest possible revision */ 585 major = 0xff; 586 minor = 0xff; 587 } 588 /* normalize revision for the driver */ 589 revision = UART_BUILD_REVISION(major, minor); 590 591 switch (revision) { 592 case OMAP_UART_REV_46: 593 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 594 break; 595 case OMAP_UART_REV_52: 596 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 597 OMAP_UART_WER_HAS_TX_WAKEUP; 598 break; 599 case OMAP_UART_REV_63: 600 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 601 OMAP_UART_WER_HAS_TX_WAKEUP; 602 break; 603 default: 604 break; 605 } 606 607 /* 608 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 609 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 610 * to enable errata workaround. 611 */ 612 if (soc_device_match(k3_soc_devices)) 613 priv->habit &= ~UART_HAS_RHR_IT_DIS; 614 } 615 616 static void omap8250_uart_qos_work(struct work_struct *work) 617 { 618 struct omap8250_priv *priv; 619 620 priv = container_of(work, struct omap8250_priv, qos_work); 621 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 622 } 623 624 #ifdef CONFIG_SERIAL_8250_DMA 625 static int omap_8250_dma_handle_irq(struct uart_port *port); 626 #endif 627 628 static irqreturn_t omap8250_irq(int irq, void *dev_id) 629 { 630 struct omap8250_priv *priv = dev_id; 631 struct uart_8250_port *up = serial8250_get_port(priv->line); 632 struct uart_port *port = &up->port; 633 unsigned int iir, lsr; 634 int ret; 635 636 #ifdef CONFIG_SERIAL_8250_DMA 637 if (up->dma) { 638 ret = omap_8250_dma_handle_irq(port); 639 return IRQ_RETVAL(ret); 640 } 641 #endif 642 643 serial8250_rpm_get(up); 644 lsr = serial_port_in(port, UART_LSR); 645 iir = serial_port_in(port, UART_IIR); 646 ret = serial8250_handle_irq(port, iir); 647 648 /* 649 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 650 * FIFO has been drained, in which case a dummy read of RX FIFO 651 * is required to clear RX TIMEOUT condition. 652 */ 653 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 654 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 655 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 656 serial_port_in(port, UART_RX); 657 } 658 659 /* Stop processing interrupts on input overrun */ 660 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 661 unsigned long delay; 662 663 /* Synchronize UART_IER access against the console. */ 664 spin_lock(&port->lock); 665 up->ier = port->serial_in(port, UART_IER); 666 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 667 port->ops->stop_rx(port); 668 } else { 669 /* Keep restarting the timer until 670 * the input overrun subsides. 671 */ 672 cancel_delayed_work(&up->overrun_backoff); 673 } 674 spin_unlock(&port->lock); 675 676 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 677 schedule_delayed_work(&up->overrun_backoff, delay); 678 } 679 680 serial8250_rpm_put(up); 681 682 return IRQ_RETVAL(ret); 683 } 684 685 static int omap_8250_startup(struct uart_port *port) 686 { 687 struct uart_8250_port *up = up_to_u8250p(port); 688 struct omap8250_priv *priv = port->private_data; 689 struct uart_8250_dma *dma = &priv->omap8250_dma; 690 int ret; 691 692 if (priv->wakeirq) { 693 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 694 if (ret) 695 return ret; 696 } 697 698 pm_runtime_get_sync(port->dev); 699 700 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 701 702 serial_out(up, UART_LCR, UART_LCR_WLEN8); 703 704 up->lsr_saved_flags = 0; 705 up->msr_saved_flags = 0; 706 707 /* Disable DMA for console UART */ 708 if (dma->fn && !uart_console(port)) { 709 up->dma = &priv->omap8250_dma; 710 ret = serial8250_request_dma(up); 711 if (ret) { 712 dev_warn_ratelimited(port->dev, 713 "failed to request DMA\n"); 714 up->dma = NULL; 715 } 716 } else { 717 up->dma = NULL; 718 } 719 720 /* Synchronize UART_IER access against the console. */ 721 spin_lock_irq(&port->lock); 722 up->ier = UART_IER_RLSI | UART_IER_RDI; 723 serial_out(up, UART_IER, up->ier); 724 spin_unlock_irq(&port->lock); 725 726 #ifdef CONFIG_PM 727 up->capabilities |= UART_CAP_RPM; 728 #endif 729 730 /* Enable module level wake up */ 731 priv->wer = OMAP_UART_WER_MOD_WKUP; 732 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 733 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 734 serial_out(up, UART_OMAP_WER, priv->wer); 735 736 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 737 spin_lock_irq(&port->lock); 738 up->dma->rx_dma(up); 739 spin_unlock_irq(&port->lock); 740 } 741 742 enable_irq(up->port.irq); 743 744 pm_runtime_mark_last_busy(port->dev); 745 pm_runtime_put_autosuspend(port->dev); 746 return 0; 747 } 748 749 static void omap_8250_shutdown(struct uart_port *port) 750 { 751 struct uart_8250_port *up = up_to_u8250p(port); 752 struct omap8250_priv *priv = port->private_data; 753 754 flush_work(&priv->qos_work); 755 if (up->dma) 756 omap_8250_rx_dma_flush(up); 757 758 pm_runtime_get_sync(port->dev); 759 760 serial_out(up, UART_OMAP_WER, 0); 761 if (priv->habit & UART_HAS_EFR2) 762 serial_out(up, UART_OMAP_EFR2, 0x0); 763 764 /* Synchronize UART_IER access against the console. */ 765 spin_lock_irq(&port->lock); 766 up->ier = 0; 767 serial_out(up, UART_IER, 0); 768 spin_unlock_irq(&port->lock); 769 disable_irq_nosync(up->port.irq); 770 dev_pm_clear_wake_irq(port->dev); 771 772 serial8250_release_dma(up); 773 up->dma = NULL; 774 775 /* 776 * Disable break condition and FIFOs 777 */ 778 if (up->lcr & UART_LCR_SBC) 779 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 780 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 781 782 pm_runtime_mark_last_busy(port->dev); 783 pm_runtime_put_autosuspend(port->dev); 784 } 785 786 static void omap_8250_throttle(struct uart_port *port) 787 { 788 struct omap8250_priv *priv = port->private_data; 789 unsigned long flags; 790 791 pm_runtime_get_sync(port->dev); 792 793 spin_lock_irqsave(&port->lock, flags); 794 port->ops->stop_rx(port); 795 priv->throttled = true; 796 spin_unlock_irqrestore(&port->lock, flags); 797 798 pm_runtime_mark_last_busy(port->dev); 799 pm_runtime_put_autosuspend(port->dev); 800 } 801 802 static void omap_8250_unthrottle(struct uart_port *port) 803 { 804 struct omap8250_priv *priv = port->private_data; 805 struct uart_8250_port *up = up_to_u8250p(port); 806 unsigned long flags; 807 808 pm_runtime_get_sync(port->dev); 809 810 /* Synchronize UART_IER access against the console. */ 811 spin_lock_irqsave(&port->lock, flags); 812 priv->throttled = false; 813 if (up->dma) 814 up->dma->rx_dma(up); 815 up->ier |= UART_IER_RLSI | UART_IER_RDI; 816 port->read_status_mask |= UART_LSR_DR; 817 serial_out(up, UART_IER, up->ier); 818 spin_unlock_irqrestore(&port->lock, flags); 819 820 pm_runtime_mark_last_busy(port->dev); 821 pm_runtime_put_autosuspend(port->dev); 822 } 823 824 static int omap8250_rs485_config(struct uart_port *port, 825 struct ktermios *termios, 826 struct serial_rs485 *rs485) 827 { 828 struct omap8250_priv *priv = port->private_data; 829 struct uart_8250_port *up = up_to_u8250p(port); 830 u32 fixed_delay_rts_before_send = 0; 831 u32 fixed_delay_rts_after_send = 0; 832 unsigned int baud; 833 834 /* 835 * There is a fixed delay of 3 bit clock cycles after the TX shift 836 * register is going empty to allow time for the stop bit to transition 837 * through the transceiver before direction is changed to receive. 838 * 839 * Additionally there appears to be a 1 bit clock delay between writing 840 * to the THR register and transmission of the start bit, per page 8783 841 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 842 */ 843 if (priv->quot) { 844 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 845 baud = port->uartclk / (16 * priv->quot); 846 else 847 baud = port->uartclk / (13 * priv->quot); 848 849 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 850 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 851 } 852 853 /* 854 * Fall back to RS485 software emulation if the UART is missing 855 * hardware support, if the device tree specifies an mctrl_gpio 856 * (indicates that RTS is unavailable due to a pinmux conflict) 857 * or if the requested delays exceed the fixed hardware delays. 858 */ 859 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 860 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 861 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 862 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 863 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 864 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 865 866 port->rs485_config = serial8250_em485_config; 867 return serial8250_em485_config(port, termios, rs485); 868 } 869 870 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 871 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 872 873 if (rs485->flags & SER_RS485_ENABLED) 874 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 875 else 876 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 877 878 /* 879 * Retain same polarity semantics as RS485 software emulation, 880 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 881 */ 882 if (rs485->flags & SER_RS485_RTS_ON_SEND) 883 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 884 else 885 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 886 887 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 888 889 return 0; 890 } 891 892 #ifdef CONFIG_SERIAL_8250_DMA 893 static int omap_8250_rx_dma(struct uart_8250_port *p); 894 895 /* Must be called while priv->rx_dma_lock is held */ 896 static void __dma_rx_do_complete(struct uart_8250_port *p) 897 { 898 struct uart_8250_dma *dma = p->dma; 899 struct tty_port *tty_port = &p->port.state->port; 900 struct omap8250_priv *priv = p->port.private_data; 901 struct dma_chan *rxchan = dma->rxchan; 902 dma_cookie_t cookie; 903 struct dma_tx_state state; 904 int count; 905 int ret; 906 u32 reg; 907 908 if (!dma->rx_running) 909 goto out; 910 911 cookie = dma->rx_cookie; 912 dma->rx_running = 0; 913 914 /* Re-enable RX FIFO interrupt now that transfer is complete */ 915 if (priv->habit & UART_HAS_RHR_IT_DIS) { 916 reg = serial_in(p, UART_OMAP_IER2); 917 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 918 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 919 } 920 921 dmaengine_tx_status(rxchan, cookie, &state); 922 923 count = dma->rx_size - state.residue + state.in_flight_bytes; 924 if (count < dma->rx_size) { 925 dmaengine_terminate_async(rxchan); 926 927 /* 928 * Poll for teardown to complete which guarantees in 929 * flight data is drained. 930 */ 931 if (state.in_flight_bytes) { 932 int poll_count = 25; 933 934 while (dmaengine_tx_status(rxchan, cookie, NULL) && 935 poll_count--) 936 cpu_relax(); 937 938 if (poll_count == -1) 939 dev_err(p->port.dev, "teardown incomplete\n"); 940 } 941 } 942 if (!count) 943 goto out; 944 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 945 946 p->port.icount.rx += ret; 947 p->port.icount.buf_overrun += count - ret; 948 out: 949 950 tty_flip_buffer_push(tty_port); 951 } 952 953 static void __dma_rx_complete(void *param) 954 { 955 struct uart_8250_port *p = param; 956 struct omap8250_priv *priv = p->port.private_data; 957 struct uart_8250_dma *dma = p->dma; 958 struct dma_tx_state state; 959 unsigned long flags; 960 961 /* Synchronize UART_IER access against the console. */ 962 spin_lock_irqsave(&p->port.lock, flags); 963 964 /* 965 * If the tx status is not DMA_COMPLETE, then this is a delayed 966 * completion callback. A previous RX timeout flush would have 967 * already pushed the data, so exit. 968 */ 969 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 970 DMA_COMPLETE) { 971 spin_unlock_irqrestore(&p->port.lock, flags); 972 return; 973 } 974 __dma_rx_do_complete(p); 975 if (!priv->throttled) { 976 p->ier |= UART_IER_RLSI | UART_IER_RDI; 977 serial_out(p, UART_IER, p->ier); 978 if (!(priv->habit & UART_HAS_EFR2)) 979 omap_8250_rx_dma(p); 980 } 981 982 spin_unlock_irqrestore(&p->port.lock, flags); 983 } 984 985 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 986 { 987 struct omap8250_priv *priv = p->port.private_data; 988 struct uart_8250_dma *dma = p->dma; 989 struct dma_tx_state state; 990 unsigned long flags; 991 int ret; 992 993 spin_lock_irqsave(&priv->rx_dma_lock, flags); 994 995 if (!dma->rx_running) { 996 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 997 return; 998 } 999 1000 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 1001 if (ret == DMA_IN_PROGRESS) { 1002 ret = dmaengine_pause(dma->rxchan); 1003 if (WARN_ON_ONCE(ret)) 1004 priv->rx_dma_broken = true; 1005 } 1006 __dma_rx_do_complete(p); 1007 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1008 } 1009 1010 static int omap_8250_rx_dma(struct uart_8250_port *p) 1011 { 1012 struct omap8250_priv *priv = p->port.private_data; 1013 struct uart_8250_dma *dma = p->dma; 1014 int err = 0; 1015 struct dma_async_tx_descriptor *desc; 1016 unsigned long flags; 1017 u32 reg; 1018 1019 /* Port locked to synchronize UART_IER access against the console. */ 1020 lockdep_assert_held_once(&p->port.lock); 1021 1022 if (priv->rx_dma_broken) 1023 return -EINVAL; 1024 1025 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1026 1027 if (dma->rx_running) { 1028 enum dma_status state; 1029 1030 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1031 if (state == DMA_COMPLETE) { 1032 /* 1033 * Disable RX interrupts to allow RX DMA completion 1034 * callback to run. 1035 */ 1036 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1037 serial_out(p, UART_IER, p->ier); 1038 } 1039 goto out; 1040 } 1041 1042 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1043 dma->rx_size, DMA_DEV_TO_MEM, 1044 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1045 if (!desc) { 1046 err = -EBUSY; 1047 goto out; 1048 } 1049 1050 dma->rx_running = 1; 1051 desc->callback = __dma_rx_complete; 1052 desc->callback_param = p; 1053 1054 dma->rx_cookie = dmaengine_submit(desc); 1055 1056 /* 1057 * Disable RX FIFO interrupt while RX DMA is enabled, else 1058 * spurious interrupt may be raised when data is in the RX FIFO 1059 * but is yet to be drained by DMA. 1060 */ 1061 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1062 reg = serial_in(p, UART_OMAP_IER2); 1063 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1064 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 1065 } 1066 1067 dma_async_issue_pending(dma->rxchan); 1068 out: 1069 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1070 return err; 1071 } 1072 1073 static int omap_8250_tx_dma(struct uart_8250_port *p); 1074 1075 static void omap_8250_dma_tx_complete(void *param) 1076 { 1077 struct uart_8250_port *p = param; 1078 struct uart_8250_dma *dma = p->dma; 1079 struct circ_buf *xmit = &p->port.state->xmit; 1080 unsigned long flags; 1081 bool en_thri = false; 1082 struct omap8250_priv *priv = p->port.private_data; 1083 1084 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1085 UART_XMIT_SIZE, DMA_TO_DEVICE); 1086 1087 spin_lock_irqsave(&p->port.lock, flags); 1088 1089 dma->tx_running = 0; 1090 1091 uart_xmit_advance(&p->port, dma->tx_size); 1092 1093 if (priv->delayed_restore) { 1094 priv->delayed_restore = 0; 1095 omap8250_restore_regs(p); 1096 } 1097 1098 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1099 uart_write_wakeup(&p->port); 1100 1101 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1102 int ret; 1103 1104 ret = omap_8250_tx_dma(p); 1105 if (ret) 1106 en_thri = true; 1107 } else if (p->capabilities & UART_CAP_RPM) { 1108 en_thri = true; 1109 } 1110 1111 if (en_thri) { 1112 dma->tx_err = 1; 1113 serial8250_set_THRI(p); 1114 } 1115 1116 spin_unlock_irqrestore(&p->port.lock, flags); 1117 } 1118 1119 static int omap_8250_tx_dma(struct uart_8250_port *p) 1120 { 1121 struct uart_8250_dma *dma = p->dma; 1122 struct omap8250_priv *priv = p->port.private_data; 1123 struct circ_buf *xmit = &p->port.state->xmit; 1124 struct dma_async_tx_descriptor *desc; 1125 unsigned int skip_byte = 0; 1126 int ret; 1127 1128 if (dma->tx_running) 1129 return 0; 1130 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1131 1132 /* 1133 * Even if no data, we need to return an error for the two cases 1134 * below so serial8250_tx_chars() is invoked and properly clears 1135 * THRI and/or runtime suspend. 1136 */ 1137 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1138 ret = -EBUSY; 1139 goto err; 1140 } 1141 serial8250_clear_THRI(p); 1142 return 0; 1143 } 1144 1145 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1146 if (priv->habit & OMAP_DMA_TX_KICK) { 1147 u8 tx_lvl; 1148 1149 /* 1150 * We need to put the first byte into the FIFO in order to start 1151 * the DMA transfer. For transfers smaller than four bytes we 1152 * don't bother doing DMA at all. It seem not matter if there 1153 * are still bytes in the FIFO from the last transfer (in case 1154 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1155 * leaving the FIFO seem not to trigger the DMA transfer. It is 1156 * really the byte that we put into the FIFO. 1157 * If the FIFO is already full then we most likely got here from 1158 * omap_8250_dma_tx_complete(). And this means the DMA engine 1159 * just completed its work. We don't have to wait the complete 1160 * 86us at 115200,8n1 but around 60us (not to mention lower 1161 * baudrates). So in that case we take the interrupt and try 1162 * again with an empty FIFO. 1163 */ 1164 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1165 if (tx_lvl == p->tx_loadsz) { 1166 ret = -EBUSY; 1167 goto err; 1168 } 1169 if (dma->tx_size < 4) { 1170 ret = -EINVAL; 1171 goto err; 1172 } 1173 skip_byte = 1; 1174 } 1175 1176 desc = dmaengine_prep_slave_single(dma->txchan, 1177 dma->tx_addr + xmit->tail + skip_byte, 1178 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1179 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1180 if (!desc) { 1181 ret = -EBUSY; 1182 goto err; 1183 } 1184 1185 dma->tx_running = 1; 1186 1187 desc->callback = omap_8250_dma_tx_complete; 1188 desc->callback_param = p; 1189 1190 dma->tx_cookie = dmaengine_submit(desc); 1191 1192 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1193 UART_XMIT_SIZE, DMA_TO_DEVICE); 1194 1195 dma_async_issue_pending(dma->txchan); 1196 if (dma->tx_err) 1197 dma->tx_err = 0; 1198 1199 serial8250_clear_THRI(p); 1200 if (skip_byte) 1201 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1202 return 0; 1203 err: 1204 dma->tx_err = 1; 1205 return ret; 1206 } 1207 1208 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1209 { 1210 switch (iir & 0x3f) { 1211 case UART_IIR_RLSI: 1212 case UART_IIR_RX_TIMEOUT: 1213 case UART_IIR_RDI: 1214 omap_8250_rx_dma_flush(up); 1215 return true; 1216 } 1217 return omap_8250_rx_dma(up); 1218 } 1219 1220 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1221 { 1222 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1223 (iir & UART_IIR_RDI)) { 1224 if (handle_rx_dma(up, iir)) { 1225 status = serial8250_rx_chars(up, status); 1226 omap_8250_rx_dma(up); 1227 } 1228 } 1229 1230 return status; 1231 } 1232 1233 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1234 u16 status) 1235 { 1236 /* Port locked to synchronize UART_IER access against the console. */ 1237 lockdep_assert_held_once(&up->port.lock); 1238 1239 /* 1240 * Queue a new transfer if FIFO has data. 1241 */ 1242 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1243 (up->ier & UART_IER_RDI)) { 1244 omap_8250_rx_dma(up); 1245 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1246 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1247 /* 1248 * Disable RX timeout, read IIR to clear 1249 * current timeout condition, clear EFR2 to 1250 * periodic timeouts, re-enable interrupts. 1251 */ 1252 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1253 serial_out(up, UART_IER, up->ier); 1254 omap_8250_rx_dma_flush(up); 1255 serial_in(up, UART_IIR); 1256 serial_out(up, UART_OMAP_EFR2, 0x0); 1257 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1258 serial_out(up, UART_IER, up->ier); 1259 } 1260 } 1261 1262 /* 1263 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1264 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1265 * use the default routine in the non-DMA case and this one for with DMA. 1266 */ 1267 static int omap_8250_dma_handle_irq(struct uart_port *port) 1268 { 1269 struct uart_8250_port *up = up_to_u8250p(port); 1270 struct omap8250_priv *priv = up->port.private_data; 1271 u16 status; 1272 u8 iir; 1273 1274 serial8250_rpm_get(up); 1275 1276 iir = serial_port_in(port, UART_IIR); 1277 if (iir & UART_IIR_NO_INT) { 1278 serial8250_rpm_put(up); 1279 return IRQ_HANDLED; 1280 } 1281 1282 spin_lock(&port->lock); 1283 1284 status = serial_port_in(port, UART_LSR); 1285 1286 if (priv->habit & UART_HAS_EFR2) 1287 am654_8250_handle_rx_dma(up, iir, status); 1288 else 1289 status = omap_8250_handle_rx_dma(up, iir, status); 1290 1291 serial8250_modem_status(up); 1292 if (status & UART_LSR_THRE && up->dma->tx_err) { 1293 if (uart_tx_stopped(&up->port) || 1294 uart_circ_empty(&up->port.state->xmit)) { 1295 up->dma->tx_err = 0; 1296 serial8250_tx_chars(up); 1297 } else { 1298 /* 1299 * try again due to an earlier failer which 1300 * might have been resolved by now. 1301 */ 1302 if (omap_8250_tx_dma(up)) 1303 serial8250_tx_chars(up); 1304 } 1305 } 1306 1307 uart_unlock_and_check_sysrq(port); 1308 1309 serial8250_rpm_put(up); 1310 return 1; 1311 } 1312 1313 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1314 { 1315 return false; 1316 } 1317 1318 #else 1319 1320 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1321 { 1322 return -EINVAL; 1323 } 1324 #endif 1325 1326 static int omap8250_no_handle_irq(struct uart_port *port) 1327 { 1328 /* IRQ has not been requested but handling irq? */ 1329 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1330 return 0; 1331 } 1332 1333 static struct omap8250_dma_params am654_dma = { 1334 .rx_size = SZ_2K, 1335 .rx_trigger = 1, 1336 .tx_trigger = TX_TRIGGER, 1337 }; 1338 1339 static struct omap8250_dma_params am33xx_dma = { 1340 .rx_size = RX_TRIGGER, 1341 .rx_trigger = RX_TRIGGER, 1342 .tx_trigger = TX_TRIGGER, 1343 }; 1344 1345 static struct omap8250_platdata am654_platdata = { 1346 .dma_params = &am654_dma, 1347 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1348 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1349 }; 1350 1351 static struct omap8250_platdata am33xx_platdata = { 1352 .dma_params = &am33xx_dma, 1353 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1354 }; 1355 1356 static struct omap8250_platdata omap4_platdata = { 1357 .dma_params = &am33xx_dma, 1358 .habit = UART_ERRATA_CLOCK_DISABLE, 1359 }; 1360 1361 static const struct of_device_id omap8250_dt_ids[] = { 1362 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1363 { .compatible = "ti,omap2-uart" }, 1364 { .compatible = "ti,omap3-uart" }, 1365 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1366 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1367 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1368 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1369 {}, 1370 }; 1371 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1372 1373 static int omap8250_probe(struct platform_device *pdev) 1374 { 1375 struct device_node *np = pdev->dev.of_node; 1376 struct omap8250_priv *priv; 1377 const struct omap8250_platdata *pdata; 1378 struct uart_8250_port up; 1379 struct resource *regs; 1380 void __iomem *membase; 1381 int irq, ret; 1382 1383 irq = platform_get_irq(pdev, 0); 1384 if (irq < 0) 1385 return irq; 1386 1387 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1388 if (!regs) { 1389 dev_err(&pdev->dev, "missing registers\n"); 1390 return -EINVAL; 1391 } 1392 1393 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1394 if (!priv) 1395 return -ENOMEM; 1396 1397 membase = devm_ioremap(&pdev->dev, regs->start, 1398 resource_size(regs)); 1399 if (!membase) 1400 return -ENODEV; 1401 1402 memset(&up, 0, sizeof(up)); 1403 up.port.dev = &pdev->dev; 1404 up.port.mapbase = regs->start; 1405 up.port.membase = membase; 1406 up.port.irq = irq; 1407 /* 1408 * It claims to be 16C750 compatible however it is a little different. 1409 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1410 * have) is enabled via EFR instead of MCR. The type is set here 8250 1411 * just to get things going. UNKNOWN does not work for a few reasons and 1412 * we don't need our own type since we don't use 8250's set_termios() 1413 * or pm callback. 1414 */ 1415 up.port.type = PORT_8250; 1416 up.port.iotype = UPIO_MEM; 1417 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1418 UPF_HARD_FLOW; 1419 up.port.private_data = priv; 1420 1421 up.port.regshift = OMAP_UART_REGSHIFT; 1422 up.port.fifosize = 64; 1423 up.tx_loadsz = 64; 1424 up.capabilities = UART_CAP_FIFO; 1425 #ifdef CONFIG_PM 1426 /* 1427 * Runtime PM is mostly transparent. However to do it right we need to a 1428 * TX empty interrupt before we can put the device to auto idle. So if 1429 * PM is not enabled we don't add that flag and can spare that one extra 1430 * interrupt in the TX path. 1431 */ 1432 up.capabilities |= UART_CAP_RPM; 1433 #endif 1434 up.port.set_termios = omap_8250_set_termios; 1435 up.port.set_mctrl = omap8250_set_mctrl; 1436 up.port.pm = omap_8250_pm; 1437 up.port.startup = omap_8250_startup; 1438 up.port.shutdown = omap_8250_shutdown; 1439 up.port.throttle = omap_8250_throttle; 1440 up.port.unthrottle = omap_8250_unthrottle; 1441 up.port.rs485_config = omap8250_rs485_config; 1442 /* same rs485_supported for software emulation and native RS485 */ 1443 up.port.rs485_supported = serial8250_em485_supported; 1444 up.rs485_start_tx = serial8250_em485_start_tx; 1445 up.rs485_stop_tx = serial8250_em485_stop_tx; 1446 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1447 1448 ret = of_alias_get_id(np, "serial"); 1449 if (ret < 0) { 1450 dev_err(&pdev->dev, "failed to get alias\n"); 1451 return ret; 1452 } 1453 up.port.line = ret; 1454 1455 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1456 struct clk *clk; 1457 1458 clk = devm_clk_get(&pdev->dev, NULL); 1459 if (IS_ERR(clk)) { 1460 if (PTR_ERR(clk) == -EPROBE_DEFER) 1461 return -EPROBE_DEFER; 1462 } else { 1463 up.port.uartclk = clk_get_rate(clk); 1464 } 1465 } 1466 1467 if (of_property_read_u32(np, "overrun-throttle-ms", 1468 &up.overrun_backoff_time_ms) != 0) 1469 up.overrun_backoff_time_ms = 0; 1470 1471 pdata = of_device_get_match_data(&pdev->dev); 1472 if (pdata) 1473 priv->habit |= pdata->habit; 1474 1475 if (!up.port.uartclk) { 1476 up.port.uartclk = DEFAULT_CLK_SPEED; 1477 dev_warn(&pdev->dev, 1478 "No clock speed specified: using default: %d\n", 1479 DEFAULT_CLK_SPEED); 1480 } 1481 1482 priv->membase = membase; 1483 priv->line = -ENODEV; 1484 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1485 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1486 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1487 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1488 1489 spin_lock_init(&priv->rx_dma_lock); 1490 1491 platform_set_drvdata(pdev, priv); 1492 1493 device_init_wakeup(&pdev->dev, true); 1494 pm_runtime_enable(&pdev->dev); 1495 pm_runtime_use_autosuspend(&pdev->dev); 1496 1497 /* 1498 * Disable runtime PM until autosuspend delay unless specifically 1499 * enabled by the user via sysfs. This is the historic way to 1500 * prevent an unsafe default policy with lossy characters on wake-up. 1501 * For serdev devices this is not needed, the policy can be managed by 1502 * the serdev driver. 1503 */ 1504 if (!of_get_available_child_count(pdev->dev.of_node)) 1505 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1506 1507 pm_runtime_irq_safe(&pdev->dev); 1508 1509 pm_runtime_get_sync(&pdev->dev); 1510 1511 omap_serial_fill_features_erratas(&up, priv); 1512 up.port.handle_irq = omap8250_no_handle_irq; 1513 priv->rx_trigger = RX_TRIGGER; 1514 priv->tx_trigger = TX_TRIGGER; 1515 #ifdef CONFIG_SERIAL_8250_DMA 1516 /* 1517 * Oh DMA support. If there are no DMA properties in the DT then 1518 * we will fall back to a generic DMA channel which does not 1519 * really work here. To ensure that we do not get a generic DMA 1520 * channel assigned, we have the the_no_dma_filter_fn() here. 1521 * To avoid "failed to request DMA" messages we check for DMA 1522 * properties in DT. 1523 */ 1524 ret = of_property_count_strings(np, "dma-names"); 1525 if (ret == 2) { 1526 struct omap8250_dma_params *dma_params = NULL; 1527 struct uart_8250_dma *dma = &priv->omap8250_dma; 1528 1529 dma->fn = the_no_dma_filter_fn; 1530 dma->tx_dma = omap_8250_tx_dma; 1531 dma->rx_dma = omap_8250_rx_dma; 1532 if (pdata) 1533 dma_params = pdata->dma_params; 1534 1535 if (dma_params) { 1536 dma->rx_size = dma_params->rx_size; 1537 dma->rxconf.src_maxburst = dma_params->rx_trigger; 1538 dma->txconf.dst_maxburst = dma_params->tx_trigger; 1539 priv->rx_trigger = dma_params->rx_trigger; 1540 priv->tx_trigger = dma_params->tx_trigger; 1541 } else { 1542 dma->rx_size = RX_TRIGGER; 1543 dma->rxconf.src_maxburst = RX_TRIGGER; 1544 dma->txconf.dst_maxburst = TX_TRIGGER; 1545 } 1546 } 1547 #endif 1548 1549 irq_set_status_flags(irq, IRQ_NOAUTOEN); 1550 ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0, 1551 dev_name(&pdev->dev), priv); 1552 if (ret < 0) 1553 return ret; 1554 1555 priv->wakeirq = irq_of_parse_and_map(np, 1); 1556 1557 ret = serial8250_register_8250_port(&up); 1558 if (ret < 0) { 1559 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1560 goto err; 1561 } 1562 priv->line = ret; 1563 pm_runtime_mark_last_busy(&pdev->dev); 1564 pm_runtime_put_autosuspend(&pdev->dev); 1565 return 0; 1566 err: 1567 pm_runtime_dont_use_autosuspend(&pdev->dev); 1568 pm_runtime_put_sync(&pdev->dev); 1569 flush_work(&priv->qos_work); 1570 pm_runtime_disable(&pdev->dev); 1571 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1572 return ret; 1573 } 1574 1575 static int omap8250_remove(struct platform_device *pdev) 1576 { 1577 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1578 struct uart_8250_port *up; 1579 int err; 1580 1581 err = pm_runtime_resume_and_get(&pdev->dev); 1582 if (err) 1583 return err; 1584 1585 up = serial8250_get_port(priv->line); 1586 omap_8250_shutdown(&up->port); 1587 serial8250_unregister_port(priv->line); 1588 priv->line = -ENODEV; 1589 pm_runtime_dont_use_autosuspend(&pdev->dev); 1590 pm_runtime_put_sync(&pdev->dev); 1591 flush_work(&priv->qos_work); 1592 pm_runtime_disable(&pdev->dev); 1593 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1594 device_init_wakeup(&pdev->dev, false); 1595 return 0; 1596 } 1597 1598 static int omap8250_prepare(struct device *dev) 1599 { 1600 struct omap8250_priv *priv = dev_get_drvdata(dev); 1601 1602 if (!priv) 1603 return 0; 1604 priv->is_suspending = true; 1605 return 0; 1606 } 1607 1608 static void omap8250_complete(struct device *dev) 1609 { 1610 struct omap8250_priv *priv = dev_get_drvdata(dev); 1611 1612 if (!priv) 1613 return; 1614 priv->is_suspending = false; 1615 } 1616 1617 static int omap8250_suspend(struct device *dev) 1618 { 1619 struct omap8250_priv *priv = dev_get_drvdata(dev); 1620 struct uart_8250_port *up = serial8250_get_port(priv->line); 1621 int err; 1622 1623 serial8250_suspend_port(priv->line); 1624 1625 err = pm_runtime_resume_and_get(dev); 1626 if (err) 1627 return err; 1628 if (!device_may_wakeup(dev)) 1629 priv->wer = 0; 1630 serial_out(up, UART_OMAP_WER, priv->wer); 1631 err = pm_runtime_force_suspend(dev); 1632 flush_work(&priv->qos_work); 1633 1634 return err; 1635 } 1636 1637 static int omap8250_resume(struct device *dev) 1638 { 1639 struct omap8250_priv *priv = dev_get_drvdata(dev); 1640 int err; 1641 1642 err = pm_runtime_force_resume(dev); 1643 if (err) 1644 return err; 1645 serial8250_resume_port(priv->line); 1646 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */ 1647 pm_runtime_mark_last_busy(dev); 1648 pm_runtime_put_autosuspend(dev); 1649 1650 return 0; 1651 } 1652 1653 static int omap8250_lost_context(struct uart_8250_port *up) 1654 { 1655 u32 val; 1656 1657 val = serial_in(up, UART_OMAP_SCR); 1658 /* 1659 * If we lose context, then SCR is set to its reset value of zero. 1660 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1661 * among other bits, to never set the register back to zero again. 1662 */ 1663 if (!val) 1664 return 1; 1665 return 0; 1666 } 1667 1668 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val) 1669 { 1670 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT)); 1671 } 1672 1673 /* TODO: in future, this should happen via API in drivers/reset/ */ 1674 static int omap8250_soft_reset(struct device *dev) 1675 { 1676 struct omap8250_priv *priv = dev_get_drvdata(dev); 1677 int timeout = 100; 1678 int sysc; 1679 int syss; 1680 1681 /* 1682 * At least on omap4, unused uarts may not idle after reset without 1683 * a basic scr dma configuration even with no dma in use. The 1684 * module clkctrl status bits will be 1 instead of 3 blocking idle 1685 * for the whole clockdomain. The softreset below will clear scr, 1686 * and we restore it on resume so this is safe to do on all SoCs 1687 * needing omap8250_soft_reset() quirk. Do it in two writes as 1688 * recommended in the comment for omap8250_update_scr(). 1689 */ 1690 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1691 uart_write(priv, UART_OMAP_SCR, 1692 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1693 1694 sysc = uart_read(priv, UART_OMAP_SYSC); 1695 1696 /* softreset the UART */ 1697 sysc |= OMAP_UART_SYSC_SOFTRESET; 1698 uart_write(priv, UART_OMAP_SYSC, sysc); 1699 1700 /* By experiments, 1us enough for reset complete on AM335x */ 1701 do { 1702 udelay(1); 1703 syss = uart_read(priv, UART_OMAP_SYSS); 1704 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1705 1706 if (!timeout) { 1707 dev_err(dev, "timed out waiting for reset done\n"); 1708 return -ETIMEDOUT; 1709 } 1710 1711 return 0; 1712 } 1713 1714 static int omap8250_runtime_suspend(struct device *dev) 1715 { 1716 struct omap8250_priv *priv = dev_get_drvdata(dev); 1717 struct uart_8250_port *up = NULL; 1718 1719 if (priv->line >= 0) 1720 up = serial8250_get_port(priv->line); 1721 /* 1722 * When using 'no_console_suspend', the console UART must not be 1723 * suspended. Since driver suspend is managed by runtime suspend, 1724 * preventing runtime suspend (by returning error) will keep device 1725 * active during suspend. 1726 */ 1727 if (priv->is_suspending && !console_suspend_enabled) { 1728 if (up && uart_console(&up->port)) 1729 return -EBUSY; 1730 } 1731 1732 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1733 int ret; 1734 1735 ret = omap8250_soft_reset(dev); 1736 if (ret) 1737 return ret; 1738 1739 if (up) { 1740 /* Restore to UART mode after reset (for wakeup) */ 1741 omap8250_update_mdr1(up, priv); 1742 /* Restore wakeup enable register */ 1743 serial_out(up, UART_OMAP_WER, priv->wer); 1744 } 1745 } 1746 1747 if (up && up->dma && up->dma->rxchan) 1748 omap_8250_rx_dma_flush(up); 1749 1750 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1751 schedule_work(&priv->qos_work); 1752 1753 return 0; 1754 } 1755 1756 static int omap8250_runtime_resume(struct device *dev) 1757 { 1758 struct omap8250_priv *priv = dev_get_drvdata(dev); 1759 struct uart_8250_port *up = NULL; 1760 1761 if (priv->line >= 0) 1762 up = serial8250_get_port(priv->line); 1763 1764 if (up && omap8250_lost_context(up)) { 1765 spin_lock_irq(&up->port.lock); 1766 omap8250_restore_regs(up); 1767 spin_unlock_irq(&up->port.lock); 1768 } 1769 1770 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1771 spin_lock_irq(&up->port.lock); 1772 omap_8250_rx_dma(up); 1773 spin_unlock_irq(&up->port.lock); 1774 } 1775 1776 priv->latency = priv->calc_latency; 1777 schedule_work(&priv->qos_work); 1778 return 0; 1779 } 1780 1781 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1782 static int __init omap8250_console_fixup(void) 1783 { 1784 char *omap_str; 1785 char *options; 1786 u8 idx; 1787 1788 if (strstr(boot_command_line, "console=ttyS")) 1789 /* user set a ttyS based name for the console */ 1790 return 0; 1791 1792 omap_str = strstr(boot_command_line, "console=ttyO"); 1793 if (!omap_str) 1794 /* user did not set ttyO based console, so we don't care */ 1795 return 0; 1796 1797 omap_str += 12; 1798 if ('0' <= *omap_str && *omap_str <= '9') 1799 idx = *omap_str - '0'; 1800 else 1801 return 0; 1802 1803 omap_str++; 1804 if (omap_str[0] == ',') { 1805 omap_str++; 1806 options = omap_str; 1807 } else { 1808 options = NULL; 1809 } 1810 1811 add_preferred_console("ttyS", idx, options); 1812 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1813 idx, idx); 1814 pr_err("This ensures that you still see kernel messages. Please\n"); 1815 pr_err("update your kernel commandline.\n"); 1816 return 0; 1817 } 1818 console_initcall(omap8250_console_fixup); 1819 #endif 1820 1821 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1822 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1823 RUNTIME_PM_OPS(omap8250_runtime_suspend, 1824 omap8250_runtime_resume, NULL) 1825 .prepare = pm_sleep_ptr(omap8250_prepare), 1826 .complete = pm_sleep_ptr(omap8250_complete), 1827 }; 1828 1829 static struct platform_driver omap8250_platform_driver = { 1830 .driver = { 1831 .name = "omap8250", 1832 .pm = pm_ptr(&omap8250_dev_pm_ops), 1833 .of_match_table = omap8250_dt_ids, 1834 }, 1835 .probe = omap8250_probe, 1836 .remove = omap8250_remove, 1837 }; 1838 module_platform_driver(omap8250_platform_driver); 1839 1840 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1841 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1842 MODULE_LICENSE("GPL v2"); 1843