1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/serial_8250.h> 16 #include <linux/serial_reg.h> 17 #include <linux/tty_flip.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/delay.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/console.h> 27 #include <linux/pm_qos.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sys_soc.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 #define UART_HAS_NATIVE_RS485 BIT(7) 48 49 #define OMAP_UART_FCR_RX_TRIG 6 50 #define OMAP_UART_FCR_TX_TRIG 4 51 52 /* SCR register bitmasks */ 53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 59 60 /* MVR register bitmasks */ 61 #define OMAP_UART_MVR_SCHEME_SHIFT 30 62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 65 #define OMAP_UART_MVR_MAJ_MASK 0x700 66 #define OMAP_UART_MVR_MAJ_SHIFT 8 67 #define OMAP_UART_MVR_MIN_MASK 0x3f 68 69 /* SYSC register bitmasks */ 70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 71 72 /* SYSS register bitmasks */ 73 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 74 75 #define UART_TI752_TLR_TX 0 76 #define UART_TI752_TLR_RX 4 77 78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 79 #define TRIGGER_FCR_MASK(x) (x & 3) 80 81 /* Enable XON/XOFF flow control on output */ 82 #define OMAP_UART_SW_TX 0x08 83 /* Enable XON/XOFF flow control on input */ 84 #define OMAP_UART_SW_RX 0x02 85 86 #define OMAP_UART_WER_MOD_WKUP 0x7f 87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 88 89 #define TX_TRIGGER 1 90 #define RX_TRIGGER 48 91 92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 94 95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 96 97 #define OMAP_UART_REV_46 0x0406 98 #define OMAP_UART_REV_52 0x0502 99 #define OMAP_UART_REV_63 0x0603 100 101 /* Interrupt Enable Register 2 */ 102 #define UART_OMAP_IER2 0x1B 103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 104 105 /* Mode Definition Register 3 */ 106 #define UART_OMAP_MDR3 0x20 107 #define UART_OMAP_MDR3_DIR_POL BIT(3) 108 #define UART_OMAP_MDR3_DIR_EN BIT(4) 109 110 /* Enhanced features register 2 */ 111 #define UART_OMAP_EFR2 0x23 112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 113 114 /* RX FIFO occupancy indicator */ 115 #define UART_OMAP_RX_LVL 0x19 116 117 struct omap8250_priv { 118 int line; 119 u8 habit; 120 u8 mdr1; 121 u8 mdr3; 122 u8 efr; 123 u8 scr; 124 u8 wer; 125 u8 xon; 126 u8 xoff; 127 u8 delayed_restore; 128 u16 quot; 129 130 u8 tx_trigger; 131 u8 rx_trigger; 132 bool is_suspending; 133 int wakeirq; 134 int wakeups_enabled; 135 u32 latency; 136 u32 calc_latency; 137 struct pm_qos_request pm_qos_request; 138 struct work_struct qos_work; 139 struct uart_8250_dma omap8250_dma; 140 spinlock_t rx_dma_lock; 141 bool rx_dma_broken; 142 bool throttled; 143 }; 144 145 struct omap8250_dma_params { 146 u32 rx_size; 147 u8 rx_trigger; 148 u8 tx_trigger; 149 }; 150 151 struct omap8250_platdata { 152 struct omap8250_dma_params *dma_params; 153 u8 habit; 154 }; 155 156 #ifdef CONFIG_SERIAL_8250_DMA 157 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 158 #else 159 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 160 #endif 161 162 static u32 uart_read(struct uart_8250_port *up, u32 reg) 163 { 164 return readl(up->port.membase + (reg << up->port.regshift)); 165 } 166 167 /* 168 * Called on runtime PM resume path from omap8250_restore_regs(), and 169 * omap8250_set_mctrl(). 170 */ 171 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 172 { 173 struct uart_8250_port *up = up_to_u8250p(port); 174 struct omap8250_priv *priv = up->port.private_data; 175 u8 lcr; 176 177 serial8250_do_set_mctrl(port, mctrl); 178 179 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 180 /* 181 * Turn off autoRTS if RTS is lowered and restore autoRTS 182 * setting if RTS is raised 183 */ 184 lcr = serial_in(up, UART_LCR); 185 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 186 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 187 priv->efr |= UART_EFR_RTS; 188 else 189 priv->efr &= ~UART_EFR_RTS; 190 serial_out(up, UART_EFR, priv->efr); 191 serial_out(up, UART_LCR, lcr); 192 } 193 } 194 195 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 196 { 197 int err; 198 199 err = pm_runtime_resume_and_get(port->dev); 200 if (err) 201 return; 202 203 __omap8250_set_mctrl(port, mctrl); 204 205 pm_runtime_mark_last_busy(port->dev); 206 pm_runtime_put_autosuspend(port->dev); 207 } 208 209 /* 210 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 211 * The access to uart register after MDR1 Access 212 * causes UART to corrupt data. 213 * 214 * Need a delay = 215 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 216 * give 10 times as much 217 */ 218 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 219 struct omap8250_priv *priv) 220 { 221 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 222 udelay(2); 223 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 224 UART_FCR_CLEAR_RCVR); 225 } 226 227 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 228 struct omap8250_priv *priv) 229 { 230 unsigned int uartclk = port->uartclk; 231 unsigned int div_13, div_16; 232 unsigned int abs_d13, abs_d16; 233 234 /* 235 * Old custom speed handling. 236 */ 237 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 238 priv->quot = port->custom_divisor & UART_DIV_MAX; 239 /* 240 * I assume that nobody is using this. But hey, if somebody 241 * would like to specify the divisor _and_ the mode then the 242 * driver is ready and waiting for it. 243 */ 244 if (port->custom_divisor & (1 << 16)) 245 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 246 else 247 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 248 return; 249 } 250 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 251 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 252 253 if (!div_13) 254 div_13 = 1; 255 if (!div_16) 256 div_16 = 1; 257 258 abs_d13 = abs(baud - uartclk / 13 / div_13); 259 abs_d16 = abs(baud - uartclk / 16 / div_16); 260 261 if (abs_d13 >= abs_d16) { 262 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 263 priv->quot = div_16; 264 } else { 265 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 266 priv->quot = div_13; 267 } 268 } 269 270 static void omap8250_update_scr(struct uart_8250_port *up, 271 struct omap8250_priv *priv) 272 { 273 u8 old_scr; 274 275 old_scr = serial_in(up, UART_OMAP_SCR); 276 if (old_scr == priv->scr) 277 return; 278 279 /* 280 * The manual recommends not to enable the DMA mode selector in the SCR 281 * (instead of the FCR) register _and_ selecting the DMA mode as one 282 * register write because this may lead to malfunction. 283 */ 284 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 285 serial_out(up, UART_OMAP_SCR, 286 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 287 serial_out(up, UART_OMAP_SCR, priv->scr); 288 } 289 290 static void omap8250_update_mdr1(struct uart_8250_port *up, 291 struct omap8250_priv *priv) 292 { 293 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 294 omap_8250_mdr1_errataset(up, priv); 295 else 296 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 297 } 298 299 static void omap8250_restore_regs(struct uart_8250_port *up) 300 { 301 struct omap8250_priv *priv = up->port.private_data; 302 struct uart_8250_dma *dma = up->dma; 303 u8 mcr = serial8250_in_MCR(up); 304 305 if (dma && dma->tx_running) { 306 /* 307 * TCSANOW requests the change to occur immediately however if 308 * we have a TX-DMA operation in progress then it has been 309 * observed that it might stall and never complete. Therefore we 310 * delay DMA completes to prevent this hang from happen. 311 */ 312 priv->delayed_restore = 1; 313 return; 314 } 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 serial_out(up, UART_EFR, UART_EFR_ECB); 318 319 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 320 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR); 321 serial_out(up, UART_FCR, up->fcr); 322 323 omap8250_update_scr(up, priv); 324 325 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 326 327 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 328 OMAP_UART_TCR_HALT(52)); 329 serial_out(up, UART_TI752_TLR, 330 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 331 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 332 333 serial_out(up, UART_LCR, 0); 334 335 /* drop TCR + TLR access, we setup XON/XOFF later */ 336 serial8250_out_MCR(up, mcr); 337 338 serial_out(up, UART_IER, up->ier); 339 340 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 341 serial_dl_write(up, priv->quot); 342 343 serial_out(up, UART_EFR, priv->efr); 344 345 /* Configure flow control */ 346 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 347 serial_out(up, UART_XON1, priv->xon); 348 serial_out(up, UART_XOFF1, priv->xoff); 349 350 serial_out(up, UART_LCR, up->lcr); 351 352 omap8250_update_mdr1(up, priv); 353 354 __omap8250_set_mctrl(&up->port, up->port.mctrl); 355 356 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 357 358 if (up->port.rs485.flags & SER_RS485_ENABLED && 359 up->port.rs485_config == serial8250_em485_config) 360 serial8250_em485_stop_tx(up); 361 } 362 363 /* 364 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 365 * some differences in how we want to handle flow control. 366 */ 367 static void omap_8250_set_termios(struct uart_port *port, 368 struct ktermios *termios, 369 const struct ktermios *old) 370 { 371 struct uart_8250_port *up = up_to_u8250p(port); 372 struct omap8250_priv *priv = up->port.private_data; 373 unsigned char cval = 0; 374 unsigned int baud; 375 376 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 377 378 if (termios->c_cflag & CSTOPB) 379 cval |= UART_LCR_STOP; 380 if (termios->c_cflag & PARENB) 381 cval |= UART_LCR_PARITY; 382 if (!(termios->c_cflag & PARODD)) 383 cval |= UART_LCR_EPAR; 384 if (termios->c_cflag & CMSPAR) 385 cval |= UART_LCR_SPAR; 386 387 /* 388 * Ask the core to calculate the divisor for us. 389 */ 390 baud = uart_get_baud_rate(port, termios, old, 391 port->uartclk / 16 / UART_DIV_MAX, 392 port->uartclk / 13); 393 omap_8250_get_divisor(port, baud, priv); 394 395 /* 396 * Ok, we're now changing the port state. Do it with 397 * interrupts disabled. 398 */ 399 pm_runtime_get_sync(port->dev); 400 spin_lock_irq(&port->lock); 401 402 /* 403 * Update the per-port timeout. 404 */ 405 uart_update_timeout(port, termios->c_cflag, baud); 406 407 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 408 if (termios->c_iflag & INPCK) 409 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 410 if (termios->c_iflag & (IGNBRK | PARMRK)) 411 up->port.read_status_mask |= UART_LSR_BI; 412 413 /* 414 * Characters to ignore 415 */ 416 up->port.ignore_status_mask = 0; 417 if (termios->c_iflag & IGNPAR) 418 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 419 if (termios->c_iflag & IGNBRK) { 420 up->port.ignore_status_mask |= UART_LSR_BI; 421 /* 422 * If we're ignoring parity and break indicators, 423 * ignore overruns too (for real raw support). 424 */ 425 if (termios->c_iflag & IGNPAR) 426 up->port.ignore_status_mask |= UART_LSR_OE; 427 } 428 429 /* 430 * ignore all characters if CREAD is not set 431 */ 432 if ((termios->c_cflag & CREAD) == 0) 433 up->port.ignore_status_mask |= UART_LSR_DR; 434 435 /* 436 * Modem status interrupts 437 */ 438 up->ier &= ~UART_IER_MSI; 439 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 440 up->ier |= UART_IER_MSI; 441 442 up->lcr = cval; 443 /* Up to here it was mostly serial8250_do_set_termios() */ 444 445 /* 446 * We enable TRIG_GRANU for RX and TX and additionally we set 447 * SCR_TX_EMPTY bit. The result is the following: 448 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 449 * - less than RX_TRIGGER number of bytes will also cause an interrupt 450 * once the UART decides that there no new bytes arriving. 451 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 452 * empty - the trigger level is ignored here. 453 * 454 * Once DMA is enabled: 455 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 456 * bytes in the TX FIFO. On each assert the DMA engine will move 457 * TX_TRIGGER bytes into the FIFO. 458 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 459 * the FIFO and move RX_TRIGGER bytes. 460 * This is because threshold and trigger values are the same. 461 */ 462 up->fcr = UART_FCR_ENABLE_FIFO; 463 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 464 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 465 466 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 467 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 468 469 if (up->dma) 470 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 471 OMAP_UART_SCR_DMAMODE_CTL; 472 473 priv->xon = termios->c_cc[VSTART]; 474 priv->xoff = termios->c_cc[VSTOP]; 475 476 priv->efr = 0; 477 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 478 479 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 480 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 481 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 482 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 483 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 484 priv->efr |= UART_EFR_CTS; 485 } else if (up->port.flags & UPF_SOFT_FLOW) { 486 /* 487 * OMAP rx s/w flow control is borked; the transmitter remains 488 * stuck off even if rx flow control is subsequently disabled 489 */ 490 491 /* 492 * IXOFF Flag: 493 * Enable XON/XOFF flow control on output. 494 * Transmit XON1, XOFF1 495 */ 496 if (termios->c_iflag & IXOFF) { 497 up->port.status |= UPSTAT_AUTOXOFF; 498 priv->efr |= OMAP_UART_SW_TX; 499 } 500 } 501 omap8250_restore_regs(up); 502 503 spin_unlock_irq(&up->port.lock); 504 pm_runtime_mark_last_busy(port->dev); 505 pm_runtime_put_autosuspend(port->dev); 506 507 /* calculate wakeup latency constraint */ 508 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 509 priv->latency = priv->calc_latency; 510 511 schedule_work(&priv->qos_work); 512 513 /* Don't rewrite B0 */ 514 if (tty_termios_baud_rate(termios)) 515 tty_termios_encode_baud_rate(termios, baud, baud); 516 } 517 518 /* same as 8250 except that we may have extra flow bits set in EFR */ 519 static void omap_8250_pm(struct uart_port *port, unsigned int state, 520 unsigned int oldstate) 521 { 522 struct uart_8250_port *up = up_to_u8250p(port); 523 u8 efr; 524 525 pm_runtime_get_sync(port->dev); 526 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 527 efr = serial_in(up, UART_EFR); 528 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 529 serial_out(up, UART_LCR, 0); 530 531 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 532 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 533 serial_out(up, UART_EFR, efr); 534 serial_out(up, UART_LCR, 0); 535 536 pm_runtime_mark_last_busy(port->dev); 537 pm_runtime_put_autosuspend(port->dev); 538 } 539 540 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 541 struct omap8250_priv *priv) 542 { 543 static const struct soc_device_attribute k3_soc_devices[] = { 544 { .family = "AM65X", }, 545 { .family = "J721E", .revision = "SR1.0" }, 546 { /* sentinel */ } 547 }; 548 u32 mvr, scheme; 549 u16 revision, major, minor; 550 551 mvr = uart_read(up, UART_OMAP_MVER); 552 553 /* Check revision register scheme */ 554 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 555 556 switch (scheme) { 557 case 0: /* Legacy Scheme: OMAP2/3 */ 558 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 559 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 560 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 561 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 562 break; 563 case 1: 564 /* New Scheme: OMAP4+ */ 565 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 566 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 567 OMAP_UART_MVR_MAJ_SHIFT; 568 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 569 break; 570 default: 571 dev_warn(up->port.dev, 572 "Unknown revision, defaulting to highest\n"); 573 /* highest possible revision */ 574 major = 0xff; 575 minor = 0xff; 576 } 577 /* normalize revision for the driver */ 578 revision = UART_BUILD_REVISION(major, minor); 579 580 switch (revision) { 581 case OMAP_UART_REV_46: 582 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 583 break; 584 case OMAP_UART_REV_52: 585 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 586 OMAP_UART_WER_HAS_TX_WAKEUP; 587 break; 588 case OMAP_UART_REV_63: 589 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 590 OMAP_UART_WER_HAS_TX_WAKEUP; 591 break; 592 default: 593 break; 594 } 595 596 /* 597 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 598 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 599 * to enable errata workaround. 600 */ 601 if (soc_device_match(k3_soc_devices)) 602 priv->habit &= ~UART_HAS_RHR_IT_DIS; 603 } 604 605 static void omap8250_uart_qos_work(struct work_struct *work) 606 { 607 struct omap8250_priv *priv; 608 609 priv = container_of(work, struct omap8250_priv, qos_work); 610 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 611 } 612 613 #ifdef CONFIG_SERIAL_8250_DMA 614 static int omap_8250_dma_handle_irq(struct uart_port *port); 615 #endif 616 617 static irqreturn_t omap8250_irq(int irq, void *dev_id) 618 { 619 struct uart_port *port = dev_id; 620 struct omap8250_priv *priv = port->private_data; 621 struct uart_8250_port *up = up_to_u8250p(port); 622 unsigned int iir, lsr; 623 int ret; 624 625 #ifdef CONFIG_SERIAL_8250_DMA 626 if (up->dma) { 627 ret = omap_8250_dma_handle_irq(port); 628 return IRQ_RETVAL(ret); 629 } 630 #endif 631 632 serial8250_rpm_get(up); 633 lsr = serial_port_in(port, UART_LSR); 634 iir = serial_port_in(port, UART_IIR); 635 ret = serial8250_handle_irq(port, iir); 636 637 /* 638 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 639 * FIFO has been drained, in which case a dummy read of RX FIFO 640 * is required to clear RX TIMEOUT condition. 641 */ 642 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 643 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 644 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 645 serial_port_in(port, UART_RX); 646 } 647 648 /* Stop processing interrupts on input overrun */ 649 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 650 unsigned long delay; 651 652 up->ier = port->serial_in(port, UART_IER); 653 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 654 port->ops->stop_rx(port); 655 } else { 656 /* Keep restarting the timer until 657 * the input overrun subsides. 658 */ 659 cancel_delayed_work(&up->overrun_backoff); 660 } 661 662 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 663 schedule_delayed_work(&up->overrun_backoff, delay); 664 } 665 666 serial8250_rpm_put(up); 667 668 return IRQ_RETVAL(ret); 669 } 670 671 static int omap_8250_startup(struct uart_port *port) 672 { 673 struct uart_8250_port *up = up_to_u8250p(port); 674 struct omap8250_priv *priv = port->private_data; 675 int ret; 676 677 if (priv->wakeirq) { 678 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 679 if (ret) 680 return ret; 681 } 682 683 pm_runtime_get_sync(port->dev); 684 685 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 686 687 serial_out(up, UART_LCR, UART_LCR_WLEN8); 688 689 up->lsr_saved_flags = 0; 690 up->msr_saved_flags = 0; 691 692 /* Disable DMA for console UART */ 693 if (uart_console(port)) 694 up->dma = NULL; 695 696 if (up->dma) { 697 ret = serial8250_request_dma(up); 698 if (ret) { 699 dev_warn_ratelimited(port->dev, 700 "failed to request DMA\n"); 701 up->dma = NULL; 702 } 703 } 704 705 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 706 dev_name(port->dev), port); 707 if (ret < 0) 708 goto err; 709 710 up->ier = UART_IER_RLSI | UART_IER_RDI; 711 serial_out(up, UART_IER, up->ier); 712 713 #ifdef CONFIG_PM 714 up->capabilities |= UART_CAP_RPM; 715 #endif 716 717 /* Enable module level wake up */ 718 priv->wer = OMAP_UART_WER_MOD_WKUP; 719 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 720 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 721 serial_out(up, UART_OMAP_WER, priv->wer); 722 723 if (up->dma && !(priv->habit & UART_HAS_EFR2)) 724 up->dma->rx_dma(up); 725 726 pm_runtime_mark_last_busy(port->dev); 727 pm_runtime_put_autosuspend(port->dev); 728 return 0; 729 err: 730 pm_runtime_mark_last_busy(port->dev); 731 pm_runtime_put_autosuspend(port->dev); 732 dev_pm_clear_wake_irq(port->dev); 733 return ret; 734 } 735 736 static void omap_8250_shutdown(struct uart_port *port) 737 { 738 struct uart_8250_port *up = up_to_u8250p(port); 739 struct omap8250_priv *priv = port->private_data; 740 741 flush_work(&priv->qos_work); 742 if (up->dma) 743 omap_8250_rx_dma_flush(up); 744 745 pm_runtime_get_sync(port->dev); 746 747 serial_out(up, UART_OMAP_WER, 0); 748 if (priv->habit & UART_HAS_EFR2) 749 serial_out(up, UART_OMAP_EFR2, 0x0); 750 751 up->ier = 0; 752 serial_out(up, UART_IER, 0); 753 754 if (up->dma) 755 serial8250_release_dma(up); 756 757 /* 758 * Disable break condition and FIFOs 759 */ 760 if (up->lcr & UART_LCR_SBC) 761 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 762 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 763 764 pm_runtime_mark_last_busy(port->dev); 765 pm_runtime_put_autosuspend(port->dev); 766 free_irq(port->irq, port); 767 dev_pm_clear_wake_irq(port->dev); 768 } 769 770 static void omap_8250_throttle(struct uart_port *port) 771 { 772 struct omap8250_priv *priv = port->private_data; 773 unsigned long flags; 774 775 pm_runtime_get_sync(port->dev); 776 777 spin_lock_irqsave(&port->lock, flags); 778 port->ops->stop_rx(port); 779 priv->throttled = true; 780 spin_unlock_irqrestore(&port->lock, flags); 781 782 pm_runtime_mark_last_busy(port->dev); 783 pm_runtime_put_autosuspend(port->dev); 784 } 785 786 static void omap_8250_unthrottle(struct uart_port *port) 787 { 788 struct omap8250_priv *priv = port->private_data; 789 struct uart_8250_port *up = up_to_u8250p(port); 790 unsigned long flags; 791 792 pm_runtime_get_sync(port->dev); 793 794 spin_lock_irqsave(&port->lock, flags); 795 priv->throttled = false; 796 if (up->dma) 797 up->dma->rx_dma(up); 798 up->ier |= UART_IER_RLSI | UART_IER_RDI; 799 port->read_status_mask |= UART_LSR_DR; 800 serial_out(up, UART_IER, up->ier); 801 spin_unlock_irqrestore(&port->lock, flags); 802 803 pm_runtime_mark_last_busy(port->dev); 804 pm_runtime_put_autosuspend(port->dev); 805 } 806 807 static int omap8250_rs485_config(struct uart_port *port, 808 struct ktermios *termios, 809 struct serial_rs485 *rs485) 810 { 811 struct omap8250_priv *priv = port->private_data; 812 struct uart_8250_port *up = up_to_u8250p(port); 813 u32 fixed_delay_rts_before_send = 0; 814 u32 fixed_delay_rts_after_send = 0; 815 unsigned int baud; 816 817 /* 818 * There is a fixed delay of 3 bit clock cycles after the TX shift 819 * register is going empty to allow time for the stop bit to transition 820 * through the transceiver before direction is changed to receive. 821 * 822 * Additionally there appears to be a 1 bit clock delay between writing 823 * to the THR register and transmission of the start bit, per page 8783 824 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf 825 */ 826 if (priv->quot) { 827 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE) 828 baud = port->uartclk / (16 * priv->quot); 829 else 830 baud = port->uartclk / (13 * priv->quot); 831 832 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud; 833 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud; 834 } 835 836 /* 837 * Fall back to RS485 software emulation if the UART is missing 838 * hardware support, if the device tree specifies an mctrl_gpio 839 * (indicates that RTS is unavailable due to a pinmux conflict) 840 * or if the requested delays exceed the fixed hardware delays. 841 */ 842 if (!(priv->habit & UART_HAS_NATIVE_RS485) || 843 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) || 844 rs485->delay_rts_after_send > fixed_delay_rts_after_send || 845 rs485->delay_rts_before_send > fixed_delay_rts_before_send) { 846 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 847 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 848 849 port->rs485_config = serial8250_em485_config; 850 return serial8250_em485_config(port, termios, rs485); 851 } 852 853 rs485->delay_rts_after_send = fixed_delay_rts_after_send; 854 rs485->delay_rts_before_send = fixed_delay_rts_before_send; 855 856 if (rs485->flags & SER_RS485_ENABLED) 857 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN; 858 else 859 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN; 860 861 /* 862 * Retain same polarity semantics as RS485 software emulation, 863 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send. 864 */ 865 if (rs485->flags & SER_RS485_RTS_ON_SEND) 866 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL; 867 else 868 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL; 869 870 serial_out(up, UART_OMAP_MDR3, priv->mdr3); 871 872 return 0; 873 } 874 875 #ifdef CONFIG_SERIAL_8250_DMA 876 static int omap_8250_rx_dma(struct uart_8250_port *p); 877 878 /* Must be called while priv->rx_dma_lock is held */ 879 static void __dma_rx_do_complete(struct uart_8250_port *p) 880 { 881 struct uart_8250_dma *dma = p->dma; 882 struct tty_port *tty_port = &p->port.state->port; 883 struct omap8250_priv *priv = p->port.private_data; 884 struct dma_chan *rxchan = dma->rxchan; 885 dma_cookie_t cookie; 886 struct dma_tx_state state; 887 int count; 888 int ret; 889 u32 reg; 890 891 if (!dma->rx_running) 892 goto out; 893 894 cookie = dma->rx_cookie; 895 dma->rx_running = 0; 896 897 /* Re-enable RX FIFO interrupt now that transfer is complete */ 898 if (priv->habit & UART_HAS_RHR_IT_DIS) { 899 reg = serial_in(p, UART_OMAP_IER2); 900 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 901 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 902 } 903 904 dmaengine_tx_status(rxchan, cookie, &state); 905 906 count = dma->rx_size - state.residue + state.in_flight_bytes; 907 if (count < dma->rx_size) { 908 dmaengine_terminate_async(rxchan); 909 910 /* 911 * Poll for teardown to complete which guarantees in 912 * flight data is drained. 913 */ 914 if (state.in_flight_bytes) { 915 int poll_count = 25; 916 917 while (dmaengine_tx_status(rxchan, cookie, NULL) && 918 poll_count--) 919 cpu_relax(); 920 921 if (poll_count == -1) 922 dev_err(p->port.dev, "teardown incomplete\n"); 923 } 924 } 925 if (!count) 926 goto out; 927 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 928 929 p->port.icount.rx += ret; 930 p->port.icount.buf_overrun += count - ret; 931 out: 932 933 tty_flip_buffer_push(tty_port); 934 } 935 936 static void __dma_rx_complete(void *param) 937 { 938 struct uart_8250_port *p = param; 939 struct omap8250_priv *priv = p->port.private_data; 940 struct uart_8250_dma *dma = p->dma; 941 struct dma_tx_state state; 942 unsigned long flags; 943 944 spin_lock_irqsave(&p->port.lock, flags); 945 946 /* 947 * If the tx status is not DMA_COMPLETE, then this is a delayed 948 * completion callback. A previous RX timeout flush would have 949 * already pushed the data, so exit. 950 */ 951 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 952 DMA_COMPLETE) { 953 spin_unlock_irqrestore(&p->port.lock, flags); 954 return; 955 } 956 __dma_rx_do_complete(p); 957 if (!priv->throttled) { 958 p->ier |= UART_IER_RLSI | UART_IER_RDI; 959 serial_out(p, UART_IER, p->ier); 960 if (!(priv->habit & UART_HAS_EFR2)) 961 omap_8250_rx_dma(p); 962 } 963 964 spin_unlock_irqrestore(&p->port.lock, flags); 965 } 966 967 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 968 { 969 struct omap8250_priv *priv = p->port.private_data; 970 struct uart_8250_dma *dma = p->dma; 971 struct dma_tx_state state; 972 unsigned long flags; 973 int ret; 974 975 spin_lock_irqsave(&priv->rx_dma_lock, flags); 976 977 if (!dma->rx_running) { 978 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 979 return; 980 } 981 982 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 983 if (ret == DMA_IN_PROGRESS) { 984 ret = dmaengine_pause(dma->rxchan); 985 if (WARN_ON_ONCE(ret)) 986 priv->rx_dma_broken = true; 987 } 988 __dma_rx_do_complete(p); 989 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 990 } 991 992 static int omap_8250_rx_dma(struct uart_8250_port *p) 993 { 994 struct omap8250_priv *priv = p->port.private_data; 995 struct uart_8250_dma *dma = p->dma; 996 int err = 0; 997 struct dma_async_tx_descriptor *desc; 998 unsigned long flags; 999 u32 reg; 1000 1001 if (priv->rx_dma_broken) 1002 return -EINVAL; 1003 1004 spin_lock_irqsave(&priv->rx_dma_lock, flags); 1005 1006 if (dma->rx_running) { 1007 enum dma_status state; 1008 1009 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 1010 if (state == DMA_COMPLETE) { 1011 /* 1012 * Disable RX interrupts to allow RX DMA completion 1013 * callback to run. 1014 */ 1015 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1016 serial_out(p, UART_IER, p->ier); 1017 } 1018 goto out; 1019 } 1020 1021 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 1022 dma->rx_size, DMA_DEV_TO_MEM, 1023 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1024 if (!desc) { 1025 err = -EBUSY; 1026 goto out; 1027 } 1028 1029 dma->rx_running = 1; 1030 desc->callback = __dma_rx_complete; 1031 desc->callback_param = p; 1032 1033 dma->rx_cookie = dmaengine_submit(desc); 1034 1035 /* 1036 * Disable RX FIFO interrupt while RX DMA is enabled, else 1037 * spurious interrupt may be raised when data is in the RX FIFO 1038 * but is yet to be drained by DMA. 1039 */ 1040 if (priv->habit & UART_HAS_RHR_IT_DIS) { 1041 reg = serial_in(p, UART_OMAP_IER2); 1042 reg |= UART_OMAP_IER2_RHR_IT_DIS; 1043 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 1044 } 1045 1046 dma_async_issue_pending(dma->rxchan); 1047 out: 1048 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 1049 return err; 1050 } 1051 1052 static int omap_8250_tx_dma(struct uart_8250_port *p); 1053 1054 static void omap_8250_dma_tx_complete(void *param) 1055 { 1056 struct uart_8250_port *p = param; 1057 struct uart_8250_dma *dma = p->dma; 1058 struct circ_buf *xmit = &p->port.state->xmit; 1059 unsigned long flags; 1060 bool en_thri = false; 1061 struct omap8250_priv *priv = p->port.private_data; 1062 1063 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1064 UART_XMIT_SIZE, DMA_TO_DEVICE); 1065 1066 spin_lock_irqsave(&p->port.lock, flags); 1067 1068 dma->tx_running = 0; 1069 1070 uart_xmit_advance(&p->port, dma->tx_size); 1071 1072 if (priv->delayed_restore) { 1073 priv->delayed_restore = 0; 1074 omap8250_restore_regs(p); 1075 } 1076 1077 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1078 uart_write_wakeup(&p->port); 1079 1080 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1081 int ret; 1082 1083 ret = omap_8250_tx_dma(p); 1084 if (ret) 1085 en_thri = true; 1086 } else if (p->capabilities & UART_CAP_RPM) { 1087 en_thri = true; 1088 } 1089 1090 if (en_thri) { 1091 dma->tx_err = 1; 1092 serial8250_set_THRI(p); 1093 } 1094 1095 spin_unlock_irqrestore(&p->port.lock, flags); 1096 } 1097 1098 static int omap_8250_tx_dma(struct uart_8250_port *p) 1099 { 1100 struct uart_8250_dma *dma = p->dma; 1101 struct omap8250_priv *priv = p->port.private_data; 1102 struct circ_buf *xmit = &p->port.state->xmit; 1103 struct dma_async_tx_descriptor *desc; 1104 unsigned int skip_byte = 0; 1105 int ret; 1106 1107 if (dma->tx_running) 1108 return 0; 1109 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1110 1111 /* 1112 * Even if no data, we need to return an error for the two cases 1113 * below so serial8250_tx_chars() is invoked and properly clears 1114 * THRI and/or runtime suspend. 1115 */ 1116 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1117 ret = -EBUSY; 1118 goto err; 1119 } 1120 serial8250_clear_THRI(p); 1121 return 0; 1122 } 1123 1124 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1125 if (priv->habit & OMAP_DMA_TX_KICK) { 1126 u8 tx_lvl; 1127 1128 /* 1129 * We need to put the first byte into the FIFO in order to start 1130 * the DMA transfer. For transfers smaller than four bytes we 1131 * don't bother doing DMA at all. It seem not matter if there 1132 * are still bytes in the FIFO from the last transfer (in case 1133 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1134 * leaving the FIFO seem not to trigger the DMA transfer. It is 1135 * really the byte that we put into the FIFO. 1136 * If the FIFO is already full then we most likely got here from 1137 * omap_8250_dma_tx_complete(). And this means the DMA engine 1138 * just completed its work. We don't have to wait the complete 1139 * 86us at 115200,8n1 but around 60us (not to mention lower 1140 * baudrates). So in that case we take the interrupt and try 1141 * again with an empty FIFO. 1142 */ 1143 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1144 if (tx_lvl == p->tx_loadsz) { 1145 ret = -EBUSY; 1146 goto err; 1147 } 1148 if (dma->tx_size < 4) { 1149 ret = -EINVAL; 1150 goto err; 1151 } 1152 skip_byte = 1; 1153 } 1154 1155 desc = dmaengine_prep_slave_single(dma->txchan, 1156 dma->tx_addr + xmit->tail + skip_byte, 1157 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1158 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1159 if (!desc) { 1160 ret = -EBUSY; 1161 goto err; 1162 } 1163 1164 dma->tx_running = 1; 1165 1166 desc->callback = omap_8250_dma_tx_complete; 1167 desc->callback_param = p; 1168 1169 dma->tx_cookie = dmaengine_submit(desc); 1170 1171 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1172 UART_XMIT_SIZE, DMA_TO_DEVICE); 1173 1174 dma_async_issue_pending(dma->txchan); 1175 if (dma->tx_err) 1176 dma->tx_err = 0; 1177 1178 serial8250_clear_THRI(p); 1179 if (skip_byte) 1180 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1181 return 0; 1182 err: 1183 dma->tx_err = 1; 1184 return ret; 1185 } 1186 1187 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1188 { 1189 switch (iir & 0x3f) { 1190 case UART_IIR_RLSI: 1191 case UART_IIR_RX_TIMEOUT: 1192 case UART_IIR_RDI: 1193 omap_8250_rx_dma_flush(up); 1194 return true; 1195 } 1196 return omap_8250_rx_dma(up); 1197 } 1198 1199 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1200 { 1201 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1202 (iir & UART_IIR_RDI)) { 1203 if (handle_rx_dma(up, iir)) { 1204 status = serial8250_rx_chars(up, status); 1205 omap_8250_rx_dma(up); 1206 } 1207 } 1208 1209 return status; 1210 } 1211 1212 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1213 u16 status) 1214 { 1215 /* 1216 * Queue a new transfer if FIFO has data. 1217 */ 1218 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1219 (up->ier & UART_IER_RDI)) { 1220 omap_8250_rx_dma(up); 1221 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1222 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1223 /* 1224 * Disable RX timeout, read IIR to clear 1225 * current timeout condition, clear EFR2 to 1226 * periodic timeouts, re-enable interrupts. 1227 */ 1228 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1229 serial_out(up, UART_IER, up->ier); 1230 omap_8250_rx_dma_flush(up); 1231 serial_in(up, UART_IIR); 1232 serial_out(up, UART_OMAP_EFR2, 0x0); 1233 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1234 serial_out(up, UART_IER, up->ier); 1235 } 1236 } 1237 1238 /* 1239 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1240 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1241 * use the default routine in the non-DMA case and this one for with DMA. 1242 */ 1243 static int omap_8250_dma_handle_irq(struct uart_port *port) 1244 { 1245 struct uart_8250_port *up = up_to_u8250p(port); 1246 struct omap8250_priv *priv = up->port.private_data; 1247 u16 status; 1248 u8 iir; 1249 1250 serial8250_rpm_get(up); 1251 1252 iir = serial_port_in(port, UART_IIR); 1253 if (iir & UART_IIR_NO_INT) { 1254 serial8250_rpm_put(up); 1255 return IRQ_HANDLED; 1256 } 1257 1258 spin_lock(&port->lock); 1259 1260 status = serial_port_in(port, UART_LSR); 1261 1262 if (priv->habit & UART_HAS_EFR2) 1263 am654_8250_handle_rx_dma(up, iir, status); 1264 else 1265 status = omap_8250_handle_rx_dma(up, iir, status); 1266 1267 serial8250_modem_status(up); 1268 if (status & UART_LSR_THRE && up->dma->tx_err) { 1269 if (uart_tx_stopped(&up->port) || 1270 uart_circ_empty(&up->port.state->xmit)) { 1271 up->dma->tx_err = 0; 1272 serial8250_tx_chars(up); 1273 } else { 1274 /* 1275 * try again due to an earlier failer which 1276 * might have been resolved by now. 1277 */ 1278 if (omap_8250_tx_dma(up)) 1279 serial8250_tx_chars(up); 1280 } 1281 } 1282 1283 uart_unlock_and_check_sysrq(port); 1284 1285 serial8250_rpm_put(up); 1286 return 1; 1287 } 1288 1289 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1290 { 1291 return false; 1292 } 1293 1294 #else 1295 1296 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1297 { 1298 return -EINVAL; 1299 } 1300 #endif 1301 1302 static int omap8250_no_handle_irq(struct uart_port *port) 1303 { 1304 /* IRQ has not been requested but handling irq? */ 1305 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1306 return 0; 1307 } 1308 1309 static struct omap8250_dma_params am654_dma = { 1310 .rx_size = SZ_2K, 1311 .rx_trigger = 1, 1312 .tx_trigger = TX_TRIGGER, 1313 }; 1314 1315 static struct omap8250_dma_params am33xx_dma = { 1316 .rx_size = RX_TRIGGER, 1317 .rx_trigger = RX_TRIGGER, 1318 .tx_trigger = TX_TRIGGER, 1319 }; 1320 1321 static struct omap8250_platdata am654_platdata = { 1322 .dma_params = &am654_dma, 1323 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1324 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485, 1325 }; 1326 1327 static struct omap8250_platdata am33xx_platdata = { 1328 .dma_params = &am33xx_dma, 1329 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1330 }; 1331 1332 static struct omap8250_platdata omap4_platdata = { 1333 .dma_params = &am33xx_dma, 1334 .habit = UART_ERRATA_CLOCK_DISABLE, 1335 }; 1336 1337 static const struct of_device_id omap8250_dt_ids[] = { 1338 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1339 { .compatible = "ti,omap2-uart" }, 1340 { .compatible = "ti,omap3-uart" }, 1341 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1342 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1343 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1344 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1345 {}, 1346 }; 1347 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1348 1349 static int omap8250_probe(struct platform_device *pdev) 1350 { 1351 struct device_node *np = pdev->dev.of_node; 1352 struct omap8250_priv *priv; 1353 const struct omap8250_platdata *pdata; 1354 struct uart_8250_port up; 1355 struct resource *regs; 1356 void __iomem *membase; 1357 int irq, ret; 1358 1359 irq = platform_get_irq(pdev, 0); 1360 if (irq < 0) 1361 return irq; 1362 1363 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1364 if (!regs) { 1365 dev_err(&pdev->dev, "missing registers\n"); 1366 return -EINVAL; 1367 } 1368 1369 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1370 if (!priv) 1371 return -ENOMEM; 1372 1373 membase = devm_ioremap(&pdev->dev, regs->start, 1374 resource_size(regs)); 1375 if (!membase) 1376 return -ENODEV; 1377 1378 memset(&up, 0, sizeof(up)); 1379 up.port.dev = &pdev->dev; 1380 up.port.mapbase = regs->start; 1381 up.port.membase = membase; 1382 up.port.irq = irq; 1383 /* 1384 * It claims to be 16C750 compatible however it is a little different. 1385 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1386 * have) is enabled via EFR instead of MCR. The type is set here 8250 1387 * just to get things going. UNKNOWN does not work for a few reasons and 1388 * we don't need our own type since we don't use 8250's set_termios() 1389 * or pm callback. 1390 */ 1391 up.port.type = PORT_8250; 1392 up.port.iotype = UPIO_MEM; 1393 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1394 UPF_HARD_FLOW; 1395 up.port.private_data = priv; 1396 1397 up.port.regshift = 2; 1398 up.port.fifosize = 64; 1399 up.tx_loadsz = 64; 1400 up.capabilities = UART_CAP_FIFO; 1401 #ifdef CONFIG_PM 1402 /* 1403 * Runtime PM is mostly transparent. However to do it right we need to a 1404 * TX empty interrupt before we can put the device to auto idle. So if 1405 * PM is not enabled we don't add that flag and can spare that one extra 1406 * interrupt in the TX path. 1407 */ 1408 up.capabilities |= UART_CAP_RPM; 1409 #endif 1410 up.port.set_termios = omap_8250_set_termios; 1411 up.port.set_mctrl = omap8250_set_mctrl; 1412 up.port.pm = omap_8250_pm; 1413 up.port.startup = omap_8250_startup; 1414 up.port.shutdown = omap_8250_shutdown; 1415 up.port.throttle = omap_8250_throttle; 1416 up.port.unthrottle = omap_8250_unthrottle; 1417 up.port.rs485_config = omap8250_rs485_config; 1418 /* same rs485_supported for software emulation and native RS485 */ 1419 up.port.rs485_supported = serial8250_em485_supported; 1420 up.rs485_start_tx = serial8250_em485_start_tx; 1421 up.rs485_stop_tx = serial8250_em485_stop_tx; 1422 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1423 1424 ret = of_alias_get_id(np, "serial"); 1425 if (ret < 0) { 1426 dev_err(&pdev->dev, "failed to get alias\n"); 1427 return ret; 1428 } 1429 up.port.line = ret; 1430 1431 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1432 struct clk *clk; 1433 1434 clk = devm_clk_get(&pdev->dev, NULL); 1435 if (IS_ERR(clk)) { 1436 if (PTR_ERR(clk) == -EPROBE_DEFER) 1437 return -EPROBE_DEFER; 1438 } else { 1439 up.port.uartclk = clk_get_rate(clk); 1440 } 1441 } 1442 1443 if (of_property_read_u32(np, "overrun-throttle-ms", 1444 &up.overrun_backoff_time_ms) != 0) 1445 up.overrun_backoff_time_ms = 0; 1446 1447 priv->wakeirq = irq_of_parse_and_map(np, 1); 1448 1449 pdata = of_device_get_match_data(&pdev->dev); 1450 if (pdata) 1451 priv->habit |= pdata->habit; 1452 1453 if (!up.port.uartclk) { 1454 up.port.uartclk = DEFAULT_CLK_SPEED; 1455 dev_warn(&pdev->dev, 1456 "No clock speed specified: using default: %d\n", 1457 DEFAULT_CLK_SPEED); 1458 } 1459 1460 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1461 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1462 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1463 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1464 1465 spin_lock_init(&priv->rx_dma_lock); 1466 1467 device_init_wakeup(&pdev->dev, true); 1468 pm_runtime_enable(&pdev->dev); 1469 pm_runtime_use_autosuspend(&pdev->dev); 1470 1471 /* 1472 * Disable runtime PM until autosuspend delay unless specifically 1473 * enabled by the user via sysfs. This is the historic way to 1474 * prevent an unsafe default policy with lossy characters on wake-up. 1475 * For serdev devices this is not needed, the policy can be managed by 1476 * the serdev driver. 1477 */ 1478 if (!of_get_available_child_count(pdev->dev.of_node)) 1479 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1480 1481 pm_runtime_irq_safe(&pdev->dev); 1482 1483 pm_runtime_get_sync(&pdev->dev); 1484 1485 omap_serial_fill_features_erratas(&up, priv); 1486 up.port.handle_irq = omap8250_no_handle_irq; 1487 priv->rx_trigger = RX_TRIGGER; 1488 priv->tx_trigger = TX_TRIGGER; 1489 #ifdef CONFIG_SERIAL_8250_DMA 1490 /* 1491 * Oh DMA support. If there are no DMA properties in the DT then 1492 * we will fall back to a generic DMA channel which does not 1493 * really work here. To ensure that we do not get a generic DMA 1494 * channel assigned, we have the the_no_dma_filter_fn() here. 1495 * To avoid "failed to request DMA" messages we check for DMA 1496 * properties in DT. 1497 */ 1498 ret = of_property_count_strings(np, "dma-names"); 1499 if (ret == 2) { 1500 struct omap8250_dma_params *dma_params = NULL; 1501 1502 up.dma = &priv->omap8250_dma; 1503 up.dma->fn = the_no_dma_filter_fn; 1504 up.dma->tx_dma = omap_8250_tx_dma; 1505 up.dma->rx_dma = omap_8250_rx_dma; 1506 if (pdata) 1507 dma_params = pdata->dma_params; 1508 1509 if (dma_params) { 1510 up.dma->rx_size = dma_params->rx_size; 1511 up.dma->rxconf.src_maxburst = dma_params->rx_trigger; 1512 up.dma->txconf.dst_maxburst = dma_params->tx_trigger; 1513 priv->rx_trigger = dma_params->rx_trigger; 1514 priv->tx_trigger = dma_params->tx_trigger; 1515 } else { 1516 up.dma->rx_size = RX_TRIGGER; 1517 up.dma->rxconf.src_maxburst = RX_TRIGGER; 1518 up.dma->txconf.dst_maxburst = TX_TRIGGER; 1519 } 1520 } 1521 #endif 1522 ret = serial8250_register_8250_port(&up); 1523 if (ret < 0) { 1524 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1525 goto err; 1526 } 1527 priv->line = ret; 1528 platform_set_drvdata(pdev, priv); 1529 pm_runtime_mark_last_busy(&pdev->dev); 1530 pm_runtime_put_autosuspend(&pdev->dev); 1531 return 0; 1532 err: 1533 pm_runtime_dont_use_autosuspend(&pdev->dev); 1534 pm_runtime_put_sync(&pdev->dev); 1535 pm_runtime_disable(&pdev->dev); 1536 return ret; 1537 } 1538 1539 static int omap8250_remove(struct platform_device *pdev) 1540 { 1541 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1542 int err; 1543 1544 err = pm_runtime_resume_and_get(&pdev->dev); 1545 if (err) 1546 return err; 1547 1548 pm_runtime_dont_use_autosuspend(&pdev->dev); 1549 pm_runtime_put_sync(&pdev->dev); 1550 flush_work(&priv->qos_work); 1551 pm_runtime_disable(&pdev->dev); 1552 serial8250_unregister_port(priv->line); 1553 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1554 device_init_wakeup(&pdev->dev, false); 1555 return 0; 1556 } 1557 1558 #ifdef CONFIG_PM_SLEEP 1559 static int omap8250_prepare(struct device *dev) 1560 { 1561 struct omap8250_priv *priv = dev_get_drvdata(dev); 1562 1563 if (!priv) 1564 return 0; 1565 priv->is_suspending = true; 1566 return 0; 1567 } 1568 1569 static void omap8250_complete(struct device *dev) 1570 { 1571 struct omap8250_priv *priv = dev_get_drvdata(dev); 1572 1573 if (!priv) 1574 return; 1575 priv->is_suspending = false; 1576 } 1577 1578 static int omap8250_suspend(struct device *dev) 1579 { 1580 struct omap8250_priv *priv = dev_get_drvdata(dev); 1581 struct uart_8250_port *up = serial8250_get_port(priv->line); 1582 1583 serial8250_suspend_port(priv->line); 1584 1585 pm_runtime_get_sync(dev); 1586 if (!device_may_wakeup(dev)) 1587 priv->wer = 0; 1588 serial_out(up, UART_OMAP_WER, priv->wer); 1589 pm_runtime_mark_last_busy(dev); 1590 pm_runtime_put_autosuspend(dev); 1591 1592 flush_work(&priv->qos_work); 1593 return 0; 1594 } 1595 1596 static int omap8250_resume(struct device *dev) 1597 { 1598 struct omap8250_priv *priv = dev_get_drvdata(dev); 1599 1600 serial8250_resume_port(priv->line); 1601 return 0; 1602 } 1603 #else 1604 #define omap8250_prepare NULL 1605 #define omap8250_complete NULL 1606 #endif 1607 1608 #ifdef CONFIG_PM 1609 static int omap8250_lost_context(struct uart_8250_port *up) 1610 { 1611 u32 val; 1612 1613 val = serial_in(up, UART_OMAP_SCR); 1614 /* 1615 * If we lose context, then SCR is set to its reset value of zero. 1616 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1617 * among other bits, to never set the register back to zero again. 1618 */ 1619 if (!val) 1620 return 1; 1621 return 0; 1622 } 1623 1624 /* TODO: in future, this should happen via API in drivers/reset/ */ 1625 static int omap8250_soft_reset(struct device *dev) 1626 { 1627 struct omap8250_priv *priv = dev_get_drvdata(dev); 1628 struct uart_8250_port *up = serial8250_get_port(priv->line); 1629 int timeout = 100; 1630 int sysc; 1631 int syss; 1632 1633 /* 1634 * At least on omap4, unused uarts may not idle after reset without 1635 * a basic scr dma configuration even with no dma in use. The 1636 * module clkctrl status bits will be 1 instead of 3 blocking idle 1637 * for the whole clockdomain. The softreset below will clear scr, 1638 * and we restore it on resume so this is safe to do on all SoCs 1639 * needing omap8250_soft_reset() quirk. Do it in two writes as 1640 * recommended in the comment for omap8250_update_scr(). 1641 */ 1642 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1643 serial_out(up, UART_OMAP_SCR, 1644 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1645 1646 sysc = serial_in(up, UART_OMAP_SYSC); 1647 1648 /* softreset the UART */ 1649 sysc |= OMAP_UART_SYSC_SOFTRESET; 1650 serial_out(up, UART_OMAP_SYSC, sysc); 1651 1652 /* By experiments, 1us enough for reset complete on AM335x */ 1653 do { 1654 udelay(1); 1655 syss = serial_in(up, UART_OMAP_SYSS); 1656 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1657 1658 if (!timeout) { 1659 dev_err(dev, "timed out waiting for reset done\n"); 1660 return -ETIMEDOUT; 1661 } 1662 1663 return 0; 1664 } 1665 1666 static int omap8250_runtime_suspend(struct device *dev) 1667 { 1668 struct omap8250_priv *priv = dev_get_drvdata(dev); 1669 struct uart_8250_port *up; 1670 1671 /* In case runtime-pm tries this before we are setup */ 1672 if (!priv) 1673 return 0; 1674 1675 up = serial8250_get_port(priv->line); 1676 /* 1677 * When using 'no_console_suspend', the console UART must not be 1678 * suspended. Since driver suspend is managed by runtime suspend, 1679 * preventing runtime suspend (by returning error) will keep device 1680 * active during suspend. 1681 */ 1682 if (priv->is_suspending && !console_suspend_enabled) { 1683 if (uart_console(&up->port)) 1684 return -EBUSY; 1685 } 1686 1687 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1688 int ret; 1689 1690 ret = omap8250_soft_reset(dev); 1691 if (ret) 1692 return ret; 1693 1694 /* Restore to UART mode after reset (for wakeup) */ 1695 omap8250_update_mdr1(up, priv); 1696 /* Restore wakeup enable register */ 1697 serial_out(up, UART_OMAP_WER, priv->wer); 1698 } 1699 1700 if (up->dma && up->dma->rxchan) 1701 omap_8250_rx_dma_flush(up); 1702 1703 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1704 schedule_work(&priv->qos_work); 1705 1706 return 0; 1707 } 1708 1709 static int omap8250_runtime_resume(struct device *dev) 1710 { 1711 struct omap8250_priv *priv = dev_get_drvdata(dev); 1712 struct uart_8250_port *up; 1713 1714 /* In case runtime-pm tries this before we are setup */ 1715 if (!priv) 1716 return 0; 1717 1718 up = serial8250_get_port(priv->line); 1719 1720 if (omap8250_lost_context(up)) 1721 omap8250_restore_regs(up); 1722 1723 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) 1724 omap_8250_rx_dma(up); 1725 1726 priv->latency = priv->calc_latency; 1727 schedule_work(&priv->qos_work); 1728 return 0; 1729 } 1730 #endif 1731 1732 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1733 static int __init omap8250_console_fixup(void) 1734 { 1735 char *omap_str; 1736 char *options; 1737 u8 idx; 1738 1739 if (strstr(boot_command_line, "console=ttyS")) 1740 /* user set a ttyS based name for the console */ 1741 return 0; 1742 1743 omap_str = strstr(boot_command_line, "console=ttyO"); 1744 if (!omap_str) 1745 /* user did not set ttyO based console, so we don't care */ 1746 return 0; 1747 1748 omap_str += 12; 1749 if ('0' <= *omap_str && *omap_str <= '9') 1750 idx = *omap_str - '0'; 1751 else 1752 return 0; 1753 1754 omap_str++; 1755 if (omap_str[0] == ',') { 1756 omap_str++; 1757 options = omap_str; 1758 } else { 1759 options = NULL; 1760 } 1761 1762 add_preferred_console("ttyS", idx, options); 1763 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1764 idx, idx); 1765 pr_err("This ensures that you still see kernel messages. Please\n"); 1766 pr_err("update your kernel commandline.\n"); 1767 return 0; 1768 } 1769 console_initcall(omap8250_console_fixup); 1770 #endif 1771 1772 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1773 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1774 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1775 omap8250_runtime_resume, NULL) 1776 .prepare = omap8250_prepare, 1777 .complete = omap8250_complete, 1778 }; 1779 1780 static struct platform_driver omap8250_platform_driver = { 1781 .driver = { 1782 .name = "omap8250", 1783 .pm = &omap8250_dev_pm_ops, 1784 .of_match_table = omap8250_dt_ids, 1785 }, 1786 .probe = omap8250_probe, 1787 .remove = omap8250_remove, 1788 }; 1789 module_platform_driver(omap8250_platform_driver); 1790 1791 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1792 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1793 MODULE_LICENSE("GPL v2"); 1794