1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_reg.h> 15 #include <linux/tty_flip.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/of_gpio.h> 20 #include <linux/of_irq.h> 21 #include <linux/delay.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/console.h> 24 #include <linux/pm_qos.h> 25 #include <linux/pm_wakeirq.h> 26 #include <linux/dma-mapping.h> 27 28 #include "8250.h" 29 30 #define DEFAULT_CLK_SPEED 48000000 31 32 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 33 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 34 #define OMAP_DMA_TX_KICK (1 << 2) 35 36 #define OMAP_UART_FCR_RX_TRIG 6 37 #define OMAP_UART_FCR_TX_TRIG 4 38 39 /* SCR register bitmasks */ 40 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 41 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 42 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 43 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 44 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 45 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 46 47 /* MVR register bitmasks */ 48 #define OMAP_UART_MVR_SCHEME_SHIFT 30 49 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 50 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 51 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 52 #define OMAP_UART_MVR_MAJ_MASK 0x700 53 #define OMAP_UART_MVR_MAJ_SHIFT 8 54 #define OMAP_UART_MVR_MIN_MASK 0x3f 55 56 #define UART_TI752_TLR_TX 0 57 #define UART_TI752_TLR_RX 4 58 59 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 60 #define TRIGGER_FCR_MASK(x) (x & 3) 61 62 /* Enable XON/XOFF flow control on output */ 63 #define OMAP_UART_SW_TX 0x08 64 /* Enable XON/XOFF flow control on input */ 65 #define OMAP_UART_SW_RX 0x02 66 67 #define OMAP_UART_WER_MOD_WKUP 0x7f 68 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 69 70 #define TX_TRIGGER 1 71 #define RX_TRIGGER 48 72 73 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 74 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 75 76 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 77 78 #define OMAP_UART_REV_46 0x0406 79 #define OMAP_UART_REV_52 0x0502 80 #define OMAP_UART_REV_63 0x0603 81 82 struct omap8250_priv { 83 int line; 84 u8 habit; 85 u8 mdr1; 86 u8 efr; 87 u8 scr; 88 u8 wer; 89 u8 xon; 90 u8 xoff; 91 u8 delayed_restore; 92 u16 quot; 93 94 bool is_suspending; 95 int wakeirq; 96 int wakeups_enabled; 97 u32 latency; 98 u32 calc_latency; 99 struct pm_qos_request pm_qos_request; 100 struct work_struct qos_work; 101 struct uart_8250_dma omap8250_dma; 102 spinlock_t rx_dma_lock; 103 }; 104 105 static u32 uart_read(struct uart_8250_port *up, u32 reg) 106 { 107 return readl(up->port.membase + (reg << up->port.regshift)); 108 } 109 110 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 111 { 112 struct uart_8250_port *up = up_to_u8250p(port); 113 struct omap8250_priv *priv = up->port.private_data; 114 u8 lcr; 115 116 serial8250_do_set_mctrl(port, mctrl); 117 118 /* 119 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 120 * if RTS is raised 121 */ 122 lcr = serial_in(up, UART_LCR); 123 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 124 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 125 priv->efr |= UART_EFR_RTS; 126 else 127 priv->efr &= ~UART_EFR_RTS; 128 serial_out(up, UART_EFR, priv->efr); 129 serial_out(up, UART_LCR, lcr); 130 } 131 132 /* 133 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 134 * The access to uart register after MDR1 Access 135 * causes UART to corrupt data. 136 * 137 * Need a delay = 138 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 139 * give 10 times as much 140 */ 141 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 142 struct omap8250_priv *priv) 143 { 144 u8 timeout = 255; 145 u8 old_mdr1; 146 147 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 148 if (old_mdr1 == priv->mdr1) 149 return; 150 151 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 152 udelay(2); 153 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 154 UART_FCR_CLEAR_RCVR); 155 /* 156 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 157 * TX_FIFO_E bit is 1. 158 */ 159 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 160 (UART_LSR_THRE | UART_LSR_DR))) { 161 timeout--; 162 if (!timeout) { 163 /* Should *never* happen. we warn and carry on */ 164 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 165 serial_in(up, UART_LSR)); 166 break; 167 } 168 udelay(1); 169 } 170 } 171 172 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 173 struct omap8250_priv *priv) 174 { 175 unsigned int uartclk = port->uartclk; 176 unsigned int div_13, div_16; 177 unsigned int abs_d13, abs_d16; 178 179 /* 180 * Old custom speed handling. 181 */ 182 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 183 priv->quot = port->custom_divisor & 0xffff; 184 /* 185 * I assume that nobody is using this. But hey, if somebody 186 * would like to specify the divisor _and_ the mode then the 187 * driver is ready and waiting for it. 188 */ 189 if (port->custom_divisor & (1 << 16)) 190 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 191 else 192 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 193 return; 194 } 195 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 196 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 197 198 if (!div_13) 199 div_13 = 1; 200 if (!div_16) 201 div_16 = 1; 202 203 abs_d13 = abs(baud - uartclk / 13 / div_13); 204 abs_d16 = abs(baud - uartclk / 16 / div_16); 205 206 if (abs_d13 >= abs_d16) { 207 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 208 priv->quot = div_16; 209 } else { 210 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 211 priv->quot = div_13; 212 } 213 } 214 215 static void omap8250_update_scr(struct uart_8250_port *up, 216 struct omap8250_priv *priv) 217 { 218 u8 old_scr; 219 220 old_scr = serial_in(up, UART_OMAP_SCR); 221 if (old_scr == priv->scr) 222 return; 223 224 /* 225 * The manual recommends not to enable the DMA mode selector in the SCR 226 * (instead of the FCR) register _and_ selecting the DMA mode as one 227 * register write because this may lead to malfunction. 228 */ 229 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 230 serial_out(up, UART_OMAP_SCR, 231 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 232 serial_out(up, UART_OMAP_SCR, priv->scr); 233 } 234 235 static void omap8250_restore_regs(struct uart_8250_port *up) 236 { 237 struct omap8250_priv *priv = up->port.private_data; 238 struct uart_8250_dma *dma = up->dma; 239 240 if (dma && dma->tx_running) { 241 /* 242 * TCSANOW requests the change to occur immediately however if 243 * we have a TX-DMA operation in progress then it has been 244 * observed that it might stall and never complete. Therefore we 245 * delay DMA completes to prevent this hang from happen. 246 */ 247 priv->delayed_restore = 1; 248 return; 249 } 250 251 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 252 serial_out(up, UART_EFR, UART_EFR_ECB); 253 254 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 255 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 256 serial_out(up, UART_FCR, up->fcr); 257 258 omap8250_update_scr(up, priv); 259 260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 261 262 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 263 OMAP_UART_TCR_HALT(52)); 264 serial_out(up, UART_TI752_TLR, 265 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 266 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 267 268 serial_out(up, UART_LCR, 0); 269 270 /* drop TCR + TLR access, we setup XON/XOFF later */ 271 serial_out(up, UART_MCR, up->mcr); 272 serial_out(up, UART_IER, up->ier); 273 274 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 275 serial_dl_write(up, priv->quot); 276 277 serial_out(up, UART_EFR, priv->efr); 278 279 /* Configure flow control */ 280 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 281 serial_out(up, UART_XON1, priv->xon); 282 serial_out(up, UART_XOFF1, priv->xoff); 283 284 serial_out(up, UART_LCR, up->lcr); 285 /* need mode A for FCR */ 286 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 287 omap_8250_mdr1_errataset(up, priv); 288 else 289 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 290 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 291 } 292 293 /* 294 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 295 * some differences in how we want to handle flow control. 296 */ 297 static void omap_8250_set_termios(struct uart_port *port, 298 struct ktermios *termios, 299 struct ktermios *old) 300 { 301 struct uart_8250_port *up = 302 container_of(port, struct uart_8250_port, port); 303 struct omap8250_priv *priv = up->port.private_data; 304 unsigned char cval = 0; 305 unsigned int baud; 306 307 switch (termios->c_cflag & CSIZE) { 308 case CS5: 309 cval = UART_LCR_WLEN5; 310 break; 311 case CS6: 312 cval = UART_LCR_WLEN6; 313 break; 314 case CS7: 315 cval = UART_LCR_WLEN7; 316 break; 317 default: 318 case CS8: 319 cval = UART_LCR_WLEN8; 320 break; 321 } 322 323 if (termios->c_cflag & CSTOPB) 324 cval |= UART_LCR_STOP; 325 if (termios->c_cflag & PARENB) 326 cval |= UART_LCR_PARITY; 327 if (!(termios->c_cflag & PARODD)) 328 cval |= UART_LCR_EPAR; 329 if (termios->c_cflag & CMSPAR) 330 cval |= UART_LCR_SPAR; 331 332 /* 333 * Ask the core to calculate the divisor for us. 334 */ 335 baud = uart_get_baud_rate(port, termios, old, 336 port->uartclk / 16 / 0xffff, 337 port->uartclk / 13); 338 omap_8250_get_divisor(port, baud, priv); 339 340 /* 341 * Ok, we're now changing the port state. Do it with 342 * interrupts disabled. 343 */ 344 pm_runtime_get_sync(port->dev); 345 spin_lock_irq(&port->lock); 346 347 /* 348 * Update the per-port timeout. 349 */ 350 uart_update_timeout(port, termios->c_cflag, baud); 351 352 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 353 if (termios->c_iflag & INPCK) 354 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 355 if (termios->c_iflag & (IGNBRK | PARMRK)) 356 up->port.read_status_mask |= UART_LSR_BI; 357 358 /* 359 * Characters to ignore 360 */ 361 up->port.ignore_status_mask = 0; 362 if (termios->c_iflag & IGNPAR) 363 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 364 if (termios->c_iflag & IGNBRK) { 365 up->port.ignore_status_mask |= UART_LSR_BI; 366 /* 367 * If we're ignoring parity and break indicators, 368 * ignore overruns too (for real raw support). 369 */ 370 if (termios->c_iflag & IGNPAR) 371 up->port.ignore_status_mask |= UART_LSR_OE; 372 } 373 374 /* 375 * ignore all characters if CREAD is not set 376 */ 377 if ((termios->c_cflag & CREAD) == 0) 378 up->port.ignore_status_mask |= UART_LSR_DR; 379 380 /* 381 * Modem status interrupts 382 */ 383 up->ier &= ~UART_IER_MSI; 384 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 385 up->ier |= UART_IER_MSI; 386 387 up->lcr = cval; 388 /* Up to here it was mostly serial8250_do_set_termios() */ 389 390 /* 391 * We enable TRIG_GRANU for RX and TX and additionaly we set 392 * SCR_TX_EMPTY bit. The result is the following: 393 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 394 * - less than RX_TRIGGER number of bytes will also cause an interrupt 395 * once the UART decides that there no new bytes arriving. 396 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 397 * empty - the trigger level is ignored here. 398 * 399 * Once DMA is enabled: 400 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 401 * bytes in the TX FIFO. On each assert the DMA engine will move 402 * TX_TRIGGER bytes into the FIFO. 403 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 404 * the FIFO and move RX_TRIGGER bytes. 405 * This is because threshold and trigger values are the same. 406 */ 407 up->fcr = UART_FCR_ENABLE_FIFO; 408 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 409 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 410 411 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 412 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 413 414 if (up->dma) 415 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 416 OMAP_UART_SCR_DMAMODE_CTL; 417 418 priv->xon = termios->c_cc[VSTART]; 419 priv->xoff = termios->c_cc[VSTOP]; 420 421 priv->efr = 0; 422 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); 423 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 424 425 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 426 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 427 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 428 priv->efr |= UART_EFR_CTS; 429 } else if (up->port.flags & UPF_SOFT_FLOW) { 430 /* 431 * IXON Flag: 432 * Enable XON/XOFF flow control on input. 433 * Receiver compares XON1, XOFF1. 434 */ 435 if (termios->c_iflag & IXON) 436 priv->efr |= OMAP_UART_SW_RX; 437 438 /* 439 * IXOFF Flag: 440 * Enable XON/XOFF flow control on output. 441 * Transmit XON1, XOFF1 442 */ 443 if (termios->c_iflag & IXOFF) { 444 up->port.status |= UPSTAT_AUTOXOFF; 445 priv->efr |= OMAP_UART_SW_TX; 446 } 447 448 /* 449 * IXANY Flag: 450 * Enable any character to restart output. 451 * Operation resumes after receiving any 452 * character after recognition of the XOFF character 453 */ 454 if (termios->c_iflag & IXANY) 455 up->mcr |= UART_MCR_XONANY; 456 } 457 omap8250_restore_regs(up); 458 459 spin_unlock_irq(&up->port.lock); 460 pm_runtime_mark_last_busy(port->dev); 461 pm_runtime_put_autosuspend(port->dev); 462 463 /* calculate wakeup latency constraint */ 464 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 465 priv->latency = priv->calc_latency; 466 467 schedule_work(&priv->qos_work); 468 469 /* Don't rewrite B0 */ 470 if (tty_termios_baud_rate(termios)) 471 tty_termios_encode_baud_rate(termios, baud, baud); 472 } 473 474 /* same as 8250 except that we may have extra flow bits set in EFR */ 475 static void omap_8250_pm(struct uart_port *port, unsigned int state, 476 unsigned int oldstate) 477 { 478 struct uart_8250_port *up = up_to_u8250p(port); 479 u8 efr; 480 481 pm_runtime_get_sync(port->dev); 482 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 483 efr = serial_in(up, UART_EFR); 484 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 485 serial_out(up, UART_LCR, 0); 486 487 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 488 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 489 serial_out(up, UART_EFR, efr); 490 serial_out(up, UART_LCR, 0); 491 492 pm_runtime_mark_last_busy(port->dev); 493 pm_runtime_put_autosuspend(port->dev); 494 } 495 496 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 497 struct omap8250_priv *priv) 498 { 499 u32 mvr, scheme; 500 u16 revision, major, minor; 501 502 mvr = uart_read(up, UART_OMAP_MVER); 503 504 /* Check revision register scheme */ 505 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 506 507 switch (scheme) { 508 case 0: /* Legacy Scheme: OMAP2/3 */ 509 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 510 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 511 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 512 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 513 break; 514 case 1: 515 /* New Scheme: OMAP4+ */ 516 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 517 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 518 OMAP_UART_MVR_MAJ_SHIFT; 519 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 520 break; 521 default: 522 dev_warn(up->port.dev, 523 "Unknown revision, defaulting to highest\n"); 524 /* highest possible revision */ 525 major = 0xff; 526 minor = 0xff; 527 } 528 /* normalize revision for the driver */ 529 revision = UART_BUILD_REVISION(major, minor); 530 531 switch (revision) { 532 case OMAP_UART_REV_46: 533 priv->habit = UART_ERRATA_i202_MDR1_ACCESS; 534 break; 535 case OMAP_UART_REV_52: 536 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 537 OMAP_UART_WER_HAS_TX_WAKEUP; 538 break; 539 case OMAP_UART_REV_63: 540 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 541 OMAP_UART_WER_HAS_TX_WAKEUP; 542 break; 543 default: 544 break; 545 } 546 } 547 548 static void omap8250_uart_qos_work(struct work_struct *work) 549 { 550 struct omap8250_priv *priv; 551 552 priv = container_of(work, struct omap8250_priv, qos_work); 553 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 554 } 555 556 #ifdef CONFIG_SERIAL_8250_DMA 557 static int omap_8250_dma_handle_irq(struct uart_port *port); 558 #endif 559 560 static irqreturn_t omap8250_irq(int irq, void *dev_id) 561 { 562 struct uart_port *port = dev_id; 563 struct uart_8250_port *up = up_to_u8250p(port); 564 unsigned int iir; 565 int ret; 566 567 #ifdef CONFIG_SERIAL_8250_DMA 568 if (up->dma) { 569 ret = omap_8250_dma_handle_irq(port); 570 return IRQ_RETVAL(ret); 571 } 572 #endif 573 574 serial8250_rpm_get(up); 575 iir = serial_port_in(port, UART_IIR); 576 ret = serial8250_handle_irq(port, iir); 577 serial8250_rpm_put(up); 578 579 return IRQ_RETVAL(ret); 580 } 581 582 static int omap_8250_startup(struct uart_port *port) 583 { 584 struct uart_8250_port *up = up_to_u8250p(port); 585 struct omap8250_priv *priv = port->private_data; 586 int ret; 587 588 if (priv->wakeirq) { 589 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 590 if (ret) 591 return ret; 592 } 593 594 pm_runtime_get_sync(port->dev); 595 596 up->mcr = 0; 597 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 598 599 serial_out(up, UART_LCR, UART_LCR_WLEN8); 600 601 up->lsr_saved_flags = 0; 602 up->msr_saved_flags = 0; 603 604 if (up->dma) { 605 ret = serial8250_request_dma(up); 606 if (ret) { 607 dev_warn_ratelimited(port->dev, 608 "failed to request DMA\n"); 609 up->dma = NULL; 610 } 611 } 612 613 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 614 dev_name(port->dev), port); 615 if (ret < 0) 616 goto err; 617 618 up->ier = UART_IER_RLSI | UART_IER_RDI; 619 serial_out(up, UART_IER, up->ier); 620 621 #ifdef CONFIG_PM 622 up->capabilities |= UART_CAP_RPM; 623 #endif 624 625 /* Enable module level wake up */ 626 priv->wer = OMAP_UART_WER_MOD_WKUP; 627 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 628 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 629 serial_out(up, UART_OMAP_WER, priv->wer); 630 631 if (up->dma) 632 up->dma->rx_dma(up, 0); 633 634 pm_runtime_mark_last_busy(port->dev); 635 pm_runtime_put_autosuspend(port->dev); 636 return 0; 637 err: 638 pm_runtime_mark_last_busy(port->dev); 639 pm_runtime_put_autosuspend(port->dev); 640 dev_pm_clear_wake_irq(port->dev); 641 return ret; 642 } 643 644 static void omap_8250_shutdown(struct uart_port *port) 645 { 646 struct uart_8250_port *up = up_to_u8250p(port); 647 struct omap8250_priv *priv = port->private_data; 648 649 flush_work(&priv->qos_work); 650 if (up->dma) 651 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 652 653 pm_runtime_get_sync(port->dev); 654 655 serial_out(up, UART_OMAP_WER, 0); 656 657 up->ier = 0; 658 serial_out(up, UART_IER, 0); 659 660 if (up->dma) 661 serial8250_release_dma(up); 662 663 /* 664 * Disable break condition and FIFOs 665 */ 666 if (up->lcr & UART_LCR_SBC) 667 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 668 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 669 670 pm_runtime_mark_last_busy(port->dev); 671 pm_runtime_put_autosuspend(port->dev); 672 free_irq(port->irq, port); 673 dev_pm_clear_wake_irq(port->dev); 674 } 675 676 static void omap_8250_throttle(struct uart_port *port) 677 { 678 unsigned long flags; 679 struct uart_8250_port *up = 680 container_of(port, struct uart_8250_port, port); 681 682 pm_runtime_get_sync(port->dev); 683 684 spin_lock_irqsave(&port->lock, flags); 685 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 686 serial_out(up, UART_IER, up->ier); 687 spin_unlock_irqrestore(&port->lock, flags); 688 689 pm_runtime_mark_last_busy(port->dev); 690 pm_runtime_put_autosuspend(port->dev); 691 } 692 693 static void omap_8250_unthrottle(struct uart_port *port) 694 { 695 unsigned long flags; 696 struct uart_8250_port *up = 697 container_of(port, struct uart_8250_port, port); 698 699 pm_runtime_get_sync(port->dev); 700 701 spin_lock_irqsave(&port->lock, flags); 702 up->ier |= UART_IER_RLSI | UART_IER_RDI; 703 serial_out(up, UART_IER, up->ier); 704 spin_unlock_irqrestore(&port->lock, flags); 705 706 pm_runtime_mark_last_busy(port->dev); 707 pm_runtime_put_autosuspend(port->dev); 708 } 709 710 #ifdef CONFIG_SERIAL_8250_DMA 711 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 712 713 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 714 { 715 struct omap8250_priv *priv = p->port.private_data; 716 struct uart_8250_dma *dma = p->dma; 717 struct tty_port *tty_port = &p->port.state->port; 718 struct dma_tx_state state; 719 int count; 720 unsigned long flags; 721 722 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 723 dma->rx_size, DMA_FROM_DEVICE); 724 725 spin_lock_irqsave(&priv->rx_dma_lock, flags); 726 727 if (!dma->rx_running) 728 goto unlock; 729 730 dma->rx_running = 0; 731 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 732 dmaengine_terminate_all(dma->rxchan); 733 734 count = dma->rx_size - state.residue; 735 736 tty_insert_flip_string(tty_port, dma->rx_buf, count); 737 p->port.icount.rx += count; 738 unlock: 739 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 740 741 if (!error) 742 omap_8250_rx_dma(p, 0); 743 744 tty_flip_buffer_push(tty_port); 745 } 746 747 static void __dma_rx_complete(void *param) 748 { 749 __dma_rx_do_complete(param, false); 750 } 751 752 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 753 { 754 struct omap8250_priv *priv = p->port.private_data; 755 struct uart_8250_dma *dma = p->dma; 756 unsigned long flags; 757 758 spin_lock_irqsave(&priv->rx_dma_lock, flags); 759 760 if (!dma->rx_running) { 761 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 762 return; 763 } 764 765 dmaengine_pause(dma->rxchan); 766 767 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 768 769 __dma_rx_do_complete(p, true); 770 } 771 772 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 773 { 774 struct omap8250_priv *priv = p->port.private_data; 775 struct uart_8250_dma *dma = p->dma; 776 int err = 0; 777 struct dma_async_tx_descriptor *desc; 778 unsigned long flags; 779 780 switch (iir & 0x3f) { 781 case UART_IIR_RLSI: 782 /* 8250_core handles errors and break interrupts */ 783 omap_8250_rx_dma_flush(p); 784 return -EIO; 785 case UART_IIR_RX_TIMEOUT: 786 /* 787 * If RCVR FIFO trigger level was not reached, complete the 788 * transfer and let 8250_core copy the remaining data. 789 */ 790 omap_8250_rx_dma_flush(p); 791 return -ETIMEDOUT; 792 case UART_IIR_RDI: 793 /* 794 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 795 * a DMA transfer programmed but it didn't work. One reason is 796 * that we were too slow and there were too many bytes in the 797 * FIFO, the UART counted wrong and never kicked the DMA engine 798 * to do anything. That means once we receive RDI on OMAP then 799 * the DMA won't do anything soon so we have to cancel the DMA 800 * transfer and purge the FIFO manually. 801 */ 802 omap_8250_rx_dma_flush(p); 803 return -ETIMEDOUT; 804 805 default: 806 break; 807 } 808 809 spin_lock_irqsave(&priv->rx_dma_lock, flags); 810 811 if (dma->rx_running) 812 goto out; 813 814 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 815 dma->rx_size, DMA_DEV_TO_MEM, 816 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 817 if (!desc) { 818 err = -EBUSY; 819 goto out; 820 } 821 822 dma->rx_running = 1; 823 desc->callback = __dma_rx_complete; 824 desc->callback_param = p; 825 826 dma->rx_cookie = dmaengine_submit(desc); 827 828 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 829 dma->rx_size, DMA_FROM_DEVICE); 830 831 dma_async_issue_pending(dma->rxchan); 832 out: 833 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 834 return err; 835 } 836 837 static int omap_8250_tx_dma(struct uart_8250_port *p); 838 839 static void omap_8250_dma_tx_complete(void *param) 840 { 841 struct uart_8250_port *p = param; 842 struct uart_8250_dma *dma = p->dma; 843 struct circ_buf *xmit = &p->port.state->xmit; 844 unsigned long flags; 845 bool en_thri = false; 846 struct omap8250_priv *priv = p->port.private_data; 847 848 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 849 UART_XMIT_SIZE, DMA_TO_DEVICE); 850 851 spin_lock_irqsave(&p->port.lock, flags); 852 853 dma->tx_running = 0; 854 855 xmit->tail += dma->tx_size; 856 xmit->tail &= UART_XMIT_SIZE - 1; 857 p->port.icount.tx += dma->tx_size; 858 859 if (priv->delayed_restore) { 860 priv->delayed_restore = 0; 861 omap8250_restore_regs(p); 862 } 863 864 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 865 uart_write_wakeup(&p->port); 866 867 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 868 int ret; 869 870 ret = omap_8250_tx_dma(p); 871 if (ret) 872 en_thri = true; 873 874 } else if (p->capabilities & UART_CAP_RPM) { 875 en_thri = true; 876 } 877 878 if (en_thri) { 879 dma->tx_err = 1; 880 p->ier |= UART_IER_THRI; 881 serial_port_out(&p->port, UART_IER, p->ier); 882 } 883 884 spin_unlock_irqrestore(&p->port.lock, flags); 885 } 886 887 static int omap_8250_tx_dma(struct uart_8250_port *p) 888 { 889 struct uart_8250_dma *dma = p->dma; 890 struct omap8250_priv *priv = p->port.private_data; 891 struct circ_buf *xmit = &p->port.state->xmit; 892 struct dma_async_tx_descriptor *desc; 893 unsigned int skip_byte = 0; 894 int ret; 895 896 if (dma->tx_running) 897 return 0; 898 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 899 900 /* 901 * Even if no data, we need to return an error for the two cases 902 * below so serial8250_tx_chars() is invoked and properly clears 903 * THRI and/or runtime suspend. 904 */ 905 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 906 ret = -EBUSY; 907 goto err; 908 } 909 if (p->ier & UART_IER_THRI) { 910 p->ier &= ~UART_IER_THRI; 911 serial_out(p, UART_IER, p->ier); 912 } 913 return 0; 914 } 915 916 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 917 if (priv->habit & OMAP_DMA_TX_KICK) { 918 u8 tx_lvl; 919 920 /* 921 * We need to put the first byte into the FIFO in order to start 922 * the DMA transfer. For transfers smaller than four bytes we 923 * don't bother doing DMA at all. It seem not matter if there 924 * are still bytes in the FIFO from the last transfer (in case 925 * we got here directly from omap_8250_dma_tx_complete()). Bytes 926 * leaving the FIFO seem not to trigger the DMA transfer. It is 927 * really the byte that we put into the FIFO. 928 * If the FIFO is already full then we most likely got here from 929 * omap_8250_dma_tx_complete(). And this means the DMA engine 930 * just completed its work. We don't have to wait the complete 931 * 86us at 115200,8n1 but around 60us (not to mention lower 932 * baudrates). So in that case we take the interrupt and try 933 * again with an empty FIFO. 934 */ 935 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 936 if (tx_lvl == p->tx_loadsz) { 937 ret = -EBUSY; 938 goto err; 939 } 940 if (dma->tx_size < 4) { 941 ret = -EINVAL; 942 goto err; 943 } 944 skip_byte = 1; 945 } 946 947 desc = dmaengine_prep_slave_single(dma->txchan, 948 dma->tx_addr + xmit->tail + skip_byte, 949 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 950 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 951 if (!desc) { 952 ret = -EBUSY; 953 goto err; 954 } 955 956 dma->tx_running = 1; 957 958 desc->callback = omap_8250_dma_tx_complete; 959 desc->callback_param = p; 960 961 dma->tx_cookie = dmaengine_submit(desc); 962 963 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 964 UART_XMIT_SIZE, DMA_TO_DEVICE); 965 966 dma_async_issue_pending(dma->txchan); 967 if (dma->tx_err) 968 dma->tx_err = 0; 969 970 if (p->ier & UART_IER_THRI) { 971 p->ier &= ~UART_IER_THRI; 972 serial_out(p, UART_IER, p->ier); 973 } 974 if (skip_byte) 975 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 976 return 0; 977 err: 978 dma->tx_err = 1; 979 return ret; 980 } 981 982 /* 983 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 984 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 985 * use the default routine in the non-DMA case and this one for with DMA. 986 */ 987 static int omap_8250_dma_handle_irq(struct uart_port *port) 988 { 989 struct uart_8250_port *up = up_to_u8250p(port); 990 unsigned char status; 991 unsigned long flags; 992 u8 iir; 993 int dma_err = 0; 994 995 serial8250_rpm_get(up); 996 997 iir = serial_port_in(port, UART_IIR); 998 if (iir & UART_IIR_NO_INT) { 999 serial8250_rpm_put(up); 1000 return 0; 1001 } 1002 1003 spin_lock_irqsave(&port->lock, flags); 1004 1005 status = serial_port_in(port, UART_LSR); 1006 1007 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1008 1009 dma_err = omap_8250_rx_dma(up, iir); 1010 if (dma_err) { 1011 status = serial8250_rx_chars(up, status); 1012 omap_8250_rx_dma(up, 0); 1013 } 1014 } 1015 serial8250_modem_status(up); 1016 if (status & UART_LSR_THRE && up->dma->tx_err) { 1017 if (uart_tx_stopped(&up->port) || 1018 uart_circ_empty(&up->port.state->xmit)) { 1019 up->dma->tx_err = 0; 1020 serial8250_tx_chars(up); 1021 } else { 1022 /* 1023 * try again due to an earlier failer which 1024 * might have been resolved by now. 1025 */ 1026 dma_err = omap_8250_tx_dma(up); 1027 if (dma_err) 1028 serial8250_tx_chars(up); 1029 } 1030 } 1031 1032 spin_unlock_irqrestore(&port->lock, flags); 1033 serial8250_rpm_put(up); 1034 return 1; 1035 } 1036 1037 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1038 { 1039 return false; 1040 } 1041 1042 #else 1043 1044 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 1045 { 1046 return -EINVAL; 1047 } 1048 #endif 1049 1050 static int omap8250_no_handle_irq(struct uart_port *port) 1051 { 1052 /* IRQ has not been requested but handling irq? */ 1053 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1054 return 0; 1055 } 1056 1057 static int omap8250_probe(struct platform_device *pdev) 1058 { 1059 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1060 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1061 struct omap8250_priv *priv; 1062 struct uart_8250_port up; 1063 int ret; 1064 void __iomem *membase; 1065 1066 if (!regs || !irq) { 1067 dev_err(&pdev->dev, "missing registers or irq\n"); 1068 return -EINVAL; 1069 } 1070 1071 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1072 if (!priv) 1073 return -ENOMEM; 1074 1075 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1076 resource_size(regs)); 1077 if (!membase) 1078 return -ENODEV; 1079 1080 memset(&up, 0, sizeof(up)); 1081 up.port.dev = &pdev->dev; 1082 up.port.mapbase = regs->start; 1083 up.port.membase = membase; 1084 up.port.irq = irq->start; 1085 /* 1086 * It claims to be 16C750 compatible however it is a little different. 1087 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1088 * have) is enabled via EFR instead of MCR. The type is set here 8250 1089 * just to get things going. UNKNOWN does not work for a few reasons and 1090 * we don't need our own type since we don't use 8250's set_termios() 1091 * or pm callback. 1092 */ 1093 up.port.type = PORT_8250; 1094 up.port.iotype = UPIO_MEM; 1095 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1096 UPF_HARD_FLOW; 1097 up.port.private_data = priv; 1098 1099 up.port.regshift = 2; 1100 up.port.fifosize = 64; 1101 up.tx_loadsz = 64; 1102 up.capabilities = UART_CAP_FIFO; 1103 #ifdef CONFIG_PM 1104 /* 1105 * Runtime PM is mostly transparent. However to do it right we need to a 1106 * TX empty interrupt before we can put the device to auto idle. So if 1107 * PM is not enabled we don't add that flag and can spare that one extra 1108 * interrupt in the TX path. 1109 */ 1110 up.capabilities |= UART_CAP_RPM; 1111 #endif 1112 up.port.set_termios = omap_8250_set_termios; 1113 up.port.set_mctrl = omap8250_set_mctrl; 1114 up.port.pm = omap_8250_pm; 1115 up.port.startup = omap_8250_startup; 1116 up.port.shutdown = omap_8250_shutdown; 1117 up.port.throttle = omap_8250_throttle; 1118 up.port.unthrottle = omap_8250_unthrottle; 1119 1120 if (pdev->dev.of_node) { 1121 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1122 1123 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1124 &up.port.uartclk); 1125 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1126 } else { 1127 ret = pdev->id; 1128 } 1129 if (ret < 0) { 1130 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1131 return ret; 1132 } 1133 up.port.line = ret; 1134 1135 if (!up.port.uartclk) { 1136 up.port.uartclk = DEFAULT_CLK_SPEED; 1137 dev_warn(&pdev->dev, 1138 "No clock speed specified: using default: %d\n", 1139 DEFAULT_CLK_SPEED); 1140 } 1141 1142 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1143 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1144 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1145 priv->latency); 1146 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1147 1148 spin_lock_init(&priv->rx_dma_lock); 1149 1150 device_init_wakeup(&pdev->dev, true); 1151 pm_runtime_use_autosuspend(&pdev->dev); 1152 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1153 1154 pm_runtime_irq_safe(&pdev->dev); 1155 pm_runtime_enable(&pdev->dev); 1156 1157 pm_runtime_get_sync(&pdev->dev); 1158 1159 omap_serial_fill_features_erratas(&up, priv); 1160 up.port.handle_irq = omap8250_no_handle_irq; 1161 #ifdef CONFIG_SERIAL_8250_DMA 1162 if (pdev->dev.of_node) { 1163 /* 1164 * Oh DMA support. If there are no DMA properties in the DT then 1165 * we will fall back to a generic DMA channel which does not 1166 * really work here. To ensure that we do not get a generic DMA 1167 * channel assigned, we have the the_no_dma_filter_fn() here. 1168 * To avoid "failed to request DMA" messages we check for DMA 1169 * properties in DT. 1170 */ 1171 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1172 if (ret == 2) { 1173 up.dma = &priv->omap8250_dma; 1174 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1175 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1176 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1177 priv->omap8250_dma.rx_size = RX_TRIGGER; 1178 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1179 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1180 1181 if (of_machine_is_compatible("ti,am33xx")) 1182 priv->habit |= OMAP_DMA_TX_KICK; 1183 } 1184 } 1185 #endif 1186 ret = serial8250_register_8250_port(&up); 1187 if (ret < 0) { 1188 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1189 goto err; 1190 } 1191 priv->line = ret; 1192 platform_set_drvdata(pdev, priv); 1193 pm_runtime_mark_last_busy(&pdev->dev); 1194 pm_runtime_put_autosuspend(&pdev->dev); 1195 return 0; 1196 err: 1197 pm_runtime_put(&pdev->dev); 1198 pm_runtime_disable(&pdev->dev); 1199 return ret; 1200 } 1201 1202 static int omap8250_remove(struct platform_device *pdev) 1203 { 1204 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1205 1206 pm_runtime_put_sync(&pdev->dev); 1207 pm_runtime_disable(&pdev->dev); 1208 serial8250_unregister_port(priv->line); 1209 pm_qos_remove_request(&priv->pm_qos_request); 1210 device_init_wakeup(&pdev->dev, false); 1211 return 0; 1212 } 1213 1214 #ifdef CONFIG_PM_SLEEP 1215 static int omap8250_prepare(struct device *dev) 1216 { 1217 struct omap8250_priv *priv = dev_get_drvdata(dev); 1218 1219 if (!priv) 1220 return 0; 1221 priv->is_suspending = true; 1222 return 0; 1223 } 1224 1225 static void omap8250_complete(struct device *dev) 1226 { 1227 struct omap8250_priv *priv = dev_get_drvdata(dev); 1228 1229 if (!priv) 1230 return; 1231 priv->is_suspending = false; 1232 } 1233 1234 static int omap8250_suspend(struct device *dev) 1235 { 1236 struct omap8250_priv *priv = dev_get_drvdata(dev); 1237 1238 serial8250_suspend_port(priv->line); 1239 flush_work(&priv->qos_work); 1240 return 0; 1241 } 1242 1243 static int omap8250_resume(struct device *dev) 1244 { 1245 struct omap8250_priv *priv = dev_get_drvdata(dev); 1246 1247 serial8250_resume_port(priv->line); 1248 return 0; 1249 } 1250 #else 1251 #define omap8250_prepare NULL 1252 #define omap8250_complete NULL 1253 #endif 1254 1255 #ifdef CONFIG_PM 1256 static int omap8250_lost_context(struct uart_8250_port *up) 1257 { 1258 u32 val; 1259 1260 val = serial_in(up, UART_OMAP_MDR1); 1261 /* 1262 * If we lose context, then MDR1 is set to its reset value which is 1263 * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x 1264 * or 16x but never to disable again. 1265 */ 1266 if (val == UART_OMAP_MDR1_DISABLE) 1267 return 1; 1268 return 0; 1269 } 1270 1271 static int omap8250_runtime_suspend(struct device *dev) 1272 { 1273 struct omap8250_priv *priv = dev_get_drvdata(dev); 1274 struct uart_8250_port *up; 1275 1276 up = serial8250_get_port(priv->line); 1277 /* 1278 * When using 'no_console_suspend', the console UART must not be 1279 * suspended. Since driver suspend is managed by runtime suspend, 1280 * preventing runtime suspend (by returning error) will keep device 1281 * active during suspend. 1282 */ 1283 if (priv->is_suspending && !console_suspend_enabled) { 1284 if (uart_console(&up->port)) 1285 return -EBUSY; 1286 } 1287 1288 if (up->dma) 1289 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1290 1291 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1292 schedule_work(&priv->qos_work); 1293 1294 return 0; 1295 } 1296 1297 static int omap8250_runtime_resume(struct device *dev) 1298 { 1299 struct omap8250_priv *priv = dev_get_drvdata(dev); 1300 struct uart_8250_port *up; 1301 int loss_cntx; 1302 1303 /* In case runtime-pm tries this before we are setup */ 1304 if (!priv) 1305 return 0; 1306 1307 up = serial8250_get_port(priv->line); 1308 loss_cntx = omap8250_lost_context(up); 1309 1310 if (loss_cntx) 1311 omap8250_restore_regs(up); 1312 1313 if (up->dma) 1314 omap_8250_rx_dma(up, 0); 1315 1316 priv->latency = priv->calc_latency; 1317 schedule_work(&priv->qos_work); 1318 return 0; 1319 } 1320 #endif 1321 1322 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1323 static int __init omap8250_console_fixup(void) 1324 { 1325 char *omap_str; 1326 char *options; 1327 u8 idx; 1328 1329 if (strstr(boot_command_line, "console=ttyS")) 1330 /* user set a ttyS based name for the console */ 1331 return 0; 1332 1333 omap_str = strstr(boot_command_line, "console=ttyO"); 1334 if (!omap_str) 1335 /* user did not set ttyO based console, so we don't care */ 1336 return 0; 1337 1338 omap_str += 12; 1339 if ('0' <= *omap_str && *omap_str <= '9') 1340 idx = *omap_str - '0'; 1341 else 1342 return 0; 1343 1344 omap_str++; 1345 if (omap_str[0] == ',') { 1346 omap_str++; 1347 options = omap_str; 1348 } else { 1349 options = NULL; 1350 } 1351 1352 add_preferred_console("ttyS", idx, options); 1353 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1354 idx, idx); 1355 pr_err("This ensures that you still see kernel messages. Please\n"); 1356 pr_err("update your kernel commandline.\n"); 1357 return 0; 1358 } 1359 console_initcall(omap8250_console_fixup); 1360 #endif 1361 1362 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1363 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1364 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1365 omap8250_runtime_resume, NULL) 1366 .prepare = omap8250_prepare, 1367 .complete = omap8250_complete, 1368 }; 1369 1370 static const struct of_device_id omap8250_dt_ids[] = { 1371 { .compatible = "ti,omap2-uart" }, 1372 { .compatible = "ti,omap3-uart" }, 1373 { .compatible = "ti,omap4-uart" }, 1374 {}, 1375 }; 1376 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1377 1378 static struct platform_driver omap8250_platform_driver = { 1379 .driver = { 1380 .name = "omap8250", 1381 .pm = &omap8250_dev_pm_ops, 1382 .of_match_table = omap8250_dt_ids, 1383 }, 1384 .probe = omap8250_probe, 1385 .remove = omap8250_remove, 1386 }; 1387 module_platform_driver(omap8250_platform_driver); 1388 1389 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1390 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1391 MODULE_LICENSE("GPL v2"); 1392