1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 12 #define SUPPORT_SYSRQ 13 #endif 14 15 #include <linux/device.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/serial_8250.h> 19 #include <linux/serial_reg.h> 20 #include <linux/tty_flip.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_irq.h> 27 #include <linux/delay.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/console.h> 30 #include <linux/pm_qos.h> 31 #include <linux/pm_wakeirq.h> 32 #include <linux/dma-mapping.h> 33 34 #include "8250.h" 35 36 #define DEFAULT_CLK_SPEED 48000000 37 38 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 39 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 40 #define OMAP_DMA_TX_KICK (1 << 2) 41 /* 42 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 43 * The same errata is applicable to AM335x and DRA7x processors too. 44 */ 45 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 46 47 #define OMAP_UART_FCR_RX_TRIG 6 48 #define OMAP_UART_FCR_TX_TRIG 4 49 50 /* SCR register bitmasks */ 51 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 52 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 53 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 54 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 55 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 56 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 57 58 /* MVR register bitmasks */ 59 #define OMAP_UART_MVR_SCHEME_SHIFT 30 60 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 61 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 62 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 63 #define OMAP_UART_MVR_MAJ_MASK 0x700 64 #define OMAP_UART_MVR_MAJ_SHIFT 8 65 #define OMAP_UART_MVR_MIN_MASK 0x3f 66 67 /* SYSC register bitmasks */ 68 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 69 70 /* SYSS register bitmasks */ 71 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 72 73 #define UART_TI752_TLR_TX 0 74 #define UART_TI752_TLR_RX 4 75 76 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 77 #define TRIGGER_FCR_MASK(x) (x & 3) 78 79 /* Enable XON/XOFF flow control on output */ 80 #define OMAP_UART_SW_TX 0x08 81 /* Enable XON/XOFF flow control on input */ 82 #define OMAP_UART_SW_RX 0x02 83 84 #define OMAP_UART_WER_MOD_WKUP 0x7f 85 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 86 87 #define TX_TRIGGER 1 88 #define RX_TRIGGER 48 89 90 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 91 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 92 93 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 94 95 #define OMAP_UART_REV_46 0x0406 96 #define OMAP_UART_REV_52 0x0502 97 #define OMAP_UART_REV_63 0x0603 98 99 struct omap8250_priv { 100 int line; 101 u8 habit; 102 u8 mdr1; 103 u8 efr; 104 u8 scr; 105 u8 wer; 106 u8 xon; 107 u8 xoff; 108 u8 delayed_restore; 109 u16 quot; 110 111 bool is_suspending; 112 int wakeirq; 113 int wakeups_enabled; 114 u32 latency; 115 u32 calc_latency; 116 struct pm_qos_request pm_qos_request; 117 struct work_struct qos_work; 118 struct uart_8250_dma omap8250_dma; 119 spinlock_t rx_dma_lock; 120 bool rx_dma_broken; 121 bool throttled; 122 }; 123 124 #ifdef CONFIG_SERIAL_8250_DMA 125 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 126 #else 127 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 128 #endif 129 130 static u32 uart_read(struct uart_8250_port *up, u32 reg) 131 { 132 return readl(up->port.membase + (reg << up->port.regshift)); 133 } 134 135 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 136 { 137 struct uart_8250_port *up = up_to_u8250p(port); 138 struct omap8250_priv *priv = up->port.private_data; 139 u8 lcr; 140 141 serial8250_do_set_mctrl(port, mctrl); 142 143 /* 144 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 145 * if RTS is raised 146 */ 147 lcr = serial_in(up, UART_LCR); 148 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 149 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 150 priv->efr |= UART_EFR_RTS; 151 else 152 priv->efr &= ~UART_EFR_RTS; 153 serial_out(up, UART_EFR, priv->efr); 154 serial_out(up, UART_LCR, lcr); 155 } 156 157 /* 158 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 159 * The access to uart register after MDR1 Access 160 * causes UART to corrupt data. 161 * 162 * Need a delay = 163 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 164 * give 10 times as much 165 */ 166 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 167 struct omap8250_priv *priv) 168 { 169 u8 timeout = 255; 170 u8 old_mdr1; 171 172 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 173 if (old_mdr1 == priv->mdr1) 174 return; 175 176 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 177 udelay(2); 178 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 179 UART_FCR_CLEAR_RCVR); 180 /* 181 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 182 * TX_FIFO_E bit is 1. 183 */ 184 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 185 (UART_LSR_THRE | UART_LSR_DR))) { 186 timeout--; 187 if (!timeout) { 188 /* Should *never* happen. we warn and carry on */ 189 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 190 serial_in(up, UART_LSR)); 191 break; 192 } 193 udelay(1); 194 } 195 } 196 197 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 198 struct omap8250_priv *priv) 199 { 200 unsigned int uartclk = port->uartclk; 201 unsigned int div_13, div_16; 202 unsigned int abs_d13, abs_d16; 203 204 /* 205 * Old custom speed handling. 206 */ 207 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 208 priv->quot = port->custom_divisor & UART_DIV_MAX; 209 /* 210 * I assume that nobody is using this. But hey, if somebody 211 * would like to specify the divisor _and_ the mode then the 212 * driver is ready and waiting for it. 213 */ 214 if (port->custom_divisor & (1 << 16)) 215 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 216 else 217 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 218 return; 219 } 220 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 221 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 222 223 if (!div_13) 224 div_13 = 1; 225 if (!div_16) 226 div_16 = 1; 227 228 abs_d13 = abs(baud - uartclk / 13 / div_13); 229 abs_d16 = abs(baud - uartclk / 16 / div_16); 230 231 if (abs_d13 >= abs_d16) { 232 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 233 priv->quot = div_16; 234 } else { 235 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 236 priv->quot = div_13; 237 } 238 } 239 240 static void omap8250_update_scr(struct uart_8250_port *up, 241 struct omap8250_priv *priv) 242 { 243 u8 old_scr; 244 245 old_scr = serial_in(up, UART_OMAP_SCR); 246 if (old_scr == priv->scr) 247 return; 248 249 /* 250 * The manual recommends not to enable the DMA mode selector in the SCR 251 * (instead of the FCR) register _and_ selecting the DMA mode as one 252 * register write because this may lead to malfunction. 253 */ 254 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 255 serial_out(up, UART_OMAP_SCR, 256 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 257 serial_out(up, UART_OMAP_SCR, priv->scr); 258 } 259 260 static void omap8250_update_mdr1(struct uart_8250_port *up, 261 struct omap8250_priv *priv) 262 { 263 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 264 omap_8250_mdr1_errataset(up, priv); 265 else 266 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 267 } 268 269 static void omap8250_restore_regs(struct uart_8250_port *up) 270 { 271 struct omap8250_priv *priv = up->port.private_data; 272 struct uart_8250_dma *dma = up->dma; 273 274 if (dma && dma->tx_running) { 275 /* 276 * TCSANOW requests the change to occur immediately however if 277 * we have a TX-DMA operation in progress then it has been 278 * observed that it might stall and never complete. Therefore we 279 * delay DMA completes to prevent this hang from happen. 280 */ 281 priv->delayed_restore = 1; 282 return; 283 } 284 285 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 286 serial_out(up, UART_EFR, UART_EFR_ECB); 287 288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 289 serial8250_out_MCR(up, UART_MCR_TCRTLR); 290 serial_out(up, UART_FCR, up->fcr); 291 292 omap8250_update_scr(up, priv); 293 294 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 295 296 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 297 OMAP_UART_TCR_HALT(52)); 298 serial_out(up, UART_TI752_TLR, 299 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 300 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 301 302 serial_out(up, UART_LCR, 0); 303 304 /* drop TCR + TLR access, we setup XON/XOFF later */ 305 serial8250_out_MCR(up, up->mcr); 306 serial_out(up, UART_IER, up->ier); 307 308 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 309 serial_dl_write(up, priv->quot); 310 311 serial_out(up, UART_EFR, priv->efr); 312 313 /* Configure flow control */ 314 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 315 serial_out(up, UART_XON1, priv->xon); 316 serial_out(up, UART_XOFF1, priv->xoff); 317 318 serial_out(up, UART_LCR, up->lcr); 319 320 omap8250_update_mdr1(up, priv); 321 322 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 323 } 324 325 /* 326 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 327 * some differences in how we want to handle flow control. 328 */ 329 static void omap_8250_set_termios(struct uart_port *port, 330 struct ktermios *termios, 331 struct ktermios *old) 332 { 333 struct uart_8250_port *up = up_to_u8250p(port); 334 struct omap8250_priv *priv = up->port.private_data; 335 unsigned char cval = 0; 336 unsigned int baud; 337 338 switch (termios->c_cflag & CSIZE) { 339 case CS5: 340 cval = UART_LCR_WLEN5; 341 break; 342 case CS6: 343 cval = UART_LCR_WLEN6; 344 break; 345 case CS7: 346 cval = UART_LCR_WLEN7; 347 break; 348 default: 349 case CS8: 350 cval = UART_LCR_WLEN8; 351 break; 352 } 353 354 if (termios->c_cflag & CSTOPB) 355 cval |= UART_LCR_STOP; 356 if (termios->c_cflag & PARENB) 357 cval |= UART_LCR_PARITY; 358 if (!(termios->c_cflag & PARODD)) 359 cval |= UART_LCR_EPAR; 360 if (termios->c_cflag & CMSPAR) 361 cval |= UART_LCR_SPAR; 362 363 /* 364 * Ask the core to calculate the divisor for us. 365 */ 366 baud = uart_get_baud_rate(port, termios, old, 367 port->uartclk / 16 / UART_DIV_MAX, 368 port->uartclk / 13); 369 omap_8250_get_divisor(port, baud, priv); 370 371 /* 372 * Ok, we're now changing the port state. Do it with 373 * interrupts disabled. 374 */ 375 pm_runtime_get_sync(port->dev); 376 spin_lock_irq(&port->lock); 377 378 /* 379 * Update the per-port timeout. 380 */ 381 uart_update_timeout(port, termios->c_cflag, baud); 382 383 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 384 if (termios->c_iflag & INPCK) 385 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 386 if (termios->c_iflag & (IGNBRK | PARMRK)) 387 up->port.read_status_mask |= UART_LSR_BI; 388 389 /* 390 * Characters to ignore 391 */ 392 up->port.ignore_status_mask = 0; 393 if (termios->c_iflag & IGNPAR) 394 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 395 if (termios->c_iflag & IGNBRK) { 396 up->port.ignore_status_mask |= UART_LSR_BI; 397 /* 398 * If we're ignoring parity and break indicators, 399 * ignore overruns too (for real raw support). 400 */ 401 if (termios->c_iflag & IGNPAR) 402 up->port.ignore_status_mask |= UART_LSR_OE; 403 } 404 405 /* 406 * ignore all characters if CREAD is not set 407 */ 408 if ((termios->c_cflag & CREAD) == 0) 409 up->port.ignore_status_mask |= UART_LSR_DR; 410 411 /* 412 * Modem status interrupts 413 */ 414 up->ier &= ~UART_IER_MSI; 415 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 416 up->ier |= UART_IER_MSI; 417 418 up->lcr = cval; 419 /* Up to here it was mostly serial8250_do_set_termios() */ 420 421 /* 422 * We enable TRIG_GRANU for RX and TX and additionally we set 423 * SCR_TX_EMPTY bit. The result is the following: 424 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 425 * - less than RX_TRIGGER number of bytes will also cause an interrupt 426 * once the UART decides that there no new bytes arriving. 427 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 428 * empty - the trigger level is ignored here. 429 * 430 * Once DMA is enabled: 431 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 432 * bytes in the TX FIFO. On each assert the DMA engine will move 433 * TX_TRIGGER bytes into the FIFO. 434 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 435 * the FIFO and move RX_TRIGGER bytes. 436 * This is because threshold and trigger values are the same. 437 */ 438 up->fcr = UART_FCR_ENABLE_FIFO; 439 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 440 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 441 442 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 443 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 444 445 if (up->dma) 446 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 447 OMAP_UART_SCR_DMAMODE_CTL; 448 449 priv->xon = termios->c_cc[VSTART]; 450 priv->xoff = termios->c_cc[VSTOP]; 451 452 priv->efr = 0; 453 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 454 455 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 456 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 457 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 458 priv->efr |= UART_EFR_CTS; 459 } else if (up->port.flags & UPF_SOFT_FLOW) { 460 /* 461 * OMAP rx s/w flow control is borked; the transmitter remains 462 * stuck off even if rx flow control is subsequently disabled 463 */ 464 465 /* 466 * IXOFF Flag: 467 * Enable XON/XOFF flow control on output. 468 * Transmit XON1, XOFF1 469 */ 470 if (termios->c_iflag & IXOFF) { 471 up->port.status |= UPSTAT_AUTOXOFF; 472 priv->efr |= OMAP_UART_SW_TX; 473 } 474 } 475 omap8250_restore_regs(up); 476 477 spin_unlock_irq(&up->port.lock); 478 pm_runtime_mark_last_busy(port->dev); 479 pm_runtime_put_autosuspend(port->dev); 480 481 /* calculate wakeup latency constraint */ 482 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 483 priv->latency = priv->calc_latency; 484 485 schedule_work(&priv->qos_work); 486 487 /* Don't rewrite B0 */ 488 if (tty_termios_baud_rate(termios)) 489 tty_termios_encode_baud_rate(termios, baud, baud); 490 } 491 492 /* same as 8250 except that we may have extra flow bits set in EFR */ 493 static void omap_8250_pm(struct uart_port *port, unsigned int state, 494 unsigned int oldstate) 495 { 496 struct uart_8250_port *up = up_to_u8250p(port); 497 u8 efr; 498 499 pm_runtime_get_sync(port->dev); 500 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 501 efr = serial_in(up, UART_EFR); 502 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 503 serial_out(up, UART_LCR, 0); 504 505 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 506 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 507 serial_out(up, UART_EFR, efr); 508 serial_out(up, UART_LCR, 0); 509 510 pm_runtime_mark_last_busy(port->dev); 511 pm_runtime_put_autosuspend(port->dev); 512 } 513 514 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 515 struct omap8250_priv *priv) 516 { 517 u32 mvr, scheme; 518 u16 revision, major, minor; 519 520 mvr = uart_read(up, UART_OMAP_MVER); 521 522 /* Check revision register scheme */ 523 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 524 525 switch (scheme) { 526 case 0: /* Legacy Scheme: OMAP2/3 */ 527 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 528 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 529 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 530 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 531 break; 532 case 1: 533 /* New Scheme: OMAP4+ */ 534 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 535 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 536 OMAP_UART_MVR_MAJ_SHIFT; 537 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 538 break; 539 default: 540 dev_warn(up->port.dev, 541 "Unknown revision, defaulting to highest\n"); 542 /* highest possible revision */ 543 major = 0xff; 544 minor = 0xff; 545 } 546 /* normalize revision for the driver */ 547 revision = UART_BUILD_REVISION(major, minor); 548 549 switch (revision) { 550 case OMAP_UART_REV_46: 551 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 552 break; 553 case OMAP_UART_REV_52: 554 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 555 OMAP_UART_WER_HAS_TX_WAKEUP; 556 break; 557 case OMAP_UART_REV_63: 558 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 559 OMAP_UART_WER_HAS_TX_WAKEUP; 560 break; 561 default: 562 break; 563 } 564 } 565 566 static void omap8250_uart_qos_work(struct work_struct *work) 567 { 568 struct omap8250_priv *priv; 569 570 priv = container_of(work, struct omap8250_priv, qos_work); 571 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 572 } 573 574 #ifdef CONFIG_SERIAL_8250_DMA 575 static int omap_8250_dma_handle_irq(struct uart_port *port); 576 #endif 577 578 static irqreturn_t omap8250_irq(int irq, void *dev_id) 579 { 580 struct uart_port *port = dev_id; 581 struct uart_8250_port *up = up_to_u8250p(port); 582 unsigned int iir; 583 int ret; 584 585 #ifdef CONFIG_SERIAL_8250_DMA 586 if (up->dma) { 587 ret = omap_8250_dma_handle_irq(port); 588 return IRQ_RETVAL(ret); 589 } 590 #endif 591 592 serial8250_rpm_get(up); 593 iir = serial_port_in(port, UART_IIR); 594 ret = serial8250_handle_irq(port, iir); 595 serial8250_rpm_put(up); 596 597 return IRQ_RETVAL(ret); 598 } 599 600 static int omap_8250_startup(struct uart_port *port) 601 { 602 struct uart_8250_port *up = up_to_u8250p(port); 603 struct omap8250_priv *priv = port->private_data; 604 int ret; 605 606 if (priv->wakeirq) { 607 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 608 if (ret) 609 return ret; 610 } 611 612 pm_runtime_get_sync(port->dev); 613 614 up->mcr = 0; 615 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 616 617 serial_out(up, UART_LCR, UART_LCR_WLEN8); 618 619 up->lsr_saved_flags = 0; 620 up->msr_saved_flags = 0; 621 622 /* Disable DMA for console UART */ 623 if (uart_console(port)) 624 up->dma = NULL; 625 626 if (up->dma) { 627 ret = serial8250_request_dma(up); 628 if (ret) { 629 dev_warn_ratelimited(port->dev, 630 "failed to request DMA\n"); 631 up->dma = NULL; 632 } 633 } 634 635 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 636 dev_name(port->dev), port); 637 if (ret < 0) 638 goto err; 639 640 up->ier = UART_IER_RLSI | UART_IER_RDI; 641 serial_out(up, UART_IER, up->ier); 642 643 #ifdef CONFIG_PM 644 up->capabilities |= UART_CAP_RPM; 645 #endif 646 647 /* Enable module level wake up */ 648 priv->wer = OMAP_UART_WER_MOD_WKUP; 649 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 650 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 651 serial_out(up, UART_OMAP_WER, priv->wer); 652 653 if (up->dma) 654 up->dma->rx_dma(up); 655 656 pm_runtime_mark_last_busy(port->dev); 657 pm_runtime_put_autosuspend(port->dev); 658 return 0; 659 err: 660 pm_runtime_mark_last_busy(port->dev); 661 pm_runtime_put_autosuspend(port->dev); 662 dev_pm_clear_wake_irq(port->dev); 663 return ret; 664 } 665 666 static void omap_8250_shutdown(struct uart_port *port) 667 { 668 struct uart_8250_port *up = up_to_u8250p(port); 669 struct omap8250_priv *priv = port->private_data; 670 671 flush_work(&priv->qos_work); 672 if (up->dma) 673 omap_8250_rx_dma_flush(up); 674 675 pm_runtime_get_sync(port->dev); 676 677 serial_out(up, UART_OMAP_WER, 0); 678 679 up->ier = 0; 680 serial_out(up, UART_IER, 0); 681 682 if (up->dma) 683 serial8250_release_dma(up); 684 685 /* 686 * Disable break condition and FIFOs 687 */ 688 if (up->lcr & UART_LCR_SBC) 689 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 690 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 691 692 pm_runtime_mark_last_busy(port->dev); 693 pm_runtime_put_autosuspend(port->dev); 694 free_irq(port->irq, port); 695 dev_pm_clear_wake_irq(port->dev); 696 } 697 698 static void omap_8250_throttle(struct uart_port *port) 699 { 700 struct omap8250_priv *priv = port->private_data; 701 struct uart_8250_port *up = up_to_u8250p(port); 702 unsigned long flags; 703 704 pm_runtime_get_sync(port->dev); 705 706 spin_lock_irqsave(&port->lock, flags); 707 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 708 serial_out(up, UART_IER, up->ier); 709 priv->throttled = true; 710 spin_unlock_irqrestore(&port->lock, flags); 711 712 pm_runtime_mark_last_busy(port->dev); 713 pm_runtime_put_autosuspend(port->dev); 714 } 715 716 static int omap_8250_rs485_config(struct uart_port *port, 717 struct serial_rs485 *rs485) 718 { 719 struct uart_8250_port *up = up_to_u8250p(port); 720 721 /* Clamp the delays to [0, 100ms] */ 722 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 723 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 724 725 port->rs485 = *rs485; 726 727 /* 728 * Both serial8250_em485_init and serial8250_em485_destroy 729 * are idempotent 730 */ 731 if (rs485->flags & SER_RS485_ENABLED) { 732 int ret = serial8250_em485_init(up); 733 734 if (ret) { 735 rs485->flags &= ~SER_RS485_ENABLED; 736 port->rs485.flags &= ~SER_RS485_ENABLED; 737 } 738 return ret; 739 } 740 741 serial8250_em485_destroy(up); 742 743 return 0; 744 } 745 746 static void omap_8250_unthrottle(struct uart_port *port) 747 { 748 struct omap8250_priv *priv = port->private_data; 749 struct uart_8250_port *up = up_to_u8250p(port); 750 unsigned long flags; 751 752 pm_runtime_get_sync(port->dev); 753 754 spin_lock_irqsave(&port->lock, flags); 755 priv->throttled = false; 756 if (up->dma) 757 up->dma->rx_dma(up); 758 up->ier |= UART_IER_RLSI | UART_IER_RDI; 759 serial_out(up, UART_IER, up->ier); 760 spin_unlock_irqrestore(&port->lock, flags); 761 762 pm_runtime_mark_last_busy(port->dev); 763 pm_runtime_put_autosuspend(port->dev); 764 } 765 766 #ifdef CONFIG_SERIAL_8250_DMA 767 static int omap_8250_rx_dma(struct uart_8250_port *p); 768 769 static void __dma_rx_do_complete(struct uart_8250_port *p) 770 { 771 struct omap8250_priv *priv = p->port.private_data; 772 struct uart_8250_dma *dma = p->dma; 773 struct tty_port *tty_port = &p->port.state->port; 774 struct dma_tx_state state; 775 int count; 776 unsigned long flags; 777 int ret; 778 779 spin_lock_irqsave(&priv->rx_dma_lock, flags); 780 781 if (!dma->rx_running) 782 goto unlock; 783 784 dma->rx_running = 0; 785 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 786 787 count = dma->rx_size - state.residue; 788 789 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 790 791 p->port.icount.rx += ret; 792 p->port.icount.buf_overrun += count - ret; 793 unlock: 794 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 795 796 tty_flip_buffer_push(tty_port); 797 } 798 799 static void __dma_rx_complete(void *param) 800 { 801 struct uart_8250_port *p = param; 802 struct omap8250_priv *priv = p->port.private_data; 803 struct uart_8250_dma *dma = p->dma; 804 struct dma_tx_state state; 805 unsigned long flags; 806 807 spin_lock_irqsave(&p->port.lock, flags); 808 809 /* 810 * If the tx status is not DMA_COMPLETE, then this is a delayed 811 * completion callback. A previous RX timeout flush would have 812 * already pushed the data, so exit. 813 */ 814 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 815 DMA_COMPLETE) { 816 spin_unlock_irqrestore(&p->port.lock, flags); 817 return; 818 } 819 __dma_rx_do_complete(p); 820 if (!priv->throttled) 821 omap_8250_rx_dma(p); 822 823 spin_unlock_irqrestore(&p->port.lock, flags); 824 } 825 826 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 827 { 828 struct omap8250_priv *priv = p->port.private_data; 829 struct uart_8250_dma *dma = p->dma; 830 struct dma_tx_state state; 831 unsigned long flags; 832 int ret; 833 834 spin_lock_irqsave(&priv->rx_dma_lock, flags); 835 836 if (!dma->rx_running) { 837 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 838 return; 839 } 840 841 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 842 if (ret == DMA_IN_PROGRESS) { 843 ret = dmaengine_pause(dma->rxchan); 844 if (WARN_ON_ONCE(ret)) 845 priv->rx_dma_broken = true; 846 } 847 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 848 849 __dma_rx_do_complete(p); 850 dmaengine_terminate_all(dma->rxchan); 851 } 852 853 static int omap_8250_rx_dma(struct uart_8250_port *p) 854 { 855 struct omap8250_priv *priv = p->port.private_data; 856 struct uart_8250_dma *dma = p->dma; 857 int err = 0; 858 struct dma_async_tx_descriptor *desc; 859 unsigned long flags; 860 861 if (priv->rx_dma_broken) 862 return -EINVAL; 863 864 spin_lock_irqsave(&priv->rx_dma_lock, flags); 865 866 if (dma->rx_running) 867 goto out; 868 869 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 870 dma->rx_size, DMA_DEV_TO_MEM, 871 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 872 if (!desc) { 873 err = -EBUSY; 874 goto out; 875 } 876 877 dma->rx_running = 1; 878 desc->callback = __dma_rx_complete; 879 desc->callback_param = p; 880 881 dma->rx_cookie = dmaengine_submit(desc); 882 883 dma_async_issue_pending(dma->rxchan); 884 out: 885 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 886 return err; 887 } 888 889 static int omap_8250_tx_dma(struct uart_8250_port *p); 890 891 static void omap_8250_dma_tx_complete(void *param) 892 { 893 struct uart_8250_port *p = param; 894 struct uart_8250_dma *dma = p->dma; 895 struct circ_buf *xmit = &p->port.state->xmit; 896 unsigned long flags; 897 bool en_thri = false; 898 struct omap8250_priv *priv = p->port.private_data; 899 900 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 901 UART_XMIT_SIZE, DMA_TO_DEVICE); 902 903 spin_lock_irqsave(&p->port.lock, flags); 904 905 dma->tx_running = 0; 906 907 xmit->tail += dma->tx_size; 908 xmit->tail &= UART_XMIT_SIZE - 1; 909 p->port.icount.tx += dma->tx_size; 910 911 if (priv->delayed_restore) { 912 priv->delayed_restore = 0; 913 omap8250_restore_regs(p); 914 } 915 916 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 917 uart_write_wakeup(&p->port); 918 919 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 920 int ret; 921 922 ret = omap_8250_tx_dma(p); 923 if (ret) 924 en_thri = true; 925 926 } else if (p->capabilities & UART_CAP_RPM) { 927 en_thri = true; 928 } 929 930 if (en_thri) { 931 dma->tx_err = 1; 932 p->ier |= UART_IER_THRI; 933 serial_port_out(&p->port, UART_IER, p->ier); 934 } 935 936 spin_unlock_irqrestore(&p->port.lock, flags); 937 } 938 939 static int omap_8250_tx_dma(struct uart_8250_port *p) 940 { 941 struct uart_8250_dma *dma = p->dma; 942 struct omap8250_priv *priv = p->port.private_data; 943 struct circ_buf *xmit = &p->port.state->xmit; 944 struct dma_async_tx_descriptor *desc; 945 unsigned int skip_byte = 0; 946 int ret; 947 948 if (dma->tx_running) 949 return 0; 950 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 951 952 /* 953 * Even if no data, we need to return an error for the two cases 954 * below so serial8250_tx_chars() is invoked and properly clears 955 * THRI and/or runtime suspend. 956 */ 957 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 958 ret = -EBUSY; 959 goto err; 960 } 961 if (p->ier & UART_IER_THRI) { 962 p->ier &= ~UART_IER_THRI; 963 serial_out(p, UART_IER, p->ier); 964 } 965 return 0; 966 } 967 968 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 969 if (priv->habit & OMAP_DMA_TX_KICK) { 970 u8 tx_lvl; 971 972 /* 973 * We need to put the first byte into the FIFO in order to start 974 * the DMA transfer. For transfers smaller than four bytes we 975 * don't bother doing DMA at all. It seem not matter if there 976 * are still bytes in the FIFO from the last transfer (in case 977 * we got here directly from omap_8250_dma_tx_complete()). Bytes 978 * leaving the FIFO seem not to trigger the DMA transfer. It is 979 * really the byte that we put into the FIFO. 980 * If the FIFO is already full then we most likely got here from 981 * omap_8250_dma_tx_complete(). And this means the DMA engine 982 * just completed its work. We don't have to wait the complete 983 * 86us at 115200,8n1 but around 60us (not to mention lower 984 * baudrates). So in that case we take the interrupt and try 985 * again with an empty FIFO. 986 */ 987 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 988 if (tx_lvl == p->tx_loadsz) { 989 ret = -EBUSY; 990 goto err; 991 } 992 if (dma->tx_size < 4) { 993 ret = -EINVAL; 994 goto err; 995 } 996 skip_byte = 1; 997 } 998 999 desc = dmaengine_prep_slave_single(dma->txchan, 1000 dma->tx_addr + xmit->tail + skip_byte, 1001 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1002 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1003 if (!desc) { 1004 ret = -EBUSY; 1005 goto err; 1006 } 1007 1008 dma->tx_running = 1; 1009 1010 desc->callback = omap_8250_dma_tx_complete; 1011 desc->callback_param = p; 1012 1013 dma->tx_cookie = dmaengine_submit(desc); 1014 1015 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1016 UART_XMIT_SIZE, DMA_TO_DEVICE); 1017 1018 dma_async_issue_pending(dma->txchan); 1019 if (dma->tx_err) 1020 dma->tx_err = 0; 1021 1022 if (p->ier & UART_IER_THRI) { 1023 p->ier &= ~UART_IER_THRI; 1024 serial_out(p, UART_IER, p->ier); 1025 } 1026 if (skip_byte) 1027 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1028 return 0; 1029 err: 1030 dma->tx_err = 1; 1031 return ret; 1032 } 1033 1034 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1035 { 1036 switch (iir & 0x3f) { 1037 case UART_IIR_RLSI: 1038 case UART_IIR_RX_TIMEOUT: 1039 case UART_IIR_RDI: 1040 omap_8250_rx_dma_flush(up); 1041 return true; 1042 } 1043 return omap_8250_rx_dma(up); 1044 } 1045 1046 /* 1047 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1048 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1049 * use the default routine in the non-DMA case and this one for with DMA. 1050 */ 1051 static int omap_8250_dma_handle_irq(struct uart_port *port) 1052 { 1053 struct uart_8250_port *up = up_to_u8250p(port); 1054 unsigned char status; 1055 unsigned long flags; 1056 u8 iir; 1057 1058 serial8250_rpm_get(up); 1059 1060 iir = serial_port_in(port, UART_IIR); 1061 if (iir & UART_IIR_NO_INT) { 1062 serial8250_rpm_put(up); 1063 return 0; 1064 } 1065 1066 spin_lock_irqsave(&port->lock, flags); 1067 1068 status = serial_port_in(port, UART_LSR); 1069 1070 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1071 if (handle_rx_dma(up, iir)) { 1072 status = serial8250_rx_chars(up, status); 1073 omap_8250_rx_dma(up); 1074 } 1075 } 1076 serial8250_modem_status(up); 1077 if (status & UART_LSR_THRE && up->dma->tx_err) { 1078 if (uart_tx_stopped(&up->port) || 1079 uart_circ_empty(&up->port.state->xmit)) { 1080 up->dma->tx_err = 0; 1081 serial8250_tx_chars(up); 1082 } else { 1083 /* 1084 * try again due to an earlier failer which 1085 * might have been resolved by now. 1086 */ 1087 if (omap_8250_tx_dma(up)) 1088 serial8250_tx_chars(up); 1089 } 1090 } 1091 1092 uart_unlock_and_check_sysrq(port, flags); 1093 serial8250_rpm_put(up); 1094 return 1; 1095 } 1096 1097 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1098 { 1099 return false; 1100 } 1101 1102 #else 1103 1104 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1105 { 1106 return -EINVAL; 1107 } 1108 #endif 1109 1110 static int omap8250_no_handle_irq(struct uart_port *port) 1111 { 1112 /* IRQ has not been requested but handling irq? */ 1113 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1114 return 0; 1115 } 1116 1117 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE; 1118 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; 1119 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE; 1120 1121 static const struct of_device_id omap8250_dt_ids[] = { 1122 { .compatible = "ti,am654-uart" }, 1123 { .compatible = "ti,omap2-uart" }, 1124 { .compatible = "ti,omap3-uart" }, 1125 { .compatible = "ti,omap4-uart", .data = &omap4_habit, }, 1126 { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, 1127 { .compatible = "ti,am4372-uart", .data = &am3352_habit, }, 1128 { .compatible = "ti,dra742-uart", .data = &dra742_habit, }, 1129 {}, 1130 }; 1131 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1132 1133 static int omap8250_probe(struct platform_device *pdev) 1134 { 1135 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1136 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1137 struct omap8250_priv *priv; 1138 struct uart_8250_port up; 1139 int ret; 1140 void __iomem *membase; 1141 1142 if (!regs || !irq) { 1143 dev_err(&pdev->dev, "missing registers or irq\n"); 1144 return -EINVAL; 1145 } 1146 1147 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1148 if (!priv) 1149 return -ENOMEM; 1150 1151 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1152 resource_size(regs)); 1153 if (!membase) 1154 return -ENODEV; 1155 1156 memset(&up, 0, sizeof(up)); 1157 up.port.dev = &pdev->dev; 1158 up.port.mapbase = regs->start; 1159 up.port.membase = membase; 1160 up.port.irq = irq->start; 1161 /* 1162 * It claims to be 16C750 compatible however it is a little different. 1163 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1164 * have) is enabled via EFR instead of MCR. The type is set here 8250 1165 * just to get things going. UNKNOWN does not work for a few reasons and 1166 * we don't need our own type since we don't use 8250's set_termios() 1167 * or pm callback. 1168 */ 1169 up.port.type = PORT_8250; 1170 up.port.iotype = UPIO_MEM; 1171 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1172 UPF_HARD_FLOW; 1173 up.port.private_data = priv; 1174 1175 up.port.regshift = 2; 1176 up.port.fifosize = 64; 1177 up.tx_loadsz = 64; 1178 up.capabilities = UART_CAP_FIFO; 1179 #ifdef CONFIG_PM 1180 /* 1181 * Runtime PM is mostly transparent. However to do it right we need to a 1182 * TX empty interrupt before we can put the device to auto idle. So if 1183 * PM is not enabled we don't add that flag and can spare that one extra 1184 * interrupt in the TX path. 1185 */ 1186 up.capabilities |= UART_CAP_RPM; 1187 #endif 1188 up.port.set_termios = omap_8250_set_termios; 1189 up.port.set_mctrl = omap8250_set_mctrl; 1190 up.port.pm = omap_8250_pm; 1191 up.port.startup = omap_8250_startup; 1192 up.port.shutdown = omap_8250_shutdown; 1193 up.port.throttle = omap_8250_throttle; 1194 up.port.unthrottle = omap_8250_unthrottle; 1195 up.port.rs485_config = omap_8250_rs485_config; 1196 1197 if (pdev->dev.of_node) { 1198 const struct of_device_id *id; 1199 1200 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1201 1202 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1203 &up.port.uartclk); 1204 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1205 1206 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); 1207 if (id && id->data) 1208 priv->habit |= *(u8 *)id->data; 1209 } else { 1210 ret = pdev->id; 1211 } 1212 if (ret < 0) { 1213 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1214 return ret; 1215 } 1216 up.port.line = ret; 1217 1218 if (!up.port.uartclk) { 1219 up.port.uartclk = DEFAULT_CLK_SPEED; 1220 dev_warn(&pdev->dev, 1221 "No clock speed specified: using default: %d\n", 1222 DEFAULT_CLK_SPEED); 1223 } 1224 1225 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1226 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1227 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1228 priv->latency); 1229 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1230 1231 spin_lock_init(&priv->rx_dma_lock); 1232 1233 device_init_wakeup(&pdev->dev, true); 1234 pm_runtime_use_autosuspend(&pdev->dev); 1235 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1236 1237 pm_runtime_irq_safe(&pdev->dev); 1238 pm_runtime_enable(&pdev->dev); 1239 1240 pm_runtime_get_sync(&pdev->dev); 1241 1242 omap_serial_fill_features_erratas(&up, priv); 1243 up.port.handle_irq = omap8250_no_handle_irq; 1244 #ifdef CONFIG_SERIAL_8250_DMA 1245 if (pdev->dev.of_node) { 1246 /* 1247 * Oh DMA support. If there are no DMA properties in the DT then 1248 * we will fall back to a generic DMA channel which does not 1249 * really work here. To ensure that we do not get a generic DMA 1250 * channel assigned, we have the the_no_dma_filter_fn() here. 1251 * To avoid "failed to request DMA" messages we check for DMA 1252 * properties in DT. 1253 */ 1254 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1255 if (ret == 2) { 1256 up.dma = &priv->omap8250_dma; 1257 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1258 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1259 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1260 priv->omap8250_dma.rx_size = RX_TRIGGER; 1261 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1262 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1263 } 1264 } 1265 #endif 1266 ret = serial8250_register_8250_port(&up); 1267 if (ret < 0) { 1268 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1269 goto err; 1270 } 1271 priv->line = ret; 1272 platform_set_drvdata(pdev, priv); 1273 pm_runtime_mark_last_busy(&pdev->dev); 1274 pm_runtime_put_autosuspend(&pdev->dev); 1275 return 0; 1276 err: 1277 pm_runtime_dont_use_autosuspend(&pdev->dev); 1278 pm_runtime_put_sync(&pdev->dev); 1279 pm_runtime_disable(&pdev->dev); 1280 return ret; 1281 } 1282 1283 static int omap8250_remove(struct platform_device *pdev) 1284 { 1285 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1286 1287 pm_runtime_dont_use_autosuspend(&pdev->dev); 1288 pm_runtime_put_sync(&pdev->dev); 1289 pm_runtime_disable(&pdev->dev); 1290 serial8250_unregister_port(priv->line); 1291 pm_qos_remove_request(&priv->pm_qos_request); 1292 device_init_wakeup(&pdev->dev, false); 1293 return 0; 1294 } 1295 1296 #ifdef CONFIG_PM_SLEEP 1297 static int omap8250_prepare(struct device *dev) 1298 { 1299 struct omap8250_priv *priv = dev_get_drvdata(dev); 1300 1301 if (!priv) 1302 return 0; 1303 priv->is_suspending = true; 1304 return 0; 1305 } 1306 1307 static void omap8250_complete(struct device *dev) 1308 { 1309 struct omap8250_priv *priv = dev_get_drvdata(dev); 1310 1311 if (!priv) 1312 return; 1313 priv->is_suspending = false; 1314 } 1315 1316 static int omap8250_suspend(struct device *dev) 1317 { 1318 struct omap8250_priv *priv = dev_get_drvdata(dev); 1319 struct uart_8250_port *up = serial8250_get_port(priv->line); 1320 1321 serial8250_suspend_port(priv->line); 1322 1323 pm_runtime_get_sync(dev); 1324 if (!device_may_wakeup(dev)) 1325 priv->wer = 0; 1326 serial_out(up, UART_OMAP_WER, priv->wer); 1327 pm_runtime_mark_last_busy(dev); 1328 pm_runtime_put_autosuspend(dev); 1329 1330 flush_work(&priv->qos_work); 1331 return 0; 1332 } 1333 1334 static int omap8250_resume(struct device *dev) 1335 { 1336 struct omap8250_priv *priv = dev_get_drvdata(dev); 1337 1338 serial8250_resume_port(priv->line); 1339 return 0; 1340 } 1341 #else 1342 #define omap8250_prepare NULL 1343 #define omap8250_complete NULL 1344 #endif 1345 1346 #ifdef CONFIG_PM 1347 static int omap8250_lost_context(struct uart_8250_port *up) 1348 { 1349 u32 val; 1350 1351 val = serial_in(up, UART_OMAP_SCR); 1352 /* 1353 * If we lose context, then SCR is set to its reset value of zero. 1354 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1355 * among other bits, to never set the register back to zero again. 1356 */ 1357 if (!val) 1358 return 1; 1359 return 0; 1360 } 1361 1362 /* TODO: in future, this should happen via API in drivers/reset/ */ 1363 static int omap8250_soft_reset(struct device *dev) 1364 { 1365 struct omap8250_priv *priv = dev_get_drvdata(dev); 1366 struct uart_8250_port *up = serial8250_get_port(priv->line); 1367 int timeout = 100; 1368 int sysc; 1369 int syss; 1370 1371 /* 1372 * At least on omap4, unused uarts may not idle after reset without 1373 * a basic scr dma configuration even with no dma in use. The 1374 * module clkctrl status bits will be 1 instead of 3 blocking idle 1375 * for the whole clockdomain. The softreset below will clear scr, 1376 * and we restore it on resume so this is safe to do on all SoCs 1377 * needing omap8250_soft_reset() quirk. Do it in two writes as 1378 * recommended in the comment for omap8250_update_scr(). 1379 */ 1380 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1381 serial_out(up, UART_OMAP_SCR, 1382 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1383 1384 sysc = serial_in(up, UART_OMAP_SYSC); 1385 1386 /* softreset the UART */ 1387 sysc |= OMAP_UART_SYSC_SOFTRESET; 1388 serial_out(up, UART_OMAP_SYSC, sysc); 1389 1390 /* By experiments, 1us enough for reset complete on AM335x */ 1391 do { 1392 udelay(1); 1393 syss = serial_in(up, UART_OMAP_SYSS); 1394 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1395 1396 if (!timeout) { 1397 dev_err(dev, "timed out waiting for reset done\n"); 1398 return -ETIMEDOUT; 1399 } 1400 1401 return 0; 1402 } 1403 1404 static int omap8250_runtime_suspend(struct device *dev) 1405 { 1406 struct omap8250_priv *priv = dev_get_drvdata(dev); 1407 struct uart_8250_port *up; 1408 1409 /* In case runtime-pm tries this before we are setup */ 1410 if (!priv) 1411 return 0; 1412 1413 up = serial8250_get_port(priv->line); 1414 /* 1415 * When using 'no_console_suspend', the console UART must not be 1416 * suspended. Since driver suspend is managed by runtime suspend, 1417 * preventing runtime suspend (by returning error) will keep device 1418 * active during suspend. 1419 */ 1420 if (priv->is_suspending && !console_suspend_enabled) { 1421 if (uart_console(&up->port)) 1422 return -EBUSY; 1423 } 1424 1425 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1426 int ret; 1427 1428 ret = omap8250_soft_reset(dev); 1429 if (ret) 1430 return ret; 1431 1432 /* Restore to UART mode after reset (for wakeup) */ 1433 omap8250_update_mdr1(up, priv); 1434 /* Restore wakeup enable register */ 1435 serial_out(up, UART_OMAP_WER, priv->wer); 1436 } 1437 1438 if (up->dma && up->dma->rxchan) 1439 omap_8250_rx_dma_flush(up); 1440 1441 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1442 schedule_work(&priv->qos_work); 1443 1444 return 0; 1445 } 1446 1447 static int omap8250_runtime_resume(struct device *dev) 1448 { 1449 struct omap8250_priv *priv = dev_get_drvdata(dev); 1450 struct uart_8250_port *up; 1451 1452 /* In case runtime-pm tries this before we are setup */ 1453 if (!priv) 1454 return 0; 1455 1456 up = serial8250_get_port(priv->line); 1457 1458 if (omap8250_lost_context(up)) 1459 omap8250_restore_regs(up); 1460 1461 if (up->dma && up->dma->rxchan) 1462 omap_8250_rx_dma(up); 1463 1464 priv->latency = priv->calc_latency; 1465 schedule_work(&priv->qos_work); 1466 return 0; 1467 } 1468 #endif 1469 1470 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1471 static int __init omap8250_console_fixup(void) 1472 { 1473 char *omap_str; 1474 char *options; 1475 u8 idx; 1476 1477 if (strstr(boot_command_line, "console=ttyS")) 1478 /* user set a ttyS based name for the console */ 1479 return 0; 1480 1481 omap_str = strstr(boot_command_line, "console=ttyO"); 1482 if (!omap_str) 1483 /* user did not set ttyO based console, so we don't care */ 1484 return 0; 1485 1486 omap_str += 12; 1487 if ('0' <= *omap_str && *omap_str <= '9') 1488 idx = *omap_str - '0'; 1489 else 1490 return 0; 1491 1492 omap_str++; 1493 if (omap_str[0] == ',') { 1494 omap_str++; 1495 options = omap_str; 1496 } else { 1497 options = NULL; 1498 } 1499 1500 add_preferred_console("ttyS", idx, options); 1501 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1502 idx, idx); 1503 pr_err("This ensures that you still see kernel messages. Please\n"); 1504 pr_err("update your kernel commandline.\n"); 1505 return 0; 1506 } 1507 console_initcall(omap8250_console_fixup); 1508 #endif 1509 1510 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1511 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1512 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1513 omap8250_runtime_resume, NULL) 1514 .prepare = omap8250_prepare, 1515 .complete = omap8250_complete, 1516 }; 1517 1518 static struct platform_driver omap8250_platform_driver = { 1519 .driver = { 1520 .name = "omap8250", 1521 .pm = &omap8250_dev_pm_ops, 1522 .of_match_table = omap8250_dt_ids, 1523 }, 1524 .probe = omap8250_probe, 1525 .remove = omap8250_remove, 1526 }; 1527 module_platform_driver(omap8250_platform_driver); 1528 1529 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1530 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1531 MODULE_LICENSE("GPL v2"); 1532