1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_core.h> 15 #include <linux/serial_reg.h> 16 #include <linux/tty_flip.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/delay.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/console.h> 25 #include <linux/pm_qos.h> 26 #include <linux/dma-mapping.h> 27 28 #include "8250.h" 29 30 #define DEFAULT_CLK_SPEED 48000000 31 32 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 33 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 34 #define OMAP_DMA_TX_KICK (1 << 2) 35 36 #define OMAP_UART_FCR_RX_TRIG 6 37 #define OMAP_UART_FCR_TX_TRIG 4 38 39 /* SCR register bitmasks */ 40 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 41 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 42 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 43 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 44 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 45 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 46 47 /* MVR register bitmasks */ 48 #define OMAP_UART_MVR_SCHEME_SHIFT 30 49 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 50 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 51 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 52 #define OMAP_UART_MVR_MAJ_MASK 0x700 53 #define OMAP_UART_MVR_MAJ_SHIFT 8 54 #define OMAP_UART_MVR_MIN_MASK 0x3f 55 56 #define UART_TI752_TLR_TX 0 57 #define UART_TI752_TLR_RX 4 58 59 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 60 #define TRIGGER_FCR_MASK(x) (x & 3) 61 62 /* Enable XON/XOFF flow control on output */ 63 #define OMAP_UART_SW_TX 0x08 64 /* Enable XON/XOFF flow control on input */ 65 #define OMAP_UART_SW_RX 0x02 66 67 #define OMAP_UART_WER_MOD_WKUP 0x7f 68 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 69 70 #define TX_TRIGGER 1 71 #define RX_TRIGGER 48 72 73 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 74 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 75 76 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 77 78 #define OMAP_UART_REV_46 0x0406 79 #define OMAP_UART_REV_52 0x0502 80 #define OMAP_UART_REV_63 0x0603 81 82 struct omap8250_priv { 83 int line; 84 u8 habit; 85 u8 mdr1; 86 u8 efr; 87 u8 scr; 88 u8 wer; 89 u8 xon; 90 u8 xoff; 91 u8 delayed_restore; 92 u16 quot; 93 94 bool is_suspending; 95 int wakeirq; 96 int wakeups_enabled; 97 u32 latency; 98 u32 calc_latency; 99 struct pm_qos_request pm_qos_request; 100 struct work_struct qos_work; 101 struct uart_8250_dma omap8250_dma; 102 }; 103 104 static u32 uart_read(struct uart_8250_port *up, u32 reg) 105 { 106 return readl(up->port.membase + (reg << up->port.regshift)); 107 } 108 109 /* 110 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 111 * The access to uart register after MDR1 Access 112 * causes UART to corrupt data. 113 * 114 * Need a delay = 115 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 116 * give 10 times as much 117 */ 118 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 119 struct omap8250_priv *priv) 120 { 121 u8 timeout = 255; 122 u8 old_mdr1; 123 124 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 125 if (old_mdr1 == priv->mdr1) 126 return; 127 128 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 129 udelay(2); 130 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 131 UART_FCR_CLEAR_RCVR); 132 /* 133 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 134 * TX_FIFO_E bit is 1. 135 */ 136 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 137 (UART_LSR_THRE | UART_LSR_DR))) { 138 timeout--; 139 if (!timeout) { 140 /* Should *never* happen. we warn and carry on */ 141 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 142 serial_in(up, UART_LSR)); 143 break; 144 } 145 udelay(1); 146 } 147 } 148 149 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 150 struct omap8250_priv *priv) 151 { 152 unsigned int uartclk = port->uartclk; 153 unsigned int div_13, div_16; 154 unsigned int abs_d13, abs_d16; 155 156 /* 157 * Old custom speed handling. 158 */ 159 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 160 priv->quot = port->custom_divisor & 0xffff; 161 /* 162 * I assume that nobody is using this. But hey, if somebody 163 * would like to specify the divisor _and_ the mode then the 164 * driver is ready and waiting for it. 165 */ 166 if (port->custom_divisor & (1 << 16)) 167 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 168 else 169 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 170 return; 171 } 172 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 173 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 174 175 if (!div_13) 176 div_13 = 1; 177 if (!div_16) 178 div_16 = 1; 179 180 abs_d13 = abs(baud - uartclk / 13 / div_13); 181 abs_d16 = abs(baud - uartclk / 16 / div_16); 182 183 if (abs_d13 >= abs_d16) { 184 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 185 priv->quot = div_16; 186 } else { 187 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 188 priv->quot = div_13; 189 } 190 } 191 192 static void omap8250_update_scr(struct uart_8250_port *up, 193 struct omap8250_priv *priv) 194 { 195 u8 old_scr; 196 197 old_scr = serial_in(up, UART_OMAP_SCR); 198 if (old_scr == priv->scr) 199 return; 200 201 /* 202 * The manual recommends not to enable the DMA mode selector in the SCR 203 * (instead of the FCR) register _and_ selecting the DMA mode as one 204 * register write because this may lead to malfunction. 205 */ 206 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 207 serial_out(up, UART_OMAP_SCR, 208 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 209 serial_out(up, UART_OMAP_SCR, priv->scr); 210 } 211 212 static void omap8250_restore_regs(struct uart_8250_port *up) 213 { 214 struct omap8250_priv *priv = up->port.private_data; 215 struct uart_8250_dma *dma = up->dma; 216 217 if (dma && dma->tx_running) { 218 /* 219 * TCSANOW requests the change to occur immediately however if 220 * we have a TX-DMA operation in progress then it has been 221 * observed that it might stall and never complete. Therefore we 222 * delay DMA completes to prevent this hang from happen. 223 */ 224 priv->delayed_restore = 1; 225 return; 226 } 227 228 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 229 serial_out(up, UART_EFR, UART_EFR_ECB); 230 231 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 232 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 233 serial_out(up, UART_FCR, up->fcr); 234 235 omap8250_update_scr(up, priv); 236 237 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 238 239 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 240 OMAP_UART_TCR_HALT(52)); 241 serial_out(up, UART_TI752_TLR, 242 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 243 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 244 245 serial_out(up, UART_LCR, 0); 246 247 /* drop TCR + TLR access, we setup XON/XOFF later */ 248 serial_out(up, UART_MCR, up->mcr); 249 serial_out(up, UART_IER, up->ier); 250 251 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 252 serial_dl_write(up, priv->quot); 253 254 serial_out(up, UART_EFR, priv->efr); 255 256 /* Configure flow control */ 257 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 258 serial_out(up, UART_XON1, priv->xon); 259 serial_out(up, UART_XOFF1, priv->xoff); 260 261 serial_out(up, UART_LCR, up->lcr); 262 /* need mode A for FCR */ 263 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 264 omap_8250_mdr1_errataset(up, priv); 265 else 266 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 267 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 268 } 269 270 /* 271 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 272 * some differences in how we want to handle flow control. 273 */ 274 static void omap_8250_set_termios(struct uart_port *port, 275 struct ktermios *termios, 276 struct ktermios *old) 277 { 278 struct uart_8250_port *up = 279 container_of(port, struct uart_8250_port, port); 280 struct omap8250_priv *priv = up->port.private_data; 281 unsigned char cval = 0; 282 unsigned int baud; 283 284 switch (termios->c_cflag & CSIZE) { 285 case CS5: 286 cval = UART_LCR_WLEN5; 287 break; 288 case CS6: 289 cval = UART_LCR_WLEN6; 290 break; 291 case CS7: 292 cval = UART_LCR_WLEN7; 293 break; 294 default: 295 case CS8: 296 cval = UART_LCR_WLEN8; 297 break; 298 } 299 300 if (termios->c_cflag & CSTOPB) 301 cval |= UART_LCR_STOP; 302 if (termios->c_cflag & PARENB) 303 cval |= UART_LCR_PARITY; 304 if (!(termios->c_cflag & PARODD)) 305 cval |= UART_LCR_EPAR; 306 if (termios->c_cflag & CMSPAR) 307 cval |= UART_LCR_SPAR; 308 309 /* 310 * Ask the core to calculate the divisor for us. 311 */ 312 baud = uart_get_baud_rate(port, termios, old, 313 port->uartclk / 16 / 0xffff, 314 port->uartclk / 13); 315 omap_8250_get_divisor(port, baud, priv); 316 317 /* 318 * Ok, we're now changing the port state. Do it with 319 * interrupts disabled. 320 */ 321 pm_runtime_get_sync(port->dev); 322 spin_lock_irq(&port->lock); 323 324 /* 325 * Update the per-port timeout. 326 */ 327 uart_update_timeout(port, termios->c_cflag, baud); 328 329 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 330 if (termios->c_iflag & INPCK) 331 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 332 if (termios->c_iflag & (IGNBRK | PARMRK)) 333 up->port.read_status_mask |= UART_LSR_BI; 334 335 /* 336 * Characters to ignore 337 */ 338 up->port.ignore_status_mask = 0; 339 if (termios->c_iflag & IGNPAR) 340 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 341 if (termios->c_iflag & IGNBRK) { 342 up->port.ignore_status_mask |= UART_LSR_BI; 343 /* 344 * If we're ignoring parity and break indicators, 345 * ignore overruns too (for real raw support). 346 */ 347 if (termios->c_iflag & IGNPAR) 348 up->port.ignore_status_mask |= UART_LSR_OE; 349 } 350 351 /* 352 * ignore all characters if CREAD is not set 353 */ 354 if ((termios->c_cflag & CREAD) == 0) 355 up->port.ignore_status_mask |= UART_LSR_DR; 356 357 /* 358 * Modem status interrupts 359 */ 360 up->ier &= ~UART_IER_MSI; 361 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 362 up->ier |= UART_IER_MSI; 363 364 up->lcr = cval; 365 /* Up to here it was mostly serial8250_do_set_termios() */ 366 367 /* 368 * We enable TRIG_GRANU for RX and TX and additionaly we set 369 * SCR_TX_EMPTY bit. The result is the following: 370 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 371 * - less than RX_TRIGGER number of bytes will also cause an interrupt 372 * once the UART decides that there no new bytes arriving. 373 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 374 * empty - the trigger level is ignored here. 375 * 376 * Once DMA is enabled: 377 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 378 * bytes in the TX FIFO. On each assert the DMA engine will move 379 * TX_TRIGGER bytes into the FIFO. 380 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 381 * the FIFO and move RX_TRIGGER bytes. 382 * This is because threshold and trigger values are the same. 383 */ 384 up->fcr = UART_FCR_ENABLE_FIFO; 385 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 386 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 387 388 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 389 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 390 391 if (up->dma) 392 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 393 OMAP_UART_SCR_DMAMODE_CTL; 394 395 priv->xon = termios->c_cc[VSTART]; 396 priv->xoff = termios->c_cc[VSTOP]; 397 398 priv->efr = 0; 399 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); 400 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 401 /* Enable AUTORTS and AUTOCTS */ 402 priv->efr |= UART_EFR_CTS | UART_EFR_RTS; 403 404 /* Ensure MCR RTS is asserted */ 405 up->mcr |= UART_MCR_RTS; 406 } else if (up->port.flags & UPF_SOFT_FLOW) { 407 /* 408 * IXON Flag: 409 * Enable XON/XOFF flow control on input. 410 * Receiver compares XON1, XOFF1. 411 */ 412 if (termios->c_iflag & IXON) 413 priv->efr |= OMAP_UART_SW_RX; 414 415 /* 416 * IXOFF Flag: 417 * Enable XON/XOFF flow control on output. 418 * Transmit XON1, XOFF1 419 */ 420 if (termios->c_iflag & IXOFF) 421 priv->efr |= OMAP_UART_SW_TX; 422 423 /* 424 * IXANY Flag: 425 * Enable any character to restart output. 426 * Operation resumes after receiving any 427 * character after recognition of the XOFF character 428 */ 429 if (termios->c_iflag & IXANY) 430 up->mcr |= UART_MCR_XONANY; 431 } 432 omap8250_restore_regs(up); 433 434 spin_unlock_irq(&up->port.lock); 435 pm_runtime_mark_last_busy(port->dev); 436 pm_runtime_put_autosuspend(port->dev); 437 438 /* calculate wakeup latency constraint */ 439 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 440 priv->latency = priv->calc_latency; 441 442 schedule_work(&priv->qos_work); 443 444 /* Don't rewrite B0 */ 445 if (tty_termios_baud_rate(termios)) 446 tty_termios_encode_baud_rate(termios, baud, baud); 447 } 448 449 /* same as 8250 except that we may have extra flow bits set in EFR */ 450 static void omap_8250_pm(struct uart_port *port, unsigned int state, 451 unsigned int oldstate) 452 { 453 struct uart_8250_port *up = 454 container_of(port, struct uart_8250_port, port); 455 struct omap8250_priv *priv = up->port.private_data; 456 457 pm_runtime_get_sync(port->dev); 458 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 459 serial_out(up, UART_EFR, priv->efr | UART_EFR_ECB); 460 serial_out(up, UART_LCR, 0); 461 462 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 463 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 464 serial_out(up, UART_EFR, priv->efr); 465 serial_out(up, UART_LCR, 0); 466 467 pm_runtime_mark_last_busy(port->dev); 468 pm_runtime_put_autosuspend(port->dev); 469 } 470 471 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 472 struct omap8250_priv *priv) 473 { 474 u32 mvr, scheme; 475 u16 revision, major, minor; 476 477 mvr = uart_read(up, UART_OMAP_MVER); 478 479 /* Check revision register scheme */ 480 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 481 482 switch (scheme) { 483 case 0: /* Legacy Scheme: OMAP2/3 */ 484 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 485 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 486 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 487 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 488 break; 489 case 1: 490 /* New Scheme: OMAP4+ */ 491 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 492 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 493 OMAP_UART_MVR_MAJ_SHIFT; 494 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 495 break; 496 default: 497 dev_warn(up->port.dev, 498 "Unknown revision, defaulting to highest\n"); 499 /* highest possible revision */ 500 major = 0xff; 501 minor = 0xff; 502 } 503 /* normalize revision for the driver */ 504 revision = UART_BUILD_REVISION(major, minor); 505 506 switch (revision) { 507 case OMAP_UART_REV_46: 508 priv->habit = UART_ERRATA_i202_MDR1_ACCESS; 509 break; 510 case OMAP_UART_REV_52: 511 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 512 OMAP_UART_WER_HAS_TX_WAKEUP; 513 break; 514 case OMAP_UART_REV_63: 515 priv->habit = UART_ERRATA_i202_MDR1_ACCESS | 516 OMAP_UART_WER_HAS_TX_WAKEUP; 517 break; 518 default: 519 break; 520 } 521 } 522 523 static void omap8250_uart_qos_work(struct work_struct *work) 524 { 525 struct omap8250_priv *priv; 526 527 priv = container_of(work, struct omap8250_priv, qos_work); 528 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 529 } 530 531 static irqreturn_t omap_wake_irq(int irq, void *dev_id) 532 { 533 struct uart_port *port = dev_id; 534 int ret; 535 536 ret = port->handle_irq(port); 537 if (ret) 538 return IRQ_HANDLED; 539 return IRQ_NONE; 540 } 541 542 static int omap_8250_startup(struct uart_port *port) 543 { 544 struct uart_8250_port *up = 545 container_of(port, struct uart_8250_port, port); 546 struct omap8250_priv *priv = port->private_data; 547 548 int ret; 549 550 if (priv->wakeirq) { 551 ret = request_irq(priv->wakeirq, omap_wake_irq, 552 port->irqflags, "uart wakeup irq", port); 553 if (ret) 554 return ret; 555 disable_irq(priv->wakeirq); 556 } 557 558 pm_runtime_get_sync(port->dev); 559 560 ret = serial8250_do_startup(port); 561 if (ret) 562 goto err; 563 564 #ifdef CONFIG_PM 565 up->capabilities |= UART_CAP_RPM; 566 #endif 567 568 /* Enable module level wake up */ 569 priv->wer = OMAP_UART_WER_MOD_WKUP; 570 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 571 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 572 serial_out(up, UART_OMAP_WER, priv->wer); 573 574 if (up->dma) 575 up->dma->rx_dma(up, 0); 576 577 pm_runtime_mark_last_busy(port->dev); 578 pm_runtime_put_autosuspend(port->dev); 579 return 0; 580 err: 581 pm_runtime_mark_last_busy(port->dev); 582 pm_runtime_put_autosuspend(port->dev); 583 if (priv->wakeirq) 584 free_irq(priv->wakeirq, port); 585 return ret; 586 } 587 588 static void omap_8250_shutdown(struct uart_port *port) 589 { 590 struct uart_8250_port *up = 591 container_of(port, struct uart_8250_port, port); 592 struct omap8250_priv *priv = port->private_data; 593 594 flush_work(&priv->qos_work); 595 if (up->dma) 596 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 597 598 pm_runtime_get_sync(port->dev); 599 600 serial_out(up, UART_OMAP_WER, 0); 601 serial8250_do_shutdown(port); 602 603 pm_runtime_mark_last_busy(port->dev); 604 pm_runtime_put_autosuspend(port->dev); 605 606 if (priv->wakeirq) 607 free_irq(priv->wakeirq, port); 608 } 609 610 static void omap_8250_throttle(struct uart_port *port) 611 { 612 unsigned long flags; 613 struct uart_8250_port *up = 614 container_of(port, struct uart_8250_port, port); 615 616 pm_runtime_get_sync(port->dev); 617 618 spin_lock_irqsave(&port->lock, flags); 619 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 620 serial_out(up, UART_IER, up->ier); 621 spin_unlock_irqrestore(&port->lock, flags); 622 623 pm_runtime_mark_last_busy(port->dev); 624 pm_runtime_put_autosuspend(port->dev); 625 } 626 627 static void omap_8250_unthrottle(struct uart_port *port) 628 { 629 unsigned long flags; 630 struct uart_8250_port *up = 631 container_of(port, struct uart_8250_port, port); 632 633 pm_runtime_get_sync(port->dev); 634 635 spin_lock_irqsave(&port->lock, flags); 636 up->ier |= UART_IER_RLSI | UART_IER_RDI; 637 serial_out(up, UART_IER, up->ier); 638 spin_unlock_irqrestore(&port->lock, flags); 639 640 pm_runtime_mark_last_busy(port->dev); 641 pm_runtime_put_autosuspend(port->dev); 642 } 643 644 #ifdef CONFIG_SERIAL_8250_DMA 645 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 646 647 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 648 { 649 struct uart_8250_dma *dma = p->dma; 650 struct tty_port *tty_port = &p->port.state->port; 651 struct dma_tx_state state; 652 int count; 653 654 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 655 dma->rx_size, DMA_FROM_DEVICE); 656 657 dma->rx_running = 0; 658 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 659 dmaengine_terminate_all(dma->rxchan); 660 661 count = dma->rx_size - state.residue; 662 663 tty_insert_flip_string(tty_port, dma->rx_buf, count); 664 p->port.icount.rx += count; 665 if (!error) 666 omap_8250_rx_dma(p, 0); 667 668 tty_flip_buffer_push(tty_port); 669 } 670 671 static void __dma_rx_complete(void *param) 672 { 673 __dma_rx_do_complete(param, false); 674 } 675 676 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 677 { 678 struct uart_8250_dma *dma = p->dma; 679 struct dma_async_tx_descriptor *desc; 680 681 switch (iir & 0x3f) { 682 case UART_IIR_RLSI: 683 /* 8250_core handles errors and break interrupts */ 684 if (dma->rx_running) { 685 dmaengine_pause(dma->rxchan); 686 __dma_rx_do_complete(p, true); 687 } 688 return -EIO; 689 case UART_IIR_RX_TIMEOUT: 690 /* 691 * If RCVR FIFO trigger level was not reached, complete the 692 * transfer and let 8250_core copy the remaining data. 693 */ 694 if (dma->rx_running) { 695 dmaengine_pause(dma->rxchan); 696 __dma_rx_do_complete(p, true); 697 } 698 return -ETIMEDOUT; 699 case UART_IIR_RDI: 700 /* 701 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 702 * a DMA transfer programmed but it didn't work. One reason is 703 * that we were too slow and there were too many bytes in the 704 * FIFO, the UART counted wrong and never kicked the DMA engine 705 * to do anything. That means once we receive RDI on OMAP then 706 * the DMA won't do anything soon so we have to cancel the DMA 707 * transfer and purge the FIFO manually. 708 */ 709 if (dma->rx_running) { 710 dmaengine_pause(dma->rxchan); 711 __dma_rx_do_complete(p, true); 712 } 713 return -ETIMEDOUT; 714 715 default: 716 break; 717 } 718 719 if (dma->rx_running) 720 return 0; 721 722 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 723 dma->rx_size, DMA_DEV_TO_MEM, 724 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 725 if (!desc) 726 return -EBUSY; 727 728 dma->rx_running = 1; 729 desc->callback = __dma_rx_complete; 730 desc->callback_param = p; 731 732 dma->rx_cookie = dmaengine_submit(desc); 733 734 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 735 dma->rx_size, DMA_FROM_DEVICE); 736 737 dma_async_issue_pending(dma->rxchan); 738 return 0; 739 } 740 741 static int omap_8250_tx_dma(struct uart_8250_port *p); 742 743 static void omap_8250_dma_tx_complete(void *param) 744 { 745 struct uart_8250_port *p = param; 746 struct uart_8250_dma *dma = p->dma; 747 struct circ_buf *xmit = &p->port.state->xmit; 748 unsigned long flags; 749 bool en_thri = false; 750 struct omap8250_priv *priv = p->port.private_data; 751 752 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 753 UART_XMIT_SIZE, DMA_TO_DEVICE); 754 755 spin_lock_irqsave(&p->port.lock, flags); 756 757 dma->tx_running = 0; 758 759 xmit->tail += dma->tx_size; 760 xmit->tail &= UART_XMIT_SIZE - 1; 761 p->port.icount.tx += dma->tx_size; 762 763 if (priv->delayed_restore) { 764 priv->delayed_restore = 0; 765 omap8250_restore_regs(p); 766 } 767 768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 769 uart_write_wakeup(&p->port); 770 771 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 772 int ret; 773 774 ret = omap_8250_tx_dma(p); 775 if (ret) 776 en_thri = true; 777 778 } else if (p->capabilities & UART_CAP_RPM) { 779 en_thri = true; 780 } 781 782 if (en_thri) { 783 dma->tx_err = 1; 784 p->ier |= UART_IER_THRI; 785 serial_port_out(&p->port, UART_IER, p->ier); 786 } 787 788 spin_unlock_irqrestore(&p->port.lock, flags); 789 } 790 791 static int omap_8250_tx_dma(struct uart_8250_port *p) 792 { 793 struct uart_8250_dma *dma = p->dma; 794 struct omap8250_priv *priv = p->port.private_data; 795 struct circ_buf *xmit = &p->port.state->xmit; 796 struct dma_async_tx_descriptor *desc; 797 unsigned int skip_byte = 0; 798 int ret; 799 800 if (dma->tx_running) 801 return 0; 802 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 803 804 /* 805 * Even if no data, we need to return an error for the two cases 806 * below so serial8250_tx_chars() is invoked and properly clears 807 * THRI and/or runtime suspend. 808 */ 809 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 810 ret = -EBUSY; 811 goto err; 812 } 813 if (p->ier & UART_IER_THRI) { 814 p->ier &= ~UART_IER_THRI; 815 serial_out(p, UART_IER, p->ier); 816 } 817 return 0; 818 } 819 820 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 821 if (priv->habit & OMAP_DMA_TX_KICK) { 822 u8 tx_lvl; 823 824 /* 825 * We need to put the first byte into the FIFO in order to start 826 * the DMA transfer. For transfers smaller than four bytes we 827 * don't bother doing DMA at all. It seem not matter if there 828 * are still bytes in the FIFO from the last transfer (in case 829 * we got here directly from omap_8250_dma_tx_complete()). Bytes 830 * leaving the FIFO seem not to trigger the DMA transfer. It is 831 * really the byte that we put into the FIFO. 832 * If the FIFO is already full then we most likely got here from 833 * omap_8250_dma_tx_complete(). And this means the DMA engine 834 * just completed its work. We don't have to wait the complete 835 * 86us at 115200,8n1 but around 60us (not to mention lower 836 * baudrates). So in that case we take the interrupt and try 837 * again with an empty FIFO. 838 */ 839 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 840 if (tx_lvl == p->tx_loadsz) { 841 ret = -EBUSY; 842 goto err; 843 } 844 if (dma->tx_size < 4) { 845 ret = -EINVAL; 846 goto err; 847 } 848 skip_byte = 1; 849 } 850 851 desc = dmaengine_prep_slave_single(dma->txchan, 852 dma->tx_addr + xmit->tail + skip_byte, 853 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 854 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 855 if (!desc) { 856 ret = -EBUSY; 857 goto err; 858 } 859 860 dma->tx_running = 1; 861 862 desc->callback = omap_8250_dma_tx_complete; 863 desc->callback_param = p; 864 865 dma->tx_cookie = dmaengine_submit(desc); 866 867 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 868 UART_XMIT_SIZE, DMA_TO_DEVICE); 869 870 dma_async_issue_pending(dma->txchan); 871 if (dma->tx_err) 872 dma->tx_err = 0; 873 874 if (p->ier & UART_IER_THRI) { 875 p->ier &= ~UART_IER_THRI; 876 serial_out(p, UART_IER, p->ier); 877 } 878 if (skip_byte) 879 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 880 return 0; 881 err: 882 dma->tx_err = 1; 883 return ret; 884 } 885 886 /* 887 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 888 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 889 * use the default routine in the non-DMA case and this one for with DMA. 890 */ 891 static int omap_8250_dma_handle_irq(struct uart_port *port) 892 { 893 struct uart_8250_port *up = up_to_u8250p(port); 894 unsigned char status; 895 unsigned long flags; 896 u8 iir; 897 int dma_err = 0; 898 899 serial8250_rpm_get(up); 900 901 iir = serial_port_in(port, UART_IIR); 902 if (iir & UART_IIR_NO_INT) { 903 serial8250_rpm_put(up); 904 return 0; 905 } 906 907 spin_lock_irqsave(&port->lock, flags); 908 909 status = serial_port_in(port, UART_LSR); 910 911 if (status & (UART_LSR_DR | UART_LSR_BI)) { 912 913 dma_err = omap_8250_rx_dma(up, iir); 914 if (dma_err) { 915 status = serial8250_rx_chars(up, status); 916 omap_8250_rx_dma(up, 0); 917 } 918 } 919 serial8250_modem_status(up); 920 if (status & UART_LSR_THRE && up->dma->tx_err) { 921 if (uart_tx_stopped(&up->port) || 922 uart_circ_empty(&up->port.state->xmit)) { 923 up->dma->tx_err = 0; 924 serial8250_tx_chars(up); 925 } else { 926 /* 927 * try again due to an earlier failer which 928 * might have been resolved by now. 929 */ 930 dma_err = omap_8250_tx_dma(up); 931 if (dma_err) 932 serial8250_tx_chars(up); 933 } 934 } 935 936 spin_unlock_irqrestore(&port->lock, flags); 937 serial8250_rpm_put(up); 938 return 1; 939 } 940 941 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 942 { 943 return false; 944 } 945 946 #else 947 948 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 949 { 950 return -EINVAL; 951 } 952 #endif 953 954 static int omap8250_probe(struct platform_device *pdev) 955 { 956 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 957 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 958 struct omap8250_priv *priv; 959 struct uart_8250_port up; 960 int ret; 961 void __iomem *membase; 962 963 if (!regs || !irq) { 964 dev_err(&pdev->dev, "missing registers or irq\n"); 965 return -EINVAL; 966 } 967 968 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 969 if (!priv) 970 return -ENOMEM; 971 972 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 973 resource_size(regs)); 974 if (!membase) 975 return -ENODEV; 976 977 memset(&up, 0, sizeof(up)); 978 up.port.dev = &pdev->dev; 979 up.port.mapbase = regs->start; 980 up.port.membase = membase; 981 up.port.irq = irq->start; 982 /* 983 * It claims to be 16C750 compatible however it is a little different. 984 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 985 * have) is enabled via EFR instead of MCR. The type is set here 8250 986 * just to get things going. UNKNOWN does not work for a few reasons and 987 * we don't need our own type since we don't use 8250's set_termios() 988 * or pm callback. 989 */ 990 up.port.type = PORT_8250; 991 up.port.iotype = UPIO_MEM; 992 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 993 UPF_HARD_FLOW; 994 up.port.private_data = priv; 995 996 up.port.regshift = 2; 997 up.port.fifosize = 64; 998 up.tx_loadsz = 64; 999 up.capabilities = UART_CAP_FIFO; 1000 #ifdef CONFIG_PM 1001 /* 1002 * Runtime PM is mostly transparent. However to do it right we need to a 1003 * TX empty interrupt before we can put the device to auto idle. So if 1004 * PM is not enabled we don't add that flag and can spare that one extra 1005 * interrupt in the TX path. 1006 */ 1007 up.capabilities |= UART_CAP_RPM; 1008 #endif 1009 up.port.set_termios = omap_8250_set_termios; 1010 up.port.pm = omap_8250_pm; 1011 up.port.startup = omap_8250_startup; 1012 up.port.shutdown = omap_8250_shutdown; 1013 up.port.throttle = omap_8250_throttle; 1014 up.port.unthrottle = omap_8250_unthrottle; 1015 1016 if (pdev->dev.of_node) { 1017 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1018 1019 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1020 &up.port.uartclk); 1021 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1022 } else { 1023 ret = pdev->id; 1024 } 1025 if (ret < 0) { 1026 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1027 return ret; 1028 } 1029 up.port.line = ret; 1030 1031 if (!up.port.uartclk) { 1032 up.port.uartclk = DEFAULT_CLK_SPEED; 1033 dev_warn(&pdev->dev, 1034 "No clock speed specified: using default: %d\n", 1035 DEFAULT_CLK_SPEED); 1036 } 1037 1038 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1039 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1040 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1041 priv->latency); 1042 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1043 1044 device_init_wakeup(&pdev->dev, true); 1045 pm_runtime_use_autosuspend(&pdev->dev); 1046 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1047 1048 pm_runtime_irq_safe(&pdev->dev); 1049 pm_runtime_enable(&pdev->dev); 1050 1051 pm_runtime_get_sync(&pdev->dev); 1052 1053 omap_serial_fill_features_erratas(&up, priv); 1054 #ifdef CONFIG_SERIAL_8250_DMA 1055 if (pdev->dev.of_node) { 1056 /* 1057 * Oh DMA support. If there are no DMA properties in the DT then 1058 * we will fall back to a generic DMA channel which does not 1059 * really work here. To ensure that we do not get a generic DMA 1060 * channel assigned, we have the the_no_dma_filter_fn() here. 1061 * To avoid "failed to request DMA" messages we check for DMA 1062 * properties in DT. 1063 */ 1064 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1065 if (ret == 2) { 1066 up.dma = &priv->omap8250_dma; 1067 up.port.handle_irq = omap_8250_dma_handle_irq; 1068 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1069 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1070 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1071 priv->omap8250_dma.rx_size = RX_TRIGGER; 1072 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1073 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1074 1075 if (of_machine_is_compatible("ti,am33xx")) 1076 priv->habit |= OMAP_DMA_TX_KICK; 1077 } 1078 } 1079 #endif 1080 ret = serial8250_register_8250_port(&up); 1081 if (ret < 0) { 1082 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1083 goto err; 1084 } 1085 priv->line = ret; 1086 platform_set_drvdata(pdev, priv); 1087 pm_runtime_mark_last_busy(&pdev->dev); 1088 pm_runtime_put_autosuspend(&pdev->dev); 1089 return 0; 1090 err: 1091 pm_runtime_put(&pdev->dev); 1092 pm_runtime_disable(&pdev->dev); 1093 return ret; 1094 } 1095 1096 static int omap8250_remove(struct platform_device *pdev) 1097 { 1098 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1099 1100 pm_runtime_put_sync(&pdev->dev); 1101 pm_runtime_disable(&pdev->dev); 1102 serial8250_unregister_port(priv->line); 1103 pm_qos_remove_request(&priv->pm_qos_request); 1104 device_init_wakeup(&pdev->dev, false); 1105 return 0; 1106 } 1107 1108 #ifdef CONFIG_PM 1109 1110 static inline void omap8250_enable_wakeirq(struct omap8250_priv *priv, 1111 bool enable) 1112 { 1113 if (!priv->wakeirq) 1114 return; 1115 1116 if (enable) 1117 enable_irq(priv->wakeirq); 1118 else 1119 disable_irq_nosync(priv->wakeirq); 1120 } 1121 1122 static void omap8250_enable_wakeup(struct omap8250_priv *priv, 1123 bool enable) 1124 { 1125 if (enable == priv->wakeups_enabled) 1126 return; 1127 1128 omap8250_enable_wakeirq(priv, enable); 1129 priv->wakeups_enabled = enable; 1130 } 1131 #endif 1132 1133 #ifdef CONFIG_PM_SLEEP 1134 static int omap8250_prepare(struct device *dev) 1135 { 1136 struct omap8250_priv *priv = dev_get_drvdata(dev); 1137 1138 if (!priv) 1139 return 0; 1140 priv->is_suspending = true; 1141 return 0; 1142 } 1143 1144 static void omap8250_complete(struct device *dev) 1145 { 1146 struct omap8250_priv *priv = dev_get_drvdata(dev); 1147 1148 if (!priv) 1149 return; 1150 priv->is_suspending = false; 1151 } 1152 1153 static int omap8250_suspend(struct device *dev) 1154 { 1155 struct omap8250_priv *priv = dev_get_drvdata(dev); 1156 1157 serial8250_suspend_port(priv->line); 1158 flush_work(&priv->qos_work); 1159 1160 if (device_may_wakeup(dev)) 1161 omap8250_enable_wakeup(priv, true); 1162 else 1163 omap8250_enable_wakeup(priv, false); 1164 return 0; 1165 } 1166 1167 static int omap8250_resume(struct device *dev) 1168 { 1169 struct omap8250_priv *priv = dev_get_drvdata(dev); 1170 1171 if (device_may_wakeup(dev)) 1172 omap8250_enable_wakeup(priv, false); 1173 1174 serial8250_resume_port(priv->line); 1175 return 0; 1176 } 1177 #else 1178 #define omap8250_prepare NULL 1179 #define omap8250_complete NULL 1180 #endif 1181 1182 #ifdef CONFIG_PM 1183 static int omap8250_lost_context(struct uart_8250_port *up) 1184 { 1185 u32 val; 1186 1187 val = serial_in(up, UART_OMAP_MDR1); 1188 /* 1189 * If we lose context, then MDR1 is set to its reset value which is 1190 * UART_OMAP_MDR1_DISABLE. After set_termios() we set it either to 13x 1191 * or 16x but never to disable again. 1192 */ 1193 if (val == UART_OMAP_MDR1_DISABLE) 1194 return 1; 1195 return 0; 1196 } 1197 1198 static int omap8250_runtime_suspend(struct device *dev) 1199 { 1200 struct omap8250_priv *priv = dev_get_drvdata(dev); 1201 struct uart_8250_port *up; 1202 1203 up = serial8250_get_port(priv->line); 1204 /* 1205 * When using 'no_console_suspend', the console UART must not be 1206 * suspended. Since driver suspend is managed by runtime suspend, 1207 * preventing runtime suspend (by returning error) will keep device 1208 * active during suspend. 1209 */ 1210 if (priv->is_suspending && !console_suspend_enabled) { 1211 if (uart_console(&up->port)) 1212 return -EBUSY; 1213 } 1214 1215 omap8250_enable_wakeup(priv, true); 1216 if (up->dma) 1217 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1218 1219 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1220 schedule_work(&priv->qos_work); 1221 1222 return 0; 1223 } 1224 1225 static int omap8250_runtime_resume(struct device *dev) 1226 { 1227 struct omap8250_priv *priv = dev_get_drvdata(dev); 1228 struct uart_8250_port *up; 1229 int loss_cntx; 1230 1231 /* In case runtime-pm tries this before we are setup */ 1232 if (!priv) 1233 return 0; 1234 1235 up = serial8250_get_port(priv->line); 1236 omap8250_enable_wakeup(priv, false); 1237 loss_cntx = omap8250_lost_context(up); 1238 1239 if (loss_cntx) 1240 omap8250_restore_regs(up); 1241 1242 if (up->dma) 1243 omap_8250_rx_dma(up, 0); 1244 1245 priv->latency = priv->calc_latency; 1246 schedule_work(&priv->qos_work); 1247 return 0; 1248 } 1249 #endif 1250 1251 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1252 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1253 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1254 omap8250_runtime_resume, NULL) 1255 .prepare = omap8250_prepare, 1256 .complete = omap8250_complete, 1257 }; 1258 1259 static const struct of_device_id omap8250_dt_ids[] = { 1260 { .compatible = "ti,omap2-uart" }, 1261 { .compatible = "ti,omap3-uart" }, 1262 { .compatible = "ti,omap4-uart" }, 1263 {}, 1264 }; 1265 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1266 1267 static struct platform_driver omap8250_platform_driver = { 1268 .driver = { 1269 .name = "omap8250", 1270 .pm = &omap8250_dev_pm_ops, 1271 .of_match_table = omap8250_dt_ids, 1272 .owner = THIS_MODULE, 1273 }, 1274 .probe = omap8250_probe, 1275 .remove = omap8250_remove, 1276 }; 1277 module_platform_driver(omap8250_platform_driver); 1278 1279 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1280 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1281 MODULE_LICENSE("GPL v2"); 1282