1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_reg.h> 15 #include <linux/tty_flip.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/delay.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/console.h> 25 #include <linux/pm_qos.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/dma-mapping.h> 28 29 #include "8250.h" 30 31 #define DEFAULT_CLK_SPEED 48000000 32 33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 35 #define OMAP_DMA_TX_KICK (1 << 2) 36 /* 37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 38 * The same errata is applicable to AM335x and DRA7x processors too. 39 */ 40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 41 42 #define OMAP_UART_FCR_RX_TRIG 6 43 #define OMAP_UART_FCR_TX_TRIG 4 44 45 /* SCR register bitmasks */ 46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 52 53 /* MVR register bitmasks */ 54 #define OMAP_UART_MVR_SCHEME_SHIFT 30 55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 58 #define OMAP_UART_MVR_MAJ_MASK 0x700 59 #define OMAP_UART_MVR_MAJ_SHIFT 8 60 #define OMAP_UART_MVR_MIN_MASK 0x3f 61 62 /* SYSC register bitmasks */ 63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 64 65 /* SYSS register bitmasks */ 66 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 67 68 #define UART_TI752_TLR_TX 0 69 #define UART_TI752_TLR_RX 4 70 71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 72 #define TRIGGER_FCR_MASK(x) (x & 3) 73 74 /* Enable XON/XOFF flow control on output */ 75 #define OMAP_UART_SW_TX 0x08 76 /* Enable XON/XOFF flow control on input */ 77 #define OMAP_UART_SW_RX 0x02 78 79 #define OMAP_UART_WER_MOD_WKUP 0x7f 80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 81 82 #define TX_TRIGGER 1 83 #define RX_TRIGGER 48 84 85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 87 88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 89 90 #define OMAP_UART_REV_46 0x0406 91 #define OMAP_UART_REV_52 0x0502 92 #define OMAP_UART_REV_63 0x0603 93 94 struct omap8250_priv { 95 int line; 96 u8 habit; 97 u8 mdr1; 98 u8 efr; 99 u8 scr; 100 u8 wer; 101 u8 xon; 102 u8 xoff; 103 u8 delayed_restore; 104 u16 quot; 105 106 bool is_suspending; 107 int wakeirq; 108 int wakeups_enabled; 109 u32 latency; 110 u32 calc_latency; 111 struct pm_qos_request pm_qos_request; 112 struct work_struct qos_work; 113 struct uart_8250_dma omap8250_dma; 114 spinlock_t rx_dma_lock; 115 bool rx_dma_broken; 116 }; 117 118 static u32 uart_read(struct uart_8250_port *up, u32 reg) 119 { 120 return readl(up->port.membase + (reg << up->port.regshift)); 121 } 122 123 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 124 { 125 struct uart_8250_port *up = up_to_u8250p(port); 126 struct omap8250_priv *priv = up->port.private_data; 127 u8 lcr; 128 129 serial8250_do_set_mctrl(port, mctrl); 130 131 /* 132 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 133 * if RTS is raised 134 */ 135 lcr = serial_in(up, UART_LCR); 136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 137 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 138 priv->efr |= UART_EFR_RTS; 139 else 140 priv->efr &= ~UART_EFR_RTS; 141 serial_out(up, UART_EFR, priv->efr); 142 serial_out(up, UART_LCR, lcr); 143 } 144 145 /* 146 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 147 * The access to uart register after MDR1 Access 148 * causes UART to corrupt data. 149 * 150 * Need a delay = 151 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 152 * give 10 times as much 153 */ 154 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 155 struct omap8250_priv *priv) 156 { 157 u8 timeout = 255; 158 u8 old_mdr1; 159 160 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 161 if (old_mdr1 == priv->mdr1) 162 return; 163 164 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 165 udelay(2); 166 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 167 UART_FCR_CLEAR_RCVR); 168 /* 169 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 170 * TX_FIFO_E bit is 1. 171 */ 172 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 173 (UART_LSR_THRE | UART_LSR_DR))) { 174 timeout--; 175 if (!timeout) { 176 /* Should *never* happen. we warn and carry on */ 177 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 178 serial_in(up, UART_LSR)); 179 break; 180 } 181 udelay(1); 182 } 183 } 184 185 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 186 struct omap8250_priv *priv) 187 { 188 unsigned int uartclk = port->uartclk; 189 unsigned int div_13, div_16; 190 unsigned int abs_d13, abs_d16; 191 192 /* 193 * Old custom speed handling. 194 */ 195 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 196 priv->quot = port->custom_divisor & 0xffff; 197 /* 198 * I assume that nobody is using this. But hey, if somebody 199 * would like to specify the divisor _and_ the mode then the 200 * driver is ready and waiting for it. 201 */ 202 if (port->custom_divisor & (1 << 16)) 203 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 204 else 205 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 206 return; 207 } 208 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 209 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 210 211 if (!div_13) 212 div_13 = 1; 213 if (!div_16) 214 div_16 = 1; 215 216 abs_d13 = abs(baud - uartclk / 13 / div_13); 217 abs_d16 = abs(baud - uartclk / 16 / div_16); 218 219 if (abs_d13 >= abs_d16) { 220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 221 priv->quot = div_16; 222 } else { 223 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 224 priv->quot = div_13; 225 } 226 } 227 228 static void omap8250_update_scr(struct uart_8250_port *up, 229 struct omap8250_priv *priv) 230 { 231 u8 old_scr; 232 233 old_scr = serial_in(up, UART_OMAP_SCR); 234 if (old_scr == priv->scr) 235 return; 236 237 /* 238 * The manual recommends not to enable the DMA mode selector in the SCR 239 * (instead of the FCR) register _and_ selecting the DMA mode as one 240 * register write because this may lead to malfunction. 241 */ 242 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 243 serial_out(up, UART_OMAP_SCR, 244 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 245 serial_out(up, UART_OMAP_SCR, priv->scr); 246 } 247 248 static void omap8250_update_mdr1(struct uart_8250_port *up, 249 struct omap8250_priv *priv) 250 { 251 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 252 omap_8250_mdr1_errataset(up, priv); 253 else 254 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 255 } 256 257 static void omap8250_restore_regs(struct uart_8250_port *up) 258 { 259 struct omap8250_priv *priv = up->port.private_data; 260 struct uart_8250_dma *dma = up->dma; 261 262 if (dma && dma->tx_running) { 263 /* 264 * TCSANOW requests the change to occur immediately however if 265 * we have a TX-DMA operation in progress then it has been 266 * observed that it might stall and never complete. Therefore we 267 * delay DMA completes to prevent this hang from happen. 268 */ 269 priv->delayed_restore = 1; 270 return; 271 } 272 273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 274 serial_out(up, UART_EFR, UART_EFR_ECB); 275 276 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 277 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 278 serial_out(up, UART_FCR, up->fcr); 279 280 omap8250_update_scr(up, priv); 281 282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 283 284 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 285 OMAP_UART_TCR_HALT(52)); 286 serial_out(up, UART_TI752_TLR, 287 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 288 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 289 290 serial_out(up, UART_LCR, 0); 291 292 /* drop TCR + TLR access, we setup XON/XOFF later */ 293 serial_out(up, UART_MCR, up->mcr); 294 serial_out(up, UART_IER, up->ier); 295 296 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 297 serial_dl_write(up, priv->quot); 298 299 serial_out(up, UART_EFR, priv->efr); 300 301 /* Configure flow control */ 302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 303 serial_out(up, UART_XON1, priv->xon); 304 serial_out(up, UART_XOFF1, priv->xoff); 305 306 serial_out(up, UART_LCR, up->lcr); 307 308 omap8250_update_mdr1(up, priv); 309 310 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 311 } 312 313 /* 314 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 315 * some differences in how we want to handle flow control. 316 */ 317 static void omap_8250_set_termios(struct uart_port *port, 318 struct ktermios *termios, 319 struct ktermios *old) 320 { 321 struct uart_8250_port *up = 322 container_of(port, struct uart_8250_port, port); 323 struct omap8250_priv *priv = up->port.private_data; 324 unsigned char cval = 0; 325 unsigned int baud; 326 327 switch (termios->c_cflag & CSIZE) { 328 case CS5: 329 cval = UART_LCR_WLEN5; 330 break; 331 case CS6: 332 cval = UART_LCR_WLEN6; 333 break; 334 case CS7: 335 cval = UART_LCR_WLEN7; 336 break; 337 default: 338 case CS8: 339 cval = UART_LCR_WLEN8; 340 break; 341 } 342 343 if (termios->c_cflag & CSTOPB) 344 cval |= UART_LCR_STOP; 345 if (termios->c_cflag & PARENB) 346 cval |= UART_LCR_PARITY; 347 if (!(termios->c_cflag & PARODD)) 348 cval |= UART_LCR_EPAR; 349 if (termios->c_cflag & CMSPAR) 350 cval |= UART_LCR_SPAR; 351 352 /* 353 * Ask the core to calculate the divisor for us. 354 */ 355 baud = uart_get_baud_rate(port, termios, old, 356 port->uartclk / 16 / 0xffff, 357 port->uartclk / 13); 358 omap_8250_get_divisor(port, baud, priv); 359 360 /* 361 * Ok, we're now changing the port state. Do it with 362 * interrupts disabled. 363 */ 364 pm_runtime_get_sync(port->dev); 365 spin_lock_irq(&port->lock); 366 367 /* 368 * Update the per-port timeout. 369 */ 370 uart_update_timeout(port, termios->c_cflag, baud); 371 372 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 373 if (termios->c_iflag & INPCK) 374 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 375 if (termios->c_iflag & (IGNBRK | PARMRK)) 376 up->port.read_status_mask |= UART_LSR_BI; 377 378 /* 379 * Characters to ignore 380 */ 381 up->port.ignore_status_mask = 0; 382 if (termios->c_iflag & IGNPAR) 383 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 384 if (termios->c_iflag & IGNBRK) { 385 up->port.ignore_status_mask |= UART_LSR_BI; 386 /* 387 * If we're ignoring parity and break indicators, 388 * ignore overruns too (for real raw support). 389 */ 390 if (termios->c_iflag & IGNPAR) 391 up->port.ignore_status_mask |= UART_LSR_OE; 392 } 393 394 /* 395 * ignore all characters if CREAD is not set 396 */ 397 if ((termios->c_cflag & CREAD) == 0) 398 up->port.ignore_status_mask |= UART_LSR_DR; 399 400 /* 401 * Modem status interrupts 402 */ 403 up->ier &= ~UART_IER_MSI; 404 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 405 up->ier |= UART_IER_MSI; 406 407 up->lcr = cval; 408 /* Up to here it was mostly serial8250_do_set_termios() */ 409 410 /* 411 * We enable TRIG_GRANU for RX and TX and additionaly we set 412 * SCR_TX_EMPTY bit. The result is the following: 413 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 414 * - less than RX_TRIGGER number of bytes will also cause an interrupt 415 * once the UART decides that there no new bytes arriving. 416 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 417 * empty - the trigger level is ignored here. 418 * 419 * Once DMA is enabled: 420 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 421 * bytes in the TX FIFO. On each assert the DMA engine will move 422 * TX_TRIGGER bytes into the FIFO. 423 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 424 * the FIFO and move RX_TRIGGER bytes. 425 * This is because threshold and trigger values are the same. 426 */ 427 up->fcr = UART_FCR_ENABLE_FIFO; 428 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 429 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 430 431 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 432 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 433 434 if (up->dma) 435 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 436 OMAP_UART_SCR_DMAMODE_CTL; 437 438 priv->xon = termios->c_cc[VSTART]; 439 priv->xoff = termios->c_cc[VSTOP]; 440 441 priv->efr = 0; 442 up->mcr &= ~(UART_MCR_RTS | UART_MCR_XONANY); 443 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 444 445 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 446 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 447 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 448 priv->efr |= UART_EFR_CTS; 449 } else if (up->port.flags & UPF_SOFT_FLOW) { 450 /* 451 * OMAP rx s/w flow control is borked; the transmitter remains 452 * stuck off even if rx flow control is subsequently disabled 453 */ 454 455 /* 456 * IXOFF Flag: 457 * Enable XON/XOFF flow control on output. 458 * Transmit XON1, XOFF1 459 */ 460 if (termios->c_iflag & IXOFF) { 461 up->port.status |= UPSTAT_AUTOXOFF; 462 priv->efr |= OMAP_UART_SW_TX; 463 } 464 } 465 omap8250_restore_regs(up); 466 467 spin_unlock_irq(&up->port.lock); 468 pm_runtime_mark_last_busy(port->dev); 469 pm_runtime_put_autosuspend(port->dev); 470 471 /* calculate wakeup latency constraint */ 472 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 473 priv->latency = priv->calc_latency; 474 475 schedule_work(&priv->qos_work); 476 477 /* Don't rewrite B0 */ 478 if (tty_termios_baud_rate(termios)) 479 tty_termios_encode_baud_rate(termios, baud, baud); 480 } 481 482 /* same as 8250 except that we may have extra flow bits set in EFR */ 483 static void omap_8250_pm(struct uart_port *port, unsigned int state, 484 unsigned int oldstate) 485 { 486 struct uart_8250_port *up = up_to_u8250p(port); 487 u8 efr; 488 489 pm_runtime_get_sync(port->dev); 490 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 491 efr = serial_in(up, UART_EFR); 492 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 493 serial_out(up, UART_LCR, 0); 494 495 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 496 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 497 serial_out(up, UART_EFR, efr); 498 serial_out(up, UART_LCR, 0); 499 500 pm_runtime_mark_last_busy(port->dev); 501 pm_runtime_put_autosuspend(port->dev); 502 } 503 504 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 505 struct omap8250_priv *priv) 506 { 507 u32 mvr, scheme; 508 u16 revision, major, minor; 509 510 mvr = uart_read(up, UART_OMAP_MVER); 511 512 /* Check revision register scheme */ 513 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 514 515 switch (scheme) { 516 case 0: /* Legacy Scheme: OMAP2/3 */ 517 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 518 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 519 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 520 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 521 break; 522 case 1: 523 /* New Scheme: OMAP4+ */ 524 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 525 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 526 OMAP_UART_MVR_MAJ_SHIFT; 527 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 528 break; 529 default: 530 dev_warn(up->port.dev, 531 "Unknown revision, defaulting to highest\n"); 532 /* highest possible revision */ 533 major = 0xff; 534 minor = 0xff; 535 } 536 /* normalize revision for the driver */ 537 revision = UART_BUILD_REVISION(major, minor); 538 539 switch (revision) { 540 case OMAP_UART_REV_46: 541 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 542 break; 543 case OMAP_UART_REV_52: 544 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 545 OMAP_UART_WER_HAS_TX_WAKEUP; 546 break; 547 case OMAP_UART_REV_63: 548 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 549 OMAP_UART_WER_HAS_TX_WAKEUP; 550 break; 551 default: 552 break; 553 } 554 } 555 556 static void omap8250_uart_qos_work(struct work_struct *work) 557 { 558 struct omap8250_priv *priv; 559 560 priv = container_of(work, struct omap8250_priv, qos_work); 561 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 562 } 563 564 #ifdef CONFIG_SERIAL_8250_DMA 565 static int omap_8250_dma_handle_irq(struct uart_port *port); 566 #endif 567 568 static irqreturn_t omap8250_irq(int irq, void *dev_id) 569 { 570 struct uart_port *port = dev_id; 571 struct uart_8250_port *up = up_to_u8250p(port); 572 unsigned int iir; 573 int ret; 574 575 #ifdef CONFIG_SERIAL_8250_DMA 576 if (up->dma) { 577 ret = omap_8250_dma_handle_irq(port); 578 return IRQ_RETVAL(ret); 579 } 580 #endif 581 582 serial8250_rpm_get(up); 583 iir = serial_port_in(port, UART_IIR); 584 ret = serial8250_handle_irq(port, iir); 585 serial8250_rpm_put(up); 586 587 return IRQ_RETVAL(ret); 588 } 589 590 static int omap_8250_startup(struct uart_port *port) 591 { 592 struct uart_8250_port *up = up_to_u8250p(port); 593 struct omap8250_priv *priv = port->private_data; 594 int ret; 595 596 if (priv->wakeirq) { 597 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 598 if (ret) 599 return ret; 600 } 601 602 pm_runtime_get_sync(port->dev); 603 604 up->mcr = 0; 605 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 606 607 serial_out(up, UART_LCR, UART_LCR_WLEN8); 608 609 up->lsr_saved_flags = 0; 610 up->msr_saved_flags = 0; 611 612 if (up->dma) { 613 ret = serial8250_request_dma(up); 614 if (ret) { 615 dev_warn_ratelimited(port->dev, 616 "failed to request DMA\n"); 617 up->dma = NULL; 618 } 619 } 620 621 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 622 dev_name(port->dev), port); 623 if (ret < 0) 624 goto err; 625 626 up->ier = UART_IER_RLSI | UART_IER_RDI; 627 serial_out(up, UART_IER, up->ier); 628 629 #ifdef CONFIG_PM 630 up->capabilities |= UART_CAP_RPM; 631 #endif 632 633 /* Enable module level wake up */ 634 priv->wer = OMAP_UART_WER_MOD_WKUP; 635 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 636 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 637 serial_out(up, UART_OMAP_WER, priv->wer); 638 639 if (up->dma) 640 up->dma->rx_dma(up, 0); 641 642 pm_runtime_mark_last_busy(port->dev); 643 pm_runtime_put_autosuspend(port->dev); 644 return 0; 645 err: 646 pm_runtime_mark_last_busy(port->dev); 647 pm_runtime_put_autosuspend(port->dev); 648 dev_pm_clear_wake_irq(port->dev); 649 return ret; 650 } 651 652 static void omap_8250_shutdown(struct uart_port *port) 653 { 654 struct uart_8250_port *up = up_to_u8250p(port); 655 struct omap8250_priv *priv = port->private_data; 656 657 flush_work(&priv->qos_work); 658 if (up->dma) 659 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 660 661 pm_runtime_get_sync(port->dev); 662 663 serial_out(up, UART_OMAP_WER, 0); 664 665 up->ier = 0; 666 serial_out(up, UART_IER, 0); 667 668 if (up->dma) 669 serial8250_release_dma(up); 670 671 /* 672 * Disable break condition and FIFOs 673 */ 674 if (up->lcr & UART_LCR_SBC) 675 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 676 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 677 678 pm_runtime_mark_last_busy(port->dev); 679 pm_runtime_put_autosuspend(port->dev); 680 free_irq(port->irq, port); 681 dev_pm_clear_wake_irq(port->dev); 682 } 683 684 static void omap_8250_throttle(struct uart_port *port) 685 { 686 unsigned long flags; 687 struct uart_8250_port *up = 688 container_of(port, struct uart_8250_port, port); 689 690 pm_runtime_get_sync(port->dev); 691 692 spin_lock_irqsave(&port->lock, flags); 693 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 694 serial_out(up, UART_IER, up->ier); 695 spin_unlock_irqrestore(&port->lock, flags); 696 697 pm_runtime_mark_last_busy(port->dev); 698 pm_runtime_put_autosuspend(port->dev); 699 } 700 701 static void omap_8250_unthrottle(struct uart_port *port) 702 { 703 unsigned long flags; 704 struct uart_8250_port *up = 705 container_of(port, struct uart_8250_port, port); 706 707 pm_runtime_get_sync(port->dev); 708 709 spin_lock_irqsave(&port->lock, flags); 710 up->ier |= UART_IER_RLSI | UART_IER_RDI; 711 serial_out(up, UART_IER, up->ier); 712 spin_unlock_irqrestore(&port->lock, flags); 713 714 pm_runtime_mark_last_busy(port->dev); 715 pm_runtime_put_autosuspend(port->dev); 716 } 717 718 #ifdef CONFIG_SERIAL_8250_DMA 719 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 720 721 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 722 { 723 struct omap8250_priv *priv = p->port.private_data; 724 struct uart_8250_dma *dma = p->dma; 725 struct tty_port *tty_port = &p->port.state->port; 726 struct dma_tx_state state; 727 int count; 728 unsigned long flags; 729 730 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 731 dma->rx_size, DMA_FROM_DEVICE); 732 733 spin_lock_irqsave(&priv->rx_dma_lock, flags); 734 735 if (!dma->rx_running) 736 goto unlock; 737 738 dma->rx_running = 0; 739 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 740 dmaengine_terminate_all(dma->rxchan); 741 742 count = dma->rx_size - state.residue; 743 744 tty_insert_flip_string(tty_port, dma->rx_buf, count); 745 p->port.icount.rx += count; 746 unlock: 747 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 748 749 if (!error) 750 omap_8250_rx_dma(p, 0); 751 752 tty_flip_buffer_push(tty_port); 753 } 754 755 static void __dma_rx_complete(void *param) 756 { 757 __dma_rx_do_complete(param, false); 758 } 759 760 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 761 { 762 struct omap8250_priv *priv = p->port.private_data; 763 struct uart_8250_dma *dma = p->dma; 764 unsigned long flags; 765 int ret; 766 767 spin_lock_irqsave(&priv->rx_dma_lock, flags); 768 769 if (!dma->rx_running) { 770 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 771 return; 772 } 773 774 ret = dmaengine_pause(dma->rxchan); 775 if (WARN_ON_ONCE(ret)) 776 priv->rx_dma_broken = true; 777 778 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 779 780 __dma_rx_do_complete(p, true); 781 } 782 783 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 784 { 785 struct omap8250_priv *priv = p->port.private_data; 786 struct uart_8250_dma *dma = p->dma; 787 int err = 0; 788 struct dma_async_tx_descriptor *desc; 789 unsigned long flags; 790 791 switch (iir & 0x3f) { 792 case UART_IIR_RLSI: 793 /* 8250_core handles errors and break interrupts */ 794 omap_8250_rx_dma_flush(p); 795 return -EIO; 796 case UART_IIR_RX_TIMEOUT: 797 /* 798 * If RCVR FIFO trigger level was not reached, complete the 799 * transfer and let 8250_core copy the remaining data. 800 */ 801 omap_8250_rx_dma_flush(p); 802 return -ETIMEDOUT; 803 case UART_IIR_RDI: 804 /* 805 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 806 * a DMA transfer programmed but it didn't work. One reason is 807 * that we were too slow and there were too many bytes in the 808 * FIFO, the UART counted wrong and never kicked the DMA engine 809 * to do anything. That means once we receive RDI on OMAP then 810 * the DMA won't do anything soon so we have to cancel the DMA 811 * transfer and purge the FIFO manually. 812 */ 813 omap_8250_rx_dma_flush(p); 814 return -ETIMEDOUT; 815 816 default: 817 break; 818 } 819 820 if (priv->rx_dma_broken) 821 return -EINVAL; 822 823 spin_lock_irqsave(&priv->rx_dma_lock, flags); 824 825 if (dma->rx_running) 826 goto out; 827 828 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 829 dma->rx_size, DMA_DEV_TO_MEM, 830 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 831 if (!desc) { 832 err = -EBUSY; 833 goto out; 834 } 835 836 dma->rx_running = 1; 837 desc->callback = __dma_rx_complete; 838 desc->callback_param = p; 839 840 dma->rx_cookie = dmaengine_submit(desc); 841 842 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 843 dma->rx_size, DMA_FROM_DEVICE); 844 845 dma_async_issue_pending(dma->rxchan); 846 out: 847 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 848 return err; 849 } 850 851 static int omap_8250_tx_dma(struct uart_8250_port *p); 852 853 static void omap_8250_dma_tx_complete(void *param) 854 { 855 struct uart_8250_port *p = param; 856 struct uart_8250_dma *dma = p->dma; 857 struct circ_buf *xmit = &p->port.state->xmit; 858 unsigned long flags; 859 bool en_thri = false; 860 struct omap8250_priv *priv = p->port.private_data; 861 862 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 863 UART_XMIT_SIZE, DMA_TO_DEVICE); 864 865 spin_lock_irqsave(&p->port.lock, flags); 866 867 dma->tx_running = 0; 868 869 xmit->tail += dma->tx_size; 870 xmit->tail &= UART_XMIT_SIZE - 1; 871 p->port.icount.tx += dma->tx_size; 872 873 if (priv->delayed_restore) { 874 priv->delayed_restore = 0; 875 omap8250_restore_regs(p); 876 } 877 878 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 879 uart_write_wakeup(&p->port); 880 881 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 882 int ret; 883 884 ret = omap_8250_tx_dma(p); 885 if (ret) 886 en_thri = true; 887 888 } else if (p->capabilities & UART_CAP_RPM) { 889 en_thri = true; 890 } 891 892 if (en_thri) { 893 dma->tx_err = 1; 894 p->ier |= UART_IER_THRI; 895 serial_port_out(&p->port, UART_IER, p->ier); 896 } 897 898 spin_unlock_irqrestore(&p->port.lock, flags); 899 } 900 901 static int omap_8250_tx_dma(struct uart_8250_port *p) 902 { 903 struct uart_8250_dma *dma = p->dma; 904 struct omap8250_priv *priv = p->port.private_data; 905 struct circ_buf *xmit = &p->port.state->xmit; 906 struct dma_async_tx_descriptor *desc; 907 unsigned int skip_byte = 0; 908 int ret; 909 910 if (dma->tx_running) 911 return 0; 912 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 913 914 /* 915 * Even if no data, we need to return an error for the two cases 916 * below so serial8250_tx_chars() is invoked and properly clears 917 * THRI and/or runtime suspend. 918 */ 919 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 920 ret = -EBUSY; 921 goto err; 922 } 923 if (p->ier & UART_IER_THRI) { 924 p->ier &= ~UART_IER_THRI; 925 serial_out(p, UART_IER, p->ier); 926 } 927 return 0; 928 } 929 930 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 931 if (priv->habit & OMAP_DMA_TX_KICK) { 932 u8 tx_lvl; 933 934 /* 935 * We need to put the first byte into the FIFO in order to start 936 * the DMA transfer. For transfers smaller than four bytes we 937 * don't bother doing DMA at all. It seem not matter if there 938 * are still bytes in the FIFO from the last transfer (in case 939 * we got here directly from omap_8250_dma_tx_complete()). Bytes 940 * leaving the FIFO seem not to trigger the DMA transfer. It is 941 * really the byte that we put into the FIFO. 942 * If the FIFO is already full then we most likely got here from 943 * omap_8250_dma_tx_complete(). And this means the DMA engine 944 * just completed its work. We don't have to wait the complete 945 * 86us at 115200,8n1 but around 60us (not to mention lower 946 * baudrates). So in that case we take the interrupt and try 947 * again with an empty FIFO. 948 */ 949 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 950 if (tx_lvl == p->tx_loadsz) { 951 ret = -EBUSY; 952 goto err; 953 } 954 if (dma->tx_size < 4) { 955 ret = -EINVAL; 956 goto err; 957 } 958 skip_byte = 1; 959 } 960 961 desc = dmaengine_prep_slave_single(dma->txchan, 962 dma->tx_addr + xmit->tail + skip_byte, 963 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 964 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 965 if (!desc) { 966 ret = -EBUSY; 967 goto err; 968 } 969 970 dma->tx_running = 1; 971 972 desc->callback = omap_8250_dma_tx_complete; 973 desc->callback_param = p; 974 975 dma->tx_cookie = dmaengine_submit(desc); 976 977 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 978 UART_XMIT_SIZE, DMA_TO_DEVICE); 979 980 dma_async_issue_pending(dma->txchan); 981 if (dma->tx_err) 982 dma->tx_err = 0; 983 984 if (p->ier & UART_IER_THRI) { 985 p->ier &= ~UART_IER_THRI; 986 serial_out(p, UART_IER, p->ier); 987 } 988 if (skip_byte) 989 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 990 return 0; 991 err: 992 dma->tx_err = 1; 993 return ret; 994 } 995 996 /* 997 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 998 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 999 * use the default routine in the non-DMA case and this one for with DMA. 1000 */ 1001 static int omap_8250_dma_handle_irq(struct uart_port *port) 1002 { 1003 struct uart_8250_port *up = up_to_u8250p(port); 1004 unsigned char status; 1005 unsigned long flags; 1006 u8 iir; 1007 int dma_err = 0; 1008 1009 serial8250_rpm_get(up); 1010 1011 iir = serial_port_in(port, UART_IIR); 1012 if (iir & UART_IIR_NO_INT) { 1013 serial8250_rpm_put(up); 1014 return 0; 1015 } 1016 1017 spin_lock_irqsave(&port->lock, flags); 1018 1019 status = serial_port_in(port, UART_LSR); 1020 1021 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1022 1023 dma_err = omap_8250_rx_dma(up, iir); 1024 if (dma_err) { 1025 status = serial8250_rx_chars(up, status); 1026 omap_8250_rx_dma(up, 0); 1027 } 1028 } 1029 serial8250_modem_status(up); 1030 if (status & UART_LSR_THRE && up->dma->tx_err) { 1031 if (uart_tx_stopped(&up->port) || 1032 uart_circ_empty(&up->port.state->xmit)) { 1033 up->dma->tx_err = 0; 1034 serial8250_tx_chars(up); 1035 } else { 1036 /* 1037 * try again due to an earlier failer which 1038 * might have been resolved by now. 1039 */ 1040 dma_err = omap_8250_tx_dma(up); 1041 if (dma_err) 1042 serial8250_tx_chars(up); 1043 } 1044 } 1045 1046 spin_unlock_irqrestore(&port->lock, flags); 1047 serial8250_rpm_put(up); 1048 return 1; 1049 } 1050 1051 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1052 { 1053 return false; 1054 } 1055 1056 #else 1057 1058 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 1059 { 1060 return -EINVAL; 1061 } 1062 #endif 1063 1064 static int omap8250_no_handle_irq(struct uart_port *port) 1065 { 1066 /* IRQ has not been requested but handling irq? */ 1067 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1068 return 0; 1069 } 1070 1071 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; 1072 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE; 1073 1074 static const struct of_device_id omap8250_dt_ids[] = { 1075 { .compatible = "ti,omap2-uart" }, 1076 { .compatible = "ti,omap3-uart" }, 1077 { .compatible = "ti,omap4-uart" }, 1078 { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, 1079 { .compatible = "ti,am4372-uart", .data = &am4372_habit, }, 1080 { .compatible = "ti,dra742-uart", .data = &am4372_habit, }, 1081 {}, 1082 }; 1083 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1084 1085 static int omap8250_probe(struct platform_device *pdev) 1086 { 1087 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1088 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1089 struct omap8250_priv *priv; 1090 struct uart_8250_port up; 1091 int ret; 1092 void __iomem *membase; 1093 1094 if (!regs || !irq) { 1095 dev_err(&pdev->dev, "missing registers or irq\n"); 1096 return -EINVAL; 1097 } 1098 1099 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1100 if (!priv) 1101 return -ENOMEM; 1102 1103 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1104 resource_size(regs)); 1105 if (!membase) 1106 return -ENODEV; 1107 1108 memset(&up, 0, sizeof(up)); 1109 up.port.dev = &pdev->dev; 1110 up.port.mapbase = regs->start; 1111 up.port.membase = membase; 1112 up.port.irq = irq->start; 1113 /* 1114 * It claims to be 16C750 compatible however it is a little different. 1115 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1116 * have) is enabled via EFR instead of MCR. The type is set here 8250 1117 * just to get things going. UNKNOWN does not work for a few reasons and 1118 * we don't need our own type since we don't use 8250's set_termios() 1119 * or pm callback. 1120 */ 1121 up.port.type = PORT_8250; 1122 up.port.iotype = UPIO_MEM; 1123 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1124 UPF_HARD_FLOW; 1125 up.port.private_data = priv; 1126 1127 up.port.regshift = 2; 1128 up.port.fifosize = 64; 1129 up.tx_loadsz = 64; 1130 up.capabilities = UART_CAP_FIFO; 1131 #ifdef CONFIG_PM 1132 /* 1133 * Runtime PM is mostly transparent. However to do it right we need to a 1134 * TX empty interrupt before we can put the device to auto idle. So if 1135 * PM is not enabled we don't add that flag and can spare that one extra 1136 * interrupt in the TX path. 1137 */ 1138 up.capabilities |= UART_CAP_RPM; 1139 #endif 1140 up.port.set_termios = omap_8250_set_termios; 1141 up.port.set_mctrl = omap8250_set_mctrl; 1142 up.port.pm = omap_8250_pm; 1143 up.port.startup = omap_8250_startup; 1144 up.port.shutdown = omap_8250_shutdown; 1145 up.port.throttle = omap_8250_throttle; 1146 up.port.unthrottle = omap_8250_unthrottle; 1147 1148 if (pdev->dev.of_node) { 1149 const struct of_device_id *id; 1150 1151 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1152 1153 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1154 &up.port.uartclk); 1155 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1156 1157 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); 1158 if (id && id->data) 1159 priv->habit |= *(u8 *)id->data; 1160 } else { 1161 ret = pdev->id; 1162 } 1163 if (ret < 0) { 1164 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1165 return ret; 1166 } 1167 up.port.line = ret; 1168 1169 if (!up.port.uartclk) { 1170 up.port.uartclk = DEFAULT_CLK_SPEED; 1171 dev_warn(&pdev->dev, 1172 "No clock speed specified: using default: %d\n", 1173 DEFAULT_CLK_SPEED); 1174 } 1175 1176 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1177 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1178 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1179 priv->latency); 1180 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1181 1182 spin_lock_init(&priv->rx_dma_lock); 1183 1184 device_init_wakeup(&pdev->dev, true); 1185 pm_runtime_use_autosuspend(&pdev->dev); 1186 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1187 1188 pm_runtime_irq_safe(&pdev->dev); 1189 pm_runtime_enable(&pdev->dev); 1190 1191 pm_runtime_get_sync(&pdev->dev); 1192 1193 omap_serial_fill_features_erratas(&up, priv); 1194 up.port.handle_irq = omap8250_no_handle_irq; 1195 #ifdef CONFIG_SERIAL_8250_DMA 1196 if (pdev->dev.of_node) { 1197 /* 1198 * Oh DMA support. If there are no DMA properties in the DT then 1199 * we will fall back to a generic DMA channel which does not 1200 * really work here. To ensure that we do not get a generic DMA 1201 * channel assigned, we have the the_no_dma_filter_fn() here. 1202 * To avoid "failed to request DMA" messages we check for DMA 1203 * properties in DT. 1204 */ 1205 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1206 if (ret == 2) { 1207 up.dma = &priv->omap8250_dma; 1208 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1209 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1210 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1211 priv->omap8250_dma.rx_size = RX_TRIGGER; 1212 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1213 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1214 1215 if (of_machine_is_compatible("ti,am33xx")) 1216 priv->habit |= OMAP_DMA_TX_KICK; 1217 /* 1218 * pause is currently not supported atleast on omap-sdma 1219 * and edma on most earlier kernels. 1220 */ 1221 priv->rx_dma_broken = true; 1222 } 1223 } 1224 #endif 1225 ret = serial8250_register_8250_port(&up); 1226 if (ret < 0) { 1227 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1228 goto err; 1229 } 1230 priv->line = ret; 1231 platform_set_drvdata(pdev, priv); 1232 pm_runtime_mark_last_busy(&pdev->dev); 1233 pm_runtime_put_autosuspend(&pdev->dev); 1234 return 0; 1235 err: 1236 pm_runtime_put(&pdev->dev); 1237 pm_runtime_disable(&pdev->dev); 1238 return ret; 1239 } 1240 1241 static int omap8250_remove(struct platform_device *pdev) 1242 { 1243 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1244 1245 pm_runtime_put_sync(&pdev->dev); 1246 pm_runtime_disable(&pdev->dev); 1247 serial8250_unregister_port(priv->line); 1248 pm_qos_remove_request(&priv->pm_qos_request); 1249 device_init_wakeup(&pdev->dev, false); 1250 return 0; 1251 } 1252 1253 #ifdef CONFIG_PM_SLEEP 1254 static int omap8250_prepare(struct device *dev) 1255 { 1256 struct omap8250_priv *priv = dev_get_drvdata(dev); 1257 1258 if (!priv) 1259 return 0; 1260 priv->is_suspending = true; 1261 return 0; 1262 } 1263 1264 static void omap8250_complete(struct device *dev) 1265 { 1266 struct omap8250_priv *priv = dev_get_drvdata(dev); 1267 1268 if (!priv) 1269 return; 1270 priv->is_suspending = false; 1271 } 1272 1273 static int omap8250_suspend(struct device *dev) 1274 { 1275 struct omap8250_priv *priv = dev_get_drvdata(dev); 1276 1277 serial8250_suspend_port(priv->line); 1278 flush_work(&priv->qos_work); 1279 return 0; 1280 } 1281 1282 static int omap8250_resume(struct device *dev) 1283 { 1284 struct omap8250_priv *priv = dev_get_drvdata(dev); 1285 1286 serial8250_resume_port(priv->line); 1287 return 0; 1288 } 1289 #else 1290 #define omap8250_prepare NULL 1291 #define omap8250_complete NULL 1292 #endif 1293 1294 #ifdef CONFIG_PM 1295 static int omap8250_lost_context(struct uart_8250_port *up) 1296 { 1297 u32 val; 1298 1299 val = serial_in(up, UART_OMAP_SCR); 1300 /* 1301 * If we lose context, then SCR is set to its reset value of zero. 1302 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1303 * among other bits, to never set the register back to zero again. 1304 */ 1305 if (!val) 1306 return 1; 1307 return 0; 1308 } 1309 1310 /* TODO: in future, this should happen via API in drivers/reset/ */ 1311 static int omap8250_soft_reset(struct device *dev) 1312 { 1313 struct omap8250_priv *priv = dev_get_drvdata(dev); 1314 struct uart_8250_port *up = serial8250_get_port(priv->line); 1315 int timeout = 100; 1316 int sysc; 1317 int syss; 1318 1319 sysc = serial_in(up, UART_OMAP_SYSC); 1320 1321 /* softreset the UART */ 1322 sysc |= OMAP_UART_SYSC_SOFTRESET; 1323 serial_out(up, UART_OMAP_SYSC, sysc); 1324 1325 /* By experiments, 1us enough for reset complete on AM335x */ 1326 do { 1327 udelay(1); 1328 syss = serial_in(up, UART_OMAP_SYSS); 1329 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1330 1331 if (!timeout) { 1332 dev_err(dev, "timed out waiting for reset done\n"); 1333 return -ETIMEDOUT; 1334 } 1335 1336 return 0; 1337 } 1338 1339 static int omap8250_runtime_suspend(struct device *dev) 1340 { 1341 struct omap8250_priv *priv = dev_get_drvdata(dev); 1342 struct uart_8250_port *up; 1343 1344 up = serial8250_get_port(priv->line); 1345 /* 1346 * When using 'no_console_suspend', the console UART must not be 1347 * suspended. Since driver suspend is managed by runtime suspend, 1348 * preventing runtime suspend (by returning error) will keep device 1349 * active during suspend. 1350 */ 1351 if (priv->is_suspending && !console_suspend_enabled) { 1352 if (uart_console(&up->port)) 1353 return -EBUSY; 1354 } 1355 1356 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1357 int ret; 1358 1359 ret = omap8250_soft_reset(dev); 1360 if (ret) 1361 return ret; 1362 1363 /* Restore to UART mode after reset (for wakeup) */ 1364 omap8250_update_mdr1(up, priv); 1365 } 1366 1367 if (up->dma && up->dma->rxchan) 1368 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1369 1370 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1371 schedule_work(&priv->qos_work); 1372 1373 return 0; 1374 } 1375 1376 static int omap8250_runtime_resume(struct device *dev) 1377 { 1378 struct omap8250_priv *priv = dev_get_drvdata(dev); 1379 struct uart_8250_port *up; 1380 int loss_cntx; 1381 1382 /* In case runtime-pm tries this before we are setup */ 1383 if (!priv) 1384 return 0; 1385 1386 up = serial8250_get_port(priv->line); 1387 loss_cntx = omap8250_lost_context(up); 1388 1389 if (loss_cntx) 1390 omap8250_restore_regs(up); 1391 1392 if (up->dma && up->dma->rxchan) 1393 omap_8250_rx_dma(up, 0); 1394 1395 priv->latency = priv->calc_latency; 1396 schedule_work(&priv->qos_work); 1397 return 0; 1398 } 1399 #endif 1400 1401 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1402 static int __init omap8250_console_fixup(void) 1403 { 1404 char *omap_str; 1405 char *options; 1406 u8 idx; 1407 1408 if (strstr(boot_command_line, "console=ttyS")) 1409 /* user set a ttyS based name for the console */ 1410 return 0; 1411 1412 omap_str = strstr(boot_command_line, "console=ttyO"); 1413 if (!omap_str) 1414 /* user did not set ttyO based console, so we don't care */ 1415 return 0; 1416 1417 omap_str += 12; 1418 if ('0' <= *omap_str && *omap_str <= '9') 1419 idx = *omap_str - '0'; 1420 else 1421 return 0; 1422 1423 omap_str++; 1424 if (omap_str[0] == ',') { 1425 omap_str++; 1426 options = omap_str; 1427 } else { 1428 options = NULL; 1429 } 1430 1431 add_preferred_console("ttyS", idx, options); 1432 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1433 idx, idx); 1434 pr_err("This ensures that you still see kernel messages. Please\n"); 1435 pr_err("update your kernel commandline.\n"); 1436 return 0; 1437 } 1438 console_initcall(omap8250_console_fixup); 1439 #endif 1440 1441 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1442 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1443 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1444 omap8250_runtime_resume, NULL) 1445 .prepare = omap8250_prepare, 1446 .complete = omap8250_complete, 1447 }; 1448 1449 static struct platform_driver omap8250_platform_driver = { 1450 .driver = { 1451 .name = "omap8250", 1452 .pm = &omap8250_dev_pm_ops, 1453 .of_match_table = omap8250_dt_ids, 1454 }, 1455 .probe = omap8250_probe, 1456 .remove = omap8250_remove, 1457 }; 1458 module_platform_driver(omap8250_platform_driver); 1459 1460 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1461 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1462 MODULE_LICENSE("GPL v2"); 1463