1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_reg.h> 15 #include <linux/tty_flip.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/delay.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/console.h> 25 #include <linux/pm_qos.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/dma-mapping.h> 28 29 #include "8250.h" 30 31 #define DEFAULT_CLK_SPEED 48000000 32 33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 35 #define OMAP_DMA_TX_KICK (1 << 2) 36 /* 37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 38 * The same errata is applicable to AM335x and DRA7x processors too. 39 */ 40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 41 42 #define OMAP_UART_FCR_RX_TRIG 6 43 #define OMAP_UART_FCR_TX_TRIG 4 44 45 /* SCR register bitmasks */ 46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 52 53 /* MVR register bitmasks */ 54 #define OMAP_UART_MVR_SCHEME_SHIFT 30 55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 58 #define OMAP_UART_MVR_MAJ_MASK 0x700 59 #define OMAP_UART_MVR_MAJ_SHIFT 8 60 #define OMAP_UART_MVR_MIN_MASK 0x3f 61 62 /* SYSC register bitmasks */ 63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 64 65 /* SYSS register bitmasks */ 66 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 67 68 #define UART_TI752_TLR_TX 0 69 #define UART_TI752_TLR_RX 4 70 71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 72 #define TRIGGER_FCR_MASK(x) (x & 3) 73 74 /* Enable XON/XOFF flow control on output */ 75 #define OMAP_UART_SW_TX 0x08 76 /* Enable XON/XOFF flow control on input */ 77 #define OMAP_UART_SW_RX 0x02 78 79 #define OMAP_UART_WER_MOD_WKUP 0x7f 80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 81 82 #define TX_TRIGGER 1 83 #define RX_TRIGGER 48 84 85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 87 88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 89 90 #define OMAP_UART_REV_46 0x0406 91 #define OMAP_UART_REV_52 0x0502 92 #define OMAP_UART_REV_63 0x0603 93 94 struct omap8250_priv { 95 int line; 96 u8 habit; 97 u8 mdr1; 98 u8 efr; 99 u8 scr; 100 u8 wer; 101 u8 xon; 102 u8 xoff; 103 u8 delayed_restore; 104 u16 quot; 105 106 bool is_suspending; 107 int wakeirq; 108 int wakeups_enabled; 109 u32 latency; 110 u32 calc_latency; 111 struct pm_qos_request pm_qos_request; 112 struct work_struct qos_work; 113 struct uart_8250_dma omap8250_dma; 114 spinlock_t rx_dma_lock; 115 bool rx_dma_broken; 116 }; 117 118 #ifdef CONFIG_SERIAL_8250_DMA 119 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 120 #else 121 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 122 #endif 123 124 static u32 uart_read(struct uart_8250_port *up, u32 reg) 125 { 126 return readl(up->port.membase + (reg << up->port.regshift)); 127 } 128 129 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 130 { 131 struct uart_8250_port *up = up_to_u8250p(port); 132 struct omap8250_priv *priv = up->port.private_data; 133 u8 lcr; 134 135 serial8250_do_set_mctrl(port, mctrl); 136 137 /* 138 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 139 * if RTS is raised 140 */ 141 lcr = serial_in(up, UART_LCR); 142 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 143 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 144 priv->efr |= UART_EFR_RTS; 145 else 146 priv->efr &= ~UART_EFR_RTS; 147 serial_out(up, UART_EFR, priv->efr); 148 serial_out(up, UART_LCR, lcr); 149 } 150 151 /* 152 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 153 * The access to uart register after MDR1 Access 154 * causes UART to corrupt data. 155 * 156 * Need a delay = 157 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 158 * give 10 times as much 159 */ 160 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 161 struct omap8250_priv *priv) 162 { 163 u8 timeout = 255; 164 u8 old_mdr1; 165 166 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 167 if (old_mdr1 == priv->mdr1) 168 return; 169 170 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 171 udelay(2); 172 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 173 UART_FCR_CLEAR_RCVR); 174 /* 175 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 176 * TX_FIFO_E bit is 1. 177 */ 178 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 179 (UART_LSR_THRE | UART_LSR_DR))) { 180 timeout--; 181 if (!timeout) { 182 /* Should *never* happen. we warn and carry on */ 183 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 184 serial_in(up, UART_LSR)); 185 break; 186 } 187 udelay(1); 188 } 189 } 190 191 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 192 struct omap8250_priv *priv) 193 { 194 unsigned int uartclk = port->uartclk; 195 unsigned int div_13, div_16; 196 unsigned int abs_d13, abs_d16; 197 198 /* 199 * Old custom speed handling. 200 */ 201 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 202 priv->quot = port->custom_divisor & 0xffff; 203 /* 204 * I assume that nobody is using this. But hey, if somebody 205 * would like to specify the divisor _and_ the mode then the 206 * driver is ready and waiting for it. 207 */ 208 if (port->custom_divisor & (1 << 16)) 209 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 210 else 211 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 212 return; 213 } 214 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 215 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 216 217 if (!div_13) 218 div_13 = 1; 219 if (!div_16) 220 div_16 = 1; 221 222 abs_d13 = abs(baud - uartclk / 13 / div_13); 223 abs_d16 = abs(baud - uartclk / 16 / div_16); 224 225 if (abs_d13 >= abs_d16) { 226 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 227 priv->quot = div_16; 228 } else { 229 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 230 priv->quot = div_13; 231 } 232 } 233 234 static void omap8250_update_scr(struct uart_8250_port *up, 235 struct omap8250_priv *priv) 236 { 237 u8 old_scr; 238 239 old_scr = serial_in(up, UART_OMAP_SCR); 240 if (old_scr == priv->scr) 241 return; 242 243 /* 244 * The manual recommends not to enable the DMA mode selector in the SCR 245 * (instead of the FCR) register _and_ selecting the DMA mode as one 246 * register write because this may lead to malfunction. 247 */ 248 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 249 serial_out(up, UART_OMAP_SCR, 250 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 251 serial_out(up, UART_OMAP_SCR, priv->scr); 252 } 253 254 static void omap8250_update_mdr1(struct uart_8250_port *up, 255 struct omap8250_priv *priv) 256 { 257 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 258 omap_8250_mdr1_errataset(up, priv); 259 else 260 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 261 } 262 263 static void omap8250_restore_regs(struct uart_8250_port *up) 264 { 265 struct omap8250_priv *priv = up->port.private_data; 266 struct uart_8250_dma *dma = up->dma; 267 268 if (dma && dma->tx_running) { 269 /* 270 * TCSANOW requests the change to occur immediately however if 271 * we have a TX-DMA operation in progress then it has been 272 * observed that it might stall and never complete. Therefore we 273 * delay DMA completes to prevent this hang from happen. 274 */ 275 priv->delayed_restore = 1; 276 return; 277 } 278 279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 280 serial_out(up, UART_EFR, UART_EFR_ECB); 281 282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 283 serial8250_out_MCR(up, UART_MCR_TCRTLR); 284 serial_out(up, UART_FCR, up->fcr); 285 286 omap8250_update_scr(up, priv); 287 288 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 289 290 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 291 OMAP_UART_TCR_HALT(52)); 292 serial_out(up, UART_TI752_TLR, 293 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 294 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 295 296 serial_out(up, UART_LCR, 0); 297 298 /* drop TCR + TLR access, we setup XON/XOFF later */ 299 serial8250_out_MCR(up, up->mcr); 300 serial_out(up, UART_IER, up->ier); 301 302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 303 serial_dl_write(up, priv->quot); 304 305 serial_out(up, UART_EFR, priv->efr); 306 307 /* Configure flow control */ 308 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 309 serial_out(up, UART_XON1, priv->xon); 310 serial_out(up, UART_XOFF1, priv->xoff); 311 312 serial_out(up, UART_LCR, up->lcr); 313 314 omap8250_update_mdr1(up, priv); 315 316 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 317 } 318 319 /* 320 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 321 * some differences in how we want to handle flow control. 322 */ 323 static void omap_8250_set_termios(struct uart_port *port, 324 struct ktermios *termios, 325 struct ktermios *old) 326 { 327 struct uart_8250_port *up = up_to_u8250p(port); 328 struct omap8250_priv *priv = up->port.private_data; 329 unsigned char cval = 0; 330 unsigned int baud; 331 332 switch (termios->c_cflag & CSIZE) { 333 case CS5: 334 cval = UART_LCR_WLEN5; 335 break; 336 case CS6: 337 cval = UART_LCR_WLEN6; 338 break; 339 case CS7: 340 cval = UART_LCR_WLEN7; 341 break; 342 default: 343 case CS8: 344 cval = UART_LCR_WLEN8; 345 break; 346 } 347 348 if (termios->c_cflag & CSTOPB) 349 cval |= UART_LCR_STOP; 350 if (termios->c_cflag & PARENB) 351 cval |= UART_LCR_PARITY; 352 if (!(termios->c_cflag & PARODD)) 353 cval |= UART_LCR_EPAR; 354 if (termios->c_cflag & CMSPAR) 355 cval |= UART_LCR_SPAR; 356 357 /* 358 * Ask the core to calculate the divisor for us. 359 */ 360 baud = uart_get_baud_rate(port, termios, old, 361 port->uartclk / 16 / 0xffff, 362 port->uartclk / 13); 363 omap_8250_get_divisor(port, baud, priv); 364 365 /* 366 * Ok, we're now changing the port state. Do it with 367 * interrupts disabled. 368 */ 369 pm_runtime_get_sync(port->dev); 370 spin_lock_irq(&port->lock); 371 372 /* 373 * Update the per-port timeout. 374 */ 375 uart_update_timeout(port, termios->c_cflag, baud); 376 377 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 378 if (termios->c_iflag & INPCK) 379 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 380 if (termios->c_iflag & (IGNBRK | PARMRK)) 381 up->port.read_status_mask |= UART_LSR_BI; 382 383 /* 384 * Characters to ignore 385 */ 386 up->port.ignore_status_mask = 0; 387 if (termios->c_iflag & IGNPAR) 388 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 389 if (termios->c_iflag & IGNBRK) { 390 up->port.ignore_status_mask |= UART_LSR_BI; 391 /* 392 * If we're ignoring parity and break indicators, 393 * ignore overruns too (for real raw support). 394 */ 395 if (termios->c_iflag & IGNPAR) 396 up->port.ignore_status_mask |= UART_LSR_OE; 397 } 398 399 /* 400 * ignore all characters if CREAD is not set 401 */ 402 if ((termios->c_cflag & CREAD) == 0) 403 up->port.ignore_status_mask |= UART_LSR_DR; 404 405 /* 406 * Modem status interrupts 407 */ 408 up->ier &= ~UART_IER_MSI; 409 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 410 up->ier |= UART_IER_MSI; 411 412 up->lcr = cval; 413 /* Up to here it was mostly serial8250_do_set_termios() */ 414 415 /* 416 * We enable TRIG_GRANU for RX and TX and additionaly we set 417 * SCR_TX_EMPTY bit. The result is the following: 418 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 419 * - less than RX_TRIGGER number of bytes will also cause an interrupt 420 * once the UART decides that there no new bytes arriving. 421 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 422 * empty - the trigger level is ignored here. 423 * 424 * Once DMA is enabled: 425 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 426 * bytes in the TX FIFO. On each assert the DMA engine will move 427 * TX_TRIGGER bytes into the FIFO. 428 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 429 * the FIFO and move RX_TRIGGER bytes. 430 * This is because threshold and trigger values are the same. 431 */ 432 up->fcr = UART_FCR_ENABLE_FIFO; 433 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 434 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 435 436 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 437 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 438 439 if (up->dma) 440 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 441 OMAP_UART_SCR_DMAMODE_CTL; 442 443 priv->xon = termios->c_cc[VSTART]; 444 priv->xoff = termios->c_cc[VSTOP]; 445 446 priv->efr = 0; 447 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 448 449 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 450 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 451 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 452 priv->efr |= UART_EFR_CTS; 453 } else if (up->port.flags & UPF_SOFT_FLOW) { 454 /* 455 * OMAP rx s/w flow control is borked; the transmitter remains 456 * stuck off even if rx flow control is subsequently disabled 457 */ 458 459 /* 460 * IXOFF Flag: 461 * Enable XON/XOFF flow control on output. 462 * Transmit XON1, XOFF1 463 */ 464 if (termios->c_iflag & IXOFF) { 465 up->port.status |= UPSTAT_AUTOXOFF; 466 priv->efr |= OMAP_UART_SW_TX; 467 } 468 } 469 omap8250_restore_regs(up); 470 471 spin_unlock_irq(&up->port.lock); 472 pm_runtime_mark_last_busy(port->dev); 473 pm_runtime_put_autosuspend(port->dev); 474 475 /* calculate wakeup latency constraint */ 476 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 477 priv->latency = priv->calc_latency; 478 479 schedule_work(&priv->qos_work); 480 481 /* Don't rewrite B0 */ 482 if (tty_termios_baud_rate(termios)) 483 tty_termios_encode_baud_rate(termios, baud, baud); 484 } 485 486 /* same as 8250 except that we may have extra flow bits set in EFR */ 487 static void omap_8250_pm(struct uart_port *port, unsigned int state, 488 unsigned int oldstate) 489 { 490 struct uart_8250_port *up = up_to_u8250p(port); 491 u8 efr; 492 493 pm_runtime_get_sync(port->dev); 494 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 495 efr = serial_in(up, UART_EFR); 496 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 497 serial_out(up, UART_LCR, 0); 498 499 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 500 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 501 serial_out(up, UART_EFR, efr); 502 serial_out(up, UART_LCR, 0); 503 504 pm_runtime_mark_last_busy(port->dev); 505 pm_runtime_put_autosuspend(port->dev); 506 } 507 508 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 509 struct omap8250_priv *priv) 510 { 511 u32 mvr, scheme; 512 u16 revision, major, minor; 513 514 mvr = uart_read(up, UART_OMAP_MVER); 515 516 /* Check revision register scheme */ 517 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 518 519 switch (scheme) { 520 case 0: /* Legacy Scheme: OMAP2/3 */ 521 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 522 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 523 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 524 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 525 break; 526 case 1: 527 /* New Scheme: OMAP4+ */ 528 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 529 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 530 OMAP_UART_MVR_MAJ_SHIFT; 531 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 532 break; 533 default: 534 dev_warn(up->port.dev, 535 "Unknown revision, defaulting to highest\n"); 536 /* highest possible revision */ 537 major = 0xff; 538 minor = 0xff; 539 } 540 /* normalize revision for the driver */ 541 revision = UART_BUILD_REVISION(major, minor); 542 543 switch (revision) { 544 case OMAP_UART_REV_46: 545 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 546 break; 547 case OMAP_UART_REV_52: 548 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 549 OMAP_UART_WER_HAS_TX_WAKEUP; 550 break; 551 case OMAP_UART_REV_63: 552 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 553 OMAP_UART_WER_HAS_TX_WAKEUP; 554 break; 555 default: 556 break; 557 } 558 } 559 560 static void omap8250_uart_qos_work(struct work_struct *work) 561 { 562 struct omap8250_priv *priv; 563 564 priv = container_of(work, struct omap8250_priv, qos_work); 565 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 566 } 567 568 #ifdef CONFIG_SERIAL_8250_DMA 569 static int omap_8250_dma_handle_irq(struct uart_port *port); 570 #endif 571 572 static irqreturn_t omap8250_irq(int irq, void *dev_id) 573 { 574 struct uart_port *port = dev_id; 575 struct uart_8250_port *up = up_to_u8250p(port); 576 unsigned int iir; 577 int ret; 578 579 #ifdef CONFIG_SERIAL_8250_DMA 580 if (up->dma) { 581 ret = omap_8250_dma_handle_irq(port); 582 return IRQ_RETVAL(ret); 583 } 584 #endif 585 586 serial8250_rpm_get(up); 587 iir = serial_port_in(port, UART_IIR); 588 ret = serial8250_handle_irq(port, iir); 589 serial8250_rpm_put(up); 590 591 return IRQ_RETVAL(ret); 592 } 593 594 static int omap_8250_startup(struct uart_port *port) 595 { 596 struct uart_8250_port *up = up_to_u8250p(port); 597 struct omap8250_priv *priv = port->private_data; 598 int ret; 599 600 if (priv->wakeirq) { 601 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 602 if (ret) 603 return ret; 604 } 605 606 pm_runtime_get_sync(port->dev); 607 608 up->mcr = 0; 609 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 610 611 serial_out(up, UART_LCR, UART_LCR_WLEN8); 612 613 up->lsr_saved_flags = 0; 614 up->msr_saved_flags = 0; 615 616 if (up->dma) { 617 ret = serial8250_request_dma(up); 618 if (ret) { 619 dev_warn_ratelimited(port->dev, 620 "failed to request DMA\n"); 621 up->dma = NULL; 622 } 623 } 624 625 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 626 dev_name(port->dev), port); 627 if (ret < 0) 628 goto err; 629 630 up->ier = UART_IER_RLSI | UART_IER_RDI; 631 serial_out(up, UART_IER, up->ier); 632 633 #ifdef CONFIG_PM 634 up->capabilities |= UART_CAP_RPM; 635 #endif 636 637 /* Enable module level wake up */ 638 priv->wer = OMAP_UART_WER_MOD_WKUP; 639 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 640 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 641 serial_out(up, UART_OMAP_WER, priv->wer); 642 643 if (up->dma) 644 up->dma->rx_dma(up); 645 646 pm_runtime_mark_last_busy(port->dev); 647 pm_runtime_put_autosuspend(port->dev); 648 return 0; 649 err: 650 pm_runtime_mark_last_busy(port->dev); 651 pm_runtime_put_autosuspend(port->dev); 652 dev_pm_clear_wake_irq(port->dev); 653 return ret; 654 } 655 656 static void omap_8250_shutdown(struct uart_port *port) 657 { 658 struct uart_8250_port *up = up_to_u8250p(port); 659 struct omap8250_priv *priv = port->private_data; 660 661 flush_work(&priv->qos_work); 662 if (up->dma) 663 omap_8250_rx_dma_flush(up); 664 665 pm_runtime_get_sync(port->dev); 666 667 serial_out(up, UART_OMAP_WER, 0); 668 669 up->ier = 0; 670 serial_out(up, UART_IER, 0); 671 672 if (up->dma) 673 serial8250_release_dma(up); 674 675 /* 676 * Disable break condition and FIFOs 677 */ 678 if (up->lcr & UART_LCR_SBC) 679 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 680 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 681 682 pm_runtime_mark_last_busy(port->dev); 683 pm_runtime_put_autosuspend(port->dev); 684 free_irq(port->irq, port); 685 dev_pm_clear_wake_irq(port->dev); 686 } 687 688 static void omap_8250_throttle(struct uart_port *port) 689 { 690 struct uart_8250_port *up = up_to_u8250p(port); 691 unsigned long flags; 692 693 pm_runtime_get_sync(port->dev); 694 695 spin_lock_irqsave(&port->lock, flags); 696 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 697 serial_out(up, UART_IER, up->ier); 698 spin_unlock_irqrestore(&port->lock, flags); 699 700 pm_runtime_mark_last_busy(port->dev); 701 pm_runtime_put_autosuspend(port->dev); 702 } 703 704 static int omap_8250_rs485_config(struct uart_port *port, 705 struct serial_rs485 *rs485) 706 { 707 struct uart_8250_port *up = up_to_u8250p(port); 708 709 /* Clamp the delays to [0, 100ms] */ 710 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 711 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 712 713 port->rs485 = *rs485; 714 715 /* 716 * Both serial8250_em485_init and serial8250_em485_destroy 717 * are idempotent 718 */ 719 if (rs485->flags & SER_RS485_ENABLED) { 720 int ret = serial8250_em485_init(up); 721 722 if (ret) { 723 rs485->flags &= ~SER_RS485_ENABLED; 724 port->rs485.flags &= ~SER_RS485_ENABLED; 725 } 726 return ret; 727 } 728 729 serial8250_em485_destroy(up); 730 731 return 0; 732 } 733 734 static void omap_8250_unthrottle(struct uart_port *port) 735 { 736 struct uart_8250_port *up = up_to_u8250p(port); 737 unsigned long flags; 738 739 pm_runtime_get_sync(port->dev); 740 741 spin_lock_irqsave(&port->lock, flags); 742 up->ier |= UART_IER_RLSI | UART_IER_RDI; 743 serial_out(up, UART_IER, up->ier); 744 spin_unlock_irqrestore(&port->lock, flags); 745 746 pm_runtime_mark_last_busy(port->dev); 747 pm_runtime_put_autosuspend(port->dev); 748 } 749 750 #ifdef CONFIG_SERIAL_8250_DMA 751 static int omap_8250_rx_dma(struct uart_8250_port *p); 752 753 static void __dma_rx_do_complete(struct uart_8250_port *p) 754 { 755 struct omap8250_priv *priv = p->port.private_data; 756 struct uart_8250_dma *dma = p->dma; 757 struct tty_port *tty_port = &p->port.state->port; 758 struct dma_tx_state state; 759 int count; 760 unsigned long flags; 761 int ret; 762 763 spin_lock_irqsave(&priv->rx_dma_lock, flags); 764 765 if (!dma->rx_running) 766 goto unlock; 767 768 dma->rx_running = 0; 769 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 770 771 count = dma->rx_size - state.residue; 772 773 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 774 775 p->port.icount.rx += ret; 776 p->port.icount.buf_overrun += count - ret; 777 unlock: 778 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 779 780 tty_flip_buffer_push(tty_port); 781 } 782 783 static void __dma_rx_complete(void *param) 784 { 785 __dma_rx_do_complete(param); 786 omap_8250_rx_dma(param); 787 } 788 789 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 790 { 791 struct omap8250_priv *priv = p->port.private_data; 792 struct uart_8250_dma *dma = p->dma; 793 unsigned long flags; 794 int ret; 795 796 spin_lock_irqsave(&priv->rx_dma_lock, flags); 797 798 if (!dma->rx_running) { 799 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 800 return; 801 } 802 803 ret = dmaengine_pause(dma->rxchan); 804 if (WARN_ON_ONCE(ret)) 805 priv->rx_dma_broken = true; 806 807 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 808 809 __dma_rx_do_complete(p); 810 dmaengine_terminate_all(dma->rxchan); 811 } 812 813 static int omap_8250_rx_dma(struct uart_8250_port *p) 814 { 815 struct omap8250_priv *priv = p->port.private_data; 816 struct uart_8250_dma *dma = p->dma; 817 int err = 0; 818 struct dma_async_tx_descriptor *desc; 819 unsigned long flags; 820 821 if (priv->rx_dma_broken) 822 return -EINVAL; 823 824 spin_lock_irqsave(&priv->rx_dma_lock, flags); 825 826 if (dma->rx_running) 827 goto out; 828 829 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 830 dma->rx_size, DMA_DEV_TO_MEM, 831 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 832 if (!desc) { 833 err = -EBUSY; 834 goto out; 835 } 836 837 dma->rx_running = 1; 838 desc->callback = __dma_rx_complete; 839 desc->callback_param = p; 840 841 dma->rx_cookie = dmaengine_submit(desc); 842 843 dma_async_issue_pending(dma->rxchan); 844 out: 845 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 846 return err; 847 } 848 849 static int omap_8250_tx_dma(struct uart_8250_port *p); 850 851 static void omap_8250_dma_tx_complete(void *param) 852 { 853 struct uart_8250_port *p = param; 854 struct uart_8250_dma *dma = p->dma; 855 struct circ_buf *xmit = &p->port.state->xmit; 856 unsigned long flags; 857 bool en_thri = false; 858 struct omap8250_priv *priv = p->port.private_data; 859 860 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 861 UART_XMIT_SIZE, DMA_TO_DEVICE); 862 863 spin_lock_irqsave(&p->port.lock, flags); 864 865 dma->tx_running = 0; 866 867 xmit->tail += dma->tx_size; 868 xmit->tail &= UART_XMIT_SIZE - 1; 869 p->port.icount.tx += dma->tx_size; 870 871 if (priv->delayed_restore) { 872 priv->delayed_restore = 0; 873 omap8250_restore_regs(p); 874 } 875 876 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 877 uart_write_wakeup(&p->port); 878 879 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 880 int ret; 881 882 ret = omap_8250_tx_dma(p); 883 if (ret) 884 en_thri = true; 885 886 } else if (p->capabilities & UART_CAP_RPM) { 887 en_thri = true; 888 } 889 890 if (en_thri) { 891 dma->tx_err = 1; 892 p->ier |= UART_IER_THRI; 893 serial_port_out(&p->port, UART_IER, p->ier); 894 } 895 896 spin_unlock_irqrestore(&p->port.lock, flags); 897 } 898 899 static int omap_8250_tx_dma(struct uart_8250_port *p) 900 { 901 struct uart_8250_dma *dma = p->dma; 902 struct omap8250_priv *priv = p->port.private_data; 903 struct circ_buf *xmit = &p->port.state->xmit; 904 struct dma_async_tx_descriptor *desc; 905 unsigned int skip_byte = 0; 906 int ret; 907 908 if (dma->tx_running) 909 return 0; 910 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 911 912 /* 913 * Even if no data, we need to return an error for the two cases 914 * below so serial8250_tx_chars() is invoked and properly clears 915 * THRI and/or runtime suspend. 916 */ 917 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 918 ret = -EBUSY; 919 goto err; 920 } 921 if (p->ier & UART_IER_THRI) { 922 p->ier &= ~UART_IER_THRI; 923 serial_out(p, UART_IER, p->ier); 924 } 925 return 0; 926 } 927 928 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 929 if (priv->habit & OMAP_DMA_TX_KICK) { 930 u8 tx_lvl; 931 932 /* 933 * We need to put the first byte into the FIFO in order to start 934 * the DMA transfer. For transfers smaller than four bytes we 935 * don't bother doing DMA at all. It seem not matter if there 936 * are still bytes in the FIFO from the last transfer (in case 937 * we got here directly from omap_8250_dma_tx_complete()). Bytes 938 * leaving the FIFO seem not to trigger the DMA transfer. It is 939 * really the byte that we put into the FIFO. 940 * If the FIFO is already full then we most likely got here from 941 * omap_8250_dma_tx_complete(). And this means the DMA engine 942 * just completed its work. We don't have to wait the complete 943 * 86us at 115200,8n1 but around 60us (not to mention lower 944 * baudrates). So in that case we take the interrupt and try 945 * again with an empty FIFO. 946 */ 947 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 948 if (tx_lvl == p->tx_loadsz) { 949 ret = -EBUSY; 950 goto err; 951 } 952 if (dma->tx_size < 4) { 953 ret = -EINVAL; 954 goto err; 955 } 956 skip_byte = 1; 957 } 958 959 desc = dmaengine_prep_slave_single(dma->txchan, 960 dma->tx_addr + xmit->tail + skip_byte, 961 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 962 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 963 if (!desc) { 964 ret = -EBUSY; 965 goto err; 966 } 967 968 dma->tx_running = 1; 969 970 desc->callback = omap_8250_dma_tx_complete; 971 desc->callback_param = p; 972 973 dma->tx_cookie = dmaengine_submit(desc); 974 975 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 976 UART_XMIT_SIZE, DMA_TO_DEVICE); 977 978 dma_async_issue_pending(dma->txchan); 979 if (dma->tx_err) 980 dma->tx_err = 0; 981 982 if (p->ier & UART_IER_THRI) { 983 p->ier &= ~UART_IER_THRI; 984 serial_out(p, UART_IER, p->ier); 985 } 986 if (skip_byte) 987 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 988 return 0; 989 err: 990 dma->tx_err = 1; 991 return ret; 992 } 993 994 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 995 { 996 switch (iir & 0x3f) { 997 case UART_IIR_RLSI: 998 case UART_IIR_RX_TIMEOUT: 999 case UART_IIR_RDI: 1000 omap_8250_rx_dma_flush(up); 1001 return true; 1002 } 1003 return omap_8250_rx_dma(up); 1004 } 1005 1006 /* 1007 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1008 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1009 * use the default routine in the non-DMA case and this one for with DMA. 1010 */ 1011 static int omap_8250_dma_handle_irq(struct uart_port *port) 1012 { 1013 struct uart_8250_port *up = up_to_u8250p(port); 1014 unsigned char status; 1015 unsigned long flags; 1016 u8 iir; 1017 1018 serial8250_rpm_get(up); 1019 1020 iir = serial_port_in(port, UART_IIR); 1021 if (iir & UART_IIR_NO_INT) { 1022 serial8250_rpm_put(up); 1023 return 0; 1024 } 1025 1026 spin_lock_irqsave(&port->lock, flags); 1027 1028 status = serial_port_in(port, UART_LSR); 1029 1030 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1031 if (handle_rx_dma(up, iir)) { 1032 status = serial8250_rx_chars(up, status); 1033 omap_8250_rx_dma(up); 1034 } 1035 } 1036 serial8250_modem_status(up); 1037 if (status & UART_LSR_THRE && up->dma->tx_err) { 1038 if (uart_tx_stopped(&up->port) || 1039 uart_circ_empty(&up->port.state->xmit)) { 1040 up->dma->tx_err = 0; 1041 serial8250_tx_chars(up); 1042 } else { 1043 /* 1044 * try again due to an earlier failer which 1045 * might have been resolved by now. 1046 */ 1047 if (omap_8250_tx_dma(up)) 1048 serial8250_tx_chars(up); 1049 } 1050 } 1051 1052 spin_unlock_irqrestore(&port->lock, flags); 1053 serial8250_rpm_put(up); 1054 return 1; 1055 } 1056 1057 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1058 { 1059 return false; 1060 } 1061 1062 #else 1063 1064 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1065 { 1066 return -EINVAL; 1067 } 1068 #endif 1069 1070 static int omap8250_no_handle_irq(struct uart_port *port) 1071 { 1072 /* IRQ has not been requested but handling irq? */ 1073 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1074 return 0; 1075 } 1076 1077 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; 1078 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE; 1079 1080 static const struct of_device_id omap8250_dt_ids[] = { 1081 { .compatible = "ti,omap2-uart" }, 1082 { .compatible = "ti,omap3-uart" }, 1083 { .compatible = "ti,omap4-uart" }, 1084 { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, 1085 { .compatible = "ti,am4372-uart", .data = &am4372_habit, }, 1086 { .compatible = "ti,dra742-uart", .data = &am4372_habit, }, 1087 {}, 1088 }; 1089 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1090 1091 static int omap8250_probe(struct platform_device *pdev) 1092 { 1093 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1094 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1095 struct omap8250_priv *priv; 1096 struct uart_8250_port up; 1097 int ret; 1098 void __iomem *membase; 1099 1100 if (!regs || !irq) { 1101 dev_err(&pdev->dev, "missing registers or irq\n"); 1102 return -EINVAL; 1103 } 1104 1105 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1106 if (!priv) 1107 return -ENOMEM; 1108 1109 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1110 resource_size(regs)); 1111 if (!membase) 1112 return -ENODEV; 1113 1114 memset(&up, 0, sizeof(up)); 1115 up.port.dev = &pdev->dev; 1116 up.port.mapbase = regs->start; 1117 up.port.membase = membase; 1118 up.port.irq = irq->start; 1119 /* 1120 * It claims to be 16C750 compatible however it is a little different. 1121 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1122 * have) is enabled via EFR instead of MCR. The type is set here 8250 1123 * just to get things going. UNKNOWN does not work for a few reasons and 1124 * we don't need our own type since we don't use 8250's set_termios() 1125 * or pm callback. 1126 */ 1127 up.port.type = PORT_8250; 1128 up.port.iotype = UPIO_MEM; 1129 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1130 UPF_HARD_FLOW; 1131 up.port.private_data = priv; 1132 1133 up.port.regshift = 2; 1134 up.port.fifosize = 64; 1135 up.tx_loadsz = 64; 1136 up.capabilities = UART_CAP_FIFO; 1137 #ifdef CONFIG_PM 1138 /* 1139 * Runtime PM is mostly transparent. However to do it right we need to a 1140 * TX empty interrupt before we can put the device to auto idle. So if 1141 * PM is not enabled we don't add that flag and can spare that one extra 1142 * interrupt in the TX path. 1143 */ 1144 up.capabilities |= UART_CAP_RPM; 1145 #endif 1146 up.port.set_termios = omap_8250_set_termios; 1147 up.port.set_mctrl = omap8250_set_mctrl; 1148 up.port.pm = omap_8250_pm; 1149 up.port.startup = omap_8250_startup; 1150 up.port.shutdown = omap_8250_shutdown; 1151 up.port.throttle = omap_8250_throttle; 1152 up.port.unthrottle = omap_8250_unthrottle; 1153 up.port.rs485_config = omap_8250_rs485_config; 1154 1155 if (pdev->dev.of_node) { 1156 const struct of_device_id *id; 1157 1158 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1159 1160 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1161 &up.port.uartclk); 1162 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1163 1164 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); 1165 if (id && id->data) 1166 priv->habit |= *(u8 *)id->data; 1167 } else { 1168 ret = pdev->id; 1169 } 1170 if (ret < 0) { 1171 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1172 return ret; 1173 } 1174 up.port.line = ret; 1175 1176 if (!up.port.uartclk) { 1177 up.port.uartclk = DEFAULT_CLK_SPEED; 1178 dev_warn(&pdev->dev, 1179 "No clock speed specified: using default: %d\n", 1180 DEFAULT_CLK_SPEED); 1181 } 1182 1183 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1184 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1185 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1186 priv->latency); 1187 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1188 1189 spin_lock_init(&priv->rx_dma_lock); 1190 1191 device_init_wakeup(&pdev->dev, true); 1192 pm_runtime_use_autosuspend(&pdev->dev); 1193 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1194 1195 pm_runtime_irq_safe(&pdev->dev); 1196 pm_runtime_enable(&pdev->dev); 1197 1198 pm_runtime_get_sync(&pdev->dev); 1199 1200 omap_serial_fill_features_erratas(&up, priv); 1201 up.port.handle_irq = omap8250_no_handle_irq; 1202 #ifdef CONFIG_SERIAL_8250_DMA 1203 if (pdev->dev.of_node) { 1204 /* 1205 * Oh DMA support. If there are no DMA properties in the DT then 1206 * we will fall back to a generic DMA channel which does not 1207 * really work here. To ensure that we do not get a generic DMA 1208 * channel assigned, we have the the_no_dma_filter_fn() here. 1209 * To avoid "failed to request DMA" messages we check for DMA 1210 * properties in DT. 1211 */ 1212 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1213 if (ret == 2) { 1214 up.dma = &priv->omap8250_dma; 1215 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1216 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1217 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1218 priv->omap8250_dma.rx_size = RX_TRIGGER; 1219 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1220 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1221 1222 if (of_machine_is_compatible("ti,am33xx")) 1223 priv->habit |= OMAP_DMA_TX_KICK; 1224 /* 1225 * pause is currently not supported atleast on omap-sdma 1226 * and edma on most earlier kernels. 1227 */ 1228 priv->rx_dma_broken = true; 1229 } 1230 } 1231 #endif 1232 ret = serial8250_register_8250_port(&up); 1233 if (ret < 0) { 1234 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1235 goto err; 1236 } 1237 priv->line = ret; 1238 platform_set_drvdata(pdev, priv); 1239 pm_runtime_mark_last_busy(&pdev->dev); 1240 pm_runtime_put_autosuspend(&pdev->dev); 1241 return 0; 1242 err: 1243 pm_runtime_put(&pdev->dev); 1244 pm_runtime_disable(&pdev->dev); 1245 return ret; 1246 } 1247 1248 static int omap8250_remove(struct platform_device *pdev) 1249 { 1250 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1251 1252 pm_runtime_put_sync(&pdev->dev); 1253 pm_runtime_disable(&pdev->dev); 1254 serial8250_unregister_port(priv->line); 1255 pm_qos_remove_request(&priv->pm_qos_request); 1256 device_init_wakeup(&pdev->dev, false); 1257 return 0; 1258 } 1259 1260 #ifdef CONFIG_PM_SLEEP 1261 static int omap8250_prepare(struct device *dev) 1262 { 1263 struct omap8250_priv *priv = dev_get_drvdata(dev); 1264 1265 if (!priv) 1266 return 0; 1267 priv->is_suspending = true; 1268 return 0; 1269 } 1270 1271 static void omap8250_complete(struct device *dev) 1272 { 1273 struct omap8250_priv *priv = dev_get_drvdata(dev); 1274 1275 if (!priv) 1276 return; 1277 priv->is_suspending = false; 1278 } 1279 1280 static int omap8250_suspend(struct device *dev) 1281 { 1282 struct omap8250_priv *priv = dev_get_drvdata(dev); 1283 1284 serial8250_suspend_port(priv->line); 1285 flush_work(&priv->qos_work); 1286 return 0; 1287 } 1288 1289 static int omap8250_resume(struct device *dev) 1290 { 1291 struct omap8250_priv *priv = dev_get_drvdata(dev); 1292 1293 serial8250_resume_port(priv->line); 1294 return 0; 1295 } 1296 #else 1297 #define omap8250_prepare NULL 1298 #define omap8250_complete NULL 1299 #endif 1300 1301 #ifdef CONFIG_PM 1302 static int omap8250_lost_context(struct uart_8250_port *up) 1303 { 1304 u32 val; 1305 1306 val = serial_in(up, UART_OMAP_SCR); 1307 /* 1308 * If we lose context, then SCR is set to its reset value of zero. 1309 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1310 * among other bits, to never set the register back to zero again. 1311 */ 1312 if (!val) 1313 return 1; 1314 return 0; 1315 } 1316 1317 /* TODO: in future, this should happen via API in drivers/reset/ */ 1318 static int omap8250_soft_reset(struct device *dev) 1319 { 1320 struct omap8250_priv *priv = dev_get_drvdata(dev); 1321 struct uart_8250_port *up = serial8250_get_port(priv->line); 1322 int timeout = 100; 1323 int sysc; 1324 int syss; 1325 1326 sysc = serial_in(up, UART_OMAP_SYSC); 1327 1328 /* softreset the UART */ 1329 sysc |= OMAP_UART_SYSC_SOFTRESET; 1330 serial_out(up, UART_OMAP_SYSC, sysc); 1331 1332 /* By experiments, 1us enough for reset complete on AM335x */ 1333 do { 1334 udelay(1); 1335 syss = serial_in(up, UART_OMAP_SYSS); 1336 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1337 1338 if (!timeout) { 1339 dev_err(dev, "timed out waiting for reset done\n"); 1340 return -ETIMEDOUT; 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int omap8250_runtime_suspend(struct device *dev) 1347 { 1348 struct omap8250_priv *priv = dev_get_drvdata(dev); 1349 struct uart_8250_port *up; 1350 1351 up = serial8250_get_port(priv->line); 1352 /* 1353 * When using 'no_console_suspend', the console UART must not be 1354 * suspended. Since driver suspend is managed by runtime suspend, 1355 * preventing runtime suspend (by returning error) will keep device 1356 * active during suspend. 1357 */ 1358 if (priv->is_suspending && !console_suspend_enabled) { 1359 if (uart_console(&up->port)) 1360 return -EBUSY; 1361 } 1362 1363 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1364 int ret; 1365 1366 ret = omap8250_soft_reset(dev); 1367 if (ret) 1368 return ret; 1369 1370 /* Restore to UART mode after reset (for wakeup) */ 1371 omap8250_update_mdr1(up, priv); 1372 } 1373 1374 if (up->dma && up->dma->rxchan) 1375 omap_8250_rx_dma_flush(up); 1376 1377 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1378 schedule_work(&priv->qos_work); 1379 1380 return 0; 1381 } 1382 1383 static int omap8250_runtime_resume(struct device *dev) 1384 { 1385 struct omap8250_priv *priv = dev_get_drvdata(dev); 1386 struct uart_8250_port *up; 1387 1388 /* In case runtime-pm tries this before we are setup */ 1389 if (!priv) 1390 return 0; 1391 1392 up = serial8250_get_port(priv->line); 1393 1394 if (omap8250_lost_context(up)) 1395 omap8250_restore_regs(up); 1396 1397 if (up->dma && up->dma->rxchan) 1398 omap_8250_rx_dma(up); 1399 1400 priv->latency = priv->calc_latency; 1401 schedule_work(&priv->qos_work); 1402 return 0; 1403 } 1404 #endif 1405 1406 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1407 static int __init omap8250_console_fixup(void) 1408 { 1409 char *omap_str; 1410 char *options; 1411 u8 idx; 1412 1413 if (strstr(boot_command_line, "console=ttyS")) 1414 /* user set a ttyS based name for the console */ 1415 return 0; 1416 1417 omap_str = strstr(boot_command_line, "console=ttyO"); 1418 if (!omap_str) 1419 /* user did not set ttyO based console, so we don't care */ 1420 return 0; 1421 1422 omap_str += 12; 1423 if ('0' <= *omap_str && *omap_str <= '9') 1424 idx = *omap_str - '0'; 1425 else 1426 return 0; 1427 1428 omap_str++; 1429 if (omap_str[0] == ',') { 1430 omap_str++; 1431 options = omap_str; 1432 } else { 1433 options = NULL; 1434 } 1435 1436 add_preferred_console("ttyS", idx, options); 1437 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1438 idx, idx); 1439 pr_err("This ensures that you still see kernel messages. Please\n"); 1440 pr_err("update your kernel commandline.\n"); 1441 return 0; 1442 } 1443 console_initcall(omap8250_console_fixup); 1444 #endif 1445 1446 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1447 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1448 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1449 omap8250_runtime_resume, NULL) 1450 .prepare = omap8250_prepare, 1451 .complete = omap8250_complete, 1452 }; 1453 1454 static struct platform_driver omap8250_platform_driver = { 1455 .driver = { 1456 .name = "omap8250", 1457 .pm = &omap8250_dev_pm_ops, 1458 .of_match_table = omap8250_dt_ids, 1459 }, 1460 .probe = omap8250_probe, 1461 .remove = omap8250_remove, 1462 }; 1463 module_platform_driver(omap8250_platform_driver); 1464 1465 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1466 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1467 MODULE_LICENSE("GPL v2"); 1468