1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/serial_8250.h> 16 #include <linux/serial_reg.h> 17 #include <linux/tty_flip.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/delay.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/console.h> 27 #include <linux/pm_qos.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sys_soc.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 48 #define OMAP_UART_FCR_RX_TRIG 6 49 #define OMAP_UART_FCR_TX_TRIG 4 50 51 /* SCR register bitmasks */ 52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 58 59 /* MVR register bitmasks */ 60 #define OMAP_UART_MVR_SCHEME_SHIFT 30 61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 64 #define OMAP_UART_MVR_MAJ_MASK 0x700 65 #define OMAP_UART_MVR_MAJ_SHIFT 8 66 #define OMAP_UART_MVR_MIN_MASK 0x3f 67 68 /* SYSC register bitmasks */ 69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 70 71 /* SYSS register bitmasks */ 72 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 73 74 #define UART_TI752_TLR_TX 0 75 #define UART_TI752_TLR_RX 4 76 77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 78 #define TRIGGER_FCR_MASK(x) (x & 3) 79 80 /* Enable XON/XOFF flow control on output */ 81 #define OMAP_UART_SW_TX 0x08 82 /* Enable XON/XOFF flow control on input */ 83 #define OMAP_UART_SW_RX 0x02 84 85 #define OMAP_UART_WER_MOD_WKUP 0x7f 86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 87 88 #define TX_TRIGGER 1 89 #define RX_TRIGGER 48 90 91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 93 94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 95 96 #define OMAP_UART_REV_46 0x0406 97 #define OMAP_UART_REV_52 0x0502 98 #define OMAP_UART_REV_63 0x0603 99 100 /* Interrupt Enable Register 2 */ 101 #define UART_OMAP_IER2 0x1B 102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 103 104 /* Enhanced features register 2 */ 105 #define UART_OMAP_EFR2 0x23 106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 107 108 /* RX FIFO occupancy indicator */ 109 #define UART_OMAP_RX_LVL 0x19 110 111 struct omap8250_priv { 112 int line; 113 u8 habit; 114 u8 mdr1; 115 u8 efr; 116 u8 scr; 117 u8 wer; 118 u8 xon; 119 u8 xoff; 120 u8 delayed_restore; 121 u16 quot; 122 123 u8 tx_trigger; 124 u8 rx_trigger; 125 bool is_suspending; 126 int wakeirq; 127 int wakeups_enabled; 128 u32 latency; 129 u32 calc_latency; 130 struct pm_qos_request pm_qos_request; 131 struct work_struct qos_work; 132 struct uart_8250_dma omap8250_dma; 133 spinlock_t rx_dma_lock; 134 bool rx_dma_broken; 135 bool throttled; 136 }; 137 138 struct omap8250_dma_params { 139 u32 rx_size; 140 u8 rx_trigger; 141 u8 tx_trigger; 142 }; 143 144 struct omap8250_platdata { 145 struct omap8250_dma_params *dma_params; 146 u8 habit; 147 }; 148 149 #ifdef CONFIG_SERIAL_8250_DMA 150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 151 #else 152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 153 #endif 154 155 static u32 uart_read(struct uart_8250_port *up, u32 reg) 156 { 157 return readl(up->port.membase + (reg << up->port.regshift)); 158 } 159 160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 161 { 162 struct uart_8250_port *up = up_to_u8250p(port); 163 struct omap8250_priv *priv = up->port.private_data; 164 u8 lcr; 165 166 serial8250_do_set_mctrl(port, mctrl); 167 168 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 169 /* 170 * Turn off autoRTS if RTS is lowered and restore autoRTS 171 * setting if RTS is raised 172 */ 173 lcr = serial_in(up, UART_LCR); 174 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 175 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 176 priv->efr |= UART_EFR_RTS; 177 else 178 priv->efr &= ~UART_EFR_RTS; 179 serial_out(up, UART_EFR, priv->efr); 180 serial_out(up, UART_LCR, lcr); 181 } 182 } 183 184 /* 185 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 186 * The access to uart register after MDR1 Access 187 * causes UART to corrupt data. 188 * 189 * Need a delay = 190 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 191 * give 10 times as much 192 */ 193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 194 struct omap8250_priv *priv) 195 { 196 u8 timeout = 255; 197 198 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 199 udelay(2); 200 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 201 UART_FCR_CLEAR_RCVR); 202 /* 203 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 204 * TX_FIFO_E bit is 1. 205 */ 206 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 207 (UART_LSR_THRE | UART_LSR_DR))) { 208 timeout--; 209 if (!timeout) { 210 /* Should *never* happen. we warn and carry on */ 211 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 212 serial_in(up, UART_LSR)); 213 break; 214 } 215 udelay(1); 216 } 217 } 218 219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 220 struct omap8250_priv *priv) 221 { 222 unsigned int uartclk = port->uartclk; 223 unsigned int div_13, div_16; 224 unsigned int abs_d13, abs_d16; 225 226 /* 227 * Old custom speed handling. 228 */ 229 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 230 priv->quot = port->custom_divisor & UART_DIV_MAX; 231 /* 232 * I assume that nobody is using this. But hey, if somebody 233 * would like to specify the divisor _and_ the mode then the 234 * driver is ready and waiting for it. 235 */ 236 if (port->custom_divisor & (1 << 16)) 237 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 238 else 239 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 240 return; 241 } 242 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 243 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 244 245 if (!div_13) 246 div_13 = 1; 247 if (!div_16) 248 div_16 = 1; 249 250 abs_d13 = abs(baud - uartclk / 13 / div_13); 251 abs_d16 = abs(baud - uartclk / 16 / div_16); 252 253 if (abs_d13 >= abs_d16) { 254 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 255 priv->quot = div_16; 256 } else { 257 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 258 priv->quot = div_13; 259 } 260 } 261 262 static void omap8250_update_scr(struct uart_8250_port *up, 263 struct omap8250_priv *priv) 264 { 265 u8 old_scr; 266 267 old_scr = serial_in(up, UART_OMAP_SCR); 268 if (old_scr == priv->scr) 269 return; 270 271 /* 272 * The manual recommends not to enable the DMA mode selector in the SCR 273 * (instead of the FCR) register _and_ selecting the DMA mode as one 274 * register write because this may lead to malfunction. 275 */ 276 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 277 serial_out(up, UART_OMAP_SCR, 278 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 279 serial_out(up, UART_OMAP_SCR, priv->scr); 280 } 281 282 static void omap8250_update_mdr1(struct uart_8250_port *up, 283 struct omap8250_priv *priv) 284 { 285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 286 omap_8250_mdr1_errataset(up, priv); 287 else 288 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 289 } 290 291 static void omap8250_restore_regs(struct uart_8250_port *up) 292 { 293 struct omap8250_priv *priv = up->port.private_data; 294 struct uart_8250_dma *dma = up->dma; 295 296 if (dma && dma->tx_running) { 297 /* 298 * TCSANOW requests the change to occur immediately however if 299 * we have a TX-DMA operation in progress then it has been 300 * observed that it might stall and never complete. Therefore we 301 * delay DMA completes to prevent this hang from happen. 302 */ 303 priv->delayed_restore = 1; 304 return; 305 } 306 307 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 308 serial_out(up, UART_EFR, UART_EFR_ECB); 309 310 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 311 serial8250_out_MCR(up, UART_MCR_TCRTLR); 312 serial_out(up, UART_FCR, up->fcr); 313 314 omap8250_update_scr(up, priv); 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 318 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 319 OMAP_UART_TCR_HALT(52)); 320 serial_out(up, UART_TI752_TLR, 321 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 322 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 323 324 serial_out(up, UART_LCR, 0); 325 326 /* drop TCR + TLR access, we setup XON/XOFF later */ 327 serial8250_out_MCR(up, up->mcr); 328 serial_out(up, UART_IER, up->ier); 329 330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 331 serial_dl_write(up, priv->quot); 332 333 serial_out(up, UART_EFR, priv->efr); 334 335 /* Configure flow control */ 336 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 337 serial_out(up, UART_XON1, priv->xon); 338 serial_out(up, UART_XOFF1, priv->xoff); 339 340 serial_out(up, UART_LCR, up->lcr); 341 342 omap8250_update_mdr1(up, priv); 343 344 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 345 346 if (up->port.rs485.flags & SER_RS485_ENABLED) 347 serial8250_em485_stop_tx(up); 348 } 349 350 /* 351 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 352 * some differences in how we want to handle flow control. 353 */ 354 static void omap_8250_set_termios(struct uart_port *port, 355 struct ktermios *termios, 356 const struct ktermios *old) 357 { 358 struct uart_8250_port *up = up_to_u8250p(port); 359 struct omap8250_priv *priv = up->port.private_data; 360 unsigned char cval = 0; 361 unsigned int baud; 362 363 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 364 365 if (termios->c_cflag & CSTOPB) 366 cval |= UART_LCR_STOP; 367 if (termios->c_cflag & PARENB) 368 cval |= UART_LCR_PARITY; 369 if (!(termios->c_cflag & PARODD)) 370 cval |= UART_LCR_EPAR; 371 if (termios->c_cflag & CMSPAR) 372 cval |= UART_LCR_SPAR; 373 374 /* 375 * Ask the core to calculate the divisor for us. 376 */ 377 baud = uart_get_baud_rate(port, termios, old, 378 port->uartclk / 16 / UART_DIV_MAX, 379 port->uartclk / 13); 380 omap_8250_get_divisor(port, baud, priv); 381 382 /* 383 * Ok, we're now changing the port state. Do it with 384 * interrupts disabled. 385 */ 386 pm_runtime_get_sync(port->dev); 387 spin_lock_irq(&port->lock); 388 389 /* 390 * Update the per-port timeout. 391 */ 392 uart_update_timeout(port, termios->c_cflag, baud); 393 394 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 395 if (termios->c_iflag & INPCK) 396 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 397 if (termios->c_iflag & (IGNBRK | PARMRK)) 398 up->port.read_status_mask |= UART_LSR_BI; 399 400 /* 401 * Characters to ignore 402 */ 403 up->port.ignore_status_mask = 0; 404 if (termios->c_iflag & IGNPAR) 405 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 406 if (termios->c_iflag & IGNBRK) { 407 up->port.ignore_status_mask |= UART_LSR_BI; 408 /* 409 * If we're ignoring parity and break indicators, 410 * ignore overruns too (for real raw support). 411 */ 412 if (termios->c_iflag & IGNPAR) 413 up->port.ignore_status_mask |= UART_LSR_OE; 414 } 415 416 /* 417 * ignore all characters if CREAD is not set 418 */ 419 if ((termios->c_cflag & CREAD) == 0) 420 up->port.ignore_status_mask |= UART_LSR_DR; 421 422 /* 423 * Modem status interrupts 424 */ 425 up->ier &= ~UART_IER_MSI; 426 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 427 up->ier |= UART_IER_MSI; 428 429 up->lcr = cval; 430 /* Up to here it was mostly serial8250_do_set_termios() */ 431 432 /* 433 * We enable TRIG_GRANU for RX and TX and additionally we set 434 * SCR_TX_EMPTY bit. The result is the following: 435 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 436 * - less than RX_TRIGGER number of bytes will also cause an interrupt 437 * once the UART decides that there no new bytes arriving. 438 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 439 * empty - the trigger level is ignored here. 440 * 441 * Once DMA is enabled: 442 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 443 * bytes in the TX FIFO. On each assert the DMA engine will move 444 * TX_TRIGGER bytes into the FIFO. 445 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 446 * the FIFO and move RX_TRIGGER bytes. 447 * This is because threshold and trigger values are the same. 448 */ 449 up->fcr = UART_FCR_ENABLE_FIFO; 450 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 451 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 452 453 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 454 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 455 456 if (up->dma) 457 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 458 OMAP_UART_SCR_DMAMODE_CTL; 459 460 priv->xon = termios->c_cc[VSTART]; 461 priv->xoff = termios->c_cc[VSTOP]; 462 463 priv->efr = 0; 464 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 465 466 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 467 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 468 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 469 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 470 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 471 priv->efr |= UART_EFR_CTS; 472 } else if (up->port.flags & UPF_SOFT_FLOW) { 473 /* 474 * OMAP rx s/w flow control is borked; the transmitter remains 475 * stuck off even if rx flow control is subsequently disabled 476 */ 477 478 /* 479 * IXOFF Flag: 480 * Enable XON/XOFF flow control on output. 481 * Transmit XON1, XOFF1 482 */ 483 if (termios->c_iflag & IXOFF) { 484 up->port.status |= UPSTAT_AUTOXOFF; 485 priv->efr |= OMAP_UART_SW_TX; 486 } 487 } 488 omap8250_restore_regs(up); 489 490 spin_unlock_irq(&up->port.lock); 491 pm_runtime_mark_last_busy(port->dev); 492 pm_runtime_put_autosuspend(port->dev); 493 494 /* calculate wakeup latency constraint */ 495 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 496 priv->latency = priv->calc_latency; 497 498 schedule_work(&priv->qos_work); 499 500 /* Don't rewrite B0 */ 501 if (tty_termios_baud_rate(termios)) 502 tty_termios_encode_baud_rate(termios, baud, baud); 503 } 504 505 /* same as 8250 except that we may have extra flow bits set in EFR */ 506 static void omap_8250_pm(struct uart_port *port, unsigned int state, 507 unsigned int oldstate) 508 { 509 struct uart_8250_port *up = up_to_u8250p(port); 510 u8 efr; 511 512 pm_runtime_get_sync(port->dev); 513 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 514 efr = serial_in(up, UART_EFR); 515 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 516 serial_out(up, UART_LCR, 0); 517 518 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 519 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 520 serial_out(up, UART_EFR, efr); 521 serial_out(up, UART_LCR, 0); 522 523 pm_runtime_mark_last_busy(port->dev); 524 pm_runtime_put_autosuspend(port->dev); 525 } 526 527 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 528 struct omap8250_priv *priv) 529 { 530 static const struct soc_device_attribute k3_soc_devices[] = { 531 { .family = "AM65X", }, 532 { .family = "J721E", .revision = "SR1.0" }, 533 { /* sentinel */ } 534 }; 535 u32 mvr, scheme; 536 u16 revision, major, minor; 537 538 mvr = uart_read(up, UART_OMAP_MVER); 539 540 /* Check revision register scheme */ 541 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 542 543 switch (scheme) { 544 case 0: /* Legacy Scheme: OMAP2/3 */ 545 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 546 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 547 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 548 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 549 break; 550 case 1: 551 /* New Scheme: OMAP4+ */ 552 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 553 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 554 OMAP_UART_MVR_MAJ_SHIFT; 555 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 556 break; 557 default: 558 dev_warn(up->port.dev, 559 "Unknown revision, defaulting to highest\n"); 560 /* highest possible revision */ 561 major = 0xff; 562 minor = 0xff; 563 } 564 /* normalize revision for the driver */ 565 revision = UART_BUILD_REVISION(major, minor); 566 567 switch (revision) { 568 case OMAP_UART_REV_46: 569 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 570 break; 571 case OMAP_UART_REV_52: 572 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 573 OMAP_UART_WER_HAS_TX_WAKEUP; 574 break; 575 case OMAP_UART_REV_63: 576 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 577 OMAP_UART_WER_HAS_TX_WAKEUP; 578 break; 579 default: 580 break; 581 } 582 583 /* 584 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 585 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 586 * to enable errata workaround. 587 */ 588 if (soc_device_match(k3_soc_devices)) 589 priv->habit &= ~UART_HAS_RHR_IT_DIS; 590 } 591 592 static void omap8250_uart_qos_work(struct work_struct *work) 593 { 594 struct omap8250_priv *priv; 595 596 priv = container_of(work, struct omap8250_priv, qos_work); 597 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 598 } 599 600 #ifdef CONFIG_SERIAL_8250_DMA 601 static int omap_8250_dma_handle_irq(struct uart_port *port); 602 #endif 603 604 static irqreturn_t omap8250_irq(int irq, void *dev_id) 605 { 606 struct uart_port *port = dev_id; 607 struct omap8250_priv *priv = port->private_data; 608 struct uart_8250_port *up = up_to_u8250p(port); 609 unsigned int iir, lsr; 610 int ret; 611 612 #ifdef CONFIG_SERIAL_8250_DMA 613 if (up->dma) { 614 ret = omap_8250_dma_handle_irq(port); 615 return IRQ_RETVAL(ret); 616 } 617 #endif 618 619 serial8250_rpm_get(up); 620 lsr = serial_port_in(port, UART_LSR); 621 iir = serial_port_in(port, UART_IIR); 622 ret = serial8250_handle_irq(port, iir); 623 624 /* 625 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 626 * FIFO has been drained, in which case a dummy read of RX FIFO 627 * is required to clear RX TIMEOUT condition. 628 */ 629 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 630 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 631 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 632 serial_port_in(port, UART_RX); 633 } 634 635 /* Stop processing interrupts on input overrun */ 636 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 637 unsigned long delay; 638 639 up->ier = port->serial_in(port, UART_IER); 640 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 641 port->ops->stop_rx(port); 642 } else { 643 /* Keep restarting the timer until 644 * the input overrun subsides. 645 */ 646 cancel_delayed_work(&up->overrun_backoff); 647 } 648 649 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 650 schedule_delayed_work(&up->overrun_backoff, delay); 651 } 652 653 serial8250_rpm_put(up); 654 655 return IRQ_RETVAL(ret); 656 } 657 658 static int omap_8250_startup(struct uart_port *port) 659 { 660 struct uart_8250_port *up = up_to_u8250p(port); 661 struct omap8250_priv *priv = port->private_data; 662 int ret; 663 664 if (priv->wakeirq) { 665 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 666 if (ret) 667 return ret; 668 } 669 670 pm_runtime_get_sync(port->dev); 671 672 up->mcr = 0; 673 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 674 675 serial_out(up, UART_LCR, UART_LCR_WLEN8); 676 677 up->lsr_saved_flags = 0; 678 up->msr_saved_flags = 0; 679 680 /* Disable DMA for console UART */ 681 if (uart_console(port)) 682 up->dma = NULL; 683 684 if (up->dma) { 685 ret = serial8250_request_dma(up); 686 if (ret) { 687 dev_warn_ratelimited(port->dev, 688 "failed to request DMA\n"); 689 up->dma = NULL; 690 } 691 } 692 693 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 694 dev_name(port->dev), port); 695 if (ret < 0) 696 goto err; 697 698 up->ier = UART_IER_RLSI | UART_IER_RDI; 699 serial_out(up, UART_IER, up->ier); 700 701 #ifdef CONFIG_PM 702 up->capabilities |= UART_CAP_RPM; 703 #endif 704 705 /* Enable module level wake up */ 706 priv->wer = OMAP_UART_WER_MOD_WKUP; 707 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 708 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 709 serial_out(up, UART_OMAP_WER, priv->wer); 710 711 if (up->dma && !(priv->habit & UART_HAS_EFR2)) 712 up->dma->rx_dma(up); 713 714 pm_runtime_mark_last_busy(port->dev); 715 pm_runtime_put_autosuspend(port->dev); 716 return 0; 717 err: 718 pm_runtime_mark_last_busy(port->dev); 719 pm_runtime_put_autosuspend(port->dev); 720 dev_pm_clear_wake_irq(port->dev); 721 return ret; 722 } 723 724 static void omap_8250_shutdown(struct uart_port *port) 725 { 726 struct uart_8250_port *up = up_to_u8250p(port); 727 struct omap8250_priv *priv = port->private_data; 728 729 flush_work(&priv->qos_work); 730 if (up->dma) 731 omap_8250_rx_dma_flush(up); 732 733 pm_runtime_get_sync(port->dev); 734 735 serial_out(up, UART_OMAP_WER, 0); 736 if (priv->habit & UART_HAS_EFR2) 737 serial_out(up, UART_OMAP_EFR2, 0x0); 738 739 up->ier = 0; 740 serial_out(up, UART_IER, 0); 741 742 if (up->dma) 743 serial8250_release_dma(up); 744 745 /* 746 * Disable break condition and FIFOs 747 */ 748 if (up->lcr & UART_LCR_SBC) 749 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 750 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 751 752 pm_runtime_mark_last_busy(port->dev); 753 pm_runtime_put_autosuspend(port->dev); 754 free_irq(port->irq, port); 755 dev_pm_clear_wake_irq(port->dev); 756 } 757 758 static void omap_8250_throttle(struct uart_port *port) 759 { 760 struct omap8250_priv *priv = port->private_data; 761 unsigned long flags; 762 763 pm_runtime_get_sync(port->dev); 764 765 spin_lock_irqsave(&port->lock, flags); 766 port->ops->stop_rx(port); 767 priv->throttled = true; 768 spin_unlock_irqrestore(&port->lock, flags); 769 770 pm_runtime_mark_last_busy(port->dev); 771 pm_runtime_put_autosuspend(port->dev); 772 } 773 774 static void omap_8250_unthrottle(struct uart_port *port) 775 { 776 struct omap8250_priv *priv = port->private_data; 777 struct uart_8250_port *up = up_to_u8250p(port); 778 unsigned long flags; 779 780 pm_runtime_get_sync(port->dev); 781 782 spin_lock_irqsave(&port->lock, flags); 783 priv->throttled = false; 784 if (up->dma) 785 up->dma->rx_dma(up); 786 up->ier |= UART_IER_RLSI | UART_IER_RDI; 787 port->read_status_mask |= UART_LSR_DR; 788 serial_out(up, UART_IER, up->ier); 789 spin_unlock_irqrestore(&port->lock, flags); 790 791 pm_runtime_mark_last_busy(port->dev); 792 pm_runtime_put_autosuspend(port->dev); 793 } 794 795 #ifdef CONFIG_SERIAL_8250_DMA 796 static int omap_8250_rx_dma(struct uart_8250_port *p); 797 798 /* Must be called while priv->rx_dma_lock is held */ 799 static void __dma_rx_do_complete(struct uart_8250_port *p) 800 { 801 struct uart_8250_dma *dma = p->dma; 802 struct tty_port *tty_port = &p->port.state->port; 803 struct omap8250_priv *priv = p->port.private_data; 804 struct dma_chan *rxchan = dma->rxchan; 805 dma_cookie_t cookie; 806 struct dma_tx_state state; 807 int count; 808 int ret; 809 u32 reg; 810 811 if (!dma->rx_running) 812 goto out; 813 814 cookie = dma->rx_cookie; 815 dma->rx_running = 0; 816 817 /* Re-enable RX FIFO interrupt now that transfer is complete */ 818 if (priv->habit & UART_HAS_RHR_IT_DIS) { 819 reg = serial_in(p, UART_OMAP_IER2); 820 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 821 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 822 } 823 824 dmaengine_tx_status(rxchan, cookie, &state); 825 826 count = dma->rx_size - state.residue + state.in_flight_bytes; 827 if (count < dma->rx_size) { 828 dmaengine_terminate_async(rxchan); 829 830 /* 831 * Poll for teardown to complete which guarantees in 832 * flight data is drained. 833 */ 834 if (state.in_flight_bytes) { 835 int poll_count = 25; 836 837 while (dmaengine_tx_status(rxchan, cookie, NULL) && 838 poll_count--) 839 cpu_relax(); 840 841 if (poll_count == -1) 842 dev_err(p->port.dev, "teardown incomplete\n"); 843 } 844 } 845 if (!count) 846 goto out; 847 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 848 849 p->port.icount.rx += ret; 850 p->port.icount.buf_overrun += count - ret; 851 out: 852 853 tty_flip_buffer_push(tty_port); 854 } 855 856 static void __dma_rx_complete(void *param) 857 { 858 struct uart_8250_port *p = param; 859 struct omap8250_priv *priv = p->port.private_data; 860 struct uart_8250_dma *dma = p->dma; 861 struct dma_tx_state state; 862 unsigned long flags; 863 864 spin_lock_irqsave(&p->port.lock, flags); 865 866 /* 867 * If the tx status is not DMA_COMPLETE, then this is a delayed 868 * completion callback. A previous RX timeout flush would have 869 * already pushed the data, so exit. 870 */ 871 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 872 DMA_COMPLETE) { 873 spin_unlock_irqrestore(&p->port.lock, flags); 874 return; 875 } 876 __dma_rx_do_complete(p); 877 if (!priv->throttled) { 878 p->ier |= UART_IER_RLSI | UART_IER_RDI; 879 serial_out(p, UART_IER, p->ier); 880 if (!(priv->habit & UART_HAS_EFR2)) 881 omap_8250_rx_dma(p); 882 } 883 884 spin_unlock_irqrestore(&p->port.lock, flags); 885 } 886 887 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 888 { 889 struct omap8250_priv *priv = p->port.private_data; 890 struct uart_8250_dma *dma = p->dma; 891 struct dma_tx_state state; 892 unsigned long flags; 893 int ret; 894 895 spin_lock_irqsave(&priv->rx_dma_lock, flags); 896 897 if (!dma->rx_running) { 898 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 899 return; 900 } 901 902 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 903 if (ret == DMA_IN_PROGRESS) { 904 ret = dmaengine_pause(dma->rxchan); 905 if (WARN_ON_ONCE(ret)) 906 priv->rx_dma_broken = true; 907 } 908 __dma_rx_do_complete(p); 909 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 910 } 911 912 static int omap_8250_rx_dma(struct uart_8250_port *p) 913 { 914 struct omap8250_priv *priv = p->port.private_data; 915 struct uart_8250_dma *dma = p->dma; 916 int err = 0; 917 struct dma_async_tx_descriptor *desc; 918 unsigned long flags; 919 u32 reg; 920 921 if (priv->rx_dma_broken) 922 return -EINVAL; 923 924 spin_lock_irqsave(&priv->rx_dma_lock, flags); 925 926 if (dma->rx_running) { 927 enum dma_status state; 928 929 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 930 if (state == DMA_COMPLETE) { 931 /* 932 * Disable RX interrupts to allow RX DMA completion 933 * callback to run. 934 */ 935 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 936 serial_out(p, UART_IER, p->ier); 937 } 938 goto out; 939 } 940 941 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 942 dma->rx_size, DMA_DEV_TO_MEM, 943 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 944 if (!desc) { 945 err = -EBUSY; 946 goto out; 947 } 948 949 dma->rx_running = 1; 950 desc->callback = __dma_rx_complete; 951 desc->callback_param = p; 952 953 dma->rx_cookie = dmaengine_submit(desc); 954 955 /* 956 * Disable RX FIFO interrupt while RX DMA is enabled, else 957 * spurious interrupt may be raised when data is in the RX FIFO 958 * but is yet to be drained by DMA. 959 */ 960 if (priv->habit & UART_HAS_RHR_IT_DIS) { 961 reg = serial_in(p, UART_OMAP_IER2); 962 reg |= UART_OMAP_IER2_RHR_IT_DIS; 963 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 964 } 965 966 dma_async_issue_pending(dma->rxchan); 967 out: 968 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 969 return err; 970 } 971 972 static int omap_8250_tx_dma(struct uart_8250_port *p); 973 974 static void omap_8250_dma_tx_complete(void *param) 975 { 976 struct uart_8250_port *p = param; 977 struct uart_8250_dma *dma = p->dma; 978 struct circ_buf *xmit = &p->port.state->xmit; 979 unsigned long flags; 980 bool en_thri = false; 981 struct omap8250_priv *priv = p->port.private_data; 982 983 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 984 UART_XMIT_SIZE, DMA_TO_DEVICE); 985 986 spin_lock_irqsave(&p->port.lock, flags); 987 988 dma->tx_running = 0; 989 990 uart_xmit_advance(&p->port, dma->tx_size); 991 992 if (priv->delayed_restore) { 993 priv->delayed_restore = 0; 994 omap8250_restore_regs(p); 995 } 996 997 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 998 uart_write_wakeup(&p->port); 999 1000 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1001 int ret; 1002 1003 ret = omap_8250_tx_dma(p); 1004 if (ret) 1005 en_thri = true; 1006 } else if (p->capabilities & UART_CAP_RPM) { 1007 en_thri = true; 1008 } 1009 1010 if (en_thri) { 1011 dma->tx_err = 1; 1012 serial8250_set_THRI(p); 1013 } 1014 1015 spin_unlock_irqrestore(&p->port.lock, flags); 1016 } 1017 1018 static int omap_8250_tx_dma(struct uart_8250_port *p) 1019 { 1020 struct uart_8250_dma *dma = p->dma; 1021 struct omap8250_priv *priv = p->port.private_data; 1022 struct circ_buf *xmit = &p->port.state->xmit; 1023 struct dma_async_tx_descriptor *desc; 1024 unsigned int skip_byte = 0; 1025 int ret; 1026 1027 if (dma->tx_running) 1028 return 0; 1029 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1030 1031 /* 1032 * Even if no data, we need to return an error for the two cases 1033 * below so serial8250_tx_chars() is invoked and properly clears 1034 * THRI and/or runtime suspend. 1035 */ 1036 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1037 ret = -EBUSY; 1038 goto err; 1039 } 1040 serial8250_clear_THRI(p); 1041 return 0; 1042 } 1043 1044 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1045 if (priv->habit & OMAP_DMA_TX_KICK) { 1046 u8 tx_lvl; 1047 1048 /* 1049 * We need to put the first byte into the FIFO in order to start 1050 * the DMA transfer. For transfers smaller than four bytes we 1051 * don't bother doing DMA at all. It seem not matter if there 1052 * are still bytes in the FIFO from the last transfer (in case 1053 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1054 * leaving the FIFO seem not to trigger the DMA transfer. It is 1055 * really the byte that we put into the FIFO. 1056 * If the FIFO is already full then we most likely got here from 1057 * omap_8250_dma_tx_complete(). And this means the DMA engine 1058 * just completed its work. We don't have to wait the complete 1059 * 86us at 115200,8n1 but around 60us (not to mention lower 1060 * baudrates). So in that case we take the interrupt and try 1061 * again with an empty FIFO. 1062 */ 1063 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1064 if (tx_lvl == p->tx_loadsz) { 1065 ret = -EBUSY; 1066 goto err; 1067 } 1068 if (dma->tx_size < 4) { 1069 ret = -EINVAL; 1070 goto err; 1071 } 1072 skip_byte = 1; 1073 } 1074 1075 desc = dmaengine_prep_slave_single(dma->txchan, 1076 dma->tx_addr + xmit->tail + skip_byte, 1077 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1078 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1079 if (!desc) { 1080 ret = -EBUSY; 1081 goto err; 1082 } 1083 1084 dma->tx_running = 1; 1085 1086 desc->callback = omap_8250_dma_tx_complete; 1087 desc->callback_param = p; 1088 1089 dma->tx_cookie = dmaengine_submit(desc); 1090 1091 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1092 UART_XMIT_SIZE, DMA_TO_DEVICE); 1093 1094 dma_async_issue_pending(dma->txchan); 1095 if (dma->tx_err) 1096 dma->tx_err = 0; 1097 1098 serial8250_clear_THRI(p); 1099 if (skip_byte) 1100 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1101 return 0; 1102 err: 1103 dma->tx_err = 1; 1104 return ret; 1105 } 1106 1107 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1108 { 1109 switch (iir & 0x3f) { 1110 case UART_IIR_RLSI: 1111 case UART_IIR_RX_TIMEOUT: 1112 case UART_IIR_RDI: 1113 omap_8250_rx_dma_flush(up); 1114 return true; 1115 } 1116 return omap_8250_rx_dma(up); 1117 } 1118 1119 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status) 1120 { 1121 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1122 (iir & UART_IIR_RDI)) { 1123 if (handle_rx_dma(up, iir)) { 1124 status = serial8250_rx_chars(up, status); 1125 omap_8250_rx_dma(up); 1126 } 1127 } 1128 1129 return status; 1130 } 1131 1132 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1133 u16 status) 1134 { 1135 /* 1136 * Queue a new transfer if FIFO has data. 1137 */ 1138 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1139 (up->ier & UART_IER_RDI)) { 1140 omap_8250_rx_dma(up); 1141 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1142 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1143 /* 1144 * Disable RX timeout, read IIR to clear 1145 * current timeout condition, clear EFR2 to 1146 * periodic timeouts, re-enable interrupts. 1147 */ 1148 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1149 serial_out(up, UART_IER, up->ier); 1150 omap_8250_rx_dma_flush(up); 1151 serial_in(up, UART_IIR); 1152 serial_out(up, UART_OMAP_EFR2, 0x0); 1153 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1154 serial_out(up, UART_IER, up->ier); 1155 } 1156 } 1157 1158 /* 1159 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1160 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1161 * use the default routine in the non-DMA case and this one for with DMA. 1162 */ 1163 static int omap_8250_dma_handle_irq(struct uart_port *port) 1164 { 1165 struct uart_8250_port *up = up_to_u8250p(port); 1166 struct omap8250_priv *priv = up->port.private_data; 1167 u16 status; 1168 u8 iir; 1169 1170 serial8250_rpm_get(up); 1171 1172 iir = serial_port_in(port, UART_IIR); 1173 if (iir & UART_IIR_NO_INT) { 1174 serial8250_rpm_put(up); 1175 return IRQ_HANDLED; 1176 } 1177 1178 spin_lock(&port->lock); 1179 1180 status = serial_port_in(port, UART_LSR); 1181 1182 if (priv->habit & UART_HAS_EFR2) 1183 am654_8250_handle_rx_dma(up, iir, status); 1184 else 1185 status = omap_8250_handle_rx_dma(up, iir, status); 1186 1187 serial8250_modem_status(up); 1188 if (status & UART_LSR_THRE && up->dma->tx_err) { 1189 if (uart_tx_stopped(&up->port) || 1190 uart_circ_empty(&up->port.state->xmit)) { 1191 up->dma->tx_err = 0; 1192 serial8250_tx_chars(up); 1193 } else { 1194 /* 1195 * try again due to an earlier failer which 1196 * might have been resolved by now. 1197 */ 1198 if (omap_8250_tx_dma(up)) 1199 serial8250_tx_chars(up); 1200 } 1201 } 1202 1203 uart_unlock_and_check_sysrq(port); 1204 1205 serial8250_rpm_put(up); 1206 return 1; 1207 } 1208 1209 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1210 { 1211 return false; 1212 } 1213 1214 #else 1215 1216 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1217 { 1218 return -EINVAL; 1219 } 1220 #endif 1221 1222 static int omap8250_no_handle_irq(struct uart_port *port) 1223 { 1224 /* IRQ has not been requested but handling irq? */ 1225 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1226 return 0; 1227 } 1228 1229 static struct omap8250_dma_params am654_dma = { 1230 .rx_size = SZ_2K, 1231 .rx_trigger = 1, 1232 .tx_trigger = TX_TRIGGER, 1233 }; 1234 1235 static struct omap8250_dma_params am33xx_dma = { 1236 .rx_size = RX_TRIGGER, 1237 .rx_trigger = RX_TRIGGER, 1238 .tx_trigger = TX_TRIGGER, 1239 }; 1240 1241 static struct omap8250_platdata am654_platdata = { 1242 .dma_params = &am654_dma, 1243 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1244 UART_RX_TIMEOUT_QUIRK, 1245 }; 1246 1247 static struct omap8250_platdata am33xx_platdata = { 1248 .dma_params = &am33xx_dma, 1249 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1250 }; 1251 1252 static struct omap8250_platdata omap4_platdata = { 1253 .dma_params = &am33xx_dma, 1254 .habit = UART_ERRATA_CLOCK_DISABLE, 1255 }; 1256 1257 static const struct of_device_id omap8250_dt_ids[] = { 1258 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1259 { .compatible = "ti,omap2-uart" }, 1260 { .compatible = "ti,omap3-uart" }, 1261 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1262 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1263 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1264 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1265 {}, 1266 }; 1267 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1268 1269 static int omap8250_probe(struct platform_device *pdev) 1270 { 1271 struct device_node *np = pdev->dev.of_node; 1272 struct omap8250_priv *priv; 1273 const struct omap8250_platdata *pdata; 1274 struct uart_8250_port up; 1275 struct resource *regs; 1276 void __iomem *membase; 1277 int irq, ret; 1278 1279 irq = platform_get_irq(pdev, 0); 1280 if (irq < 0) 1281 return irq; 1282 1283 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1284 if (!regs) { 1285 dev_err(&pdev->dev, "missing registers\n"); 1286 return -EINVAL; 1287 } 1288 1289 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1290 if (!priv) 1291 return -ENOMEM; 1292 1293 membase = devm_ioremap(&pdev->dev, regs->start, 1294 resource_size(regs)); 1295 if (!membase) 1296 return -ENODEV; 1297 1298 memset(&up, 0, sizeof(up)); 1299 up.port.dev = &pdev->dev; 1300 up.port.mapbase = regs->start; 1301 up.port.membase = membase; 1302 up.port.irq = irq; 1303 /* 1304 * It claims to be 16C750 compatible however it is a little different. 1305 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1306 * have) is enabled via EFR instead of MCR. The type is set here 8250 1307 * just to get things going. UNKNOWN does not work for a few reasons and 1308 * we don't need our own type since we don't use 8250's set_termios() 1309 * or pm callback. 1310 */ 1311 up.port.type = PORT_8250; 1312 up.port.iotype = UPIO_MEM; 1313 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1314 UPF_HARD_FLOW; 1315 up.port.private_data = priv; 1316 1317 up.port.regshift = 2; 1318 up.port.fifosize = 64; 1319 up.tx_loadsz = 64; 1320 up.capabilities = UART_CAP_FIFO; 1321 #ifdef CONFIG_PM 1322 /* 1323 * Runtime PM is mostly transparent. However to do it right we need to a 1324 * TX empty interrupt before we can put the device to auto idle. So if 1325 * PM is not enabled we don't add that flag and can spare that one extra 1326 * interrupt in the TX path. 1327 */ 1328 up.capabilities |= UART_CAP_RPM; 1329 #endif 1330 up.port.set_termios = omap_8250_set_termios; 1331 up.port.set_mctrl = omap8250_set_mctrl; 1332 up.port.pm = omap_8250_pm; 1333 up.port.startup = omap_8250_startup; 1334 up.port.shutdown = omap_8250_shutdown; 1335 up.port.throttle = omap_8250_throttle; 1336 up.port.unthrottle = omap_8250_unthrottle; 1337 up.port.rs485_config = serial8250_em485_config; 1338 up.port.rs485_supported = serial8250_em485_supported; 1339 up.rs485_start_tx = serial8250_em485_start_tx; 1340 up.rs485_stop_tx = serial8250_em485_stop_tx; 1341 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1342 1343 ret = of_alias_get_id(np, "serial"); 1344 if (ret < 0) { 1345 dev_err(&pdev->dev, "failed to get alias\n"); 1346 return ret; 1347 } 1348 up.port.line = ret; 1349 1350 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1351 struct clk *clk; 1352 1353 clk = devm_clk_get(&pdev->dev, NULL); 1354 if (IS_ERR(clk)) { 1355 if (PTR_ERR(clk) == -EPROBE_DEFER) 1356 return -EPROBE_DEFER; 1357 } else { 1358 up.port.uartclk = clk_get_rate(clk); 1359 } 1360 } 1361 1362 if (of_property_read_u32(np, "overrun-throttle-ms", 1363 &up.overrun_backoff_time_ms) != 0) 1364 up.overrun_backoff_time_ms = 0; 1365 1366 priv->wakeirq = irq_of_parse_and_map(np, 1); 1367 1368 pdata = of_device_get_match_data(&pdev->dev); 1369 if (pdata) 1370 priv->habit |= pdata->habit; 1371 1372 if (!up.port.uartclk) { 1373 up.port.uartclk = DEFAULT_CLK_SPEED; 1374 dev_warn(&pdev->dev, 1375 "No clock speed specified: using default: %d\n", 1376 DEFAULT_CLK_SPEED); 1377 } 1378 1379 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1380 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1381 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1382 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1383 1384 spin_lock_init(&priv->rx_dma_lock); 1385 1386 device_init_wakeup(&pdev->dev, true); 1387 pm_runtime_enable(&pdev->dev); 1388 pm_runtime_use_autosuspend(&pdev->dev); 1389 1390 /* 1391 * Disable runtime PM until autosuspend delay unless specifically 1392 * enabled by the user via sysfs. This is the historic way to 1393 * prevent an unsafe default policy with lossy characters on wake-up. 1394 * For serdev devices this is not needed, the policy can be managed by 1395 * the serdev driver. 1396 */ 1397 if (!of_get_available_child_count(pdev->dev.of_node)) 1398 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1399 1400 pm_runtime_irq_safe(&pdev->dev); 1401 1402 pm_runtime_get_sync(&pdev->dev); 1403 1404 omap_serial_fill_features_erratas(&up, priv); 1405 up.port.handle_irq = omap8250_no_handle_irq; 1406 priv->rx_trigger = RX_TRIGGER; 1407 priv->tx_trigger = TX_TRIGGER; 1408 #ifdef CONFIG_SERIAL_8250_DMA 1409 /* 1410 * Oh DMA support. If there are no DMA properties in the DT then 1411 * we will fall back to a generic DMA channel which does not 1412 * really work here. To ensure that we do not get a generic DMA 1413 * channel assigned, we have the the_no_dma_filter_fn() here. 1414 * To avoid "failed to request DMA" messages we check for DMA 1415 * properties in DT. 1416 */ 1417 ret = of_property_count_strings(np, "dma-names"); 1418 if (ret == 2) { 1419 struct omap8250_dma_params *dma_params = NULL; 1420 1421 up.dma = &priv->omap8250_dma; 1422 up.dma->fn = the_no_dma_filter_fn; 1423 up.dma->tx_dma = omap_8250_tx_dma; 1424 up.dma->rx_dma = omap_8250_rx_dma; 1425 if (pdata) 1426 dma_params = pdata->dma_params; 1427 1428 if (dma_params) { 1429 up.dma->rx_size = dma_params->rx_size; 1430 up.dma->rxconf.src_maxburst = dma_params->rx_trigger; 1431 up.dma->txconf.dst_maxburst = dma_params->tx_trigger; 1432 priv->rx_trigger = dma_params->rx_trigger; 1433 priv->tx_trigger = dma_params->tx_trigger; 1434 } else { 1435 up.dma->rx_size = RX_TRIGGER; 1436 up.dma->rxconf.src_maxburst = RX_TRIGGER; 1437 up.dma->txconf.dst_maxburst = TX_TRIGGER; 1438 } 1439 } 1440 #endif 1441 ret = serial8250_register_8250_port(&up); 1442 if (ret < 0) { 1443 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1444 goto err; 1445 } 1446 priv->line = ret; 1447 platform_set_drvdata(pdev, priv); 1448 pm_runtime_mark_last_busy(&pdev->dev); 1449 pm_runtime_put_autosuspend(&pdev->dev); 1450 return 0; 1451 err: 1452 pm_runtime_dont_use_autosuspend(&pdev->dev); 1453 pm_runtime_put_sync(&pdev->dev); 1454 pm_runtime_disable(&pdev->dev); 1455 return ret; 1456 } 1457 1458 static int omap8250_remove(struct platform_device *pdev) 1459 { 1460 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1461 1462 pm_runtime_dont_use_autosuspend(&pdev->dev); 1463 pm_runtime_put_sync(&pdev->dev); 1464 pm_runtime_disable(&pdev->dev); 1465 serial8250_unregister_port(priv->line); 1466 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1467 device_init_wakeup(&pdev->dev, false); 1468 return 0; 1469 } 1470 1471 #ifdef CONFIG_PM_SLEEP 1472 static int omap8250_prepare(struct device *dev) 1473 { 1474 struct omap8250_priv *priv = dev_get_drvdata(dev); 1475 1476 if (!priv) 1477 return 0; 1478 priv->is_suspending = true; 1479 return 0; 1480 } 1481 1482 static void omap8250_complete(struct device *dev) 1483 { 1484 struct omap8250_priv *priv = dev_get_drvdata(dev); 1485 1486 if (!priv) 1487 return; 1488 priv->is_suspending = false; 1489 } 1490 1491 static int omap8250_suspend(struct device *dev) 1492 { 1493 struct omap8250_priv *priv = dev_get_drvdata(dev); 1494 struct uart_8250_port *up = serial8250_get_port(priv->line); 1495 1496 serial8250_suspend_port(priv->line); 1497 1498 pm_runtime_get_sync(dev); 1499 if (!device_may_wakeup(dev)) 1500 priv->wer = 0; 1501 serial_out(up, UART_OMAP_WER, priv->wer); 1502 pm_runtime_mark_last_busy(dev); 1503 pm_runtime_put_autosuspend(dev); 1504 1505 flush_work(&priv->qos_work); 1506 return 0; 1507 } 1508 1509 static int omap8250_resume(struct device *dev) 1510 { 1511 struct omap8250_priv *priv = dev_get_drvdata(dev); 1512 1513 serial8250_resume_port(priv->line); 1514 return 0; 1515 } 1516 #else 1517 #define omap8250_prepare NULL 1518 #define omap8250_complete NULL 1519 #endif 1520 1521 #ifdef CONFIG_PM 1522 static int omap8250_lost_context(struct uart_8250_port *up) 1523 { 1524 u32 val; 1525 1526 val = serial_in(up, UART_OMAP_SCR); 1527 /* 1528 * If we lose context, then SCR is set to its reset value of zero. 1529 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1530 * among other bits, to never set the register back to zero again. 1531 */ 1532 if (!val) 1533 return 1; 1534 return 0; 1535 } 1536 1537 /* TODO: in future, this should happen via API in drivers/reset/ */ 1538 static int omap8250_soft_reset(struct device *dev) 1539 { 1540 struct omap8250_priv *priv = dev_get_drvdata(dev); 1541 struct uart_8250_port *up = serial8250_get_port(priv->line); 1542 int timeout = 100; 1543 int sysc; 1544 int syss; 1545 1546 /* 1547 * At least on omap4, unused uarts may not idle after reset without 1548 * a basic scr dma configuration even with no dma in use. The 1549 * module clkctrl status bits will be 1 instead of 3 blocking idle 1550 * for the whole clockdomain. The softreset below will clear scr, 1551 * and we restore it on resume so this is safe to do on all SoCs 1552 * needing omap8250_soft_reset() quirk. Do it in two writes as 1553 * recommended in the comment for omap8250_update_scr(). 1554 */ 1555 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1556 serial_out(up, UART_OMAP_SCR, 1557 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1558 1559 sysc = serial_in(up, UART_OMAP_SYSC); 1560 1561 /* softreset the UART */ 1562 sysc |= OMAP_UART_SYSC_SOFTRESET; 1563 serial_out(up, UART_OMAP_SYSC, sysc); 1564 1565 /* By experiments, 1us enough for reset complete on AM335x */ 1566 do { 1567 udelay(1); 1568 syss = serial_in(up, UART_OMAP_SYSS); 1569 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1570 1571 if (!timeout) { 1572 dev_err(dev, "timed out waiting for reset done\n"); 1573 return -ETIMEDOUT; 1574 } 1575 1576 return 0; 1577 } 1578 1579 static int omap8250_runtime_suspend(struct device *dev) 1580 { 1581 struct omap8250_priv *priv = dev_get_drvdata(dev); 1582 struct uart_8250_port *up; 1583 1584 /* In case runtime-pm tries this before we are setup */ 1585 if (!priv) 1586 return 0; 1587 1588 up = serial8250_get_port(priv->line); 1589 /* 1590 * When using 'no_console_suspend', the console UART must not be 1591 * suspended. Since driver suspend is managed by runtime suspend, 1592 * preventing runtime suspend (by returning error) will keep device 1593 * active during suspend. 1594 */ 1595 if (priv->is_suspending && !console_suspend_enabled) { 1596 if (uart_console(&up->port)) 1597 return -EBUSY; 1598 } 1599 1600 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1601 int ret; 1602 1603 ret = omap8250_soft_reset(dev); 1604 if (ret) 1605 return ret; 1606 1607 /* Restore to UART mode after reset (for wakeup) */ 1608 omap8250_update_mdr1(up, priv); 1609 /* Restore wakeup enable register */ 1610 serial_out(up, UART_OMAP_WER, priv->wer); 1611 } 1612 1613 if (up->dma && up->dma->rxchan) 1614 omap_8250_rx_dma_flush(up); 1615 1616 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1617 schedule_work(&priv->qos_work); 1618 1619 return 0; 1620 } 1621 1622 static int omap8250_runtime_resume(struct device *dev) 1623 { 1624 struct omap8250_priv *priv = dev_get_drvdata(dev); 1625 struct uart_8250_port *up; 1626 1627 /* In case runtime-pm tries this before we are setup */ 1628 if (!priv) 1629 return 0; 1630 1631 up = serial8250_get_port(priv->line); 1632 1633 if (omap8250_lost_context(up)) 1634 omap8250_restore_regs(up); 1635 1636 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) 1637 omap_8250_rx_dma(up); 1638 1639 priv->latency = priv->calc_latency; 1640 schedule_work(&priv->qos_work); 1641 return 0; 1642 } 1643 #endif 1644 1645 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1646 static int __init omap8250_console_fixup(void) 1647 { 1648 char *omap_str; 1649 char *options; 1650 u8 idx; 1651 1652 if (strstr(boot_command_line, "console=ttyS")) 1653 /* user set a ttyS based name for the console */ 1654 return 0; 1655 1656 omap_str = strstr(boot_command_line, "console=ttyO"); 1657 if (!omap_str) 1658 /* user did not set ttyO based console, so we don't care */ 1659 return 0; 1660 1661 omap_str += 12; 1662 if ('0' <= *omap_str && *omap_str <= '9') 1663 idx = *omap_str - '0'; 1664 else 1665 return 0; 1666 1667 omap_str++; 1668 if (omap_str[0] == ',') { 1669 omap_str++; 1670 options = omap_str; 1671 } else { 1672 options = NULL; 1673 } 1674 1675 add_preferred_console("ttyS", idx, options); 1676 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1677 idx, idx); 1678 pr_err("This ensures that you still see kernel messages. Please\n"); 1679 pr_err("update your kernel commandline.\n"); 1680 return 0; 1681 } 1682 console_initcall(omap8250_console_fixup); 1683 #endif 1684 1685 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1686 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1687 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1688 omap8250_runtime_resume, NULL) 1689 .prepare = omap8250_prepare, 1690 .complete = omap8250_complete, 1691 }; 1692 1693 static struct platform_driver omap8250_platform_driver = { 1694 .driver = { 1695 .name = "omap8250", 1696 .pm = &omap8250_dev_pm_ops, 1697 .of_match_table = omap8250_dt_ids, 1698 }, 1699 .probe = omap8250_probe, 1700 .remove = omap8250_remove, 1701 }; 1702 module_platform_driver(omap8250_platform_driver); 1703 1704 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1705 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1706 MODULE_LICENSE("GPL v2"); 1707