1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * 8250-core based driver for the OMAP internal UART
4  *
5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
6  *
7  * Copyright (C) 2014 Sebastian Andrzej Siewior
8  *
9  */
10 
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/io.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_irq.h>
24 #include <linux/delay.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/console.h>
27 #include <linux/pm_qos.h>
28 #include <linux/pm_wakeirq.h>
29 #include <linux/dma-mapping.h>
30 
31 #include "8250.h"
32 
33 #define DEFAULT_CLK_SPEED	48000000
34 
35 #define UART_ERRATA_i202_MDR1_ACCESS	(1 << 0)
36 #define OMAP_UART_WER_HAS_TX_WAKEUP	(1 << 1)
37 #define OMAP_DMA_TX_KICK		(1 << 2)
38 /*
39  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
40  * The same errata is applicable to AM335x and DRA7x processors too.
41  */
42 #define UART_ERRATA_CLOCK_DISABLE	(1 << 3)
43 
44 #define OMAP_UART_FCR_RX_TRIG		6
45 #define OMAP_UART_FCR_TX_TRIG		4
46 
47 /* SCR register bitmasks */
48 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK	(1 << 7)
49 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK	(1 << 6)
50 #define OMAP_UART_SCR_TX_EMPTY			(1 << 3)
51 #define OMAP_UART_SCR_DMAMODE_MASK		(3 << 1)
52 #define OMAP_UART_SCR_DMAMODE_1			(1 << 1)
53 #define OMAP_UART_SCR_DMAMODE_CTL		(1 << 0)
54 
55 /* MVR register bitmasks */
56 #define OMAP_UART_MVR_SCHEME_SHIFT	30
57 #define OMAP_UART_LEGACY_MVR_MAJ_MASK	0xf0
58 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT	4
59 #define OMAP_UART_LEGACY_MVR_MIN_MASK	0x0f
60 #define OMAP_UART_MVR_MAJ_MASK		0x700
61 #define OMAP_UART_MVR_MAJ_SHIFT		8
62 #define OMAP_UART_MVR_MIN_MASK		0x3f
63 
64 /* SYSC register bitmasks */
65 #define OMAP_UART_SYSC_SOFTRESET	(1 << 1)
66 
67 /* SYSS register bitmasks */
68 #define OMAP_UART_SYSS_RESETDONE	(1 << 0)
69 
70 #define UART_TI752_TLR_TX	0
71 #define UART_TI752_TLR_RX	4
72 
73 #define TRIGGER_TLR_MASK(x)	((x & 0x3c) >> 2)
74 #define TRIGGER_FCR_MASK(x)	(x & 3)
75 
76 /* Enable XON/XOFF flow control on output */
77 #define OMAP_UART_SW_TX		0x08
78 /* Enable XON/XOFF flow control on input */
79 #define OMAP_UART_SW_RX		0x02
80 
81 #define OMAP_UART_WER_MOD_WKUP	0x7f
82 #define OMAP_UART_TX_WAKEUP_EN	(1 << 7)
83 
84 #define TX_TRIGGER	1
85 #define RX_TRIGGER	48
86 
87 #define OMAP_UART_TCR_RESTORE(x)	((x / 4) << 4)
88 #define OMAP_UART_TCR_HALT(x)		((x / 4) << 0)
89 
90 #define UART_BUILD_REVISION(x, y)	(((x) << 8) | (y))
91 
92 #define OMAP_UART_REV_46 0x0406
93 #define OMAP_UART_REV_52 0x0502
94 #define OMAP_UART_REV_63 0x0603
95 
96 struct omap8250_priv {
97 	int line;
98 	u8 habit;
99 	u8 mdr1;
100 	u8 efr;
101 	u8 scr;
102 	u8 wer;
103 	u8 xon;
104 	u8 xoff;
105 	u8 delayed_restore;
106 	u16 quot;
107 
108 	bool is_suspending;
109 	int wakeirq;
110 	int wakeups_enabled;
111 	u32 latency;
112 	u32 calc_latency;
113 	struct pm_qos_request pm_qos_request;
114 	struct work_struct qos_work;
115 	struct uart_8250_dma omap8250_dma;
116 	spinlock_t rx_dma_lock;
117 	bool rx_dma_broken;
118 	bool throttled;
119 };
120 
121 #ifdef CONFIG_SERIAL_8250_DMA
122 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
123 #else
124 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
125 #endif
126 
127 static u32 uart_read(struct uart_8250_port *up, u32 reg)
128 {
129 	return readl(up->port.membase + (reg << up->port.regshift));
130 }
131 
132 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
133 {
134 	struct uart_8250_port *up = up_to_u8250p(port);
135 	struct omap8250_priv *priv = up->port.private_data;
136 	u8 lcr;
137 
138 	serial8250_do_set_mctrl(port, mctrl);
139 
140 	if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
141 		/*
142 		 * Turn off autoRTS if RTS is lowered and restore autoRTS
143 		 * setting if RTS is raised
144 		 */
145 		lcr = serial_in(up, UART_LCR);
146 		serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
147 		if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
148 			priv->efr |= UART_EFR_RTS;
149 		else
150 			priv->efr &= ~UART_EFR_RTS;
151 		serial_out(up, UART_EFR, priv->efr);
152 		serial_out(up, UART_LCR, lcr);
153 	}
154 }
155 
156 /*
157  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
158  * The access to uart register after MDR1 Access
159  * causes UART to corrupt data.
160  *
161  * Need a delay =
162  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
163  * give 10 times as much
164  */
165 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
166 				     struct omap8250_priv *priv)
167 {
168 	u8 timeout = 255;
169 	u8 old_mdr1;
170 
171 	old_mdr1 = serial_in(up, UART_OMAP_MDR1);
172 	if (old_mdr1 == priv->mdr1)
173 		return;
174 
175 	serial_out(up, UART_OMAP_MDR1, priv->mdr1);
176 	udelay(2);
177 	serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
178 			UART_FCR_CLEAR_RCVR);
179 	/*
180 	 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
181 	 * TX_FIFO_E bit is 1.
182 	 */
183 	while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
184 				(UART_LSR_THRE | UART_LSR_DR))) {
185 		timeout--;
186 		if (!timeout) {
187 			/* Should *never* happen. we warn and carry on */
188 			dev_crit(up->port.dev, "Errata i202: timedout %x\n",
189 				 serial_in(up, UART_LSR));
190 			break;
191 		}
192 		udelay(1);
193 	}
194 }
195 
196 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
197 				  struct omap8250_priv *priv)
198 {
199 	unsigned int uartclk = port->uartclk;
200 	unsigned int div_13, div_16;
201 	unsigned int abs_d13, abs_d16;
202 
203 	/*
204 	 * Old custom speed handling.
205 	 */
206 	if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
207 		priv->quot = port->custom_divisor & UART_DIV_MAX;
208 		/*
209 		 * I assume that nobody is using this. But hey, if somebody
210 		 * would like to specify the divisor _and_ the mode then the
211 		 * driver is ready and waiting for it.
212 		 */
213 		if (port->custom_divisor & (1 << 16))
214 			priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
215 		else
216 			priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
217 		return;
218 	}
219 	div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
220 	div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
221 
222 	if (!div_13)
223 		div_13 = 1;
224 	if (!div_16)
225 		div_16 = 1;
226 
227 	abs_d13 = abs(baud - uartclk / 13 / div_13);
228 	abs_d16 = abs(baud - uartclk / 16 / div_16);
229 
230 	if (abs_d13 >= abs_d16) {
231 		priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
232 		priv->quot = div_16;
233 	} else {
234 		priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
235 		priv->quot = div_13;
236 	}
237 }
238 
239 static void omap8250_update_scr(struct uart_8250_port *up,
240 				struct omap8250_priv *priv)
241 {
242 	u8 old_scr;
243 
244 	old_scr = serial_in(up, UART_OMAP_SCR);
245 	if (old_scr == priv->scr)
246 		return;
247 
248 	/*
249 	 * The manual recommends not to enable the DMA mode selector in the SCR
250 	 * (instead of the FCR) register _and_ selecting the DMA mode as one
251 	 * register write because this may lead to malfunction.
252 	 */
253 	if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
254 		serial_out(up, UART_OMAP_SCR,
255 			   priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
256 	serial_out(up, UART_OMAP_SCR, priv->scr);
257 }
258 
259 static void omap8250_update_mdr1(struct uart_8250_port *up,
260 				 struct omap8250_priv *priv)
261 {
262 	if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
263 		omap_8250_mdr1_errataset(up, priv);
264 	else
265 		serial_out(up, UART_OMAP_MDR1, priv->mdr1);
266 }
267 
268 static void omap8250_restore_regs(struct uart_8250_port *up)
269 {
270 	struct omap8250_priv *priv = up->port.private_data;
271 	struct uart_8250_dma	*dma = up->dma;
272 
273 	if (dma && dma->tx_running) {
274 		/*
275 		 * TCSANOW requests the change to occur immediately however if
276 		 * we have a TX-DMA operation in progress then it has been
277 		 * observed that it might stall and never complete. Therefore we
278 		 * delay DMA completes to prevent this hang from happen.
279 		 */
280 		priv->delayed_restore = 1;
281 		return;
282 	}
283 
284 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
285 	serial_out(up, UART_EFR, UART_EFR_ECB);
286 
287 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
288 	serial8250_out_MCR(up, UART_MCR_TCRTLR);
289 	serial_out(up, UART_FCR, up->fcr);
290 
291 	omap8250_update_scr(up, priv);
292 
293 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
294 
295 	serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
296 			OMAP_UART_TCR_HALT(52));
297 	serial_out(up, UART_TI752_TLR,
298 		   TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
299 		   TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
300 
301 	serial_out(up, UART_LCR, 0);
302 
303 	/* drop TCR + TLR access, we setup XON/XOFF later */
304 	serial8250_out_MCR(up, up->mcr);
305 	serial_out(up, UART_IER, up->ier);
306 
307 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
308 	serial_dl_write(up, priv->quot);
309 
310 	serial_out(up, UART_EFR, priv->efr);
311 
312 	/* Configure flow control */
313 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
314 	serial_out(up, UART_XON1, priv->xon);
315 	serial_out(up, UART_XOFF1, priv->xoff);
316 
317 	serial_out(up, UART_LCR, up->lcr);
318 
319 	omap8250_update_mdr1(up, priv);
320 
321 	up->port.ops->set_mctrl(&up->port, up->port.mctrl);
322 }
323 
324 /*
325  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
326  * some differences in how we want to handle flow control.
327  */
328 static void omap_8250_set_termios(struct uart_port *port,
329 				  struct ktermios *termios,
330 				  struct ktermios *old)
331 {
332 	struct uart_8250_port *up = up_to_u8250p(port);
333 	struct omap8250_priv *priv = up->port.private_data;
334 	unsigned char cval = 0;
335 	unsigned int baud;
336 
337 	switch (termios->c_cflag & CSIZE) {
338 	case CS5:
339 		cval = UART_LCR_WLEN5;
340 		break;
341 	case CS6:
342 		cval = UART_LCR_WLEN6;
343 		break;
344 	case CS7:
345 		cval = UART_LCR_WLEN7;
346 		break;
347 	default:
348 	case CS8:
349 		cval = UART_LCR_WLEN8;
350 		break;
351 	}
352 
353 	if (termios->c_cflag & CSTOPB)
354 		cval |= UART_LCR_STOP;
355 	if (termios->c_cflag & PARENB)
356 		cval |= UART_LCR_PARITY;
357 	if (!(termios->c_cflag & PARODD))
358 		cval |= UART_LCR_EPAR;
359 	if (termios->c_cflag & CMSPAR)
360 		cval |= UART_LCR_SPAR;
361 
362 	/*
363 	 * Ask the core to calculate the divisor for us.
364 	 */
365 	baud = uart_get_baud_rate(port, termios, old,
366 				  port->uartclk / 16 / UART_DIV_MAX,
367 				  port->uartclk / 13);
368 	omap_8250_get_divisor(port, baud, priv);
369 
370 	/*
371 	 * Ok, we're now changing the port state. Do it with
372 	 * interrupts disabled.
373 	 */
374 	pm_runtime_get_sync(port->dev);
375 	spin_lock_irq(&port->lock);
376 
377 	/*
378 	 * Update the per-port timeout.
379 	 */
380 	uart_update_timeout(port, termios->c_cflag, baud);
381 
382 	up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
383 	if (termios->c_iflag & INPCK)
384 		up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
385 	if (termios->c_iflag & (IGNBRK | PARMRK))
386 		up->port.read_status_mask |= UART_LSR_BI;
387 
388 	/*
389 	 * Characters to ignore
390 	 */
391 	up->port.ignore_status_mask = 0;
392 	if (termios->c_iflag & IGNPAR)
393 		up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
394 	if (termios->c_iflag & IGNBRK) {
395 		up->port.ignore_status_mask |= UART_LSR_BI;
396 		/*
397 		 * If we're ignoring parity and break indicators,
398 		 * ignore overruns too (for real raw support).
399 		 */
400 		if (termios->c_iflag & IGNPAR)
401 			up->port.ignore_status_mask |= UART_LSR_OE;
402 	}
403 
404 	/*
405 	 * ignore all characters if CREAD is not set
406 	 */
407 	if ((termios->c_cflag & CREAD) == 0)
408 		up->port.ignore_status_mask |= UART_LSR_DR;
409 
410 	/*
411 	 * Modem status interrupts
412 	 */
413 	up->ier &= ~UART_IER_MSI;
414 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
415 		up->ier |= UART_IER_MSI;
416 
417 	up->lcr = cval;
418 	/* Up to here it was mostly serial8250_do_set_termios() */
419 
420 	/*
421 	 * We enable TRIG_GRANU for RX and TX and additionally we set
422 	 * SCR_TX_EMPTY bit. The result is the following:
423 	 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
424 	 * - less than RX_TRIGGER number of bytes will also cause an interrupt
425 	 *   once the UART decides that there no new bytes arriving.
426 	 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
427 	 *   empty - the trigger level is ignored here.
428 	 *
429 	 * Once DMA is enabled:
430 	 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
431 	 *   bytes in the TX FIFO. On each assert the DMA engine will move
432 	 *   TX_TRIGGER bytes into the FIFO.
433 	 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
434 	 *   the FIFO and move RX_TRIGGER bytes.
435 	 * This is because threshold and trigger values are the same.
436 	 */
437 	up->fcr = UART_FCR_ENABLE_FIFO;
438 	up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
439 	up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
440 
441 	priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
442 		OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
443 
444 	if (up->dma)
445 		priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
446 			OMAP_UART_SCR_DMAMODE_CTL;
447 
448 	priv->xon = termios->c_cc[VSTART];
449 	priv->xoff = termios->c_cc[VSTOP];
450 
451 	priv->efr = 0;
452 	up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
453 
454 	if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
455 	    !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
456 	    !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
457 		/* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
458 		up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
459 		priv->efr |= UART_EFR_CTS;
460 	} else	if (up->port.flags & UPF_SOFT_FLOW) {
461 		/*
462 		 * OMAP rx s/w flow control is borked; the transmitter remains
463 		 * stuck off even if rx flow control is subsequently disabled
464 		 */
465 
466 		/*
467 		 * IXOFF Flag:
468 		 * Enable XON/XOFF flow control on output.
469 		 * Transmit XON1, XOFF1
470 		 */
471 		if (termios->c_iflag & IXOFF) {
472 			up->port.status |= UPSTAT_AUTOXOFF;
473 			priv->efr |= OMAP_UART_SW_TX;
474 		}
475 	}
476 	omap8250_restore_regs(up);
477 
478 	spin_unlock_irq(&up->port.lock);
479 	pm_runtime_mark_last_busy(port->dev);
480 	pm_runtime_put_autosuspend(port->dev);
481 
482 	/* calculate wakeup latency constraint */
483 	priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
484 	priv->latency = priv->calc_latency;
485 
486 	schedule_work(&priv->qos_work);
487 
488 	/* Don't rewrite B0 */
489 	if (tty_termios_baud_rate(termios))
490 		tty_termios_encode_baud_rate(termios, baud, baud);
491 }
492 
493 /* same as 8250 except that we may have extra flow bits set in EFR */
494 static void omap_8250_pm(struct uart_port *port, unsigned int state,
495 			 unsigned int oldstate)
496 {
497 	struct uart_8250_port *up = up_to_u8250p(port);
498 	u8 efr;
499 
500 	pm_runtime_get_sync(port->dev);
501 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
502 	efr = serial_in(up, UART_EFR);
503 	serial_out(up, UART_EFR, efr | UART_EFR_ECB);
504 	serial_out(up, UART_LCR, 0);
505 
506 	serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
507 	serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
508 	serial_out(up, UART_EFR, efr);
509 	serial_out(up, UART_LCR, 0);
510 
511 	pm_runtime_mark_last_busy(port->dev);
512 	pm_runtime_put_autosuspend(port->dev);
513 }
514 
515 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
516 					      struct omap8250_priv *priv)
517 {
518 	u32 mvr, scheme;
519 	u16 revision, major, minor;
520 
521 	mvr = uart_read(up, UART_OMAP_MVER);
522 
523 	/* Check revision register scheme */
524 	scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
525 
526 	switch (scheme) {
527 	case 0: /* Legacy Scheme: OMAP2/3 */
528 		/* MINOR_REV[0:4], MAJOR_REV[4:7] */
529 		major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
530 			OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
531 		minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
532 		break;
533 	case 1:
534 		/* New Scheme: OMAP4+ */
535 		/* MINOR_REV[0:5], MAJOR_REV[8:10] */
536 		major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
537 			OMAP_UART_MVR_MAJ_SHIFT;
538 		minor = (mvr & OMAP_UART_MVR_MIN_MASK);
539 		break;
540 	default:
541 		dev_warn(up->port.dev,
542 			 "Unknown revision, defaulting to highest\n");
543 		/* highest possible revision */
544 		major = 0xff;
545 		minor = 0xff;
546 	}
547 	/* normalize revision for the driver */
548 	revision = UART_BUILD_REVISION(major, minor);
549 
550 	switch (revision) {
551 	case OMAP_UART_REV_46:
552 		priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
553 		break;
554 	case OMAP_UART_REV_52:
555 		priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
556 				OMAP_UART_WER_HAS_TX_WAKEUP;
557 		break;
558 	case OMAP_UART_REV_63:
559 		priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
560 			OMAP_UART_WER_HAS_TX_WAKEUP;
561 		break;
562 	default:
563 		break;
564 	}
565 }
566 
567 static void omap8250_uart_qos_work(struct work_struct *work)
568 {
569 	struct omap8250_priv *priv;
570 
571 	priv = container_of(work, struct omap8250_priv, qos_work);
572 	pm_qos_update_request(&priv->pm_qos_request, priv->latency);
573 }
574 
575 #ifdef CONFIG_SERIAL_8250_DMA
576 static int omap_8250_dma_handle_irq(struct uart_port *port);
577 #endif
578 
579 static irqreturn_t omap8250_irq(int irq, void *dev_id)
580 {
581 	struct uart_port *port = dev_id;
582 	struct uart_8250_port *up = up_to_u8250p(port);
583 	unsigned int iir;
584 	int ret;
585 
586 #ifdef CONFIG_SERIAL_8250_DMA
587 	if (up->dma) {
588 		ret = omap_8250_dma_handle_irq(port);
589 		return IRQ_RETVAL(ret);
590 	}
591 #endif
592 
593 	serial8250_rpm_get(up);
594 	iir = serial_port_in(port, UART_IIR);
595 	ret = serial8250_handle_irq(port, iir);
596 	serial8250_rpm_put(up);
597 
598 	return IRQ_RETVAL(ret);
599 }
600 
601 static int omap_8250_startup(struct uart_port *port)
602 {
603 	struct uart_8250_port *up = up_to_u8250p(port);
604 	struct omap8250_priv *priv = port->private_data;
605 	int ret;
606 
607 	if (priv->wakeirq) {
608 		ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
609 		if (ret)
610 			return ret;
611 	}
612 
613 	pm_runtime_get_sync(port->dev);
614 
615 	up->mcr = 0;
616 	serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
617 
618 	serial_out(up, UART_LCR, UART_LCR_WLEN8);
619 
620 	up->lsr_saved_flags = 0;
621 	up->msr_saved_flags = 0;
622 
623 	/* Disable DMA for console UART */
624 	if (uart_console(port))
625 		up->dma = NULL;
626 
627 	if (up->dma) {
628 		ret = serial8250_request_dma(up);
629 		if (ret) {
630 			dev_warn_ratelimited(port->dev,
631 					     "failed to request DMA\n");
632 			up->dma = NULL;
633 		}
634 	}
635 
636 	ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
637 			  dev_name(port->dev), port);
638 	if (ret < 0)
639 		goto err;
640 
641 	up->ier = UART_IER_RLSI | UART_IER_RDI;
642 	serial_out(up, UART_IER, up->ier);
643 
644 #ifdef CONFIG_PM
645 	up->capabilities |= UART_CAP_RPM;
646 #endif
647 
648 	/* Enable module level wake up */
649 	priv->wer = OMAP_UART_WER_MOD_WKUP;
650 	if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
651 		priv->wer |= OMAP_UART_TX_WAKEUP_EN;
652 	serial_out(up, UART_OMAP_WER, priv->wer);
653 
654 	if (up->dma)
655 		up->dma->rx_dma(up);
656 
657 	pm_runtime_mark_last_busy(port->dev);
658 	pm_runtime_put_autosuspend(port->dev);
659 	return 0;
660 err:
661 	pm_runtime_mark_last_busy(port->dev);
662 	pm_runtime_put_autosuspend(port->dev);
663 	dev_pm_clear_wake_irq(port->dev);
664 	return ret;
665 }
666 
667 static void omap_8250_shutdown(struct uart_port *port)
668 {
669 	struct uart_8250_port *up = up_to_u8250p(port);
670 	struct omap8250_priv *priv = port->private_data;
671 
672 	flush_work(&priv->qos_work);
673 	if (up->dma)
674 		omap_8250_rx_dma_flush(up);
675 
676 	pm_runtime_get_sync(port->dev);
677 
678 	serial_out(up, UART_OMAP_WER, 0);
679 
680 	up->ier = 0;
681 	serial_out(up, UART_IER, 0);
682 
683 	if (up->dma)
684 		serial8250_release_dma(up);
685 
686 	/*
687 	 * Disable break condition and FIFOs
688 	 */
689 	if (up->lcr & UART_LCR_SBC)
690 		serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
691 	serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
692 
693 	pm_runtime_mark_last_busy(port->dev);
694 	pm_runtime_put_autosuspend(port->dev);
695 	free_irq(port->irq, port);
696 	dev_pm_clear_wake_irq(port->dev);
697 }
698 
699 static void omap_8250_throttle(struct uart_port *port)
700 {
701 	struct omap8250_priv *priv = port->private_data;
702 	struct uart_8250_port *up = up_to_u8250p(port);
703 	unsigned long flags;
704 
705 	pm_runtime_get_sync(port->dev);
706 
707 	spin_lock_irqsave(&port->lock, flags);
708 	up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
709 	serial_out(up, UART_IER, up->ier);
710 	priv->throttled = true;
711 	spin_unlock_irqrestore(&port->lock, flags);
712 
713 	pm_runtime_mark_last_busy(port->dev);
714 	pm_runtime_put_autosuspend(port->dev);
715 }
716 
717 static int omap_8250_rs485_config(struct uart_port *port,
718 				  struct serial_rs485 *rs485)
719 {
720 	struct uart_8250_port *up = up_to_u8250p(port);
721 
722 	/* Clamp the delays to [0, 100ms] */
723 	rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
724 	rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
725 
726 	port->rs485 = *rs485;
727 
728 	/*
729 	 * Both serial8250_em485_init and serial8250_em485_destroy
730 	 * are idempotent
731 	 */
732 	if (rs485->flags & SER_RS485_ENABLED) {
733 		int ret = serial8250_em485_init(up);
734 
735 		if (ret) {
736 			rs485->flags &= ~SER_RS485_ENABLED;
737 			port->rs485.flags &= ~SER_RS485_ENABLED;
738 		}
739 		return ret;
740 	}
741 
742 	serial8250_em485_destroy(up);
743 
744 	return 0;
745 }
746 
747 static void omap_8250_unthrottle(struct uart_port *port)
748 {
749 	struct omap8250_priv *priv = port->private_data;
750 	struct uart_8250_port *up = up_to_u8250p(port);
751 	unsigned long flags;
752 
753 	pm_runtime_get_sync(port->dev);
754 
755 	spin_lock_irqsave(&port->lock, flags);
756 	priv->throttled = false;
757 	if (up->dma)
758 		up->dma->rx_dma(up);
759 	up->ier |= UART_IER_RLSI | UART_IER_RDI;
760 	serial_out(up, UART_IER, up->ier);
761 	spin_unlock_irqrestore(&port->lock, flags);
762 
763 	pm_runtime_mark_last_busy(port->dev);
764 	pm_runtime_put_autosuspend(port->dev);
765 }
766 
767 #ifdef CONFIG_SERIAL_8250_DMA
768 static int omap_8250_rx_dma(struct uart_8250_port *p);
769 
770 static void __dma_rx_do_complete(struct uart_8250_port *p)
771 {
772 	struct omap8250_priv	*priv = p->port.private_data;
773 	struct uart_8250_dma    *dma = p->dma;
774 	struct tty_port         *tty_port = &p->port.state->port;
775 	struct dma_tx_state     state;
776 	int                     count;
777 	unsigned long		flags;
778 	int			ret;
779 
780 	spin_lock_irqsave(&priv->rx_dma_lock, flags);
781 
782 	if (!dma->rx_running)
783 		goto unlock;
784 
785 	dma->rx_running = 0;
786 	dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
787 
788 	count = dma->rx_size - state.residue;
789 
790 	ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
791 
792 	p->port.icount.rx += ret;
793 	p->port.icount.buf_overrun += count - ret;
794 unlock:
795 	spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
796 
797 	tty_flip_buffer_push(tty_port);
798 }
799 
800 static void __dma_rx_complete(void *param)
801 {
802 	struct uart_8250_port *p = param;
803 	struct omap8250_priv *priv = p->port.private_data;
804 	struct uart_8250_dma *dma = p->dma;
805 	struct dma_tx_state     state;
806 	unsigned long flags;
807 
808 	spin_lock_irqsave(&p->port.lock, flags);
809 
810 	/*
811 	 * If the tx status is not DMA_COMPLETE, then this is a delayed
812 	 * completion callback. A previous RX timeout flush would have
813 	 * already pushed the data, so exit.
814 	 */
815 	if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
816 			DMA_COMPLETE) {
817 		spin_unlock_irqrestore(&p->port.lock, flags);
818 		return;
819 	}
820 	__dma_rx_do_complete(p);
821 	if (!priv->throttled)
822 		omap_8250_rx_dma(p);
823 
824 	spin_unlock_irqrestore(&p->port.lock, flags);
825 }
826 
827 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
828 {
829 	struct omap8250_priv	*priv = p->port.private_data;
830 	struct uart_8250_dma	*dma = p->dma;
831 	struct dma_tx_state     state;
832 	unsigned long		flags;
833 	int ret;
834 
835 	spin_lock_irqsave(&priv->rx_dma_lock, flags);
836 
837 	if (!dma->rx_running) {
838 		spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
839 		return;
840 	}
841 
842 	ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
843 	if (ret == DMA_IN_PROGRESS) {
844 		ret = dmaengine_pause(dma->rxchan);
845 		if (WARN_ON_ONCE(ret))
846 			priv->rx_dma_broken = true;
847 	}
848 	spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
849 
850 	__dma_rx_do_complete(p);
851 	dmaengine_terminate_all(dma->rxchan);
852 }
853 
854 static int omap_8250_rx_dma(struct uart_8250_port *p)
855 {
856 	struct omap8250_priv		*priv = p->port.private_data;
857 	struct uart_8250_dma            *dma = p->dma;
858 	int				err = 0;
859 	struct dma_async_tx_descriptor  *desc;
860 	unsigned long			flags;
861 
862 	if (priv->rx_dma_broken)
863 		return -EINVAL;
864 
865 	spin_lock_irqsave(&priv->rx_dma_lock, flags);
866 
867 	if (dma->rx_running)
868 		goto out;
869 
870 	desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
871 					   dma->rx_size, DMA_DEV_TO_MEM,
872 					   DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
873 	if (!desc) {
874 		err = -EBUSY;
875 		goto out;
876 	}
877 
878 	dma->rx_running = 1;
879 	desc->callback = __dma_rx_complete;
880 	desc->callback_param = p;
881 
882 	dma->rx_cookie = dmaengine_submit(desc);
883 
884 	dma_async_issue_pending(dma->rxchan);
885 out:
886 	spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
887 	return err;
888 }
889 
890 static int omap_8250_tx_dma(struct uart_8250_port *p);
891 
892 static void omap_8250_dma_tx_complete(void *param)
893 {
894 	struct uart_8250_port	*p = param;
895 	struct uart_8250_dma	*dma = p->dma;
896 	struct circ_buf		*xmit = &p->port.state->xmit;
897 	unsigned long		flags;
898 	bool			en_thri = false;
899 	struct omap8250_priv	*priv = p->port.private_data;
900 
901 	dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
902 				UART_XMIT_SIZE, DMA_TO_DEVICE);
903 
904 	spin_lock_irqsave(&p->port.lock, flags);
905 
906 	dma->tx_running = 0;
907 
908 	xmit->tail += dma->tx_size;
909 	xmit->tail &= UART_XMIT_SIZE - 1;
910 	p->port.icount.tx += dma->tx_size;
911 
912 	if (priv->delayed_restore) {
913 		priv->delayed_restore = 0;
914 		omap8250_restore_regs(p);
915 	}
916 
917 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
918 		uart_write_wakeup(&p->port);
919 
920 	if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
921 		int ret;
922 
923 		ret = omap_8250_tx_dma(p);
924 		if (ret)
925 			en_thri = true;
926 	} else if (p->capabilities & UART_CAP_RPM) {
927 		en_thri = true;
928 	}
929 
930 	if (en_thri) {
931 		dma->tx_err = 1;
932 		serial8250_set_THRI(p);
933 	}
934 
935 	spin_unlock_irqrestore(&p->port.lock, flags);
936 }
937 
938 static int omap_8250_tx_dma(struct uart_8250_port *p)
939 {
940 	struct uart_8250_dma		*dma = p->dma;
941 	struct omap8250_priv		*priv = p->port.private_data;
942 	struct circ_buf			*xmit = &p->port.state->xmit;
943 	struct dma_async_tx_descriptor	*desc;
944 	unsigned int	skip_byte = 0;
945 	int ret;
946 
947 	if (dma->tx_running)
948 		return 0;
949 	if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
950 
951 		/*
952 		 * Even if no data, we need to return an error for the two cases
953 		 * below so serial8250_tx_chars() is invoked and properly clears
954 		 * THRI and/or runtime suspend.
955 		 */
956 		if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
957 			ret = -EBUSY;
958 			goto err;
959 		}
960 		serial8250_clear_THRI(p);
961 		return 0;
962 	}
963 
964 	dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
965 	if (priv->habit & OMAP_DMA_TX_KICK) {
966 		u8 tx_lvl;
967 
968 		/*
969 		 * We need to put the first byte into the FIFO in order to start
970 		 * the DMA transfer. For transfers smaller than four bytes we
971 		 * don't bother doing DMA at all. It seem not matter if there
972 		 * are still bytes in the FIFO from the last transfer (in case
973 		 * we got here directly from omap_8250_dma_tx_complete()). Bytes
974 		 * leaving the FIFO seem not to trigger the DMA transfer. It is
975 		 * really the byte that we put into the FIFO.
976 		 * If the FIFO is already full then we most likely got here from
977 		 * omap_8250_dma_tx_complete(). And this means the DMA engine
978 		 * just completed its work. We don't have to wait the complete
979 		 * 86us at 115200,8n1 but around 60us (not to mention lower
980 		 * baudrates). So in that case we take the interrupt and try
981 		 * again with an empty FIFO.
982 		 */
983 		tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
984 		if (tx_lvl == p->tx_loadsz) {
985 			ret = -EBUSY;
986 			goto err;
987 		}
988 		if (dma->tx_size < 4) {
989 			ret = -EINVAL;
990 			goto err;
991 		}
992 		skip_byte = 1;
993 	}
994 
995 	desc = dmaengine_prep_slave_single(dma->txchan,
996 			dma->tx_addr + xmit->tail + skip_byte,
997 			dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
998 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
999 	if (!desc) {
1000 		ret = -EBUSY;
1001 		goto err;
1002 	}
1003 
1004 	dma->tx_running = 1;
1005 
1006 	desc->callback = omap_8250_dma_tx_complete;
1007 	desc->callback_param = p;
1008 
1009 	dma->tx_cookie = dmaengine_submit(desc);
1010 
1011 	dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1012 				   UART_XMIT_SIZE, DMA_TO_DEVICE);
1013 
1014 	dma_async_issue_pending(dma->txchan);
1015 	if (dma->tx_err)
1016 		dma->tx_err = 0;
1017 
1018 	serial8250_clear_THRI(p);
1019 	if (skip_byte)
1020 		serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1021 	return 0;
1022 err:
1023 	dma->tx_err = 1;
1024 	return ret;
1025 }
1026 
1027 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1028 {
1029 	switch (iir & 0x3f) {
1030 	case UART_IIR_RLSI:
1031 	case UART_IIR_RX_TIMEOUT:
1032 	case UART_IIR_RDI:
1033 		omap_8250_rx_dma_flush(up);
1034 		return true;
1035 	}
1036 	return omap_8250_rx_dma(up);
1037 }
1038 
1039 /*
1040  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1041  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1042  * use the default routine in the non-DMA case and this one for with DMA.
1043  */
1044 static int omap_8250_dma_handle_irq(struct uart_port *port)
1045 {
1046 	struct uart_8250_port *up = up_to_u8250p(port);
1047 	unsigned char status;
1048 	unsigned long flags;
1049 	u8 iir;
1050 
1051 	serial8250_rpm_get(up);
1052 
1053 	iir = serial_port_in(port, UART_IIR);
1054 	if (iir & UART_IIR_NO_INT) {
1055 		serial8250_rpm_put(up);
1056 		return 0;
1057 	}
1058 
1059 	spin_lock_irqsave(&port->lock, flags);
1060 
1061 	status = serial_port_in(port, UART_LSR);
1062 
1063 	if (status & (UART_LSR_DR | UART_LSR_BI)) {
1064 		if (handle_rx_dma(up, iir)) {
1065 			status = serial8250_rx_chars(up, status);
1066 			omap_8250_rx_dma(up);
1067 		}
1068 	}
1069 	serial8250_modem_status(up);
1070 	if (status & UART_LSR_THRE && up->dma->tx_err) {
1071 		if (uart_tx_stopped(&up->port) ||
1072 		    uart_circ_empty(&up->port.state->xmit)) {
1073 			up->dma->tx_err = 0;
1074 			serial8250_tx_chars(up);
1075 		} else  {
1076 			/*
1077 			 * try again due to an earlier failer which
1078 			 * might have been resolved by now.
1079 			 */
1080 			if (omap_8250_tx_dma(up))
1081 				serial8250_tx_chars(up);
1082 		}
1083 	}
1084 
1085 	uart_unlock_and_check_sysrq(port, flags);
1086 	serial8250_rpm_put(up);
1087 	return 1;
1088 }
1089 
1090 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1091 {
1092 	return false;
1093 }
1094 
1095 #else
1096 
1097 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1098 {
1099 	return -EINVAL;
1100 }
1101 #endif
1102 
1103 static int omap8250_no_handle_irq(struct uart_port *port)
1104 {
1105 	/* IRQ has not been requested but handling irq? */
1106 	WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1107 	return 0;
1108 }
1109 
1110 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1111 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1112 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1113 
1114 static const struct of_device_id omap8250_dt_ids[] = {
1115 	{ .compatible = "ti,am654-uart" },
1116 	{ .compatible = "ti,omap2-uart" },
1117 	{ .compatible = "ti,omap3-uart" },
1118 	{ .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1119 	{ .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1120 	{ .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1121 	{ .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1122 	{},
1123 };
1124 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1125 
1126 static int omap8250_probe(struct platform_device *pdev)
1127 {
1128 	struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1129 	struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1130 	struct device_node *np = pdev->dev.of_node;
1131 	struct omap8250_priv *priv;
1132 	struct uart_8250_port up;
1133 	int ret;
1134 	void __iomem *membase;
1135 	const struct of_device_id *id;
1136 
1137 	if (!regs || !irq) {
1138 		dev_err(&pdev->dev, "missing registers or irq\n");
1139 		return -EINVAL;
1140 	}
1141 
1142 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1143 	if (!priv)
1144 		return -ENOMEM;
1145 
1146 	membase = devm_ioremap(&pdev->dev, regs->start,
1147 				       resource_size(regs));
1148 	if (!membase)
1149 		return -ENODEV;
1150 
1151 	memset(&up, 0, sizeof(up));
1152 	up.port.dev = &pdev->dev;
1153 	up.port.mapbase = regs->start;
1154 	up.port.membase = membase;
1155 	up.port.irq = irq->start;
1156 	/*
1157 	 * It claims to be 16C750 compatible however it is a little different.
1158 	 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1159 	 * have) is enabled via EFR instead of MCR. The type is set here 8250
1160 	 * just to get things going. UNKNOWN does not work for a few reasons and
1161 	 * we don't need our own type since we don't use 8250's set_termios()
1162 	 * or pm callback.
1163 	 */
1164 	up.port.type = PORT_8250;
1165 	up.port.iotype = UPIO_MEM;
1166 	up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1167 		UPF_HARD_FLOW;
1168 	up.port.private_data = priv;
1169 
1170 	up.port.regshift = 2;
1171 	up.port.fifosize = 64;
1172 	up.tx_loadsz = 64;
1173 	up.capabilities = UART_CAP_FIFO;
1174 #ifdef CONFIG_PM
1175 	/*
1176 	 * Runtime PM is mostly transparent. However to do it right we need to a
1177 	 * TX empty interrupt before we can put the device to auto idle. So if
1178 	 * PM is not enabled we don't add that flag and can spare that one extra
1179 	 * interrupt in the TX path.
1180 	 */
1181 	up.capabilities |= UART_CAP_RPM;
1182 #endif
1183 	up.port.set_termios = omap_8250_set_termios;
1184 	up.port.set_mctrl = omap8250_set_mctrl;
1185 	up.port.pm = omap_8250_pm;
1186 	up.port.startup = omap_8250_startup;
1187 	up.port.shutdown = omap_8250_shutdown;
1188 	up.port.throttle = omap_8250_throttle;
1189 	up.port.unthrottle = omap_8250_unthrottle;
1190 	up.port.rs485_config = omap_8250_rs485_config;
1191 	up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1192 
1193 	ret = of_alias_get_id(np, "serial");
1194 	if (ret < 0) {
1195 		dev_err(&pdev->dev, "failed to get alias\n");
1196 		return ret;
1197 	}
1198 	up.port.line = ret;
1199 
1200 	if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1201 		struct clk *clk;
1202 
1203 		clk = devm_clk_get(&pdev->dev, NULL);
1204 		if (IS_ERR(clk)) {
1205 			if (PTR_ERR(clk) == -EPROBE_DEFER)
1206 				return -EPROBE_DEFER;
1207 		} else {
1208 			up.port.uartclk = clk_get_rate(clk);
1209 		}
1210 	}
1211 
1212 	priv->wakeirq = irq_of_parse_and_map(np, 1);
1213 
1214 	id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1215 	if (id && id->data)
1216 		priv->habit |= *(u8 *)id->data;
1217 
1218 	if (!up.port.uartclk) {
1219 		up.port.uartclk = DEFAULT_CLK_SPEED;
1220 		dev_warn(&pdev->dev,
1221 			 "No clock speed specified: using default: %d\n",
1222 			 DEFAULT_CLK_SPEED);
1223 	}
1224 
1225 	priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1226 	priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1227 	pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1228 			   priv->latency);
1229 	INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1230 
1231 	spin_lock_init(&priv->rx_dma_lock);
1232 
1233 	device_init_wakeup(&pdev->dev, true);
1234 	pm_runtime_use_autosuspend(&pdev->dev);
1235 
1236 	/*
1237 	 * Disable runtime PM until autosuspend delay unless specifically
1238 	 * enabled by the user via sysfs. This is the historic way to
1239 	 * prevent an unsafe default policy with lossy characters on wake-up.
1240 	 * For serdev devices this is not needed, the policy can be managed by
1241 	 * the serdev driver.
1242 	 */
1243 	if (!of_get_available_child_count(pdev->dev.of_node))
1244 		pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1245 
1246 	pm_runtime_irq_safe(&pdev->dev);
1247 	pm_runtime_enable(&pdev->dev);
1248 
1249 	pm_runtime_get_sync(&pdev->dev);
1250 
1251 	omap_serial_fill_features_erratas(&up, priv);
1252 	up.port.handle_irq = omap8250_no_handle_irq;
1253 #ifdef CONFIG_SERIAL_8250_DMA
1254 	/*
1255 	 * Oh DMA support. If there are no DMA properties in the DT then
1256 	 * we will fall back to a generic DMA channel which does not
1257 	 * really work here. To ensure that we do not get a generic DMA
1258 	 * channel assigned, we have the the_no_dma_filter_fn() here.
1259 	 * To avoid "failed to request DMA" messages we check for DMA
1260 	 * properties in DT.
1261 	 */
1262 	ret = of_property_count_strings(np, "dma-names");
1263 	if (ret == 2) {
1264 		up.dma = &priv->omap8250_dma;
1265 		priv->omap8250_dma.fn = the_no_dma_filter_fn;
1266 		priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1267 		priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1268 		priv->omap8250_dma.rx_size = RX_TRIGGER;
1269 		priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1270 		priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1271 	}
1272 #endif
1273 	ret = serial8250_register_8250_port(&up);
1274 	if (ret < 0) {
1275 		dev_err(&pdev->dev, "unable to register 8250 port\n");
1276 		goto err;
1277 	}
1278 	priv->line = ret;
1279 	platform_set_drvdata(pdev, priv);
1280 	pm_runtime_mark_last_busy(&pdev->dev);
1281 	pm_runtime_put_autosuspend(&pdev->dev);
1282 	return 0;
1283 err:
1284 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1285 	pm_runtime_put_sync(&pdev->dev);
1286 	pm_runtime_disable(&pdev->dev);
1287 	return ret;
1288 }
1289 
1290 static int omap8250_remove(struct platform_device *pdev)
1291 {
1292 	struct omap8250_priv *priv = platform_get_drvdata(pdev);
1293 
1294 	pm_runtime_dont_use_autosuspend(&pdev->dev);
1295 	pm_runtime_put_sync(&pdev->dev);
1296 	pm_runtime_disable(&pdev->dev);
1297 	serial8250_unregister_port(priv->line);
1298 	pm_qos_remove_request(&priv->pm_qos_request);
1299 	device_init_wakeup(&pdev->dev, false);
1300 	return 0;
1301 }
1302 
1303 #ifdef CONFIG_PM_SLEEP
1304 static int omap8250_prepare(struct device *dev)
1305 {
1306 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1307 
1308 	if (!priv)
1309 		return 0;
1310 	priv->is_suspending = true;
1311 	return 0;
1312 }
1313 
1314 static void omap8250_complete(struct device *dev)
1315 {
1316 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1317 
1318 	if (!priv)
1319 		return;
1320 	priv->is_suspending = false;
1321 }
1322 
1323 static int omap8250_suspend(struct device *dev)
1324 {
1325 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1326 	struct uart_8250_port *up = serial8250_get_port(priv->line);
1327 
1328 	serial8250_suspend_port(priv->line);
1329 
1330 	pm_runtime_get_sync(dev);
1331 	if (!device_may_wakeup(dev))
1332 		priv->wer = 0;
1333 	serial_out(up, UART_OMAP_WER, priv->wer);
1334 	pm_runtime_mark_last_busy(dev);
1335 	pm_runtime_put_autosuspend(dev);
1336 
1337 	flush_work(&priv->qos_work);
1338 	return 0;
1339 }
1340 
1341 static int omap8250_resume(struct device *dev)
1342 {
1343 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1344 
1345 	serial8250_resume_port(priv->line);
1346 	return 0;
1347 }
1348 #else
1349 #define omap8250_prepare NULL
1350 #define omap8250_complete NULL
1351 #endif
1352 
1353 #ifdef CONFIG_PM
1354 static int omap8250_lost_context(struct uart_8250_port *up)
1355 {
1356 	u32 val;
1357 
1358 	val = serial_in(up, UART_OMAP_SCR);
1359 	/*
1360 	 * If we lose context, then SCR is set to its reset value of zero.
1361 	 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1362 	 * among other bits, to never set the register back to zero again.
1363 	 */
1364 	if (!val)
1365 		return 1;
1366 	return 0;
1367 }
1368 
1369 /* TODO: in future, this should happen via API in drivers/reset/ */
1370 static int omap8250_soft_reset(struct device *dev)
1371 {
1372 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1373 	struct uart_8250_port *up = serial8250_get_port(priv->line);
1374 	int timeout = 100;
1375 	int sysc;
1376 	int syss;
1377 
1378 	/*
1379 	 * At least on omap4, unused uarts may not idle after reset without
1380 	 * a basic scr dma configuration even with no dma in use. The
1381 	 * module clkctrl status bits will be 1 instead of 3 blocking idle
1382 	 * for the whole clockdomain. The softreset below will clear scr,
1383 	 * and we restore it on resume so this is safe to do on all SoCs
1384 	 * needing omap8250_soft_reset() quirk. Do it in two writes as
1385 	 * recommended in the comment for omap8250_update_scr().
1386 	 */
1387 	serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1388 	serial_out(up, UART_OMAP_SCR,
1389 		   OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1390 
1391 	sysc = serial_in(up, UART_OMAP_SYSC);
1392 
1393 	/* softreset the UART */
1394 	sysc |= OMAP_UART_SYSC_SOFTRESET;
1395 	serial_out(up, UART_OMAP_SYSC, sysc);
1396 
1397 	/* By experiments, 1us enough for reset complete on AM335x */
1398 	do {
1399 		udelay(1);
1400 		syss = serial_in(up, UART_OMAP_SYSS);
1401 	} while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1402 
1403 	if (!timeout) {
1404 		dev_err(dev, "timed out waiting for reset done\n");
1405 		return -ETIMEDOUT;
1406 	}
1407 
1408 	return 0;
1409 }
1410 
1411 static int omap8250_runtime_suspend(struct device *dev)
1412 {
1413 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1414 	struct uart_8250_port *up;
1415 
1416 	/* In case runtime-pm tries this before we are setup */
1417 	if (!priv)
1418 		return 0;
1419 
1420 	up = serial8250_get_port(priv->line);
1421 	/*
1422 	 * When using 'no_console_suspend', the console UART must not be
1423 	 * suspended. Since driver suspend is managed by runtime suspend,
1424 	 * preventing runtime suspend (by returning error) will keep device
1425 	 * active during suspend.
1426 	 */
1427 	if (priv->is_suspending && !console_suspend_enabled) {
1428 		if (uart_console(&up->port))
1429 			return -EBUSY;
1430 	}
1431 
1432 	if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1433 		int ret;
1434 
1435 		ret = omap8250_soft_reset(dev);
1436 		if (ret)
1437 			return ret;
1438 
1439 		/* Restore to UART mode after reset (for wakeup) */
1440 		omap8250_update_mdr1(up, priv);
1441 		/* Restore wakeup enable register */
1442 		serial_out(up, UART_OMAP_WER, priv->wer);
1443 	}
1444 
1445 	if (up->dma && up->dma->rxchan)
1446 		omap_8250_rx_dma_flush(up);
1447 
1448 	priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1449 	schedule_work(&priv->qos_work);
1450 
1451 	return 0;
1452 }
1453 
1454 static int omap8250_runtime_resume(struct device *dev)
1455 {
1456 	struct omap8250_priv *priv = dev_get_drvdata(dev);
1457 	struct uart_8250_port *up;
1458 
1459 	/* In case runtime-pm tries this before we are setup */
1460 	if (!priv)
1461 		return 0;
1462 
1463 	up = serial8250_get_port(priv->line);
1464 
1465 	if (omap8250_lost_context(up))
1466 		omap8250_restore_regs(up);
1467 
1468 	if (up->dma && up->dma->rxchan)
1469 		omap_8250_rx_dma(up);
1470 
1471 	priv->latency = priv->calc_latency;
1472 	schedule_work(&priv->qos_work);
1473 	return 0;
1474 }
1475 #endif
1476 
1477 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1478 static int __init omap8250_console_fixup(void)
1479 {
1480 	char *omap_str;
1481 	char *options;
1482 	u8 idx;
1483 
1484 	if (strstr(boot_command_line, "console=ttyS"))
1485 		/* user set a ttyS based name for the console */
1486 		return 0;
1487 
1488 	omap_str = strstr(boot_command_line, "console=ttyO");
1489 	if (!omap_str)
1490 		/* user did not set ttyO based console, so we don't care */
1491 		return 0;
1492 
1493 	omap_str += 12;
1494 	if ('0' <= *omap_str && *omap_str <= '9')
1495 		idx = *omap_str - '0';
1496 	else
1497 		return 0;
1498 
1499 	omap_str++;
1500 	if (omap_str[0] == ',') {
1501 		omap_str++;
1502 		options = omap_str;
1503 	} else {
1504 		options = NULL;
1505 	}
1506 
1507 	add_preferred_console("ttyS", idx, options);
1508 	pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1509 	       idx, idx);
1510 	pr_err("This ensures that you still see kernel messages. Please\n");
1511 	pr_err("update your kernel commandline.\n");
1512 	return 0;
1513 }
1514 console_initcall(omap8250_console_fixup);
1515 #endif
1516 
1517 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1518 	SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1519 	SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1520 			   omap8250_runtime_resume, NULL)
1521 	.prepare        = omap8250_prepare,
1522 	.complete       = omap8250_complete,
1523 };
1524 
1525 static struct platform_driver omap8250_platform_driver = {
1526 	.driver = {
1527 		.name		= "omap8250",
1528 		.pm		= &omap8250_dev_pm_ops,
1529 		.of_match_table = omap8250_dt_ids,
1530 	},
1531 	.probe			= omap8250_probe,
1532 	.remove			= omap8250_remove,
1533 };
1534 module_platform_driver(omap8250_platform_driver);
1535 
1536 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1537 MODULE_DESCRIPTION("OMAP 8250 Driver");
1538 MODULE_LICENSE("GPL v2");
1539