1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/serial_8250.h> 16 #include <linux/serial_reg.h> 17 #include <linux/tty_flip.h> 18 #include <linux/platform_device.h> 19 #include <linux/slab.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/of_gpio.h> 23 #include <linux/of_irq.h> 24 #include <linux/delay.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/console.h> 27 #include <linux/pm_qos.h> 28 #include <linux/pm_wakeirq.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/sys_soc.h> 31 32 #include "8250.h" 33 34 #define DEFAULT_CLK_SPEED 48000000 35 36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 38 #define OMAP_DMA_TX_KICK (1 << 2) 39 /* 40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 41 * The same errata is applicable to AM335x and DRA7x processors too. 42 */ 43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 44 #define UART_HAS_EFR2 BIT(4) 45 #define UART_HAS_RHR_IT_DIS BIT(5) 46 #define UART_RX_TIMEOUT_QUIRK BIT(6) 47 48 #define OMAP_UART_FCR_RX_TRIG 6 49 #define OMAP_UART_FCR_TX_TRIG 4 50 51 /* SCR register bitmasks */ 52 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 53 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 54 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 55 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 56 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 57 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 58 59 /* MVR register bitmasks */ 60 #define OMAP_UART_MVR_SCHEME_SHIFT 30 61 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 62 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 63 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 64 #define OMAP_UART_MVR_MAJ_MASK 0x700 65 #define OMAP_UART_MVR_MAJ_SHIFT 8 66 #define OMAP_UART_MVR_MIN_MASK 0x3f 67 68 /* SYSC register bitmasks */ 69 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 70 71 /* SYSS register bitmasks */ 72 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 73 74 #define UART_TI752_TLR_TX 0 75 #define UART_TI752_TLR_RX 4 76 77 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 78 #define TRIGGER_FCR_MASK(x) (x & 3) 79 80 /* Enable XON/XOFF flow control on output */ 81 #define OMAP_UART_SW_TX 0x08 82 /* Enable XON/XOFF flow control on input */ 83 #define OMAP_UART_SW_RX 0x02 84 85 #define OMAP_UART_WER_MOD_WKUP 0x7f 86 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 87 88 #define TX_TRIGGER 1 89 #define RX_TRIGGER 48 90 91 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 92 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 93 94 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 95 96 #define OMAP_UART_REV_46 0x0406 97 #define OMAP_UART_REV_52 0x0502 98 #define OMAP_UART_REV_63 0x0603 99 100 /* Interrupt Enable Register 2 */ 101 #define UART_OMAP_IER2 0x1B 102 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2) 103 104 /* Enhanced features register 2 */ 105 #define UART_OMAP_EFR2 0x23 106 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6) 107 108 /* RX FIFO occupancy indicator */ 109 #define UART_OMAP_RX_LVL 0x19 110 111 struct omap8250_priv { 112 int line; 113 u8 habit; 114 u8 mdr1; 115 u8 efr; 116 u8 scr; 117 u8 wer; 118 u8 xon; 119 u8 xoff; 120 u8 delayed_restore; 121 u16 quot; 122 123 u8 tx_trigger; 124 u8 rx_trigger; 125 bool is_suspending; 126 int wakeirq; 127 int wakeups_enabled; 128 u32 latency; 129 u32 calc_latency; 130 struct pm_qos_request pm_qos_request; 131 struct work_struct qos_work; 132 struct uart_8250_dma omap8250_dma; 133 spinlock_t rx_dma_lock; 134 bool rx_dma_broken; 135 bool throttled; 136 }; 137 138 struct omap8250_dma_params { 139 u32 rx_size; 140 u8 rx_trigger; 141 u8 tx_trigger; 142 }; 143 144 struct omap8250_platdata { 145 struct omap8250_dma_params *dma_params; 146 u8 habit; 147 }; 148 149 #ifdef CONFIG_SERIAL_8250_DMA 150 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 151 #else 152 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 153 #endif 154 155 static u32 uart_read(struct uart_8250_port *up, u32 reg) 156 { 157 return readl(up->port.membase + (reg << up->port.regshift)); 158 } 159 160 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 161 { 162 struct uart_8250_port *up = up_to_u8250p(port); 163 struct omap8250_priv *priv = up->port.private_data; 164 u8 lcr; 165 166 serial8250_do_set_mctrl(port, mctrl); 167 168 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { 169 /* 170 * Turn off autoRTS if RTS is lowered and restore autoRTS 171 * setting if RTS is raised 172 */ 173 lcr = serial_in(up, UART_LCR); 174 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 175 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 176 priv->efr |= UART_EFR_RTS; 177 else 178 priv->efr &= ~UART_EFR_RTS; 179 serial_out(up, UART_EFR, priv->efr); 180 serial_out(up, UART_LCR, lcr); 181 } 182 } 183 184 /* 185 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 186 * The access to uart register after MDR1 Access 187 * causes UART to corrupt data. 188 * 189 * Need a delay = 190 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 191 * give 10 times as much 192 */ 193 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 194 struct omap8250_priv *priv) 195 { 196 u8 timeout = 255; 197 198 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 199 udelay(2); 200 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 201 UART_FCR_CLEAR_RCVR); 202 /* 203 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 204 * TX_FIFO_E bit is 1. 205 */ 206 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 207 (UART_LSR_THRE | UART_LSR_DR))) { 208 timeout--; 209 if (!timeout) { 210 /* Should *never* happen. we warn and carry on */ 211 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 212 serial_in(up, UART_LSR)); 213 break; 214 } 215 udelay(1); 216 } 217 } 218 219 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 220 struct omap8250_priv *priv) 221 { 222 unsigned int uartclk = port->uartclk; 223 unsigned int div_13, div_16; 224 unsigned int abs_d13, abs_d16; 225 226 /* 227 * Old custom speed handling. 228 */ 229 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 230 priv->quot = port->custom_divisor & UART_DIV_MAX; 231 /* 232 * I assume that nobody is using this. But hey, if somebody 233 * would like to specify the divisor _and_ the mode then the 234 * driver is ready and waiting for it. 235 */ 236 if (port->custom_divisor & (1 << 16)) 237 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 238 else 239 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 240 return; 241 } 242 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 243 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 244 245 if (!div_13) 246 div_13 = 1; 247 if (!div_16) 248 div_16 = 1; 249 250 abs_d13 = abs(baud - uartclk / 13 / div_13); 251 abs_d16 = abs(baud - uartclk / 16 / div_16); 252 253 if (abs_d13 >= abs_d16) { 254 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 255 priv->quot = div_16; 256 } else { 257 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 258 priv->quot = div_13; 259 } 260 } 261 262 static void omap8250_update_scr(struct uart_8250_port *up, 263 struct omap8250_priv *priv) 264 { 265 u8 old_scr; 266 267 old_scr = serial_in(up, UART_OMAP_SCR); 268 if (old_scr == priv->scr) 269 return; 270 271 /* 272 * The manual recommends not to enable the DMA mode selector in the SCR 273 * (instead of the FCR) register _and_ selecting the DMA mode as one 274 * register write because this may lead to malfunction. 275 */ 276 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 277 serial_out(up, UART_OMAP_SCR, 278 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 279 serial_out(up, UART_OMAP_SCR, priv->scr); 280 } 281 282 static void omap8250_update_mdr1(struct uart_8250_port *up, 283 struct omap8250_priv *priv) 284 { 285 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 286 omap_8250_mdr1_errataset(up, priv); 287 else 288 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 289 } 290 291 static void omap8250_restore_regs(struct uart_8250_port *up) 292 { 293 struct omap8250_priv *priv = up->port.private_data; 294 struct uart_8250_dma *dma = up->dma; 295 296 if (dma && dma->tx_running) { 297 /* 298 * TCSANOW requests the change to occur immediately however if 299 * we have a TX-DMA operation in progress then it has been 300 * observed that it might stall and never complete. Therefore we 301 * delay DMA completes to prevent this hang from happen. 302 */ 303 priv->delayed_restore = 1; 304 return; 305 } 306 307 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 308 serial_out(up, UART_EFR, UART_EFR_ECB); 309 310 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 311 serial8250_out_MCR(up, UART_MCR_TCRTLR); 312 serial_out(up, UART_FCR, up->fcr); 313 314 omap8250_update_scr(up, priv); 315 316 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 317 318 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 319 OMAP_UART_TCR_HALT(52)); 320 serial_out(up, UART_TI752_TLR, 321 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX | 322 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX); 323 324 serial_out(up, UART_LCR, 0); 325 326 /* drop TCR + TLR access, we setup XON/XOFF later */ 327 serial8250_out_MCR(up, up->mcr); 328 serial_out(up, UART_IER, up->ier); 329 330 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 331 serial_dl_write(up, priv->quot); 332 333 serial_out(up, UART_EFR, priv->efr); 334 335 /* Configure flow control */ 336 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 337 serial_out(up, UART_XON1, priv->xon); 338 serial_out(up, UART_XOFF1, priv->xoff); 339 340 serial_out(up, UART_LCR, up->lcr); 341 342 omap8250_update_mdr1(up, priv); 343 344 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 345 } 346 347 /* 348 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 349 * some differences in how we want to handle flow control. 350 */ 351 static void omap_8250_set_termios(struct uart_port *port, 352 struct ktermios *termios, 353 struct ktermios *old) 354 { 355 struct uart_8250_port *up = up_to_u8250p(port); 356 struct omap8250_priv *priv = up->port.private_data; 357 unsigned char cval = 0; 358 unsigned int baud; 359 360 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 361 362 if (termios->c_cflag & CSTOPB) 363 cval |= UART_LCR_STOP; 364 if (termios->c_cflag & PARENB) 365 cval |= UART_LCR_PARITY; 366 if (!(termios->c_cflag & PARODD)) 367 cval |= UART_LCR_EPAR; 368 if (termios->c_cflag & CMSPAR) 369 cval |= UART_LCR_SPAR; 370 371 /* 372 * Ask the core to calculate the divisor for us. 373 */ 374 baud = uart_get_baud_rate(port, termios, old, 375 port->uartclk / 16 / UART_DIV_MAX, 376 port->uartclk / 13); 377 omap_8250_get_divisor(port, baud, priv); 378 379 /* 380 * Ok, we're now changing the port state. Do it with 381 * interrupts disabled. 382 */ 383 pm_runtime_get_sync(port->dev); 384 spin_lock_irq(&port->lock); 385 386 /* 387 * Update the per-port timeout. 388 */ 389 uart_update_timeout(port, termios->c_cflag, baud); 390 391 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 392 if (termios->c_iflag & INPCK) 393 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 394 if (termios->c_iflag & (IGNBRK | PARMRK)) 395 up->port.read_status_mask |= UART_LSR_BI; 396 397 /* 398 * Characters to ignore 399 */ 400 up->port.ignore_status_mask = 0; 401 if (termios->c_iflag & IGNPAR) 402 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 403 if (termios->c_iflag & IGNBRK) { 404 up->port.ignore_status_mask |= UART_LSR_BI; 405 /* 406 * If we're ignoring parity and break indicators, 407 * ignore overruns too (for real raw support). 408 */ 409 if (termios->c_iflag & IGNPAR) 410 up->port.ignore_status_mask |= UART_LSR_OE; 411 } 412 413 /* 414 * ignore all characters if CREAD is not set 415 */ 416 if ((termios->c_cflag & CREAD) == 0) 417 up->port.ignore_status_mask |= UART_LSR_DR; 418 419 /* 420 * Modem status interrupts 421 */ 422 up->ier &= ~UART_IER_MSI; 423 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 424 up->ier |= UART_IER_MSI; 425 426 up->lcr = cval; 427 /* Up to here it was mostly serial8250_do_set_termios() */ 428 429 /* 430 * We enable TRIG_GRANU for RX and TX and additionally we set 431 * SCR_TX_EMPTY bit. The result is the following: 432 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 433 * - less than RX_TRIGGER number of bytes will also cause an interrupt 434 * once the UART decides that there no new bytes arriving. 435 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 436 * empty - the trigger level is ignored here. 437 * 438 * Once DMA is enabled: 439 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 440 * bytes in the TX FIFO. On each assert the DMA engine will move 441 * TX_TRIGGER bytes into the FIFO. 442 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 443 * the FIFO and move RX_TRIGGER bytes. 444 * This is because threshold and trigger values are the same. 445 */ 446 up->fcr = UART_FCR_ENABLE_FIFO; 447 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG; 448 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG; 449 450 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 451 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 452 453 if (up->dma) 454 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 455 OMAP_UART_SCR_DMAMODE_CTL; 456 457 priv->xon = termios->c_cc[VSTART]; 458 priv->xoff = termios->c_cc[VSTOP]; 459 460 priv->efr = 0; 461 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 462 463 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && 464 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && 465 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { 466 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 467 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 468 priv->efr |= UART_EFR_CTS; 469 } else if (up->port.flags & UPF_SOFT_FLOW) { 470 /* 471 * OMAP rx s/w flow control is borked; the transmitter remains 472 * stuck off even if rx flow control is subsequently disabled 473 */ 474 475 /* 476 * IXOFF Flag: 477 * Enable XON/XOFF flow control on output. 478 * Transmit XON1, XOFF1 479 */ 480 if (termios->c_iflag & IXOFF) { 481 up->port.status |= UPSTAT_AUTOXOFF; 482 priv->efr |= OMAP_UART_SW_TX; 483 } 484 } 485 omap8250_restore_regs(up); 486 487 spin_unlock_irq(&up->port.lock); 488 pm_runtime_mark_last_busy(port->dev); 489 pm_runtime_put_autosuspend(port->dev); 490 491 /* calculate wakeup latency constraint */ 492 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 493 priv->latency = priv->calc_latency; 494 495 schedule_work(&priv->qos_work); 496 497 /* Don't rewrite B0 */ 498 if (tty_termios_baud_rate(termios)) 499 tty_termios_encode_baud_rate(termios, baud, baud); 500 } 501 502 /* same as 8250 except that we may have extra flow bits set in EFR */ 503 static void omap_8250_pm(struct uart_port *port, unsigned int state, 504 unsigned int oldstate) 505 { 506 struct uart_8250_port *up = up_to_u8250p(port); 507 u8 efr; 508 509 pm_runtime_get_sync(port->dev); 510 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 511 efr = serial_in(up, UART_EFR); 512 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 513 serial_out(up, UART_LCR, 0); 514 515 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 516 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 517 serial_out(up, UART_EFR, efr); 518 serial_out(up, UART_LCR, 0); 519 520 pm_runtime_mark_last_busy(port->dev); 521 pm_runtime_put_autosuspend(port->dev); 522 } 523 524 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 525 struct omap8250_priv *priv) 526 { 527 static const struct soc_device_attribute k3_soc_devices[] = { 528 { .family = "AM65X", }, 529 { .family = "J721E", .revision = "SR1.0" }, 530 { /* sentinel */ } 531 }; 532 u32 mvr, scheme; 533 u16 revision, major, minor; 534 535 mvr = uart_read(up, UART_OMAP_MVER); 536 537 /* Check revision register scheme */ 538 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 539 540 switch (scheme) { 541 case 0: /* Legacy Scheme: OMAP2/3 */ 542 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 543 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 544 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 545 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 546 break; 547 case 1: 548 /* New Scheme: OMAP4+ */ 549 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 550 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 551 OMAP_UART_MVR_MAJ_SHIFT; 552 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 553 break; 554 default: 555 dev_warn(up->port.dev, 556 "Unknown revision, defaulting to highest\n"); 557 /* highest possible revision */ 558 major = 0xff; 559 minor = 0xff; 560 } 561 /* normalize revision for the driver */ 562 revision = UART_BUILD_REVISION(major, minor); 563 564 switch (revision) { 565 case OMAP_UART_REV_46: 566 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 567 break; 568 case OMAP_UART_REV_52: 569 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 570 OMAP_UART_WER_HAS_TX_WAKEUP; 571 break; 572 case OMAP_UART_REV_63: 573 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 574 OMAP_UART_WER_HAS_TX_WAKEUP; 575 break; 576 default: 577 break; 578 } 579 580 /* 581 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't 582 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag 583 * to enable errata workaround. 584 */ 585 if (soc_device_match(k3_soc_devices)) 586 priv->habit &= ~UART_HAS_RHR_IT_DIS; 587 } 588 589 static void omap8250_uart_qos_work(struct work_struct *work) 590 { 591 struct omap8250_priv *priv; 592 593 priv = container_of(work, struct omap8250_priv, qos_work); 594 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency); 595 } 596 597 #ifdef CONFIG_SERIAL_8250_DMA 598 static int omap_8250_dma_handle_irq(struct uart_port *port); 599 #endif 600 601 static irqreturn_t omap8250_irq(int irq, void *dev_id) 602 { 603 struct uart_port *port = dev_id; 604 struct omap8250_priv *priv = port->private_data; 605 struct uart_8250_port *up = up_to_u8250p(port); 606 unsigned int iir, lsr; 607 int ret; 608 609 #ifdef CONFIG_SERIAL_8250_DMA 610 if (up->dma) { 611 ret = omap_8250_dma_handle_irq(port); 612 return IRQ_RETVAL(ret); 613 } 614 #endif 615 616 serial8250_rpm_get(up); 617 lsr = serial_port_in(port, UART_LSR); 618 iir = serial_port_in(port, UART_IIR); 619 ret = serial8250_handle_irq(port, iir); 620 621 /* 622 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after 623 * FIFO has been drained, in which case a dummy read of RX FIFO 624 * is required to clear RX TIMEOUT condition. 625 */ 626 if (priv->habit & UART_RX_TIMEOUT_QUIRK && 627 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT && 628 serial_port_in(port, UART_OMAP_RX_LVL) == 0) { 629 serial_port_in(port, UART_RX); 630 } 631 632 /* Stop processing interrupts on input overrun */ 633 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) { 634 unsigned long delay; 635 636 up->ier = port->serial_in(port, UART_IER); 637 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 638 port->ops->stop_rx(port); 639 } else { 640 /* Keep restarting the timer until 641 * the input overrun subsides. 642 */ 643 cancel_delayed_work(&up->overrun_backoff); 644 } 645 646 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 647 schedule_delayed_work(&up->overrun_backoff, delay); 648 } 649 650 serial8250_rpm_put(up); 651 652 return IRQ_RETVAL(ret); 653 } 654 655 static int omap_8250_startup(struct uart_port *port) 656 { 657 struct uart_8250_port *up = up_to_u8250p(port); 658 struct omap8250_priv *priv = port->private_data; 659 int ret; 660 661 if (priv->wakeirq) { 662 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 663 if (ret) 664 return ret; 665 } 666 667 pm_runtime_get_sync(port->dev); 668 669 up->mcr = 0; 670 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 671 672 serial_out(up, UART_LCR, UART_LCR_WLEN8); 673 674 up->lsr_saved_flags = 0; 675 up->msr_saved_flags = 0; 676 677 /* Disable DMA for console UART */ 678 if (uart_console(port)) 679 up->dma = NULL; 680 681 if (up->dma) { 682 ret = serial8250_request_dma(up); 683 if (ret) { 684 dev_warn_ratelimited(port->dev, 685 "failed to request DMA\n"); 686 up->dma = NULL; 687 } 688 } 689 690 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 691 dev_name(port->dev), port); 692 if (ret < 0) 693 goto err; 694 695 up->ier = UART_IER_RLSI | UART_IER_RDI; 696 serial_out(up, UART_IER, up->ier); 697 698 #ifdef CONFIG_PM 699 up->capabilities |= UART_CAP_RPM; 700 #endif 701 702 /* Enable module level wake up */ 703 priv->wer = OMAP_UART_WER_MOD_WKUP; 704 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 705 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 706 serial_out(up, UART_OMAP_WER, priv->wer); 707 708 if (up->dma && !(priv->habit & UART_HAS_EFR2)) 709 up->dma->rx_dma(up); 710 711 pm_runtime_mark_last_busy(port->dev); 712 pm_runtime_put_autosuspend(port->dev); 713 return 0; 714 err: 715 pm_runtime_mark_last_busy(port->dev); 716 pm_runtime_put_autosuspend(port->dev); 717 dev_pm_clear_wake_irq(port->dev); 718 return ret; 719 } 720 721 static void omap_8250_shutdown(struct uart_port *port) 722 { 723 struct uart_8250_port *up = up_to_u8250p(port); 724 struct omap8250_priv *priv = port->private_data; 725 726 flush_work(&priv->qos_work); 727 if (up->dma) 728 omap_8250_rx_dma_flush(up); 729 730 pm_runtime_get_sync(port->dev); 731 732 serial_out(up, UART_OMAP_WER, 0); 733 if (priv->habit & UART_HAS_EFR2) 734 serial_out(up, UART_OMAP_EFR2, 0x0); 735 736 up->ier = 0; 737 serial_out(up, UART_IER, 0); 738 739 if (up->dma) 740 serial8250_release_dma(up); 741 742 /* 743 * Disable break condition and FIFOs 744 */ 745 if (up->lcr & UART_LCR_SBC) 746 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 747 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 748 749 pm_runtime_mark_last_busy(port->dev); 750 pm_runtime_put_autosuspend(port->dev); 751 free_irq(port->irq, port); 752 dev_pm_clear_wake_irq(port->dev); 753 } 754 755 static void omap_8250_throttle(struct uart_port *port) 756 { 757 struct omap8250_priv *priv = port->private_data; 758 unsigned long flags; 759 760 pm_runtime_get_sync(port->dev); 761 762 spin_lock_irqsave(&port->lock, flags); 763 port->ops->stop_rx(port); 764 priv->throttled = true; 765 spin_unlock_irqrestore(&port->lock, flags); 766 767 pm_runtime_mark_last_busy(port->dev); 768 pm_runtime_put_autosuspend(port->dev); 769 } 770 771 static void omap_8250_unthrottle(struct uart_port *port) 772 { 773 struct omap8250_priv *priv = port->private_data; 774 struct uart_8250_port *up = up_to_u8250p(port); 775 unsigned long flags; 776 777 pm_runtime_get_sync(port->dev); 778 779 spin_lock_irqsave(&port->lock, flags); 780 priv->throttled = false; 781 if (up->dma) 782 up->dma->rx_dma(up); 783 up->ier |= UART_IER_RLSI | UART_IER_RDI; 784 port->read_status_mask |= UART_LSR_DR; 785 serial_out(up, UART_IER, up->ier); 786 spin_unlock_irqrestore(&port->lock, flags); 787 788 pm_runtime_mark_last_busy(port->dev); 789 pm_runtime_put_autosuspend(port->dev); 790 } 791 792 #ifdef CONFIG_SERIAL_8250_DMA 793 static int omap_8250_rx_dma(struct uart_8250_port *p); 794 795 /* Must be called while priv->rx_dma_lock is held */ 796 static void __dma_rx_do_complete(struct uart_8250_port *p) 797 { 798 struct uart_8250_dma *dma = p->dma; 799 struct tty_port *tty_port = &p->port.state->port; 800 struct omap8250_priv *priv = p->port.private_data; 801 struct dma_chan *rxchan = dma->rxchan; 802 dma_cookie_t cookie; 803 struct dma_tx_state state; 804 int count; 805 int ret; 806 u32 reg; 807 808 if (!dma->rx_running) 809 goto out; 810 811 cookie = dma->rx_cookie; 812 dma->rx_running = 0; 813 814 /* Re-enable RX FIFO interrupt now that transfer is complete */ 815 if (priv->habit & UART_HAS_RHR_IT_DIS) { 816 reg = serial_in(p, UART_OMAP_IER2); 817 reg &= ~UART_OMAP_IER2_RHR_IT_DIS; 818 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 819 } 820 821 dmaengine_tx_status(rxchan, cookie, &state); 822 823 count = dma->rx_size - state.residue + state.in_flight_bytes; 824 if (count < dma->rx_size) { 825 dmaengine_terminate_async(rxchan); 826 827 /* 828 * Poll for teardown to complete which guarantees in 829 * flight data is drained. 830 */ 831 if (state.in_flight_bytes) { 832 int poll_count = 25; 833 834 while (dmaengine_tx_status(rxchan, cookie, NULL) && 835 poll_count--) 836 cpu_relax(); 837 838 if (poll_count == -1) 839 dev_err(p->port.dev, "teardown incomplete\n"); 840 } 841 } 842 if (!count) 843 goto out; 844 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 845 846 p->port.icount.rx += ret; 847 p->port.icount.buf_overrun += count - ret; 848 out: 849 850 tty_flip_buffer_push(tty_port); 851 } 852 853 static void __dma_rx_complete(void *param) 854 { 855 struct uart_8250_port *p = param; 856 struct omap8250_priv *priv = p->port.private_data; 857 struct uart_8250_dma *dma = p->dma; 858 struct dma_tx_state state; 859 unsigned long flags; 860 861 spin_lock_irqsave(&p->port.lock, flags); 862 863 /* 864 * If the tx status is not DMA_COMPLETE, then this is a delayed 865 * completion callback. A previous RX timeout flush would have 866 * already pushed the data, so exit. 867 */ 868 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 869 DMA_COMPLETE) { 870 spin_unlock_irqrestore(&p->port.lock, flags); 871 return; 872 } 873 __dma_rx_do_complete(p); 874 if (!priv->throttled) { 875 p->ier |= UART_IER_RLSI | UART_IER_RDI; 876 serial_out(p, UART_IER, p->ier); 877 if (!(priv->habit & UART_HAS_EFR2)) 878 omap_8250_rx_dma(p); 879 } 880 881 spin_unlock_irqrestore(&p->port.lock, flags); 882 } 883 884 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 885 { 886 struct omap8250_priv *priv = p->port.private_data; 887 struct uart_8250_dma *dma = p->dma; 888 struct dma_tx_state state; 889 unsigned long flags; 890 int ret; 891 892 spin_lock_irqsave(&priv->rx_dma_lock, flags); 893 894 if (!dma->rx_running) { 895 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 896 return; 897 } 898 899 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 900 if (ret == DMA_IN_PROGRESS) { 901 ret = dmaengine_pause(dma->rxchan); 902 if (WARN_ON_ONCE(ret)) 903 priv->rx_dma_broken = true; 904 } 905 __dma_rx_do_complete(p); 906 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 907 } 908 909 static int omap_8250_rx_dma(struct uart_8250_port *p) 910 { 911 struct omap8250_priv *priv = p->port.private_data; 912 struct uart_8250_dma *dma = p->dma; 913 int err = 0; 914 struct dma_async_tx_descriptor *desc; 915 unsigned long flags; 916 u32 reg; 917 918 if (priv->rx_dma_broken) 919 return -EINVAL; 920 921 spin_lock_irqsave(&priv->rx_dma_lock, flags); 922 923 if (dma->rx_running) { 924 enum dma_status state; 925 926 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL); 927 if (state == DMA_COMPLETE) { 928 /* 929 * Disable RX interrupts to allow RX DMA completion 930 * callback to run. 931 */ 932 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 933 serial_out(p, UART_IER, p->ier); 934 } 935 goto out; 936 } 937 938 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 939 dma->rx_size, DMA_DEV_TO_MEM, 940 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 941 if (!desc) { 942 err = -EBUSY; 943 goto out; 944 } 945 946 dma->rx_running = 1; 947 desc->callback = __dma_rx_complete; 948 desc->callback_param = p; 949 950 dma->rx_cookie = dmaengine_submit(desc); 951 952 /* 953 * Disable RX FIFO interrupt while RX DMA is enabled, else 954 * spurious interrupt may be raised when data is in the RX FIFO 955 * but is yet to be drained by DMA. 956 */ 957 if (priv->habit & UART_HAS_RHR_IT_DIS) { 958 reg = serial_in(p, UART_OMAP_IER2); 959 reg |= UART_OMAP_IER2_RHR_IT_DIS; 960 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS); 961 } 962 963 dma_async_issue_pending(dma->rxchan); 964 out: 965 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 966 return err; 967 } 968 969 static int omap_8250_tx_dma(struct uart_8250_port *p); 970 971 static void omap_8250_dma_tx_complete(void *param) 972 { 973 struct uart_8250_port *p = param; 974 struct uart_8250_dma *dma = p->dma; 975 struct circ_buf *xmit = &p->port.state->xmit; 976 unsigned long flags; 977 bool en_thri = false; 978 struct omap8250_priv *priv = p->port.private_data; 979 980 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 981 UART_XMIT_SIZE, DMA_TO_DEVICE); 982 983 spin_lock_irqsave(&p->port.lock, flags); 984 985 dma->tx_running = 0; 986 987 xmit->tail += dma->tx_size; 988 xmit->tail &= UART_XMIT_SIZE - 1; 989 p->port.icount.tx += dma->tx_size; 990 991 if (priv->delayed_restore) { 992 priv->delayed_restore = 0; 993 omap8250_restore_regs(p); 994 } 995 996 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 997 uart_write_wakeup(&p->port); 998 999 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 1000 int ret; 1001 1002 ret = omap_8250_tx_dma(p); 1003 if (ret) 1004 en_thri = true; 1005 } else if (p->capabilities & UART_CAP_RPM) { 1006 en_thri = true; 1007 } 1008 1009 if (en_thri) { 1010 dma->tx_err = 1; 1011 serial8250_set_THRI(p); 1012 } 1013 1014 spin_unlock_irqrestore(&p->port.lock, flags); 1015 } 1016 1017 static int omap_8250_tx_dma(struct uart_8250_port *p) 1018 { 1019 struct uart_8250_dma *dma = p->dma; 1020 struct omap8250_priv *priv = p->port.private_data; 1021 struct circ_buf *xmit = &p->port.state->xmit; 1022 struct dma_async_tx_descriptor *desc; 1023 unsigned int skip_byte = 0; 1024 int ret; 1025 1026 if (dma->tx_running) 1027 return 0; 1028 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 1029 1030 /* 1031 * Even if no data, we need to return an error for the two cases 1032 * below so serial8250_tx_chars() is invoked and properly clears 1033 * THRI and/or runtime suspend. 1034 */ 1035 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 1036 ret = -EBUSY; 1037 goto err; 1038 } 1039 serial8250_clear_THRI(p); 1040 return 0; 1041 } 1042 1043 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 1044 if (priv->habit & OMAP_DMA_TX_KICK) { 1045 u8 tx_lvl; 1046 1047 /* 1048 * We need to put the first byte into the FIFO in order to start 1049 * the DMA transfer. For transfers smaller than four bytes we 1050 * don't bother doing DMA at all. It seem not matter if there 1051 * are still bytes in the FIFO from the last transfer (in case 1052 * we got here directly from omap_8250_dma_tx_complete()). Bytes 1053 * leaving the FIFO seem not to trigger the DMA transfer. It is 1054 * really the byte that we put into the FIFO. 1055 * If the FIFO is already full then we most likely got here from 1056 * omap_8250_dma_tx_complete(). And this means the DMA engine 1057 * just completed its work. We don't have to wait the complete 1058 * 86us at 115200,8n1 but around 60us (not to mention lower 1059 * baudrates). So in that case we take the interrupt and try 1060 * again with an empty FIFO. 1061 */ 1062 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 1063 if (tx_lvl == p->tx_loadsz) { 1064 ret = -EBUSY; 1065 goto err; 1066 } 1067 if (dma->tx_size < 4) { 1068 ret = -EINVAL; 1069 goto err; 1070 } 1071 skip_byte = 1; 1072 } 1073 1074 desc = dmaengine_prep_slave_single(dma->txchan, 1075 dma->tx_addr + xmit->tail + skip_byte, 1076 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 1077 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1078 if (!desc) { 1079 ret = -EBUSY; 1080 goto err; 1081 } 1082 1083 dma->tx_running = 1; 1084 1085 desc->callback = omap_8250_dma_tx_complete; 1086 desc->callback_param = p; 1087 1088 dma->tx_cookie = dmaengine_submit(desc); 1089 1090 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1091 UART_XMIT_SIZE, DMA_TO_DEVICE); 1092 1093 dma_async_issue_pending(dma->txchan); 1094 if (dma->tx_err) 1095 dma->tx_err = 0; 1096 1097 serial8250_clear_THRI(p); 1098 if (skip_byte) 1099 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1100 return 0; 1101 err: 1102 dma->tx_err = 1; 1103 return ret; 1104 } 1105 1106 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1107 { 1108 switch (iir & 0x3f) { 1109 case UART_IIR_RLSI: 1110 case UART_IIR_RX_TIMEOUT: 1111 case UART_IIR_RDI: 1112 omap_8250_rx_dma_flush(up); 1113 return true; 1114 } 1115 return omap_8250_rx_dma(up); 1116 } 1117 1118 static unsigned char omap_8250_handle_rx_dma(struct uart_8250_port *up, 1119 u8 iir, unsigned char status) 1120 { 1121 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1122 (iir & UART_IIR_RDI)) { 1123 if (handle_rx_dma(up, iir)) { 1124 status = serial8250_rx_chars(up, status); 1125 omap_8250_rx_dma(up); 1126 } 1127 } 1128 1129 return status; 1130 } 1131 1132 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, 1133 unsigned char status) 1134 { 1135 /* 1136 * Queue a new transfer if FIFO has data. 1137 */ 1138 if ((status & (UART_LSR_DR | UART_LSR_BI)) && 1139 (up->ier & UART_IER_RDI)) { 1140 omap_8250_rx_dma(up); 1141 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE); 1142 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) { 1143 /* 1144 * Disable RX timeout, read IIR to clear 1145 * current timeout condition, clear EFR2 to 1146 * periodic timeouts, re-enable interrupts. 1147 */ 1148 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1149 serial_out(up, UART_IER, up->ier); 1150 omap_8250_rx_dma_flush(up); 1151 serial_in(up, UART_IIR); 1152 serial_out(up, UART_OMAP_EFR2, 0x0); 1153 up->ier |= UART_IER_RLSI | UART_IER_RDI; 1154 serial_out(up, UART_IER, up->ier); 1155 } 1156 } 1157 1158 /* 1159 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1160 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1161 * use the default routine in the non-DMA case and this one for with DMA. 1162 */ 1163 static int omap_8250_dma_handle_irq(struct uart_port *port) 1164 { 1165 struct uart_8250_port *up = up_to_u8250p(port); 1166 struct omap8250_priv *priv = up->port.private_data; 1167 unsigned char status; 1168 u8 iir; 1169 1170 serial8250_rpm_get(up); 1171 1172 iir = serial_port_in(port, UART_IIR); 1173 if (iir & UART_IIR_NO_INT) { 1174 serial8250_rpm_put(up); 1175 return IRQ_HANDLED; 1176 } 1177 1178 spin_lock(&port->lock); 1179 1180 status = serial_port_in(port, UART_LSR); 1181 1182 if (priv->habit & UART_HAS_EFR2) 1183 am654_8250_handle_rx_dma(up, iir, status); 1184 else 1185 status = omap_8250_handle_rx_dma(up, iir, status); 1186 1187 serial8250_modem_status(up); 1188 if (status & UART_LSR_THRE && up->dma->tx_err) { 1189 if (uart_tx_stopped(&up->port) || 1190 uart_circ_empty(&up->port.state->xmit)) { 1191 up->dma->tx_err = 0; 1192 serial8250_tx_chars(up); 1193 } else { 1194 /* 1195 * try again due to an earlier failer which 1196 * might have been resolved by now. 1197 */ 1198 if (omap_8250_tx_dma(up)) 1199 serial8250_tx_chars(up); 1200 } 1201 } 1202 1203 uart_unlock_and_check_sysrq(port); 1204 1205 serial8250_rpm_put(up); 1206 return 1; 1207 } 1208 1209 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1210 { 1211 return false; 1212 } 1213 1214 #else 1215 1216 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1217 { 1218 return -EINVAL; 1219 } 1220 #endif 1221 1222 static int omap8250_no_handle_irq(struct uart_port *port) 1223 { 1224 /* IRQ has not been requested but handling irq? */ 1225 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1226 return 0; 1227 } 1228 1229 static struct omap8250_dma_params am654_dma = { 1230 .rx_size = SZ_2K, 1231 .rx_trigger = 1, 1232 .tx_trigger = TX_TRIGGER, 1233 }; 1234 1235 static struct omap8250_dma_params am33xx_dma = { 1236 .rx_size = RX_TRIGGER, 1237 .rx_trigger = RX_TRIGGER, 1238 .tx_trigger = TX_TRIGGER, 1239 }; 1240 1241 static struct omap8250_platdata am654_platdata = { 1242 .dma_params = &am654_dma, 1243 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS | 1244 UART_RX_TIMEOUT_QUIRK, 1245 }; 1246 1247 static struct omap8250_platdata am33xx_platdata = { 1248 .dma_params = &am33xx_dma, 1249 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE, 1250 }; 1251 1252 static struct omap8250_platdata omap4_platdata = { 1253 .dma_params = &am33xx_dma, 1254 .habit = UART_ERRATA_CLOCK_DISABLE, 1255 }; 1256 1257 static const struct of_device_id omap8250_dt_ids[] = { 1258 { .compatible = "ti,am654-uart", .data = &am654_platdata, }, 1259 { .compatible = "ti,omap2-uart" }, 1260 { .compatible = "ti,omap3-uart" }, 1261 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, }, 1262 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, }, 1263 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, }, 1264 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, }, 1265 {}, 1266 }; 1267 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1268 1269 static int omap8250_probe(struct platform_device *pdev) 1270 { 1271 struct device_node *np = pdev->dev.of_node; 1272 struct omap8250_priv *priv; 1273 const struct omap8250_platdata *pdata; 1274 struct uart_8250_port up; 1275 struct resource *regs; 1276 void __iomem *membase; 1277 int irq, ret; 1278 1279 irq = platform_get_irq(pdev, 0); 1280 if (irq < 0) 1281 return irq; 1282 1283 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1284 if (!regs) { 1285 dev_err(&pdev->dev, "missing registers\n"); 1286 return -EINVAL; 1287 } 1288 1289 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1290 if (!priv) 1291 return -ENOMEM; 1292 1293 membase = devm_ioremap(&pdev->dev, regs->start, 1294 resource_size(regs)); 1295 if (!membase) 1296 return -ENODEV; 1297 1298 memset(&up, 0, sizeof(up)); 1299 up.port.dev = &pdev->dev; 1300 up.port.mapbase = regs->start; 1301 up.port.membase = membase; 1302 up.port.irq = irq; 1303 /* 1304 * It claims to be 16C750 compatible however it is a little different. 1305 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1306 * have) is enabled via EFR instead of MCR. The type is set here 8250 1307 * just to get things going. UNKNOWN does not work for a few reasons and 1308 * we don't need our own type since we don't use 8250's set_termios() 1309 * or pm callback. 1310 */ 1311 up.port.type = PORT_8250; 1312 up.port.iotype = UPIO_MEM; 1313 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1314 UPF_HARD_FLOW; 1315 up.port.private_data = priv; 1316 1317 up.port.regshift = 2; 1318 up.port.fifosize = 64; 1319 up.tx_loadsz = 64; 1320 up.capabilities = UART_CAP_FIFO; 1321 #ifdef CONFIG_PM 1322 /* 1323 * Runtime PM is mostly transparent. However to do it right we need to a 1324 * TX empty interrupt before we can put the device to auto idle. So if 1325 * PM is not enabled we don't add that flag and can spare that one extra 1326 * interrupt in the TX path. 1327 */ 1328 up.capabilities |= UART_CAP_RPM; 1329 #endif 1330 up.port.set_termios = omap_8250_set_termios; 1331 up.port.set_mctrl = omap8250_set_mctrl; 1332 up.port.pm = omap_8250_pm; 1333 up.port.startup = omap_8250_startup; 1334 up.port.shutdown = omap_8250_shutdown; 1335 up.port.throttle = omap_8250_throttle; 1336 up.port.unthrottle = omap_8250_unthrottle; 1337 up.port.rs485_config = serial8250_em485_config; 1338 up.rs485_start_tx = serial8250_em485_start_tx; 1339 up.rs485_stop_tx = serial8250_em485_stop_tx; 1340 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 1341 1342 ret = of_alias_get_id(np, "serial"); 1343 if (ret < 0) { 1344 dev_err(&pdev->dev, "failed to get alias\n"); 1345 return ret; 1346 } 1347 up.port.line = ret; 1348 1349 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { 1350 struct clk *clk; 1351 1352 clk = devm_clk_get(&pdev->dev, NULL); 1353 if (IS_ERR(clk)) { 1354 if (PTR_ERR(clk) == -EPROBE_DEFER) 1355 return -EPROBE_DEFER; 1356 } else { 1357 up.port.uartclk = clk_get_rate(clk); 1358 } 1359 } 1360 1361 if (of_property_read_u32(np, "overrun-throttle-ms", 1362 &up.overrun_backoff_time_ms) != 0) 1363 up.overrun_backoff_time_ms = 0; 1364 1365 priv->wakeirq = irq_of_parse_and_map(np, 1); 1366 1367 pdata = of_device_get_match_data(&pdev->dev); 1368 if (pdata) 1369 priv->habit |= pdata->habit; 1370 1371 if (!up.port.uartclk) { 1372 up.port.uartclk = DEFAULT_CLK_SPEED; 1373 dev_warn(&pdev->dev, 1374 "No clock speed specified: using default: %d\n", 1375 DEFAULT_CLK_SPEED); 1376 } 1377 1378 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1379 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1380 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency); 1381 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1382 1383 spin_lock_init(&priv->rx_dma_lock); 1384 1385 device_init_wakeup(&pdev->dev, true); 1386 pm_runtime_enable(&pdev->dev); 1387 pm_runtime_use_autosuspend(&pdev->dev); 1388 1389 /* 1390 * Disable runtime PM until autosuspend delay unless specifically 1391 * enabled by the user via sysfs. This is the historic way to 1392 * prevent an unsafe default policy with lossy characters on wake-up. 1393 * For serdev devices this is not needed, the policy can be managed by 1394 * the serdev driver. 1395 */ 1396 if (!of_get_available_child_count(pdev->dev.of_node)) 1397 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1398 1399 pm_runtime_irq_safe(&pdev->dev); 1400 1401 pm_runtime_get_sync(&pdev->dev); 1402 1403 omap_serial_fill_features_erratas(&up, priv); 1404 up.port.handle_irq = omap8250_no_handle_irq; 1405 priv->rx_trigger = RX_TRIGGER; 1406 priv->tx_trigger = TX_TRIGGER; 1407 #ifdef CONFIG_SERIAL_8250_DMA 1408 /* 1409 * Oh DMA support. If there are no DMA properties in the DT then 1410 * we will fall back to a generic DMA channel which does not 1411 * really work here. To ensure that we do not get a generic DMA 1412 * channel assigned, we have the the_no_dma_filter_fn() here. 1413 * To avoid "failed to request DMA" messages we check for DMA 1414 * properties in DT. 1415 */ 1416 ret = of_property_count_strings(np, "dma-names"); 1417 if (ret == 2) { 1418 struct omap8250_dma_params *dma_params = NULL; 1419 1420 up.dma = &priv->omap8250_dma; 1421 up.dma->fn = the_no_dma_filter_fn; 1422 up.dma->tx_dma = omap_8250_tx_dma; 1423 up.dma->rx_dma = omap_8250_rx_dma; 1424 if (pdata) 1425 dma_params = pdata->dma_params; 1426 1427 if (dma_params) { 1428 up.dma->rx_size = dma_params->rx_size; 1429 up.dma->rxconf.src_maxburst = dma_params->rx_trigger; 1430 up.dma->txconf.dst_maxburst = dma_params->tx_trigger; 1431 priv->rx_trigger = dma_params->rx_trigger; 1432 priv->tx_trigger = dma_params->tx_trigger; 1433 } else { 1434 up.dma->rx_size = RX_TRIGGER; 1435 up.dma->rxconf.src_maxburst = RX_TRIGGER; 1436 up.dma->txconf.dst_maxburst = TX_TRIGGER; 1437 } 1438 } 1439 #endif 1440 ret = serial8250_register_8250_port(&up); 1441 if (ret < 0) { 1442 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1443 goto err; 1444 } 1445 priv->line = ret; 1446 platform_set_drvdata(pdev, priv); 1447 pm_runtime_mark_last_busy(&pdev->dev); 1448 pm_runtime_put_autosuspend(&pdev->dev); 1449 return 0; 1450 err: 1451 pm_runtime_dont_use_autosuspend(&pdev->dev); 1452 pm_runtime_put_sync(&pdev->dev); 1453 pm_runtime_disable(&pdev->dev); 1454 return ret; 1455 } 1456 1457 static int omap8250_remove(struct platform_device *pdev) 1458 { 1459 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1460 1461 pm_runtime_dont_use_autosuspend(&pdev->dev); 1462 pm_runtime_put_sync(&pdev->dev); 1463 pm_runtime_disable(&pdev->dev); 1464 serial8250_unregister_port(priv->line); 1465 cpu_latency_qos_remove_request(&priv->pm_qos_request); 1466 device_init_wakeup(&pdev->dev, false); 1467 return 0; 1468 } 1469 1470 #ifdef CONFIG_PM_SLEEP 1471 static int omap8250_prepare(struct device *dev) 1472 { 1473 struct omap8250_priv *priv = dev_get_drvdata(dev); 1474 1475 if (!priv) 1476 return 0; 1477 priv->is_suspending = true; 1478 return 0; 1479 } 1480 1481 static void omap8250_complete(struct device *dev) 1482 { 1483 struct omap8250_priv *priv = dev_get_drvdata(dev); 1484 1485 if (!priv) 1486 return; 1487 priv->is_suspending = false; 1488 } 1489 1490 static int omap8250_suspend(struct device *dev) 1491 { 1492 struct omap8250_priv *priv = dev_get_drvdata(dev); 1493 struct uart_8250_port *up = serial8250_get_port(priv->line); 1494 1495 serial8250_suspend_port(priv->line); 1496 1497 pm_runtime_get_sync(dev); 1498 if (!device_may_wakeup(dev)) 1499 priv->wer = 0; 1500 serial_out(up, UART_OMAP_WER, priv->wer); 1501 pm_runtime_mark_last_busy(dev); 1502 pm_runtime_put_autosuspend(dev); 1503 1504 flush_work(&priv->qos_work); 1505 return 0; 1506 } 1507 1508 static int omap8250_resume(struct device *dev) 1509 { 1510 struct omap8250_priv *priv = dev_get_drvdata(dev); 1511 1512 serial8250_resume_port(priv->line); 1513 return 0; 1514 } 1515 #else 1516 #define omap8250_prepare NULL 1517 #define omap8250_complete NULL 1518 #endif 1519 1520 #ifdef CONFIG_PM 1521 static int omap8250_lost_context(struct uart_8250_port *up) 1522 { 1523 u32 val; 1524 1525 val = serial_in(up, UART_OMAP_SCR); 1526 /* 1527 * If we lose context, then SCR is set to its reset value of zero. 1528 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1529 * among other bits, to never set the register back to zero again. 1530 */ 1531 if (!val) 1532 return 1; 1533 return 0; 1534 } 1535 1536 /* TODO: in future, this should happen via API in drivers/reset/ */ 1537 static int omap8250_soft_reset(struct device *dev) 1538 { 1539 struct omap8250_priv *priv = dev_get_drvdata(dev); 1540 struct uart_8250_port *up = serial8250_get_port(priv->line); 1541 int timeout = 100; 1542 int sysc; 1543 int syss; 1544 1545 /* 1546 * At least on omap4, unused uarts may not idle after reset without 1547 * a basic scr dma configuration even with no dma in use. The 1548 * module clkctrl status bits will be 1 instead of 3 blocking idle 1549 * for the whole clockdomain. The softreset below will clear scr, 1550 * and we restore it on resume so this is safe to do on all SoCs 1551 * needing omap8250_soft_reset() quirk. Do it in two writes as 1552 * recommended in the comment for omap8250_update_scr(). 1553 */ 1554 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1555 serial_out(up, UART_OMAP_SCR, 1556 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1557 1558 sysc = serial_in(up, UART_OMAP_SYSC); 1559 1560 /* softreset the UART */ 1561 sysc |= OMAP_UART_SYSC_SOFTRESET; 1562 serial_out(up, UART_OMAP_SYSC, sysc); 1563 1564 /* By experiments, 1us enough for reset complete on AM335x */ 1565 do { 1566 udelay(1); 1567 syss = serial_in(up, UART_OMAP_SYSS); 1568 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1569 1570 if (!timeout) { 1571 dev_err(dev, "timed out waiting for reset done\n"); 1572 return -ETIMEDOUT; 1573 } 1574 1575 return 0; 1576 } 1577 1578 static int omap8250_runtime_suspend(struct device *dev) 1579 { 1580 struct omap8250_priv *priv = dev_get_drvdata(dev); 1581 struct uart_8250_port *up; 1582 1583 /* In case runtime-pm tries this before we are setup */ 1584 if (!priv) 1585 return 0; 1586 1587 up = serial8250_get_port(priv->line); 1588 /* 1589 * When using 'no_console_suspend', the console UART must not be 1590 * suspended. Since driver suspend is managed by runtime suspend, 1591 * preventing runtime suspend (by returning error) will keep device 1592 * active during suspend. 1593 */ 1594 if (priv->is_suspending && !console_suspend_enabled) { 1595 if (uart_console(&up->port)) 1596 return -EBUSY; 1597 } 1598 1599 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1600 int ret; 1601 1602 ret = omap8250_soft_reset(dev); 1603 if (ret) 1604 return ret; 1605 1606 /* Restore to UART mode after reset (for wakeup) */ 1607 omap8250_update_mdr1(up, priv); 1608 /* Restore wakeup enable register */ 1609 serial_out(up, UART_OMAP_WER, priv->wer); 1610 } 1611 1612 if (up->dma && up->dma->rxchan) 1613 omap_8250_rx_dma_flush(up); 1614 1615 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1616 schedule_work(&priv->qos_work); 1617 1618 return 0; 1619 } 1620 1621 static int omap8250_runtime_resume(struct device *dev) 1622 { 1623 struct omap8250_priv *priv = dev_get_drvdata(dev); 1624 struct uart_8250_port *up; 1625 1626 /* In case runtime-pm tries this before we are setup */ 1627 if (!priv) 1628 return 0; 1629 1630 up = serial8250_get_port(priv->line); 1631 1632 if (omap8250_lost_context(up)) 1633 omap8250_restore_regs(up); 1634 1635 if (up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) 1636 omap_8250_rx_dma(up); 1637 1638 priv->latency = priv->calc_latency; 1639 schedule_work(&priv->qos_work); 1640 return 0; 1641 } 1642 #endif 1643 1644 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1645 static int __init omap8250_console_fixup(void) 1646 { 1647 char *omap_str; 1648 char *options; 1649 u8 idx; 1650 1651 if (strstr(boot_command_line, "console=ttyS")) 1652 /* user set a ttyS based name for the console */ 1653 return 0; 1654 1655 omap_str = strstr(boot_command_line, "console=ttyO"); 1656 if (!omap_str) 1657 /* user did not set ttyO based console, so we don't care */ 1658 return 0; 1659 1660 omap_str += 12; 1661 if ('0' <= *omap_str && *omap_str <= '9') 1662 idx = *omap_str - '0'; 1663 else 1664 return 0; 1665 1666 omap_str++; 1667 if (omap_str[0] == ',') { 1668 omap_str++; 1669 options = omap_str; 1670 } else { 1671 options = NULL; 1672 } 1673 1674 add_preferred_console("ttyS", idx, options); 1675 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1676 idx, idx); 1677 pr_err("This ensures that you still see kernel messages. Please\n"); 1678 pr_err("update your kernel commandline.\n"); 1679 return 0; 1680 } 1681 console_initcall(omap8250_console_fixup); 1682 #endif 1683 1684 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1685 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1686 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1687 omap8250_runtime_resume, NULL) 1688 .prepare = omap8250_prepare, 1689 .complete = omap8250_complete, 1690 }; 1691 1692 static struct platform_driver omap8250_platform_driver = { 1693 .driver = { 1694 .name = "omap8250", 1695 .pm = &omap8250_dev_pm_ops, 1696 .of_match_table = omap8250_dt_ids, 1697 }, 1698 .probe = omap8250_probe, 1699 .remove = omap8250_remove, 1700 }; 1701 module_platform_driver(omap8250_platform_driver); 1702 1703 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1704 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1705 MODULE_LICENSE("GPL v2"); 1706