1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 8250-core based driver for the OMAP internal UART 4 * 5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 6 * 7 * Copyright (C) 2014 Sebastian Andrzej Siewior 8 * 9 */ 10 11 #include <linux/device.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/serial_8250.h> 15 #include <linux/serial_reg.h> 16 #include <linux/tty_flip.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_irq.h> 23 #include <linux/delay.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/console.h> 26 #include <linux/pm_qos.h> 27 #include <linux/pm_wakeirq.h> 28 #include <linux/dma-mapping.h> 29 30 #include "8250.h" 31 32 #define DEFAULT_CLK_SPEED 48000000 33 34 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 35 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 36 #define OMAP_DMA_TX_KICK (1 << 2) 37 /* 38 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 39 * The same errata is applicable to AM335x and DRA7x processors too. 40 */ 41 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 42 43 #define OMAP_UART_FCR_RX_TRIG 6 44 #define OMAP_UART_FCR_TX_TRIG 4 45 46 /* SCR register bitmasks */ 47 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 48 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 49 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 50 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 51 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 52 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 53 54 /* MVR register bitmasks */ 55 #define OMAP_UART_MVR_SCHEME_SHIFT 30 56 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 57 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 58 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 59 #define OMAP_UART_MVR_MAJ_MASK 0x700 60 #define OMAP_UART_MVR_MAJ_SHIFT 8 61 #define OMAP_UART_MVR_MIN_MASK 0x3f 62 63 /* SYSC register bitmasks */ 64 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 65 66 /* SYSS register bitmasks */ 67 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 68 69 #define UART_TI752_TLR_TX 0 70 #define UART_TI752_TLR_RX 4 71 72 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 73 #define TRIGGER_FCR_MASK(x) (x & 3) 74 75 /* Enable XON/XOFF flow control on output */ 76 #define OMAP_UART_SW_TX 0x08 77 /* Enable XON/XOFF flow control on input */ 78 #define OMAP_UART_SW_RX 0x02 79 80 #define OMAP_UART_WER_MOD_WKUP 0x7f 81 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 82 83 #define TX_TRIGGER 1 84 #define RX_TRIGGER 48 85 86 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 87 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 88 89 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 90 91 #define OMAP_UART_REV_46 0x0406 92 #define OMAP_UART_REV_52 0x0502 93 #define OMAP_UART_REV_63 0x0603 94 95 struct omap8250_priv { 96 int line; 97 u8 habit; 98 u8 mdr1; 99 u8 efr; 100 u8 scr; 101 u8 wer; 102 u8 xon; 103 u8 xoff; 104 u8 delayed_restore; 105 u16 quot; 106 107 bool is_suspending; 108 int wakeirq; 109 int wakeups_enabled; 110 u32 latency; 111 u32 calc_latency; 112 struct pm_qos_request pm_qos_request; 113 struct work_struct qos_work; 114 struct uart_8250_dma omap8250_dma; 115 spinlock_t rx_dma_lock; 116 bool rx_dma_broken; 117 bool throttled; 118 }; 119 120 #ifdef CONFIG_SERIAL_8250_DMA 121 static void omap_8250_rx_dma_flush(struct uart_8250_port *p); 122 #else 123 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } 124 #endif 125 126 static u32 uart_read(struct uart_8250_port *up, u32 reg) 127 { 128 return readl(up->port.membase + (reg << up->port.regshift)); 129 } 130 131 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 132 { 133 struct uart_8250_port *up = up_to_u8250p(port); 134 struct omap8250_priv *priv = up->port.private_data; 135 u8 lcr; 136 137 serial8250_do_set_mctrl(port, mctrl); 138 139 /* 140 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 141 * if RTS is raised 142 */ 143 lcr = serial_in(up, UART_LCR); 144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 145 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 146 priv->efr |= UART_EFR_RTS; 147 else 148 priv->efr &= ~UART_EFR_RTS; 149 serial_out(up, UART_EFR, priv->efr); 150 serial_out(up, UART_LCR, lcr); 151 } 152 153 /* 154 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 155 * The access to uart register after MDR1 Access 156 * causes UART to corrupt data. 157 * 158 * Need a delay = 159 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 160 * give 10 times as much 161 */ 162 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 163 struct omap8250_priv *priv) 164 { 165 u8 timeout = 255; 166 u8 old_mdr1; 167 168 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 169 if (old_mdr1 == priv->mdr1) 170 return; 171 172 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 173 udelay(2); 174 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 175 UART_FCR_CLEAR_RCVR); 176 /* 177 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 178 * TX_FIFO_E bit is 1. 179 */ 180 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 181 (UART_LSR_THRE | UART_LSR_DR))) { 182 timeout--; 183 if (!timeout) { 184 /* Should *never* happen. we warn and carry on */ 185 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 186 serial_in(up, UART_LSR)); 187 break; 188 } 189 udelay(1); 190 } 191 } 192 193 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 194 struct omap8250_priv *priv) 195 { 196 unsigned int uartclk = port->uartclk; 197 unsigned int div_13, div_16; 198 unsigned int abs_d13, abs_d16; 199 200 /* 201 * Old custom speed handling. 202 */ 203 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 204 priv->quot = port->custom_divisor & UART_DIV_MAX; 205 /* 206 * I assume that nobody is using this. But hey, if somebody 207 * would like to specify the divisor _and_ the mode then the 208 * driver is ready and waiting for it. 209 */ 210 if (port->custom_divisor & (1 << 16)) 211 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 212 else 213 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 214 return; 215 } 216 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 217 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 218 219 if (!div_13) 220 div_13 = 1; 221 if (!div_16) 222 div_16 = 1; 223 224 abs_d13 = abs(baud - uartclk / 13 / div_13); 225 abs_d16 = abs(baud - uartclk / 16 / div_16); 226 227 if (abs_d13 >= abs_d16) { 228 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 229 priv->quot = div_16; 230 } else { 231 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 232 priv->quot = div_13; 233 } 234 } 235 236 static void omap8250_update_scr(struct uart_8250_port *up, 237 struct omap8250_priv *priv) 238 { 239 u8 old_scr; 240 241 old_scr = serial_in(up, UART_OMAP_SCR); 242 if (old_scr == priv->scr) 243 return; 244 245 /* 246 * The manual recommends not to enable the DMA mode selector in the SCR 247 * (instead of the FCR) register _and_ selecting the DMA mode as one 248 * register write because this may lead to malfunction. 249 */ 250 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 251 serial_out(up, UART_OMAP_SCR, 252 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 253 serial_out(up, UART_OMAP_SCR, priv->scr); 254 } 255 256 static void omap8250_update_mdr1(struct uart_8250_port *up, 257 struct omap8250_priv *priv) 258 { 259 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 260 omap_8250_mdr1_errataset(up, priv); 261 else 262 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 263 } 264 265 static void omap8250_restore_regs(struct uart_8250_port *up) 266 { 267 struct omap8250_priv *priv = up->port.private_data; 268 struct uart_8250_dma *dma = up->dma; 269 270 if (dma && dma->tx_running) { 271 /* 272 * TCSANOW requests the change to occur immediately however if 273 * we have a TX-DMA operation in progress then it has been 274 * observed that it might stall and never complete. Therefore we 275 * delay DMA completes to prevent this hang from happen. 276 */ 277 priv->delayed_restore = 1; 278 return; 279 } 280 281 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 282 serial_out(up, UART_EFR, UART_EFR_ECB); 283 284 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 285 serial8250_out_MCR(up, UART_MCR_TCRTLR); 286 serial_out(up, UART_FCR, up->fcr); 287 288 omap8250_update_scr(up, priv); 289 290 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 291 292 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 293 OMAP_UART_TCR_HALT(52)); 294 serial_out(up, UART_TI752_TLR, 295 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 296 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 297 298 serial_out(up, UART_LCR, 0); 299 300 /* drop TCR + TLR access, we setup XON/XOFF later */ 301 serial8250_out_MCR(up, up->mcr); 302 serial_out(up, UART_IER, up->ier); 303 304 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 305 serial_dl_write(up, priv->quot); 306 307 serial_out(up, UART_EFR, priv->efr); 308 309 /* Configure flow control */ 310 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 311 serial_out(up, UART_XON1, priv->xon); 312 serial_out(up, UART_XOFF1, priv->xoff); 313 314 serial_out(up, UART_LCR, up->lcr); 315 316 omap8250_update_mdr1(up, priv); 317 318 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 319 } 320 321 /* 322 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 323 * some differences in how we want to handle flow control. 324 */ 325 static void omap_8250_set_termios(struct uart_port *port, 326 struct ktermios *termios, 327 struct ktermios *old) 328 { 329 struct uart_8250_port *up = up_to_u8250p(port); 330 struct omap8250_priv *priv = up->port.private_data; 331 unsigned char cval = 0; 332 unsigned int baud; 333 334 switch (termios->c_cflag & CSIZE) { 335 case CS5: 336 cval = UART_LCR_WLEN5; 337 break; 338 case CS6: 339 cval = UART_LCR_WLEN6; 340 break; 341 case CS7: 342 cval = UART_LCR_WLEN7; 343 break; 344 default: 345 case CS8: 346 cval = UART_LCR_WLEN8; 347 break; 348 } 349 350 if (termios->c_cflag & CSTOPB) 351 cval |= UART_LCR_STOP; 352 if (termios->c_cflag & PARENB) 353 cval |= UART_LCR_PARITY; 354 if (!(termios->c_cflag & PARODD)) 355 cval |= UART_LCR_EPAR; 356 if (termios->c_cflag & CMSPAR) 357 cval |= UART_LCR_SPAR; 358 359 /* 360 * Ask the core to calculate the divisor for us. 361 */ 362 baud = uart_get_baud_rate(port, termios, old, 363 port->uartclk / 16 / UART_DIV_MAX, 364 port->uartclk / 13); 365 omap_8250_get_divisor(port, baud, priv); 366 367 /* 368 * Ok, we're now changing the port state. Do it with 369 * interrupts disabled. 370 */ 371 pm_runtime_get_sync(port->dev); 372 spin_lock_irq(&port->lock); 373 374 /* 375 * Update the per-port timeout. 376 */ 377 uart_update_timeout(port, termios->c_cflag, baud); 378 379 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 380 if (termios->c_iflag & INPCK) 381 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 382 if (termios->c_iflag & (IGNBRK | PARMRK)) 383 up->port.read_status_mask |= UART_LSR_BI; 384 385 /* 386 * Characters to ignore 387 */ 388 up->port.ignore_status_mask = 0; 389 if (termios->c_iflag & IGNPAR) 390 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 391 if (termios->c_iflag & IGNBRK) { 392 up->port.ignore_status_mask |= UART_LSR_BI; 393 /* 394 * If we're ignoring parity and break indicators, 395 * ignore overruns too (for real raw support). 396 */ 397 if (termios->c_iflag & IGNPAR) 398 up->port.ignore_status_mask |= UART_LSR_OE; 399 } 400 401 /* 402 * ignore all characters if CREAD is not set 403 */ 404 if ((termios->c_cflag & CREAD) == 0) 405 up->port.ignore_status_mask |= UART_LSR_DR; 406 407 /* 408 * Modem status interrupts 409 */ 410 up->ier &= ~UART_IER_MSI; 411 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 412 up->ier |= UART_IER_MSI; 413 414 up->lcr = cval; 415 /* Up to here it was mostly serial8250_do_set_termios() */ 416 417 /* 418 * We enable TRIG_GRANU for RX and TX and additionally we set 419 * SCR_TX_EMPTY bit. The result is the following: 420 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 421 * - less than RX_TRIGGER number of bytes will also cause an interrupt 422 * once the UART decides that there no new bytes arriving. 423 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 424 * empty - the trigger level is ignored here. 425 * 426 * Once DMA is enabled: 427 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 428 * bytes in the TX FIFO. On each assert the DMA engine will move 429 * TX_TRIGGER bytes into the FIFO. 430 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 431 * the FIFO and move RX_TRIGGER bytes. 432 * This is because threshold and trigger values are the same. 433 */ 434 up->fcr = UART_FCR_ENABLE_FIFO; 435 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 436 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 437 438 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 439 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 440 441 if (up->dma) 442 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 443 OMAP_UART_SCR_DMAMODE_CTL; 444 445 priv->xon = termios->c_cc[VSTART]; 446 priv->xoff = termios->c_cc[VSTOP]; 447 448 priv->efr = 0; 449 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 450 451 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 452 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 453 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 454 priv->efr |= UART_EFR_CTS; 455 } else if (up->port.flags & UPF_SOFT_FLOW) { 456 /* 457 * OMAP rx s/w flow control is borked; the transmitter remains 458 * stuck off even if rx flow control is subsequently disabled 459 */ 460 461 /* 462 * IXOFF Flag: 463 * Enable XON/XOFF flow control on output. 464 * Transmit XON1, XOFF1 465 */ 466 if (termios->c_iflag & IXOFF) { 467 up->port.status |= UPSTAT_AUTOXOFF; 468 priv->efr |= OMAP_UART_SW_TX; 469 } 470 } 471 omap8250_restore_regs(up); 472 473 spin_unlock_irq(&up->port.lock); 474 pm_runtime_mark_last_busy(port->dev); 475 pm_runtime_put_autosuspend(port->dev); 476 477 /* calculate wakeup latency constraint */ 478 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 479 priv->latency = priv->calc_latency; 480 481 schedule_work(&priv->qos_work); 482 483 /* Don't rewrite B0 */ 484 if (tty_termios_baud_rate(termios)) 485 tty_termios_encode_baud_rate(termios, baud, baud); 486 } 487 488 /* same as 8250 except that we may have extra flow bits set in EFR */ 489 static void omap_8250_pm(struct uart_port *port, unsigned int state, 490 unsigned int oldstate) 491 { 492 struct uart_8250_port *up = up_to_u8250p(port); 493 u8 efr; 494 495 pm_runtime_get_sync(port->dev); 496 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 497 efr = serial_in(up, UART_EFR); 498 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 499 serial_out(up, UART_LCR, 0); 500 501 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 502 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 503 serial_out(up, UART_EFR, efr); 504 serial_out(up, UART_LCR, 0); 505 506 pm_runtime_mark_last_busy(port->dev); 507 pm_runtime_put_autosuspend(port->dev); 508 } 509 510 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 511 struct omap8250_priv *priv) 512 { 513 u32 mvr, scheme; 514 u16 revision, major, minor; 515 516 mvr = uart_read(up, UART_OMAP_MVER); 517 518 /* Check revision register scheme */ 519 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 520 521 switch (scheme) { 522 case 0: /* Legacy Scheme: OMAP2/3 */ 523 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 524 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 525 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 526 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 527 break; 528 case 1: 529 /* New Scheme: OMAP4+ */ 530 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 531 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 532 OMAP_UART_MVR_MAJ_SHIFT; 533 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 534 break; 535 default: 536 dev_warn(up->port.dev, 537 "Unknown revision, defaulting to highest\n"); 538 /* highest possible revision */ 539 major = 0xff; 540 minor = 0xff; 541 } 542 /* normalize revision for the driver */ 543 revision = UART_BUILD_REVISION(major, minor); 544 545 switch (revision) { 546 case OMAP_UART_REV_46: 547 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 548 break; 549 case OMAP_UART_REV_52: 550 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 551 OMAP_UART_WER_HAS_TX_WAKEUP; 552 break; 553 case OMAP_UART_REV_63: 554 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 555 OMAP_UART_WER_HAS_TX_WAKEUP; 556 break; 557 default: 558 break; 559 } 560 } 561 562 static void omap8250_uart_qos_work(struct work_struct *work) 563 { 564 struct omap8250_priv *priv; 565 566 priv = container_of(work, struct omap8250_priv, qos_work); 567 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 568 } 569 570 #ifdef CONFIG_SERIAL_8250_DMA 571 static int omap_8250_dma_handle_irq(struct uart_port *port); 572 #endif 573 574 static irqreturn_t omap8250_irq(int irq, void *dev_id) 575 { 576 struct uart_port *port = dev_id; 577 struct uart_8250_port *up = up_to_u8250p(port); 578 unsigned int iir; 579 int ret; 580 581 #ifdef CONFIG_SERIAL_8250_DMA 582 if (up->dma) { 583 ret = omap_8250_dma_handle_irq(port); 584 return IRQ_RETVAL(ret); 585 } 586 #endif 587 588 serial8250_rpm_get(up); 589 iir = serial_port_in(port, UART_IIR); 590 ret = serial8250_handle_irq(port, iir); 591 serial8250_rpm_put(up); 592 593 return IRQ_RETVAL(ret); 594 } 595 596 static int omap_8250_startup(struct uart_port *port) 597 { 598 struct uart_8250_port *up = up_to_u8250p(port); 599 struct omap8250_priv *priv = port->private_data; 600 int ret; 601 602 if (priv->wakeirq) { 603 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 604 if (ret) 605 return ret; 606 } 607 608 pm_runtime_get_sync(port->dev); 609 610 up->mcr = 0; 611 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 612 613 serial_out(up, UART_LCR, UART_LCR_WLEN8); 614 615 up->lsr_saved_flags = 0; 616 up->msr_saved_flags = 0; 617 618 /* Disable DMA for console UART */ 619 if (uart_console(port)) 620 up->dma = NULL; 621 622 if (up->dma) { 623 ret = serial8250_request_dma(up); 624 if (ret) { 625 dev_warn_ratelimited(port->dev, 626 "failed to request DMA\n"); 627 up->dma = NULL; 628 } 629 } 630 631 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 632 dev_name(port->dev), port); 633 if (ret < 0) 634 goto err; 635 636 up->ier = UART_IER_RLSI | UART_IER_RDI; 637 serial_out(up, UART_IER, up->ier); 638 639 #ifdef CONFIG_PM 640 up->capabilities |= UART_CAP_RPM; 641 #endif 642 643 /* Enable module level wake up */ 644 priv->wer = OMAP_UART_WER_MOD_WKUP; 645 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 646 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 647 serial_out(up, UART_OMAP_WER, priv->wer); 648 649 if (up->dma) 650 up->dma->rx_dma(up); 651 652 pm_runtime_mark_last_busy(port->dev); 653 pm_runtime_put_autosuspend(port->dev); 654 return 0; 655 err: 656 pm_runtime_mark_last_busy(port->dev); 657 pm_runtime_put_autosuspend(port->dev); 658 dev_pm_clear_wake_irq(port->dev); 659 return ret; 660 } 661 662 static void omap_8250_shutdown(struct uart_port *port) 663 { 664 struct uart_8250_port *up = up_to_u8250p(port); 665 struct omap8250_priv *priv = port->private_data; 666 667 flush_work(&priv->qos_work); 668 if (up->dma) 669 omap_8250_rx_dma_flush(up); 670 671 pm_runtime_get_sync(port->dev); 672 673 serial_out(up, UART_OMAP_WER, 0); 674 675 up->ier = 0; 676 serial_out(up, UART_IER, 0); 677 678 if (up->dma) 679 serial8250_release_dma(up); 680 681 /* 682 * Disable break condition and FIFOs 683 */ 684 if (up->lcr & UART_LCR_SBC) 685 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 686 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 687 688 pm_runtime_mark_last_busy(port->dev); 689 pm_runtime_put_autosuspend(port->dev); 690 free_irq(port->irq, port); 691 dev_pm_clear_wake_irq(port->dev); 692 } 693 694 static void omap_8250_throttle(struct uart_port *port) 695 { 696 struct omap8250_priv *priv = port->private_data; 697 struct uart_8250_port *up = up_to_u8250p(port); 698 unsigned long flags; 699 700 pm_runtime_get_sync(port->dev); 701 702 spin_lock_irqsave(&port->lock, flags); 703 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 704 serial_out(up, UART_IER, up->ier); 705 priv->throttled = true; 706 spin_unlock_irqrestore(&port->lock, flags); 707 708 pm_runtime_mark_last_busy(port->dev); 709 pm_runtime_put_autosuspend(port->dev); 710 } 711 712 static int omap_8250_rs485_config(struct uart_port *port, 713 struct serial_rs485 *rs485) 714 { 715 struct uart_8250_port *up = up_to_u8250p(port); 716 717 /* Clamp the delays to [0, 100ms] */ 718 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 719 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 720 721 port->rs485 = *rs485; 722 723 /* 724 * Both serial8250_em485_init and serial8250_em485_destroy 725 * are idempotent 726 */ 727 if (rs485->flags & SER_RS485_ENABLED) { 728 int ret = serial8250_em485_init(up); 729 730 if (ret) { 731 rs485->flags &= ~SER_RS485_ENABLED; 732 port->rs485.flags &= ~SER_RS485_ENABLED; 733 } 734 return ret; 735 } 736 737 serial8250_em485_destroy(up); 738 739 return 0; 740 } 741 742 static void omap_8250_unthrottle(struct uart_port *port) 743 { 744 struct omap8250_priv *priv = port->private_data; 745 struct uart_8250_port *up = up_to_u8250p(port); 746 unsigned long flags; 747 748 pm_runtime_get_sync(port->dev); 749 750 spin_lock_irqsave(&port->lock, flags); 751 priv->throttled = false; 752 if (up->dma) 753 up->dma->rx_dma(up); 754 up->ier |= UART_IER_RLSI | UART_IER_RDI; 755 serial_out(up, UART_IER, up->ier); 756 spin_unlock_irqrestore(&port->lock, flags); 757 758 pm_runtime_mark_last_busy(port->dev); 759 pm_runtime_put_autosuspend(port->dev); 760 } 761 762 #ifdef CONFIG_SERIAL_8250_DMA 763 static int omap_8250_rx_dma(struct uart_8250_port *p); 764 765 static void __dma_rx_do_complete(struct uart_8250_port *p) 766 { 767 struct omap8250_priv *priv = p->port.private_data; 768 struct uart_8250_dma *dma = p->dma; 769 struct tty_port *tty_port = &p->port.state->port; 770 struct dma_tx_state state; 771 int count; 772 unsigned long flags; 773 int ret; 774 775 spin_lock_irqsave(&priv->rx_dma_lock, flags); 776 777 if (!dma->rx_running) 778 goto unlock; 779 780 dma->rx_running = 0; 781 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 782 783 count = dma->rx_size - state.residue; 784 785 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 786 787 p->port.icount.rx += ret; 788 p->port.icount.buf_overrun += count - ret; 789 unlock: 790 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 791 792 tty_flip_buffer_push(tty_port); 793 } 794 795 static void __dma_rx_complete(void *param) 796 { 797 struct uart_8250_port *p = param; 798 struct omap8250_priv *priv = p->port.private_data; 799 struct uart_8250_dma *dma = p->dma; 800 struct dma_tx_state state; 801 unsigned long flags; 802 803 spin_lock_irqsave(&p->port.lock, flags); 804 805 /* 806 * If the tx status is not DMA_COMPLETE, then this is a delayed 807 * completion callback. A previous RX timeout flush would have 808 * already pushed the data, so exit. 809 */ 810 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 811 DMA_COMPLETE) { 812 spin_unlock_irqrestore(&p->port.lock, flags); 813 return; 814 } 815 __dma_rx_do_complete(p); 816 if (!priv->throttled) 817 omap_8250_rx_dma(p); 818 819 spin_unlock_irqrestore(&p->port.lock, flags); 820 } 821 822 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 823 { 824 struct omap8250_priv *priv = p->port.private_data; 825 struct uart_8250_dma *dma = p->dma; 826 struct dma_tx_state state; 827 unsigned long flags; 828 int ret; 829 830 spin_lock_irqsave(&priv->rx_dma_lock, flags); 831 832 if (!dma->rx_running) { 833 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 834 return; 835 } 836 837 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 838 if (ret == DMA_IN_PROGRESS) { 839 ret = dmaengine_pause(dma->rxchan); 840 if (WARN_ON_ONCE(ret)) 841 priv->rx_dma_broken = true; 842 } 843 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 844 845 __dma_rx_do_complete(p); 846 dmaengine_terminate_all(dma->rxchan); 847 } 848 849 static int omap_8250_rx_dma(struct uart_8250_port *p) 850 { 851 struct omap8250_priv *priv = p->port.private_data; 852 struct uart_8250_dma *dma = p->dma; 853 int err = 0; 854 struct dma_async_tx_descriptor *desc; 855 unsigned long flags; 856 857 if (priv->rx_dma_broken) 858 return -EINVAL; 859 860 spin_lock_irqsave(&priv->rx_dma_lock, flags); 861 862 if (dma->rx_running) 863 goto out; 864 865 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 866 dma->rx_size, DMA_DEV_TO_MEM, 867 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 868 if (!desc) { 869 err = -EBUSY; 870 goto out; 871 } 872 873 dma->rx_running = 1; 874 desc->callback = __dma_rx_complete; 875 desc->callback_param = p; 876 877 dma->rx_cookie = dmaengine_submit(desc); 878 879 dma_async_issue_pending(dma->rxchan); 880 out: 881 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 882 return err; 883 } 884 885 static int omap_8250_tx_dma(struct uart_8250_port *p); 886 887 static void omap_8250_dma_tx_complete(void *param) 888 { 889 struct uart_8250_port *p = param; 890 struct uart_8250_dma *dma = p->dma; 891 struct circ_buf *xmit = &p->port.state->xmit; 892 unsigned long flags; 893 bool en_thri = false; 894 struct omap8250_priv *priv = p->port.private_data; 895 896 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 897 UART_XMIT_SIZE, DMA_TO_DEVICE); 898 899 spin_lock_irqsave(&p->port.lock, flags); 900 901 dma->tx_running = 0; 902 903 xmit->tail += dma->tx_size; 904 xmit->tail &= UART_XMIT_SIZE - 1; 905 p->port.icount.tx += dma->tx_size; 906 907 if (priv->delayed_restore) { 908 priv->delayed_restore = 0; 909 omap8250_restore_regs(p); 910 } 911 912 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 913 uart_write_wakeup(&p->port); 914 915 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 916 int ret; 917 918 ret = omap_8250_tx_dma(p); 919 if (ret) 920 en_thri = true; 921 922 } else if (p->capabilities & UART_CAP_RPM) { 923 en_thri = true; 924 } 925 926 if (en_thri) { 927 dma->tx_err = 1; 928 p->ier |= UART_IER_THRI; 929 serial_port_out(&p->port, UART_IER, p->ier); 930 } 931 932 spin_unlock_irqrestore(&p->port.lock, flags); 933 } 934 935 static int omap_8250_tx_dma(struct uart_8250_port *p) 936 { 937 struct uart_8250_dma *dma = p->dma; 938 struct omap8250_priv *priv = p->port.private_data; 939 struct circ_buf *xmit = &p->port.state->xmit; 940 struct dma_async_tx_descriptor *desc; 941 unsigned int skip_byte = 0; 942 int ret; 943 944 if (dma->tx_running) 945 return 0; 946 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 947 948 /* 949 * Even if no data, we need to return an error for the two cases 950 * below so serial8250_tx_chars() is invoked and properly clears 951 * THRI and/or runtime suspend. 952 */ 953 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 954 ret = -EBUSY; 955 goto err; 956 } 957 if (p->ier & UART_IER_THRI) { 958 p->ier &= ~UART_IER_THRI; 959 serial_out(p, UART_IER, p->ier); 960 } 961 return 0; 962 } 963 964 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 965 if (priv->habit & OMAP_DMA_TX_KICK) { 966 u8 tx_lvl; 967 968 /* 969 * We need to put the first byte into the FIFO in order to start 970 * the DMA transfer. For transfers smaller than four bytes we 971 * don't bother doing DMA at all. It seem not matter if there 972 * are still bytes in the FIFO from the last transfer (in case 973 * we got here directly from omap_8250_dma_tx_complete()). Bytes 974 * leaving the FIFO seem not to trigger the DMA transfer. It is 975 * really the byte that we put into the FIFO. 976 * If the FIFO is already full then we most likely got here from 977 * omap_8250_dma_tx_complete(). And this means the DMA engine 978 * just completed its work. We don't have to wait the complete 979 * 86us at 115200,8n1 but around 60us (not to mention lower 980 * baudrates). So in that case we take the interrupt and try 981 * again with an empty FIFO. 982 */ 983 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 984 if (tx_lvl == p->tx_loadsz) { 985 ret = -EBUSY; 986 goto err; 987 } 988 if (dma->tx_size < 4) { 989 ret = -EINVAL; 990 goto err; 991 } 992 skip_byte = 1; 993 } 994 995 desc = dmaengine_prep_slave_single(dma->txchan, 996 dma->tx_addr + xmit->tail + skip_byte, 997 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 998 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 999 if (!desc) { 1000 ret = -EBUSY; 1001 goto err; 1002 } 1003 1004 dma->tx_running = 1; 1005 1006 desc->callback = omap_8250_dma_tx_complete; 1007 desc->callback_param = p; 1008 1009 dma->tx_cookie = dmaengine_submit(desc); 1010 1011 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1012 UART_XMIT_SIZE, DMA_TO_DEVICE); 1013 1014 dma_async_issue_pending(dma->txchan); 1015 if (dma->tx_err) 1016 dma->tx_err = 0; 1017 1018 if (p->ier & UART_IER_THRI) { 1019 p->ier &= ~UART_IER_THRI; 1020 serial_out(p, UART_IER, p->ier); 1021 } 1022 if (skip_byte) 1023 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1024 return 0; 1025 err: 1026 dma->tx_err = 1; 1027 return ret; 1028 } 1029 1030 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) 1031 { 1032 switch (iir & 0x3f) { 1033 case UART_IIR_RLSI: 1034 case UART_IIR_RX_TIMEOUT: 1035 case UART_IIR_RDI: 1036 omap_8250_rx_dma_flush(up); 1037 return true; 1038 } 1039 return omap_8250_rx_dma(up); 1040 } 1041 1042 /* 1043 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1044 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1045 * use the default routine in the non-DMA case and this one for with DMA. 1046 */ 1047 static int omap_8250_dma_handle_irq(struct uart_port *port) 1048 { 1049 struct uart_8250_port *up = up_to_u8250p(port); 1050 unsigned char status; 1051 unsigned long flags; 1052 u8 iir; 1053 1054 serial8250_rpm_get(up); 1055 1056 iir = serial_port_in(port, UART_IIR); 1057 if (iir & UART_IIR_NO_INT) { 1058 serial8250_rpm_put(up); 1059 return 0; 1060 } 1061 1062 spin_lock_irqsave(&port->lock, flags); 1063 1064 status = serial_port_in(port, UART_LSR); 1065 1066 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1067 if (handle_rx_dma(up, iir)) { 1068 status = serial8250_rx_chars(up, status); 1069 omap_8250_rx_dma(up); 1070 } 1071 } 1072 serial8250_modem_status(up); 1073 if (status & UART_LSR_THRE && up->dma->tx_err) { 1074 if (uart_tx_stopped(&up->port) || 1075 uart_circ_empty(&up->port.state->xmit)) { 1076 up->dma->tx_err = 0; 1077 serial8250_tx_chars(up); 1078 } else { 1079 /* 1080 * try again due to an earlier failer which 1081 * might have been resolved by now. 1082 */ 1083 if (omap_8250_tx_dma(up)) 1084 serial8250_tx_chars(up); 1085 } 1086 } 1087 1088 spin_unlock_irqrestore(&port->lock, flags); 1089 serial8250_rpm_put(up); 1090 return 1; 1091 } 1092 1093 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1094 { 1095 return false; 1096 } 1097 1098 #else 1099 1100 static inline int omap_8250_rx_dma(struct uart_8250_port *p) 1101 { 1102 return -EINVAL; 1103 } 1104 #endif 1105 1106 static int omap8250_no_handle_irq(struct uart_port *port) 1107 { 1108 /* IRQ has not been requested but handling irq? */ 1109 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1110 return 0; 1111 } 1112 1113 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE; 1114 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; 1115 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE; 1116 1117 static const struct of_device_id omap8250_dt_ids[] = { 1118 { .compatible = "ti,omap2-uart" }, 1119 { .compatible = "ti,omap3-uart" }, 1120 { .compatible = "ti,omap4-uart", .data = &omap4_habit, }, 1121 { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, 1122 { .compatible = "ti,am4372-uart", .data = &am3352_habit, }, 1123 { .compatible = "ti,dra742-uart", .data = &dra742_habit, }, 1124 {}, 1125 }; 1126 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1127 1128 static int omap8250_probe(struct platform_device *pdev) 1129 { 1130 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1131 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1132 struct omap8250_priv *priv; 1133 struct uart_8250_port up; 1134 int ret; 1135 void __iomem *membase; 1136 1137 if (!regs || !irq) { 1138 dev_err(&pdev->dev, "missing registers or irq\n"); 1139 return -EINVAL; 1140 } 1141 1142 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1143 if (!priv) 1144 return -ENOMEM; 1145 1146 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1147 resource_size(regs)); 1148 if (!membase) 1149 return -ENODEV; 1150 1151 memset(&up, 0, sizeof(up)); 1152 up.port.dev = &pdev->dev; 1153 up.port.mapbase = regs->start; 1154 up.port.membase = membase; 1155 up.port.irq = irq->start; 1156 /* 1157 * It claims to be 16C750 compatible however it is a little different. 1158 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1159 * have) is enabled via EFR instead of MCR. The type is set here 8250 1160 * just to get things going. UNKNOWN does not work for a few reasons and 1161 * we don't need our own type since we don't use 8250's set_termios() 1162 * or pm callback. 1163 */ 1164 up.port.type = PORT_8250; 1165 up.port.iotype = UPIO_MEM; 1166 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1167 UPF_HARD_FLOW; 1168 up.port.private_data = priv; 1169 1170 up.port.regshift = 2; 1171 up.port.fifosize = 64; 1172 up.tx_loadsz = 64; 1173 up.capabilities = UART_CAP_FIFO; 1174 #ifdef CONFIG_PM 1175 /* 1176 * Runtime PM is mostly transparent. However to do it right we need to a 1177 * TX empty interrupt before we can put the device to auto idle. So if 1178 * PM is not enabled we don't add that flag and can spare that one extra 1179 * interrupt in the TX path. 1180 */ 1181 up.capabilities |= UART_CAP_RPM; 1182 #endif 1183 up.port.set_termios = omap_8250_set_termios; 1184 up.port.set_mctrl = omap8250_set_mctrl; 1185 up.port.pm = omap_8250_pm; 1186 up.port.startup = omap_8250_startup; 1187 up.port.shutdown = omap_8250_shutdown; 1188 up.port.throttle = omap_8250_throttle; 1189 up.port.unthrottle = omap_8250_unthrottle; 1190 up.port.rs485_config = omap_8250_rs485_config; 1191 1192 if (pdev->dev.of_node) { 1193 const struct of_device_id *id; 1194 1195 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1196 1197 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1198 &up.port.uartclk); 1199 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1200 1201 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); 1202 if (id && id->data) 1203 priv->habit |= *(u8 *)id->data; 1204 } else { 1205 ret = pdev->id; 1206 } 1207 if (ret < 0) { 1208 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1209 return ret; 1210 } 1211 up.port.line = ret; 1212 1213 if (!up.port.uartclk) { 1214 up.port.uartclk = DEFAULT_CLK_SPEED; 1215 dev_warn(&pdev->dev, 1216 "No clock speed specified: using default: %d\n", 1217 DEFAULT_CLK_SPEED); 1218 } 1219 1220 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1221 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1222 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1223 priv->latency); 1224 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1225 1226 spin_lock_init(&priv->rx_dma_lock); 1227 1228 device_init_wakeup(&pdev->dev, true); 1229 pm_runtime_use_autosuspend(&pdev->dev); 1230 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1231 1232 pm_runtime_irq_safe(&pdev->dev); 1233 pm_runtime_enable(&pdev->dev); 1234 1235 pm_runtime_get_sync(&pdev->dev); 1236 1237 omap_serial_fill_features_erratas(&up, priv); 1238 up.port.handle_irq = omap8250_no_handle_irq; 1239 #ifdef CONFIG_SERIAL_8250_DMA 1240 if (pdev->dev.of_node) { 1241 /* 1242 * Oh DMA support. If there are no DMA properties in the DT then 1243 * we will fall back to a generic DMA channel which does not 1244 * really work here. To ensure that we do not get a generic DMA 1245 * channel assigned, we have the the_no_dma_filter_fn() here. 1246 * To avoid "failed to request DMA" messages we check for DMA 1247 * properties in DT. 1248 */ 1249 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1250 if (ret == 2) { 1251 up.dma = &priv->omap8250_dma; 1252 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1253 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1254 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1255 priv->omap8250_dma.rx_size = RX_TRIGGER; 1256 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1257 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1258 } 1259 } 1260 #endif 1261 ret = serial8250_register_8250_port(&up); 1262 if (ret < 0) { 1263 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1264 goto err; 1265 } 1266 priv->line = ret; 1267 platform_set_drvdata(pdev, priv); 1268 pm_runtime_mark_last_busy(&pdev->dev); 1269 pm_runtime_put_autosuspend(&pdev->dev); 1270 return 0; 1271 err: 1272 pm_runtime_dont_use_autosuspend(&pdev->dev); 1273 pm_runtime_put_sync(&pdev->dev); 1274 pm_runtime_disable(&pdev->dev); 1275 return ret; 1276 } 1277 1278 static int omap8250_remove(struct platform_device *pdev) 1279 { 1280 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1281 1282 pm_runtime_dont_use_autosuspend(&pdev->dev); 1283 pm_runtime_put_sync(&pdev->dev); 1284 pm_runtime_disable(&pdev->dev); 1285 serial8250_unregister_port(priv->line); 1286 pm_qos_remove_request(&priv->pm_qos_request); 1287 device_init_wakeup(&pdev->dev, false); 1288 return 0; 1289 } 1290 1291 #ifdef CONFIG_PM_SLEEP 1292 static int omap8250_prepare(struct device *dev) 1293 { 1294 struct omap8250_priv *priv = dev_get_drvdata(dev); 1295 1296 if (!priv) 1297 return 0; 1298 priv->is_suspending = true; 1299 return 0; 1300 } 1301 1302 static void omap8250_complete(struct device *dev) 1303 { 1304 struct omap8250_priv *priv = dev_get_drvdata(dev); 1305 1306 if (!priv) 1307 return; 1308 priv->is_suspending = false; 1309 } 1310 1311 static int omap8250_suspend(struct device *dev) 1312 { 1313 struct omap8250_priv *priv = dev_get_drvdata(dev); 1314 struct uart_8250_port *up = serial8250_get_port(priv->line); 1315 1316 serial8250_suspend_port(priv->line); 1317 1318 pm_runtime_get_sync(dev); 1319 if (!device_may_wakeup(dev)) 1320 priv->wer = 0; 1321 serial_out(up, UART_OMAP_WER, priv->wer); 1322 pm_runtime_mark_last_busy(dev); 1323 pm_runtime_put_autosuspend(dev); 1324 1325 flush_work(&priv->qos_work); 1326 return 0; 1327 } 1328 1329 static int omap8250_resume(struct device *dev) 1330 { 1331 struct omap8250_priv *priv = dev_get_drvdata(dev); 1332 1333 serial8250_resume_port(priv->line); 1334 return 0; 1335 } 1336 #else 1337 #define omap8250_prepare NULL 1338 #define omap8250_complete NULL 1339 #endif 1340 1341 #ifdef CONFIG_PM 1342 static int omap8250_lost_context(struct uart_8250_port *up) 1343 { 1344 u32 val; 1345 1346 val = serial_in(up, UART_OMAP_SCR); 1347 /* 1348 * If we lose context, then SCR is set to its reset value of zero. 1349 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1350 * among other bits, to never set the register back to zero again. 1351 */ 1352 if (!val) 1353 return 1; 1354 return 0; 1355 } 1356 1357 /* TODO: in future, this should happen via API in drivers/reset/ */ 1358 static int omap8250_soft_reset(struct device *dev) 1359 { 1360 struct omap8250_priv *priv = dev_get_drvdata(dev); 1361 struct uart_8250_port *up = serial8250_get_port(priv->line); 1362 int timeout = 100; 1363 int sysc; 1364 int syss; 1365 1366 /* 1367 * At least on omap4, unused uarts may not idle after reset without 1368 * a basic scr dma configuration even with no dma in use. The 1369 * module clkctrl status bits will be 1 instead of 3 blocking idle 1370 * for the whole clockdomain. The softreset below will clear scr, 1371 * and we restore it on resume so this is safe to do on all SoCs 1372 * needing omap8250_soft_reset() quirk. Do it in two writes as 1373 * recommended in the comment for omap8250_update_scr(). 1374 */ 1375 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); 1376 serial_out(up, UART_OMAP_SCR, 1377 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); 1378 1379 sysc = serial_in(up, UART_OMAP_SYSC); 1380 1381 /* softreset the UART */ 1382 sysc |= OMAP_UART_SYSC_SOFTRESET; 1383 serial_out(up, UART_OMAP_SYSC, sysc); 1384 1385 /* By experiments, 1us enough for reset complete on AM335x */ 1386 do { 1387 udelay(1); 1388 syss = serial_in(up, UART_OMAP_SYSS); 1389 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1390 1391 if (!timeout) { 1392 dev_err(dev, "timed out waiting for reset done\n"); 1393 return -ETIMEDOUT; 1394 } 1395 1396 return 0; 1397 } 1398 1399 static int omap8250_runtime_suspend(struct device *dev) 1400 { 1401 struct omap8250_priv *priv = dev_get_drvdata(dev); 1402 struct uart_8250_port *up; 1403 1404 /* In case runtime-pm tries this before we are setup */ 1405 if (!priv) 1406 return 0; 1407 1408 up = serial8250_get_port(priv->line); 1409 /* 1410 * When using 'no_console_suspend', the console UART must not be 1411 * suspended. Since driver suspend is managed by runtime suspend, 1412 * preventing runtime suspend (by returning error) will keep device 1413 * active during suspend. 1414 */ 1415 if (priv->is_suspending && !console_suspend_enabled) { 1416 if (uart_console(&up->port)) 1417 return -EBUSY; 1418 } 1419 1420 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1421 int ret; 1422 1423 ret = omap8250_soft_reset(dev); 1424 if (ret) 1425 return ret; 1426 1427 /* Restore to UART mode after reset (for wakeup) */ 1428 omap8250_update_mdr1(up, priv); 1429 /* Restore wakeup enable register */ 1430 serial_out(up, UART_OMAP_WER, priv->wer); 1431 } 1432 1433 if (up->dma && up->dma->rxchan) 1434 omap_8250_rx_dma_flush(up); 1435 1436 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1437 schedule_work(&priv->qos_work); 1438 1439 return 0; 1440 } 1441 1442 static int omap8250_runtime_resume(struct device *dev) 1443 { 1444 struct omap8250_priv *priv = dev_get_drvdata(dev); 1445 struct uart_8250_port *up; 1446 1447 /* In case runtime-pm tries this before we are setup */ 1448 if (!priv) 1449 return 0; 1450 1451 up = serial8250_get_port(priv->line); 1452 1453 if (omap8250_lost_context(up)) 1454 omap8250_restore_regs(up); 1455 1456 if (up->dma && up->dma->rxchan) 1457 omap_8250_rx_dma(up); 1458 1459 priv->latency = priv->calc_latency; 1460 schedule_work(&priv->qos_work); 1461 return 0; 1462 } 1463 #endif 1464 1465 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1466 static int __init omap8250_console_fixup(void) 1467 { 1468 char *omap_str; 1469 char *options; 1470 u8 idx; 1471 1472 if (strstr(boot_command_line, "console=ttyS")) 1473 /* user set a ttyS based name for the console */ 1474 return 0; 1475 1476 omap_str = strstr(boot_command_line, "console=ttyO"); 1477 if (!omap_str) 1478 /* user did not set ttyO based console, so we don't care */ 1479 return 0; 1480 1481 omap_str += 12; 1482 if ('0' <= *omap_str && *omap_str <= '9') 1483 idx = *omap_str - '0'; 1484 else 1485 return 0; 1486 1487 omap_str++; 1488 if (omap_str[0] == ',') { 1489 omap_str++; 1490 options = omap_str; 1491 } else { 1492 options = NULL; 1493 } 1494 1495 add_preferred_console("ttyS", idx, options); 1496 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1497 idx, idx); 1498 pr_err("This ensures that you still see kernel messages. Please\n"); 1499 pr_err("update your kernel commandline.\n"); 1500 return 0; 1501 } 1502 console_initcall(omap8250_console_fixup); 1503 #endif 1504 1505 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1506 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1507 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1508 omap8250_runtime_resume, NULL) 1509 .prepare = omap8250_prepare, 1510 .complete = omap8250_complete, 1511 }; 1512 1513 static struct platform_driver omap8250_platform_driver = { 1514 .driver = { 1515 .name = "omap8250", 1516 .pm = &omap8250_dev_pm_ops, 1517 .of_match_table = omap8250_dt_ids, 1518 }, 1519 .probe = omap8250_probe, 1520 .remove = omap8250_remove, 1521 }; 1522 module_platform_driver(omap8250_platform_driver); 1523 1524 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1525 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1526 MODULE_LICENSE("GPL v2"); 1527