1 /* 2 * 8250-core based driver for the OMAP internal UART 3 * 4 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. 5 * 6 * Copyright (C) 2014 Sebastian Andrzej Siewior 7 * 8 */ 9 10 #include <linux/device.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/serial_8250.h> 14 #include <linux/serial_reg.h> 15 #include <linux/tty_flip.h> 16 #include <linux/platform_device.h> 17 #include <linux/slab.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/of_irq.h> 22 #include <linux/delay.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/console.h> 25 #include <linux/pm_qos.h> 26 #include <linux/pm_wakeirq.h> 27 #include <linux/dma-mapping.h> 28 29 #include "8250.h" 30 31 #define DEFAULT_CLK_SPEED 48000000 32 33 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) 34 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) 35 #define OMAP_DMA_TX_KICK (1 << 2) 36 /* 37 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. 38 * The same errata is applicable to AM335x and DRA7x processors too. 39 */ 40 #define UART_ERRATA_CLOCK_DISABLE (1 << 3) 41 42 #define OMAP_UART_FCR_RX_TRIG 6 43 #define OMAP_UART_FCR_TX_TRIG 4 44 45 /* SCR register bitmasks */ 46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 48 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 49 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) 50 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) 51 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) 52 53 /* MVR register bitmasks */ 54 #define OMAP_UART_MVR_SCHEME_SHIFT 30 55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 57 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 58 #define OMAP_UART_MVR_MAJ_MASK 0x700 59 #define OMAP_UART_MVR_MAJ_SHIFT 8 60 #define OMAP_UART_MVR_MIN_MASK 0x3f 61 62 /* SYSC register bitmasks */ 63 #define OMAP_UART_SYSC_SOFTRESET (1 << 1) 64 65 /* SYSS register bitmasks */ 66 #define OMAP_UART_SYSS_RESETDONE (1 << 0) 67 68 #define UART_TI752_TLR_TX 0 69 #define UART_TI752_TLR_RX 4 70 71 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) 72 #define TRIGGER_FCR_MASK(x) (x & 3) 73 74 /* Enable XON/XOFF flow control on output */ 75 #define OMAP_UART_SW_TX 0x08 76 /* Enable XON/XOFF flow control on input */ 77 #define OMAP_UART_SW_RX 0x02 78 79 #define OMAP_UART_WER_MOD_WKUP 0x7f 80 #define OMAP_UART_TX_WAKEUP_EN (1 << 7) 81 82 #define TX_TRIGGER 1 83 #define RX_TRIGGER 48 84 85 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) 86 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) 87 88 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 89 90 #define OMAP_UART_REV_46 0x0406 91 #define OMAP_UART_REV_52 0x0502 92 #define OMAP_UART_REV_63 0x0603 93 94 struct omap8250_priv { 95 int line; 96 u8 habit; 97 u8 mdr1; 98 u8 efr; 99 u8 scr; 100 u8 wer; 101 u8 xon; 102 u8 xoff; 103 u8 delayed_restore; 104 u16 quot; 105 106 bool is_suspending; 107 int wakeirq; 108 int wakeups_enabled; 109 u32 latency; 110 u32 calc_latency; 111 struct pm_qos_request pm_qos_request; 112 struct work_struct qos_work; 113 struct uart_8250_dma omap8250_dma; 114 spinlock_t rx_dma_lock; 115 bool rx_dma_broken; 116 }; 117 118 static u32 uart_read(struct uart_8250_port *up, u32 reg) 119 { 120 return readl(up->port.membase + (reg << up->port.regshift)); 121 } 122 123 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 124 { 125 struct uart_8250_port *up = up_to_u8250p(port); 126 struct omap8250_priv *priv = up->port.private_data; 127 u8 lcr; 128 129 serial8250_do_set_mctrl(port, mctrl); 130 131 /* 132 * Turn off autoRTS if RTS is lowered and restore autoRTS setting 133 * if RTS is raised 134 */ 135 lcr = serial_in(up, UART_LCR); 136 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 137 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 138 priv->efr |= UART_EFR_RTS; 139 else 140 priv->efr &= ~UART_EFR_RTS; 141 serial_out(up, UART_EFR, priv->efr); 142 serial_out(up, UART_LCR, lcr); 143 } 144 145 /* 146 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 147 * The access to uart register after MDR1 Access 148 * causes UART to corrupt data. 149 * 150 * Need a delay = 151 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 152 * give 10 times as much 153 */ 154 static void omap_8250_mdr1_errataset(struct uart_8250_port *up, 155 struct omap8250_priv *priv) 156 { 157 u8 timeout = 255; 158 u8 old_mdr1; 159 160 old_mdr1 = serial_in(up, UART_OMAP_MDR1); 161 if (old_mdr1 == priv->mdr1) 162 return; 163 164 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 165 udelay(2); 166 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 167 UART_FCR_CLEAR_RCVR); 168 /* 169 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 170 * TX_FIFO_E bit is 1. 171 */ 172 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 173 (UART_LSR_THRE | UART_LSR_DR))) { 174 timeout--; 175 if (!timeout) { 176 /* Should *never* happen. we warn and carry on */ 177 dev_crit(up->port.dev, "Errata i202: timedout %x\n", 178 serial_in(up, UART_LSR)); 179 break; 180 } 181 udelay(1); 182 } 183 } 184 185 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, 186 struct omap8250_priv *priv) 187 { 188 unsigned int uartclk = port->uartclk; 189 unsigned int div_13, div_16; 190 unsigned int abs_d13, abs_d16; 191 192 /* 193 * Old custom speed handling. 194 */ 195 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { 196 priv->quot = port->custom_divisor & 0xffff; 197 /* 198 * I assume that nobody is using this. But hey, if somebody 199 * would like to specify the divisor _and_ the mode then the 200 * driver is ready and waiting for it. 201 */ 202 if (port->custom_divisor & (1 << 16)) 203 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 204 else 205 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 206 return; 207 } 208 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); 209 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); 210 211 if (!div_13) 212 div_13 = 1; 213 if (!div_16) 214 div_16 = 1; 215 216 abs_d13 = abs(baud - uartclk / 13 / div_13); 217 abs_d16 = abs(baud - uartclk / 16 / div_16); 218 219 if (abs_d13 >= abs_d16) { 220 priv->mdr1 = UART_OMAP_MDR1_16X_MODE; 221 priv->quot = div_16; 222 } else { 223 priv->mdr1 = UART_OMAP_MDR1_13X_MODE; 224 priv->quot = div_13; 225 } 226 } 227 228 static void omap8250_update_scr(struct uart_8250_port *up, 229 struct omap8250_priv *priv) 230 { 231 u8 old_scr; 232 233 old_scr = serial_in(up, UART_OMAP_SCR); 234 if (old_scr == priv->scr) 235 return; 236 237 /* 238 * The manual recommends not to enable the DMA mode selector in the SCR 239 * (instead of the FCR) register _and_ selecting the DMA mode as one 240 * register write because this may lead to malfunction. 241 */ 242 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) 243 serial_out(up, UART_OMAP_SCR, 244 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); 245 serial_out(up, UART_OMAP_SCR, priv->scr); 246 } 247 248 static void omap8250_update_mdr1(struct uart_8250_port *up, 249 struct omap8250_priv *priv) 250 { 251 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) 252 omap_8250_mdr1_errataset(up, priv); 253 else 254 serial_out(up, UART_OMAP_MDR1, priv->mdr1); 255 } 256 257 static void omap8250_restore_regs(struct uart_8250_port *up) 258 { 259 struct omap8250_priv *priv = up->port.private_data; 260 struct uart_8250_dma *dma = up->dma; 261 262 if (dma && dma->tx_running) { 263 /* 264 * TCSANOW requests the change to occur immediately however if 265 * we have a TX-DMA operation in progress then it has been 266 * observed that it might stall and never complete. Therefore we 267 * delay DMA completes to prevent this hang from happen. 268 */ 269 priv->delayed_restore = 1; 270 return; 271 } 272 273 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 274 serial_out(up, UART_EFR, UART_EFR_ECB); 275 276 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 277 serial_out(up, UART_MCR, UART_MCR_TCRTLR); 278 serial_out(up, UART_FCR, up->fcr); 279 280 omap8250_update_scr(up, priv); 281 282 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 283 284 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | 285 OMAP_UART_TCR_HALT(52)); 286 serial_out(up, UART_TI752_TLR, 287 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | 288 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); 289 290 serial_out(up, UART_LCR, 0); 291 292 /* drop TCR + TLR access, we setup XON/XOFF later */ 293 serial_out(up, UART_MCR, up->mcr); 294 serial_out(up, UART_IER, up->ier); 295 296 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 297 serial_dl_write(up, priv->quot); 298 299 serial_out(up, UART_EFR, priv->efr); 300 301 /* Configure flow control */ 302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 303 serial_out(up, UART_XON1, priv->xon); 304 serial_out(up, UART_XOFF1, priv->xoff); 305 306 serial_out(up, UART_LCR, up->lcr); 307 308 omap8250_update_mdr1(up, priv); 309 310 up->port.ops->set_mctrl(&up->port, up->port.mctrl); 311 } 312 313 /* 314 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have 315 * some differences in how we want to handle flow control. 316 */ 317 static void omap_8250_set_termios(struct uart_port *port, 318 struct ktermios *termios, 319 struct ktermios *old) 320 { 321 struct uart_8250_port *up = up_to_u8250p(port); 322 struct omap8250_priv *priv = up->port.private_data; 323 unsigned char cval = 0; 324 unsigned int baud; 325 326 switch (termios->c_cflag & CSIZE) { 327 case CS5: 328 cval = UART_LCR_WLEN5; 329 break; 330 case CS6: 331 cval = UART_LCR_WLEN6; 332 break; 333 case CS7: 334 cval = UART_LCR_WLEN7; 335 break; 336 default: 337 case CS8: 338 cval = UART_LCR_WLEN8; 339 break; 340 } 341 342 if (termios->c_cflag & CSTOPB) 343 cval |= UART_LCR_STOP; 344 if (termios->c_cflag & PARENB) 345 cval |= UART_LCR_PARITY; 346 if (!(termios->c_cflag & PARODD)) 347 cval |= UART_LCR_EPAR; 348 if (termios->c_cflag & CMSPAR) 349 cval |= UART_LCR_SPAR; 350 351 /* 352 * Ask the core to calculate the divisor for us. 353 */ 354 baud = uart_get_baud_rate(port, termios, old, 355 port->uartclk / 16 / 0xffff, 356 port->uartclk / 13); 357 omap_8250_get_divisor(port, baud, priv); 358 359 /* 360 * Ok, we're now changing the port state. Do it with 361 * interrupts disabled. 362 */ 363 pm_runtime_get_sync(port->dev); 364 spin_lock_irq(&port->lock); 365 366 /* 367 * Update the per-port timeout. 368 */ 369 uart_update_timeout(port, termios->c_cflag, baud); 370 371 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 372 if (termios->c_iflag & INPCK) 373 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 374 if (termios->c_iflag & (IGNBRK | PARMRK)) 375 up->port.read_status_mask |= UART_LSR_BI; 376 377 /* 378 * Characters to ignore 379 */ 380 up->port.ignore_status_mask = 0; 381 if (termios->c_iflag & IGNPAR) 382 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 383 if (termios->c_iflag & IGNBRK) { 384 up->port.ignore_status_mask |= UART_LSR_BI; 385 /* 386 * If we're ignoring parity and break indicators, 387 * ignore overruns too (for real raw support). 388 */ 389 if (termios->c_iflag & IGNPAR) 390 up->port.ignore_status_mask |= UART_LSR_OE; 391 } 392 393 /* 394 * ignore all characters if CREAD is not set 395 */ 396 if ((termios->c_cflag & CREAD) == 0) 397 up->port.ignore_status_mask |= UART_LSR_DR; 398 399 /* 400 * Modem status interrupts 401 */ 402 up->ier &= ~UART_IER_MSI; 403 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 404 up->ier |= UART_IER_MSI; 405 406 up->lcr = cval; 407 /* Up to here it was mostly serial8250_do_set_termios() */ 408 409 /* 410 * We enable TRIG_GRANU for RX and TX and additionaly we set 411 * SCR_TX_EMPTY bit. The result is the following: 412 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. 413 * - less than RX_TRIGGER number of bytes will also cause an interrupt 414 * once the UART decides that there no new bytes arriving. 415 * - Once THRE is enabled, the interrupt will be fired once the FIFO is 416 * empty - the trigger level is ignored here. 417 * 418 * Once DMA is enabled: 419 * - UART will assert the TX DMA line once there is room for TX_TRIGGER 420 * bytes in the TX FIFO. On each assert the DMA engine will move 421 * TX_TRIGGER bytes into the FIFO. 422 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in 423 * the FIFO and move RX_TRIGGER bytes. 424 * This is because threshold and trigger values are the same. 425 */ 426 up->fcr = UART_FCR_ENABLE_FIFO; 427 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; 428 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; 429 430 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | 431 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; 432 433 if (up->dma) 434 priv->scr |= OMAP_UART_SCR_DMAMODE_1 | 435 OMAP_UART_SCR_DMAMODE_CTL; 436 437 priv->xon = termios->c_cc[VSTART]; 438 priv->xoff = termios->c_cc[VSTOP]; 439 440 priv->efr = 0; 441 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 442 443 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 444 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 445 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 446 priv->efr |= UART_EFR_CTS; 447 } else if (up->port.flags & UPF_SOFT_FLOW) { 448 /* 449 * OMAP rx s/w flow control is borked; the transmitter remains 450 * stuck off even if rx flow control is subsequently disabled 451 */ 452 453 /* 454 * IXOFF Flag: 455 * Enable XON/XOFF flow control on output. 456 * Transmit XON1, XOFF1 457 */ 458 if (termios->c_iflag & IXOFF) { 459 up->port.status |= UPSTAT_AUTOXOFF; 460 priv->efr |= OMAP_UART_SW_TX; 461 } 462 } 463 omap8250_restore_regs(up); 464 465 spin_unlock_irq(&up->port.lock); 466 pm_runtime_mark_last_busy(port->dev); 467 pm_runtime_put_autosuspend(port->dev); 468 469 /* calculate wakeup latency constraint */ 470 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; 471 priv->latency = priv->calc_latency; 472 473 schedule_work(&priv->qos_work); 474 475 /* Don't rewrite B0 */ 476 if (tty_termios_baud_rate(termios)) 477 tty_termios_encode_baud_rate(termios, baud, baud); 478 } 479 480 /* same as 8250 except that we may have extra flow bits set in EFR */ 481 static void omap_8250_pm(struct uart_port *port, unsigned int state, 482 unsigned int oldstate) 483 { 484 struct uart_8250_port *up = up_to_u8250p(port); 485 u8 efr; 486 487 pm_runtime_get_sync(port->dev); 488 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 489 efr = serial_in(up, UART_EFR); 490 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 491 serial_out(up, UART_LCR, 0); 492 493 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 494 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 495 serial_out(up, UART_EFR, efr); 496 serial_out(up, UART_LCR, 0); 497 498 pm_runtime_mark_last_busy(port->dev); 499 pm_runtime_put_autosuspend(port->dev); 500 } 501 502 static void omap_serial_fill_features_erratas(struct uart_8250_port *up, 503 struct omap8250_priv *priv) 504 { 505 u32 mvr, scheme; 506 u16 revision, major, minor; 507 508 mvr = uart_read(up, UART_OMAP_MVER); 509 510 /* Check revision register scheme */ 511 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 512 513 switch (scheme) { 514 case 0: /* Legacy Scheme: OMAP2/3 */ 515 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 516 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 517 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 518 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 519 break; 520 case 1: 521 /* New Scheme: OMAP4+ */ 522 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 523 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 524 OMAP_UART_MVR_MAJ_SHIFT; 525 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 526 break; 527 default: 528 dev_warn(up->port.dev, 529 "Unknown revision, defaulting to highest\n"); 530 /* highest possible revision */ 531 major = 0xff; 532 minor = 0xff; 533 } 534 /* normalize revision for the driver */ 535 revision = UART_BUILD_REVISION(major, minor); 536 537 switch (revision) { 538 case OMAP_UART_REV_46: 539 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; 540 break; 541 case OMAP_UART_REV_52: 542 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 543 OMAP_UART_WER_HAS_TX_WAKEUP; 544 break; 545 case OMAP_UART_REV_63: 546 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | 547 OMAP_UART_WER_HAS_TX_WAKEUP; 548 break; 549 default: 550 break; 551 } 552 } 553 554 static void omap8250_uart_qos_work(struct work_struct *work) 555 { 556 struct omap8250_priv *priv; 557 558 priv = container_of(work, struct omap8250_priv, qos_work); 559 pm_qos_update_request(&priv->pm_qos_request, priv->latency); 560 } 561 562 #ifdef CONFIG_SERIAL_8250_DMA 563 static int omap_8250_dma_handle_irq(struct uart_port *port); 564 #endif 565 566 static irqreturn_t omap8250_irq(int irq, void *dev_id) 567 { 568 struct uart_port *port = dev_id; 569 struct uart_8250_port *up = up_to_u8250p(port); 570 unsigned int iir; 571 int ret; 572 573 #ifdef CONFIG_SERIAL_8250_DMA 574 if (up->dma) { 575 ret = omap_8250_dma_handle_irq(port); 576 return IRQ_RETVAL(ret); 577 } 578 #endif 579 580 serial8250_rpm_get(up); 581 iir = serial_port_in(port, UART_IIR); 582 ret = serial8250_handle_irq(port, iir); 583 serial8250_rpm_put(up); 584 585 return IRQ_RETVAL(ret); 586 } 587 588 static int omap_8250_startup(struct uart_port *port) 589 { 590 struct uart_8250_port *up = up_to_u8250p(port); 591 struct omap8250_priv *priv = port->private_data; 592 int ret; 593 594 if (priv->wakeirq) { 595 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); 596 if (ret) 597 return ret; 598 } 599 600 pm_runtime_get_sync(port->dev); 601 602 up->mcr = 0; 603 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 604 605 serial_out(up, UART_LCR, UART_LCR_WLEN8); 606 607 up->lsr_saved_flags = 0; 608 up->msr_saved_flags = 0; 609 610 if (up->dma) { 611 ret = serial8250_request_dma(up); 612 if (ret) { 613 dev_warn_ratelimited(port->dev, 614 "failed to request DMA\n"); 615 up->dma = NULL; 616 } 617 } 618 619 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, 620 dev_name(port->dev), port); 621 if (ret < 0) 622 goto err; 623 624 up->ier = UART_IER_RLSI | UART_IER_RDI; 625 serial_out(up, UART_IER, up->ier); 626 627 #ifdef CONFIG_PM 628 up->capabilities |= UART_CAP_RPM; 629 #endif 630 631 /* Enable module level wake up */ 632 priv->wer = OMAP_UART_WER_MOD_WKUP; 633 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) 634 priv->wer |= OMAP_UART_TX_WAKEUP_EN; 635 serial_out(up, UART_OMAP_WER, priv->wer); 636 637 if (up->dma) 638 up->dma->rx_dma(up, 0); 639 640 pm_runtime_mark_last_busy(port->dev); 641 pm_runtime_put_autosuspend(port->dev); 642 return 0; 643 err: 644 pm_runtime_mark_last_busy(port->dev); 645 pm_runtime_put_autosuspend(port->dev); 646 dev_pm_clear_wake_irq(port->dev); 647 return ret; 648 } 649 650 static void omap_8250_shutdown(struct uart_port *port) 651 { 652 struct uart_8250_port *up = up_to_u8250p(port); 653 struct omap8250_priv *priv = port->private_data; 654 655 flush_work(&priv->qos_work); 656 if (up->dma) 657 up->dma->rx_dma(up, UART_IIR_RX_TIMEOUT); 658 659 pm_runtime_get_sync(port->dev); 660 661 serial_out(up, UART_OMAP_WER, 0); 662 663 up->ier = 0; 664 serial_out(up, UART_IER, 0); 665 666 if (up->dma) 667 serial8250_release_dma(up); 668 669 /* 670 * Disable break condition and FIFOs 671 */ 672 if (up->lcr & UART_LCR_SBC) 673 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); 674 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 675 676 pm_runtime_mark_last_busy(port->dev); 677 pm_runtime_put_autosuspend(port->dev); 678 free_irq(port->irq, port); 679 dev_pm_clear_wake_irq(port->dev); 680 } 681 682 static void omap_8250_throttle(struct uart_port *port) 683 { 684 struct uart_8250_port *up = up_to_u8250p(port); 685 unsigned long flags; 686 687 pm_runtime_get_sync(port->dev); 688 689 spin_lock_irqsave(&port->lock, flags); 690 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 691 serial_out(up, UART_IER, up->ier); 692 spin_unlock_irqrestore(&port->lock, flags); 693 694 pm_runtime_mark_last_busy(port->dev); 695 pm_runtime_put_autosuspend(port->dev); 696 } 697 698 static int omap_8250_rs485_config(struct uart_port *port, 699 struct serial_rs485 *rs485) 700 { 701 struct uart_8250_port *up = up_to_u8250p(port); 702 703 /* Clamp the delays to [0, 100ms] */ 704 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 705 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 706 707 port->rs485 = *rs485; 708 709 /* 710 * Both serial8250_em485_init and serial8250_em485_destroy 711 * are idempotent 712 */ 713 if (rs485->flags & SER_RS485_ENABLED) { 714 int ret = serial8250_em485_init(up); 715 716 if (ret) { 717 rs485->flags &= ~SER_RS485_ENABLED; 718 port->rs485.flags &= ~SER_RS485_ENABLED; 719 } 720 return ret; 721 } 722 723 serial8250_em485_destroy(up); 724 725 return 0; 726 } 727 728 static void omap_8250_unthrottle(struct uart_port *port) 729 { 730 struct uart_8250_port *up = up_to_u8250p(port); 731 unsigned long flags; 732 733 pm_runtime_get_sync(port->dev); 734 735 spin_lock_irqsave(&port->lock, flags); 736 up->ier |= UART_IER_RLSI | UART_IER_RDI; 737 serial_out(up, UART_IER, up->ier); 738 spin_unlock_irqrestore(&port->lock, flags); 739 740 pm_runtime_mark_last_busy(port->dev); 741 pm_runtime_put_autosuspend(port->dev); 742 } 743 744 #ifdef CONFIG_SERIAL_8250_DMA 745 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir); 746 747 static void __dma_rx_do_complete(struct uart_8250_port *p, bool error) 748 { 749 struct omap8250_priv *priv = p->port.private_data; 750 struct uart_8250_dma *dma = p->dma; 751 struct tty_port *tty_port = &p->port.state->port; 752 struct dma_tx_state state; 753 int count; 754 unsigned long flags; 755 int ret; 756 757 dma_sync_single_for_cpu(dma->rxchan->device->dev, dma->rx_addr, 758 dma->rx_size, DMA_FROM_DEVICE); 759 760 spin_lock_irqsave(&priv->rx_dma_lock, flags); 761 762 if (!dma->rx_running) 763 goto unlock; 764 765 dma->rx_running = 0; 766 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 767 dmaengine_terminate_all(dma->rxchan); 768 769 count = dma->rx_size - state.residue; 770 771 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); 772 773 p->port.icount.rx += ret; 774 p->port.icount.buf_overrun += count - ret; 775 unlock: 776 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 777 778 if (!error) 779 omap_8250_rx_dma(p, 0); 780 781 tty_flip_buffer_push(tty_port); 782 } 783 784 static void __dma_rx_complete(void *param) 785 { 786 __dma_rx_do_complete(param, false); 787 } 788 789 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) 790 { 791 struct omap8250_priv *priv = p->port.private_data; 792 struct uart_8250_dma *dma = p->dma; 793 unsigned long flags; 794 int ret; 795 796 spin_lock_irqsave(&priv->rx_dma_lock, flags); 797 798 if (!dma->rx_running) { 799 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 800 return; 801 } 802 803 ret = dmaengine_pause(dma->rxchan); 804 if (WARN_ON_ONCE(ret)) 805 priv->rx_dma_broken = true; 806 807 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 808 809 __dma_rx_do_complete(p, true); 810 } 811 812 static int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 813 { 814 struct omap8250_priv *priv = p->port.private_data; 815 struct uart_8250_dma *dma = p->dma; 816 int err = 0; 817 struct dma_async_tx_descriptor *desc; 818 unsigned long flags; 819 820 switch (iir & 0x3f) { 821 case UART_IIR_RLSI: 822 /* 8250_core handles errors and break interrupts */ 823 omap_8250_rx_dma_flush(p); 824 return -EIO; 825 case UART_IIR_RX_TIMEOUT: 826 /* 827 * If RCVR FIFO trigger level was not reached, complete the 828 * transfer and let 8250_core copy the remaining data. 829 */ 830 omap_8250_rx_dma_flush(p); 831 return -ETIMEDOUT; 832 case UART_IIR_RDI: 833 /* 834 * The OMAP UART is a special BEAST. If we receive RDI we _have_ 835 * a DMA transfer programmed but it didn't work. One reason is 836 * that we were too slow and there were too many bytes in the 837 * FIFO, the UART counted wrong and never kicked the DMA engine 838 * to do anything. That means once we receive RDI on OMAP then 839 * the DMA won't do anything soon so we have to cancel the DMA 840 * transfer and purge the FIFO manually. 841 */ 842 omap_8250_rx_dma_flush(p); 843 return -ETIMEDOUT; 844 845 default: 846 break; 847 } 848 849 if (priv->rx_dma_broken) 850 return -EINVAL; 851 852 spin_lock_irqsave(&priv->rx_dma_lock, flags); 853 854 if (dma->rx_running) 855 goto out; 856 857 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 858 dma->rx_size, DMA_DEV_TO_MEM, 859 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 860 if (!desc) { 861 err = -EBUSY; 862 goto out; 863 } 864 865 dma->rx_running = 1; 866 desc->callback = __dma_rx_complete; 867 desc->callback_param = p; 868 869 dma->rx_cookie = dmaengine_submit(desc); 870 871 dma_sync_single_for_device(dma->rxchan->device->dev, dma->rx_addr, 872 dma->rx_size, DMA_FROM_DEVICE); 873 874 dma_async_issue_pending(dma->rxchan); 875 out: 876 spin_unlock_irqrestore(&priv->rx_dma_lock, flags); 877 return err; 878 } 879 880 static int omap_8250_tx_dma(struct uart_8250_port *p); 881 882 static void omap_8250_dma_tx_complete(void *param) 883 { 884 struct uart_8250_port *p = param; 885 struct uart_8250_dma *dma = p->dma; 886 struct circ_buf *xmit = &p->port.state->xmit; 887 unsigned long flags; 888 bool en_thri = false; 889 struct omap8250_priv *priv = p->port.private_data; 890 891 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 892 UART_XMIT_SIZE, DMA_TO_DEVICE); 893 894 spin_lock_irqsave(&p->port.lock, flags); 895 896 dma->tx_running = 0; 897 898 xmit->tail += dma->tx_size; 899 xmit->tail &= UART_XMIT_SIZE - 1; 900 p->port.icount.tx += dma->tx_size; 901 902 if (priv->delayed_restore) { 903 priv->delayed_restore = 0; 904 omap8250_restore_regs(p); 905 } 906 907 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 908 uart_write_wakeup(&p->port); 909 910 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { 911 int ret; 912 913 ret = omap_8250_tx_dma(p); 914 if (ret) 915 en_thri = true; 916 917 } else if (p->capabilities & UART_CAP_RPM) { 918 en_thri = true; 919 } 920 921 if (en_thri) { 922 dma->tx_err = 1; 923 p->ier |= UART_IER_THRI; 924 serial_port_out(&p->port, UART_IER, p->ier); 925 } 926 927 spin_unlock_irqrestore(&p->port.lock, flags); 928 } 929 930 static int omap_8250_tx_dma(struct uart_8250_port *p) 931 { 932 struct uart_8250_dma *dma = p->dma; 933 struct omap8250_priv *priv = p->port.private_data; 934 struct circ_buf *xmit = &p->port.state->xmit; 935 struct dma_async_tx_descriptor *desc; 936 unsigned int skip_byte = 0; 937 int ret; 938 939 if (dma->tx_running) 940 return 0; 941 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { 942 943 /* 944 * Even if no data, we need to return an error for the two cases 945 * below so serial8250_tx_chars() is invoked and properly clears 946 * THRI and/or runtime suspend. 947 */ 948 if (dma->tx_err || p->capabilities & UART_CAP_RPM) { 949 ret = -EBUSY; 950 goto err; 951 } 952 if (p->ier & UART_IER_THRI) { 953 p->ier &= ~UART_IER_THRI; 954 serial_out(p, UART_IER, p->ier); 955 } 956 return 0; 957 } 958 959 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 960 if (priv->habit & OMAP_DMA_TX_KICK) { 961 u8 tx_lvl; 962 963 /* 964 * We need to put the first byte into the FIFO in order to start 965 * the DMA transfer. For transfers smaller than four bytes we 966 * don't bother doing DMA at all. It seem not matter if there 967 * are still bytes in the FIFO from the last transfer (in case 968 * we got here directly from omap_8250_dma_tx_complete()). Bytes 969 * leaving the FIFO seem not to trigger the DMA transfer. It is 970 * really the byte that we put into the FIFO. 971 * If the FIFO is already full then we most likely got here from 972 * omap_8250_dma_tx_complete(). And this means the DMA engine 973 * just completed its work. We don't have to wait the complete 974 * 86us at 115200,8n1 but around 60us (not to mention lower 975 * baudrates). So in that case we take the interrupt and try 976 * again with an empty FIFO. 977 */ 978 tx_lvl = serial_in(p, UART_OMAP_TX_LVL); 979 if (tx_lvl == p->tx_loadsz) { 980 ret = -EBUSY; 981 goto err; 982 } 983 if (dma->tx_size < 4) { 984 ret = -EINVAL; 985 goto err; 986 } 987 skip_byte = 1; 988 } 989 990 desc = dmaengine_prep_slave_single(dma->txchan, 991 dma->tx_addr + xmit->tail + skip_byte, 992 dma->tx_size - skip_byte, DMA_MEM_TO_DEV, 993 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 994 if (!desc) { 995 ret = -EBUSY; 996 goto err; 997 } 998 999 dma->tx_running = 1; 1000 1001 desc->callback = omap_8250_dma_tx_complete; 1002 desc->callback_param = p; 1003 1004 dma->tx_cookie = dmaengine_submit(desc); 1005 1006 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, 1007 UART_XMIT_SIZE, DMA_TO_DEVICE); 1008 1009 dma_async_issue_pending(dma->txchan); 1010 if (dma->tx_err) 1011 dma->tx_err = 0; 1012 1013 if (p->ier & UART_IER_THRI) { 1014 p->ier &= ~UART_IER_THRI; 1015 serial_out(p, UART_IER, p->ier); 1016 } 1017 if (skip_byte) 1018 serial_out(p, UART_TX, xmit->buf[xmit->tail]); 1019 return 0; 1020 err: 1021 dma->tx_err = 1; 1022 return ret; 1023 } 1024 1025 /* 1026 * This is mostly serial8250_handle_irq(). We have a slightly different DMA 1027 * hoook for RX/TX and need different logic for them in the ISR. Therefore we 1028 * use the default routine in the non-DMA case and this one for with DMA. 1029 */ 1030 static int omap_8250_dma_handle_irq(struct uart_port *port) 1031 { 1032 struct uart_8250_port *up = up_to_u8250p(port); 1033 unsigned char status; 1034 unsigned long flags; 1035 u8 iir; 1036 int dma_err = 0; 1037 1038 serial8250_rpm_get(up); 1039 1040 iir = serial_port_in(port, UART_IIR); 1041 if (iir & UART_IIR_NO_INT) { 1042 serial8250_rpm_put(up); 1043 return 0; 1044 } 1045 1046 spin_lock_irqsave(&port->lock, flags); 1047 1048 status = serial_port_in(port, UART_LSR); 1049 1050 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1051 1052 dma_err = omap_8250_rx_dma(up, iir); 1053 if (dma_err) { 1054 status = serial8250_rx_chars(up, status); 1055 omap_8250_rx_dma(up, 0); 1056 } 1057 } 1058 serial8250_modem_status(up); 1059 if (status & UART_LSR_THRE && up->dma->tx_err) { 1060 if (uart_tx_stopped(&up->port) || 1061 uart_circ_empty(&up->port.state->xmit)) { 1062 up->dma->tx_err = 0; 1063 serial8250_tx_chars(up); 1064 } else { 1065 /* 1066 * try again due to an earlier failer which 1067 * might have been resolved by now. 1068 */ 1069 dma_err = omap_8250_tx_dma(up); 1070 if (dma_err) 1071 serial8250_tx_chars(up); 1072 } 1073 } 1074 1075 spin_unlock_irqrestore(&port->lock, flags); 1076 serial8250_rpm_put(up); 1077 return 1; 1078 } 1079 1080 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) 1081 { 1082 return false; 1083 } 1084 1085 #else 1086 1087 static inline int omap_8250_rx_dma(struct uart_8250_port *p, unsigned int iir) 1088 { 1089 return -EINVAL; 1090 } 1091 #endif 1092 1093 static int omap8250_no_handle_irq(struct uart_port *port) 1094 { 1095 /* IRQ has not been requested but handling irq? */ 1096 WARN_ONCE(1, "Unexpected irq handling before port startup\n"); 1097 return 0; 1098 } 1099 1100 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; 1101 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE; 1102 1103 static const struct of_device_id omap8250_dt_ids[] = { 1104 { .compatible = "ti,omap2-uart" }, 1105 { .compatible = "ti,omap3-uart" }, 1106 { .compatible = "ti,omap4-uart" }, 1107 { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, 1108 { .compatible = "ti,am4372-uart", .data = &am4372_habit, }, 1109 { .compatible = "ti,dra742-uart", .data = &am4372_habit, }, 1110 {}, 1111 }; 1112 MODULE_DEVICE_TABLE(of, omap8250_dt_ids); 1113 1114 static int omap8250_probe(struct platform_device *pdev) 1115 { 1116 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1117 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1118 struct omap8250_priv *priv; 1119 struct uart_8250_port up; 1120 int ret; 1121 void __iomem *membase; 1122 1123 if (!regs || !irq) { 1124 dev_err(&pdev->dev, "missing registers or irq\n"); 1125 return -EINVAL; 1126 } 1127 1128 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1129 if (!priv) 1130 return -ENOMEM; 1131 1132 membase = devm_ioremap_nocache(&pdev->dev, regs->start, 1133 resource_size(regs)); 1134 if (!membase) 1135 return -ENODEV; 1136 1137 memset(&up, 0, sizeof(up)); 1138 up.port.dev = &pdev->dev; 1139 up.port.mapbase = regs->start; 1140 up.port.membase = membase; 1141 up.port.irq = irq->start; 1142 /* 1143 * It claims to be 16C750 compatible however it is a little different. 1144 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to 1145 * have) is enabled via EFR instead of MCR. The type is set here 8250 1146 * just to get things going. UNKNOWN does not work for a few reasons and 1147 * we don't need our own type since we don't use 8250's set_termios() 1148 * or pm callback. 1149 */ 1150 up.port.type = PORT_8250; 1151 up.port.iotype = UPIO_MEM; 1152 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | 1153 UPF_HARD_FLOW; 1154 up.port.private_data = priv; 1155 1156 up.port.regshift = 2; 1157 up.port.fifosize = 64; 1158 up.tx_loadsz = 64; 1159 up.capabilities = UART_CAP_FIFO; 1160 #ifdef CONFIG_PM 1161 /* 1162 * Runtime PM is mostly transparent. However to do it right we need to a 1163 * TX empty interrupt before we can put the device to auto idle. So if 1164 * PM is not enabled we don't add that flag and can spare that one extra 1165 * interrupt in the TX path. 1166 */ 1167 up.capabilities |= UART_CAP_RPM; 1168 #endif 1169 up.port.set_termios = omap_8250_set_termios; 1170 up.port.set_mctrl = omap8250_set_mctrl; 1171 up.port.pm = omap_8250_pm; 1172 up.port.startup = omap_8250_startup; 1173 up.port.shutdown = omap_8250_shutdown; 1174 up.port.throttle = omap_8250_throttle; 1175 up.port.unthrottle = omap_8250_unthrottle; 1176 up.port.rs485_config = omap_8250_rs485_config; 1177 1178 if (pdev->dev.of_node) { 1179 const struct of_device_id *id; 1180 1181 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1182 1183 of_property_read_u32(pdev->dev.of_node, "clock-frequency", 1184 &up.port.uartclk); 1185 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1186 1187 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); 1188 if (id && id->data) 1189 priv->habit |= *(u8 *)id->data; 1190 } else { 1191 ret = pdev->id; 1192 } 1193 if (ret < 0) { 1194 dev_err(&pdev->dev, "failed to get alias/pdev id\n"); 1195 return ret; 1196 } 1197 up.port.line = ret; 1198 1199 if (!up.port.uartclk) { 1200 up.port.uartclk = DEFAULT_CLK_SPEED; 1201 dev_warn(&pdev->dev, 1202 "No clock speed specified: using default: %d\n", 1203 DEFAULT_CLK_SPEED); 1204 } 1205 1206 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1207 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1208 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, 1209 priv->latency); 1210 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); 1211 1212 spin_lock_init(&priv->rx_dma_lock); 1213 1214 device_init_wakeup(&pdev->dev, true); 1215 pm_runtime_use_autosuspend(&pdev->dev); 1216 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1217 1218 pm_runtime_irq_safe(&pdev->dev); 1219 pm_runtime_enable(&pdev->dev); 1220 1221 pm_runtime_get_sync(&pdev->dev); 1222 1223 omap_serial_fill_features_erratas(&up, priv); 1224 up.port.handle_irq = omap8250_no_handle_irq; 1225 #ifdef CONFIG_SERIAL_8250_DMA 1226 if (pdev->dev.of_node) { 1227 /* 1228 * Oh DMA support. If there are no DMA properties in the DT then 1229 * we will fall back to a generic DMA channel which does not 1230 * really work here. To ensure that we do not get a generic DMA 1231 * channel assigned, we have the the_no_dma_filter_fn() here. 1232 * To avoid "failed to request DMA" messages we check for DMA 1233 * properties in DT. 1234 */ 1235 ret = of_property_count_strings(pdev->dev.of_node, "dma-names"); 1236 if (ret == 2) { 1237 up.dma = &priv->omap8250_dma; 1238 priv->omap8250_dma.fn = the_no_dma_filter_fn; 1239 priv->omap8250_dma.tx_dma = omap_8250_tx_dma; 1240 priv->omap8250_dma.rx_dma = omap_8250_rx_dma; 1241 priv->omap8250_dma.rx_size = RX_TRIGGER; 1242 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; 1243 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; 1244 1245 if (of_machine_is_compatible("ti,am33xx")) 1246 priv->habit |= OMAP_DMA_TX_KICK; 1247 /* 1248 * pause is currently not supported atleast on omap-sdma 1249 * and edma on most earlier kernels. 1250 */ 1251 priv->rx_dma_broken = true; 1252 } 1253 } 1254 #endif 1255 ret = serial8250_register_8250_port(&up); 1256 if (ret < 0) { 1257 dev_err(&pdev->dev, "unable to register 8250 port\n"); 1258 goto err; 1259 } 1260 priv->line = ret; 1261 platform_set_drvdata(pdev, priv); 1262 pm_runtime_mark_last_busy(&pdev->dev); 1263 pm_runtime_put_autosuspend(&pdev->dev); 1264 return 0; 1265 err: 1266 pm_runtime_put(&pdev->dev); 1267 pm_runtime_disable(&pdev->dev); 1268 return ret; 1269 } 1270 1271 static int omap8250_remove(struct platform_device *pdev) 1272 { 1273 struct omap8250_priv *priv = platform_get_drvdata(pdev); 1274 1275 pm_runtime_put_sync(&pdev->dev); 1276 pm_runtime_disable(&pdev->dev); 1277 serial8250_unregister_port(priv->line); 1278 pm_qos_remove_request(&priv->pm_qos_request); 1279 device_init_wakeup(&pdev->dev, false); 1280 return 0; 1281 } 1282 1283 #ifdef CONFIG_PM_SLEEP 1284 static int omap8250_prepare(struct device *dev) 1285 { 1286 struct omap8250_priv *priv = dev_get_drvdata(dev); 1287 1288 if (!priv) 1289 return 0; 1290 priv->is_suspending = true; 1291 return 0; 1292 } 1293 1294 static void omap8250_complete(struct device *dev) 1295 { 1296 struct omap8250_priv *priv = dev_get_drvdata(dev); 1297 1298 if (!priv) 1299 return; 1300 priv->is_suspending = false; 1301 } 1302 1303 static int omap8250_suspend(struct device *dev) 1304 { 1305 struct omap8250_priv *priv = dev_get_drvdata(dev); 1306 1307 serial8250_suspend_port(priv->line); 1308 flush_work(&priv->qos_work); 1309 return 0; 1310 } 1311 1312 static int omap8250_resume(struct device *dev) 1313 { 1314 struct omap8250_priv *priv = dev_get_drvdata(dev); 1315 1316 serial8250_resume_port(priv->line); 1317 return 0; 1318 } 1319 #else 1320 #define omap8250_prepare NULL 1321 #define omap8250_complete NULL 1322 #endif 1323 1324 #ifdef CONFIG_PM 1325 static int omap8250_lost_context(struct uart_8250_port *up) 1326 { 1327 u32 val; 1328 1329 val = serial_in(up, UART_OMAP_SCR); 1330 /* 1331 * If we lose context, then SCR is set to its reset value of zero. 1332 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, 1333 * among other bits, to never set the register back to zero again. 1334 */ 1335 if (!val) 1336 return 1; 1337 return 0; 1338 } 1339 1340 /* TODO: in future, this should happen via API in drivers/reset/ */ 1341 static int omap8250_soft_reset(struct device *dev) 1342 { 1343 struct omap8250_priv *priv = dev_get_drvdata(dev); 1344 struct uart_8250_port *up = serial8250_get_port(priv->line); 1345 int timeout = 100; 1346 int sysc; 1347 int syss; 1348 1349 sysc = serial_in(up, UART_OMAP_SYSC); 1350 1351 /* softreset the UART */ 1352 sysc |= OMAP_UART_SYSC_SOFTRESET; 1353 serial_out(up, UART_OMAP_SYSC, sysc); 1354 1355 /* By experiments, 1us enough for reset complete on AM335x */ 1356 do { 1357 udelay(1); 1358 syss = serial_in(up, UART_OMAP_SYSS); 1359 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); 1360 1361 if (!timeout) { 1362 dev_err(dev, "timed out waiting for reset done\n"); 1363 return -ETIMEDOUT; 1364 } 1365 1366 return 0; 1367 } 1368 1369 static int omap8250_runtime_suspend(struct device *dev) 1370 { 1371 struct omap8250_priv *priv = dev_get_drvdata(dev); 1372 struct uart_8250_port *up; 1373 1374 up = serial8250_get_port(priv->line); 1375 /* 1376 * When using 'no_console_suspend', the console UART must not be 1377 * suspended. Since driver suspend is managed by runtime suspend, 1378 * preventing runtime suspend (by returning error) will keep device 1379 * active during suspend. 1380 */ 1381 if (priv->is_suspending && !console_suspend_enabled) { 1382 if (uart_console(&up->port)) 1383 return -EBUSY; 1384 } 1385 1386 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { 1387 int ret; 1388 1389 ret = omap8250_soft_reset(dev); 1390 if (ret) 1391 return ret; 1392 1393 /* Restore to UART mode after reset (for wakeup) */ 1394 omap8250_update_mdr1(up, priv); 1395 } 1396 1397 if (up->dma && up->dma->rxchan) 1398 omap_8250_rx_dma(up, UART_IIR_RX_TIMEOUT); 1399 1400 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1401 schedule_work(&priv->qos_work); 1402 1403 return 0; 1404 } 1405 1406 static int omap8250_runtime_resume(struct device *dev) 1407 { 1408 struct omap8250_priv *priv = dev_get_drvdata(dev); 1409 struct uart_8250_port *up; 1410 int loss_cntx; 1411 1412 /* In case runtime-pm tries this before we are setup */ 1413 if (!priv) 1414 return 0; 1415 1416 up = serial8250_get_port(priv->line); 1417 loss_cntx = omap8250_lost_context(up); 1418 1419 if (loss_cntx) 1420 omap8250_restore_regs(up); 1421 1422 if (up->dma && up->dma->rxchan) 1423 omap_8250_rx_dma(up, 0); 1424 1425 priv->latency = priv->calc_latency; 1426 schedule_work(&priv->qos_work); 1427 return 0; 1428 } 1429 #endif 1430 1431 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP 1432 static int __init omap8250_console_fixup(void) 1433 { 1434 char *omap_str; 1435 char *options; 1436 u8 idx; 1437 1438 if (strstr(boot_command_line, "console=ttyS")) 1439 /* user set a ttyS based name for the console */ 1440 return 0; 1441 1442 omap_str = strstr(boot_command_line, "console=ttyO"); 1443 if (!omap_str) 1444 /* user did not set ttyO based console, so we don't care */ 1445 return 0; 1446 1447 omap_str += 12; 1448 if ('0' <= *omap_str && *omap_str <= '9') 1449 idx = *omap_str - '0'; 1450 else 1451 return 0; 1452 1453 omap_str++; 1454 if (omap_str[0] == ',') { 1455 omap_str++; 1456 options = omap_str; 1457 } else { 1458 options = NULL; 1459 } 1460 1461 add_preferred_console("ttyS", idx, options); 1462 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", 1463 idx, idx); 1464 pr_err("This ensures that you still see kernel messages. Please\n"); 1465 pr_err("update your kernel commandline.\n"); 1466 return 0; 1467 } 1468 console_initcall(omap8250_console_fixup); 1469 #endif 1470 1471 static const struct dev_pm_ops omap8250_dev_pm_ops = { 1472 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) 1473 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, 1474 omap8250_runtime_resume, NULL) 1475 .prepare = omap8250_prepare, 1476 .complete = omap8250_complete, 1477 }; 1478 1479 static struct platform_driver omap8250_platform_driver = { 1480 .driver = { 1481 .name = "omap8250", 1482 .pm = &omap8250_dev_pm_ops, 1483 .of_match_table = omap8250_dt_ids, 1484 }, 1485 .probe = omap8250_probe, 1486 .remove = omap8250_remove, 1487 }; 1488 module_platform_driver(omap8250_platform_driver); 1489 1490 MODULE_AUTHOR("Sebastian Andrzej Siewior"); 1491 MODULE_DESCRIPTION("OMAP 8250 Driver"); 1492 MODULE_LICENSE("GPL v2"); 1493