1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Serial Port driver for Open Firmware platform devices 4 * 5 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp. 6 */ 7 #include <linux/console.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/delay.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_reg.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/clk.h> 18 #include <linux/reset.h> 19 20 #include "8250.h" 21 22 struct of_serial_info { 23 struct clk *clk; 24 struct reset_control *rst; 25 int type; 26 int line; 27 }; 28 29 #ifdef CONFIG_ARCH_TEGRA 30 static void tegra_serial_handle_break(struct uart_port *p) 31 { 32 unsigned int status, tmout = 10000; 33 34 do { 35 status = p->serial_in(p, UART_LSR); 36 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 37 status = p->serial_in(p, UART_RX); 38 else 39 break; 40 if (--tmout == 0) 41 break; 42 udelay(1); 43 } while (1); 44 } 45 #else 46 static inline void tegra_serial_handle_break(struct uart_port *port) 47 { 48 } 49 #endif 50 51 static int of_8250_rs485_config(struct uart_port *port, 52 struct serial_rs485 *rs485) 53 { 54 struct uart_8250_port *up = up_to_u8250p(port); 55 56 /* Clamp the delays to [0, 100ms] */ 57 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); 58 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); 59 60 port->rs485 = *rs485; 61 62 /* 63 * Both serial8250_em485_init and serial8250_em485_destroy 64 * are idempotent 65 */ 66 if (rs485->flags & SER_RS485_ENABLED) { 67 int ret = serial8250_em485_init(up); 68 69 if (ret) { 70 rs485->flags &= ~SER_RS485_ENABLED; 71 port->rs485.flags &= ~SER_RS485_ENABLED; 72 } 73 return ret; 74 } 75 76 serial8250_em485_destroy(up); 77 78 return 0; 79 } 80 81 /* 82 * Fill a struct uart_port for a given device node 83 */ 84 static int of_platform_serial_setup(struct platform_device *ofdev, 85 int type, struct uart_port *port, 86 struct of_serial_info *info) 87 { 88 struct resource resource; 89 struct device_node *np = ofdev->dev.of_node; 90 u32 clk, spd, prop; 91 int ret, irq; 92 93 memset(port, 0, sizeof *port); 94 95 pm_runtime_enable(&ofdev->dev); 96 pm_runtime_get_sync(&ofdev->dev); 97 98 if (of_property_read_u32(np, "clock-frequency", &clk)) { 99 100 /* Get clk rate through clk driver if present */ 101 info->clk = devm_clk_get(&ofdev->dev, NULL); 102 if (IS_ERR(info->clk)) { 103 ret = PTR_ERR(info->clk); 104 if (ret != -EPROBE_DEFER) 105 dev_warn(&ofdev->dev, 106 "failed to get clock: %d\n", ret); 107 goto err_pmruntime; 108 } 109 110 ret = clk_prepare_enable(info->clk); 111 if (ret < 0) 112 goto err_pmruntime; 113 114 clk = clk_get_rate(info->clk); 115 } 116 /* If current-speed was set, then try not to change it. */ 117 if (of_property_read_u32(np, "current-speed", &spd) == 0) 118 port->custom_divisor = clk / (16 * spd); 119 120 ret = of_address_to_resource(np, 0, &resource); 121 if (ret) { 122 dev_warn(&ofdev->dev, "invalid address\n"); 123 goto err_unprepare; 124 } 125 126 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | 127 UPF_FIXED_TYPE; 128 spin_lock_init(&port->lock); 129 130 if (resource_type(&resource) == IORESOURCE_IO) { 131 port->iotype = UPIO_PORT; 132 port->iobase = resource.start; 133 } else { 134 port->mapbase = resource.start; 135 port->mapsize = resource_size(&resource); 136 137 /* Check for shifted address mapping */ 138 if (of_property_read_u32(np, "reg-offset", &prop) == 0) 139 port->mapbase += prop; 140 141 port->iotype = UPIO_MEM; 142 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 143 switch (prop) { 144 case 1: 145 port->iotype = UPIO_MEM; 146 break; 147 case 2: 148 port->iotype = UPIO_MEM16; 149 break; 150 case 4: 151 port->iotype = of_device_is_big_endian(np) ? 152 UPIO_MEM32BE : UPIO_MEM32; 153 break; 154 default: 155 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 156 prop); 157 ret = -EINVAL; 158 goto err_unprepare; 159 } 160 } 161 port->flags |= UPF_IOREMAP; 162 } 163 164 /* Compatibility with the deprecated pxa driver and 8250_pxa drivers. */ 165 if (of_device_is_compatible(np, "mrvl,mmp-uart")) 166 port->regshift = 2; 167 168 /* Check for registers offset within the devices address range */ 169 if (of_property_read_u32(np, "reg-shift", &prop) == 0) 170 port->regshift = prop; 171 172 /* Check for fifo size */ 173 if (of_property_read_u32(np, "fifo-size", &prop) == 0) 174 port->fifosize = prop; 175 176 /* Check for a fixed line number */ 177 ret = of_alias_get_id(np, "serial"); 178 if (ret >= 0) 179 port->line = ret; 180 181 irq = of_irq_get(np, 0); 182 if (irq < 0) { 183 if (irq == -EPROBE_DEFER) { 184 ret = -EPROBE_DEFER; 185 goto err_unprepare; 186 } 187 /* IRQ support not mandatory */ 188 irq = 0; 189 } 190 191 port->irq = irq; 192 193 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 194 if (IS_ERR(info->rst)) { 195 ret = PTR_ERR(info->rst); 196 goto err_unprepare; 197 } 198 199 ret = reset_control_deassert(info->rst); 200 if (ret) 201 goto err_unprepare; 202 203 port->type = type; 204 port->uartclk = clk; 205 206 if (of_property_read_bool(np, "no-loopback-test")) 207 port->flags |= UPF_SKIP_TEST; 208 209 port->dev = &ofdev->dev; 210 port->rs485_config = of_8250_rs485_config; 211 212 switch (type) { 213 case PORT_TEGRA: 214 port->handle_break = tegra_serial_handle_break; 215 break; 216 217 case PORT_RT2880: 218 port->iotype = UPIO_AU; 219 break; 220 } 221 222 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 223 (of_device_is_compatible(np, "fsl,ns16550") || 224 of_device_is_compatible(np, "fsl,16550-FIFO64"))) { 225 port->handle_irq = fsl8250_handle_irq; 226 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE); 227 } 228 229 return 0; 230 err_unprepare: 231 clk_disable_unprepare(info->clk); 232 err_pmruntime: 233 pm_runtime_put_sync(&ofdev->dev); 234 pm_runtime_disable(&ofdev->dev); 235 return ret; 236 } 237 238 /* 239 * Try to register a serial port 240 */ 241 static int of_platform_serial_probe(struct platform_device *ofdev) 242 { 243 struct of_serial_info *info; 244 struct uart_8250_port port8250; 245 unsigned int port_type; 246 u32 tx_threshold; 247 int ret; 248 249 port_type = (unsigned long)of_device_get_match_data(&ofdev->dev); 250 if (port_type == PORT_UNKNOWN) 251 return -EINVAL; 252 253 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas")) 254 return -EBUSY; 255 256 info = kzalloc(sizeof(*info), GFP_KERNEL); 257 if (info == NULL) 258 return -ENOMEM; 259 260 memset(&port8250, 0, sizeof(port8250)); 261 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info); 262 if (ret) 263 goto err_free; 264 265 if (port8250.port.fifosize) 266 port8250.capabilities = UART_CAP_FIFO; 267 268 /* Check for TX FIFO threshold & set tx_loadsz */ 269 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold", 270 &tx_threshold) == 0) && 271 (tx_threshold < port8250.port.fifosize)) 272 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold; 273 274 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control")) 275 port8250.capabilities |= UART_CAP_AFE; 276 277 if (of_property_read_u32(ofdev->dev.of_node, 278 "overrun-throttle-ms", 279 &port8250.overrun_backoff_time_ms) != 0) 280 port8250.overrun_backoff_time_ms = 0; 281 282 ret = serial8250_register_8250_port(&port8250); 283 if (ret < 0) 284 goto err_dispose; 285 286 info->type = port_type; 287 info->line = ret; 288 platform_set_drvdata(ofdev, info); 289 return 0; 290 err_dispose: 291 irq_dispose_mapping(port8250.port.irq); 292 pm_runtime_put_sync(&ofdev->dev); 293 pm_runtime_disable(&ofdev->dev); 294 clk_disable_unprepare(info->clk); 295 err_free: 296 kfree(info); 297 return ret; 298 } 299 300 /* 301 * Release a line 302 */ 303 static int of_platform_serial_remove(struct platform_device *ofdev) 304 { 305 struct of_serial_info *info = platform_get_drvdata(ofdev); 306 307 serial8250_unregister_port(info->line); 308 309 reset_control_assert(info->rst); 310 pm_runtime_put_sync(&ofdev->dev); 311 pm_runtime_disable(&ofdev->dev); 312 clk_disable_unprepare(info->clk); 313 kfree(info); 314 return 0; 315 } 316 317 #ifdef CONFIG_PM_SLEEP 318 static int of_serial_suspend(struct device *dev) 319 { 320 struct of_serial_info *info = dev_get_drvdata(dev); 321 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 322 struct uart_port *port = &port8250->port; 323 324 serial8250_suspend_port(info->line); 325 326 if (!uart_console(port) || console_suspend_enabled) { 327 pm_runtime_put_sync(dev); 328 clk_disable_unprepare(info->clk); 329 } 330 return 0; 331 } 332 333 static int of_serial_resume(struct device *dev) 334 { 335 struct of_serial_info *info = dev_get_drvdata(dev); 336 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 337 struct uart_port *port = &port8250->port; 338 339 if (!uart_console(port) || console_suspend_enabled) { 340 pm_runtime_get_sync(dev); 341 clk_prepare_enable(info->clk); 342 } 343 344 serial8250_resume_port(info->line); 345 346 return 0; 347 } 348 #endif 349 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); 350 351 /* 352 * A few common types, add more as needed. 353 */ 354 static const struct of_device_id of_platform_serial_table[] = { 355 { .compatible = "ns8250", .data = (void *)PORT_8250, }, 356 { .compatible = "ns16450", .data = (void *)PORT_16450, }, 357 { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, 358 { .compatible = "ns16550", .data = (void *)PORT_16550, }, 359 { .compatible = "ns16750", .data = (void *)PORT_16750, }, 360 { .compatible = "ns16850", .data = (void *)PORT_16850, }, 361 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, }, 362 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, }, 363 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, }, 364 { .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, }, 365 { .compatible = "altr,16550-FIFO32", 366 .data = (void *)PORT_ALTR_16550_F32, }, 367 { .compatible = "altr,16550-FIFO64", 368 .data = (void *)PORT_ALTR_16550_F64, }, 369 { .compatible = "altr,16550-FIFO128", 370 .data = (void *)PORT_ALTR_16550_F128, }, 371 { .compatible = "mediatek,mtk-btif", 372 .data = (void *)PORT_MTK_BTIF, }, 373 { .compatible = "mrvl,mmp-uart", 374 .data = (void *)PORT_XSCALE, }, 375 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, 376 { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, }, 377 { /* end of list */ }, 378 }; 379 MODULE_DEVICE_TABLE(of, of_platform_serial_table); 380 381 static struct platform_driver of_platform_serial_driver = { 382 .driver = { 383 .name = "of_serial", 384 .of_match_table = of_platform_serial_table, 385 .pm = &of_serial_pm_ops, 386 }, 387 .probe = of_platform_serial_probe, 388 .remove = of_platform_serial_remove, 389 }; 390 391 module_platform_driver(of_platform_serial_driver); 392 393 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>"); 394 MODULE_LICENSE("GPL"); 395 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices"); 396