1 /* 2 * Serial Port driver for Open Firmware platform devices 3 * 4 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 * 11 */ 12 #include <linux/console.h> 13 #include <linux/module.h> 14 #include <linux/slab.h> 15 #include <linux/delay.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/clk.h> 23 #include <linux/reset.h> 24 25 #include "8250.h" 26 27 struct of_serial_info { 28 struct clk *clk; 29 struct reset_control *rst; 30 int type; 31 int line; 32 }; 33 34 #ifdef CONFIG_ARCH_TEGRA 35 static void tegra_serial_handle_break(struct uart_port *p) 36 { 37 unsigned int status, tmout = 10000; 38 39 do { 40 status = p->serial_in(p, UART_LSR); 41 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 42 status = p->serial_in(p, UART_RX); 43 else 44 break; 45 if (--tmout == 0) 46 break; 47 udelay(1); 48 } while (1); 49 } 50 #else 51 static inline void tegra_serial_handle_break(struct uart_port *port) 52 { 53 } 54 #endif 55 56 /* 57 * Fill a struct uart_port for a given device node 58 */ 59 static int of_platform_serial_setup(struct platform_device *ofdev, 60 int type, struct uart_port *port, 61 struct of_serial_info *info) 62 { 63 struct resource resource; 64 struct device_node *np = ofdev->dev.of_node; 65 u32 clk, spd, prop; 66 int ret; 67 68 memset(port, 0, sizeof *port); 69 70 pm_runtime_enable(&ofdev->dev); 71 pm_runtime_get_sync(&ofdev->dev); 72 73 if (of_property_read_u32(np, "clock-frequency", &clk)) { 74 75 /* Get clk rate through clk driver if present */ 76 info->clk = devm_clk_get(&ofdev->dev, NULL); 77 if (IS_ERR(info->clk)) { 78 dev_warn(&ofdev->dev, 79 "clk or clock-frequency not defined\n"); 80 ret = PTR_ERR(info->clk); 81 goto err_pmruntime; 82 } 83 84 ret = clk_prepare_enable(info->clk); 85 if (ret < 0) 86 goto err_pmruntime; 87 88 clk = clk_get_rate(info->clk); 89 } 90 /* If current-speed was set, then try not to change it. */ 91 if (of_property_read_u32(np, "current-speed", &spd) == 0) 92 port->custom_divisor = clk / (16 * spd); 93 94 ret = of_address_to_resource(np, 0, &resource); 95 if (ret) { 96 dev_warn(&ofdev->dev, "invalid address\n"); 97 goto err_unprepare; 98 } 99 100 spin_lock_init(&port->lock); 101 port->mapbase = resource.start; 102 port->mapsize = resource_size(&resource); 103 104 /* Check for shifted address mapping */ 105 if (of_property_read_u32(np, "reg-offset", &prop) == 0) 106 port->mapbase += prop; 107 108 /* Check for registers offset within the devices address range */ 109 if (of_property_read_u32(np, "reg-shift", &prop) == 0) 110 port->regshift = prop; 111 112 /* Check for fifo size */ 113 if (of_property_read_u32(np, "fifo-size", &prop) == 0) 114 port->fifosize = prop; 115 116 /* Check for a fixed line number */ 117 ret = of_alias_get_id(np, "serial"); 118 if (ret >= 0) 119 port->line = ret; 120 121 port->irq = irq_of_parse_and_map(np, 0); 122 port->iotype = UPIO_MEM; 123 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 124 switch (prop) { 125 case 1: 126 port->iotype = UPIO_MEM; 127 break; 128 case 2: 129 port->iotype = UPIO_MEM16; 130 break; 131 case 4: 132 port->iotype = of_device_is_big_endian(np) ? 133 UPIO_MEM32BE : UPIO_MEM32; 134 break; 135 default: 136 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 137 prop); 138 ret = -EINVAL; 139 goto err_dispose; 140 } 141 } 142 143 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 144 if (IS_ERR(info->rst)) 145 goto err_dispose; 146 ret = reset_control_deassert(info->rst); 147 if (ret) 148 goto err_dispose; 149 150 port->type = type; 151 port->uartclk = clk; 152 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP 153 | UPF_FIXED_PORT | UPF_FIXED_TYPE; 154 155 if (of_property_read_bool(np, "no-loopback-test")) 156 port->flags |= UPF_SKIP_TEST; 157 158 port->dev = &ofdev->dev; 159 160 switch (type) { 161 case PORT_TEGRA: 162 port->handle_break = tegra_serial_handle_break; 163 break; 164 165 case PORT_RT2880: 166 port->iotype = UPIO_AU; 167 break; 168 } 169 170 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 171 (of_device_is_compatible(np, "fsl,ns16550") || 172 of_device_is_compatible(np, "fsl,16550-FIFO64"))) 173 port->handle_irq = fsl8250_handle_irq; 174 175 return 0; 176 err_dispose: 177 irq_dispose_mapping(port->irq); 178 err_unprepare: 179 clk_disable_unprepare(info->clk); 180 err_pmruntime: 181 pm_runtime_put_sync(&ofdev->dev); 182 pm_runtime_disable(&ofdev->dev); 183 return ret; 184 } 185 186 /* 187 * Try to register a serial port 188 */ 189 static const struct of_device_id of_platform_serial_table[]; 190 static int of_platform_serial_probe(struct platform_device *ofdev) 191 { 192 const struct of_device_id *match; 193 struct of_serial_info *info; 194 struct uart_8250_port port8250; 195 u32 tx_threshold; 196 int port_type; 197 int ret; 198 199 match = of_match_device(of_platform_serial_table, &ofdev->dev); 200 if (!match) 201 return -EINVAL; 202 203 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas")) 204 return -EBUSY; 205 206 info = kzalloc(sizeof(*info), GFP_KERNEL); 207 if (info == NULL) 208 return -ENOMEM; 209 210 port_type = (unsigned long)match->data; 211 memset(&port8250, 0, sizeof(port8250)); 212 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info); 213 if (ret) 214 goto err_free; 215 216 if (port8250.port.fifosize) 217 port8250.capabilities = UART_CAP_FIFO; 218 219 /* Check for TX FIFO threshold & set tx_loadsz */ 220 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold", 221 &tx_threshold) == 0) && 222 (tx_threshold < port8250.port.fifosize)) 223 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold; 224 225 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control")) 226 port8250.capabilities |= UART_CAP_AFE; 227 228 ret = serial8250_register_8250_port(&port8250); 229 if (ret < 0) 230 goto err_dispose; 231 232 info->type = port_type; 233 info->line = ret; 234 platform_set_drvdata(ofdev, info); 235 return 0; 236 err_dispose: 237 irq_dispose_mapping(port8250.port.irq); 238 pm_runtime_put_sync(&ofdev->dev); 239 pm_runtime_disable(&ofdev->dev); 240 clk_disable_unprepare(info->clk); 241 err_free: 242 kfree(info); 243 return ret; 244 } 245 246 /* 247 * Release a line 248 */ 249 static int of_platform_serial_remove(struct platform_device *ofdev) 250 { 251 struct of_serial_info *info = platform_get_drvdata(ofdev); 252 253 serial8250_unregister_port(info->line); 254 255 reset_control_assert(info->rst); 256 pm_runtime_put_sync(&ofdev->dev); 257 pm_runtime_disable(&ofdev->dev); 258 clk_disable_unprepare(info->clk); 259 kfree(info); 260 return 0; 261 } 262 263 #ifdef CONFIG_PM_SLEEP 264 static int of_serial_suspend(struct device *dev) 265 { 266 struct of_serial_info *info = dev_get_drvdata(dev); 267 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 268 struct uart_port *port = &port8250->port; 269 270 serial8250_suspend_port(info->line); 271 272 if (!uart_console(port) || console_suspend_enabled) { 273 pm_runtime_put_sync(dev); 274 clk_disable_unprepare(info->clk); 275 } 276 return 0; 277 } 278 279 static int of_serial_resume(struct device *dev) 280 { 281 struct of_serial_info *info = dev_get_drvdata(dev); 282 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 283 struct uart_port *port = &port8250->port; 284 285 if (!uart_console(port) || console_suspend_enabled) { 286 pm_runtime_get_sync(dev); 287 clk_prepare_enable(info->clk); 288 } 289 290 serial8250_resume_port(info->line); 291 292 return 0; 293 } 294 #endif 295 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); 296 297 /* 298 * A few common types, add more as needed. 299 */ 300 static const struct of_device_id of_platform_serial_table[] = { 301 { .compatible = "ns8250", .data = (void *)PORT_8250, }, 302 { .compatible = "ns16450", .data = (void *)PORT_16450, }, 303 { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, 304 { .compatible = "ns16550", .data = (void *)PORT_16550, }, 305 { .compatible = "ns16750", .data = (void *)PORT_16750, }, 306 { .compatible = "ns16850", .data = (void *)PORT_16850, }, 307 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, }, 308 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, }, 309 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, }, 310 { .compatible = "altr,16550-FIFO32", 311 .data = (void *)PORT_ALTR_16550_F32, }, 312 { .compatible = "altr,16550-FIFO64", 313 .data = (void *)PORT_ALTR_16550_F64, }, 314 { .compatible = "altr,16550-FIFO128", 315 .data = (void *)PORT_ALTR_16550_F128, }, 316 { .compatible = "mediatek,mtk-btif", 317 .data = (void *)PORT_MTK_BTIF, }, 318 { .compatible = "mrvl,mmp-uart", 319 .data = (void *)PORT_XSCALE, }, 320 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, 321 { /* end of list */ }, 322 }; 323 MODULE_DEVICE_TABLE(of, of_platform_serial_table); 324 325 static struct platform_driver of_platform_serial_driver = { 326 .driver = { 327 .name = "of_serial", 328 .of_match_table = of_platform_serial_table, 329 .pm = &of_serial_pm_ops, 330 }, 331 .probe = of_platform_serial_probe, 332 .remove = of_platform_serial_remove, 333 }; 334 335 module_platform_driver(of_platform_serial_driver); 336 337 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>"); 338 MODULE_LICENSE("GPL"); 339 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices"); 340