1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Serial Port driver for Open Firmware platform devices 4 * 5 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp. 6 */ 7 #include <linux/console.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/delay.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_reg.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/clk.h> 18 #include <linux/reset.h> 19 20 #include "8250.h" 21 22 struct of_serial_info { 23 struct clk *clk; 24 struct reset_control *rst; 25 int type; 26 int line; 27 }; 28 29 #ifdef CONFIG_ARCH_TEGRA 30 static void tegra_serial_handle_break(struct uart_port *p) 31 { 32 unsigned int status, tmout = 10000; 33 34 do { 35 status = p->serial_in(p, UART_LSR); 36 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 37 status = p->serial_in(p, UART_RX); 38 else 39 break; 40 if (--tmout == 0) 41 break; 42 udelay(1); 43 } while (1); 44 } 45 #else 46 static inline void tegra_serial_handle_break(struct uart_port *port) 47 { 48 } 49 #endif 50 51 /* 52 * Fill a struct uart_port for a given device node 53 */ 54 static int of_platform_serial_setup(struct platform_device *ofdev, 55 int type, struct uart_port *port, 56 struct of_serial_info *info) 57 { 58 struct resource resource; 59 struct device_node *np = ofdev->dev.of_node; 60 u32 clk, spd, prop; 61 int ret; 62 63 memset(port, 0, sizeof *port); 64 65 pm_runtime_enable(&ofdev->dev); 66 pm_runtime_get_sync(&ofdev->dev); 67 68 if (of_property_read_u32(np, "clock-frequency", &clk)) { 69 70 /* Get clk rate through clk driver if present */ 71 info->clk = devm_clk_get(&ofdev->dev, NULL); 72 if (IS_ERR(info->clk)) { 73 dev_warn(&ofdev->dev, 74 "clk or clock-frequency not defined\n"); 75 ret = PTR_ERR(info->clk); 76 goto err_pmruntime; 77 } 78 79 ret = clk_prepare_enable(info->clk); 80 if (ret < 0) 81 goto err_pmruntime; 82 83 clk = clk_get_rate(info->clk); 84 } 85 /* If current-speed was set, then try not to change it. */ 86 if (of_property_read_u32(np, "current-speed", &spd) == 0) 87 port->custom_divisor = clk / (16 * spd); 88 89 ret = of_address_to_resource(np, 0, &resource); 90 if (ret) { 91 dev_warn(&ofdev->dev, "invalid address\n"); 92 goto err_unprepare; 93 } 94 95 spin_lock_init(&port->lock); 96 port->mapbase = resource.start; 97 port->mapsize = resource_size(&resource); 98 99 /* Check for shifted address mapping */ 100 if (of_property_read_u32(np, "reg-offset", &prop) == 0) 101 port->mapbase += prop; 102 103 /* Check for registers offset within the devices address range */ 104 if (of_property_read_u32(np, "reg-shift", &prop) == 0) 105 port->regshift = prop; 106 107 /* Check for fifo size */ 108 if (of_property_read_u32(np, "fifo-size", &prop) == 0) 109 port->fifosize = prop; 110 111 /* Check for a fixed line number */ 112 ret = of_alias_get_id(np, "serial"); 113 if (ret >= 0) 114 port->line = ret; 115 116 port->irq = irq_of_parse_and_map(np, 0); 117 port->iotype = UPIO_MEM; 118 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 119 switch (prop) { 120 case 1: 121 port->iotype = UPIO_MEM; 122 break; 123 case 2: 124 port->iotype = UPIO_MEM16; 125 break; 126 case 4: 127 port->iotype = of_device_is_big_endian(np) ? 128 UPIO_MEM32BE : UPIO_MEM32; 129 break; 130 default: 131 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 132 prop); 133 ret = -EINVAL; 134 goto err_dispose; 135 } 136 } 137 138 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 139 if (IS_ERR(info->rst)) 140 goto err_dispose; 141 ret = reset_control_deassert(info->rst); 142 if (ret) 143 goto err_dispose; 144 145 port->type = type; 146 port->uartclk = clk; 147 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP 148 | UPF_FIXED_PORT | UPF_FIXED_TYPE; 149 150 if (of_property_read_bool(np, "no-loopback-test")) 151 port->flags |= UPF_SKIP_TEST; 152 153 port->dev = &ofdev->dev; 154 155 switch (type) { 156 case PORT_TEGRA: 157 port->handle_break = tegra_serial_handle_break; 158 break; 159 160 case PORT_RT2880: 161 port->iotype = UPIO_AU; 162 break; 163 } 164 165 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 166 (of_device_is_compatible(np, "fsl,ns16550") || 167 of_device_is_compatible(np, "fsl,16550-FIFO64"))) 168 port->handle_irq = fsl8250_handle_irq; 169 170 return 0; 171 err_dispose: 172 irq_dispose_mapping(port->irq); 173 err_unprepare: 174 clk_disable_unprepare(info->clk); 175 err_pmruntime: 176 pm_runtime_put_sync(&ofdev->dev); 177 pm_runtime_disable(&ofdev->dev); 178 return ret; 179 } 180 181 /* 182 * Try to register a serial port 183 */ 184 static const struct of_device_id of_platform_serial_table[]; 185 static int of_platform_serial_probe(struct platform_device *ofdev) 186 { 187 const struct of_device_id *match; 188 struct of_serial_info *info; 189 struct uart_8250_port port8250; 190 u32 tx_threshold; 191 int port_type; 192 int ret; 193 194 match = of_match_device(of_platform_serial_table, &ofdev->dev); 195 if (!match) 196 return -EINVAL; 197 198 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas")) 199 return -EBUSY; 200 201 info = kzalloc(sizeof(*info), GFP_KERNEL); 202 if (info == NULL) 203 return -ENOMEM; 204 205 port_type = (unsigned long)match->data; 206 memset(&port8250, 0, sizeof(port8250)); 207 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info); 208 if (ret) 209 goto err_free; 210 211 if (port8250.port.fifosize) 212 port8250.capabilities = UART_CAP_FIFO; 213 214 /* Check for TX FIFO threshold & set tx_loadsz */ 215 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold", 216 &tx_threshold) == 0) && 217 (tx_threshold < port8250.port.fifosize)) 218 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold; 219 220 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control")) 221 port8250.capabilities |= UART_CAP_AFE; 222 223 ret = serial8250_register_8250_port(&port8250); 224 if (ret < 0) 225 goto err_dispose; 226 227 info->type = port_type; 228 info->line = ret; 229 platform_set_drvdata(ofdev, info); 230 return 0; 231 err_dispose: 232 irq_dispose_mapping(port8250.port.irq); 233 pm_runtime_put_sync(&ofdev->dev); 234 pm_runtime_disable(&ofdev->dev); 235 clk_disable_unprepare(info->clk); 236 err_free: 237 kfree(info); 238 return ret; 239 } 240 241 /* 242 * Release a line 243 */ 244 static int of_platform_serial_remove(struct platform_device *ofdev) 245 { 246 struct of_serial_info *info = platform_get_drvdata(ofdev); 247 248 serial8250_unregister_port(info->line); 249 250 reset_control_assert(info->rst); 251 pm_runtime_put_sync(&ofdev->dev); 252 pm_runtime_disable(&ofdev->dev); 253 clk_disable_unprepare(info->clk); 254 kfree(info); 255 return 0; 256 } 257 258 #ifdef CONFIG_PM_SLEEP 259 static int of_serial_suspend(struct device *dev) 260 { 261 struct of_serial_info *info = dev_get_drvdata(dev); 262 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 263 struct uart_port *port = &port8250->port; 264 265 serial8250_suspend_port(info->line); 266 267 if (!uart_console(port) || console_suspend_enabled) { 268 pm_runtime_put_sync(dev); 269 clk_disable_unprepare(info->clk); 270 } 271 return 0; 272 } 273 274 static int of_serial_resume(struct device *dev) 275 { 276 struct of_serial_info *info = dev_get_drvdata(dev); 277 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 278 struct uart_port *port = &port8250->port; 279 280 if (!uart_console(port) || console_suspend_enabled) { 281 pm_runtime_get_sync(dev); 282 clk_prepare_enable(info->clk); 283 } 284 285 serial8250_resume_port(info->line); 286 287 return 0; 288 } 289 #endif 290 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); 291 292 /* 293 * A few common types, add more as needed. 294 */ 295 static const struct of_device_id of_platform_serial_table[] = { 296 { .compatible = "ns8250", .data = (void *)PORT_8250, }, 297 { .compatible = "ns16450", .data = (void *)PORT_16450, }, 298 { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, 299 { .compatible = "ns16550", .data = (void *)PORT_16550, }, 300 { .compatible = "ns16750", .data = (void *)PORT_16750, }, 301 { .compatible = "ns16850", .data = (void *)PORT_16850, }, 302 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, }, 303 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, }, 304 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, }, 305 { .compatible = "altr,16550-FIFO32", 306 .data = (void *)PORT_ALTR_16550_F32, }, 307 { .compatible = "altr,16550-FIFO64", 308 .data = (void *)PORT_ALTR_16550_F64, }, 309 { .compatible = "altr,16550-FIFO128", 310 .data = (void *)PORT_ALTR_16550_F128, }, 311 { .compatible = "mediatek,mtk-btif", 312 .data = (void *)PORT_MTK_BTIF, }, 313 { .compatible = "mrvl,mmp-uart", 314 .data = (void *)PORT_XSCALE, }, 315 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, 316 { /* end of list */ }, 317 }; 318 MODULE_DEVICE_TABLE(of, of_platform_serial_table); 319 320 static struct platform_driver of_platform_serial_driver = { 321 .driver = { 322 .name = "of_serial", 323 .of_match_table = of_platform_serial_table, 324 .pm = &of_serial_pm_ops, 325 }, 326 .probe = of_platform_serial_probe, 327 .remove = of_platform_serial_remove, 328 }; 329 330 module_platform_driver(of_platform_serial_driver); 331 332 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>"); 333 MODULE_LICENSE("GPL"); 334 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices"); 335