1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Serial Port driver for Open Firmware platform devices 4 * 5 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp. 6 */ 7 #include <linux/console.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/delay.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_reg.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/clk.h> 18 #include <linux/reset.h> 19 20 #include "8250.h" 21 22 struct of_serial_info { 23 struct clk *clk; 24 struct reset_control *rst; 25 int type; 26 int line; 27 }; 28 29 #ifdef CONFIG_ARCH_TEGRA 30 static void tegra_serial_handle_break(struct uart_port *p) 31 { 32 unsigned int status, tmout = 10000; 33 34 do { 35 status = p->serial_in(p, UART_LSR); 36 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 37 status = p->serial_in(p, UART_RX); 38 else 39 break; 40 if (--tmout == 0) 41 break; 42 udelay(1); 43 } while (1); 44 } 45 #else 46 static inline void tegra_serial_handle_break(struct uart_port *port) 47 { 48 } 49 #endif 50 51 /* 52 * Fill a struct uart_port for a given device node 53 */ 54 static int of_platform_serial_setup(struct platform_device *ofdev, 55 int type, struct uart_port *port, 56 struct of_serial_info *info) 57 { 58 struct resource resource; 59 struct device_node *np = ofdev->dev.of_node; 60 u32 clk, spd, prop; 61 int ret; 62 63 memset(port, 0, sizeof *port); 64 65 pm_runtime_enable(&ofdev->dev); 66 pm_runtime_get_sync(&ofdev->dev); 67 68 if (of_property_read_u32(np, "clock-frequency", &clk)) { 69 70 /* Get clk rate through clk driver if present */ 71 info->clk = devm_clk_get(&ofdev->dev, NULL); 72 if (IS_ERR(info->clk)) { 73 dev_warn(&ofdev->dev, 74 "clk or clock-frequency not defined\n"); 75 ret = PTR_ERR(info->clk); 76 goto err_pmruntime; 77 } 78 79 ret = clk_prepare_enable(info->clk); 80 if (ret < 0) 81 goto err_pmruntime; 82 83 clk = clk_get_rate(info->clk); 84 } 85 /* If current-speed was set, then try not to change it. */ 86 if (of_property_read_u32(np, "current-speed", &spd) == 0) 87 port->custom_divisor = clk / (16 * spd); 88 89 ret = of_address_to_resource(np, 0, &resource); 90 if (ret) { 91 dev_warn(&ofdev->dev, "invalid address\n"); 92 goto err_unprepare; 93 } 94 95 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | 96 UPF_FIXED_TYPE; 97 spin_lock_init(&port->lock); 98 99 if (resource_type(&resource) == IORESOURCE_IO) { 100 port->iotype = UPIO_PORT; 101 port->iobase = resource.start; 102 } else { 103 port->mapbase = resource.start; 104 port->mapsize = resource_size(&resource); 105 106 /* Check for shifted address mapping */ 107 if (of_property_read_u32(np, "reg-offset", &prop) == 0) 108 port->mapbase += prop; 109 110 port->iotype = UPIO_MEM; 111 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 112 switch (prop) { 113 case 1: 114 port->iotype = UPIO_MEM; 115 break; 116 case 2: 117 port->iotype = UPIO_MEM16; 118 break; 119 case 4: 120 port->iotype = of_device_is_big_endian(np) ? 121 UPIO_MEM32BE : UPIO_MEM32; 122 break; 123 default: 124 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 125 prop); 126 ret = -EINVAL; 127 goto err_dispose; 128 } 129 } 130 port->flags |= UPF_IOREMAP; 131 } 132 133 /* Check for registers offset within the devices address range */ 134 if (of_property_read_u32(np, "reg-shift", &prop) == 0) 135 port->regshift = prop; 136 137 /* Check for fifo size */ 138 if (of_property_read_u32(np, "fifo-size", &prop) == 0) 139 port->fifosize = prop; 140 141 /* Check for a fixed line number */ 142 ret = of_alias_get_id(np, "serial"); 143 if (ret >= 0) 144 port->line = ret; 145 146 port->irq = irq_of_parse_and_map(np, 0); 147 148 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 149 if (IS_ERR(info->rst)) { 150 ret = PTR_ERR(info->rst); 151 goto err_dispose; 152 } 153 154 ret = reset_control_deassert(info->rst); 155 if (ret) 156 goto err_dispose; 157 158 port->type = type; 159 port->uartclk = clk; 160 port->irqflags |= IRQF_SHARED; 161 162 if (of_property_read_bool(np, "no-loopback-test")) 163 port->flags |= UPF_SKIP_TEST; 164 165 port->dev = &ofdev->dev; 166 167 switch (type) { 168 case PORT_TEGRA: 169 port->handle_break = tegra_serial_handle_break; 170 break; 171 172 case PORT_RT2880: 173 port->iotype = UPIO_AU; 174 break; 175 } 176 177 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 178 (of_device_is_compatible(np, "fsl,ns16550") || 179 of_device_is_compatible(np, "fsl,16550-FIFO64"))) 180 port->handle_irq = fsl8250_handle_irq; 181 182 return 0; 183 err_dispose: 184 irq_dispose_mapping(port->irq); 185 err_unprepare: 186 clk_disable_unprepare(info->clk); 187 err_pmruntime: 188 pm_runtime_put_sync(&ofdev->dev); 189 pm_runtime_disable(&ofdev->dev); 190 return ret; 191 } 192 193 /* 194 * Try to register a serial port 195 */ 196 static const struct of_device_id of_platform_serial_table[]; 197 static int of_platform_serial_probe(struct platform_device *ofdev) 198 { 199 const struct of_device_id *match; 200 struct of_serial_info *info; 201 struct uart_8250_port port8250; 202 u32 tx_threshold; 203 int port_type; 204 int ret; 205 206 match = of_match_device(of_platform_serial_table, &ofdev->dev); 207 if (!match) 208 return -EINVAL; 209 210 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas")) 211 return -EBUSY; 212 213 info = kzalloc(sizeof(*info), GFP_KERNEL); 214 if (info == NULL) 215 return -ENOMEM; 216 217 port_type = (unsigned long)match->data; 218 memset(&port8250, 0, sizeof(port8250)); 219 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info); 220 if (ret) 221 goto err_free; 222 223 if (port8250.port.fifosize) 224 port8250.capabilities = UART_CAP_FIFO; 225 226 /* Check for TX FIFO threshold & set tx_loadsz */ 227 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold", 228 &tx_threshold) == 0) && 229 (tx_threshold < port8250.port.fifosize)) 230 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold; 231 232 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control")) 233 port8250.capabilities |= UART_CAP_AFE; 234 235 ret = serial8250_register_8250_port(&port8250); 236 if (ret < 0) 237 goto err_dispose; 238 239 info->type = port_type; 240 info->line = ret; 241 platform_set_drvdata(ofdev, info); 242 return 0; 243 err_dispose: 244 irq_dispose_mapping(port8250.port.irq); 245 pm_runtime_put_sync(&ofdev->dev); 246 pm_runtime_disable(&ofdev->dev); 247 clk_disable_unprepare(info->clk); 248 err_free: 249 kfree(info); 250 return ret; 251 } 252 253 /* 254 * Release a line 255 */ 256 static int of_platform_serial_remove(struct platform_device *ofdev) 257 { 258 struct of_serial_info *info = platform_get_drvdata(ofdev); 259 260 serial8250_unregister_port(info->line); 261 262 reset_control_assert(info->rst); 263 pm_runtime_put_sync(&ofdev->dev); 264 pm_runtime_disable(&ofdev->dev); 265 clk_disable_unprepare(info->clk); 266 kfree(info); 267 return 0; 268 } 269 270 #ifdef CONFIG_PM_SLEEP 271 static int of_serial_suspend(struct device *dev) 272 { 273 struct of_serial_info *info = dev_get_drvdata(dev); 274 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 275 struct uart_port *port = &port8250->port; 276 277 serial8250_suspend_port(info->line); 278 279 if (!uart_console(port) || console_suspend_enabled) { 280 pm_runtime_put_sync(dev); 281 clk_disable_unprepare(info->clk); 282 } 283 return 0; 284 } 285 286 static int of_serial_resume(struct device *dev) 287 { 288 struct of_serial_info *info = dev_get_drvdata(dev); 289 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 290 struct uart_port *port = &port8250->port; 291 292 if (!uart_console(port) || console_suspend_enabled) { 293 pm_runtime_get_sync(dev); 294 clk_prepare_enable(info->clk); 295 } 296 297 serial8250_resume_port(info->line); 298 299 return 0; 300 } 301 #endif 302 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); 303 304 /* 305 * A few common types, add more as needed. 306 */ 307 static const struct of_device_id of_platform_serial_table[] = { 308 { .compatible = "ns8250", .data = (void *)PORT_8250, }, 309 { .compatible = "ns16450", .data = (void *)PORT_16450, }, 310 { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, 311 { .compatible = "ns16550", .data = (void *)PORT_16550, }, 312 { .compatible = "ns16750", .data = (void *)PORT_16750, }, 313 { .compatible = "ns16850", .data = (void *)PORT_16850, }, 314 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, }, 315 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, }, 316 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, }, 317 { .compatible = "altr,16550-FIFO32", 318 .data = (void *)PORT_ALTR_16550_F32, }, 319 { .compatible = "altr,16550-FIFO64", 320 .data = (void *)PORT_ALTR_16550_F64, }, 321 { .compatible = "altr,16550-FIFO128", 322 .data = (void *)PORT_ALTR_16550_F128, }, 323 { .compatible = "mediatek,mtk-btif", 324 .data = (void *)PORT_MTK_BTIF, }, 325 { .compatible = "mrvl,mmp-uart", 326 .data = (void *)PORT_XSCALE, }, 327 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, 328 { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, }, 329 { /* end of list */ }, 330 }; 331 MODULE_DEVICE_TABLE(of, of_platform_serial_table); 332 333 static struct platform_driver of_platform_serial_driver = { 334 .driver = { 335 .name = "of_serial", 336 .of_match_table = of_platform_serial_table, 337 .pm = &of_serial_pm_ops, 338 }, 339 .probe = of_platform_serial_probe, 340 .remove = of_platform_serial_remove, 341 }; 342 343 module_platform_driver(of_platform_serial_driver); 344 345 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>"); 346 MODULE_LICENSE("GPL"); 347 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices"); 348