1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Serial Port driver for Open Firmware platform devices 4 * 5 * Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp. 6 */ 7 #include <linux/console.h> 8 #include <linux/module.h> 9 #include <linux/slab.h> 10 #include <linux/delay.h> 11 #include <linux/serial_core.h> 12 #include <linux/serial_reg.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/of_platform.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/clk.h> 18 #include <linux/reset.h> 19 20 #include "8250.h" 21 22 struct of_serial_info { 23 struct clk *clk; 24 struct reset_control *rst; 25 int type; 26 int line; 27 }; 28 29 #ifdef CONFIG_ARCH_TEGRA 30 static void tegra_serial_handle_break(struct uart_port *p) 31 { 32 unsigned int status, tmout = 10000; 33 34 do { 35 status = p->serial_in(p, UART_LSR); 36 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) 37 status = p->serial_in(p, UART_RX); 38 else 39 break; 40 if (--tmout == 0) 41 break; 42 udelay(1); 43 } while (1); 44 } 45 #else 46 static inline void tegra_serial_handle_break(struct uart_port *port) 47 { 48 } 49 #endif 50 51 /* 52 * Fill a struct uart_port for a given device node 53 */ 54 static int of_platform_serial_setup(struct platform_device *ofdev, 55 int type, struct uart_port *port, 56 struct of_serial_info *info) 57 { 58 struct resource resource; 59 struct device_node *np = ofdev->dev.of_node; 60 u32 clk, spd, prop; 61 int ret, irq; 62 63 memset(port, 0, sizeof *port); 64 65 pm_runtime_enable(&ofdev->dev); 66 pm_runtime_get_sync(&ofdev->dev); 67 68 if (of_property_read_u32(np, "clock-frequency", &clk)) { 69 70 /* Get clk rate through clk driver if present */ 71 info->clk = devm_clk_get(&ofdev->dev, NULL); 72 if (IS_ERR(info->clk)) { 73 dev_warn(&ofdev->dev, 74 "clk or clock-frequency not defined\n"); 75 ret = PTR_ERR(info->clk); 76 goto err_pmruntime; 77 } 78 79 ret = clk_prepare_enable(info->clk); 80 if (ret < 0) 81 goto err_pmruntime; 82 83 clk = clk_get_rate(info->clk); 84 } 85 /* If current-speed was set, then try not to change it. */ 86 if (of_property_read_u32(np, "current-speed", &spd) == 0) 87 port->custom_divisor = clk / (16 * spd); 88 89 ret = of_address_to_resource(np, 0, &resource); 90 if (ret) { 91 dev_warn(&ofdev->dev, "invalid address\n"); 92 goto err_unprepare; 93 } 94 95 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | 96 UPF_FIXED_TYPE; 97 spin_lock_init(&port->lock); 98 99 if (resource_type(&resource) == IORESOURCE_IO) { 100 port->iotype = UPIO_PORT; 101 port->iobase = resource.start; 102 } else { 103 port->mapbase = resource.start; 104 port->mapsize = resource_size(&resource); 105 106 /* Check for shifted address mapping */ 107 if (of_property_read_u32(np, "reg-offset", &prop) == 0) 108 port->mapbase += prop; 109 110 port->iotype = UPIO_MEM; 111 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) { 112 switch (prop) { 113 case 1: 114 port->iotype = UPIO_MEM; 115 break; 116 case 2: 117 port->iotype = UPIO_MEM16; 118 break; 119 case 4: 120 port->iotype = of_device_is_big_endian(np) ? 121 UPIO_MEM32BE : UPIO_MEM32; 122 break; 123 default: 124 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 125 prop); 126 ret = -EINVAL; 127 goto err_unprepare; 128 } 129 } 130 port->flags |= UPF_IOREMAP; 131 } 132 133 /* Compatibility with the deprecated pxa driver and 8250_pxa drivers. */ 134 if (of_device_is_compatible(np, "mrvl,mmp-uart")) 135 port->regshift = 2; 136 137 /* Check for registers offset within the devices address range */ 138 if (of_property_read_u32(np, "reg-shift", &prop) == 0) 139 port->regshift = prop; 140 141 /* Check for fifo size */ 142 if (of_property_read_u32(np, "fifo-size", &prop) == 0) 143 port->fifosize = prop; 144 145 /* Check for a fixed line number */ 146 ret = of_alias_get_id(np, "serial"); 147 if (ret >= 0) 148 port->line = ret; 149 150 irq = of_irq_get(np, 0); 151 if (irq < 0) { 152 if (irq == -EPROBE_DEFER) { 153 ret = -EPROBE_DEFER; 154 goto err_unprepare; 155 } 156 /* IRQ support not mandatory */ 157 irq = 0; 158 } 159 160 port->irq = irq; 161 162 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 163 if (IS_ERR(info->rst)) { 164 ret = PTR_ERR(info->rst); 165 goto err_unprepare; 166 } 167 168 ret = reset_control_deassert(info->rst); 169 if (ret) 170 goto err_unprepare; 171 172 port->type = type; 173 port->uartclk = clk; 174 port->irqflags |= IRQF_SHARED; 175 176 if (of_property_read_bool(np, "no-loopback-test")) 177 port->flags |= UPF_SKIP_TEST; 178 179 port->dev = &ofdev->dev; 180 181 switch (type) { 182 case PORT_TEGRA: 183 port->handle_break = tegra_serial_handle_break; 184 break; 185 186 case PORT_RT2880: 187 port->iotype = UPIO_AU; 188 break; 189 } 190 191 if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) && 192 (of_device_is_compatible(np, "fsl,ns16550") || 193 of_device_is_compatible(np, "fsl,16550-FIFO64"))) 194 port->handle_irq = fsl8250_handle_irq; 195 196 return 0; 197 err_unprepare: 198 clk_disable_unprepare(info->clk); 199 err_pmruntime: 200 pm_runtime_put_sync(&ofdev->dev); 201 pm_runtime_disable(&ofdev->dev); 202 return ret; 203 } 204 205 /* 206 * Try to register a serial port 207 */ 208 static const struct of_device_id of_platform_serial_table[]; 209 static int of_platform_serial_probe(struct platform_device *ofdev) 210 { 211 const struct of_device_id *match; 212 struct of_serial_info *info; 213 struct uart_8250_port port8250; 214 u32 tx_threshold; 215 int port_type; 216 int ret; 217 218 match = of_match_device(of_platform_serial_table, &ofdev->dev); 219 if (!match) 220 return -EINVAL; 221 222 if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas")) 223 return -EBUSY; 224 225 info = kzalloc(sizeof(*info), GFP_KERNEL); 226 if (info == NULL) 227 return -ENOMEM; 228 229 port_type = (unsigned long)match->data; 230 memset(&port8250, 0, sizeof(port8250)); 231 ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info); 232 if (ret) 233 goto err_free; 234 235 if (port8250.port.fifosize) 236 port8250.capabilities = UART_CAP_FIFO; 237 238 /* Check for TX FIFO threshold & set tx_loadsz */ 239 if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold", 240 &tx_threshold) == 0) && 241 (tx_threshold < port8250.port.fifosize)) 242 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold; 243 244 if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control")) 245 port8250.capabilities |= UART_CAP_AFE; 246 247 if (of_property_read_u32(ofdev->dev.of_node, 248 "overrun-throttle-ms", 249 &port8250.overrun_backoff_time_ms) != 0) 250 port8250.overrun_backoff_time_ms = 0; 251 252 ret = serial8250_register_8250_port(&port8250); 253 if (ret < 0) 254 goto err_dispose; 255 256 info->type = port_type; 257 info->line = ret; 258 platform_set_drvdata(ofdev, info); 259 return 0; 260 err_dispose: 261 irq_dispose_mapping(port8250.port.irq); 262 pm_runtime_put_sync(&ofdev->dev); 263 pm_runtime_disable(&ofdev->dev); 264 clk_disable_unprepare(info->clk); 265 err_free: 266 kfree(info); 267 return ret; 268 } 269 270 /* 271 * Release a line 272 */ 273 static int of_platform_serial_remove(struct platform_device *ofdev) 274 { 275 struct of_serial_info *info = platform_get_drvdata(ofdev); 276 277 serial8250_unregister_port(info->line); 278 279 reset_control_assert(info->rst); 280 pm_runtime_put_sync(&ofdev->dev); 281 pm_runtime_disable(&ofdev->dev); 282 clk_disable_unprepare(info->clk); 283 kfree(info); 284 return 0; 285 } 286 287 #ifdef CONFIG_PM_SLEEP 288 static int of_serial_suspend(struct device *dev) 289 { 290 struct of_serial_info *info = dev_get_drvdata(dev); 291 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 292 struct uart_port *port = &port8250->port; 293 294 serial8250_suspend_port(info->line); 295 296 if (!uart_console(port) || console_suspend_enabled) { 297 pm_runtime_put_sync(dev); 298 clk_disable_unprepare(info->clk); 299 } 300 return 0; 301 } 302 303 static int of_serial_resume(struct device *dev) 304 { 305 struct of_serial_info *info = dev_get_drvdata(dev); 306 struct uart_8250_port *port8250 = serial8250_get_port(info->line); 307 struct uart_port *port = &port8250->port; 308 309 if (!uart_console(port) || console_suspend_enabled) { 310 pm_runtime_get_sync(dev); 311 clk_prepare_enable(info->clk); 312 } 313 314 serial8250_resume_port(info->line); 315 316 return 0; 317 } 318 #endif 319 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume); 320 321 /* 322 * A few common types, add more as needed. 323 */ 324 static const struct of_device_id of_platform_serial_table[] = { 325 { .compatible = "ns8250", .data = (void *)PORT_8250, }, 326 { .compatible = "ns16450", .data = (void *)PORT_16450, }, 327 { .compatible = "ns16550a", .data = (void *)PORT_16550A, }, 328 { .compatible = "ns16550", .data = (void *)PORT_16550, }, 329 { .compatible = "ns16750", .data = (void *)PORT_16750, }, 330 { .compatible = "ns16850", .data = (void *)PORT_16850, }, 331 { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, }, 332 { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, }, 333 { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, }, 334 { .compatible = "intel,xscale-uart", .data = (void *)PORT_XSCALE, }, 335 { .compatible = "altr,16550-FIFO32", 336 .data = (void *)PORT_ALTR_16550_F32, }, 337 { .compatible = "altr,16550-FIFO64", 338 .data = (void *)PORT_ALTR_16550_F64, }, 339 { .compatible = "altr,16550-FIFO128", 340 .data = (void *)PORT_ALTR_16550_F128, }, 341 { .compatible = "mediatek,mtk-btif", 342 .data = (void *)PORT_MTK_BTIF, }, 343 { .compatible = "mrvl,mmp-uart", 344 .data = (void *)PORT_XSCALE, }, 345 { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, }, 346 { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, }, 347 { /* end of list */ }, 348 }; 349 MODULE_DEVICE_TABLE(of, of_platform_serial_table); 350 351 static struct platform_driver of_platform_serial_driver = { 352 .driver = { 353 .name = "of_serial", 354 .of_match_table = of_platform_serial_table, 355 .pm = &of_serial_pm_ops, 356 }, 357 .probe = of_platform_serial_probe, 358 .remove = of_platform_serial_remove, 359 }; 360 361 module_platform_driver(of_platform_serial_driver); 362 363 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>"); 364 MODULE_LICENSE("GPL"); 365 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices"); 366