1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Mediatek 8250 driver. 4 * 5 * Copyright (c) 2014 MundoReader S.L. 6 * Author: Matthias Brugger <matthias.bgg@gmail.com> 7 */ 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of_irq.h> 12 #include <linux/of_platform.h> 13 #include <linux/pinctrl/consumer.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/console.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/tty.h> 21 #include <linux/tty_flip.h> 22 23 #include "8250.h" 24 25 #define MTK_UART_HIGHS 0x09 /* Highspeed register */ 26 #define MTK_UART_SAMPLE_COUNT 0x0a /* Sample count register */ 27 #define MTK_UART_SAMPLE_POINT 0x0b /* Sample point register */ 28 #define MTK_UART_RATE_FIX 0x0d /* UART Rate Fix Register */ 29 #define MTK_UART_ESCAPE_DAT 0x10 /* Escape Character register */ 30 #define MTK_UART_ESCAPE_EN 0x11 /* Escape Enable register */ 31 #define MTK_UART_DMA_EN 0x13 /* DMA Enable register */ 32 #define MTK_UART_RXTRI_AD 0x14 /* RX Trigger address */ 33 #define MTK_UART_FRACDIV_L 0x15 /* Fractional divider LSB address */ 34 #define MTK_UART_FRACDIV_M 0x16 /* Fractional divider MSB address */ 35 #define MTK_UART_DEBUG0 0x18 36 #define MTK_UART_IER_XOFFI 0x20 /* Enable XOFF character interrupt */ 37 #define MTK_UART_IER_RTSI 0x40 /* Enable RTS Modem status interrupt */ 38 #define MTK_UART_IER_CTSI 0x80 /* Enable CTS Modem status interrupt */ 39 40 #define MTK_UART_EFR_EN 0x10 /* Enable enhancement feature */ 41 #define MTK_UART_EFR_RTS 0x40 /* Enable hardware rx flow control */ 42 #define MTK_UART_EFR_CTS 0x80 /* Enable hardware tx flow control */ 43 #define MTK_UART_EFR_NO_SW_FC 0x0 /* no sw flow control */ 44 #define MTK_UART_EFR_XON1_XOFF1 0xa /* XON1/XOFF1 as sw flow control */ 45 #define MTK_UART_EFR_XON2_XOFF2 0x5 /* XON2/XOFF2 as sw flow control */ 46 #define MTK_UART_EFR_SW_FC_MASK 0xf /* Enable CTS Modem status interrupt */ 47 #define MTK_UART_EFR_HW_FC (MTK_UART_EFR_RTS | MTK_UART_EFR_CTS) 48 #define MTK_UART_DMA_EN_TX 0x2 49 #define MTK_UART_DMA_EN_RX 0x5 50 51 #define MTK_UART_ESCAPE_CHAR 0x77 /* Escape char added under sw fc */ 52 #define MTK_UART_RX_SIZE 0x8000 53 #define MTK_UART_TX_TRIGGER 1 54 #define MTK_UART_RX_TRIGGER MTK_UART_RX_SIZE 55 56 #ifdef CONFIG_SERIAL_8250_DMA 57 enum dma_rx_status { 58 DMA_RX_START = 0, 59 DMA_RX_RUNNING = 1, 60 DMA_RX_SHUTDOWN = 2, 61 }; 62 #endif 63 64 struct mtk8250_data { 65 int line; 66 unsigned int rx_pos; 67 unsigned int clk_count; 68 struct clk *uart_clk; 69 struct clk *bus_clk; 70 struct uart_8250_dma *dma; 71 #ifdef CONFIG_SERIAL_8250_DMA 72 enum dma_rx_status rx_status; 73 #endif 74 int rx_wakeup_irq; 75 }; 76 77 /* flow control mode */ 78 enum { 79 MTK_UART_FC_NONE, 80 MTK_UART_FC_SW, 81 MTK_UART_FC_HW, 82 }; 83 84 #ifdef CONFIG_SERIAL_8250_DMA 85 static void mtk8250_rx_dma(struct uart_8250_port *up); 86 87 static void mtk8250_dma_rx_complete(void *param) 88 { 89 struct uart_8250_port *up = param; 90 struct uart_8250_dma *dma = up->dma; 91 struct mtk8250_data *data = up->port.private_data; 92 struct tty_port *tty_port = &up->port.state->port; 93 struct dma_tx_state state; 94 int copied, total, cnt; 95 unsigned char *ptr; 96 97 if (data->rx_status == DMA_RX_SHUTDOWN) 98 return; 99 100 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 101 total = dma->rx_size - state.residue; 102 cnt = total; 103 104 if ((data->rx_pos + cnt) > dma->rx_size) 105 cnt = dma->rx_size - data->rx_pos; 106 107 ptr = (unsigned char *)(data->rx_pos + dma->rx_buf); 108 copied = tty_insert_flip_string(tty_port, ptr, cnt); 109 data->rx_pos += cnt; 110 111 if (total > cnt) { 112 ptr = (unsigned char *)(dma->rx_buf); 113 cnt = total - cnt; 114 copied += tty_insert_flip_string(tty_port, ptr, cnt); 115 data->rx_pos = cnt; 116 } 117 118 up->port.icount.rx += copied; 119 120 tty_flip_buffer_push(tty_port); 121 122 mtk8250_rx_dma(up); 123 } 124 125 static void mtk8250_rx_dma(struct uart_8250_port *up) 126 { 127 struct uart_8250_dma *dma = up->dma; 128 struct dma_async_tx_descriptor *desc; 129 130 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, 131 dma->rx_size, DMA_DEV_TO_MEM, 132 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 133 if (!desc) { 134 pr_err("failed to prepare rx slave single\n"); 135 return; 136 } 137 138 desc->callback = mtk8250_dma_rx_complete; 139 desc->callback_param = up; 140 141 dma->rx_cookie = dmaengine_submit(desc); 142 143 dma_async_issue_pending(dma->rxchan); 144 } 145 146 static void mtk8250_dma_enable(struct uart_8250_port *up) 147 { 148 struct uart_8250_dma *dma = up->dma; 149 struct mtk8250_data *data = up->port.private_data; 150 int lcr = serial_in(up, UART_LCR); 151 152 if (data->rx_status != DMA_RX_START) 153 return; 154 155 dma->rxconf.src_port_window_size = dma->rx_size; 156 dma->rxconf.src_addr = dma->rx_addr; 157 158 dma->txconf.dst_port_window_size = UART_XMIT_SIZE; 159 dma->txconf.dst_addr = dma->tx_addr; 160 161 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 162 UART_FCR_CLEAR_XMIT); 163 serial_out(up, MTK_UART_DMA_EN, 164 MTK_UART_DMA_EN_RX | MTK_UART_DMA_EN_TX); 165 166 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 167 serial_out(up, UART_EFR, UART_EFR_ECB); 168 serial_out(up, UART_LCR, lcr); 169 170 if (dmaengine_slave_config(dma->rxchan, &dma->rxconf) != 0) 171 pr_err("failed to configure rx dma channel\n"); 172 if (dmaengine_slave_config(dma->txchan, &dma->txconf) != 0) 173 pr_err("failed to configure tx dma channel\n"); 174 175 data->rx_status = DMA_RX_RUNNING; 176 data->rx_pos = 0; 177 mtk8250_rx_dma(up); 178 } 179 #endif 180 181 static int mtk8250_startup(struct uart_port *port) 182 { 183 #ifdef CONFIG_SERIAL_8250_DMA 184 struct uart_8250_port *up = up_to_u8250p(port); 185 struct mtk8250_data *data = port->private_data; 186 187 /* disable DMA for console */ 188 if (uart_console(port)) 189 up->dma = NULL; 190 191 if (up->dma) { 192 data->rx_status = DMA_RX_START; 193 uart_circ_clear(&port->state->xmit); 194 } 195 #endif 196 memset(&port->icount, 0, sizeof(port->icount)); 197 198 return serial8250_do_startup(port); 199 } 200 201 static void mtk8250_shutdown(struct uart_port *port) 202 { 203 #ifdef CONFIG_SERIAL_8250_DMA 204 struct uart_8250_port *up = up_to_u8250p(port); 205 struct mtk8250_data *data = port->private_data; 206 207 if (up->dma) 208 data->rx_status = DMA_RX_SHUTDOWN; 209 #endif 210 211 return serial8250_do_shutdown(port); 212 } 213 214 static void mtk8250_disable_intrs(struct uart_8250_port *up, int mask) 215 { 216 serial_out(up, UART_IER, serial_in(up, UART_IER) & (~mask)); 217 } 218 219 static void mtk8250_enable_intrs(struct uart_8250_port *up, int mask) 220 { 221 serial_out(up, UART_IER, serial_in(up, UART_IER) | mask); 222 } 223 224 static void mtk8250_set_flow_ctrl(struct uart_8250_port *up, int mode) 225 { 226 struct uart_port *port = &up->port; 227 int lcr = serial_in(up, UART_LCR); 228 229 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 230 serial_out(up, UART_EFR, UART_EFR_ECB); 231 serial_out(up, UART_LCR, lcr); 232 lcr = serial_in(up, UART_LCR); 233 234 switch (mode) { 235 case MTK_UART_FC_NONE: 236 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 237 serial_out(up, MTK_UART_ESCAPE_EN, 0x00); 238 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 239 serial_out(up, UART_EFR, serial_in(up, UART_EFR) & 240 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK))); 241 serial_out(up, UART_LCR, lcr); 242 mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI | 243 MTK_UART_IER_RTSI | MTK_UART_IER_CTSI); 244 break; 245 246 case MTK_UART_FC_HW: 247 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 248 serial_out(up, MTK_UART_ESCAPE_EN, 0x00); 249 serial_out(up, UART_MCR, UART_MCR_RTS); 250 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 251 252 /*enable hw flow control*/ 253 serial_out(up, UART_EFR, MTK_UART_EFR_HW_FC | 254 (serial_in(up, UART_EFR) & 255 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); 256 257 serial_out(up, UART_LCR, lcr); 258 mtk8250_disable_intrs(up, MTK_UART_IER_XOFFI); 259 mtk8250_enable_intrs(up, MTK_UART_IER_CTSI | MTK_UART_IER_RTSI); 260 break; 261 262 case MTK_UART_FC_SW: /*MTK software flow control */ 263 serial_out(up, MTK_UART_ESCAPE_DAT, MTK_UART_ESCAPE_CHAR); 264 serial_out(up, MTK_UART_ESCAPE_EN, 0x01); 265 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 266 267 /*enable sw flow control */ 268 serial_out(up, UART_EFR, MTK_UART_EFR_XON1_XOFF1 | 269 (serial_in(up, UART_EFR) & 270 (~(MTK_UART_EFR_HW_FC | MTK_UART_EFR_SW_FC_MASK)))); 271 272 serial_out(up, UART_XON1, START_CHAR(port->state->port.tty)); 273 serial_out(up, UART_XOFF1, STOP_CHAR(port->state->port.tty)); 274 serial_out(up, UART_LCR, lcr); 275 mtk8250_disable_intrs(up, MTK_UART_IER_CTSI|MTK_UART_IER_RTSI); 276 mtk8250_enable_intrs(up, MTK_UART_IER_XOFFI); 277 break; 278 default: 279 break; 280 } 281 } 282 283 static void 284 mtk8250_set_termios(struct uart_port *port, struct ktermios *termios, 285 struct ktermios *old) 286 { 287 unsigned short fraction_L_mapping[] = { 288 0, 1, 0x5, 0x15, 0x55, 0x57, 0x57, 0x77, 0x7F, 0xFF, 0xFF 289 }; 290 unsigned short fraction_M_mapping[] = { 291 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 3 292 }; 293 struct uart_8250_port *up = up_to_u8250p(port); 294 unsigned int baud, quot, fraction; 295 unsigned long flags; 296 int mode; 297 298 #ifdef CONFIG_SERIAL_8250_DMA 299 if (up->dma) { 300 if (uart_console(port)) { 301 devm_kfree(up->port.dev, up->dma); 302 up->dma = NULL; 303 } else { 304 mtk8250_dma_enable(up); 305 } 306 } 307 #endif 308 309 /* 310 * Store the requested baud rate before calling the generic 8250 311 * set_termios method. Standard 8250 port expects bauds to be 312 * no higher than (uartclk / 16) so the baud will be clamped if it 313 * gets out of that bound. Mediatek 8250 port supports speed 314 * higher than that, therefore we'll get original baud rate back 315 * after calling the generic set_termios method and recalculate 316 * the speed later in this method. 317 */ 318 baud = tty_termios_baud_rate(termios); 319 320 serial8250_do_set_termios(port, termios, NULL); 321 322 tty_termios_encode_baud_rate(termios, baud, baud); 323 324 /* 325 * Mediatek UARTs use an extra highspeed register (MTK_UART_HIGHS) 326 * 327 * We need to recalcualte the quot register, as the claculation depends 328 * on the vaule in the highspeed register. 329 * 330 * Some baudrates are not supported by the chip, so we use the next 331 * lower rate supported and update termios c_flag. 332 * 333 * If highspeed register is set to 3, we need to specify sample count 334 * and sample point to increase accuracy. If not, we reset the 335 * registers to their default values. 336 */ 337 baud = uart_get_baud_rate(port, termios, old, 338 port->uartclk / 16 / UART_DIV_MAX, 339 port->uartclk); 340 341 if (baud < 115200) { 342 serial_port_out(port, MTK_UART_HIGHS, 0x0); 343 quot = uart_get_divisor(port, baud); 344 } else { 345 serial_port_out(port, MTK_UART_HIGHS, 0x3); 346 quot = DIV_ROUND_UP(port->uartclk, 256 * baud); 347 } 348 349 /* 350 * Ok, we're now changing the port state. Do it with 351 * interrupts disabled. 352 */ 353 spin_lock_irqsave(&port->lock, flags); 354 355 /* 356 * Update the per-port timeout. 357 */ 358 uart_update_timeout(port, termios->c_cflag, baud); 359 360 /* set DLAB we have cval saved in up->lcr from the call to the core */ 361 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 362 serial_dl_write(up, quot); 363 364 /* reset DLAB */ 365 serial_port_out(port, UART_LCR, up->lcr); 366 367 if (baud >= 115200) { 368 unsigned int tmp; 369 370 tmp = (port->uartclk / (baud * quot)) - 1; 371 serial_port_out(port, MTK_UART_SAMPLE_COUNT, tmp); 372 serial_port_out(port, MTK_UART_SAMPLE_POINT, 373 (tmp >> 1) - 1); 374 375 /*count fraction to set fractoin register */ 376 fraction = ((port->uartclk * 100) / baud / quot) % 100; 377 fraction = DIV_ROUND_CLOSEST(fraction, 10); 378 serial_port_out(port, MTK_UART_FRACDIV_L, 379 fraction_L_mapping[fraction]); 380 serial_port_out(port, MTK_UART_FRACDIV_M, 381 fraction_M_mapping[fraction]); 382 } else { 383 serial_port_out(port, MTK_UART_SAMPLE_COUNT, 0x00); 384 serial_port_out(port, MTK_UART_SAMPLE_POINT, 0xff); 385 serial_port_out(port, MTK_UART_FRACDIV_L, 0x00); 386 serial_port_out(port, MTK_UART_FRACDIV_M, 0x00); 387 } 388 389 if ((termios->c_cflag & CRTSCTS) && (!(termios->c_iflag & CRTSCTS))) 390 mode = MTK_UART_FC_HW; 391 else if (termios->c_iflag & CRTSCTS) 392 mode = MTK_UART_FC_SW; 393 else 394 mode = MTK_UART_FC_NONE; 395 396 mtk8250_set_flow_ctrl(up, mode); 397 398 if (uart_console(port)) 399 up->port.cons->cflag = termios->c_cflag; 400 401 spin_unlock_irqrestore(&port->lock, flags); 402 /* Don't rewrite B0 */ 403 if (tty_termios_baud_rate(termios)) 404 tty_termios_encode_baud_rate(termios, baud, baud); 405 } 406 407 static int __maybe_unused mtk8250_runtime_suspend(struct device *dev) 408 { 409 struct mtk8250_data *data = dev_get_drvdata(dev); 410 struct uart_8250_port *up = serial8250_get_port(data->line); 411 412 /* wait until UART in idle status */ 413 while 414 (serial_in(up, MTK_UART_DEBUG0)); 415 416 if (data->clk_count == 0U) { 417 dev_dbg(dev, "%s clock count is 0\n", __func__); 418 } else { 419 clk_disable_unprepare(data->bus_clk); 420 data->clk_count--; 421 } 422 423 return 0; 424 } 425 426 static int __maybe_unused mtk8250_runtime_resume(struct device *dev) 427 { 428 struct mtk8250_data *data = dev_get_drvdata(dev); 429 int err; 430 431 if (data->clk_count > 0U) { 432 dev_dbg(dev, "%s clock count is %d\n", __func__, 433 data->clk_count); 434 } else { 435 err = clk_prepare_enable(data->bus_clk); 436 if (err) { 437 dev_warn(dev, "Can't enable bus clock\n"); 438 return err; 439 } 440 data->clk_count++; 441 } 442 443 return 0; 444 } 445 446 static void 447 mtk8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 448 { 449 if (!state) 450 if (!mtk8250_runtime_resume(port->dev)) 451 pm_runtime_get_sync(port->dev); 452 453 serial8250_do_pm(port, state, old); 454 455 if (state) 456 if (!pm_runtime_put_sync_suspend(port->dev)) 457 mtk8250_runtime_suspend(port->dev); 458 } 459 460 #ifdef CONFIG_SERIAL_8250_DMA 461 static bool mtk8250_dma_filter(struct dma_chan *chan, void *param) 462 { 463 return false; 464 } 465 #endif 466 467 static int mtk8250_probe_of(struct platform_device *pdev, struct uart_port *p, 468 struct mtk8250_data *data) 469 { 470 #ifdef CONFIG_SERIAL_8250_DMA 471 int dmacnt; 472 #endif 473 474 data->uart_clk = devm_clk_get(&pdev->dev, "baud"); 475 if (IS_ERR(data->uart_clk)) { 476 /* 477 * For compatibility with older device trees try unnamed 478 * clk when no baud clk can be found. 479 */ 480 data->uart_clk = devm_clk_get(&pdev->dev, NULL); 481 if (IS_ERR(data->uart_clk)) { 482 dev_warn(&pdev->dev, "Can't get uart clock\n"); 483 return PTR_ERR(data->uart_clk); 484 } 485 486 return 0; 487 } 488 489 data->bus_clk = devm_clk_get(&pdev->dev, "bus"); 490 if (IS_ERR(data->bus_clk)) 491 return PTR_ERR(data->bus_clk); 492 493 data->dma = NULL; 494 #ifdef CONFIG_SERIAL_8250_DMA 495 dmacnt = of_property_count_strings(pdev->dev.of_node, "dma-names"); 496 if (dmacnt == 2) { 497 data->dma = devm_kzalloc(&pdev->dev, sizeof(*data->dma), 498 GFP_KERNEL); 499 if (!data->dma) 500 return -ENOMEM; 501 502 data->dma->fn = mtk8250_dma_filter; 503 data->dma->rx_size = MTK_UART_RX_SIZE; 504 data->dma->rxconf.src_maxburst = MTK_UART_RX_TRIGGER; 505 data->dma->txconf.dst_maxburst = MTK_UART_TX_TRIGGER; 506 } 507 #endif 508 509 return 0; 510 } 511 512 static int mtk8250_probe(struct platform_device *pdev) 513 { 514 struct uart_8250_port uart = {}; 515 struct mtk8250_data *data; 516 struct resource *regs; 517 int irq, err; 518 519 irq = platform_get_irq(pdev, 0); 520 if (irq < 0) 521 return irq; 522 523 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 524 if (!regs) { 525 dev_err(&pdev->dev, "no registers defined\n"); 526 return -EINVAL; 527 } 528 529 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 530 resource_size(regs)); 531 if (!uart.port.membase) 532 return -ENOMEM; 533 534 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 535 if (!data) 536 return -ENOMEM; 537 538 data->clk_count = 0; 539 540 if (pdev->dev.of_node) { 541 err = mtk8250_probe_of(pdev, &uart.port, data); 542 if (err) 543 return err; 544 } else 545 return -ENODEV; 546 547 spin_lock_init(&uart.port.lock); 548 uart.port.mapbase = regs->start; 549 uart.port.irq = irq; 550 uart.port.pm = mtk8250_do_pm; 551 uart.port.type = PORT_16550; 552 uart.port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 553 uart.port.dev = &pdev->dev; 554 uart.port.iotype = UPIO_MEM32; 555 uart.port.regshift = 2; 556 uart.port.private_data = data; 557 uart.port.shutdown = mtk8250_shutdown; 558 uart.port.startup = mtk8250_startup; 559 uart.port.set_termios = mtk8250_set_termios; 560 uart.port.uartclk = clk_get_rate(data->uart_clk); 561 #ifdef CONFIG_SERIAL_8250_DMA 562 if (data->dma) 563 uart.dma = data->dma; 564 #endif 565 566 /* Disable Rate Fix function */ 567 writel(0x0, uart.port.membase + 568 (MTK_UART_RATE_FIX << uart.port.regshift)); 569 570 platform_set_drvdata(pdev, data); 571 572 pm_runtime_enable(&pdev->dev); 573 err = mtk8250_runtime_resume(&pdev->dev); 574 if (err) 575 goto err_pm_disable; 576 577 data->line = serial8250_register_8250_port(&uart); 578 if (data->line < 0) { 579 err = data->line; 580 goto err_pm_disable; 581 } 582 583 data->rx_wakeup_irq = platform_get_irq_optional(pdev, 1); 584 585 return 0; 586 587 err_pm_disable: 588 pm_runtime_disable(&pdev->dev); 589 590 return err; 591 } 592 593 static int mtk8250_remove(struct platform_device *pdev) 594 { 595 struct mtk8250_data *data = platform_get_drvdata(pdev); 596 597 pm_runtime_get_sync(&pdev->dev); 598 599 serial8250_unregister_port(data->line); 600 601 pm_runtime_disable(&pdev->dev); 602 pm_runtime_put_noidle(&pdev->dev); 603 604 if (!pm_runtime_status_suspended(&pdev->dev)) 605 mtk8250_runtime_suspend(&pdev->dev); 606 607 return 0; 608 } 609 610 static int __maybe_unused mtk8250_suspend(struct device *dev) 611 { 612 struct mtk8250_data *data = dev_get_drvdata(dev); 613 int irq = data->rx_wakeup_irq; 614 int err; 615 616 serial8250_suspend_port(data->line); 617 618 pinctrl_pm_select_sleep_state(dev); 619 if (irq >= 0) { 620 err = enable_irq_wake(irq); 621 if (err) { 622 dev_err(dev, 623 "failed to enable irq wake on IRQ %d: %d\n", 624 irq, err); 625 pinctrl_pm_select_default_state(dev); 626 serial8250_resume_port(data->line); 627 return err; 628 } 629 } 630 631 return 0; 632 } 633 634 static int __maybe_unused mtk8250_resume(struct device *dev) 635 { 636 struct mtk8250_data *data = dev_get_drvdata(dev); 637 int irq = data->rx_wakeup_irq; 638 639 if (irq >= 0) 640 disable_irq_wake(irq); 641 pinctrl_pm_select_default_state(dev); 642 643 serial8250_resume_port(data->line); 644 645 return 0; 646 } 647 648 static const struct dev_pm_ops mtk8250_pm_ops = { 649 SET_SYSTEM_SLEEP_PM_OPS(mtk8250_suspend, mtk8250_resume) 650 SET_RUNTIME_PM_OPS(mtk8250_runtime_suspend, mtk8250_runtime_resume, 651 NULL) 652 }; 653 654 static const struct of_device_id mtk8250_of_match[] = { 655 { .compatible = "mediatek,mt6577-uart" }, 656 { /* Sentinel */ } 657 }; 658 MODULE_DEVICE_TABLE(of, mtk8250_of_match); 659 660 static struct platform_driver mtk8250_platform_driver = { 661 .driver = { 662 .name = "mt6577-uart", 663 .pm = &mtk8250_pm_ops, 664 .of_match_table = mtk8250_of_match, 665 }, 666 .probe = mtk8250_probe, 667 .remove = mtk8250_remove, 668 }; 669 module_platform_driver(mtk8250_platform_driver); 670 671 #ifdef CONFIG_SERIAL_8250_CONSOLE 672 static int __init early_mtk8250_setup(struct earlycon_device *device, 673 const char *options) 674 { 675 if (!device->port.membase) 676 return -ENODEV; 677 678 device->port.iotype = UPIO_MEM32; 679 device->port.regshift = 2; 680 681 return early_serial8250_setup(device, NULL); 682 } 683 684 OF_EARLYCON_DECLARE(mtk8250, "mediatek,mt6577-uart", early_mtk8250_setup); 685 #endif 686 687 MODULE_AUTHOR("Matthias Brugger"); 688 MODULE_LICENSE("GPL"); 689 MODULE_DESCRIPTION("Mediatek 8250 serial port driver"); 690