1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * 8250_lpss.c - Driver for UART on Intel Braswell and various other Intel SoCs
4  *
5  * Copyright (C) 2016 Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/rational.h>
13 
14 #include <linux/dmaengine.h>
15 #include <linux/dma/dw.h>
16 
17 #include "8250_dwlib.h"
18 
19 #define PCI_DEVICE_ID_INTEL_QRK_UARTx	0x0936
20 
21 #define PCI_DEVICE_ID_INTEL_BYT_UART1	0x0f0a
22 #define PCI_DEVICE_ID_INTEL_BYT_UART2	0x0f0c
23 
24 #define PCI_DEVICE_ID_INTEL_BSW_UART1	0x228a
25 #define PCI_DEVICE_ID_INTEL_BSW_UART2	0x228c
26 
27 #define PCI_DEVICE_ID_INTEL_EHL_UART0	0x4b96
28 #define PCI_DEVICE_ID_INTEL_EHL_UART1	0x4b97
29 #define PCI_DEVICE_ID_INTEL_EHL_UART2	0x4b98
30 #define PCI_DEVICE_ID_INTEL_EHL_UART3	0x4b99
31 #define PCI_DEVICE_ID_INTEL_EHL_UART4	0x4b9a
32 #define PCI_DEVICE_ID_INTEL_EHL_UART5	0x4b9b
33 
34 #define PCI_DEVICE_ID_INTEL_BDW_UART1	0x9ce3
35 #define PCI_DEVICE_ID_INTEL_BDW_UART2	0x9ce4
36 
37 /* Intel LPSS specific registers */
38 
39 #define BYT_PRV_CLK			0x800
40 #define BYT_PRV_CLK_EN			BIT(0)
41 #define BYT_PRV_CLK_M_VAL_SHIFT		1
42 #define BYT_PRV_CLK_N_VAL_SHIFT		16
43 #define BYT_PRV_CLK_UPDATE		BIT(31)
44 
45 #define BYT_TX_OVF_INT			0x820
46 #define BYT_TX_OVF_INT_MASK		BIT(1)
47 
48 struct lpss8250;
49 
50 struct lpss8250_board {
51 	unsigned long freq;
52 	unsigned int base_baud;
53 	int (*setup)(struct lpss8250 *, struct uart_port *p);
54 	void (*exit)(struct lpss8250 *);
55 };
56 
57 struct lpss8250 {
58 	struct dw8250_port_data data;
59 	struct lpss8250_board *board;
60 
61 	/* DMA parameters */
62 	struct dw_dma_chip dma_chip;
63 	struct dw_dma_slave dma_param;
64 	u8 dma_maxburst;
65 };
66 
67 static inline struct lpss8250 *to_lpss8250(struct dw8250_port_data *data)
68 {
69 	return container_of(data, struct lpss8250, data);
70 }
71 
72 static void byt_set_termios(struct uart_port *p, struct ktermios *termios,
73 			    struct ktermios *old)
74 {
75 	unsigned int baud = tty_termios_baud_rate(termios);
76 	struct lpss8250 *lpss = to_lpss8250(p->private_data);
77 	unsigned long fref = lpss->board->freq, fuart = baud * 16;
78 	unsigned long w = BIT(15) - 1;
79 	unsigned long m, n;
80 	u32 reg;
81 
82 	/* Gracefully handle the B0 case: fall back to B9600 */
83 	fuart = fuart ? fuart : 9600 * 16;
84 
85 	/* Get Fuart closer to Fref */
86 	fuart *= rounddown_pow_of_two(fref / fuart);
87 
88 	/*
89 	 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
90 	 * dividers must be adjusted.
91 	 *
92 	 * uartclk = (m / n) * 100 MHz, where m <= n
93 	 */
94 	rational_best_approximation(fuart, fref, w, w, &m, &n);
95 	p->uartclk = fuart;
96 
97 	/* Reset the clock */
98 	reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
99 	writel(reg, p->membase + BYT_PRV_CLK);
100 	reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
101 	writel(reg, p->membase + BYT_PRV_CLK);
102 
103 	dw8250_do_set_termios(p, termios, old);
104 }
105 
106 static unsigned int byt_get_mctrl(struct uart_port *port)
107 {
108 	unsigned int ret = serial8250_do_get_mctrl(port);
109 
110 	/* Force DCD and DSR signals to permanently be reported as active */
111 	ret |= TIOCM_CAR | TIOCM_DSR;
112 
113 	return ret;
114 }
115 
116 static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
117 {
118 	struct dw_dma_slave *param = &lpss->dma_param;
119 	struct pci_dev *pdev = to_pci_dev(port->dev);
120 	struct pci_dev *dma_dev;
121 
122 	switch (pdev->device) {
123 	case PCI_DEVICE_ID_INTEL_BYT_UART1:
124 	case PCI_DEVICE_ID_INTEL_BSW_UART1:
125 	case PCI_DEVICE_ID_INTEL_BDW_UART1:
126 		param->src_id = 3;
127 		param->dst_id = 2;
128 		break;
129 	case PCI_DEVICE_ID_INTEL_BYT_UART2:
130 	case PCI_DEVICE_ID_INTEL_BSW_UART2:
131 	case PCI_DEVICE_ID_INTEL_BDW_UART2:
132 		param->src_id = 5;
133 		param->dst_id = 4;
134 		break;
135 	default:
136 		return -EINVAL;
137 	}
138 
139 	dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
140 
141 	param->dma_dev = &dma_dev->dev;
142 	param->m_master = 0;
143 	param->p_master = 1;
144 
145 	lpss->dma_maxburst = 16;
146 
147 	port->set_termios = byt_set_termios;
148 	port->get_mctrl = byt_get_mctrl;
149 
150 	/* Disable TX counter interrupts */
151 	writel(BYT_TX_OVF_INT_MASK, port->membase + BYT_TX_OVF_INT);
152 
153 	return 0;
154 }
155 
156 static void byt_serial_exit(struct lpss8250 *lpss)
157 {
158 	struct dw_dma_slave *param = &lpss->dma_param;
159 
160 	/* Paired with pci_get_slot() in the byt_serial_setup() above */
161 	put_device(param->dma_dev);
162 }
163 
164 static int ehl_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
165 {
166 	struct uart_8250_dma *dma = &lpss->data.dma;
167 	struct uart_8250_port *up = up_to_u8250p(port);
168 
169 	/*
170 	 * This simply makes the checks in the 8250_port to try the DMA
171 	 * channel request which in turn uses the magic of ACPI tables
172 	 * parsing (see drivers/dma/acpi-dma.c for the details) and
173 	 * matching with the registered General Purpose DMA controllers.
174 	 */
175 	up->dma = dma;
176 
177 	port->set_termios = dw8250_do_set_termios;
178 
179 	return 0;
180 }
181 
182 static void ehl_serial_exit(struct lpss8250 *lpss)
183 {
184 	struct uart_8250_port *up = serial8250_get_port(lpss->data.line);
185 
186 	up->dma = NULL;
187 }
188 
189 #ifdef CONFIG_SERIAL_8250_DMA
190 static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
191 	.nr_channels = 2,
192 	.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
193 	.chan_priority = CHAN_PRIORITY_ASCENDING,
194 	.block_size = 4095,
195 	.nr_masters = 1,
196 	.data_width = {4},
197 	.multi_block = {0},
198 };
199 
200 static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
201 {
202 	struct uart_8250_dma *dma = &lpss->data.dma;
203 	struct dw_dma_chip *chip = &lpss->dma_chip;
204 	struct dw_dma_slave *param = &lpss->dma_param;
205 	struct pci_dev *pdev = to_pci_dev(port->dev);
206 	int ret;
207 
208 	chip->pdata = &qrk_serial_dma_pdata;
209 	chip->dev = &pdev->dev;
210 	chip->id = pdev->devfn;
211 	chip->irq = pci_irq_vector(pdev, 0);
212 	chip->regs = pci_ioremap_bar(pdev, 1);
213 	if (!chip->regs)
214 		return;
215 
216 	/* Falling back to PIO mode if DMA probing fails */
217 	ret = dw_dma_probe(chip);
218 	if (ret)
219 		return;
220 
221 	pci_try_set_mwi(pdev);
222 
223 	/* Special DMA address for UART */
224 	dma->rx_dma_addr = 0xfffff000;
225 	dma->tx_dma_addr = 0xfffff000;
226 
227 	param->dma_dev = &pdev->dev;
228 	param->src_id = 0;
229 	param->dst_id = 1;
230 	param->hs_polarity = true;
231 
232 	lpss->dma_maxburst = 8;
233 }
234 
235 static void qrk_serial_exit_dma(struct lpss8250 *lpss)
236 {
237 	struct dw_dma_chip *chip = &lpss->dma_chip;
238 	struct dw_dma_slave *param = &lpss->dma_param;
239 
240 	if (!param->dma_dev)
241 		return;
242 
243 	dw_dma_remove(chip);
244 
245 	pci_iounmap(to_pci_dev(chip->dev), chip->regs);
246 }
247 #else	/* CONFIG_SERIAL_8250_DMA */
248 static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port) {}
249 static void qrk_serial_exit_dma(struct lpss8250 *lpss) {}
250 #endif	/* !CONFIG_SERIAL_8250_DMA */
251 
252 static int qrk_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
253 {
254 	qrk_serial_setup_dma(lpss, port);
255 	return 0;
256 }
257 
258 static void qrk_serial_exit(struct lpss8250 *lpss)
259 {
260 	qrk_serial_exit_dma(lpss);
261 }
262 
263 static bool lpss8250_dma_filter(struct dma_chan *chan, void *param)
264 {
265 	struct dw_dma_slave *dws = param;
266 
267 	if (dws->dma_dev != chan->device->dev)
268 		return false;
269 
270 	chan->private = dws;
271 	return true;
272 }
273 
274 static int lpss8250_dma_setup(struct lpss8250 *lpss, struct uart_8250_port *port)
275 {
276 	struct uart_8250_dma *dma = &lpss->data.dma;
277 	struct dw_dma_slave *rx_param, *tx_param;
278 	struct device *dev = port->port.dev;
279 
280 	if (!lpss->dma_param.dma_dev)
281 		return 0;
282 
283 	rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
284 	if (!rx_param)
285 		return -ENOMEM;
286 
287 	tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
288 	if (!tx_param)
289 		return -ENOMEM;
290 
291 	*rx_param = lpss->dma_param;
292 	dma->rxconf.src_maxburst = lpss->dma_maxburst;
293 
294 	*tx_param = lpss->dma_param;
295 	dma->txconf.dst_maxburst = lpss->dma_maxburst;
296 
297 	dma->fn = lpss8250_dma_filter;
298 	dma->rx_param = rx_param;
299 	dma->tx_param = tx_param;
300 
301 	port->dma = dma;
302 	return 0;
303 }
304 
305 static int lpss8250_probe(struct pci_dev *pdev, const struct pci_device_id *id)
306 {
307 	struct uart_8250_port uart;
308 	struct lpss8250 *lpss;
309 	int ret;
310 
311 	ret = pcim_enable_device(pdev);
312 	if (ret)
313 		return ret;
314 
315 	pci_set_master(pdev);
316 
317 	lpss = devm_kzalloc(&pdev->dev, sizeof(*lpss), GFP_KERNEL);
318 	if (!lpss)
319 		return -ENOMEM;
320 
321 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
322 	if (ret < 0)
323 		return ret;
324 
325 	lpss->board = (struct lpss8250_board *)id->driver_data;
326 
327 	memset(&uart, 0, sizeof(struct uart_8250_port));
328 
329 	uart.port.dev = &pdev->dev;
330 	uart.port.irq = pci_irq_vector(pdev, 0);
331 	uart.port.private_data = &lpss->data;
332 	uart.port.type = PORT_16550A;
333 	uart.port.iotype = UPIO_MEM32;
334 	uart.port.regshift = 2;
335 	uart.port.uartclk = lpss->board->base_baud * 16;
336 	uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE;
337 	uart.capabilities = UART_CAP_FIFO | UART_CAP_AFE;
338 	uart.port.mapbase = pci_resource_start(pdev, 0);
339 	uart.port.membase = pcim_iomap(pdev, 0, 0);
340 	if (!uart.port.membase)
341 		return -ENOMEM;
342 
343 	ret = lpss->board->setup(lpss, &uart.port);
344 	if (ret)
345 		return ret;
346 
347 	dw8250_setup_port(&uart.port);
348 
349 	ret = lpss8250_dma_setup(lpss, &uart);
350 	if (ret)
351 		goto err_exit;
352 
353 	ret = serial8250_register_8250_port(&uart);
354 	if (ret < 0)
355 		goto err_exit;
356 
357 	lpss->data.line = ret;
358 
359 	pci_set_drvdata(pdev, lpss);
360 	return 0;
361 
362 err_exit:
363 	lpss->board->exit(lpss);
364 	pci_free_irq_vectors(pdev);
365 	return ret;
366 }
367 
368 static void lpss8250_remove(struct pci_dev *pdev)
369 {
370 	struct lpss8250 *lpss = pci_get_drvdata(pdev);
371 
372 	serial8250_unregister_port(lpss->data.line);
373 
374 	lpss->board->exit(lpss);
375 	pci_free_irq_vectors(pdev);
376 }
377 
378 static const struct lpss8250_board byt_board = {
379 	.freq = 100000000,
380 	.base_baud = 2764800,
381 	.setup = byt_serial_setup,
382 	.exit = byt_serial_exit,
383 };
384 
385 static const struct lpss8250_board ehl_board = {
386 	.freq = 200000000,
387 	.base_baud = 12500000,
388 	.setup = ehl_serial_setup,
389 	.exit = ehl_serial_exit,
390 };
391 
392 static const struct lpss8250_board qrk_board = {
393 	.freq = 44236800,
394 	.base_baud = 2764800,
395 	.setup = qrk_serial_setup,
396 	.exit = qrk_serial_exit,
397 };
398 
399 static const struct pci_device_id pci_ids[] = {
400 	{ PCI_DEVICE_DATA(INTEL, QRK_UARTx, &qrk_board) },
401 	{ PCI_DEVICE_DATA(INTEL, EHL_UART0, &ehl_board) },
402 	{ PCI_DEVICE_DATA(INTEL, EHL_UART1, &ehl_board) },
403 	{ PCI_DEVICE_DATA(INTEL, EHL_UART2, &ehl_board) },
404 	{ PCI_DEVICE_DATA(INTEL, EHL_UART3, &ehl_board) },
405 	{ PCI_DEVICE_DATA(INTEL, EHL_UART4, &ehl_board) },
406 	{ PCI_DEVICE_DATA(INTEL, EHL_UART5, &ehl_board) },
407 	{ PCI_DEVICE_DATA(INTEL, BYT_UART1, &byt_board) },
408 	{ PCI_DEVICE_DATA(INTEL, BYT_UART2, &byt_board) },
409 	{ PCI_DEVICE_DATA(INTEL, BSW_UART1, &byt_board) },
410 	{ PCI_DEVICE_DATA(INTEL, BSW_UART2, &byt_board) },
411 	{ PCI_DEVICE_DATA(INTEL, BDW_UART1, &byt_board) },
412 	{ PCI_DEVICE_DATA(INTEL, BDW_UART2, &byt_board) },
413 	{ }
414 };
415 MODULE_DEVICE_TABLE(pci, pci_ids);
416 
417 static struct pci_driver lpss8250_pci_driver = {
418 	.name           = "8250_lpss",
419 	.id_table       = pci_ids,
420 	.probe          = lpss8250_probe,
421 	.remove         = lpss8250_remove,
422 };
423 
424 module_pci_driver(lpss8250_pci_driver);
425 
426 MODULE_AUTHOR("Intel Corporation");
427 MODULE_LICENSE("GPL v2");
428 MODULE_DESCRIPTION("Intel LPSS UART driver");
429