1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Serial port driver for NXP LPC18xx/43xx UART 4 * 5 * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com> 6 * 7 * Based on 8250_mtk.c: 8 * Copyright (c) 2014 MundoReader S.L. 9 * Matthias Brugger <matthias.bgg@gmail.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 18 #include "8250.h" 19 20 /* Additional LPC18xx/43xx 8250 registers and bits */ 21 #define LPC18XX_UART_RS485CTRL (0x04c / sizeof(u32)) 22 #define LPC18XX_UART_RS485CTRL_NMMEN BIT(0) 23 #define LPC18XX_UART_RS485CTRL_DCTRL BIT(4) 24 #define LPC18XX_UART_RS485CTRL_OINV BIT(5) 25 #define LPC18XX_UART_RS485DLY (0x054 / sizeof(u32)) 26 #define LPC18XX_UART_RS485DLY_MAX 255 27 28 struct lpc18xx_uart_data { 29 struct uart_8250_dma dma; 30 struct clk *clk_uart; 31 struct clk *clk_reg; 32 int line; 33 }; 34 35 static int lpc18xx_rs485_config(struct uart_port *port, struct ktermios *termios, 36 struct serial_rs485 *rs485) 37 { 38 struct uart_8250_port *up = up_to_u8250p(port); 39 u32 rs485_ctrl_reg = 0; 40 u32 rs485_dly_reg = 0; 41 unsigned baud_clk; 42 43 if (rs485->flags & SER_RS485_ENABLED) { 44 rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_NMMEN | 45 LPC18XX_UART_RS485CTRL_DCTRL; 46 47 if (rs485->flags & SER_RS485_RTS_ON_SEND) 48 rs485_ctrl_reg |= LPC18XX_UART_RS485CTRL_OINV; 49 } 50 51 if (rs485->delay_rts_after_send) { 52 baud_clk = port->uartclk / up->dl_read(up); 53 rs485_dly_reg = DIV_ROUND_UP(rs485->delay_rts_after_send 54 * baud_clk, MSEC_PER_SEC); 55 56 if (rs485_dly_reg > LPC18XX_UART_RS485DLY_MAX) 57 rs485_dly_reg = LPC18XX_UART_RS485DLY_MAX; 58 59 /* Calculate the resulting delay in ms */ 60 rs485->delay_rts_after_send = (rs485_dly_reg * MSEC_PER_SEC) 61 / baud_clk; 62 } 63 64 serial_out(up, LPC18XX_UART_RS485CTRL, rs485_ctrl_reg); 65 serial_out(up, LPC18XX_UART_RS485DLY, rs485_dly_reg); 66 67 return 0; 68 } 69 70 static void lpc18xx_uart_serial_out(struct uart_port *p, int offset, int value) 71 { 72 /* 73 * For DMA mode one must ensure that the UART_FCR_DMA_SELECT 74 * bit is set when FIFO is enabled. Even if DMA is not used 75 * setting this bit doesn't seem to affect anything. 76 */ 77 if (offset == UART_FCR && (value & UART_FCR_ENABLE_FIFO)) 78 value |= UART_FCR_DMA_SELECT; 79 80 offset = offset << p->regshift; 81 writel(value, p->membase + offset); 82 } 83 84 static const struct serial_rs485 lpc18xx_rs485_supported = { 85 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 86 .delay_rts_after_send = 1, 87 /* Delay RTS before send is not supported */ 88 }; 89 90 static int lpc18xx_serial_probe(struct platform_device *pdev) 91 { 92 struct lpc18xx_uart_data *data; 93 struct uart_8250_port uart; 94 struct resource *res; 95 int irq, ret; 96 97 irq = platform_get_irq(pdev, 0); 98 if (irq < 0) 99 return irq; 100 101 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 102 if (!res) { 103 dev_err(&pdev->dev, "memory resource not found"); 104 return -EINVAL; 105 } 106 107 memset(&uart, 0, sizeof(uart)); 108 109 uart.port.membase = devm_ioremap(&pdev->dev, res->start, 110 resource_size(res)); 111 if (!uart.port.membase) 112 return -ENOMEM; 113 114 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 115 if (!data) 116 return -ENOMEM; 117 118 data->clk_uart = devm_clk_get(&pdev->dev, "uartclk"); 119 if (IS_ERR(data->clk_uart)) { 120 dev_err(&pdev->dev, "uart clock not found\n"); 121 return PTR_ERR(data->clk_uart); 122 } 123 124 data->clk_reg = devm_clk_get(&pdev->dev, "reg"); 125 if (IS_ERR(data->clk_reg)) { 126 dev_err(&pdev->dev, "reg clock not found\n"); 127 return PTR_ERR(data->clk_reg); 128 } 129 130 ret = clk_prepare_enable(data->clk_reg); 131 if (ret) { 132 dev_err(&pdev->dev, "unable to enable reg clock\n"); 133 return ret; 134 } 135 136 ret = clk_prepare_enable(data->clk_uart); 137 if (ret) { 138 dev_err(&pdev->dev, "unable to enable uart clock\n"); 139 goto dis_clk_reg; 140 } 141 142 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 143 if (ret >= 0) 144 uart.port.line = ret; 145 146 data->dma.rx_param = data; 147 data->dma.tx_param = data; 148 149 spin_lock_init(&uart.port.lock); 150 uart.port.dev = &pdev->dev; 151 uart.port.irq = irq; 152 uart.port.iotype = UPIO_MEM32; 153 uart.port.mapbase = res->start; 154 uart.port.regshift = 2; 155 uart.port.type = PORT_16550A; 156 uart.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SKIP_TEST; 157 uart.port.uartclk = clk_get_rate(data->clk_uart); 158 uart.port.private_data = data; 159 uart.port.rs485_config = lpc18xx_rs485_config; 160 uart.port.rs485_supported = lpc18xx_rs485_supported; 161 uart.port.serial_out = lpc18xx_uart_serial_out; 162 163 uart.dma = &data->dma; 164 uart.dma->rxconf.src_maxburst = 1; 165 uart.dma->txconf.dst_maxburst = 1; 166 167 ret = serial8250_register_8250_port(&uart); 168 if (ret < 0) { 169 dev_err(&pdev->dev, "unable to register 8250 port\n"); 170 goto dis_uart_clk; 171 } 172 173 data->line = ret; 174 platform_set_drvdata(pdev, data); 175 176 return 0; 177 178 dis_uart_clk: 179 clk_disable_unprepare(data->clk_uart); 180 dis_clk_reg: 181 clk_disable_unprepare(data->clk_reg); 182 return ret; 183 } 184 185 static int lpc18xx_serial_remove(struct platform_device *pdev) 186 { 187 struct lpc18xx_uart_data *data = platform_get_drvdata(pdev); 188 189 serial8250_unregister_port(data->line); 190 clk_disable_unprepare(data->clk_uart); 191 clk_disable_unprepare(data->clk_reg); 192 193 return 0; 194 } 195 196 static const struct of_device_id lpc18xx_serial_match[] = { 197 { .compatible = "nxp,lpc1850-uart" }, 198 { }, 199 }; 200 MODULE_DEVICE_TABLE(of, lpc18xx_serial_match); 201 202 static struct platform_driver lpc18xx_serial_driver = { 203 .probe = lpc18xx_serial_probe, 204 .remove = lpc18xx_serial_remove, 205 .driver = { 206 .name = "lpc18xx-uart", 207 .of_match_table = lpc18xx_serial_match, 208 }, 209 }; 210 module_platform_driver(lpc18xx_serial_driver); 211 212 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>"); 213 MODULE_DESCRIPTION("Serial port driver NXP LPC18xx/43xx devices"); 214 MODULE_LICENSE("GPL v2"); 215