1 /* 2 * Copyright (C) 2010 Lars-Peter Clausen <lars@metafoo.de> 3 * Copyright (C) 2015 Imagination Technologies 4 * 5 * Ingenic SoC UART support 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * You should have received a copy of the GNU General Public License along 13 * with this program; if not, write to the Free Software Foundation, Inc., 14 * 675 Mass Ave, Cambridge, MA 02139, USA. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/console.h> 19 #include <linux/io.h> 20 #include <linux/libfdt.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_fdt.h> 24 #include <linux/of_device.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial_8250.h> 27 #include <linux/serial_core.h> 28 #include <linux/serial_reg.h> 29 30 #include "8250.h" 31 32 /** ingenic_uart_config: SOC specific config data. */ 33 struct ingenic_uart_config { 34 int tx_loadsz; 35 int fifosize; 36 }; 37 38 struct ingenic_uart_data { 39 struct clk *clk_module; 40 struct clk *clk_baud; 41 int line; 42 }; 43 44 static const struct of_device_id of_match[]; 45 46 #define UART_FCR_UME BIT(4) 47 48 #define UART_MCR_MDCE BIT(7) 49 #define UART_MCR_FCM BIT(6) 50 51 #ifdef CONFIG_SERIAL_EARLYCON 52 static struct earlycon_device *early_device; 53 54 static uint8_t __init early_in(struct uart_port *port, int offset) 55 { 56 return readl(port->membase + (offset << 2)); 57 } 58 59 static void __init early_out(struct uart_port *port, int offset, uint8_t value) 60 { 61 writel(value, port->membase + (offset << 2)); 62 } 63 64 static void __init ingenic_early_console_putc(struct uart_port *port, int c) 65 { 66 uint8_t lsr; 67 68 do { 69 lsr = early_in(port, UART_LSR); 70 } while ((lsr & UART_LSR_TEMT) == 0); 71 72 early_out(port, UART_TX, c); 73 } 74 75 static void __init ingenic_early_console_write(struct console *console, 76 const char *s, unsigned int count) 77 { 78 uart_console_write(&early_device->port, s, count, 79 ingenic_early_console_putc); 80 } 81 82 static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev) 83 { 84 void *fdt = initial_boot_params; 85 const __be32 *prop; 86 int offset; 87 88 offset = fdt_path_offset(fdt, "/ext"); 89 if (offset < 0) 90 return; 91 92 prop = fdt_getprop(fdt, offset, "clock-frequency", NULL); 93 if (!prop) 94 return; 95 96 dev->port.uartclk = be32_to_cpup(prop); 97 } 98 99 static int __init ingenic_early_console_setup(struct earlycon_device *dev, 100 const char *opt) 101 { 102 struct uart_port *port = &dev->port; 103 unsigned int baud, divisor; 104 105 if (!dev->port.membase) 106 return -ENODEV; 107 108 ingenic_early_console_setup_clock(dev); 109 110 baud = dev->baud ?: 115200; 111 divisor = DIV_ROUND_CLOSEST(port->uartclk, 16 * baud); 112 113 early_out(port, UART_IER, 0); 114 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); 115 early_out(port, UART_DLL, 0); 116 early_out(port, UART_DLM, 0); 117 early_out(port, UART_LCR, UART_LCR_WLEN8); 118 early_out(port, UART_FCR, UART_FCR_UME | UART_FCR_CLEAR_XMIT | 119 UART_FCR_CLEAR_RCVR | UART_FCR_ENABLE_FIFO); 120 early_out(port, UART_MCR, UART_MCR_RTS | UART_MCR_DTR); 121 122 early_out(port, UART_LCR, UART_LCR_DLAB | UART_LCR_WLEN8); 123 early_out(port, UART_DLL, divisor & 0xff); 124 early_out(port, UART_DLM, (divisor >> 8) & 0xff); 125 early_out(port, UART_LCR, UART_LCR_WLEN8); 126 127 early_device = dev; 128 dev->con->write = ingenic_early_console_write; 129 130 return 0; 131 } 132 133 EARLYCON_DECLARE(jz4740_uart, ingenic_early_console_setup); 134 OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart", 135 ingenic_early_console_setup); 136 137 EARLYCON_DECLARE(jz4775_uart, ingenic_early_console_setup); 138 OF_EARLYCON_DECLARE(jz4775_uart, "ingenic,jz4775-uart", 139 ingenic_early_console_setup); 140 141 EARLYCON_DECLARE(jz4780_uart, ingenic_early_console_setup); 142 OF_EARLYCON_DECLARE(jz4780_uart, "ingenic,jz4780-uart", 143 ingenic_early_console_setup); 144 #endif /* CONFIG_SERIAL_EARLYCON */ 145 146 static void ingenic_uart_serial_out(struct uart_port *p, int offset, int value) 147 { 148 int ier; 149 150 switch (offset) { 151 case UART_FCR: 152 /* UART module enable */ 153 value |= UART_FCR_UME; 154 break; 155 156 case UART_IER: 157 /* Enable receive timeout interrupt with the 158 * receive line status interrupt */ 159 value |= (value & 0x4) << 2; 160 break; 161 162 case UART_MCR: 163 /* If we have enabled modem status IRQs we should enable modem 164 * mode. */ 165 ier = p->serial_in(p, UART_IER); 166 167 if (ier & UART_IER_MSI) 168 value |= UART_MCR_MDCE | UART_MCR_FCM; 169 else 170 value &= ~(UART_MCR_MDCE | UART_MCR_FCM); 171 break; 172 173 default: 174 break; 175 } 176 177 writeb(value, p->membase + (offset << p->regshift)); 178 } 179 180 static unsigned int ingenic_uart_serial_in(struct uart_port *p, int offset) 181 { 182 unsigned int value; 183 184 value = readb(p->membase + (offset << p->regshift)); 185 186 /* Hide non-16550 compliant bits from higher levels */ 187 switch (offset) { 188 case UART_FCR: 189 value &= ~UART_FCR_UME; 190 break; 191 192 case UART_MCR: 193 value &= ~(UART_MCR_MDCE | UART_MCR_FCM); 194 break; 195 196 default: 197 break; 198 } 199 return value; 200 } 201 202 static int ingenic_uart_probe(struct platform_device *pdev) 203 { 204 struct uart_8250_port uart = {}; 205 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 206 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 207 struct ingenic_uart_data *data; 208 const struct ingenic_uart_config *cdata; 209 const struct of_device_id *match; 210 int err, line; 211 212 match = of_match_device(of_match, &pdev->dev); 213 if (!match) { 214 dev_err(&pdev->dev, "Error: No device match found\n"); 215 return -ENODEV; 216 } 217 cdata = match->data; 218 219 if (!regs || !irq) { 220 dev_err(&pdev->dev, "no registers/irq defined\n"); 221 return -EINVAL; 222 } 223 224 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 225 if (!data) 226 return -ENOMEM; 227 228 spin_lock_init(&uart.port.lock); 229 uart.port.type = PORT_16550A; 230 uart.port.flags = UPF_SKIP_TEST | UPF_IOREMAP | UPF_FIXED_TYPE; 231 uart.port.iotype = UPIO_MEM; 232 uart.port.mapbase = regs->start; 233 uart.port.regshift = 2; 234 uart.port.serial_out = ingenic_uart_serial_out; 235 uart.port.serial_in = ingenic_uart_serial_in; 236 uart.port.irq = irq->start; 237 uart.port.dev = &pdev->dev; 238 uart.port.fifosize = cdata->fifosize; 239 uart.tx_loadsz = cdata->tx_loadsz; 240 uart.capabilities = UART_CAP_FIFO | UART_CAP_RTOIE; 241 242 /* Check for a fixed line number */ 243 line = of_alias_get_id(pdev->dev.of_node, "serial"); 244 if (line >= 0) 245 uart.port.line = line; 246 247 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 248 resource_size(regs)); 249 if (!uart.port.membase) 250 return -ENOMEM; 251 252 data->clk_module = devm_clk_get(&pdev->dev, "module"); 253 if (IS_ERR(data->clk_module)) { 254 err = PTR_ERR(data->clk_module); 255 if (err != -EPROBE_DEFER) 256 dev_err(&pdev->dev, 257 "unable to get module clock: %d\n", err); 258 return err; 259 } 260 261 data->clk_baud = devm_clk_get(&pdev->dev, "baud"); 262 if (IS_ERR(data->clk_baud)) { 263 err = PTR_ERR(data->clk_baud); 264 if (err != -EPROBE_DEFER) 265 dev_err(&pdev->dev, 266 "unable to get baud clock: %d\n", err); 267 return err; 268 } 269 270 err = clk_prepare_enable(data->clk_module); 271 if (err) { 272 dev_err(&pdev->dev, "could not enable module clock: %d\n", err); 273 goto out; 274 } 275 276 err = clk_prepare_enable(data->clk_baud); 277 if (err) { 278 dev_err(&pdev->dev, "could not enable baud clock: %d\n", err); 279 goto out_disable_moduleclk; 280 } 281 uart.port.uartclk = clk_get_rate(data->clk_baud); 282 283 data->line = serial8250_register_8250_port(&uart); 284 if (data->line < 0) { 285 err = data->line; 286 goto out_disable_baudclk; 287 } 288 289 platform_set_drvdata(pdev, data); 290 return 0; 291 292 out_disable_baudclk: 293 clk_disable_unprepare(data->clk_baud); 294 out_disable_moduleclk: 295 clk_disable_unprepare(data->clk_module); 296 out: 297 return err; 298 } 299 300 static int ingenic_uart_remove(struct platform_device *pdev) 301 { 302 struct ingenic_uart_data *data = platform_get_drvdata(pdev); 303 304 serial8250_unregister_port(data->line); 305 clk_disable_unprepare(data->clk_module); 306 clk_disable_unprepare(data->clk_baud); 307 return 0; 308 } 309 310 static const struct ingenic_uart_config jz4740_uart_config = { 311 .tx_loadsz = 8, 312 .fifosize = 16, 313 }; 314 315 static const struct ingenic_uart_config jz4760_uart_config = { 316 .tx_loadsz = 16, 317 .fifosize = 32, 318 }; 319 320 static const struct ingenic_uart_config jz4780_uart_config = { 321 .tx_loadsz = 32, 322 .fifosize = 64, 323 }; 324 325 static const struct of_device_id of_match[] = { 326 { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config }, 327 { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config }, 328 { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config }, 329 { .compatible = "ingenic,jz4780-uart", .data = &jz4780_uart_config }, 330 { /* sentinel */ } 331 }; 332 MODULE_DEVICE_TABLE(of, of_match); 333 334 static struct platform_driver ingenic_uart_platform_driver = { 335 .driver = { 336 .name = "ingenic-uart", 337 .of_match_table = of_match, 338 }, 339 .probe = ingenic_uart_probe, 340 .remove = ingenic_uart_remove, 341 }; 342 343 module_platform_driver(ingenic_uart_platform_driver); 344 345 MODULE_AUTHOR("Paul Burton"); 346 MODULE_LICENSE("GPL"); 347 MODULE_DESCRIPTION("Ingenic SoC UART driver"); 348