1 /* 2 * Probe for F81216A LPC to 4 UART 3 * 4 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S 5 * 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 */ 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/pnp.h> 14 #include <linux/kernel.h> 15 #include <linux/serial_core.h> 16 #include <linux/irq.h> 17 #include "8250.h" 18 19 #define ADDR_PORT 0 20 #define DATA_PORT 1 21 #define EXIT_KEY 0xAA 22 #define CHIP_ID1 0x20 23 #define CHIP_ID2 0x21 24 #define CHIP_ID_F81865 0x0407 25 #define CHIP_ID_F81866 0x1010 26 #define CHIP_ID_F81216AD 0x1602 27 #define CHIP_ID_F81216H 0x0501 28 #define CHIP_ID_F81216 0x0802 29 #define VENDOR_ID1 0x23 30 #define VENDOR_ID1_VAL 0x19 31 #define VENDOR_ID2 0x24 32 #define VENDOR_ID2_VAL 0x34 33 #define IO_ADDR1 0x61 34 #define IO_ADDR2 0x60 35 #define LDN 0x7 36 37 #define FINTEK_IRQ_MODE 0x70 38 #define IRQ_SHARE BIT(4) 39 #define IRQ_MODE_MASK (BIT(6) | BIT(5)) 40 #define IRQ_LEVEL_LOW 0 41 #define IRQ_EDGE_HIGH BIT(5) 42 43 #define RS485 0xF0 44 #define RTS_INVERT BIT(5) 45 #define RS485_URA BIT(4) 46 #define RXW4C_IRA BIT(3) 47 #define TXW4C_IRA BIT(2) 48 49 #define FIFO_CTRL 0xF6 50 #define FIFO_MODE_MASK (BIT(1) | BIT(0)) 51 #define FIFO_MODE_128 (BIT(1) | BIT(0)) 52 #define RXFTHR_MODE_MASK (BIT(5) | BIT(4)) 53 #define RXFTHR_MODE_4X BIT(5) 54 55 #define F81216_LDN_LOW 0x0 56 #define F81216_LDN_HIGH 0x4 57 58 /* 59 * F81866 registers 60 * 61 * The IRQ setting mode of F81866 is not the same with F81216 series. 62 * Level/Low: IRQ_MODE0:0, IRQ_MODE1:0 63 * Edge/High: IRQ_MODE0:1, IRQ_MODE1:0 64 */ 65 #define F81866_IRQ_MODE 0xf0 66 #define F81866_IRQ_SHARE BIT(0) 67 #define F81866_IRQ_MODE0 BIT(1) 68 69 #define F81866_FIFO_CTRL FIFO_CTRL 70 #define F81866_IRQ_MODE1 BIT(3) 71 72 #define F81866_LDN_LOW 0x10 73 #define F81866_LDN_HIGH 0x16 74 75 struct fintek_8250 { 76 u16 pid; 77 u16 base_port; 78 u8 index; 79 u8 key; 80 }; 81 82 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg) 83 { 84 outb(reg, pdata->base_port + ADDR_PORT); 85 return inb(pdata->base_port + DATA_PORT); 86 } 87 88 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data) 89 { 90 outb(reg, pdata->base_port + ADDR_PORT); 91 outb(data, pdata->base_port + DATA_PORT); 92 } 93 94 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask, 95 u8 data) 96 { 97 u8 tmp; 98 99 tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data); 100 sio_write_reg(pdata, reg, tmp); 101 } 102 103 static int fintek_8250_enter_key(u16 base_port, u8 key) 104 { 105 if (!request_muxed_region(base_port, 2, "8250_fintek")) 106 return -EBUSY; 107 108 outb(key, base_port + ADDR_PORT); 109 outb(key, base_port + ADDR_PORT); 110 return 0; 111 } 112 113 static void fintek_8250_exit_key(u16 base_port) 114 { 115 116 outb(EXIT_KEY, base_port + ADDR_PORT); 117 release_region(base_port + ADDR_PORT, 2); 118 } 119 120 static int fintek_8250_check_id(struct fintek_8250 *pdata) 121 { 122 u16 chip; 123 124 if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL) 125 return -ENODEV; 126 127 if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL) 128 return -ENODEV; 129 130 chip = sio_read_reg(pdata, CHIP_ID1); 131 chip |= sio_read_reg(pdata, CHIP_ID2) << 8; 132 133 switch (chip) { 134 case CHIP_ID_F81865: 135 case CHIP_ID_F81866: 136 case CHIP_ID_F81216AD: 137 case CHIP_ID_F81216H: 138 case CHIP_ID_F81216: 139 break; 140 default: 141 return -ENODEV; 142 } 143 144 pdata->pid = chip; 145 return 0; 146 } 147 148 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min, 149 int *max) 150 { 151 switch (pdata->pid) { 152 case CHIP_ID_F81865: 153 case CHIP_ID_F81866: 154 *min = F81866_LDN_LOW; 155 *max = F81866_LDN_HIGH; 156 return 0; 157 158 case CHIP_ID_F81216AD: 159 case CHIP_ID_F81216H: 160 case CHIP_ID_F81216: 161 *min = F81216_LDN_LOW; 162 *max = F81216_LDN_HIGH; 163 return 0; 164 } 165 166 return -ENODEV; 167 } 168 169 static int fintek_8250_rs485_config(struct uart_port *port, 170 struct serial_rs485 *rs485) 171 { 172 uint8_t config = 0; 173 struct fintek_8250 *pdata = port->private_data; 174 175 if (!pdata) 176 return -EINVAL; 177 178 if (rs485->flags & SER_RS485_ENABLED) 179 memset(rs485->padding, 0, sizeof(rs485->padding)); 180 else 181 memset(rs485, 0, sizeof(*rs485)); 182 183 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | 184 SER_RS485_RTS_AFTER_SEND; 185 186 if (rs485->delay_rts_before_send) { 187 rs485->delay_rts_before_send = 1; 188 config |= TXW4C_IRA; 189 } 190 191 if (rs485->delay_rts_after_send) { 192 rs485->delay_rts_after_send = 1; 193 config |= RXW4C_IRA; 194 } 195 196 if ((!!(rs485->flags & SER_RS485_RTS_ON_SEND)) == 197 (!!(rs485->flags & SER_RS485_RTS_AFTER_SEND))) 198 rs485->flags &= SER_RS485_ENABLED; 199 else 200 config |= RS485_URA; 201 202 if (rs485->flags & SER_RS485_RTS_ON_SEND) 203 config |= RTS_INVERT; 204 205 if (fintek_8250_enter_key(pdata->base_port, pdata->key)) 206 return -EBUSY; 207 208 sio_write_reg(pdata, LDN, pdata->index); 209 sio_write_reg(pdata, RS485, config); 210 fintek_8250_exit_key(pdata->base_port); 211 212 port->rs485 = *rs485; 213 214 return 0; 215 } 216 217 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level) 218 { 219 sio_write_reg(pdata, LDN, pdata->index); 220 221 switch (pdata->pid) { 222 case CHIP_ID_F81866: 223 sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1, 224 0); 225 /* fall through */ 226 case CHIP_ID_F81865: 227 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE, 228 F81866_IRQ_SHARE); 229 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0, 230 is_level ? 0 : F81866_IRQ_MODE0); 231 break; 232 233 case CHIP_ID_F81216AD: 234 case CHIP_ID_F81216H: 235 case CHIP_ID_F81216: 236 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE, 237 IRQ_SHARE); 238 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK, 239 is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH); 240 break; 241 } 242 } 243 244 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata) 245 { 246 switch (pdata->pid) { 247 case CHIP_ID_F81216H: /* 128Bytes FIFO */ 248 case CHIP_ID_F81866: 249 sio_write_mask_reg(pdata, FIFO_CTRL, 250 FIFO_MODE_MASK | RXFTHR_MODE_MASK, 251 FIFO_MODE_128 | RXFTHR_MODE_4X); 252 break; 253 254 default: /* Default 16Bytes FIFO */ 255 break; 256 } 257 } 258 259 static int probe_setup_port(struct fintek_8250 *pdata, u16 io_address, 260 unsigned int irq) 261 { 262 static const u16 addr[] = {0x4e, 0x2e}; 263 static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67}; 264 struct irq_data *irq_data; 265 bool level_mode = false; 266 int i, j, k, min, max; 267 268 for (i = 0; i < ARRAY_SIZE(addr); i++) { 269 for (j = 0; j < ARRAY_SIZE(keys); j++) { 270 pdata->base_port = addr[i]; 271 pdata->key = keys[j]; 272 273 if (fintek_8250_enter_key(addr[i], keys[j])) 274 continue; 275 if (fintek_8250_check_id(pdata) || 276 fintek_8250_get_ldn_range(pdata, &min, &max)) { 277 fintek_8250_exit_key(addr[i]); 278 continue; 279 } 280 281 for (k = min; k < max; k++) { 282 u16 aux; 283 284 sio_write_reg(pdata, LDN, k); 285 aux = sio_read_reg(pdata, IO_ADDR1); 286 aux |= sio_read_reg(pdata, IO_ADDR2) << 8; 287 if (aux != io_address) 288 continue; 289 290 pdata->index = k; 291 292 irq_data = irq_get_irq_data(irq); 293 if (irq_data) 294 level_mode = 295 irqd_is_level_type(irq_data); 296 297 fintek_8250_set_irq_mode(pdata, level_mode); 298 fintek_8250_set_max_fifo(pdata); 299 fintek_8250_exit_key(addr[i]); 300 301 return 0; 302 } 303 304 fintek_8250_exit_key(addr[i]); 305 } 306 } 307 308 return -ENODEV; 309 } 310 311 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart) 312 { 313 struct fintek_8250 *pdata = uart->port.private_data; 314 315 switch (pdata->pid) { 316 case CHIP_ID_F81216AD: 317 case CHIP_ID_F81216H: 318 case CHIP_ID_F81866: 319 case CHIP_ID_F81865: 320 uart->port.rs485_config = fintek_8250_rs485_config; 321 break; 322 323 default: /* No RS485 Auto direction functional */ 324 break; 325 } 326 } 327 328 int fintek_8250_probe(struct uart_8250_port *uart) 329 { 330 struct fintek_8250 *pdata; 331 struct fintek_8250 probe_data; 332 333 if (probe_setup_port(&probe_data, uart->port.iobase, uart->port.irq)) 334 return -ENODEV; 335 336 pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL); 337 if (!pdata) 338 return -ENOMEM; 339 340 memcpy(pdata, &probe_data, sizeof(probe_data)); 341 uart->port.private_data = pdata; 342 fintek_8250_set_rs485_handler(uart); 343 344 return 0; 345 } 346