1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type Exar chips PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. 8 */ 9 #include <linux/acpi.h> 10 #include <linux/dmi.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/property.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial_reg.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/tty.h> 21 #include <linux/8250_pci.h> 22 #include <linux/delay.h> 23 24 #include <asm/byteorder.h> 25 26 #include "8250.h" 27 28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d 30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c 31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db 34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea 35 36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 43 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 44 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 45 46 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 47 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 48 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004 49 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008 50 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010 51 52 #define UART_EXAR_INT0 0x80 53 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 54 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ 55 #define UART_EXAR_DVID 0x8d /* Device identification */ 56 57 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 58 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ 59 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ 60 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 61 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 62 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 63 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 64 65 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 66 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 67 68 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 69 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 70 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 71 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 72 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 73 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 74 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 75 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 76 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 77 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 78 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 79 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 80 81 #define UART_EXAR_RS485_DLY(x) ((x) << 4) 82 83 /* 84 * IOT2040 MPIO wiring semantics: 85 * 86 * MPIO Port Function 87 * ---- ---- -------- 88 * 0 2 Mode bit 0 89 * 1 2 Mode bit 1 90 * 2 2 Terminate bus 91 * 3 - <reserved> 92 * 4 3 Mode bit 0 93 * 5 3 Mode bit 1 94 * 6 3 Terminate bus 95 * 7 - <reserved> 96 * 8 2 Enable 97 * 9 3 Enable 98 * 10 - Red LED 99 * 11..15 - <unused> 100 */ 101 102 /* IOT2040 MPIOs 0..7 */ 103 #define IOT2040_UART_MODE_RS232 0x01 104 #define IOT2040_UART_MODE_RS485 0x02 105 #define IOT2040_UART_MODE_RS422 0x03 106 #define IOT2040_UART_TERMINATE_BUS 0x04 107 108 #define IOT2040_UART1_MASK 0x0f 109 #define IOT2040_UART2_SHIFT 4 110 111 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ 112 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ 113 114 /* IOT2040 MPIOs 8..15 */ 115 #define IOT2040_UARTS_ENABLE 0x03 116 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ 117 118 struct exar8250; 119 120 struct exar8250_platform { 121 int (*rs485_config)(struct uart_port *port, struct ktermios *termios, 122 struct serial_rs485 *rs485); 123 const struct serial_rs485 *rs485_supported; 124 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); 125 void (*unregister_gpio)(struct uart_8250_port *); 126 }; 127 128 /** 129 * struct exar8250_board - board information 130 * @num_ports: number of serial ports 131 * @reg_shift: describes UART register mapping in PCI memory 132 * @setup: quirk run at ->probe() stage 133 * @exit: quirk run at ->remove() stage 134 */ 135 struct exar8250_board { 136 unsigned int num_ports; 137 unsigned int reg_shift; 138 int (*setup)(struct exar8250 *, struct pci_dev *, 139 struct uart_8250_port *, int); 140 void (*exit)(struct pci_dev *pcidev); 141 }; 142 143 struct exar8250 { 144 unsigned int nr; 145 struct exar8250_board *board; 146 void __iomem *virt; 147 int line[]; 148 }; 149 150 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) 151 { 152 /* 153 * Exar UARTs have a SLEEP register that enables or disables each UART 154 * to enter sleep mode separately. On the XR17V35x the register 155 * is accessible to each UART at the UART_EXAR_SLEEP offset, but 156 * the UART channel may only write to the corresponding bit. 157 */ 158 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0); 159 } 160 161 /* 162 * XR17V35x UARTs have an extra fractional divisor register (DLD) 163 * Calculate divisor with extra 4-bit fractional portion 164 */ 165 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, 166 unsigned int *frac) 167 { 168 unsigned int quot_16; 169 170 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); 171 *frac = quot_16 & 0x0f; 172 173 return quot_16 >> 4; 174 } 175 176 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, 177 unsigned int quot, unsigned int quot_frac) 178 { 179 serial8250_do_set_divisor(p, baud, quot, quot_frac); 180 181 /* Preserve bits not related to baudrate; DLD[7:4]. */ 182 quot_frac |= serial_port_in(p, 0x2) & 0xf0; 183 serial_port_out(p, 0x2, quot_frac); 184 } 185 186 static int xr17v35x_startup(struct uart_port *port) 187 { 188 /* 189 * First enable access to IER [7:5], ISR [5:4], FCR [5:4], 190 * MCR [7:5] and MSR [7:0] 191 */ 192 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); 193 194 /* 195 * Make sure all interrups are masked until initialization is 196 * complete and the FIFOs are cleared 197 */ 198 serial_port_out(port, UART_IER, 0); 199 200 return serial8250_do_startup(port); 201 } 202 203 static void exar_shutdown(struct uart_port *port) 204 { 205 bool tx_complete = false; 206 struct uart_8250_port *up = up_to_u8250p(port); 207 struct circ_buf *xmit = &port->state->xmit; 208 int i = 0; 209 u16 lsr; 210 211 do { 212 lsr = serial_in(up, UART_LSR); 213 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE)) 214 tx_complete = true; 215 else 216 tx_complete = false; 217 usleep_range(1000, 1100); 218 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000); 219 220 serial8250_do_shutdown(port); 221 } 222 223 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, 224 int idx, unsigned int offset, 225 struct uart_8250_port *port) 226 { 227 const struct exar8250_board *board = priv->board; 228 unsigned int bar = 0; 229 unsigned char status; 230 231 port->port.iotype = UPIO_MEM; 232 port->port.mapbase = pci_resource_start(pcidev, bar) + offset; 233 port->port.membase = priv->virt + offset; 234 port->port.regshift = board->reg_shift; 235 236 /* 237 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled 238 * with when DLAB is set which will cause the device to incorrectly match 239 * and assign port type to PORT_16650. The EFR for this UART is found 240 * at offset 0x09. Instead check the Deice ID (DVID) register 241 * for a 2, 4 or 8 port UART. 242 */ 243 status = readb(port->port.membase + UART_EXAR_DVID); 244 if (status == 0x82 || status == 0x84 || status == 0x88) { 245 port->port.type = PORT_XR17V35X; 246 247 port->port.get_divisor = xr17v35x_get_divisor; 248 port->port.set_divisor = xr17v35x_set_divisor; 249 250 port->port.startup = xr17v35x_startup; 251 } else { 252 port->port.type = PORT_XR17D15X; 253 } 254 255 port->port.pm = exar_pm; 256 port->port.shutdown = exar_shutdown; 257 258 return 0; 259 } 260 261 static int 262 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, 263 struct uart_8250_port *port, int idx) 264 { 265 unsigned int offset = idx * 0x200; 266 unsigned int baud = 1843200; 267 u8 __iomem *p; 268 int err; 269 270 port->port.uartclk = baud * 16; 271 272 err = default_setup(priv, pcidev, idx, offset, port); 273 if (err) 274 return err; 275 276 p = port->port.membase; 277 278 writeb(0x00, p + UART_EXAR_8XMODE); 279 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 280 writeb(32, p + UART_EXAR_TXTRG); 281 writeb(32, p + UART_EXAR_RXTRG); 282 283 /* 284 * Setup Multipurpose Input/Output pins. 285 */ 286 if (idx == 0) { 287 switch (pcidev->device) { 288 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 289 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 290 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 291 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 292 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 293 break; 294 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 295 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 296 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 297 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 298 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 299 break; 300 } 301 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 302 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 303 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 304 } 305 306 return 0; 307 } 308 309 static int 310 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, 311 struct uart_8250_port *port, int idx) 312 { 313 unsigned int offset = idx * 0x200; 314 unsigned int baud = 1843200; 315 316 port->port.uartclk = baud * 16; 317 return default_setup(priv, pcidev, idx, offset, port); 318 } 319 320 static int 321 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, 322 struct uart_8250_port *port, int idx) 323 { 324 unsigned int offset = idx * 0x200; 325 unsigned int baud = 921600; 326 327 port->port.uartclk = baud * 16; 328 return default_setup(priv, pcidev, idx, offset, port); 329 } 330 331 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) 332 { 333 /* 334 * The Commtech adapters required the MPIOs to be driven low. The Exar 335 * devices will export them as GPIOs, so we pre-configure them safely 336 * as inputs. 337 */ 338 339 u8 dir = 0x00; 340 341 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && 342 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { 343 // Configure GPIO as inputs for Commtech adapters 344 dir = 0xff; 345 } else { 346 // Configure GPIO as outputs for SeaLevel adapters 347 dir = 0x00; 348 } 349 350 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 351 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 352 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 353 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 354 writeb(dir, p + UART_EXAR_MPIOSEL_7_0); 355 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 356 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 357 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 358 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 359 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 360 writeb(dir, p + UART_EXAR_MPIOSEL_15_8); 361 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 362 } 363 364 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev, 365 const struct software_node *node) 366 { 367 struct platform_device *pdev; 368 369 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); 370 if (!pdev) 371 return NULL; 372 373 pdev->dev.parent = &pcidev->dev; 374 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); 375 376 if (device_add_software_node(&pdev->dev, node) < 0 || 377 platform_device_add(pdev) < 0) { 378 platform_device_put(pdev); 379 return NULL; 380 } 381 382 return pdev; 383 } 384 385 static void __xr17v35x_unregister_gpio(struct platform_device *pdev) 386 { 387 device_remove_software_node(&pdev->dev); 388 platform_device_unregister(pdev); 389 } 390 391 static const struct property_entry exar_gpio_properties[] = { 392 PROPERTY_ENTRY_U32("exar,first-pin", 0), 393 PROPERTY_ENTRY_U32("ngpios", 16), 394 { } 395 }; 396 397 static const struct software_node exar_gpio_node = { 398 .properties = exar_gpio_properties, 399 }; 400 401 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port) 402 { 403 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) 404 port->port.private_data = 405 __xr17v35x_register_gpio(pcidev, &exar_gpio_node); 406 407 return 0; 408 } 409 410 static void xr17v35x_unregister_gpio(struct uart_8250_port *port) 411 { 412 if (!port->port.private_data) 413 return; 414 415 __xr17v35x_unregister_gpio(port->port.private_data); 416 port->port.private_data = NULL; 417 } 418 419 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios, 420 struct serial_rs485 *rs485) 421 { 422 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 423 u8 __iomem *p = port->membase; 424 u8 value; 425 426 value = readb(p + UART_EXAR_FCTR); 427 if (is_rs485) 428 value |= UART_FCTR_EXAR_485; 429 else 430 value &= ~UART_FCTR_EXAR_485; 431 432 writeb(value, p + UART_EXAR_FCTR); 433 434 if (is_rs485) 435 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); 436 437 return 0; 438 } 439 440 static const struct serial_rs485 generic_rs485_supported = { 441 .flags = SER_RS485_ENABLED, 442 }; 443 444 static const struct exar8250_platform exar8250_default_platform = { 445 .register_gpio = xr17v35x_register_gpio, 446 .unregister_gpio = xr17v35x_unregister_gpio, 447 .rs485_config = generic_rs485_config, 448 .rs485_supported = &generic_rs485_supported, 449 }; 450 451 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios, 452 struct serial_rs485 *rs485) 453 { 454 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 455 u8 __iomem *p = port->membase; 456 u8 mask = IOT2040_UART1_MASK; 457 u8 mode, value; 458 459 if (is_rs485) { 460 if (rs485->flags & SER_RS485_RX_DURING_TX) 461 mode = IOT2040_UART_MODE_RS422; 462 else 463 mode = IOT2040_UART_MODE_RS485; 464 465 if (rs485->flags & SER_RS485_TERMINATE_BUS) 466 mode |= IOT2040_UART_TERMINATE_BUS; 467 } else { 468 mode = IOT2040_UART_MODE_RS232; 469 } 470 471 if (port->line == 3) { 472 mask <<= IOT2040_UART2_SHIFT; 473 mode <<= IOT2040_UART2_SHIFT; 474 } 475 476 value = readb(p + UART_EXAR_MPIOLVL_7_0); 477 value &= ~mask; 478 value |= mode; 479 writeb(value, p + UART_EXAR_MPIOLVL_7_0); 480 481 return generic_rs485_config(port, termios, rs485); 482 } 483 484 static const struct serial_rs485 iot2040_rs485_supported = { 485 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS, 486 }; 487 488 static const struct property_entry iot2040_gpio_properties[] = { 489 PROPERTY_ENTRY_U32("exar,first-pin", 10), 490 PROPERTY_ENTRY_U32("ngpios", 1), 491 { } 492 }; 493 494 static const struct software_node iot2040_gpio_node = { 495 .properties = iot2040_gpio_properties, 496 }; 497 498 static int iot2040_register_gpio(struct pci_dev *pcidev, 499 struct uart_8250_port *port) 500 { 501 u8 __iomem *p = port->port.membase; 502 503 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); 504 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); 505 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); 506 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); 507 508 port->port.private_data = 509 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node); 510 511 return 0; 512 } 513 514 static const struct exar8250_platform iot2040_platform = { 515 .rs485_config = iot2040_rs485_config, 516 .rs485_supported = &iot2040_rs485_supported, 517 .register_gpio = iot2040_register_gpio, 518 .unregister_gpio = xr17v35x_unregister_gpio, 519 }; 520 521 /* 522 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device, 523 * IOT2020 doesn't have. Therefore it is sufficient to match on the common 524 * board name after the device was found. 525 */ 526 static const struct dmi_system_id exar_platforms[] = { 527 { 528 .matches = { 529 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 530 }, 531 .driver_data = (void *)&iot2040_platform, 532 }, 533 {} 534 }; 535 536 static const struct exar8250_platform *exar_get_platform(void) 537 { 538 const struct dmi_system_id *dmi_match; 539 540 dmi_match = dmi_first_match(exar_platforms); 541 if (dmi_match) 542 return dmi_match->driver_data; 543 544 return &exar8250_default_platform; 545 } 546 547 static int 548 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, 549 struct uart_8250_port *port, int idx) 550 { 551 const struct exar8250_platform *platform = exar_get_platform(); 552 unsigned int offset = idx * 0x400; 553 unsigned int baud = 7812500; 554 u8 __iomem *p; 555 int ret; 556 557 port->port.uartclk = baud * 16; 558 port->port.rs485_config = platform->rs485_config; 559 port->port.rs485_supported = *(platform->rs485_supported); 560 561 /* 562 * Setup the UART clock for the devices on expansion slot to 563 * half the clock speed of the main chip (which is 125MHz) 564 */ 565 if (idx >= 8) 566 port->port.uartclk /= 2; 567 568 ret = default_setup(priv, pcidev, idx, offset, port); 569 if (ret) 570 return ret; 571 572 p = port->port.membase; 573 574 writeb(0x00, p + UART_EXAR_8XMODE); 575 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 576 writeb(128, p + UART_EXAR_TXTRG); 577 writeb(128, p + UART_EXAR_RXTRG); 578 579 if (idx == 0) { 580 /* Setup Multipurpose Input/Output pins. */ 581 setup_gpio(pcidev, p); 582 583 ret = platform->register_gpio(pcidev, port); 584 } 585 586 return ret; 587 } 588 589 static void pci_xr17v35x_exit(struct pci_dev *pcidev) 590 { 591 const struct exar8250_platform *platform = exar_get_platform(); 592 struct exar8250 *priv = pci_get_drvdata(pcidev); 593 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); 594 595 platform->unregister_gpio(port); 596 } 597 598 static inline void exar_misc_clear(struct exar8250 *priv) 599 { 600 /* Clear all PCI interrupts by reading INT0. No effect on IIR */ 601 readb(priv->virt + UART_EXAR_INT0); 602 603 /* Clear INT0 for Expansion Interface slave ports, too */ 604 if (priv->board->num_ports > 8) 605 readb(priv->virt + 0x2000 + UART_EXAR_INT0); 606 } 607 608 /* 609 * These Exar UARTs have an extra interrupt indicator that could fire for a 610 * few interrupts that are not presented/cleared through IIR. One of which is 611 * a wakeup interrupt when coming out of sleep. These interrupts are only 612 * cleared by reading global INT0 or INT1 registers as interrupts are 613 * associated with channel 0. The INT[3:0] registers _are_ accessible from each 614 * channel's address space, but for the sake of bus efficiency we register a 615 * dedicated handler at the PCI device level to handle them. 616 */ 617 static irqreturn_t exar_misc_handler(int irq, void *data) 618 { 619 exar_misc_clear(data); 620 621 return IRQ_HANDLED; 622 } 623 624 static int 625 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 626 { 627 unsigned int nr_ports, i, bar = 0, maxnr; 628 struct exar8250_board *board; 629 struct uart_8250_port uart; 630 struct exar8250 *priv; 631 int rc; 632 633 board = (struct exar8250_board *)ent->driver_data; 634 if (!board) 635 return -EINVAL; 636 637 rc = pcim_enable_device(pcidev); 638 if (rc) 639 return rc; 640 641 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 642 643 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) 644 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); 645 else if (board->num_ports) 646 nr_ports = board->num_ports; 647 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL) 648 nr_ports = pcidev->device & 0xff; 649 else 650 nr_ports = pcidev->device & 0x0f; 651 652 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 653 if (!priv) 654 return -ENOMEM; 655 656 priv->board = board; 657 priv->virt = pcim_iomap(pcidev, bar, 0); 658 if (!priv->virt) 659 return -ENOMEM; 660 661 pci_set_master(pcidev); 662 663 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); 664 if (rc < 0) 665 return rc; 666 667 memset(&uart, 0, sizeof(uart)); 668 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT; 669 uart.port.irq = pci_irq_vector(pcidev, 0); 670 uart.port.dev = &pcidev->dev; 671 672 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, 673 IRQF_SHARED, "exar_uart", priv); 674 if (rc) 675 return rc; 676 677 /* Clear interrupts */ 678 exar_misc_clear(priv); 679 680 for (i = 0; i < nr_ports && i < maxnr; i++) { 681 rc = board->setup(priv, pcidev, &uart, i); 682 if (rc) { 683 dev_err(&pcidev->dev, "Failed to setup port %u\n", i); 684 break; 685 } 686 687 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 688 uart.port.iobase, uart.port.irq, uart.port.iotype); 689 690 priv->line[i] = serial8250_register_8250_port(&uart); 691 if (priv->line[i] < 0) { 692 dev_err(&pcidev->dev, 693 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 694 uart.port.iobase, uart.port.irq, 695 uart.port.iotype, priv->line[i]); 696 break; 697 } 698 } 699 priv->nr = i; 700 pci_set_drvdata(pcidev, priv); 701 return 0; 702 } 703 704 static void exar_pci_remove(struct pci_dev *pcidev) 705 { 706 struct exar8250 *priv = pci_get_drvdata(pcidev); 707 unsigned int i; 708 709 for (i = 0; i < priv->nr; i++) 710 serial8250_unregister_port(priv->line[i]); 711 712 if (priv->board->exit) 713 priv->board->exit(pcidev); 714 } 715 716 static int __maybe_unused exar_suspend(struct device *dev) 717 { 718 struct pci_dev *pcidev = to_pci_dev(dev); 719 struct exar8250 *priv = pci_get_drvdata(pcidev); 720 unsigned int i; 721 722 for (i = 0; i < priv->nr; i++) 723 if (priv->line[i] >= 0) 724 serial8250_suspend_port(priv->line[i]); 725 726 /* Ensure that every init quirk is properly torn down */ 727 if (priv->board->exit) 728 priv->board->exit(pcidev); 729 730 return 0; 731 } 732 733 static int __maybe_unused exar_resume(struct device *dev) 734 { 735 struct exar8250 *priv = dev_get_drvdata(dev); 736 unsigned int i; 737 738 exar_misc_clear(priv); 739 740 for (i = 0; i < priv->nr; i++) 741 if (priv->line[i] >= 0) 742 serial8250_resume_port(priv->line[i]); 743 744 return 0; 745 } 746 747 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); 748 749 static const struct exar8250_board pbn_fastcom335_2 = { 750 .num_ports = 2, 751 .setup = pci_fastcom335_setup, 752 }; 753 754 static const struct exar8250_board pbn_fastcom335_4 = { 755 .num_ports = 4, 756 .setup = pci_fastcom335_setup, 757 }; 758 759 static const struct exar8250_board pbn_fastcom335_8 = { 760 .num_ports = 8, 761 .setup = pci_fastcom335_setup, 762 }; 763 764 static const struct exar8250_board pbn_connect = { 765 .setup = pci_connect_tech_setup, 766 }; 767 768 static const struct exar8250_board pbn_exar_ibm_saturn = { 769 .num_ports = 1, 770 .setup = pci_xr17c154_setup, 771 }; 772 773 static const struct exar8250_board pbn_exar_XR17C15x = { 774 .setup = pci_xr17c154_setup, 775 }; 776 777 static const struct exar8250_board pbn_exar_XR17V35x = { 778 .setup = pci_xr17v35x_setup, 779 .exit = pci_xr17v35x_exit, 780 }; 781 782 static const struct exar8250_board pbn_fastcom35x_2 = { 783 .num_ports = 2, 784 .setup = pci_xr17v35x_setup, 785 .exit = pci_xr17v35x_exit, 786 }; 787 788 static const struct exar8250_board pbn_fastcom35x_4 = { 789 .num_ports = 4, 790 .setup = pci_xr17v35x_setup, 791 .exit = pci_xr17v35x_exit, 792 }; 793 794 static const struct exar8250_board pbn_fastcom35x_8 = { 795 .num_ports = 8, 796 .setup = pci_xr17v35x_setup, 797 .exit = pci_xr17v35x_exit, 798 }; 799 800 static const struct exar8250_board pbn_exar_XR17V4358 = { 801 .num_ports = 12, 802 .setup = pci_xr17v35x_setup, 803 .exit = pci_xr17v35x_exit, 804 }; 805 806 static const struct exar8250_board pbn_exar_XR17V8358 = { 807 .num_ports = 16, 808 .setup = pci_xr17v35x_setup, 809 .exit = pci_xr17v35x_exit, 810 }; 811 812 #define CONNECT_DEVICE(devid, sdevid, bd) { \ 813 PCI_DEVICE_SUB( \ 814 PCI_VENDOR_ID_EXAR, \ 815 PCI_DEVICE_ID_EXAR_##devid, \ 816 PCI_SUBVENDOR_ID_CONNECT_TECH, \ 817 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ 818 (kernel_ulong_t)&bd \ 819 } 820 821 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } 822 823 #define IBM_DEVICE(devid, sdevid, bd) { \ 824 PCI_DEVICE_SUB( \ 825 PCI_VENDOR_ID_EXAR, \ 826 PCI_DEVICE_ID_EXAR_##devid, \ 827 PCI_VENDOR_ID_IBM, \ 828 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ 829 (kernel_ulong_t)&bd \ 830 } 831 832 static const struct pci_device_id exar_pci_tbl[] = { 833 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x), 834 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x), 835 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x), 836 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x), 837 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x), 838 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), 839 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), 840 841 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), 842 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), 843 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), 844 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), 845 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), 846 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), 847 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), 848 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), 849 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), 850 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), 851 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), 852 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 853 854 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 855 856 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 857 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), 858 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), 859 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), 860 861 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ 862 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), 863 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), 864 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), 865 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), 866 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), 867 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2), 868 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4), 869 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8), 870 871 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), 872 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), 873 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), 874 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), 875 876 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x), 877 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x), 878 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x), 879 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x), 880 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x), 881 { 0, } 882 }; 883 MODULE_DEVICE_TABLE(pci, exar_pci_tbl); 884 885 static struct pci_driver exar_pci_driver = { 886 .name = "exar_serial", 887 .probe = exar_pci_probe, 888 .remove = exar_pci_remove, 889 .driver = { 890 .pm = &exar_pci_pm, 891 }, 892 .id_table = exar_pci_tbl, 893 }; 894 module_pci_driver(exar_pci_driver); 895 896 MODULE_LICENSE("GPL"); 897 MODULE_DESCRIPTION("Exar Serial Driver"); 898 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 899