1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type Exar chips PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. 8 */ 9 #include <linux/acpi.h> 10 #include <linux/dmi.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/property.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial_reg.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/tty.h> 21 #include <linux/8250_pci.h> 22 #include <linux/delay.h> 23 24 #include <asm/byteorder.h> 25 26 #include "8250.h" 27 28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S 0x1052 29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S 0x105d 30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S 0x106c 31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8 0x10a8 32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM 0x10d2 33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM 0x10db 34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM 0x10ea 35 36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 43 44 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 45 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 46 47 #define PCI_SUBDEVICE_ID_USR_2980 0x0128 48 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 49 50 #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 51 #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 52 #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004 53 #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008 54 #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010 55 56 #define UART_EXAR_INT0 0x80 57 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 58 #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ 59 #define UART_EXAR_DVID 0x8d /* Device identification */ 60 61 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 62 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ 63 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ 64 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 65 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 66 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 67 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 68 69 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 70 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 71 72 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 73 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 74 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 75 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 76 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 77 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 78 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 79 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 80 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 81 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 82 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 83 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 84 85 #define UART_EXAR_RS485_DLY(x) ((x) << 4) 86 87 /* 88 * IOT2040 MPIO wiring semantics: 89 * 90 * MPIO Port Function 91 * ---- ---- -------- 92 * 0 2 Mode bit 0 93 * 1 2 Mode bit 1 94 * 2 2 Terminate bus 95 * 3 - <reserved> 96 * 4 3 Mode bit 0 97 * 5 3 Mode bit 1 98 * 6 3 Terminate bus 99 * 7 - <reserved> 100 * 8 2 Enable 101 * 9 3 Enable 102 * 10 - Red LED 103 * 11..15 - <unused> 104 */ 105 106 /* IOT2040 MPIOs 0..7 */ 107 #define IOT2040_UART_MODE_RS232 0x01 108 #define IOT2040_UART_MODE_RS485 0x02 109 #define IOT2040_UART_MODE_RS422 0x03 110 #define IOT2040_UART_TERMINATE_BUS 0x04 111 112 #define IOT2040_UART1_MASK 0x0f 113 #define IOT2040_UART2_SHIFT 4 114 115 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ 116 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ 117 118 /* IOT2040 MPIOs 8..15 */ 119 #define IOT2040_UARTS_ENABLE 0x03 120 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ 121 122 struct exar8250; 123 124 struct exar8250_platform { 125 int (*rs485_config)(struct uart_port *port, struct ktermios *termios, 126 struct serial_rs485 *rs485); 127 const struct serial_rs485 *rs485_supported; 128 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); 129 void (*unregister_gpio)(struct uart_8250_port *); 130 }; 131 132 /** 133 * struct exar8250_board - board information 134 * @num_ports: number of serial ports 135 * @reg_shift: describes UART register mapping in PCI memory 136 * @setup: quirk run at ->probe() stage 137 * @exit: quirk run at ->remove() stage 138 */ 139 struct exar8250_board { 140 unsigned int num_ports; 141 unsigned int reg_shift; 142 int (*setup)(struct exar8250 *, struct pci_dev *, 143 struct uart_8250_port *, int); 144 void (*exit)(struct pci_dev *pcidev); 145 }; 146 147 struct exar8250 { 148 unsigned int nr; 149 struct exar8250_board *board; 150 void __iomem *virt; 151 int line[]; 152 }; 153 154 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old) 155 { 156 /* 157 * Exar UARTs have a SLEEP register that enables or disables each UART 158 * to enter sleep mode separately. On the XR17V35x the register 159 * is accessible to each UART at the UART_EXAR_SLEEP offset, but 160 * the UART channel may only write to the corresponding bit. 161 */ 162 serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0); 163 } 164 165 /* 166 * XR17V35x UARTs have an extra fractional divisor register (DLD) 167 * Calculate divisor with extra 4-bit fractional portion 168 */ 169 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud, 170 unsigned int *frac) 171 { 172 unsigned int quot_16; 173 174 quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud); 175 *frac = quot_16 & 0x0f; 176 177 return quot_16 >> 4; 178 } 179 180 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud, 181 unsigned int quot, unsigned int quot_frac) 182 { 183 serial8250_do_set_divisor(p, baud, quot, quot_frac); 184 185 /* Preserve bits not related to baudrate; DLD[7:4]. */ 186 quot_frac |= serial_port_in(p, 0x2) & 0xf0; 187 serial_port_out(p, 0x2, quot_frac); 188 } 189 190 static int xr17v35x_startup(struct uart_port *port) 191 { 192 /* 193 * First enable access to IER [7:5], ISR [5:4], FCR [5:4], 194 * MCR [7:5] and MSR [7:0] 195 */ 196 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); 197 198 /* 199 * Make sure all interrups are masked until initialization is 200 * complete and the FIFOs are cleared 201 */ 202 serial_port_out(port, UART_IER, 0); 203 204 return serial8250_do_startup(port); 205 } 206 207 static void exar_shutdown(struct uart_port *port) 208 { 209 bool tx_complete = false; 210 struct uart_8250_port *up = up_to_u8250p(port); 211 struct circ_buf *xmit = &port->state->xmit; 212 int i = 0; 213 u16 lsr; 214 215 do { 216 lsr = serial_in(up, UART_LSR); 217 if (lsr & (UART_LSR_TEMT | UART_LSR_THRE)) 218 tx_complete = true; 219 else 220 tx_complete = false; 221 usleep_range(1000, 1100); 222 } while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000); 223 224 serial8250_do_shutdown(port); 225 } 226 227 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, 228 int idx, unsigned int offset, 229 struct uart_8250_port *port) 230 { 231 const struct exar8250_board *board = priv->board; 232 unsigned int bar = 0; 233 unsigned char status; 234 235 port->port.iotype = UPIO_MEM; 236 port->port.mapbase = pci_resource_start(pcidev, bar) + offset; 237 port->port.membase = priv->virt + offset; 238 port->port.regshift = board->reg_shift; 239 240 /* 241 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled 242 * with when DLAB is set which will cause the device to incorrectly match 243 * and assign port type to PORT_16650. The EFR for this UART is found 244 * at offset 0x09. Instead check the Deice ID (DVID) register 245 * for a 2, 4 or 8 port UART. 246 */ 247 status = readb(port->port.membase + UART_EXAR_DVID); 248 if (status == 0x82 || status == 0x84 || status == 0x88) { 249 port->port.type = PORT_XR17V35X; 250 251 port->port.get_divisor = xr17v35x_get_divisor; 252 port->port.set_divisor = xr17v35x_set_divisor; 253 254 port->port.startup = xr17v35x_startup; 255 } else { 256 port->port.type = PORT_XR17D15X; 257 } 258 259 port->port.pm = exar_pm; 260 port->port.shutdown = exar_shutdown; 261 262 return 0; 263 } 264 265 static int 266 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, 267 struct uart_8250_port *port, int idx) 268 { 269 unsigned int offset = idx * 0x200; 270 unsigned int baud = 1843200; 271 u8 __iomem *p; 272 int err; 273 274 port->port.uartclk = baud * 16; 275 276 err = default_setup(priv, pcidev, idx, offset, port); 277 if (err) 278 return err; 279 280 p = port->port.membase; 281 282 writeb(0x00, p + UART_EXAR_8XMODE); 283 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 284 writeb(32, p + UART_EXAR_TXTRG); 285 writeb(32, p + UART_EXAR_RXTRG); 286 287 /* 288 * Setup Multipurpose Input/Output pins. 289 */ 290 if (idx == 0) { 291 switch (pcidev->device) { 292 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 293 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 294 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 295 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 296 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 297 break; 298 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 299 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 300 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 301 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 302 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 303 break; 304 } 305 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 306 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 307 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 308 } 309 310 return 0; 311 } 312 313 static int 314 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, 315 struct uart_8250_port *port, int idx) 316 { 317 unsigned int offset = idx * 0x200; 318 unsigned int baud = 1843200; 319 320 port->port.uartclk = baud * 16; 321 return default_setup(priv, pcidev, idx, offset, port); 322 } 323 324 static int 325 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, 326 struct uart_8250_port *port, int idx) 327 { 328 unsigned int offset = idx * 0x200; 329 unsigned int baud = 921600; 330 331 port->port.uartclk = baud * 16; 332 return default_setup(priv, pcidev, idx, offset, port); 333 } 334 335 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) 336 { 337 /* 338 * The Commtech adapters required the MPIOs to be driven low. The Exar 339 * devices will export them as GPIOs, so we pre-configure them safely 340 * as inputs. 341 */ 342 343 u8 dir = 0x00; 344 345 if ((pcidev->vendor == PCI_VENDOR_ID_EXAR) && 346 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) { 347 // Configure GPIO as inputs for Commtech adapters 348 dir = 0xff; 349 } else { 350 // Configure GPIO as outputs for SeaLevel adapters 351 dir = 0x00; 352 } 353 354 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 355 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 356 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 357 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 358 writeb(dir, p + UART_EXAR_MPIOSEL_7_0); 359 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 360 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 361 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 362 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 363 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 364 writeb(dir, p + UART_EXAR_MPIOSEL_15_8); 365 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 366 } 367 368 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev, 369 const struct software_node *node) 370 { 371 struct platform_device *pdev; 372 373 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); 374 if (!pdev) 375 return NULL; 376 377 pdev->dev.parent = &pcidev->dev; 378 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); 379 380 if (device_add_software_node(&pdev->dev, node) < 0 || 381 platform_device_add(pdev) < 0) { 382 platform_device_put(pdev); 383 return NULL; 384 } 385 386 return pdev; 387 } 388 389 static void __xr17v35x_unregister_gpio(struct platform_device *pdev) 390 { 391 device_remove_software_node(&pdev->dev); 392 platform_device_unregister(pdev); 393 } 394 395 static const struct property_entry exar_gpio_properties[] = { 396 PROPERTY_ENTRY_U32("exar,first-pin", 0), 397 PROPERTY_ENTRY_U32("ngpios", 16), 398 { } 399 }; 400 401 static const struct software_node exar_gpio_node = { 402 .properties = exar_gpio_properties, 403 }; 404 405 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port) 406 { 407 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) 408 port->port.private_data = 409 __xr17v35x_register_gpio(pcidev, &exar_gpio_node); 410 411 return 0; 412 } 413 414 static void xr17v35x_unregister_gpio(struct uart_8250_port *port) 415 { 416 if (!port->port.private_data) 417 return; 418 419 __xr17v35x_unregister_gpio(port->port.private_data); 420 port->port.private_data = NULL; 421 } 422 423 static int generic_rs485_config(struct uart_port *port, struct ktermios *termios, 424 struct serial_rs485 *rs485) 425 { 426 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 427 u8 __iomem *p = port->membase; 428 u8 value; 429 430 value = readb(p + UART_EXAR_FCTR); 431 if (is_rs485) 432 value |= UART_FCTR_EXAR_485; 433 else 434 value &= ~UART_FCTR_EXAR_485; 435 436 writeb(value, p + UART_EXAR_FCTR); 437 438 if (is_rs485) 439 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); 440 441 return 0; 442 } 443 444 static const struct serial_rs485 generic_rs485_supported = { 445 .flags = SER_RS485_ENABLED, 446 }; 447 448 static const struct exar8250_platform exar8250_default_platform = { 449 .register_gpio = xr17v35x_register_gpio, 450 .unregister_gpio = xr17v35x_unregister_gpio, 451 .rs485_config = generic_rs485_config, 452 .rs485_supported = &generic_rs485_supported, 453 }; 454 455 static int iot2040_rs485_config(struct uart_port *port, struct ktermios *termios, 456 struct serial_rs485 *rs485) 457 { 458 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 459 u8 __iomem *p = port->membase; 460 u8 mask = IOT2040_UART1_MASK; 461 u8 mode, value; 462 463 if (is_rs485) { 464 if (rs485->flags & SER_RS485_RX_DURING_TX) 465 mode = IOT2040_UART_MODE_RS422; 466 else 467 mode = IOT2040_UART_MODE_RS485; 468 469 if (rs485->flags & SER_RS485_TERMINATE_BUS) 470 mode |= IOT2040_UART_TERMINATE_BUS; 471 } else { 472 mode = IOT2040_UART_MODE_RS232; 473 } 474 475 if (port->line == 3) { 476 mask <<= IOT2040_UART2_SHIFT; 477 mode <<= IOT2040_UART2_SHIFT; 478 } 479 480 value = readb(p + UART_EXAR_MPIOLVL_7_0); 481 value &= ~mask; 482 value |= mode; 483 writeb(value, p + UART_EXAR_MPIOLVL_7_0); 484 485 return generic_rs485_config(port, termios, rs485); 486 } 487 488 static const struct serial_rs485 iot2040_rs485_supported = { 489 .flags = SER_RS485_ENABLED | SER_RS485_RX_DURING_TX | SER_RS485_TERMINATE_BUS, 490 }; 491 492 static const struct property_entry iot2040_gpio_properties[] = { 493 PROPERTY_ENTRY_U32("exar,first-pin", 10), 494 PROPERTY_ENTRY_U32("ngpios", 1), 495 { } 496 }; 497 498 static const struct software_node iot2040_gpio_node = { 499 .properties = iot2040_gpio_properties, 500 }; 501 502 static int iot2040_register_gpio(struct pci_dev *pcidev, 503 struct uart_8250_port *port) 504 { 505 u8 __iomem *p = port->port.membase; 506 507 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); 508 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); 509 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); 510 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); 511 512 port->port.private_data = 513 __xr17v35x_register_gpio(pcidev, &iot2040_gpio_node); 514 515 return 0; 516 } 517 518 static const struct exar8250_platform iot2040_platform = { 519 .rs485_config = iot2040_rs485_config, 520 .rs485_supported = &iot2040_rs485_supported, 521 .register_gpio = iot2040_register_gpio, 522 .unregister_gpio = xr17v35x_unregister_gpio, 523 }; 524 525 /* 526 * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device, 527 * IOT2020 doesn't have. Therefore it is sufficient to match on the common 528 * board name after the device was found. 529 */ 530 static const struct dmi_system_id exar_platforms[] = { 531 { 532 .matches = { 533 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 534 }, 535 .driver_data = (void *)&iot2040_platform, 536 }, 537 {} 538 }; 539 540 static const struct exar8250_platform *exar_get_platform(void) 541 { 542 const struct dmi_system_id *dmi_match; 543 544 dmi_match = dmi_first_match(exar_platforms); 545 if (dmi_match) 546 return dmi_match->driver_data; 547 548 return &exar8250_default_platform; 549 } 550 551 static int 552 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, 553 struct uart_8250_port *port, int idx) 554 { 555 const struct exar8250_platform *platform = exar_get_platform(); 556 unsigned int offset = idx * 0x400; 557 unsigned int baud = 7812500; 558 u8 __iomem *p; 559 int ret; 560 561 port->port.uartclk = baud * 16; 562 port->port.rs485_config = platform->rs485_config; 563 port->port.rs485_supported = *(platform->rs485_supported); 564 565 /* 566 * Setup the UART clock for the devices on expansion slot to 567 * half the clock speed of the main chip (which is 125MHz) 568 */ 569 if (idx >= 8) 570 port->port.uartclk /= 2; 571 572 ret = default_setup(priv, pcidev, idx, offset, port); 573 if (ret) 574 return ret; 575 576 p = port->port.membase; 577 578 writeb(0x00, p + UART_EXAR_8XMODE); 579 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 580 writeb(128, p + UART_EXAR_TXTRG); 581 writeb(128, p + UART_EXAR_RXTRG); 582 583 if (idx == 0) { 584 /* Setup Multipurpose Input/Output pins. */ 585 setup_gpio(pcidev, p); 586 587 ret = platform->register_gpio(pcidev, port); 588 } 589 590 return ret; 591 } 592 593 static void pci_xr17v35x_exit(struct pci_dev *pcidev) 594 { 595 const struct exar8250_platform *platform = exar_get_platform(); 596 struct exar8250 *priv = pci_get_drvdata(pcidev); 597 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); 598 599 platform->unregister_gpio(port); 600 } 601 602 static inline void exar_misc_clear(struct exar8250 *priv) 603 { 604 /* Clear all PCI interrupts by reading INT0. No effect on IIR */ 605 readb(priv->virt + UART_EXAR_INT0); 606 607 /* Clear INT0 for Expansion Interface slave ports, too */ 608 if (priv->board->num_ports > 8) 609 readb(priv->virt + 0x2000 + UART_EXAR_INT0); 610 } 611 612 /* 613 * These Exar UARTs have an extra interrupt indicator that could fire for a 614 * few interrupts that are not presented/cleared through IIR. One of which is 615 * a wakeup interrupt when coming out of sleep. These interrupts are only 616 * cleared by reading global INT0 or INT1 registers as interrupts are 617 * associated with channel 0. The INT[3:0] registers _are_ accessible from each 618 * channel's address space, but for the sake of bus efficiency we register a 619 * dedicated handler at the PCI device level to handle them. 620 */ 621 static irqreturn_t exar_misc_handler(int irq, void *data) 622 { 623 exar_misc_clear(data); 624 625 return IRQ_HANDLED; 626 } 627 628 static int 629 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 630 { 631 unsigned int nr_ports, i, bar = 0, maxnr; 632 struct exar8250_board *board; 633 struct uart_8250_port uart; 634 struct exar8250 *priv; 635 int rc; 636 637 board = (struct exar8250_board *)ent->driver_data; 638 if (!board) 639 return -EINVAL; 640 641 rc = pcim_enable_device(pcidev); 642 if (rc) 643 return rc; 644 645 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 646 647 if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO) 648 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); 649 else if (board->num_ports) 650 nr_ports = board->num_ports; 651 else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL) 652 nr_ports = pcidev->device & 0xff; 653 else 654 nr_ports = pcidev->device & 0x0f; 655 656 priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL); 657 if (!priv) 658 return -ENOMEM; 659 660 priv->board = board; 661 priv->virt = pcim_iomap(pcidev, bar, 0); 662 if (!priv->virt) 663 return -ENOMEM; 664 665 pci_set_master(pcidev); 666 667 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); 668 if (rc < 0) 669 return rc; 670 671 memset(&uart, 0, sizeof(uart)); 672 uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT; 673 uart.port.irq = pci_irq_vector(pcidev, 0); 674 uart.port.dev = &pcidev->dev; 675 676 rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler, 677 IRQF_SHARED, "exar_uart", priv); 678 if (rc) 679 return rc; 680 681 /* Clear interrupts */ 682 exar_misc_clear(priv); 683 684 for (i = 0; i < nr_ports && i < maxnr; i++) { 685 rc = board->setup(priv, pcidev, &uart, i); 686 if (rc) { 687 dev_err(&pcidev->dev, "Failed to setup port %u\n", i); 688 break; 689 } 690 691 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 692 uart.port.iobase, uart.port.irq, uart.port.iotype); 693 694 priv->line[i] = serial8250_register_8250_port(&uart); 695 if (priv->line[i] < 0) { 696 dev_err(&pcidev->dev, 697 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 698 uart.port.iobase, uart.port.irq, 699 uart.port.iotype, priv->line[i]); 700 break; 701 } 702 } 703 priv->nr = i; 704 pci_set_drvdata(pcidev, priv); 705 return 0; 706 } 707 708 static void exar_pci_remove(struct pci_dev *pcidev) 709 { 710 struct exar8250 *priv = pci_get_drvdata(pcidev); 711 unsigned int i; 712 713 for (i = 0; i < priv->nr; i++) 714 serial8250_unregister_port(priv->line[i]); 715 716 if (priv->board->exit) 717 priv->board->exit(pcidev); 718 } 719 720 static int __maybe_unused exar_suspend(struct device *dev) 721 { 722 struct pci_dev *pcidev = to_pci_dev(dev); 723 struct exar8250 *priv = pci_get_drvdata(pcidev); 724 unsigned int i; 725 726 for (i = 0; i < priv->nr; i++) 727 if (priv->line[i] >= 0) 728 serial8250_suspend_port(priv->line[i]); 729 730 /* Ensure that every init quirk is properly torn down */ 731 if (priv->board->exit) 732 priv->board->exit(pcidev); 733 734 return 0; 735 } 736 737 static int __maybe_unused exar_resume(struct device *dev) 738 { 739 struct exar8250 *priv = dev_get_drvdata(dev); 740 unsigned int i; 741 742 exar_misc_clear(priv); 743 744 for (i = 0; i < priv->nr; i++) 745 if (priv->line[i] >= 0) 746 serial8250_resume_port(priv->line[i]); 747 748 return 0; 749 } 750 751 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); 752 753 static const struct exar8250_board pbn_fastcom335_2 = { 754 .num_ports = 2, 755 .setup = pci_fastcom335_setup, 756 }; 757 758 static const struct exar8250_board pbn_fastcom335_4 = { 759 .num_ports = 4, 760 .setup = pci_fastcom335_setup, 761 }; 762 763 static const struct exar8250_board pbn_fastcom335_8 = { 764 .num_ports = 8, 765 .setup = pci_fastcom335_setup, 766 }; 767 768 static const struct exar8250_board pbn_connect = { 769 .setup = pci_connect_tech_setup, 770 }; 771 772 static const struct exar8250_board pbn_exar_ibm_saturn = { 773 .num_ports = 1, 774 .setup = pci_xr17c154_setup, 775 }; 776 777 static const struct exar8250_board pbn_exar_XR17C15x = { 778 .setup = pci_xr17c154_setup, 779 }; 780 781 static const struct exar8250_board pbn_exar_XR17V35x = { 782 .setup = pci_xr17v35x_setup, 783 .exit = pci_xr17v35x_exit, 784 }; 785 786 static const struct exar8250_board pbn_fastcom35x_2 = { 787 .num_ports = 2, 788 .setup = pci_xr17v35x_setup, 789 .exit = pci_xr17v35x_exit, 790 }; 791 792 static const struct exar8250_board pbn_fastcom35x_4 = { 793 .num_ports = 4, 794 .setup = pci_xr17v35x_setup, 795 .exit = pci_xr17v35x_exit, 796 }; 797 798 static const struct exar8250_board pbn_fastcom35x_8 = { 799 .num_ports = 8, 800 .setup = pci_xr17v35x_setup, 801 .exit = pci_xr17v35x_exit, 802 }; 803 804 static const struct exar8250_board pbn_exar_XR17V4358 = { 805 .num_ports = 12, 806 .setup = pci_xr17v35x_setup, 807 .exit = pci_xr17v35x_exit, 808 }; 809 810 static const struct exar8250_board pbn_exar_XR17V8358 = { 811 .num_ports = 16, 812 .setup = pci_xr17v35x_setup, 813 .exit = pci_xr17v35x_exit, 814 }; 815 816 #define CONNECT_DEVICE(devid, sdevid, bd) { \ 817 PCI_DEVICE_SUB( \ 818 PCI_VENDOR_ID_EXAR, \ 819 PCI_DEVICE_ID_EXAR_##devid, \ 820 PCI_SUBVENDOR_ID_CONNECT_TECH, \ 821 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ 822 (kernel_ulong_t)&bd \ 823 } 824 825 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) } 826 827 #define IBM_DEVICE(devid, sdevid, bd) { \ 828 PCI_DEVICE_SUB( \ 829 PCI_VENDOR_ID_EXAR, \ 830 PCI_DEVICE_ID_EXAR_##devid, \ 831 PCI_VENDOR_ID_IBM, \ 832 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ 833 (kernel_ulong_t)&bd \ 834 } 835 836 #define USR_DEVICE(devid, sdevid, bd) { \ 837 PCI_DEVICE_SUB( \ 838 PCI_VENDOR_ID_USR, \ 839 PCI_DEVICE_ID_EXAR_##devid, \ 840 PCI_VENDOR_ID_EXAR, \ 841 PCI_SUBDEVICE_ID_USR_##sdevid), 0, 0, \ 842 (kernel_ulong_t)&bd \ 843 } 844 845 static const struct pci_device_id exar_pci_tbl[] = { 846 EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x), 847 EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x), 848 EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x), 849 EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x), 850 EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x), 851 EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x), 852 EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x), 853 854 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), 855 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), 856 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), 857 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), 858 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), 859 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), 860 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), 861 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), 862 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), 863 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), 864 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), 865 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 866 867 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 868 869 /* USRobotics USR298x-OEM PCI Modems */ 870 USR_DEVICE(XR17C152, 2980, pbn_exar_XR17C15x), 871 USR_DEVICE(XR17C152, 2981, pbn_exar_XR17C15x), 872 873 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 874 EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x), 875 EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x), 876 EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x), 877 878 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ 879 EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x), 880 EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x), 881 EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x), 882 EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358), 883 EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358), 884 EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2), 885 EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4), 886 EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8), 887 888 EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2), 889 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), 890 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), 891 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), 892 893 EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x), 894 EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x), 895 EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x), 896 EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x), 897 EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x), 898 { 0, } 899 }; 900 MODULE_DEVICE_TABLE(pci, exar_pci_tbl); 901 902 static struct pci_driver exar_pci_driver = { 903 .name = "exar_serial", 904 .probe = exar_pci_probe, 905 .remove = exar_pci_remove, 906 .driver = { 907 .pm = &exar_pci_pm, 908 }, 909 .id_table = exar_pci_tbl, 910 }; 911 module_pci_driver(exar_pci_driver); 912 913 MODULE_LICENSE("GPL"); 914 MODULE_DESCRIPTION("Exar Serial Driver"); 915 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 916