1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type Exar chips PCI serial ports. 4 * 5 * Based on drivers/tty/serial/8250/8250_pci.c, 6 * 7 * Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved. 8 */ 9 #include <linux/acpi.h> 10 #include <linux/dmi.h> 11 #include <linux/io.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/property.h> 16 #include <linux/serial_core.h> 17 #include <linux/serial_reg.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/tty.h> 21 #include <linux/8250_pci.h> 22 23 #include <asm/byteorder.h> 24 25 #include "8250.h" 26 27 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002 28 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004 29 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a 30 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b 31 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020 32 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021 33 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022 34 #define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358 35 #define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358 36 37 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ 38 39 #define UART_EXAR_FCTR 0x08 /* Feature Control Register */ 40 #define UART_FCTR_EXAR_IRDA 0x10 /* IrDa data encode select */ 41 #define UART_FCTR_EXAR_485 0x20 /* Auto 485 half duplex dir ctl */ 42 #define UART_FCTR_EXAR_TRGA 0x00 /* FIFO trigger table A */ 43 #define UART_FCTR_EXAR_TRGB 0x60 /* FIFO trigger table B */ 44 #define UART_FCTR_EXAR_TRGC 0x80 /* FIFO trigger table C */ 45 #define UART_FCTR_EXAR_TRGD 0xc0 /* FIFO trigger table D programmable */ 46 47 #define UART_EXAR_TXTRG 0x0a /* Tx FIFO trigger level write-only */ 48 #define UART_EXAR_RXTRG 0x0b /* Rx FIFO trigger level write-only */ 49 50 #define UART_EXAR_MPIOINT_7_0 0x8f /* MPIOINT[7:0] */ 51 #define UART_EXAR_MPIOLVL_7_0 0x90 /* MPIOLVL[7:0] */ 52 #define UART_EXAR_MPIO3T_7_0 0x91 /* MPIO3T[7:0] */ 53 #define UART_EXAR_MPIOINV_7_0 0x92 /* MPIOINV[7:0] */ 54 #define UART_EXAR_MPIOSEL_7_0 0x93 /* MPIOSEL[7:0] */ 55 #define UART_EXAR_MPIOOD_7_0 0x94 /* MPIOOD[7:0] */ 56 #define UART_EXAR_MPIOINT_15_8 0x95 /* MPIOINT[15:8] */ 57 #define UART_EXAR_MPIOLVL_15_8 0x96 /* MPIOLVL[15:8] */ 58 #define UART_EXAR_MPIO3T_15_8 0x97 /* MPIO3T[15:8] */ 59 #define UART_EXAR_MPIOINV_15_8 0x98 /* MPIOINV[15:8] */ 60 #define UART_EXAR_MPIOSEL_15_8 0x99 /* MPIOSEL[15:8] */ 61 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 62 63 #define UART_EXAR_RS485_DLY(x) ((x) << 4) 64 65 /* 66 * IOT2040 MPIO wiring semantics: 67 * 68 * MPIO Port Function 69 * ---- ---- -------- 70 * 0 2 Mode bit 0 71 * 1 2 Mode bit 1 72 * 2 2 Terminate bus 73 * 3 - <reserved> 74 * 4 3 Mode bit 0 75 * 5 3 Mode bit 1 76 * 6 3 Terminate bus 77 * 7 - <reserved> 78 * 8 2 Enable 79 * 9 3 Enable 80 * 10 - Red LED 81 * 11..15 - <unused> 82 */ 83 84 /* IOT2040 MPIOs 0..7 */ 85 #define IOT2040_UART_MODE_RS232 0x01 86 #define IOT2040_UART_MODE_RS485 0x02 87 #define IOT2040_UART_MODE_RS422 0x03 88 #define IOT2040_UART_TERMINATE_BUS 0x04 89 90 #define IOT2040_UART1_MASK 0x0f 91 #define IOT2040_UART2_SHIFT 4 92 93 #define IOT2040_UARTS_DEFAULT_MODE 0x11 /* both RS232 */ 94 #define IOT2040_UARTS_GPIO_LO_MODE 0x88 /* reserved pins as input */ 95 96 /* IOT2040 MPIOs 8..15 */ 97 #define IOT2040_UARTS_ENABLE 0x03 98 #define IOT2040_UARTS_GPIO_HI_MODE 0xF8 /* enable & LED as outputs */ 99 100 struct exar8250; 101 102 struct exar8250_platform { 103 int (*rs485_config)(struct uart_port *, struct serial_rs485 *); 104 int (*register_gpio)(struct pci_dev *, struct uart_8250_port *); 105 }; 106 107 /** 108 * struct exar8250_board - board information 109 * @num_ports: number of serial ports 110 * @reg_shift: describes UART register mapping in PCI memory 111 */ 112 struct exar8250_board { 113 unsigned int num_ports; 114 unsigned int reg_shift; 115 bool has_slave; 116 int (*setup)(struct exar8250 *, struct pci_dev *, 117 struct uart_8250_port *, int); 118 void (*exit)(struct pci_dev *pcidev); 119 }; 120 121 struct exar8250 { 122 unsigned int nr; 123 struct exar8250_board *board; 124 int line[0]; 125 }; 126 127 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev, 128 int idx, unsigned int offset, 129 struct uart_8250_port *port) 130 { 131 const struct exar8250_board *board = priv->board; 132 unsigned int bar = 0; 133 134 if (!pcim_iomap_table(pcidev)[bar] && !pcim_iomap(pcidev, bar, 0)) 135 return -ENOMEM; 136 137 port->port.iotype = UPIO_MEM; 138 port->port.mapbase = pci_resource_start(pcidev, bar) + offset; 139 port->port.membase = pcim_iomap_table(pcidev)[bar] + offset; 140 port->port.regshift = board->reg_shift; 141 142 return 0; 143 } 144 145 static int 146 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev, 147 struct uart_8250_port *port, int idx) 148 { 149 unsigned int offset = idx * 0x200; 150 unsigned int baud = 1843200; 151 u8 __iomem *p; 152 int err; 153 154 port->port.uartclk = baud * 16; 155 156 err = default_setup(priv, pcidev, idx, offset, port); 157 if (err) 158 return err; 159 160 p = port->port.membase; 161 162 writeb(0x00, p + UART_EXAR_8XMODE); 163 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 164 writeb(32, p + UART_EXAR_TXTRG); 165 writeb(32, p + UART_EXAR_RXTRG); 166 167 /* 168 * Setup Multipurpose Input/Output pins. 169 */ 170 if (idx == 0) { 171 switch (pcidev->device) { 172 case PCI_DEVICE_ID_COMMTECH_4222PCI335: 173 case PCI_DEVICE_ID_COMMTECH_4224PCI335: 174 writeb(0x78, p + UART_EXAR_MPIOLVL_7_0); 175 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 176 writeb(0x00, p + UART_EXAR_MPIOSEL_7_0); 177 break; 178 case PCI_DEVICE_ID_COMMTECH_2324PCI335: 179 case PCI_DEVICE_ID_COMMTECH_2328PCI335: 180 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 181 writeb(0xc0, p + UART_EXAR_MPIOINV_7_0); 182 writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0); 183 break; 184 } 185 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 186 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 187 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 188 } 189 190 return 0; 191 } 192 193 static int 194 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev, 195 struct uart_8250_port *port, int idx) 196 { 197 unsigned int offset = idx * 0x200; 198 unsigned int baud = 1843200; 199 200 port->port.uartclk = baud * 16; 201 return default_setup(priv, pcidev, idx, offset, port); 202 } 203 204 static int 205 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev, 206 struct uart_8250_port *port, int idx) 207 { 208 unsigned int offset = idx * 0x200; 209 unsigned int baud = 921600; 210 211 port->port.uartclk = baud * 16; 212 return default_setup(priv, pcidev, idx, offset, port); 213 } 214 215 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p) 216 { 217 /* 218 * The Commtech adapters required the MPIOs to be driven low. The Exar 219 * devices will export them as GPIOs, so we pre-configure them safely 220 * as inputs. 221 */ 222 u8 dir = pcidev->vendor == PCI_VENDOR_ID_EXAR ? 0xff : 0x00; 223 224 writeb(0x00, p + UART_EXAR_MPIOINT_7_0); 225 writeb(0x00, p + UART_EXAR_MPIOLVL_7_0); 226 writeb(0x00, p + UART_EXAR_MPIO3T_7_0); 227 writeb(0x00, p + UART_EXAR_MPIOINV_7_0); 228 writeb(dir, p + UART_EXAR_MPIOSEL_7_0); 229 writeb(0x00, p + UART_EXAR_MPIOOD_7_0); 230 writeb(0x00, p + UART_EXAR_MPIOINT_15_8); 231 writeb(0x00, p + UART_EXAR_MPIOLVL_15_8); 232 writeb(0x00, p + UART_EXAR_MPIO3T_15_8); 233 writeb(0x00, p + UART_EXAR_MPIOINV_15_8); 234 writeb(dir, p + UART_EXAR_MPIOSEL_15_8); 235 writeb(0x00, p + UART_EXAR_MPIOOD_15_8); 236 } 237 238 static void * 239 __xr17v35x_register_gpio(struct pci_dev *pcidev, 240 const struct property_entry *properties) 241 { 242 struct platform_device *pdev; 243 244 pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO); 245 if (!pdev) 246 return NULL; 247 248 pdev->dev.parent = &pcidev->dev; 249 ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev)); 250 251 if (platform_device_add_properties(pdev, properties) < 0 || 252 platform_device_add(pdev) < 0) { 253 platform_device_put(pdev); 254 return NULL; 255 } 256 257 return pdev; 258 } 259 260 static const struct property_entry exar_gpio_properties[] = { 261 PROPERTY_ENTRY_U32("exar,first-pin", 0), 262 PROPERTY_ENTRY_U32("ngpios", 16), 263 { } 264 }; 265 266 static int xr17v35x_register_gpio(struct pci_dev *pcidev, 267 struct uart_8250_port *port) 268 { 269 if (pcidev->vendor == PCI_VENDOR_ID_EXAR) 270 port->port.private_data = 271 __xr17v35x_register_gpio(pcidev, exar_gpio_properties); 272 273 return 0; 274 } 275 276 static const struct exar8250_platform exar8250_default_platform = { 277 .register_gpio = xr17v35x_register_gpio, 278 }; 279 280 static int iot2040_rs485_config(struct uart_port *port, 281 struct serial_rs485 *rs485) 282 { 283 bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED); 284 u8 __iomem *p = port->membase; 285 u8 mask = IOT2040_UART1_MASK; 286 u8 mode, value; 287 288 if (is_rs485) { 289 if (rs485->flags & SER_RS485_RX_DURING_TX) 290 mode = IOT2040_UART_MODE_RS422; 291 else 292 mode = IOT2040_UART_MODE_RS485; 293 294 if (rs485->flags & SER_RS485_TERMINATE_BUS) 295 mode |= IOT2040_UART_TERMINATE_BUS; 296 } else { 297 mode = IOT2040_UART_MODE_RS232; 298 } 299 300 if (port->line == 3) { 301 mask <<= IOT2040_UART2_SHIFT; 302 mode <<= IOT2040_UART2_SHIFT; 303 } 304 305 value = readb(p + UART_EXAR_MPIOLVL_7_0); 306 value &= ~mask; 307 value |= mode; 308 writeb(value, p + UART_EXAR_MPIOLVL_7_0); 309 310 value = readb(p + UART_EXAR_FCTR); 311 if (is_rs485) 312 value |= UART_FCTR_EXAR_485; 313 else 314 value &= ~UART_FCTR_EXAR_485; 315 writeb(value, p + UART_EXAR_FCTR); 316 317 if (is_rs485) 318 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR); 319 320 port->rs485 = *rs485; 321 322 return 0; 323 } 324 325 static const struct property_entry iot2040_gpio_properties[] = { 326 PROPERTY_ENTRY_U32("exar,first-pin", 10), 327 PROPERTY_ENTRY_U32("ngpios", 1), 328 { } 329 }; 330 331 static int iot2040_register_gpio(struct pci_dev *pcidev, 332 struct uart_8250_port *port) 333 { 334 u8 __iomem *p = port->port.membase; 335 336 writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0); 337 writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0); 338 writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8); 339 writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8); 340 341 port->port.private_data = 342 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties); 343 344 return 0; 345 } 346 347 static const struct exar8250_platform iot2040_platform = { 348 .rs485_config = iot2040_rs485_config, 349 .register_gpio = iot2040_register_gpio, 350 }; 351 352 static const struct dmi_system_id exar_platforms[] = { 353 { 354 .matches = { 355 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 356 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 357 "6ES7647-0AA00-1YA2"), 358 }, 359 .driver_data = (void *)&iot2040_platform, 360 }, 361 {} 362 }; 363 364 static int 365 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev, 366 struct uart_8250_port *port, int idx) 367 { 368 const struct exar8250_board *board = priv->board; 369 const struct exar8250_platform *platform; 370 const struct dmi_system_id *dmi_match; 371 unsigned int offset = idx * 0x400; 372 unsigned int baud = 7812500; 373 u8 __iomem *p; 374 int ret; 375 376 dmi_match = dmi_first_match(exar_platforms); 377 if (dmi_match) 378 platform = dmi_match->driver_data; 379 else 380 platform = &exar8250_default_platform; 381 382 port->port.uartclk = baud * 16; 383 port->port.rs485_config = platform->rs485_config; 384 385 /* 386 * Setup the uart clock for the devices on expansion slot to 387 * half the clock speed of the main chip (which is 125MHz) 388 */ 389 if (board->has_slave && idx >= 8) 390 port->port.uartclk /= 2; 391 392 ret = default_setup(priv, pcidev, idx, offset, port); 393 if (ret) 394 return ret; 395 396 p = port->port.membase; 397 398 writeb(0x00, p + UART_EXAR_8XMODE); 399 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR); 400 writeb(128, p + UART_EXAR_TXTRG); 401 writeb(128, p + UART_EXAR_RXTRG); 402 403 if (idx == 0) { 404 /* Setup Multipurpose Input/Output pins. */ 405 setup_gpio(pcidev, p); 406 407 ret = platform->register_gpio(pcidev, port); 408 } 409 410 return ret; 411 } 412 413 static void pci_xr17v35x_exit(struct pci_dev *pcidev) 414 { 415 struct exar8250 *priv = pci_get_drvdata(pcidev); 416 struct uart_8250_port *port = serial8250_get_port(priv->line[0]); 417 struct platform_device *pdev = port->port.private_data; 418 419 platform_device_unregister(pdev); 420 port->port.private_data = NULL; 421 } 422 423 static int 424 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent) 425 { 426 unsigned int nr_ports, i, bar = 0, maxnr; 427 struct exar8250_board *board; 428 struct uart_8250_port uart; 429 struct exar8250 *priv; 430 int rc; 431 432 board = (struct exar8250_board *)ent->driver_data; 433 if (!board) 434 return -EINVAL; 435 436 rc = pcim_enable_device(pcidev); 437 if (rc) 438 return rc; 439 440 maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3); 441 442 nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f; 443 444 priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) + 445 sizeof(unsigned int) * nr_ports, 446 GFP_KERNEL); 447 if (!priv) 448 return -ENOMEM; 449 450 priv->board = board; 451 452 pci_set_master(pcidev); 453 454 rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES); 455 if (rc < 0) 456 return rc; 457 458 memset(&uart, 0, sizeof(uart)); 459 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ 460 | UPF_EXAR_EFR; 461 uart.port.irq = pci_irq_vector(pcidev, 0); 462 uart.port.dev = &pcidev->dev; 463 464 for (i = 0; i < nr_ports && i < maxnr; i++) { 465 rc = board->setup(priv, pcidev, &uart, i); 466 if (rc) { 467 dev_err(&pcidev->dev, "Failed to setup port %u\n", i); 468 break; 469 } 470 471 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", 472 uart.port.iobase, uart.port.irq, uart.port.iotype); 473 474 priv->line[i] = serial8250_register_8250_port(&uart); 475 if (priv->line[i] < 0) { 476 dev_err(&pcidev->dev, 477 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 478 uart.port.iobase, uart.port.irq, 479 uart.port.iotype, priv->line[i]); 480 break; 481 } 482 } 483 priv->nr = i; 484 pci_set_drvdata(pcidev, priv); 485 return 0; 486 } 487 488 static void exar_pci_remove(struct pci_dev *pcidev) 489 { 490 struct exar8250 *priv = pci_get_drvdata(pcidev); 491 unsigned int i; 492 493 for (i = 0; i < priv->nr; i++) 494 serial8250_unregister_port(priv->line[i]); 495 496 if (priv->board->exit) 497 priv->board->exit(pcidev); 498 } 499 500 static int __maybe_unused exar_suspend(struct device *dev) 501 { 502 struct pci_dev *pcidev = to_pci_dev(dev); 503 struct exar8250 *priv = pci_get_drvdata(pcidev); 504 unsigned int i; 505 506 for (i = 0; i < priv->nr; i++) 507 if (priv->line[i] >= 0) 508 serial8250_suspend_port(priv->line[i]); 509 510 /* Ensure that every init quirk is properly torn down */ 511 if (priv->board->exit) 512 priv->board->exit(pcidev); 513 514 return 0; 515 } 516 517 static int __maybe_unused exar_resume(struct device *dev) 518 { 519 struct pci_dev *pcidev = to_pci_dev(dev); 520 struct exar8250 *priv = pci_get_drvdata(pcidev); 521 unsigned int i; 522 523 for (i = 0; i < priv->nr; i++) 524 if (priv->line[i] >= 0) 525 serial8250_resume_port(priv->line[i]); 526 527 return 0; 528 } 529 530 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume); 531 532 static const struct exar8250_board pbn_fastcom335_2 = { 533 .num_ports = 2, 534 .setup = pci_fastcom335_setup, 535 }; 536 537 static const struct exar8250_board pbn_fastcom335_4 = { 538 .num_ports = 4, 539 .setup = pci_fastcom335_setup, 540 }; 541 542 static const struct exar8250_board pbn_fastcom335_8 = { 543 .num_ports = 8, 544 .setup = pci_fastcom335_setup, 545 }; 546 547 static const struct exar8250_board pbn_connect = { 548 .setup = pci_connect_tech_setup, 549 }; 550 551 static const struct exar8250_board pbn_exar_ibm_saturn = { 552 .num_ports = 1, 553 .setup = pci_xr17c154_setup, 554 }; 555 556 static const struct exar8250_board pbn_exar_XR17C15x = { 557 .setup = pci_xr17c154_setup, 558 }; 559 560 static const struct exar8250_board pbn_exar_XR17V35x = { 561 .setup = pci_xr17v35x_setup, 562 .exit = pci_xr17v35x_exit, 563 }; 564 565 static const struct exar8250_board pbn_exar_XR17V4358 = { 566 .num_ports = 12, 567 .has_slave = true, 568 .setup = pci_xr17v35x_setup, 569 .exit = pci_xr17v35x_exit, 570 }; 571 572 static const struct exar8250_board pbn_exar_XR17V8358 = { 573 .num_ports = 16, 574 .has_slave = true, 575 .setup = pci_xr17v35x_setup, 576 .exit = pci_xr17v35x_exit, 577 }; 578 579 #define CONNECT_DEVICE(devid, sdevid, bd) { \ 580 PCI_DEVICE_SUB( \ 581 PCI_VENDOR_ID_EXAR, \ 582 PCI_DEVICE_ID_EXAR_##devid, \ 583 PCI_SUBVENDOR_ID_CONNECT_TECH, \ 584 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0, \ 585 (kernel_ulong_t)&bd \ 586 } 587 588 #define EXAR_DEVICE(vend, devid, bd) { \ 589 PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd \ 590 } 591 592 #define IBM_DEVICE(devid, sdevid, bd) { \ 593 PCI_DEVICE_SUB( \ 594 PCI_VENDOR_ID_EXAR, \ 595 PCI_DEVICE_ID_EXAR_##devid, \ 596 PCI_VENDOR_ID_IBM, \ 597 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0, \ 598 (kernel_ulong_t)&bd \ 599 } 600 601 static const struct pci_device_id exar_pci_tbl[] = { 602 CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect), 603 CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect), 604 CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect), 605 CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect), 606 CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect), 607 CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect), 608 CONNECT_DEVICE(XR17C152, UART_2, pbn_connect), 609 CONNECT_DEVICE(XR17C154, UART_4, pbn_connect), 610 CONNECT_DEVICE(XR17C158, UART_8, pbn_connect), 611 CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect), 612 CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect), 613 CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect), 614 615 IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn), 616 617 /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */ 618 EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x), 619 EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x), 620 EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x), 621 622 /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */ 623 EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x), 624 EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x), 625 EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x), 626 EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358), 627 EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358), 628 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_exar_XR17V35x), 629 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_exar_XR17V35x), 630 EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_exar_XR17V35x), 631 632 EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2), 633 EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4), 634 EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4), 635 EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8), 636 { 0, } 637 }; 638 MODULE_DEVICE_TABLE(pci, exar_pci_tbl); 639 640 static struct pci_driver exar_pci_driver = { 641 .name = "exar_serial", 642 .probe = exar_pci_probe, 643 .remove = exar_pci_remove, 644 .driver = { 645 .pm = &exar_pci_pm, 646 }, 647 .id_table = exar_pci_tbl, 648 }; 649 module_pci_driver(exar_pci_driver); 650 651 MODULE_LICENSE("GPL"); 652 MODULE_DESCRIPTION("Exar Serial Driver"); 653 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>"); 654