1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Probe module for 8250/16550-type Exar chips PCI serial ports.
4  *
5  *  Based on drivers/tty/serial/8250/8250_pci.c,
6  *
7  *  Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
8  */
9 #include <linux/acpi.h>
10 #include <linux/dmi.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/property.h>
16 #include <linux/serial_core.h>
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/string.h>
20 #include <linux/tty.h>
21 #include <linux/8250_pci.h>
22 #include <linux/delay.h>
23 
24 #include <asm/byteorder.h>
25 
26 #include "8250.h"
27 
28 #define PCI_DEVICE_ID_ACCESSIO_COM_2S		0x1052
29 #define PCI_DEVICE_ID_ACCESSIO_COM_4S		0x105d
30 #define PCI_DEVICE_ID_ACCESSIO_COM_8S		0x106c
31 #define PCI_DEVICE_ID_ACCESSIO_COM232_8		0x10a8
32 #define PCI_DEVICE_ID_ACCESSIO_COM_2SM		0x10d2
33 #define PCI_DEVICE_ID_ACCESSIO_COM_4SM		0x10db
34 #define PCI_DEVICE_ID_ACCESSIO_COM_8SM		0x10ea
35 
36 #define PCI_DEVICE_ID_COMMTECH_4224PCI335	0x0002
37 #define PCI_DEVICE_ID_COMMTECH_4222PCI335	0x0004
38 #define PCI_DEVICE_ID_COMMTECH_2324PCI335	0x000a
39 #define PCI_DEVICE_ID_COMMTECH_2328PCI335	0x000b
40 #define PCI_DEVICE_ID_COMMTECH_4224PCIE		0x0020
41 #define PCI_DEVICE_ID_COMMTECH_4228PCIE		0x0021
42 #define PCI_DEVICE_ID_COMMTECH_4222PCIE		0x0022
43 #define PCI_DEVICE_ID_EXAR_XR17V4358		0x4358
44 #define PCI_DEVICE_ID_EXAR_XR17V8358		0x8358
45 
46 #define UART_EXAR_INT0		0x80
47 #define UART_EXAR_8XMODE	0x88	/* 8X sampling rate select */
48 #define UART_EXAR_SLEEP		0x8b	/* Sleep mode */
49 #define UART_EXAR_DVID		0x8d	/* Device identification */
50 
51 #define UART_EXAR_FCTR		0x08	/* Feature Control Register */
52 #define UART_FCTR_EXAR_IRDA	0x10	/* IrDa data encode select */
53 #define UART_FCTR_EXAR_485	0x20	/* Auto 485 half duplex dir ctl */
54 #define UART_FCTR_EXAR_TRGA	0x00	/* FIFO trigger table A */
55 #define UART_FCTR_EXAR_TRGB	0x60	/* FIFO trigger table B */
56 #define UART_FCTR_EXAR_TRGC	0x80	/* FIFO trigger table C */
57 #define UART_FCTR_EXAR_TRGD	0xc0	/* FIFO trigger table D programmable */
58 
59 #define UART_EXAR_TXTRG		0x0a	/* Tx FIFO trigger level write-only */
60 #define UART_EXAR_RXTRG		0x0b	/* Rx FIFO trigger level write-only */
61 
62 #define UART_EXAR_MPIOINT_7_0	0x8f	/* MPIOINT[7:0] */
63 #define UART_EXAR_MPIOLVL_7_0	0x90	/* MPIOLVL[7:0] */
64 #define UART_EXAR_MPIO3T_7_0	0x91	/* MPIO3T[7:0] */
65 #define UART_EXAR_MPIOINV_7_0	0x92	/* MPIOINV[7:0] */
66 #define UART_EXAR_MPIOSEL_7_0	0x93	/* MPIOSEL[7:0] */
67 #define UART_EXAR_MPIOOD_7_0	0x94	/* MPIOOD[7:0] */
68 #define UART_EXAR_MPIOINT_15_8	0x95	/* MPIOINT[15:8] */
69 #define UART_EXAR_MPIOLVL_15_8	0x96	/* MPIOLVL[15:8] */
70 #define UART_EXAR_MPIO3T_15_8	0x97	/* MPIO3T[15:8] */
71 #define UART_EXAR_MPIOINV_15_8	0x98	/* MPIOINV[15:8] */
72 #define UART_EXAR_MPIOSEL_15_8	0x99	/* MPIOSEL[15:8] */
73 #define UART_EXAR_MPIOOD_15_8	0x9a	/* MPIOOD[15:8] */
74 
75 #define UART_EXAR_RS485_DLY(x)	((x) << 4)
76 
77 /*
78  * IOT2040 MPIO wiring semantics:
79  *
80  * MPIO		Port	Function
81  * ----		----	--------
82  * 0		2 	Mode bit 0
83  * 1		2	Mode bit 1
84  * 2		2	Terminate bus
85  * 3		-	<reserved>
86  * 4		3	Mode bit 0
87  * 5		3	Mode bit 1
88  * 6		3	Terminate bus
89  * 7		-	<reserved>
90  * 8		2	Enable
91  * 9		3	Enable
92  * 10		-	Red LED
93  * 11..15	-	<unused>
94  */
95 
96 /* IOT2040 MPIOs 0..7 */
97 #define IOT2040_UART_MODE_RS232		0x01
98 #define IOT2040_UART_MODE_RS485		0x02
99 #define IOT2040_UART_MODE_RS422		0x03
100 #define IOT2040_UART_TERMINATE_BUS	0x04
101 
102 #define IOT2040_UART1_MASK		0x0f
103 #define IOT2040_UART2_SHIFT		4
104 
105 #define IOT2040_UARTS_DEFAULT_MODE	0x11	/* both RS232 */
106 #define IOT2040_UARTS_GPIO_LO_MODE	0x88	/* reserved pins as input */
107 
108 /* IOT2040 MPIOs 8..15 */
109 #define IOT2040_UARTS_ENABLE		0x03
110 #define IOT2040_UARTS_GPIO_HI_MODE	0xF8	/* enable & LED as outputs */
111 
112 struct exar8250;
113 
114 struct exar8250_platform {
115 	int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
116 	int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
117 	void (*unregister_gpio)(struct uart_8250_port *);
118 };
119 
120 /**
121  * struct exar8250_board - board information
122  * @num_ports: number of serial ports
123  * @reg_shift: describes UART register mapping in PCI memory
124  * @setup: quirk run at ->probe() stage
125  * @exit: quirk run at ->remove() stage
126  */
127 struct exar8250_board {
128 	unsigned int num_ports;
129 	unsigned int reg_shift;
130 	int	(*setup)(struct exar8250 *, struct pci_dev *,
131 			 struct uart_8250_port *, int);
132 	void	(*exit)(struct pci_dev *pcidev);
133 };
134 
135 struct exar8250 {
136 	unsigned int		nr;
137 	struct exar8250_board	*board;
138 	void __iomem		*virt;
139 	int			line[];
140 };
141 
142 static void exar_pm(struct uart_port *port, unsigned int state, unsigned int old)
143 {
144 	/*
145 	 * Exar UARTs have a SLEEP register that enables or disables each UART
146 	 * to enter sleep mode separately. On the XR17V35x the register
147 	 * is accessible to each UART at the UART_EXAR_SLEEP offset, but
148 	 * the UART channel may only write to the corresponding bit.
149 	 */
150 	serial_port_out(port, UART_EXAR_SLEEP, state ? 0xff : 0);
151 }
152 
153 /*
154  * XR17V35x UARTs have an extra fractional divisor register (DLD)
155  * Calculate divisor with extra 4-bit fractional portion
156  */
157 static unsigned int xr17v35x_get_divisor(struct uart_port *p, unsigned int baud,
158 					 unsigned int *frac)
159 {
160 	unsigned int quot_16;
161 
162 	quot_16 = DIV_ROUND_CLOSEST(p->uartclk, baud);
163 	*frac = quot_16 & 0x0f;
164 
165 	return quot_16 >> 4;
166 }
167 
168 static void xr17v35x_set_divisor(struct uart_port *p, unsigned int baud,
169 				 unsigned int quot, unsigned int quot_frac)
170 {
171 	serial8250_do_set_divisor(p, baud, quot, quot_frac);
172 
173 	/* Preserve bits not related to baudrate; DLD[7:4]. */
174 	quot_frac |= serial_port_in(p, 0x2) & 0xf0;
175 	serial_port_out(p, 0x2, quot_frac);
176 }
177 
178 static int xr17v35x_startup(struct uart_port *port)
179 {
180 	/*
181 	 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
182 	 * MCR [7:5] and MSR [7:0]
183 	 */
184 	serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
185 
186 	/*
187 	 * Make sure all interrups are masked until initialization is
188 	 * complete and the FIFOs are cleared
189 	 */
190 	serial_port_out(port, UART_IER, 0);
191 
192 	return serial8250_do_startup(port);
193 }
194 
195 static void exar_shutdown(struct uart_port *port)
196 {
197 	unsigned char lsr;
198 	bool tx_complete = false;
199 	struct uart_8250_port *up = up_to_u8250p(port);
200 	struct circ_buf *xmit = &port->state->xmit;
201 	int i = 0;
202 
203 	do {
204 		lsr = serial_in(up, UART_LSR);
205 		if (lsr & (UART_LSR_TEMT | UART_LSR_THRE))
206 			tx_complete = true;
207 		else
208 			tx_complete = false;
209 		usleep_range(1000, 1100);
210 	} while (!uart_circ_empty(xmit) && !tx_complete && i++ < 1000);
211 
212 	serial8250_do_shutdown(port);
213 }
214 
215 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
216 			 int idx, unsigned int offset,
217 			 struct uart_8250_port *port)
218 {
219 	const struct exar8250_board *board = priv->board;
220 	unsigned int bar = 0;
221 	unsigned char status;
222 
223 	port->port.iotype = UPIO_MEM;
224 	port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
225 	port->port.membase = priv->virt + offset;
226 	port->port.regshift = board->reg_shift;
227 
228 	/*
229 	 * XR17V35x UARTs have an extra divisor register, DLD that gets enabled
230 	 * with when DLAB is set which will cause the device to incorrectly match
231 	 * and assign port type to PORT_16650. The EFR for this UART is found
232 	 * at offset 0x09. Instead check the Deice ID (DVID) register
233 	 * for a 2, 4 or 8 port UART.
234 	 */
235 	status = readb(port->port.membase + UART_EXAR_DVID);
236 	if (status == 0x82 || status == 0x84 || status == 0x88) {
237 		port->port.type = PORT_XR17V35X;
238 
239 		port->port.get_divisor = xr17v35x_get_divisor;
240 		port->port.set_divisor = xr17v35x_set_divisor;
241 
242 		port->port.startup = xr17v35x_startup;
243 	} else {
244 		port->port.type = PORT_XR17D15X;
245 	}
246 
247 	port->port.pm = exar_pm;
248 	port->port.shutdown = exar_shutdown;
249 
250 	return 0;
251 }
252 
253 static int
254 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
255 		     struct uart_8250_port *port, int idx)
256 {
257 	unsigned int offset = idx * 0x200;
258 	unsigned int baud = 1843200;
259 	u8 __iomem *p;
260 	int err;
261 
262 	port->port.uartclk = baud * 16;
263 
264 	err = default_setup(priv, pcidev, idx, offset, port);
265 	if (err)
266 		return err;
267 
268 	p = port->port.membase;
269 
270 	writeb(0x00, p + UART_EXAR_8XMODE);
271 	writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
272 	writeb(32, p + UART_EXAR_TXTRG);
273 	writeb(32, p + UART_EXAR_RXTRG);
274 
275 	/*
276 	 * Setup Multipurpose Input/Output pins.
277 	 */
278 	if (idx == 0) {
279 		switch (pcidev->device) {
280 		case PCI_DEVICE_ID_COMMTECH_4222PCI335:
281 		case PCI_DEVICE_ID_COMMTECH_4224PCI335:
282 			writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
283 			writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
284 			writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
285 			break;
286 		case PCI_DEVICE_ID_COMMTECH_2324PCI335:
287 		case PCI_DEVICE_ID_COMMTECH_2328PCI335:
288 			writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
289 			writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
290 			writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
291 			break;
292 		}
293 		writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
294 		writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
295 		writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
296 	}
297 
298 	return 0;
299 }
300 
301 static int
302 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
303 		       struct uart_8250_port *port, int idx)
304 {
305 	unsigned int offset = idx * 0x200;
306 	unsigned int baud = 1843200;
307 
308 	port->port.uartclk = baud * 16;
309 	return default_setup(priv, pcidev, idx, offset, port);
310 }
311 
312 static int
313 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
314 		   struct uart_8250_port *port, int idx)
315 {
316 	unsigned int offset = idx * 0x200;
317 	unsigned int baud = 921600;
318 
319 	port->port.uartclk = baud * 16;
320 	return default_setup(priv, pcidev, idx, offset, port);
321 }
322 
323 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
324 {
325 	/*
326 	 * The Commtech adapters required the MPIOs to be driven low. The Exar
327 	 * devices will export them as GPIOs, so we pre-configure them safely
328 	 * as inputs.
329 	 */
330 
331 	u8 dir = 0x00;
332 
333 	if  ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
334 		(pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
335 		// Configure GPIO as inputs for Commtech adapters
336 		dir = 0xff;
337 	} else {
338 		// Configure GPIO as outputs for SeaLevel adapters
339 		dir = 0x00;
340 	}
341 
342 	writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
343 	writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
344 	writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
345 	writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
346 	writeb(dir,  p + UART_EXAR_MPIOSEL_7_0);
347 	writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
348 	writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
349 	writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
350 	writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
351 	writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
352 	writeb(dir,  p + UART_EXAR_MPIOSEL_15_8);
353 	writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
354 }
355 
356 static struct platform_device *__xr17v35x_register_gpio(struct pci_dev *pcidev,
357 							const struct software_node *node)
358 {
359 	struct platform_device *pdev;
360 
361 	pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
362 	if (!pdev)
363 		return NULL;
364 
365 	pdev->dev.parent = &pcidev->dev;
366 	ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
367 
368 	if (device_add_software_node(&pdev->dev, node) < 0 ||
369 	    platform_device_add(pdev) < 0) {
370 		platform_device_put(pdev);
371 		return NULL;
372 	}
373 
374 	return pdev;
375 }
376 
377 static void __xr17v35x_unregister_gpio(struct platform_device *pdev)
378 {
379 	device_remove_software_node(&pdev->dev);
380 	platform_device_unregister(pdev);
381 }
382 
383 static const struct property_entry exar_gpio_properties[] = {
384 	PROPERTY_ENTRY_U32("exar,first-pin", 0),
385 	PROPERTY_ENTRY_U32("ngpios", 16),
386 	{ }
387 };
388 
389 static const struct software_node exar_gpio_node = {
390 	.properties = exar_gpio_properties,
391 };
392 
393 static int xr17v35x_register_gpio(struct pci_dev *pcidev, struct uart_8250_port *port)
394 {
395 	if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
396 		port->port.private_data =
397 			__xr17v35x_register_gpio(pcidev, &exar_gpio_node);
398 
399 	return 0;
400 }
401 
402 static void xr17v35x_unregister_gpio(struct uart_8250_port *port)
403 {
404 	if (!port->port.private_data)
405 		return;
406 
407 	__xr17v35x_unregister_gpio(port->port.private_data);
408 	port->port.private_data = NULL;
409 }
410 
411 static int generic_rs485_config(struct uart_port *port,
412 				struct serial_rs485 *rs485)
413 {
414 	bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
415 	u8 __iomem *p = port->membase;
416 	u8 value;
417 
418 	value = readb(p + UART_EXAR_FCTR);
419 	if (is_rs485)
420 		value |= UART_FCTR_EXAR_485;
421 	else
422 		value &= ~UART_FCTR_EXAR_485;
423 
424 	writeb(value, p + UART_EXAR_FCTR);
425 
426 	if (is_rs485)
427 		writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
428 
429 	port->rs485 = *rs485;
430 
431 	return 0;
432 }
433 
434 static const struct exar8250_platform exar8250_default_platform = {
435 	.register_gpio = xr17v35x_register_gpio,
436 	.unregister_gpio = xr17v35x_unregister_gpio,
437 	.rs485_config = generic_rs485_config,
438 };
439 
440 static int iot2040_rs485_config(struct uart_port *port,
441 				struct serial_rs485 *rs485)
442 {
443 	bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
444 	u8 __iomem *p = port->membase;
445 	u8 mask = IOT2040_UART1_MASK;
446 	u8 mode, value;
447 
448 	if (is_rs485) {
449 		if (rs485->flags & SER_RS485_RX_DURING_TX)
450 			mode = IOT2040_UART_MODE_RS422;
451 		else
452 			mode = IOT2040_UART_MODE_RS485;
453 
454 		if (rs485->flags & SER_RS485_TERMINATE_BUS)
455 			mode |= IOT2040_UART_TERMINATE_BUS;
456 	} else {
457 		mode = IOT2040_UART_MODE_RS232;
458 	}
459 
460 	if (port->line == 3) {
461 		mask <<= IOT2040_UART2_SHIFT;
462 		mode <<= IOT2040_UART2_SHIFT;
463 	}
464 
465 	value = readb(p + UART_EXAR_MPIOLVL_7_0);
466 	value &= ~mask;
467 	value |= mode;
468 	writeb(value, p + UART_EXAR_MPIOLVL_7_0);
469 
470 	return generic_rs485_config(port, rs485);
471 }
472 
473 static const struct property_entry iot2040_gpio_properties[] = {
474 	PROPERTY_ENTRY_U32("exar,first-pin", 10),
475 	PROPERTY_ENTRY_U32("ngpios", 1),
476 	{ }
477 };
478 
479 static const struct software_node iot2040_gpio_node = {
480 	.properties = iot2040_gpio_properties,
481 };
482 
483 static int iot2040_register_gpio(struct pci_dev *pcidev,
484 			      struct uart_8250_port *port)
485 {
486 	u8 __iomem *p = port->port.membase;
487 
488 	writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
489 	writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
490 	writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
491 	writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
492 
493 	port->port.private_data =
494 		__xr17v35x_register_gpio(pcidev, &iot2040_gpio_node);
495 
496 	return 0;
497 }
498 
499 static const struct exar8250_platform iot2040_platform = {
500 	.rs485_config = iot2040_rs485_config,
501 	.register_gpio = iot2040_register_gpio,
502 	.unregister_gpio = xr17v35x_unregister_gpio,
503 };
504 
505 /*
506  * For SIMATIC IOT2000, only IOT2040 and its variants have the Exar device,
507  * IOT2020 doesn't have. Therefore it is sufficient to match on the common
508  * board name after the device was found.
509  */
510 static const struct dmi_system_id exar_platforms[] = {
511 	{
512 		.matches = {
513 			DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
514 		},
515 		.driver_data = (void *)&iot2040_platform,
516 	},
517 	{}
518 };
519 
520 static const struct exar8250_platform *exar_get_platform(void)
521 {
522 	const struct dmi_system_id *dmi_match;
523 
524 	dmi_match = dmi_first_match(exar_platforms);
525 	if (dmi_match)
526 		return dmi_match->driver_data;
527 
528 	return &exar8250_default_platform;
529 }
530 
531 static int
532 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
533 		   struct uart_8250_port *port, int idx)
534 {
535 	const struct exar8250_platform *platform = exar_get_platform();
536 	unsigned int offset = idx * 0x400;
537 	unsigned int baud = 7812500;
538 	u8 __iomem *p;
539 	int ret;
540 
541 	port->port.uartclk = baud * 16;
542 	port->port.rs485_config = platform->rs485_config;
543 
544 	/*
545 	 * Setup the UART clock for the devices on expansion slot to
546 	 * half the clock speed of the main chip (which is 125MHz)
547 	 */
548 	if (idx >= 8)
549 		port->port.uartclk /= 2;
550 
551 	ret = default_setup(priv, pcidev, idx, offset, port);
552 	if (ret)
553 		return ret;
554 
555 	p = port->port.membase;
556 
557 	writeb(0x00, p + UART_EXAR_8XMODE);
558 	writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
559 	writeb(128, p + UART_EXAR_TXTRG);
560 	writeb(128, p + UART_EXAR_RXTRG);
561 
562 	if (idx == 0) {
563 		/* Setup Multipurpose Input/Output pins. */
564 		setup_gpio(pcidev, p);
565 
566 		ret = platform->register_gpio(pcidev, port);
567 	}
568 
569 	return ret;
570 }
571 
572 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
573 {
574 	const struct exar8250_platform *platform = exar_get_platform();
575 	struct exar8250 *priv = pci_get_drvdata(pcidev);
576 	struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
577 
578 	platform->unregister_gpio(port);
579 }
580 
581 static inline void exar_misc_clear(struct exar8250 *priv)
582 {
583 	/* Clear all PCI interrupts by reading INT0. No effect on IIR */
584 	readb(priv->virt + UART_EXAR_INT0);
585 
586 	/* Clear INT0 for Expansion Interface slave ports, too */
587 	if (priv->board->num_ports > 8)
588 		readb(priv->virt + 0x2000 + UART_EXAR_INT0);
589 }
590 
591 /*
592  * These Exar UARTs have an extra interrupt indicator that could fire for a
593  * few interrupts that are not presented/cleared through IIR.  One of which is
594  * a wakeup interrupt when coming out of sleep.  These interrupts are only
595  * cleared by reading global INT0 or INT1 registers as interrupts are
596  * associated with channel 0. The INT[3:0] registers _are_ accessible from each
597  * channel's address space, but for the sake of bus efficiency we register a
598  * dedicated handler at the PCI device level to handle them.
599  */
600 static irqreturn_t exar_misc_handler(int irq, void *data)
601 {
602 	exar_misc_clear(data);
603 
604 	return IRQ_HANDLED;
605 }
606 
607 static int
608 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
609 {
610 	unsigned int nr_ports, i, bar = 0, maxnr;
611 	struct exar8250_board *board;
612 	struct uart_8250_port uart;
613 	struct exar8250 *priv;
614 	int rc;
615 
616 	board = (struct exar8250_board *)ent->driver_data;
617 	if (!board)
618 		return -EINVAL;
619 
620 	rc = pcim_enable_device(pcidev);
621 	if (rc)
622 		return rc;
623 
624 	maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
625 
626 	if (pcidev->vendor == PCI_VENDOR_ID_ACCESSIO)
627 		nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1);
628 	else if (board->num_ports)
629 		nr_ports = board->num_ports;
630 	else
631 		nr_ports = pcidev->device & 0x0f;
632 
633 	priv = devm_kzalloc(&pcidev->dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
634 	if (!priv)
635 		return -ENOMEM;
636 
637 	priv->board = board;
638 	priv->virt = pcim_iomap(pcidev, bar, 0);
639 	if (!priv->virt)
640 		return -ENOMEM;
641 
642 	pci_set_master(pcidev);
643 
644 	rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
645 	if (rc < 0)
646 		return rc;
647 
648 	memset(&uart, 0, sizeof(uart));
649 	uart.port.flags = UPF_SHARE_IRQ | UPF_EXAR_EFR | UPF_FIXED_TYPE | UPF_FIXED_PORT;
650 	uart.port.irq = pci_irq_vector(pcidev, 0);
651 	uart.port.dev = &pcidev->dev;
652 
653 	rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
654 			 IRQF_SHARED, "exar_uart", priv);
655 	if (rc)
656 		return rc;
657 
658 	/* Clear interrupts */
659 	exar_misc_clear(priv);
660 
661 	for (i = 0; i < nr_ports && i < maxnr; i++) {
662 		rc = board->setup(priv, pcidev, &uart, i);
663 		if (rc) {
664 			dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
665 			break;
666 		}
667 
668 		dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
669 			uart.port.iobase, uart.port.irq, uart.port.iotype);
670 
671 		priv->line[i] = serial8250_register_8250_port(&uart);
672 		if (priv->line[i] < 0) {
673 			dev_err(&pcidev->dev,
674 				"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
675 				uart.port.iobase, uart.port.irq,
676 				uart.port.iotype, priv->line[i]);
677 			break;
678 		}
679 	}
680 	priv->nr = i;
681 	pci_set_drvdata(pcidev, priv);
682 	return 0;
683 }
684 
685 static void exar_pci_remove(struct pci_dev *pcidev)
686 {
687 	struct exar8250 *priv = pci_get_drvdata(pcidev);
688 	unsigned int i;
689 
690 	for (i = 0; i < priv->nr; i++)
691 		serial8250_unregister_port(priv->line[i]);
692 
693 	if (priv->board->exit)
694 		priv->board->exit(pcidev);
695 }
696 
697 static int __maybe_unused exar_suspend(struct device *dev)
698 {
699 	struct pci_dev *pcidev = to_pci_dev(dev);
700 	struct exar8250 *priv = pci_get_drvdata(pcidev);
701 	unsigned int i;
702 
703 	for (i = 0; i < priv->nr; i++)
704 		if (priv->line[i] >= 0)
705 			serial8250_suspend_port(priv->line[i]);
706 
707 	/* Ensure that every init quirk is properly torn down */
708 	if (priv->board->exit)
709 		priv->board->exit(pcidev);
710 
711 	return 0;
712 }
713 
714 static int __maybe_unused exar_resume(struct device *dev)
715 {
716 	struct exar8250 *priv = dev_get_drvdata(dev);
717 	unsigned int i;
718 
719 	exar_misc_clear(priv);
720 
721 	for (i = 0; i < priv->nr; i++)
722 		if (priv->line[i] >= 0)
723 			serial8250_resume_port(priv->line[i]);
724 
725 	return 0;
726 }
727 
728 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
729 
730 static const struct exar8250_board pbn_fastcom335_2 = {
731 	.num_ports	= 2,
732 	.setup		= pci_fastcom335_setup,
733 };
734 
735 static const struct exar8250_board pbn_fastcom335_4 = {
736 	.num_ports	= 4,
737 	.setup		= pci_fastcom335_setup,
738 };
739 
740 static const struct exar8250_board pbn_fastcom335_8 = {
741 	.num_ports	= 8,
742 	.setup		= pci_fastcom335_setup,
743 };
744 
745 static const struct exar8250_board pbn_connect = {
746 	.setup		= pci_connect_tech_setup,
747 };
748 
749 static const struct exar8250_board pbn_exar_ibm_saturn = {
750 	.num_ports	= 1,
751 	.setup		= pci_xr17c154_setup,
752 };
753 
754 static const struct exar8250_board pbn_exar_XR17C15x = {
755 	.setup		= pci_xr17c154_setup,
756 };
757 
758 static const struct exar8250_board pbn_exar_XR17V35x = {
759 	.setup		= pci_xr17v35x_setup,
760 	.exit		= pci_xr17v35x_exit,
761 };
762 
763 static const struct exar8250_board pbn_fastcom35x_2 = {
764 	.num_ports	= 2,
765 	.setup		= pci_xr17v35x_setup,
766 	.exit		= pci_xr17v35x_exit,
767 };
768 
769 static const struct exar8250_board pbn_fastcom35x_4 = {
770 	.num_ports	= 4,
771 	.setup		= pci_xr17v35x_setup,
772 	.exit		= pci_xr17v35x_exit,
773 };
774 
775 static const struct exar8250_board pbn_fastcom35x_8 = {
776 	.num_ports	= 8,
777 	.setup		= pci_xr17v35x_setup,
778 	.exit		= pci_xr17v35x_exit,
779 };
780 
781 static const struct exar8250_board pbn_exar_XR17V4358 = {
782 	.num_ports	= 12,
783 	.setup		= pci_xr17v35x_setup,
784 	.exit		= pci_xr17v35x_exit,
785 };
786 
787 static const struct exar8250_board pbn_exar_XR17V8358 = {
788 	.num_ports	= 16,
789 	.setup		= pci_xr17v35x_setup,
790 	.exit		= pci_xr17v35x_exit,
791 };
792 
793 #define CONNECT_DEVICE(devid, sdevid, bd) {				\
794 	PCI_DEVICE_SUB(							\
795 		PCI_VENDOR_ID_EXAR,					\
796 		PCI_DEVICE_ID_EXAR_##devid,				\
797 		PCI_SUBVENDOR_ID_CONNECT_TECH,				\
798 		PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0,	\
799 		(kernel_ulong_t)&bd					\
800 	}
801 
802 #define EXAR_DEVICE(vend, devid, bd) { PCI_DEVICE_DATA(vend, devid, &bd) }
803 
804 #define IBM_DEVICE(devid, sdevid, bd) {			\
805 	PCI_DEVICE_SUB(					\
806 		PCI_VENDOR_ID_EXAR,			\
807 		PCI_DEVICE_ID_EXAR_##devid,		\
808 		PCI_VENDOR_ID_IBM,			\
809 		PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0,	\
810 		(kernel_ulong_t)&bd			\
811 	}
812 
813 static const struct pci_device_id exar_pci_tbl[] = {
814 	EXAR_DEVICE(ACCESSIO, COM_2S, pbn_exar_XR17C15x),
815 	EXAR_DEVICE(ACCESSIO, COM_4S, pbn_exar_XR17C15x),
816 	EXAR_DEVICE(ACCESSIO, COM_8S, pbn_exar_XR17C15x),
817 	EXAR_DEVICE(ACCESSIO, COM232_8, pbn_exar_XR17C15x),
818 	EXAR_DEVICE(ACCESSIO, COM_2SM, pbn_exar_XR17C15x),
819 	EXAR_DEVICE(ACCESSIO, COM_4SM, pbn_exar_XR17C15x),
820 	EXAR_DEVICE(ACCESSIO, COM_8SM, pbn_exar_XR17C15x),
821 
822 	CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
823 	CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
824 	CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
825 	CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
826 	CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
827 	CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
828 	CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
829 	CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
830 	CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
831 	CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
832 	CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
833 	CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
834 
835 	IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
836 
837 	/* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
838 	EXAR_DEVICE(EXAR, XR17C152, pbn_exar_XR17C15x),
839 	EXAR_DEVICE(EXAR, XR17C154, pbn_exar_XR17C15x),
840 	EXAR_DEVICE(EXAR, XR17C158, pbn_exar_XR17C15x),
841 
842 	/* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
843 	EXAR_DEVICE(EXAR, XR17V352, pbn_exar_XR17V35x),
844 	EXAR_DEVICE(EXAR, XR17V354, pbn_exar_XR17V35x),
845 	EXAR_DEVICE(EXAR, XR17V358, pbn_exar_XR17V35x),
846 	EXAR_DEVICE(EXAR, XR17V4358, pbn_exar_XR17V4358),
847 	EXAR_DEVICE(EXAR, XR17V8358, pbn_exar_XR17V8358),
848 	EXAR_DEVICE(COMMTECH, 4222PCIE, pbn_fastcom35x_2),
849 	EXAR_DEVICE(COMMTECH, 4224PCIE, pbn_fastcom35x_4),
850 	EXAR_DEVICE(COMMTECH, 4228PCIE, pbn_fastcom35x_8),
851 
852 	EXAR_DEVICE(COMMTECH, 4222PCI335, pbn_fastcom335_2),
853 	EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4),
854 	EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4),
855 	EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8),
856 	{ 0, }
857 };
858 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
859 
860 static struct pci_driver exar_pci_driver = {
861 	.name		= "exar_serial",
862 	.probe		= exar_pci_probe,
863 	.remove		= exar_pci_remove,
864 	.driver         = {
865 		.pm     = &exar_pci_pm,
866 	},
867 	.id_table	= exar_pci_tbl,
868 };
869 module_pci_driver(exar_pci_driver);
870 
871 MODULE_LICENSE("GPL");
872 MODULE_DESCRIPTION("Exar Serial Driver");
873 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
874