1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Synopsys DesignWare 8250 library header file. */ 3 4 #include <linux/io.h> 5 #include <linux/notifier.h> 6 #include <linux/types.h> 7 #include <linux/workqueue.h> 8 9 #include "8250.h" 10 11 struct clk; 12 struct reset_control; 13 14 struct dw8250_port_data { 15 /* Port properties */ 16 int line; 17 18 /* DMA operations */ 19 struct uart_8250_dma dma; 20 21 /* Hardware configuration */ 22 u32 cpr_value; 23 u8 dlf_size; 24 25 /* RS485 variables */ 26 bool hw_rs485_support; 27 }; 28 29 struct dw8250_platform_data { 30 u8 usr_reg; 31 u32 cpr_value; 32 unsigned int quirks; 33 }; 34 35 struct dw8250_data { 36 struct dw8250_port_data data; 37 const struct dw8250_platform_data *pdata; 38 39 int msr_mask_on; 40 int msr_mask_off; 41 struct clk *clk; 42 struct clk *pclk; 43 struct notifier_block clk_notifier; 44 struct work_struct clk_work; 45 struct reset_control *rst; 46 47 unsigned int skip_autocfg:1; 48 unsigned int uart_16550_compatible:1; 49 }; 50 51 void dw8250_do_set_termios(struct uart_port *p, struct ktermios *termios, const struct ktermios *old); 52 void dw8250_setup_port(struct uart_port *p); 53 54 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 55 { 56 return container_of(data, struct dw8250_data, data); 57 } 58 59 static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) 60 { 61 if (p->iotype == UPIO_MEM32BE) 62 return ioread32be(p->membase + offset); 63 return readl(p->membase + offset); 64 } 65 66 static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) 67 { 68 if (p->iotype == UPIO_MEM32BE) 69 iowrite32be(reg, p->membase + offset); 70 else 71 writel(reg, p->membase + offset); 72 } 73